Repository: supersynthesis/eurorack Branch: main Commit: 95bfdeef4712 Files: 1351 Total size: 38.0 MB Directory structure: gitextract_dvgqr6s_/ ├── .gitignore ├── Production Modules/ │ ├── 2OPFM/ │ │ ├── 2OPFM_REV5_PANEL.ai │ │ ├── diptrace/ │ │ │ ├── 2OPFM_2023_NB_PANEL.dip │ │ │ ├── 2OPFM_REV5.dch │ │ │ ├── 2OPFM_REV5.dip │ │ │ └── _archive/ │ │ │ ├── 2OPFM_2022_PANEL.dip │ │ │ ├── 2OPFM_2022_PANEL.dxf │ │ │ ├── 2OPFM_REV3.dch │ │ │ ├── 2OPFM_REV3.dip │ │ │ ├── 2OPFM_REV4.dch │ │ │ └── 2OPFM_REV4.dip │ │ ├── firmware/ │ │ │ ├── 2OPFM_G431/ │ │ │ │ ├── .cproject │ │ │ │ ├── .mxproject │ │ │ │ ├── .project │ │ │ │ ├── .settings/ │ │ │ │ │ ├── language.settings.xml │ │ │ │ │ ├── org.eclipse.cdt.core.prefs │ │ │ │ │ └── stm32cubeide.project.prefs │ │ │ │ ├── 2OPFM_G431.ioc │ │ │ │ ├── 2OPFM_G431.launch │ │ │ │ ├── App/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── 2op_main.h │ │ │ │ │ │ ├── big_sine_wave.h │ │ │ │ │ │ ├── dynamic_smooth.h │ │ │ │ │ │ ├── global_variables.h │ │ │ │ │ │ └── loop.h │ │ │ │ │ └── Src/ │ │ │ │ │ ├── 2op_main.c │ │ │ │ │ ├── dynamic_smooth.c │ │ │ │ │ └── loop.c │ │ │ │ ├── Core/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── adc.h │ │ │ │ │ │ ├── dac.h │ │ │ │ │ │ ├── dma.h │ │ │ │ │ │ ├── gpio.h │ │ │ │ │ │ ├── main.h │ │ │ │ │ │ ├── stm32g4xx_hal_conf.h │ │ │ │ │ │ ├── stm32g4xx_it.h │ │ │ │ │ │ └── tim.h │ │ │ │ │ ├── Src/ │ │ │ │ │ │ ├── adc.c │ │ │ │ │ │ ├── dac.c │ │ │ │ │ │ ├── dma.c │ │ │ │ │ │ ├── gpio.c │ │ │ │ │ │ ├── main.c │ │ │ │ │ │ ├── stm32g4xx_hal_msp.c │ │ │ │ │ │ ├── stm32g4xx_it.c │ │ │ │ │ │ ├── syscalls.c │ │ │ │ │ │ ├── sysmem.c │ │ │ │ │ │ ├── system_stm32g4xx.c │ │ │ │ │ │ └── tim.c │ │ │ │ │ └── Startup/ │ │ │ │ │ └── startup_stm32g431kbux.s │ │ │ │ ├── Debug/ │ │ │ │ │ ├── 2OPFM_G431.elf │ │ │ │ │ ├── 2OPFM_G431.list │ │ │ │ │ ├── App/ │ │ │ │ │ │ └── Src/ │ │ │ │ │ │ ├── 2op_main.d │ │ │ │ │ │ ├── 2op_main.o │ │ │ │ │ │ ├── 2op_main.su │ │ │ │ │ │ ├── dynamic_smooth.d │ │ │ │ │ │ ├── dynamic_smooth.o │ │ │ │ │ │ ├── dynamic_smooth.su │ │ │ │ │ │ ├── float_expo_table.su │ │ │ │ │ │ ├── loop.d │ │ │ │ │ │ ├── loop.o │ │ │ │ │ │ ├── loop.su │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── Core/ │ │ │ │ │ │ ├── Src/ │ │ │ │ │ │ │ ├── adc.d │ │ │ │ │ │ │ ├── adc.o │ │ │ │ │ │ │ ├── adc.su │ │ │ │ │ │ │ ├── dac.d │ │ │ │ │ │ │ ├── dac.o │ │ │ │ │ │ │ ├── dac.su │ │ │ │ │ │ │ ├── dma.d │ │ │ │ │ │ │ ├── dma.o │ │ │ │ │ │ │ ├── dma.su │ │ │ │ │ │ │ ├── gpio.d │ │ │ │ │ │ │ ├── gpio.o │ │ │ │ │ │ │ ├── gpio.su │ │ │ │ │ │ │ ├── main.d │ │ │ │ │ │ │ ├── main.o │ │ │ │ │ │ │ ├── main.su │ │ │ │ │ │ │ ├── stm32g4xx_hal_msp.d │ │ │ │ │ │ │ ├── stm32g4xx_hal_msp.o │ │ │ │ │ │ │ ├── stm32g4xx_hal_msp.su │ │ │ │ │ │ │ ├── stm32g4xx_it.d │ │ │ │ │ │ │ ├── stm32g4xx_it.o │ │ │ │ │ │ │ ├── stm32g4xx_it.su │ │ │ │ │ │ │ ├── subdir.mk │ │ │ │ │ │ │ ├── syscalls.d │ │ │ │ │ │ │ ├── syscalls.o │ │ │ │ │ │ │ ├── syscalls.su │ │ │ │ │ │ │ ├── sysmem.d │ │ │ │ │ │ │ ├── sysmem.o │ │ │ │ │ │ │ ├── sysmem.su │ │ │ │ │ │ │ ├── system_stm32g4xx.d │ │ │ │ │ │ │ ├── system_stm32g4xx.o │ │ │ │ │ │ │ ├── system_stm32g4xx.su │ │ │ │ │ │ │ ├── tim.d │ │ │ │ │ │ │ ├── tim.o │ │ │ │ │ │ │ └── tim.su │ │ │ │ │ │ └── Startup/ │ │ │ │ │ │ ├── startup_stm32g431kbux.d │ │ │ │ │ │ ├── startup_stm32g431kbux.o │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── Drivers/ │ │ │ │ │ │ └── STM32G4xx_HAL_Driver/ │ │ │ │ │ │ └── Src/ │ │ │ │ │ │ ├── stm32g4xx_hal.d │ │ │ │ │ │ ├── stm32g4xx_hal.o │ │ │ │ │ │ ├── stm32g4xx_hal.su │ │ │ │ │ │ ├── stm32g4xx_hal_adc.d │ │ │ │ │ │ ├── stm32g4xx_hal_adc.o │ │ │ │ │ │ ├── stm32g4xx_hal_adc.su │ │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.d │ │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.o │ │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.su │ │ │ │ │ │ ├── stm32g4xx_hal_cortex.d │ │ │ │ │ │ ├── stm32g4xx_hal_cortex.o │ │ │ │ │ │ ├── stm32g4xx_hal_cortex.su │ │ │ │ │ │ ├── stm32g4xx_hal_dac.d │ │ │ │ │ │ ├── stm32g4xx_hal_dac.o │ │ │ │ │ │ ├── stm32g4xx_hal_dac.su │ │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.d │ │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.o │ │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.su │ │ │ │ │ │ ├── stm32g4xx_hal_dma.d │ │ │ │ │ │ ├── stm32g4xx_hal_dma.o │ │ │ │ │ │ ├── stm32g4xx_hal_dma.su │ │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.d │ │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.o │ │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.su │ │ │ │ │ │ ├── stm32g4xx_hal_exti.d │ │ │ │ │ │ ├── stm32g4xx_hal_exti.o │ │ │ │ │ │ ├── stm32g4xx_hal_exti.su │ │ │ │ │ │ ├── stm32g4xx_hal_flash.d │ │ │ │ │ │ ├── stm32g4xx_hal_flash.o │ │ │ │ │ │ ├── stm32g4xx_hal_flash.su │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.d │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.o │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.su │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.d │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.o │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.su │ │ │ │ │ │ ├── stm32g4xx_hal_gpio.d │ │ │ │ │ │ ├── stm32g4xx_hal_gpio.o │ │ │ │ │ │ ├── stm32g4xx_hal_gpio.su │ │ │ │ │ │ ├── stm32g4xx_hal_pwr.d │ │ │ │ │ │ ├── stm32g4xx_hal_pwr.o │ │ │ │ │ │ ├── stm32g4xx_hal_pwr.su │ │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.d │ │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.o │ │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.su │ │ │ │ │ │ ├── stm32g4xx_hal_rcc.d │ │ │ │ │ │ ├── stm32g4xx_hal_rcc.o │ │ │ │ │ │ ├── stm32g4xx_hal_rcc.su │ │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.d │ │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.o │ │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.su │ │ │ │ │ │ ├── stm32g4xx_hal_tim.d │ │ │ │ │ │ ├── stm32g4xx_hal_tim.o │ │ │ │ │ │ ├── stm32g4xx_hal_tim.su │ │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.d │ │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.o │ │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.su │ │ │ │ │ │ ├── stm32g4xx_ll_adc.d │ │ │ │ │ │ ├── stm32g4xx_ll_adc.o │ │ │ │ │ │ ├── stm32g4xx_ll_adc.su │ │ │ │ │ │ ├── stm32g4xx_ll_dac.d │ │ │ │ │ │ ├── stm32g4xx_ll_dac.su │ │ │ │ │ │ ├── stm32g4xx_ll_dma.d │ │ │ │ │ │ ├── stm32g4xx_ll_dma.su │ │ │ │ │ │ ├── stm32g4xx_ll_exti.d │ │ │ │ │ │ ├── stm32g4xx_ll_exti.su │ │ │ │ │ │ ├── stm32g4xx_ll_gpio.d │ │ │ │ │ │ ├── stm32g4xx_ll_gpio.su │ │ │ │ │ │ ├── stm32g4xx_ll_utils.d │ │ │ │ │ │ ├── stm32g4xx_ll_utils.su │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── makefile │ │ │ │ │ ├── objects.list │ │ │ │ │ ├── objects.mk │ │ │ │ │ └── sources.mk │ │ │ │ ├── Drivers/ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ ├── Device/ │ │ │ │ │ │ │ └── ST/ │ │ │ │ │ │ │ └── STM32G4xx/ │ │ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ │ │ ├── stm32g431xx.h │ │ │ │ │ │ │ │ ├── stm32g4xx.h │ │ │ │ │ │ │ │ └── system_stm32g4xx.h │ │ │ │ │ │ │ └── LICENSE.txt │ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ │ │ ├── cmsis_armclang.h │ │ │ │ │ │ │ ├── cmsis_armclang_ltm.h │ │ │ │ │ │ │ ├── cmsis_compiler.h │ │ │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ │ │ ├── cmsis_iccarm.h │ │ │ │ │ │ │ ├── cmsis_version.h │ │ │ │ │ │ │ ├── core_armv81mml.h │ │ │ │ │ │ │ ├── core_armv8mbl.h │ │ │ │ │ │ │ ├── core_armv8mml.h │ │ │ │ │ │ │ ├── core_cm0.h │ │ │ │ │ │ │ ├── core_cm0plus.h │ │ │ │ │ │ │ ├── core_cm1.h │ │ │ │ │ │ │ ├── core_cm23.h │ │ │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ │ │ ├── core_cm33.h │ │ │ │ │ │ │ ├── core_cm35p.h │ │ │ │ │ │ │ ├── core_cm4.h │ │ │ │ │ │ │ ├── core_cm7.h │ │ │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ │ │ ├── core_sc300.h │ │ │ │ │ │ │ ├── mpu_armv7.h │ │ │ │ │ │ │ ├── mpu_armv8.h │ │ │ │ │ │ │ └── tz_context.h │ │ │ │ │ │ └── LICENSE.txt │ │ │ │ │ └── STM32G4xx_HAL_Driver/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── Legacy/ │ │ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ │ │ ├── stm32g4xx_hal.h │ │ │ │ │ │ ├── stm32g4xx_hal_adc.h │ │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.h │ │ │ │ │ │ ├── stm32g4xx_hal_cortex.h │ │ │ │ │ │ ├── stm32g4xx_hal_dac.h │ │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.h │ │ │ │ │ │ ├── stm32g4xx_hal_def.h │ │ │ │ │ │ ├── stm32g4xx_hal_dma.h │ │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.h │ │ │ │ │ │ ├── stm32g4xx_hal_exti.h │ │ │ │ │ │ ├── stm32g4xx_hal_flash.h │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.h │ │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.h │ │ │ │ │ │ ├── stm32g4xx_hal_gpio.h │ │ │ │ │ │ ├── stm32g4xx_hal_gpio_ex.h │ │ │ │ │ │ ├── stm32g4xx_hal_pwr.h │ │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.h │ │ │ │ │ │ ├── stm32g4xx_hal_rcc.h │ │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.h │ │ │ │ │ │ ├── stm32g4xx_hal_tim.h │ │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.h │ │ │ │ │ │ └── stm32g4xx_ll_adc.h │ │ │ │ │ ├── LICENSE.txt │ │ │ │ │ └── Src/ │ │ │ │ │ ├── stm32g4xx_hal.c │ │ │ │ │ ├── stm32g4xx_hal_adc.c │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.c │ │ │ │ │ ├── stm32g4xx_hal_cortex.c │ │ │ │ │ ├── stm32g4xx_hal_dac.c │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.c │ │ │ │ │ ├── stm32g4xx_hal_dma.c │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.c │ │ │ │ │ ├── stm32g4xx_hal_exti.c │ │ │ │ │ ├── stm32g4xx_hal_flash.c │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.c │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.c │ │ │ │ │ ├── stm32g4xx_hal_gpio.c │ │ │ │ │ ├── stm32g4xx_hal_pwr.c │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.c │ │ │ │ │ ├── stm32g4xx_hal_rcc.c │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.c │ │ │ │ │ ├── stm32g4xx_hal_tim.c │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.c │ │ │ │ │ └── stm32g4xx_ll_adc.c │ │ │ │ └── STM32G431KBUX_FLASH.ld │ │ │ ├── 2OPFM_REV5_2024.elf │ │ │ ├── README.md │ │ │ └── _archive/ │ │ │ ├── 2OPFM_2020/ │ │ │ │ ├── .cproject │ │ │ │ ├── .mxproject │ │ │ │ ├── .project │ │ │ │ ├── .settings/ │ │ │ │ │ ├── language.settings.xml │ │ │ │ │ └── stm32cubeide.project.prefs │ │ │ │ ├── 2OPFM_2020 Debug.launch │ │ │ │ ├── 2OPFM_2020.ioc │ │ │ │ ├── Core/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── 2op_main.h │ │ │ │ │ │ ├── big_expo.h │ │ │ │ │ │ ├── big_sine_wave.h │ │ │ │ │ │ ├── dac.h │ │ │ │ │ │ ├── dynamic_smooth.h │ │ │ │ │ │ ├── global_variables.h │ │ │ │ │ │ ├── loop.h │ │ │ │ │ │ ├── main.h │ │ │ │ │ │ ├── noise.h │ │ │ │ │ │ ├── pin_map.h │ │ │ │ │ │ ├── stm32_assert.h │ │ │ │ │ │ ├── stm32f3xx_hal_conf.h │ │ │ │ │ │ └── stm32f3xx_it.h │ │ │ │ │ ├── Src/ │ │ │ │ │ │ ├── 2op_main.c │ │ │ │ │ │ ├── dac.c │ │ │ │ │ │ ├── dynamic_smooth.c │ │ │ │ │ │ ├── loop.c │ │ │ │ │ │ ├── main.c │ │ │ │ │ │ ├── noise.c │ │ │ │ │ │ ├── stm32f3xx_hal_msp.c │ │ │ │ │ │ ├── stm32f3xx_it.c │ │ │ │ │ │ ├── syscalls.c │ │ │ │ │ │ ├── sysmem.c │ │ │ │ │ │ └── system_stm32f3xx.c │ │ │ │ │ └── Startup/ │ │ │ │ │ └── startup_stm32f334k8tx.s │ │ │ │ ├── Debug/ │ │ │ │ │ ├── 2OPFM_2020.elf │ │ │ │ │ ├── 2OPFM_2020.hex │ │ │ │ │ ├── 2OPFM_2020.list │ │ │ │ │ ├── Core/ │ │ │ │ │ │ ├── Src/ │ │ │ │ │ │ │ ├── 2op_main.d │ │ │ │ │ │ │ ├── 2op_main.o │ │ │ │ │ │ │ ├── 2op_main.su │ │ │ │ │ │ │ ├── dac.d │ │ │ │ │ │ │ ├── dac.o │ │ │ │ │ │ │ ├── dac.su │ │ │ │ │ │ │ ├── dynamic_smooth.d │ │ │ │ │ │ │ ├── dynamic_smooth.o │ │ │ │ │ │ │ ├── dynamic_smooth.su │ │ │ │ │ │ │ ├── loop.d │ │ │ │ │ │ │ ├── loop.o │ │ │ │ │ │ │ ├── loop.su │ │ │ │ │ │ │ ├── main.d │ │ │ │ │ │ │ ├── main.o │ │ │ │ │ │ │ ├── main.su │ │ │ │ │ │ │ ├── noise.d │ │ │ │ │ │ │ ├── noise.o │ │ │ │ │ │ │ ├── noise.su │ │ │ │ │ │ │ ├── soft_adsr.su │ │ │ │ │ │ │ ├── stm32f3xx_hal_msp.d │ │ │ │ │ │ │ ├── stm32f3xx_hal_msp.o │ │ │ │ │ │ │ ├── stm32f3xx_hal_msp.su │ │ │ │ │ │ │ ├── stm32f3xx_it.d │ │ │ │ │ │ │ ├── stm32f3xx_it.o │ │ │ │ │ │ │ ├── stm32f3xx_it.su │ │ │ │ │ │ │ ├── subdir.mk │ │ │ │ │ │ │ ├── syscalls.d │ │ │ │ │ │ │ ├── syscalls.o │ │ │ │ │ │ │ ├── syscalls.su │ │ │ │ │ │ │ ├── sysmem.d │ │ │ │ │ │ │ ├── sysmem.o │ │ │ │ │ │ │ ├── sysmem.su │ │ │ │ │ │ │ ├── system_stm32f3xx.d │ │ │ │ │ │ │ ├── system_stm32f3xx.o │ │ │ │ │ │ │ └── system_stm32f3xx.su │ │ │ │ │ │ └── Startup/ │ │ │ │ │ │ ├── startup_stm32f334k8tx.d │ │ │ │ │ │ ├── startup_stm32f334k8tx.o │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── Drivers/ │ │ │ │ │ │ └── STM32F3xx_HAL_Driver/ │ │ │ │ │ │ └── Src/ │ │ │ │ │ │ ├── stm32f3xx_hal.d │ │ │ │ │ │ ├── stm32f3xx_hal.o │ │ │ │ │ │ ├── stm32f3xx_hal.su │ │ │ │ │ │ ├── stm32f3xx_hal_adc.d │ │ │ │ │ │ ├── stm32f3xx_hal_adc.o │ │ │ │ │ │ ├── stm32f3xx_hal_adc.su │ │ │ │ │ │ ├── stm32f3xx_hal_adc_ex.d │ │ │ │ │ │ ├── stm32f3xx_hal_adc_ex.o │ │ │ │ │ │ ├── stm32f3xx_hal_adc_ex.su │ │ │ │ │ │ ├── stm32f3xx_hal_cortex.d │ │ │ │ │ │ ├── stm32f3xx_hal_cortex.o │ │ │ │ │ │ ├── stm32f3xx_hal_cortex.su │ │ │ │ │ │ ├── stm32f3xx_hal_dma.d │ │ │ │ │ │ ├── stm32f3xx_hal_dma.o │ │ │ │ │ │ ├── stm32f3xx_hal_dma.su │ │ │ │ │ │ ├── stm32f3xx_hal_exti.d │ │ │ │ │ │ ├── stm32f3xx_hal_exti.o │ │ │ │ │ │ ├── stm32f3xx_hal_exti.su │ │ │ │ │ │ ├── stm32f3xx_hal_flash.d │ │ │ │ │ │ ├── stm32f3xx_hal_flash.o │ │ │ │ │ │ ├── stm32f3xx_hal_flash.su │ │ │ │ │ │ ├── stm32f3xx_hal_flash_ex.d │ │ │ │ │ │ ├── stm32f3xx_hal_flash_ex.o │ │ │ │ │ │ ├── stm32f3xx_hal_flash_ex.su │ │ │ │ │ │ ├── stm32f3xx_hal_gpio.d │ │ │ │ │ │ ├── stm32f3xx_hal_gpio.o │ │ │ │ │ │ ├── stm32f3xx_hal_gpio.su │ │ │ │ │ │ ├── stm32f3xx_hal_i2c.d │ │ │ │ │ │ ├── stm32f3xx_hal_i2c.o │ │ │ │ │ │ ├── stm32f3xx_hal_i2c.su │ │ │ │ │ │ ├── stm32f3xx_hal_i2c_ex.d │ │ │ │ │ │ ├── stm32f3xx_hal_i2c_ex.o │ │ │ │ │ │ ├── stm32f3xx_hal_i2c_ex.su │ │ │ │ │ │ ├── stm32f3xx_hal_pwr.d │ │ │ │ │ │ ├── stm32f3xx_hal_pwr.o │ │ │ │ │ │ ├── stm32f3xx_hal_pwr.su │ │ │ │ │ │ ├── stm32f3xx_hal_pwr_ex.d │ │ │ │ │ │ ├── stm32f3xx_hal_pwr_ex.o │ │ │ │ │ │ ├── stm32f3xx_hal_pwr_ex.su │ │ │ │ │ │ ├── stm32f3xx_hal_rcc.d │ │ │ │ │ │ ├── stm32f3xx_hal_rcc.o │ │ │ │ │ │ ├── stm32f3xx_hal_rcc.su │ │ │ │ │ │ ├── stm32f3xx_hal_rcc_ex.d │ │ │ │ │ │ ├── stm32f3xx_hal_rcc_ex.o │ │ │ │ │ │ ├── stm32f3xx_hal_rcc_ex.su │ │ │ │ │ │ ├── stm32f3xx_hal_tim.d │ │ │ │ │ │ ├── stm32f3xx_hal_tim.o │ │ │ │ │ │ ├── stm32f3xx_hal_tim.su │ │ │ │ │ │ ├── stm32f3xx_hal_tim_ex.d │ │ │ │ │ │ ├── stm32f3xx_hal_tim_ex.o │ │ │ │ │ │ ├── stm32f3xx_hal_tim_ex.su │ │ │ │ │ │ ├── stm32f3xx_ll_dac.d │ │ │ │ │ │ ├── stm32f3xx_ll_dac.o │ │ │ │ │ │ ├── stm32f3xx_ll_dac.su │ │ │ │ │ │ ├── stm32f3xx_ll_dma.d │ │ │ │ │ │ ├── stm32f3xx_ll_dma.o │ │ │ │ │ │ ├── stm32f3xx_ll_dma.su │ │ │ │ │ │ ├── stm32f3xx_ll_exti.d │ │ │ │ │ │ ├── stm32f3xx_ll_exti.o │ │ │ │ │ │ ├── stm32f3xx_ll_exti.su │ │ │ │ │ │ ├── stm32f3xx_ll_gpio.d │ │ │ │ │ │ ├── stm32f3xx_ll_gpio.o │ │ │ │ │ │ ├── stm32f3xx_ll_gpio.su │ │ │ │ │ │ ├── stm32f3xx_ll_rcc.d │ │ │ │ │ │ ├── stm32f3xx_ll_rcc.o │ │ │ │ │ │ ├── stm32f3xx_ll_rcc.su │ │ │ │ │ │ ├── stm32f3xx_ll_tim.d │ │ │ │ │ │ ├── stm32f3xx_ll_tim.o │ │ │ │ │ │ ├── stm32f3xx_ll_tim.su │ │ │ │ │ │ ├── stm32f3xx_ll_utils.d │ │ │ │ │ │ ├── stm32f3xx_ll_utils.o │ │ │ │ │ │ ├── stm32f3xx_ll_utils.su │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── makefile │ │ │ │ │ ├── objects.list │ │ │ │ │ ├── objects.mk │ │ │ │ │ └── sources.mk │ │ │ │ ├── Drivers/ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ ├── Device/ │ │ │ │ │ │ │ └── ST/ │ │ │ │ │ │ │ └── STM32F3xx/ │ │ │ │ │ │ │ └── Include/ │ │ │ │ │ │ │ ├── stm32f334x8.h │ │ │ │ │ │ │ ├── stm32f3xx.h │ │ │ │ │ │ │ └── system_stm32f3xx.h │ │ │ │ │ │ └── Include/ │ │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ │ ├── cmsis_armclang.h │ │ │ │ │ │ ├── cmsis_compiler.h │ │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ │ ├── cmsis_iccarm.h │ │ │ │ │ │ ├── cmsis_version.h │ │ │ │ │ │ ├── core_armv8mbl.h │ │ │ │ │ │ ├── core_armv8mml.h │ │ │ │ │ │ ├── core_cm0.h │ │ │ │ │ │ ├── core_cm0plus.h │ │ │ │ │ │ ├── core_cm1.h │ │ │ │ │ │ ├── core_cm23.h │ │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ │ ├── core_cm33.h │ │ │ │ │ │ ├── core_cm4.h │ │ │ │ │ │ ├── core_cm7.h │ │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ │ ├── core_sc300.h │ │ │ │ │ │ ├── mpu_armv7.h │ │ │ │ │ │ ├── mpu_armv8.h │ │ │ │ │ │ └── tz_context.h │ │ │ │ │ └── STM32F3xx_HAL_Driver/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── Legacy/ │ │ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ │ │ ├── stm32f3xx_hal.h │ │ │ │ │ │ ├── stm32f3xx_hal_adc.h │ │ │ │ │ │ ├── stm32f3xx_hal_adc_ex.h │ │ │ │ │ │ ├── stm32f3xx_hal_cortex.h │ │ │ │ │ │ ├── stm32f3xx_hal_def.h │ │ │ │ │ │ ├── stm32f3xx_hal_dma.h │ │ │ │ │ │ ├── stm32f3xx_hal_dma_ex.h │ │ │ │ │ │ ├── stm32f3xx_hal_exti.h │ │ │ │ │ │ ├── stm32f3xx_hal_flash.h │ │ │ │ │ │ ├── stm32f3xx_hal_flash_ex.h │ │ │ │ │ │ ├── stm32f3xx_hal_gpio.h │ │ │ │ │ │ ├── stm32f3xx_hal_gpio_ex.h │ │ │ │ │ │ ├── stm32f3xx_hal_i2c.h │ │ │ │ │ │ ├── stm32f3xx_hal_i2c_ex.h │ │ │ │ │ │ ├── stm32f3xx_hal_pwr.h │ │ │ │ │ │ ├── stm32f3xx_hal_pwr_ex.h │ │ │ │ │ │ ├── stm32f3xx_hal_rcc.h │ │ │ │ │ │ ├── stm32f3xx_hal_rcc_ex.h │ │ │ │ │ │ ├── stm32f3xx_hal_tim.h │ │ │ │ │ │ ├── stm32f3xx_hal_tim_ex.h │ │ │ │ │ │ ├── stm32f3xx_ll_bus.h │ │ │ │ │ │ ├── stm32f3xx_ll_cortex.h │ │ │ │ │ │ ├── stm32f3xx_ll_dac.h │ │ │ │ │ │ ├── stm32f3xx_ll_dma.h │ │ │ │ │ │ ├── stm32f3xx_ll_exti.h │ │ │ │ │ │ ├── stm32f3xx_ll_gpio.h │ │ │ │ │ │ ├── stm32f3xx_ll_pwr.h │ │ │ │ │ │ ├── stm32f3xx_ll_rcc.h │ │ │ │ │ │ ├── stm32f3xx_ll_system.h │ │ │ │ │ │ ├── stm32f3xx_ll_tim.h │ │ │ │ │ │ └── stm32f3xx_ll_utils.h │ │ │ │ │ └── Src/ │ │ │ │ │ ├── stm32f3xx_hal.c │ │ │ │ │ ├── stm32f3xx_hal_adc.c │ │ │ │ │ ├── stm32f3xx_hal_adc_ex.c │ │ │ │ │ ├── stm32f3xx_hal_cortex.c │ │ │ │ │ ├── stm32f3xx_hal_dma.c │ │ │ │ │ ├── stm32f3xx_hal_exti.c │ │ │ │ │ ├── stm32f3xx_hal_flash.c │ │ │ │ │ ├── stm32f3xx_hal_flash_ex.c │ │ │ │ │ ├── stm32f3xx_hal_gpio.c │ │ │ │ │ ├── stm32f3xx_hal_i2c.c │ │ │ │ │ ├── stm32f3xx_hal_i2c_ex.c │ │ │ │ │ ├── stm32f3xx_hal_pwr.c │ │ │ │ │ ├── stm32f3xx_hal_pwr_ex.c │ │ │ │ │ ├── stm32f3xx_hal_rcc.c │ │ │ │ │ ├── stm32f3xx_hal_rcc_ex.c │ │ │ │ │ ├── stm32f3xx_hal_tim.c │ │ │ │ │ ├── stm32f3xx_hal_tim_ex.c │ │ │ │ │ ├── stm32f3xx_ll_dac.c │ │ │ │ │ ├── stm32f3xx_ll_dma.c │ │ │ │ │ ├── stm32f3xx_ll_exti.c │ │ │ │ │ ├── stm32f3xx_ll_gpio.c │ │ │ │ │ ├── stm32f3xx_ll_rcc.c │ │ │ │ │ ├── stm32f3xx_ll_tim.c │ │ │ │ │ └── stm32f3xx_ll_utils.c │ │ │ │ └── STM32F334K8TX_FLASH.ld │ │ │ └── 2OPFM_REV4_2020.elf │ │ └── jlcpcb/ │ │ ├── 2OPFM_REV5_JLCBOM.csv │ │ ├── 2OPFM_REV5_JLCXY.csv │ │ └── _archive/ │ │ ├── 2OPFM_2022_NOTES.txt │ │ ├── 2OPFM_REV3_JLCBOM.csv │ │ ├── 2OPFM_REV3_JLCXY.csv │ │ ├── 2OPFM_REV4_JLCBOM.csv │ │ ├── 2OPFM_REV4_JLCXY.csv │ │ └── 2OPFM_REV5_JLCBOM.csv │ ├── CHORUS/ │ │ ├── diptrace/ │ │ │ ├── chorus_REV1.dch │ │ │ ├── chorus_REV1.dip │ │ │ └── chorus_REV1_NB_PANEL.dip │ │ ├── firmware/ │ │ │ ├── CHORUS_2024.elf │ │ │ └── chorus_G431/ │ │ │ ├── .cproject │ │ │ ├── .mxproject │ │ │ ├── .project │ │ │ ├── .settings/ │ │ │ │ ├── com.st.stm32cube.ide.mcu.sfrview.prefs │ │ │ │ ├── language.settings.xml │ │ │ │ └── stm32cubeide.project.prefs │ │ │ ├── Core/ │ │ │ │ ├── Inc/ │ │ │ │ │ ├── adc.h │ │ │ │ │ ├── big_sine_wave.h │ │ │ │ │ ├── c_filters.h │ │ │ │ │ ├── chorus.h │ │ │ │ │ ├── dac.h │ │ │ │ │ ├── dma.h │ │ │ │ │ ├── dynamic_smooth.h │ │ │ │ │ ├── float_expo_table.h │ │ │ │ │ ├── gpio.h │ │ │ │ │ ├── lerp.h │ │ │ │ │ ├── main.h │ │ │ │ │ ├── stm32g4xx_hal_conf.h │ │ │ │ │ ├── stm32g4xx_it.h │ │ │ │ │ ├── super_filters.h │ │ │ │ │ └── tim.h │ │ │ │ ├── Src/ │ │ │ │ │ ├── adc.c │ │ │ │ │ ├── c_filters.c │ │ │ │ │ ├── chorus.c │ │ │ │ │ ├── dac.c │ │ │ │ │ ├── dma.c │ │ │ │ │ ├── dynamic_smooth.c │ │ │ │ │ ├── float_expo_table.c │ │ │ │ │ ├── gpio.c │ │ │ │ │ ├── lerp.c │ │ │ │ │ ├── main.c │ │ │ │ │ ├── stm32g4xx_hal_msp.c │ │ │ │ │ ├── stm32g4xx_it.c │ │ │ │ │ ├── super_filters.cpp │ │ │ │ │ ├── syscalls.c │ │ │ │ │ ├── sysmem.c │ │ │ │ │ ├── system_stm32g4xx.c │ │ │ │ │ └── tim.c │ │ │ │ └── Startup/ │ │ │ │ └── startup_stm32g431kbux.s │ │ │ ├── Debug/ │ │ │ │ ├── Core/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── Src/ │ │ │ │ │ │ ├── adc.cyclo │ │ │ │ │ │ ├── adc.d │ │ │ │ │ │ ├── adc.o │ │ │ │ │ │ ├── adc.su │ │ │ │ │ │ ├── c_filters.cyclo │ │ │ │ │ │ ├── c_filters.d │ │ │ │ │ │ ├── c_filters.o │ │ │ │ │ │ ├── c_filters.su │ │ │ │ │ │ ├── chorus.cyclo │ │ │ │ │ │ ├── chorus.d │ │ │ │ │ │ ├── chorus.o │ │ │ │ │ │ ├── chorus.su │ │ │ │ │ │ ├── dac.cyclo │ │ │ │ │ │ ├── dac.d │ │ │ │ │ │ ├── dac.o │ │ │ │ │ │ ├── dac.su │ │ │ │ │ │ ├── dma.cyclo │ │ │ │ │ │ ├── dma.d │ │ │ │ │ │ ├── dma.o │ │ │ │ │ │ ├── dma.su │ │ │ │ │ │ ├── dynamic_smooth.cyclo │ │ │ │ │ │ ├── dynamic_smooth.d │ │ │ │ │ │ ├── dynamic_smooth.o │ │ │ │ │ │ ├── dynamic_smooth.su │ │ │ │ │ │ ├── float_expo_table.cyclo │ │ │ │ │ │ ├── float_expo_table.d │ │ │ │ │ │ ├── float_expo_table.o │ │ │ │ │ │ ├── float_expo_table.su │ │ │ │ │ │ ├── gpio.cyclo │ │ │ │ │ │ ├── gpio.d │ │ │ │ │ │ ├── gpio.o │ │ │ │ │ │ ├── gpio.su │ │ │ │ │ │ ├── lerp.cyclo │ │ │ │ │ │ ├── lerp.d │ │ │ │ │ │ ├── lerp.o │ │ │ │ │ │ ├── lerp.su │ │ │ │ │ │ ├── main.cyclo │ │ │ │ │ │ ├── main.d │ │ │ │ │ │ ├── main.o │ │ │ │ │ │ ├── main.su │ │ │ │ │ │ ├── stm32g4xx_hal_msp.cyclo │ │ │ │ │ │ ├── stm32g4xx_hal_msp.d │ │ │ │ │ │ ├── stm32g4xx_hal_msp.o │ │ │ │ │ │ ├── stm32g4xx_hal_msp.su │ │ │ │ │ │ ├── stm32g4xx_it.cyclo │ │ │ │ │ │ ├── stm32g4xx_it.d │ │ │ │ │ │ ├── stm32g4xx_it.o │ │ │ │ │ │ ├── stm32g4xx_it.su │ │ │ │ │ │ ├── subdir.mk │ │ │ │ │ │ ├── super_filters.cyclo │ │ │ │ │ │ ├── super_filters.d │ │ │ │ │ │ ├── super_filters.o │ │ │ │ │ │ ├── super_filters.su │ │ │ │ │ │ ├── syscalls.cyclo │ │ │ │ │ │ ├── syscalls.d │ │ │ │ │ │ ├── syscalls.o │ │ │ │ │ │ ├── syscalls.su │ │ │ │ │ │ ├── sysmem.cyclo │ │ │ │ │ │ ├── sysmem.d │ │ │ │ │ │ ├── sysmem.o │ │ │ │ │ │ ├── sysmem.su │ │ │ │ │ │ ├── system_stm32g4xx.cyclo │ │ │ │ │ │ ├── system_stm32g4xx.d │ │ │ │ │ │ ├── system_stm32g4xx.o │ │ │ │ │ │ ├── system_stm32g4xx.su │ │ │ │ │ │ ├── tim.cyclo │ │ │ │ │ │ ├── tim.d │ │ │ │ │ │ ├── tim.o │ │ │ │ │ │ └── tim.su │ │ │ │ │ └── Startup/ │ │ │ │ │ ├── startup_stm32g431kbux.d │ │ │ │ │ ├── startup_stm32g431kbux.o │ │ │ │ │ └── subdir.mk │ │ │ │ ├── Drivers/ │ │ │ │ │ └── STM32G4xx_HAL_Driver/ │ │ │ │ │ └── Src/ │ │ │ │ │ ├── stm32g4xx_hal.cyclo │ │ │ │ │ ├── stm32g4xx_hal.d │ │ │ │ │ ├── stm32g4xx_hal.o │ │ │ │ │ ├── stm32g4xx_hal.su │ │ │ │ │ ├── stm32g4xx_hal_adc.cyclo │ │ │ │ │ ├── stm32g4xx_hal_adc.d │ │ │ │ │ ├── stm32g4xx_hal_adc.o │ │ │ │ │ ├── stm32g4xx_hal_adc.su │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.d │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.o │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.su │ │ │ │ │ ├── stm32g4xx_hal_cortex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_cortex.d │ │ │ │ │ ├── stm32g4xx_hal_cortex.o │ │ │ │ │ ├── stm32g4xx_hal_cortex.su │ │ │ │ │ ├── stm32g4xx_hal_dac.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dac.d │ │ │ │ │ ├── stm32g4xx_hal_dac.o │ │ │ │ │ ├── stm32g4xx_hal_dac.su │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.d │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.o │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.su │ │ │ │ │ ├── stm32g4xx_hal_dma.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dma.d │ │ │ │ │ ├── stm32g4xx_hal_dma.o │ │ │ │ │ ├── stm32g4xx_hal_dma.su │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.d │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.o │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.su │ │ │ │ │ ├── stm32g4xx_hal_exti.cyclo │ │ │ │ │ ├── stm32g4xx_hal_exti.d │ │ │ │ │ ├── stm32g4xx_hal_exti.o │ │ │ │ │ ├── stm32g4xx_hal_exti.su │ │ │ │ │ ├── stm32g4xx_hal_flash.cyclo │ │ │ │ │ ├── stm32g4xx_hal_flash.d │ │ │ │ │ ├── stm32g4xx_hal_flash.o │ │ │ │ │ ├── stm32g4xx_hal_flash.su │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.d │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.o │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.su │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.cyclo │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.d │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.o │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.su │ │ │ │ │ ├── stm32g4xx_hal_gpio.cyclo │ │ │ │ │ ├── stm32g4xx_hal_gpio.d │ │ │ │ │ ├── stm32g4xx_hal_gpio.o │ │ │ │ │ ├── stm32g4xx_hal_gpio.su │ │ │ │ │ ├── stm32g4xx_hal_pwr.cyclo │ │ │ │ │ ├── stm32g4xx_hal_pwr.d │ │ │ │ │ ├── stm32g4xx_hal_pwr.o │ │ │ │ │ ├── stm32g4xx_hal_pwr.su │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.d │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.o │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.su │ │ │ │ │ ├── stm32g4xx_hal_rcc.cyclo │ │ │ │ │ ├── stm32g4xx_hal_rcc.d │ │ │ │ │ ├── stm32g4xx_hal_rcc.o │ │ │ │ │ ├── stm32g4xx_hal_rcc.su │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.d │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.o │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.su │ │ │ │ │ ├── stm32g4xx_hal_tim.cyclo │ │ │ │ │ ├── stm32g4xx_hal_tim.d │ │ │ │ │ ├── stm32g4xx_hal_tim.o │ │ │ │ │ ├── stm32g4xx_hal_tim.su │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.d │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.o │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.su │ │ │ │ │ ├── stm32g4xx_ll_adc.cyclo │ │ │ │ │ ├── stm32g4xx_ll_adc.d │ │ │ │ │ ├── stm32g4xx_ll_adc.o │ │ │ │ │ ├── stm32g4xx_ll_adc.su │ │ │ │ │ └── subdir.mk │ │ │ │ ├── chorus_G431.elf │ │ │ │ ├── chorus_G431.list │ │ │ │ ├── makefile │ │ │ │ ├── objects.list │ │ │ │ ├── objects.mk │ │ │ │ └── sources.mk │ │ │ ├── Drivers/ │ │ │ │ ├── CMSIS/ │ │ │ │ │ ├── Device/ │ │ │ │ │ │ └── ST/ │ │ │ │ │ │ └── STM32G4xx/ │ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ │ ├── stm32g431xx.h │ │ │ │ │ │ │ ├── stm32g4xx.h │ │ │ │ │ │ │ └── system_stm32g4xx.h │ │ │ │ │ │ └── LICENSE.txt │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ │ ├── cmsis_armclang.h │ │ │ │ │ │ ├── cmsis_armclang_ltm.h │ │ │ │ │ │ ├── cmsis_compiler.h │ │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ │ ├── cmsis_iccarm.h │ │ │ │ │ │ ├── cmsis_version.h │ │ │ │ │ │ ├── core_armv81mml.h │ │ │ │ │ │ ├── core_armv8mbl.h │ │ │ │ │ │ ├── core_armv8mml.h │ │ │ │ │ │ ├── core_cm0.h │ │ │ │ │ │ ├── core_cm0plus.h │ │ │ │ │ │ ├── core_cm1.h │ │ │ │ │ │ ├── core_cm23.h │ │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ │ ├── core_cm33.h │ │ │ │ │ │ ├── core_cm35p.h │ │ │ │ │ │ ├── core_cm4.h │ │ │ │ │ │ ├── core_cm7.h │ │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ │ ├── core_sc300.h │ │ │ │ │ │ ├── mpu_armv7.h │ │ │ │ │ │ ├── mpu_armv8.h │ │ │ │ │ │ └── tz_context.h │ │ │ │ │ └── LICENSE.txt │ │ │ │ └── STM32G4xx_HAL_Driver/ │ │ │ │ ├── Inc/ │ │ │ │ │ ├── Legacy/ │ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ │ ├── stm32g4xx_hal.h │ │ │ │ │ ├── stm32g4xx_hal_adc.h │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.h │ │ │ │ │ ├── stm32g4xx_hal_cortex.h │ │ │ │ │ ├── stm32g4xx_hal_dac.h │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.h │ │ │ │ │ ├── stm32g4xx_hal_def.h │ │ │ │ │ ├── stm32g4xx_hal_dma.h │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.h │ │ │ │ │ ├── stm32g4xx_hal_exti.h │ │ │ │ │ ├── stm32g4xx_hal_flash.h │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.h │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.h │ │ │ │ │ ├── stm32g4xx_hal_gpio.h │ │ │ │ │ ├── stm32g4xx_hal_gpio_ex.h │ │ │ │ │ ├── stm32g4xx_hal_pwr.h │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.h │ │ │ │ │ ├── stm32g4xx_hal_rcc.h │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.h │ │ │ │ │ ├── stm32g4xx_hal_tim.h │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.h │ │ │ │ │ └── stm32g4xx_ll_adc.h │ │ │ │ ├── LICENSE.txt │ │ │ │ └── Src/ │ │ │ │ ├── stm32g4xx_hal.c │ │ │ │ ├── stm32g4xx_hal_adc.c │ │ │ │ ├── stm32g4xx_hal_adc_ex.c │ │ │ │ ├── stm32g4xx_hal_cortex.c │ │ │ │ ├── stm32g4xx_hal_dac.c │ │ │ │ ├── stm32g4xx_hal_dac_ex.c │ │ │ │ ├── stm32g4xx_hal_dma.c │ │ │ │ ├── stm32g4xx_hal_dma_ex.c │ │ │ │ ├── stm32g4xx_hal_exti.c │ │ │ │ ├── stm32g4xx_hal_flash.c │ │ │ │ ├── stm32g4xx_hal_flash_ex.c │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.c │ │ │ │ ├── stm32g4xx_hal_gpio.c │ │ │ │ ├── stm32g4xx_hal_pwr.c │ │ │ │ ├── stm32g4xx_hal_pwr_ex.c │ │ │ │ ├── stm32g4xx_hal_rcc.c │ │ │ │ ├── stm32g4xx_hal_rcc_ex.c │ │ │ │ ├── stm32g4xx_hal_tim.c │ │ │ │ ├── stm32g4xx_hal_tim_ex.c │ │ │ │ └── stm32g4xx_ll_adc.c │ │ │ ├── STM32G431KBUX_FLASH.ld │ │ │ ├── chorus_G431.ioc │ │ │ └── chorus_G431.launch │ │ └── jlcpcb/ │ │ ├── chorus_REV1_JLCBOM.csv │ │ └── chorus_REV1_JLCXY.csv │ ├── EG/ │ │ ├── EG_REV1_PANEL.ai │ │ ├── diptrace/ │ │ │ ├── EG_REV1.dch │ │ │ ├── EG_REV1.dip │ │ │ └── EG_REV1_PANEL.dip │ │ └── jlcpcb/ │ │ ├── EG_REV1_JLCBOM.csv │ │ └── EG_REV1_JLCXY.csv │ ├── PHRSR/ │ │ ├── PHRSR_REV7_PANEL.ai │ │ ├── diptrace/ │ │ │ ├── PHRSR_2021_V7.dch │ │ │ ├── PHRSR_2021_V7.dip │ │ │ └── PHRSR_2022_PANEL.dip │ │ ├── firmware/ │ │ │ ├── PHRSR_2024.elf │ │ │ ├── PHRSR_V4/ │ │ │ │ ├── .cproject │ │ │ │ ├── .mxproject │ │ │ │ ├── .project │ │ │ │ ├── .settings/ │ │ │ │ │ ├── language.settings.xml │ │ │ │ │ └── stm32cubeide.project.prefs │ │ │ │ ├── Core/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── expo_lut.h │ │ │ │ │ │ ├── pin_map.h │ │ │ │ │ │ ├── stm32F334_config.h │ │ │ │ │ │ ├── stm32f30x.h │ │ │ │ │ │ ├── stm32f30x_it.h │ │ │ │ │ │ └── system_stm32f30x.h │ │ │ │ │ ├── Src/ │ │ │ │ │ │ ├── main.c │ │ │ │ │ │ ├── syscalls.c │ │ │ │ │ │ └── system_stm32f30x.c │ │ │ │ │ └── Startup/ │ │ │ │ │ └── startup_stm32.s │ │ │ │ ├── Debug/ │ │ │ │ │ ├── Core/ │ │ │ │ │ │ ├── Src/ │ │ │ │ │ │ │ ├── main.d │ │ │ │ │ │ │ ├── main.o │ │ │ │ │ │ │ ├── main.su │ │ │ │ │ │ │ ├── subdir.mk │ │ │ │ │ │ │ ├── syscalls.d │ │ │ │ │ │ │ ├── syscalls.o │ │ │ │ │ │ │ ├── syscalls.su │ │ │ │ │ │ │ ├── system_stm32f30x.d │ │ │ │ │ │ │ ├── system_stm32f30x.o │ │ │ │ │ │ │ └── system_stm32f30x.su │ │ │ │ │ │ └── Startup/ │ │ │ │ │ │ ├── startup_stm32.d │ │ │ │ │ │ ├── startup_stm32.o │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── Drivers/ │ │ │ │ │ │ └── STM32F3xx_HAL_Driver/ │ │ │ │ │ │ └── Src/ │ │ │ │ │ │ ├── stm32f30x_adc.d │ │ │ │ │ │ ├── stm32f30x_adc.o │ │ │ │ │ │ ├── stm32f30x_adc.su │ │ │ │ │ │ ├── stm32f30x_can.d │ │ │ │ │ │ ├── stm32f30x_can.o │ │ │ │ │ │ ├── stm32f30x_can.su │ │ │ │ │ │ ├── stm32f30x_comp.d │ │ │ │ │ │ ├── stm32f30x_comp.o │ │ │ │ │ │ ├── stm32f30x_comp.su │ │ │ │ │ │ ├── stm32f30x_crc.d │ │ │ │ │ │ ├── stm32f30x_crc.o │ │ │ │ │ │ ├── stm32f30x_crc.su │ │ │ │ │ │ ├── stm32f30x_dac.d │ │ │ │ │ │ ├── stm32f30x_dac.o │ │ │ │ │ │ ├── stm32f30x_dac.su │ │ │ │ │ │ ├── stm32f30x_dbgmcu.d │ │ │ │ │ │ ├── stm32f30x_dbgmcu.o │ │ │ │ │ │ ├── stm32f30x_dbgmcu.su │ │ │ │ │ │ ├── stm32f30x_dma.d │ │ │ │ │ │ ├── stm32f30x_dma.o │ │ │ │ │ │ ├── stm32f30x_dma.su │ │ │ │ │ │ ├── stm32f30x_exti.d │ │ │ │ │ │ ├── stm32f30x_exti.o │ │ │ │ │ │ ├── stm32f30x_exti.su │ │ │ │ │ │ ├── stm32f30x_flash.d │ │ │ │ │ │ ├── stm32f30x_flash.o │ │ │ │ │ │ ├── stm32f30x_flash.su │ │ │ │ │ │ ├── stm32f30x_fmc.d │ │ │ │ │ │ ├── stm32f30x_fmc.o │ │ │ │ │ │ ├── stm32f30x_fmc.su │ │ │ │ │ │ ├── stm32f30x_gpio.d │ │ │ │ │ │ ├── stm32f30x_gpio.o │ │ │ │ │ │ ├── stm32f30x_gpio.su │ │ │ │ │ │ ├── stm32f30x_hrtim.d │ │ │ │ │ │ ├── stm32f30x_hrtim.o │ │ │ │ │ │ ├── stm32f30x_hrtim.su │ │ │ │ │ │ ├── stm32f30x_i2c.d │ │ │ │ │ │ ├── stm32f30x_i2c.o │ │ │ │ │ │ ├── stm32f30x_i2c.su │ │ │ │ │ │ ├── stm32f30x_iwdg.d │ │ │ │ │ │ ├── stm32f30x_iwdg.o │ │ │ │ │ │ ├── stm32f30x_iwdg.su │ │ │ │ │ │ ├── stm32f30x_misc.d │ │ │ │ │ │ ├── stm32f30x_misc.o │ │ │ │ │ │ ├── stm32f30x_misc.su │ │ │ │ │ │ ├── stm32f30x_opamp.d │ │ │ │ │ │ ├── stm32f30x_opamp.o │ │ │ │ │ │ ├── stm32f30x_opamp.su │ │ │ │ │ │ ├── stm32f30x_pwr.d │ │ │ │ │ │ ├── stm32f30x_pwr.o │ │ │ │ │ │ ├── stm32f30x_pwr.su │ │ │ │ │ │ ├── stm32f30x_rcc.d │ │ │ │ │ │ ├── stm32f30x_rcc.o │ │ │ │ │ │ ├── stm32f30x_rcc.su │ │ │ │ │ │ ├── stm32f30x_rtc.d │ │ │ │ │ │ ├── stm32f30x_rtc.o │ │ │ │ │ │ ├── stm32f30x_rtc.su │ │ │ │ │ │ ├── stm32f30x_spi.d │ │ │ │ │ │ ├── stm32f30x_spi.o │ │ │ │ │ │ ├── stm32f30x_spi.su │ │ │ │ │ │ ├── stm32f30x_syscfg.d │ │ │ │ │ │ ├── stm32f30x_syscfg.o │ │ │ │ │ │ ├── stm32f30x_syscfg.su │ │ │ │ │ │ ├── stm32f30x_tim.d │ │ │ │ │ │ ├── stm32f30x_tim.o │ │ │ │ │ │ ├── stm32f30x_tim.su │ │ │ │ │ │ ├── stm32f30x_usart.d │ │ │ │ │ │ ├── stm32f30x_usart.o │ │ │ │ │ │ ├── stm32f30x_usart.su │ │ │ │ │ │ ├── stm32f30x_wwdg.d │ │ │ │ │ │ ├── stm32f30x_wwdg.o │ │ │ │ │ │ ├── stm32f30x_wwdg.su │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── PHRSR_V4.elf │ │ │ │ │ ├── PHRSR_V4.list │ │ │ │ │ ├── makefile │ │ │ │ │ ├── objects.list │ │ │ │ │ ├── objects.mk │ │ │ │ │ └── sources.mk │ │ │ │ ├── Drivers/ │ │ │ │ │ ├── CMSIS/ │ │ │ │ │ │ ├── Device/ │ │ │ │ │ │ │ └── ST/ │ │ │ │ │ │ │ └── STM32F3xx/ │ │ │ │ │ │ │ └── Include/ │ │ │ │ │ │ │ ├── stm32f334x8.h │ │ │ │ │ │ │ ├── stm32f3xx.h │ │ │ │ │ │ │ └── system_stm32f3xx.h │ │ │ │ │ │ └── Include/ │ │ │ │ │ │ ├── arm_common_tables.h │ │ │ │ │ │ ├── arm_const_structs.h │ │ │ │ │ │ ├── arm_math.h │ │ │ │ │ │ ├── core_cm0.h │ │ │ │ │ │ ├── core_cm0plus.h │ │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ │ ├── core_cm4.h │ │ │ │ │ │ ├── core_cm7.h │ │ │ │ │ │ ├── core_cmFunc.h │ │ │ │ │ │ ├── core_cmInstr.h │ │ │ │ │ │ ├── core_cmSimd.h │ │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ │ └── core_sc300.h │ │ │ │ │ └── STM32F3xx_HAL_Driver/ │ │ │ │ │ ├── Inc/ │ │ │ │ │ │ ├── stm32f30x_adc.h │ │ │ │ │ │ ├── stm32f30x_can.h │ │ │ │ │ │ ├── stm32f30x_comp.h │ │ │ │ │ │ ├── stm32f30x_conf.h │ │ │ │ │ │ ├── stm32f30x_crc.h │ │ │ │ │ │ ├── stm32f30x_dac.h │ │ │ │ │ │ ├── stm32f30x_dbgmcu.h │ │ │ │ │ │ ├── stm32f30x_dma.h │ │ │ │ │ │ ├── stm32f30x_exti.h │ │ │ │ │ │ ├── stm32f30x_flash.h │ │ │ │ │ │ ├── stm32f30x_fmc.h │ │ │ │ │ │ ├── stm32f30x_gpio.h │ │ │ │ │ │ ├── stm32f30x_hrtim.h │ │ │ │ │ │ ├── stm32f30x_i2c.h │ │ │ │ │ │ ├── stm32f30x_iwdg.h │ │ │ │ │ │ ├── stm32f30x_misc.h │ │ │ │ │ │ ├── stm32f30x_opamp.h │ │ │ │ │ │ ├── stm32f30x_pwr.h │ │ │ │ │ │ ├── stm32f30x_rcc.h │ │ │ │ │ │ ├── stm32f30x_rtc.h │ │ │ │ │ │ ├── stm32f30x_spi.h │ │ │ │ │ │ ├── stm32f30x_syscfg.h │ │ │ │ │ │ ├── stm32f30x_tim.h │ │ │ │ │ │ ├── stm32f30x_usart.h │ │ │ │ │ │ └── stm32f30x_wwdg.h │ │ │ │ │ └── Src/ │ │ │ │ │ ├── stm32f30x_adc.c │ │ │ │ │ ├── stm32f30x_can.c │ │ │ │ │ ├── stm32f30x_comp.c │ │ │ │ │ ├── stm32f30x_crc.c │ │ │ │ │ ├── stm32f30x_dac.c │ │ │ │ │ ├── stm32f30x_dbgmcu.c │ │ │ │ │ ├── stm32f30x_dma.c │ │ │ │ │ ├── stm32f30x_exti.c │ │ │ │ │ ├── stm32f30x_flash.c │ │ │ │ │ ├── stm32f30x_fmc.c │ │ │ │ │ ├── stm32f30x_gpio.c │ │ │ │ │ ├── stm32f30x_hrtim.c │ │ │ │ │ ├── stm32f30x_i2c.c │ │ │ │ │ ├── stm32f30x_iwdg.c │ │ │ │ │ ├── stm32f30x_misc.c │ │ │ │ │ ├── stm32f30x_opamp.c │ │ │ │ │ ├── stm32f30x_pwr.c │ │ │ │ │ ├── stm32f30x_rcc.c │ │ │ │ │ ├── stm32f30x_rtc.c │ │ │ │ │ ├── stm32f30x_spi.c │ │ │ │ │ ├── stm32f30x_syscfg.c │ │ │ │ │ ├── stm32f30x_tim.c │ │ │ │ │ ├── stm32f30x_usart.c │ │ │ │ │ └── stm32f30x_wwdg.c │ │ │ │ ├── PHRSR_V4.ioc │ │ │ │ ├── PHRSR_V4.launch │ │ │ │ └── STM32F334K4TX_FLASH.ld │ │ │ └── README.md │ │ └── jlcpcb/ │ │ ├── PHRSR_2021_V7_JLCBOM.csv │ │ └── PHRSR_2021_V7_JLCXY.csv │ ├── README.md │ ├── ROOM/ │ │ ├── diptrace/ │ │ │ ├── room_REV1.dch │ │ │ ├── room_REV1.dip │ │ │ ├── room_panel_rev1.dip │ │ │ ├── room_panel_rev1_border.dip │ │ │ ├── ~room_REV1.dch~ │ │ │ └── ~room_REV1.dip~ │ │ ├── firmware/ │ │ │ ├── ROOM_2024.elf │ │ │ └── Reverb/ │ │ │ ├── .cproject │ │ │ ├── .mxproject │ │ │ ├── .project │ │ │ ├── .settings/ │ │ │ │ ├── com.st.stm32cube.ide.mcu.sfrview.prefs │ │ │ │ ├── language.settings.xml │ │ │ │ ├── org.eclipse.cdt.core.prefs │ │ │ │ └── stm32cubeide.project.prefs │ │ │ ├── Core/ │ │ │ │ ├── Inc/ │ │ │ │ │ ├── adc.h │ │ │ │ │ ├── dac.h │ │ │ │ │ ├── dma.h │ │ │ │ │ ├── gpio.h │ │ │ │ │ ├── main.h │ │ │ │ │ ├── sandbox.h │ │ │ │ │ ├── stm32g4xx_hal_conf.h │ │ │ │ │ ├── stm32g4xx_it.h │ │ │ │ │ ├── tanh_lookup_table.h │ │ │ │ │ └── tim.h │ │ │ │ ├── Lib/ │ │ │ │ │ ├── big_sine_wave.c │ │ │ │ │ ├── c_filters.c │ │ │ │ │ ├── chorus.c │ │ │ │ │ ├── delay.c │ │ │ │ │ ├── dynamic_smooth.c │ │ │ │ │ ├── envelopes.c │ │ │ │ │ ├── float_expo_table.c │ │ │ │ │ ├── include/ │ │ │ │ │ │ ├── big_sine_wave.h │ │ │ │ │ │ ├── c_filters.h │ │ │ │ │ │ ├── chorus.h │ │ │ │ │ │ ├── delay.h │ │ │ │ │ │ ├── dynamic_smooth.h │ │ │ │ │ │ ├── envelopes.h │ │ │ │ │ │ ├── expit.h │ │ │ │ │ │ ├── float_expo_table.h │ │ │ │ │ │ ├── lerp.h │ │ │ │ │ │ ├── lfo.h │ │ │ │ │ │ ├── logit.h │ │ │ │ │ │ ├── mtof.h │ │ │ │ │ │ ├── noise.h │ │ │ │ │ │ ├── opamp.h │ │ │ │ │ │ ├── operator.h │ │ │ │ │ │ ├── preset_table.h │ │ │ │ │ │ ├── shared_delays.h │ │ │ │ │ │ └── tanh_table.h │ │ │ │ │ ├── lerp.c │ │ │ │ │ ├── lfo.c │ │ │ │ │ ├── noise.c │ │ │ │ │ ├── opamp.c │ │ │ │ │ ├── operator.c │ │ │ │ │ └── shared_delays.c │ │ │ │ ├── Src/ │ │ │ │ │ ├── adc.c │ │ │ │ │ ├── dac.c │ │ │ │ │ ├── dma.c │ │ │ │ │ ├── gpio.c │ │ │ │ │ ├── main.c │ │ │ │ │ ├── sandbox.c │ │ │ │ │ ├── stm32g4xx_hal_msp.c │ │ │ │ │ ├── stm32g4xx_it.c │ │ │ │ │ ├── syscalls.c │ │ │ │ │ ├── sysmem.c │ │ │ │ │ ├── system_stm32g4xx.c │ │ │ │ │ ├── tanh_lookup_table.c │ │ │ │ │ └── tim.c │ │ │ │ └── Startup/ │ │ │ │ └── startup_stm32g431kbux.s │ │ │ ├── Debug/ │ │ │ │ ├── Core/ │ │ │ │ │ ├── Lib/ │ │ │ │ │ │ ├── big_sine_wave.cyclo │ │ │ │ │ │ ├── big_sine_wave.d │ │ │ │ │ │ ├── big_sine_wave.o │ │ │ │ │ │ ├── big_sine_wave.su │ │ │ │ │ │ ├── c_filters.cyclo │ │ │ │ │ │ ├── c_filters.d │ │ │ │ │ │ ├── c_filters.o │ │ │ │ │ │ ├── c_filters.su │ │ │ │ │ │ ├── chorus.cyclo │ │ │ │ │ │ ├── chorus.d │ │ │ │ │ │ ├── chorus.o │ │ │ │ │ │ ├── chorus.su │ │ │ │ │ │ ├── delay.cyclo │ │ │ │ │ │ ├── delay.d │ │ │ │ │ │ ├── delay.o │ │ │ │ │ │ ├── delay.su │ │ │ │ │ │ ├── dynamic_smooth.cyclo │ │ │ │ │ │ ├── dynamic_smooth.d │ │ │ │ │ │ ├── dynamic_smooth.o │ │ │ │ │ │ ├── dynamic_smooth.su │ │ │ │ │ │ ├── envelopes.cyclo │ │ │ │ │ │ ├── envelopes.d │ │ │ │ │ │ ├── envelopes.o │ │ │ │ │ │ ├── envelopes.su │ │ │ │ │ │ ├── float_expo_table.cyclo │ │ │ │ │ │ ├── float_expo_table.d │ │ │ │ │ │ ├── float_expo_table.o │ │ │ │ │ │ ├── float_expo_table.su │ │ │ │ │ │ ├── float_expo_table_with_f.cyclo │ │ │ │ │ │ ├── float_expo_table_with_f.d │ │ │ │ │ │ ├── float_expo_table_with_f.o │ │ │ │ │ │ ├── float_expo_table_with_f.su │ │ │ │ │ │ ├── lerp.cyclo │ │ │ │ │ │ ├── lerp.d │ │ │ │ │ │ ├── lerp.o │ │ │ │ │ │ ├── lerp.su │ │ │ │ │ │ ├── lfo.cyclo │ │ │ │ │ │ ├── lfo.d │ │ │ │ │ │ ├── lfo.o │ │ │ │ │ │ ├── lfo.su │ │ │ │ │ │ ├── noise.cyclo │ │ │ │ │ │ ├── noise.d │ │ │ │ │ │ ├── noise.o │ │ │ │ │ │ ├── noise.su │ │ │ │ │ │ ├── opamp.cyclo │ │ │ │ │ │ ├── opamp.d │ │ │ │ │ │ ├── opamp.o │ │ │ │ │ │ ├── opamp.su │ │ │ │ │ │ ├── operator.cyclo │ │ │ │ │ │ ├── operator.d │ │ │ │ │ │ ├── operator.o │ │ │ │ │ │ ├── operator.su │ │ │ │ │ │ ├── sandbox.su │ │ │ │ │ │ ├── shared_delays.cyclo │ │ │ │ │ │ ├── shared_delays.d │ │ │ │ │ │ ├── shared_delays.o │ │ │ │ │ │ ├── shared_delays.su │ │ │ │ │ │ └── subdir.mk │ │ │ │ │ ├── Src/ │ │ │ │ │ │ ├── adc.cyclo │ │ │ │ │ │ ├── adc.d │ │ │ │ │ │ ├── adc.o │ │ │ │ │ │ ├── adc.su │ │ │ │ │ │ ├── dac.cyclo │ │ │ │ │ │ ├── dac.d │ │ │ │ │ │ ├── dac.o │ │ │ │ │ │ ├── dac.su │ │ │ │ │ │ ├── dma.cyclo │ │ │ │ │ │ ├── dma.d │ │ │ │ │ │ ├── dma.o │ │ │ │ │ │ ├── dma.su │ │ │ │ │ │ ├── gpio.cyclo │ │ │ │ │ │ ├── gpio.d │ │ │ │ │ │ ├── gpio.o │ │ │ │ │ │ ├── gpio.su │ │ │ │ │ │ ├── main.cyclo │ │ │ │ │ │ ├── main.d │ │ │ │ │ │ ├── main.o │ │ │ │ │ │ ├── main.su │ │ │ │ │ │ ├── sandbox.cyclo │ │ │ │ │ │ ├── sandbox.d │ │ │ │ │ │ ├── sandbox.o │ │ │ │ │ │ ├── sandbox.su │ │ │ │ │ │ ├── stm32g4xx_hal_msp.cyclo │ │ │ │ │ │ ├── stm32g4xx_hal_msp.d │ │ │ │ │ │ ├── stm32g4xx_hal_msp.o │ │ │ │ │ │ ├── stm32g4xx_hal_msp.su │ │ │ │ │ │ ├── stm32g4xx_it.cyclo │ │ │ │ │ │ ├── stm32g4xx_it.d │ │ │ │ │ │ ├── stm32g4xx_it.o │ │ │ │ │ │ ├── stm32g4xx_it.su │ │ │ │ │ │ ├── subdir.mk │ │ │ │ │ │ ├── syscalls.cyclo │ │ │ │ │ │ ├── syscalls.d │ │ │ │ │ │ ├── syscalls.o │ │ │ │ │ │ ├── syscalls.su │ │ │ │ │ │ ├── sysmem.cyclo │ │ │ │ │ │ ├── sysmem.d │ │ │ │ │ │ ├── sysmem.o │ │ │ │ │ │ ├── sysmem.su │ │ │ │ │ │ ├── system_stm32g4xx.cyclo │ │ │ │ │ │ ├── system_stm32g4xx.d │ │ │ │ │ │ ├── system_stm32g4xx.o │ │ │ │ │ │ ├── system_stm32g4xx.su │ │ │ │ │ │ ├── tanh_lookup_table.cyclo │ │ │ │ │ │ ├── tanh_lookup_table.d │ │ │ │ │ │ ├── tanh_lookup_table.o │ │ │ │ │ │ ├── tanh_lookup_table.su │ │ │ │ │ │ ├── tim.cyclo │ │ │ │ │ │ ├── tim.d │ │ │ │ │ │ ├── tim.o │ │ │ │ │ │ └── tim.su │ │ │ │ │ └── Startup/ │ │ │ │ │ ├── startup_stm32g431kbux.d │ │ │ │ │ ├── startup_stm32g431kbux.o │ │ │ │ │ └── subdir.mk │ │ │ │ ├── Drivers/ │ │ │ │ │ └── STM32G4xx_HAL_Driver/ │ │ │ │ │ └── Src/ │ │ │ │ │ ├── stm32g4xx_hal.cyclo │ │ │ │ │ ├── stm32g4xx_hal.d │ │ │ │ │ ├── stm32g4xx_hal.o │ │ │ │ │ ├── stm32g4xx_hal.su │ │ │ │ │ ├── stm32g4xx_hal_adc.cyclo │ │ │ │ │ ├── stm32g4xx_hal_adc.d │ │ │ │ │ ├── stm32g4xx_hal_adc.o │ │ │ │ │ ├── stm32g4xx_hal_adc.su │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.d │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.o │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.su │ │ │ │ │ ├── stm32g4xx_hal_cortex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_cortex.d │ │ │ │ │ ├── stm32g4xx_hal_cortex.o │ │ │ │ │ ├── stm32g4xx_hal_cortex.su │ │ │ │ │ ├── stm32g4xx_hal_dac.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dac.d │ │ │ │ │ ├── stm32g4xx_hal_dac.o │ │ │ │ │ ├── stm32g4xx_hal_dac.su │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.d │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.o │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.su │ │ │ │ │ ├── stm32g4xx_hal_dma.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dma.d │ │ │ │ │ ├── stm32g4xx_hal_dma.o │ │ │ │ │ ├── stm32g4xx_hal_dma.su │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.d │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.o │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.su │ │ │ │ │ ├── stm32g4xx_hal_exti.cyclo │ │ │ │ │ ├── stm32g4xx_hal_exti.d │ │ │ │ │ ├── stm32g4xx_hal_exti.o │ │ │ │ │ ├── stm32g4xx_hal_exti.su │ │ │ │ │ ├── stm32g4xx_hal_flash.cyclo │ │ │ │ │ ├── stm32g4xx_hal_flash.d │ │ │ │ │ ├── stm32g4xx_hal_flash.o │ │ │ │ │ ├── stm32g4xx_hal_flash.su │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.d │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.o │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.su │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.cyclo │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.d │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.o │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.su │ │ │ │ │ ├── stm32g4xx_hal_gpio.cyclo │ │ │ │ │ ├── stm32g4xx_hal_gpio.d │ │ │ │ │ ├── stm32g4xx_hal_gpio.o │ │ │ │ │ ├── stm32g4xx_hal_gpio.su │ │ │ │ │ ├── stm32g4xx_hal_pwr.cyclo │ │ │ │ │ ├── stm32g4xx_hal_pwr.d │ │ │ │ │ ├── stm32g4xx_hal_pwr.o │ │ │ │ │ ├── stm32g4xx_hal_pwr.su │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.d │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.o │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.su │ │ │ │ │ ├── stm32g4xx_hal_rcc.cyclo │ │ │ │ │ ├── stm32g4xx_hal_rcc.d │ │ │ │ │ ├── stm32g4xx_hal_rcc.o │ │ │ │ │ ├── stm32g4xx_hal_rcc.su │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.d │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.o │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.su │ │ │ │ │ ├── stm32g4xx_hal_tim.cyclo │ │ │ │ │ ├── stm32g4xx_hal_tim.d │ │ │ │ │ ├── stm32g4xx_hal_tim.o │ │ │ │ │ ├── stm32g4xx_hal_tim.su │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.cyclo │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.d │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.o │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.su │ │ │ │ │ ├── stm32g4xx_ll_adc.cyclo │ │ │ │ │ ├── stm32g4xx_ll_adc.d │ │ │ │ │ ├── stm32g4xx_ll_adc.o │ │ │ │ │ ├── stm32g4xx_ll_adc.su │ │ │ │ │ └── subdir.mk │ │ │ │ ├── ROOM_2024.elf │ │ │ │ ├── Reverb.list │ │ │ │ ├── makefile │ │ │ │ ├── objects.list │ │ │ │ ├── objects.mk │ │ │ │ └── sources.mk │ │ │ ├── Drivers/ │ │ │ │ ├── CMSIS/ │ │ │ │ │ ├── Device/ │ │ │ │ │ │ └── ST/ │ │ │ │ │ │ └── STM32G4xx/ │ │ │ │ │ │ ├── Include/ │ │ │ │ │ │ │ ├── stm32g431xx.h │ │ │ │ │ │ │ ├── stm32g4xx.h │ │ │ │ │ │ │ └── system_stm32g4xx.h │ │ │ │ │ │ └── LICENSE.txt │ │ │ │ │ ├── Include/ │ │ │ │ │ │ ├── cmsis_armcc.h │ │ │ │ │ │ ├── cmsis_armclang.h │ │ │ │ │ │ ├── cmsis_armclang_ltm.h │ │ │ │ │ │ ├── cmsis_compiler.h │ │ │ │ │ │ ├── cmsis_gcc.h │ │ │ │ │ │ ├── cmsis_iccarm.h │ │ │ │ │ │ ├── cmsis_version.h │ │ │ │ │ │ ├── core_armv81mml.h │ │ │ │ │ │ ├── core_armv8mbl.h │ │ │ │ │ │ ├── core_armv8mml.h │ │ │ │ │ │ ├── core_cm0.h │ │ │ │ │ │ ├── core_cm0plus.h │ │ │ │ │ │ ├── core_cm1.h │ │ │ │ │ │ ├── core_cm23.h │ │ │ │ │ │ ├── core_cm3.h │ │ │ │ │ │ ├── core_cm33.h │ │ │ │ │ │ ├── core_cm35p.h │ │ │ │ │ │ ├── core_cm4.h │ │ │ │ │ │ ├── core_cm7.h │ │ │ │ │ │ ├── core_sc000.h │ │ │ │ │ │ ├── core_sc300.h │ │ │ │ │ │ ├── mpu_armv7.h │ │ │ │ │ │ ├── mpu_armv8.h │ │ │ │ │ │ └── tz_context.h │ │ │ │ │ └── LICENSE.txt │ │ │ │ └── STM32G4xx_HAL_Driver/ │ │ │ │ ├── Inc/ │ │ │ │ │ ├── Legacy/ │ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ │ ├── stm32g4xx_hal.h │ │ │ │ │ ├── stm32g4xx_hal_adc.h │ │ │ │ │ ├── stm32g4xx_hal_adc_ex.h │ │ │ │ │ ├── stm32g4xx_hal_cortex.h │ │ │ │ │ ├── stm32g4xx_hal_dac.h │ │ │ │ │ ├── stm32g4xx_hal_dac_ex.h │ │ │ │ │ ├── stm32g4xx_hal_def.h │ │ │ │ │ ├── stm32g4xx_hal_dma.h │ │ │ │ │ ├── stm32g4xx_hal_dma_ex.h │ │ │ │ │ ├── stm32g4xx_hal_exti.h │ │ │ │ │ ├── stm32g4xx_hal_flash.h │ │ │ │ │ ├── stm32g4xx_hal_flash_ex.h │ │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.h │ │ │ │ │ ├── stm32g4xx_hal_gpio.h │ │ │ │ │ ├── stm32g4xx_hal_gpio_ex.h │ │ │ │ │ ├── stm32g4xx_hal_pwr.h │ │ │ │ │ ├── stm32g4xx_hal_pwr_ex.h │ │ │ │ │ ├── stm32g4xx_hal_rcc.h │ │ │ │ │ ├── stm32g4xx_hal_rcc_ex.h │ │ │ │ │ ├── stm32g4xx_hal_tim.h │ │ │ │ │ ├── stm32g4xx_hal_tim_ex.h │ │ │ │ │ └── stm32g4xx_ll_adc.h │ │ │ │ ├── LICENSE.txt │ │ │ │ └── Src/ │ │ │ │ ├── stm32g4xx_hal.c │ │ │ │ ├── stm32g4xx_hal_adc.c │ │ │ │ ├── stm32g4xx_hal_adc_ex.c │ │ │ │ ├── stm32g4xx_hal_cortex.c │ │ │ │ ├── stm32g4xx_hal_dac.c │ │ │ │ ├── stm32g4xx_hal_dac_ex.c │ │ │ │ ├── stm32g4xx_hal_dma.c │ │ │ │ ├── stm32g4xx_hal_dma_ex.c │ │ │ │ ├── stm32g4xx_hal_exti.c │ │ │ │ ├── stm32g4xx_hal_flash.c │ │ │ │ ├── stm32g4xx_hal_flash_ex.c │ │ │ │ ├── stm32g4xx_hal_flash_ramfunc.c │ │ │ │ ├── stm32g4xx_hal_gpio.c │ │ │ │ ├── stm32g4xx_hal_pwr.c │ │ │ │ ├── stm32g4xx_hal_pwr_ex.c │ │ │ │ ├── stm32g4xx_hal_rcc.c │ │ │ │ ├── stm32g4xx_hal_rcc_ex.c │ │ │ │ ├── stm32g4xx_hal_tim.c │ │ │ │ ├── stm32g4xx_hal_tim_ex.c │ │ │ │ └── stm32g4xx_ll_adc.c │ │ │ ├── Reverb.ioc │ │ │ ├── Reverb.launch │ │ │ └── STM32G431KBUX_FLASH.ld │ │ ├── jlcpcb/ │ │ │ ├── room_REV1_JLCBOM.csv │ │ │ └── room_REV1_JLCXY.csv │ │ └── room_rev1.ai │ ├── SCANNER/ │ │ ├── SCANNER_REV2_PANEL.ai │ │ ├── diptrace/ │ │ │ ├── scanner_rev2.dch │ │ │ ├── scanner_rev2.dip │ │ │ └── scanner_rev2_panel.dip │ │ └── jlcpcb/ │ │ ├── scanner_REV2_JLCBOM.csv │ │ └── scanner_REV2_JLCXY.csv │ ├── SVFs/ │ │ ├── SVFs_REV3_PANEL.ai │ │ ├── diptrace/ │ │ │ ├── SVFs_REV3.dch │ │ │ ├── SVFs_REV3.dip │ │ │ └── SVFs_REV3_PANEL.dip │ │ └── jlcpcb/ │ │ ├── SVFs_2164_2021_REV3_JLCBOM.csv │ │ └── SVFs_2164_2021_REV3_JLCXY.csv │ ├── TVCA/ │ │ ├── TVCA_REV3_PANEL.ai │ │ ├── diptrace/ │ │ │ ├── TVCA_REV3.dch │ │ │ ├── TVCA_REV3.dip │ │ │ └── TVCA_REV3_PANEL.dip │ │ └── jlcpcb/ │ │ ├── TVCA_REV3_JLCBOM.csv │ │ └── TVCA_REV3_JLCXY.csv │ └── VCAs/ │ ├── VCAs_REV2_PANEL.ai │ ├── diptrace/ │ │ ├── VCAs_REV2.dch │ │ ├── VCAs_REV2.dip │ │ └── VCAs_REV2_PANEL.dip │ └── jlcpcb/ │ ├── VCAS_2022_REV1_JLCXY.csv │ └── VCAS_2022_REV2_JLCBOM.csv ├── README.md └── Unreleased/ ├── OTAVCAs/ │ ├── OTAVCA_x2_V1.ai │ ├── OTAVCAs_REV2.dch │ ├── OTAVCAs_REV2.dip │ ├── OTAVCAs_REV2_JLCBOM.csv │ └── OTAVCAs_REV2_JLCXY.csv ├── PNGBL/ │ ├── PNGBL_V2_BOM.csv │ ├── PNGBL_V2_JLCBOM.csv │ ├── PNGBL_V2_JLCXY.csv │ ├── PNGBL_V2_XY.csv │ ├── SVF_V2.dch │ └── SVF_V2.dip ├── README.md └── S&H/ ├── SNH_REV1_PCB_PANEL.ai ├── diptrace/ │ ├── SnH_REV1.dch │ ├── SnH_REV1.dip │ └── SnH_REV1_PANEL.dip └── manufacturing/ ├── SNH_REV1_JLCBOM.csv └── SNH_REV1_JLCXY.csv ================================================ FILE CONTENTS ================================================ ================================================ FILE: .gitignore ================================================ .DS_Store ================================================ FILE: Production Modules/2OPFM/2OPFM_REV5_PANEL.ai ================================================ %PDF-1.6 % 1 0 obj <>/OCGs[33 0 R 32 0 R 34 0 R 35 0 R]>>/Pages 3 0 R/Type/Catalog>> endobj 2 0 obj <>stream application/pdf 2OPFM_2022_PANEL 2022-09-28T12:46:35-05:00 2022-09-28T12:46:35-05:00 2022-09-28T12:46:34-05:00 Adobe Illustrator 26.0 (Macintosh) 60 256 JPEG /9j/4AAQSkZJRgABAgEASABIAAD/7QAsUGhvdG9zaG9wIDMuMAA4QklNA+0AAAAAABAASAAAAAEA AQBIAAAAAQAB/+4ADkFkb2JlAGTAAAAAAf/bAIQABgQEBAUEBgUFBgkGBQYJCwgGBggLDAoKCwoK DBAMDAwMDAwQDA4PEA8ODBMTFBQTExwbGxscHx8fHx8fHx8fHwEHBwcNDA0YEBAYGhURFRofHx8f Hx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8f/8AAEQgBAAA8AwER AAIRAQMRAf/EAaIAAAAHAQEBAQEAAAAAAAAAAAQFAwIGAQAHCAkKCwEAAgIDAQEBAQEAAAAAAAAA AQACAwQFBgcICQoLEAACAQMDAgQCBgcDBAIGAnMBAgMRBAAFIRIxQVEGE2EicYEUMpGhBxWxQiPB UtHhMxZi8CRygvElQzRTkqKyY3PCNUQnk6OzNhdUZHTD0uIIJoMJChgZhJRFRqS0VtNVKBry4/PE 1OT0ZXWFlaW1xdXl9WZ2hpamtsbW5vY3R1dnd4eXp7fH1+f3OEhYaHiImKi4yNjo+Ck5SVlpeYmZ qbnJ2en5KjpKWmp6ipqqusra6voRAAICAQIDBQUEBQYECAMDbQEAAhEDBCESMUEFURNhIgZxgZEy obHwFMHR4SNCFVJicvEzJDRDghaSUyWiY7LCB3PSNeJEgxdUkwgJChgZJjZFGidkdFU38qOzwygp 0+PzhJSktMTU5PRldYWVpbXF1eX1RlZmdoaWprbG1ub2R1dnd4eXp7fH1+f3OEhYaHiImKi4yNjo +DlJWWl5iZmpucnZ6fkqOkpaanqKmqq6ytrq+v/aAAwDAQACEQMRAD8A8+YVfSv5af8AOMXk3zF5 J0vXdW1W/a71KIXBSxkgSJFb7MfxxTMWX9rfrtTbArDPz6/JXQfy9t9KvdG1C4uIL95IXtr0xtMG jAbmjRpECu9COOxpvvsq8z0XRUu0lv7+U2uj2pAubkCru53WGFT9uV+w6AbnbIylWw5sox+Sq+ta Bzb0/L8AjqeAe4umanbkVkUE+NAMHCe9eIdzX6a0T/qX7b/kfd/9VseE9/3LxDud+mtE/wCpftv+ R93/ANVseE9/3LxDuVfqWnf4o9H6sPqXD1vqvN+NPq/q8OVedK+9cbPCmhaGNhpEFlZTXc1x6t5E 03GJEKqBNJDSrMD/ALqrhsklFBNdJ8432j2v1TSPMWuada8i/wBXtJ2gj5HqeEcyipx3RshtV123 1m6juNb1XVtUljAQSXTiaQJWvFXlkcgY+pOyX61rT6i8UccQtdOtQUsbFDVIkPUk/tu/V3O5PtQB jGveiUrS3JodirsVZJ/01X/Rv/2J5V/D+O9n1S/V/wDjn6J/zBP/ANRtzko8z7/0BB5BK8mxdirs VdirsVdirJP+mq/6N/8AsTyr+H8d7Pql+r/8c/RP+YJ/+o25yUeZ9/6Ag8gleTYuxV2Kq1naT3l1 FawLymmYIi+5NMjKQAss8cDOQiOZekwfkF5rnhWaOWMowqpKlSfkGIOURzyIsRLmT0cImjkjfx/U wjzR5Y1Dy7qP1K8+IlQySAEA9iKHoQcsxZRMdzRqdMcUgCQQRYI5FGf9NV/0b/8AYnj/AA/jvauq X6v/AMc/RP8AmCf/AKjbnJR5n3/oCDyCZ+SNK0S/uZf0pV0Qp+6VuLcCTyZdxuMxtVllGqdn2Zps eXi4tyOQSfXoNPt9ZvIdOdpLFJWFuz0LcOwJG1R0zIxSJiCXA1MIxyER5IDLGl6N+R1jpVz5vhe8 YGVGAijbpQg1b33AX6ffMbPziOhLn6MAQySH1iO3x5lKfzL8/wDn6Dz9fRLez2f1aVVtbaPZSooU PAg8+Xv8syHXs/8AzejhvvJWjalqqiDWXgDyD9r1KqOJHXepG/hXMeW2QV15uxxAS08uL+Ejh955 h5p/01X/AEb/APYnln8P473C6pfq/wDxz9E/5gn/AOo25yUeZ9/6Ag8gleTYuxV2Ko3RtVudK1KC /tmKywMGBU0NO+QnDiFNuDKcchL8EdXrH/K7NAnKT6josV7qMX93eMnBgR+0VBoTXfamVDxK6OVM aYysGYHdQ/WwLz552u/NOorPIxEEYpHHTiq+yqCaBRsMljgRZlzLXqc0JARxioD5k95U/wDpqv8A o3/7E8P8P473H6pfq/8Axz9E/wCYJ/8AqNuclHmff+gIPIJXk2LsVdiqvZfVfrtv9b5fVPUT6xw+ 16fIc6e/HAeWyh6PLcflharLcXlpaXUsZfhaWDTmN4PrCCGjPIjCUxepyJOw4kgtmLWQ8i33Bgut tpLrp7adGsNbRfrcasz0nEjhiS3cqFO2ZEb3tqlXRMP+mq/6N/8AsTyP8P4709UFqUUk1poMUSl5 JLRlRBuSzX1wAB88lHmff+gIPIPVbP8AJLynbaTa3Gv6pcWdzKimYiWFI/UPUIDE5p2rXfJsWP8A 5kflTZeXtIh1bRp57q0DcboysklFbZHUxom1djXxGKvM8VTLy7od1rms2ul2w/eXDhWelQiDdnP+ qMVexy/kj+X8E0dvc6vdQ3Uv93btPBzb/kjirz38zPII8panCtq0kum3KVhllKs4dftKxUKp8VNO nyxVAf8ATVf9G/8A2J5V/D+O9n1TDy3e6fZax5Xnvk5Ri0kWNiaKkjXlyEY18Pw69slHmff+gIPI J/8A85AeW/NOrazp2oabbTX+ktbKkSW6mTjJX4m4LU7rxFadskwZH5fhn8t/k4LfzWpJcScLSQ1c RPWkfzIIA8OnbFLwo0qabDsMKvSfyM1LSbTzO0d2oFxOFEUrdOAqWQfM0P0YqkX5meSPPtx5/vJV srm8N1KGtLqIMyBNuAMn2Up7keOBD0b82LmCy8h6bpWrt9Y1f0Y1O/xCdTUyVp2WtfnTFLzD/pqv +jf/ALE8r/h/Hez6pfq//HP0T/mCf/qNuclHmff+gIPIMssPzX86aHZwWdOIMUciGTcujCqP8Vft A12yQNsaSPzX581vzMEF+2yNyIBPxHoNum3thVjeKq1pdTWlzFcwNxliYOje4xVn1v8Anh5vt4li iZQiCig/EQPmQTirEfMfmTUNfvhd3rVYLxVakgeJ38cVR3/TVf8ARv8A9ieVfw/jvZ9Uv1f/AI5+ if8AME//AFG3OSjzPv8A0BB5Blkl/ouoWGnwanqWkyW8FnbxRQTrqK3VuUjUOqz21rIm7AnixdQS dq1yiiCaB+z9bZYI3I+1IPMun+Vbe2il0W+W5kZyssKyzTcV415Vms7DqfDlluOUjzH4+ZYSA6fj 7GPZawTbyprkmheZNN1dWlVLO5ilmWFijvErgyR1qNnSqkHY13yvJDiiQyhKiCy5PzTSTRINNvor i5kiDO11JK8jtM91cTMSryGP+7nUcwoeooWK0GU/l6lY/GwbPF2pK/Ovm3R9c0+zitIriOeCR3Mc vH0YI3VQLeCjueCldtl9xWpM8WMxJtjOYIQf/TVf9G//AGJ5L+H8d6OqhNp9zqI8uWNqvKe4tWjj Hapvbnc+w6nJR5n3/oCDyD1/UtM/KPyXp9haeZIbc3jxgcmhMsrkCrOwUOwqTXpTJMUn/MLyX5Y1 LydB5l8owxCCGsjm3XiJIv2+Sj9pKV+VR1xV43hVP/I/liXzJ5ittOAP1evO6cdolO+/i32Rir1/ Wbn8jtD1X9EanDZx3y8RIqwF1Qt05MAVXY/tEfdgVh35w+RrHSpLTWtGiRNLu1CSJCKRq9PhdR4M Nj7j3wqxb/pqv+jf/sTyr+H8d7PqitH1xdFv/Ld86hohZSRykipVXvbkFh7j+zJR5n3/AKAg8gzr 81Py01Pz3e2XmHy7cRTf6OtvNbSMRx4ktUcQ29XP0UyTFG8Ivy1/LMaVdTx3WqyOztEp5J6khJVR /k7/AEgeO2KvCyamuFWe/k95qg0PzIkVyqiG7Zf3lNw61ABPWh5H6cVTLzr+RfmTWvNVxqmkXNvN pmoOJfWkchkBABqFBB9t/wCuBCc/mtrllo3lWw8q28i3VxHAttK5oQFjIJb/AFqgD5/LCl51/wBN V/0b/wDYnlX8P472fVL9X/45+if8wT/9Rtzko8z7/wBAQeQTjyf5k1xb+OyW7dbaO2uSqAKCPStp HT4gOXwso74zJAWIspFqeuarqnD69cGb0ySlQq7t1PwgV6ZNigMVXKzKwZSVZTVSNiCMVZot3+aE cJ4euI2iW4ZFSI/un4cXZQK0b1VpUd8h4ke9lwFjGuSau2pzR6vzF/ATDNG4CshQ0K8RQChyQNiw xIpNf+mq/wCjf/sTyv8Ah/Hez6pfq/8Axz9E/wCYJ/8AqNuclHmff+gIPIIjybHJJroWNS7fVb08 VBJ/3kl8MGXl8vvWHNI8sYuxV2Ks40v8yfN1vdy6rb263FvaWkFm8bo8ttDEiRQqWFSoMjQqfi2L dMx5YIkV5toyS5sT1fUp9U1O61GcATXcjSyBa05OanqScujGhTWTZtOP+mq/6N/+xPIfw/jvZdVP 6rFct5djnhuJ7UWjvdpZqHn9BL25aVowarVUBNTsO+N1f46Ba5KnlTzhpFt5jsz5iFxceXtOtry2 tIIfgmUTJKY6tE0LH99Jyb4um3TbJCA+bHiKX6XqM2sWq6XfC6u5LC1lXRILSOM8XMnrSerRebRh S7E9R8sBFGx15pBvZK8sYo/Tra0e3vrm9huntreBuE1qoKpcPtD67MKCNiDXv4ZCRO1JAR8XnG0v dH80vrpmuNf1SOyXS54hwiV7edDL6qRtGhHoJxWqNv4HfGMAOSmRKGnvZNbsLrVLpbm41iKWIXVw kaC1S2EYiQvwUcX5BVHY/PABwmuiSb36o/8A6ar/AKN/+xPB/D+O9PVTN0lt/h2WWe4t7c2bpcyW jcZ/Re8uVlCVKirISKE0PfGrv8dAt8kh1XQr20WG79Jlsr3m9k7MhZkU/tBSaHcdcmJXsxITHS9P uNHtl1S8a6s3vraU6NPaOgLsH9GQSEMGWMjmrU3PyORJvb5pArdLMsYo7T7m2S3vrW7nuo7a5gPG G2YBJJ03h9ZWIBRST7jtkZDlSQUu1XQtT0u/lsL2L07mHj6iclanJQw3UkfZYd8YyBFhSKTiaxm0 OwutLu3urXV5ZIvrVorJ9We2aMTJ6hRiWcMUZRSn05EHiNjkkitkf/01X/Rv/wBieD+H8d6eqX6v /wAc/RP+YJ/+o25yUeZ9/wCgIPIJ7dfljr0EULNNC8lxZfpC0hBar2/CJyQxAQENPx4k1qCenEms Z4n50yOIpZ5m8maz5ddvroie3+sz2kVxFLG4eS2bjJ8Ab1Fof51HbJY8olyRKBikOWsGSeUfI2pe Z4b2Wznih+pvDGwlEhq06yspqiuFUegeTNQDKcmYQq2cMZkiv+VdahHZ2N5f3sFlFqNnJfQGRZmP CFPUdW4I9G9Iq48QwweOLIA5FPhnqsv/AMvb2ytpZZL+2a4S3e8itF9X1JIIwhd1PDgKczsWr8J9 qkZgTyU46UP+mq/6N/8AsTw/w/jvR1S/V/8Ajn6J/wAwT/8AUbc5KPM+/wDQEHkHS+aPMEtq9rLf yvbyKEeJjUcRGkQA8BwhRdv5R4YjHHnS8RW6t5j1zV1jXU7yS7ETO8fqUJDSMXc1p+0zEn3xjAR5 BTInmluTYo2w1jVNPUrZXLwK0kczBDsZIgwjY+6iRvvyJiDzSCQiLjzT5iuYvRuNRnlhAZVjdyVV Wj9JlUHZQY/hoO2AY4jokyK6Xzb5jmsZbGW/le1mHGVDSpX4fg5U5BT6a1UGhpg8ON3S8ZRv/TVf 9G//AGJ4P4fx3p6pfq//ABz9E/5gn/6jbnJR5n3/AKAg8glZIHU0ybF2KuxV2KuLAGhO56Yq7FWS f9NV/wBG/wD2J5V/D+O9n1S/V/8Ajn6J/wAwT/8AUbc5KPM+/wDQEHkEmuPsj55JiqL9kfIYVbxV 2KqMv98v0frwKrYVZJ/01X/Rv/2J5V/D+O9n1S/V/wDjn6J/zBP/ANRtzko8z7/0BB5BJrj7I+eS Yqi/ZHyGFW8VdirK9E0PTLnSo5p4Q8svLk5JqKMQKeHTArFMKsk/6ar/AKN/+xPKv4fx3s+qX6v/ AMc/RP8AmCf/AKjbnJR5n3/oCDyCTXH2R88kxVF+yPkMKt4q7FWW6FrGm2+kxRTXCxyR8uSMfi3Y kUHfrgViWFWSf9NV/wBG/wD2J5V/D+O9n1S/V/8Ajn6J/wAwT/8AUbc5KPM+/wDQEHkEmuPsj55J iqL9kfIYVbxV2KqMv98v0frwKrYVZJ/01X/Rv/2J5V/D+O9n1S/V/wDjn6J/zBP/ANRtzko8z7/0 BB5BBW2kX2o8haoGEe7sSABXoN8kxU5YJbeQwzLwkj+Fl8DhVZirsVUZf75fo/XgVWwqyT/pqv8A o3/7E8q/h/Hez6pfq/8Axz9E/wCYJ/8AqNuclHmff+gIPIJr5N/urr/WT9RyTFJ/MH/HYuf9Yf8A ERiqXYVdiqjL/fL9H68Cq2FWSf8ATVf9G/8A2J5V/D+O9n1S/V/+Ofon/ME//Ubc5KPM+/8AQEHk FHTdXu9P5+hxKyU5K4JFR0OxGSYoa5uZbmd55TWSQ1YjbCq0RsRXp4VwKtKkGhwq0VBNSNx0OKux Vkn/AE1X/Rv/ANieVfw/jvZ9Uv1f/jn6J/zBP/1G3OSjzPv/AEBB5BM7/wAk3bQWc2i8tSea0huL uzi+O5heSISN+5ADtHQ1DKCB0JqMgMo3vZJh3Mdntbm3bjPC8TA0IdSpr9OWgsKU7qKeRo2jf4QR tTp74qvlr8IJ5MBuemKsi/5V15rKBktkcm3S89NJY2cQyenwYqGrv66be+VeNFn4ZSPVNNvNL1G5 068QR3dpI0M6AhgHQ0YVFQd/DLIyBFhiRRpOv+mq/wCjf/sTyH8P472XVL9X/wCOfon/ADBP/wBR tzko8z7/ANAQeQVl8zyhIFOn2TtBGkSyvEWciNQoYsW67YODzK8TWs+adR1a0itbpYxHA5ePhzBB IoR8TMKfRjHGAbUyJScMR0JGWMXYqyWz/MbzbZ3630N4RMlvHaRKRySOKONIwEQ/CpKxLyp1OUnB EiqZjIQkOoX1xf3s97cEGe4cySECg5NuaDLQKFMSbTz/AKar/o3/AOxPK/4fx3suqX6v/wAc/RP+ YJ/+o25yUeZ9/wCgIPIJXk2LsVdirsVdirsVZJ/01X/Rv/2J5V/D+O9n1Q0eo+X5rCyh1C1u2ns4 mhD280aIytNJMDxeKQ1/e064eGVmkWOqcaT5RXWLX63pHlfzDqNryKfWLRfXj5DqOcdqwqMfV5L6 UJq+j6To1wtvrGh63ptw680hu3SByviFktlNMal5L6UD63k3/lk1H/pJg/6oY1LyX0q8Vv5al9L0 tM1aT124QcZom5t4JS3+I/LBcu8fj4p27iuey8voZQ+k6upgPGYGWMcDStGrb/D9ONy7x+PitDuL pLHQI1LSaTq6KKVLSxgfEaDrb9ztjcu8fj4rQ7iofpGL/E/1n6pP6VfR+p8h6/H0vR48uFOdP8n6 MNelF7pHljF9Kfln/wA5O+TvLvkrTNC1bSb5LrTYhb87FIZIpFX/AHYfUlhZWatWFDvvXArDfz6/ OvQvzCttLstG06e3gsHkmkub1Y1mLOoXgixvKAm1T8W5pttirx3Cr0LSPzE0vT/LlhpQF8ZUWaO8 mDJVBLDNCjWp5fB6Xrk8aDlVqt0piywEyJ2bhkAFOvPzSEdmLbTYJCwVYGurs85XhFmto7HiwXmw DfaDACnfEafff8b2py9yY235x2i6nrtxcWDy2up3UVxbQ/D8ItzNLF6oLEEid4mNNiFOROlNDfkE jNuWLf4us/8AlZP+K/Qk+qfpL6/9X+H1OHq+px68a098t8I+Hw+VMOP1X5v/2Q== uuid:591fa095-383a-1c4f-a354-3f1d14514891 xmp.did:27d1e5f2-afdf-4ff9-86ba-2f173e57ed0f uuid:5D20892493BFDB11914A8590D31508C8 proof:pdf xmp.iid:e7cbd5b8-7cd9-4976-99c8-86f54650e30c xmp.did:e7cbd5b8-7cd9-4976-99c8-86f54650e30c uuid:5D20892493BFDB11914A8590D31508C8 proof:pdf saved xmp.iid:ac9a98af-b05b-4cae-bce9-d1299bbc531e 2020-01-30T12:41:26-06:00 Adobe Illustrator CC 23.1 (Macintosh) / saved xmp.iid:27d1e5f2-afdf-4ff9-86ba-2f173e57ed0f 2022-09-28T12:46:18-05:00 Adobe Illustrator 26.0 (Macintosh) / Print AIRobin Document Adobe PDF library 16.03 1 False False 30.000000 128.500000 Millimeters Cyan Magenta Yellow Black Default Swatch Group 0 White CMYK PROCESS 0.000000 0.000000 0.000000 0.000000 Black CMYK PROCESS 0.000000 0.000000 0.000000 100.000000 CMYK Red CMYK PROCESS 0.000000 100.000000 100.000000 0.000000 CMYK Yellow CMYK PROCESS 0.000000 0.000000 100.000000 0.000000 CMYK Green CMYK PROCESS 100.000000 0.000000 100.000000 0.000000 CMYK Cyan CMYK PROCESS 100.000000 0.000000 0.000000 0.000000 CMYK Blue CMYK PROCESS 100.000000 100.000000 0.000000 0.000000 CMYK Magenta CMYK PROCESS 0.000000 100.000000 0.000000 0.000000 C=15 M=100 Y=90 K=10 CMYK PROCESS 15.000000 100.000000 90.000000 10.000000 C=0 M=90 Y=85 K=0 CMYK PROCESS 0.000000 90.000000 85.000000 0.000000 C=0 M=80 Y=95 K=0 CMYK PROCESS 0.000000 80.000000 95.000000 0.000000 C=0 M=50 Y=100 K=0 CMYK PROCESS 0.000000 50.000000 100.000000 0.000000 C=0 M=35 Y=85 K=0 CMYK PROCESS 0.000000 35.000000 85.000000 0.000000 C=5 M=0 Y=90 K=0 CMYK PROCESS 5.000000 0.000000 90.000000 0.000000 C=20 M=0 Y=100 K=0 CMYK PROCESS 20.000000 0.000000 100.000000 0.000000 C=50 M=0 Y=100 K=0 CMYK PROCESS 50.000000 0.000000 100.000000 0.000000 C=75 M=0 Y=100 K=0 CMYK PROCESS 75.000000 0.000000 100.000000 0.000000 C=85 M=10 Y=100 K=10 CMYK PROCESS 85.000000 10.000000 100.000000 10.000000 C=90 M=30 Y=95 K=30 CMYK PROCESS 90.000000 30.000000 95.000000 30.000000 C=75 M=0 Y=75 K=0 CMYK PROCESS 75.000000 0.000000 75.000000 0.000000 C=80 M=10 Y=45 K=0 CMYK PROCESS 80.000000 10.000000 45.000000 0.000000 C=70 M=15 Y=0 K=0 CMYK PROCESS 70.000000 15.000000 0.000000 0.000000 C=85 M=50 Y=0 K=0 CMYK PROCESS 85.000000 50.000000 0.000000 0.000000 C=100 M=95 Y=5 K=0 CMYK PROCESS 100.000000 95.000000 5.000000 0.000000 C=100 M=100 Y=25 K=25 CMYK PROCESS 100.000000 100.000000 25.000000 25.000000 C=75 M=100 Y=0 K=0 CMYK PROCESS 75.000000 100.000000 0.000000 0.000000 C=50 M=100 Y=0 K=0 CMYK PROCESS 50.000000 100.000000 0.000000 0.000000 C=35 M=100 Y=35 K=10 CMYK PROCESS 35.000000 100.000000 35.000000 10.000000 C=10 M=100 Y=50 K=0 CMYK PROCESS 10.000000 100.000000 50.000000 0.000000 C=0 M=95 Y=20 K=0 CMYK PROCESS 0.000000 95.000000 20.000000 0.000000 C=25 M=25 Y=40 K=0 CMYK PROCESS 25.000000 25.000000 40.000000 0.000000 C=40 M=45 Y=50 K=5 CMYK PROCESS 40.000000 45.000000 50.000000 5.000000 C=50 M=50 Y=60 K=25 CMYK PROCESS 50.000000 50.000000 60.000000 25.000000 C=55 M=60 Y=65 K=40 CMYK PROCESS 55.000000 60.000000 65.000000 40.000000 C=25 M=40 Y=65 K=0 CMYK PROCESS 25.000000 40.000000 65.000000 0.000000 C=30 M=50 Y=75 K=10 CMYK PROCESS 30.000000 50.000000 75.000000 10.000000 C=35 M=60 Y=80 K=25 CMYK PROCESS 35.000000 60.000000 80.000000 25.000000 C=40 M=65 Y=90 K=35 CMYK PROCESS 40.000000 65.000000 90.000000 35.000000 C=40 M=70 Y=100 K=50 CMYK PROCESS 40.000000 70.000000 100.000000 50.000000 C=50 M=70 Y=80 K=70 CMYK PROCESS 50.000000 70.000000 80.000000 70.000000 Grays 1 C=0 M=0 Y=0 K=100 CMYK PROCESS 0.000000 0.000000 0.000000 100.000000 C=0 M=0 Y=0 K=90 CMYK PROCESS 0.000000 0.000000 0.000000 89.999400 C=0 M=0 Y=0 K=80 CMYK PROCESS 0.000000 0.000000 0.000000 79.998800 C=0 M=0 Y=0 K=70 CMYK PROCESS 0.000000 0.000000 0.000000 69.999700 C=0 M=0 Y=0 K=60 CMYK PROCESS 0.000000 0.000000 0.000000 59.999100 C=0 M=0 Y=0 K=50 CMYK PROCESS 0.000000 0.000000 0.000000 50.000000 C=0 M=0 Y=0 K=40 CMYK PROCESS 0.000000 0.000000 0.000000 39.999400 C=0 M=0 Y=0 K=30 CMYK PROCESS 0.000000 0.000000 0.000000 29.998800 C=0 M=0 Y=0 K=20 CMYK PROCESS 0.000000 0.000000 0.000000 19.999700 C=0 M=0 Y=0 K=10 CMYK PROCESS 0.000000 0.000000 0.000000 9.999100 C=0 M=0 Y=0 K=5 CMYK PROCESS 0.000000 0.000000 0.000000 4.998800 Brights 1 C=0 M=100 Y=100 K=0 CMYK PROCESS 0.000000 100.000000 100.000000 0.000000 C=0 M=75 Y=100 K=0 CMYK PROCESS 0.000000 75.000000 100.000000 0.000000 C=0 M=10 Y=95 K=0 CMYK PROCESS 0.000000 10.000000 95.000000 0.000000 C=85 M=10 Y=100 K=0 CMYK PROCESS 85.000000 10.000000 100.000000 0.000000 C=100 M=90 Y=0 K=0 CMYK PROCESS 100.000000 90.000000 0.000000 0.000000 C=60 M=90 Y=0 K=0 CMYK PROCESS 60.000000 90.000000 0.003100 0.003100 endstream endobj 3 0 obj <> endobj 5 0 obj <>/Resources<>/ExtGState<>/Properties<>/Shading<>>>/Thumb 43 0 R/TrimBox[0.0 0.0 85.0394 364.252]/Type/Page>> endobj 37 0 obj <>stream HWn$WL2}%D %vH<ݳ_]NLU;~yޞ^Ï[r+VFS}?q5mo[ڻLl?궽ٖmo?6ْɦuWuUvۗ|>sowI{)~.75 @enoʶ=uJio>t%\=k)/OD<ti^ܰҮW9]zEiG?p;~EtX|LCUӸ6Z? tϽt{8~eC!>U"ELa0a~]={[[X=լ.,F8Y2V NiVb-4p/"jk O%ܪ̤@|?ƪCQ1  -b+|*_{ K犟<RKݧjai?.wt>c;2dTv1kL)}Gf !r</lNncq؋|rx"'t~ُP;.Y{ 9M<!9C[}܃C(U8X-Xjsb,k5gfJSs2֪_jEr,˿7oTչ'I"8ů;2=rs~X((nQ3V+-f[ڛlL[4$=}];dR߇ +Vr+_(\?Ư髱 xAowr4|9JĘ+"A?)zJ4Y{HIF"zROHqT\,vŮKl5j]DlѶ5m½e%G=`!O*!MF% U?jyInsDuʾ'[ u"^UZcspW|L(]F0R1e߬N=1&L.p֛ ;D:uU˨vK'>UgG_hC@Wn'LCD=-r 6PoOIYfB `9ZQ兖N9 ;fȑ251kPܚ9hKGTuF ~^O:/DG'2ޅr`4CY^ZCEߏ>FQ_x@%> X+38$k*7nXĈ‘zA=<5*)~D$\3ߵk!&3˽NHeш^p'J7)wyց3,SZ6`dy)HGLؑ2c5*$ŘCAf)8 eNqilI4&'F٢&ӃѝedTb\xeqs2d<ր"cJ3^/ ͨ-aӵձZ"(=Ǽ˴"zFhlXm )}Z˫ ,F>N懡3)A0Y]  2̱Hb@kf4 b0GE(׵jZAHhϧE̹kQ8m=_= K˓6s=ab5CGoWG(U<8%Ξ% 3sL G s>ElT)񨉻GGy4VS`<4rʭ*!ɽ1CMQ(i&Iyy߸zTR3_'3&&#epP[dx /!*( 8 h E ?_tn$R&X=R:4k紭Hٯ$ WTEOHT[\i e43vk6| g>zkfH2nX%Bc4 6;[vJHlm$W0 ' iSQ-=G fא[(|9vOF&C,M_2v{2oEZ͋!v|W# uf9ѐ62.48<,E`VS"Zpy%x5յ^VEG~L\#!\/Ꚍjx&i5!%Y 38ɦ|YQqj.͝w>KʱMG0gؓ߼]xj KpS4ZHPڅ" Z8 ]:J2q] 3z:|q34=d= CB.C2ʫe~RG:a-+?qή5Z_At@W(|$p{co8'!qe oM) R]mx.woIeCRд1[ dzKBӥ#P$ b':ETMV,a&Yp ̼t޽eYE-i²2fm&3xcY%^Qx-hT[cBF2OPZLFZo@dwWV"mzH;ޗ[E=yl )I(^bwC,nuͭA}y8ƛ6#Išmi4M o֦ uЪ8=ttALq#\7ߩzИByp=}/_}&?Cw |w܉g.L-Gޣ{ėg|Mԯsx_c_VSS@ 1Fc,[;r)rQ˽)o_wrfXz;:zB`' pXɆȒ/Jvy\r3h6ECJ9S6CQšI1ĚwzHgUN[*wlťmjӤSJIQ6<.֫s \*><1TŰ72žzd͒y{5<ղ=ygzDx#UH3x眠ڌ!0Ro..7T-=au5C˰N!lM|?Kyp ᪔g\mb=^'H= @tDXxkeiCeL+ASOt0mYq=ӯ 爄 xY5=b.15os3vEht;DVZẎv=΋pek<ۘHWtbsQ'P?͕şRSJO)~g4*{KY0V,ۤb7 SY1cGMj([9Q0c1tfZa =İzRWG/Ӗ%@-yFQ3(T+hjz=bĚ5բrH1a)ό %<|zagDgFH虑H6p^"$frI(&13O1]J? .^vdIPtbGZO ((&BHHO <.Vwl z?.ShhZqjC0KCH<>HKO4*?GXw#;/X-#I+ 9r'W֪eφڛ?}lE׶Lgk=fʱM6@mYwRZJd8mNQo[_Э#֜66<>Sg:.T/H77%oJOߠcy2hF֙kpZ>5tƈ⮄Cb zRhcƎMANod腱DP;3:@nv҄CZhL|9̄NMf2  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JݭR3z dw7D*4X4̺P2_kF:'+~q͕~֍(7G.m/,旫_ q΂]"Zh#(a{ϭꔊ޸mM|?`2_VhV2Fΐb0AmK=:} >j &_L:`}d6|!#/#yy˦c]m.v8Ss;ͦy*ӧzLxs"ƥ^KKUEX#Tg=^&%a3hq8,*Ug&oy%>~Yhk' PYei=~!O}tڿxߩgQ*<=eF#/ǟ^W>!FfwZN>n 2Upm{$qK |} + 9%'?#ݕh ٮ^uNlGaԷqb>y۞VkFc a(z_] u*˜b:K4NeS.oV7Ӄ6z㰴Aִ@ؕ9L}ݥ6\FJȸ`W#y8P[ZI𪶭`7Xm*[C=Xͼu4|iuo֥yLQ\4_-Xh% an8 ^D(rȇt덤N_=LK/6!C3]sxόxv=HCQA8J KQ 6q[ǠnQ6% n2^ 1`Ǽa9=S.^Mx;G/1uO):}|Q~U҂YrJ%ǹrPJmĬbPbm~w.0jz/ut!si\4's&ܷs!1' [a+|XI̍] ޢ1<)W#<$?XOrj.\vqb` Z/Υ<~')V97܇9X9'"O9ȹu{C {vl 쒊‘-uGFe%Gm0me 7Y_f~eլ[׋SL_ t۪VYoDM~|v,gɿLGrd, xcM[QRNkiJѿ|{@3z35Dk҈=-{8:lO\ )t20 ɽy. }Qc&}L{@dTgDU|HQjYKᙇeS`qWLNhhJԢSc(L'x79Οs^(s"r ᘯcJ5W^R7Dvmꕏ/T||j~qI endstream endobj 43 0 obj <>stream 8;V.Y_%FR-$tCCHj1[QC-L`/&Y:m5??6&91L60TT!R:tAKIoHIN5buT.YA]@J[K`s aaJ]1i"r=QJPFpSZF;::FroN2X8TmHls Qc%eM(3:DILc1GF6dI3.([g;9qbX,tY`0][-=*LnHI);LpVN=Mc@C*$mTs+ffcPDF F,D_n>ipD0O)*'SWdb*NdtaiP~> endstream endobj 44 0 obj [/Indexed/DeviceRGB 255 45 0 R] endobj 45 0 obj <>stream 8;X]O>EqN@%''O_@%e@?J;%+8(9e>X=MR6S?i^YgA3=].HDXF.R$lIL@"pJ+EP(%0 b]6ajmNZn*!='OQZeQ^Y*,=]?C.B+\Ulg9dhD*"iC[;*=3`oP1[!S^)?1)IZ4dup` E1r!/,*0[*9.aFIR2&b-C#soRZ7Dl%MLY\.?d>Mn 6%Q2oYfNRF$$+ON<+]RUJmC0InDZ4OTs0S!saG>GGKUlQ*Q?45:CI&4J'_2j$XKrcYp0n+Xl_nU*O( l[$6Nn+Z_Nq0]s7hs]`XX1nZ8&94a\~> endstream endobj 41 0 obj <> endobj 42 0 obj <> endobj 39 0 obj [/DeviceN[/Black]38 0 R 48 0 R 49 0 R] endobj 47 0 obj <> endobj 50 0 obj <> endobj 38 0 obj [/ICCBased 51 0 R] endobj 48 0 obj <>stream {1.000000 2 1 roll 1.000000 2 1 roll 1.000000 2 1 roll 0 index 1.000000 cvr exch sub 2 1 roll 5 -1 roll 1.000000 cvr exch sub 5 1 roll 4 -1 roll 1.000000 cvr exch sub 4 1 roll 3 -1 roll 1.000000 cvr exch sub 3 1 roll 2 -1 roll 1.000000 cvr exch sub 2 1 roll pop } endstream endobj 49 0 obj <> endobj 52 0 obj <> endobj 51 0 obj <>stream HuTKtKKJI,t(݋4K%ҹH4J#Ғ(H wqyy~3̙g<3Y9El @ ]!O-@\+BVKK :OX~WCaiHKL0qY `5ck X]x= 8 XĿ׽>.f#aPn D^{y8  dp H st:Y׬cxc IV?S!:_9[YbQP~+rA ShHht^ '0߅™kYXY9Yqqpl'WzEE$%D>,^|t*K)%/`\ҫ:&D [7dplDa5|mb4,yy{e5 3⚅,t+whlA   m k xYUH&%Ȥ qO'Mz3KT@v[NUnn^\o]abTrtlmE]e~U+jאZ:zaqi5};CS[\_ۆwCaQ1;>L$Lz}4:%8M7l̎Χ/}XT^]X>\Ym[n!ycskkƶʷ;v{pIs0Xݯ3s󝋒&$WWW*)!$$%!e$cHNOAKIMEq ƕ;KLw@YX;ؚ8^+DspfKOTCPpJ%D=++O%$*8IZ\Z^UK_wL"dx]}>9=;s_G8/̹N!Gz[<=2|B}PQzlH0Wc(Een|Pds::5&89yFT"od䳔i/ZK^&gd:fgQl kJХeJ*+篍kj5U[ZUh0|em6]B@`PpH?QM1Msψ*iϛ.Z [JYZ)X-]R޸Ѻپw?@?5 ǖ'vNg W3gLC#u!MMMEvAms˔FVNA̝GLwA̬,llؿsݛnͽ+!B²" 'R&k?3?4+:6oT\ұڿ6VʝoF?LT;:>::>:;eqvx^sawݥʕ'_EFO\DKLtAnFF)F|ԭ6\`@z?m+F;LwiAhy͖)Mgw~_ @ZH_XA,"F)%/*9aZ:Q,\B^_AU񡒀2 *'[j o5[uR1uh`fm$1xJgBdrltlyyEe$feg-g#`dGbwj0TOC9; ܨݿxz6zx8IP=A!.aAxۑϊ}bG-ޒēx`G/Ԝq_O?0"۬խЮ˯ǰı²µŶȷ͸ӹۺ 0@RfzƏǦȾ *GcЀџҿ'LsٛFsM6+1MZ:{T?~ò~i~L}~cbA~Dad~ty~W~O>~\/~|~`Cx}%H}1X}%z}K} {N}׋<_~7A~-ψ||Dz|+E|[s|z} ^}wO@}-~ċ {Gu{Dz{]Ĭ{f{Zx|[]|ϕM?}R<}Ǝz]YzHħz|z={LNw{\|=>|v|ېI8z/r z;bz'sMzd6zɬqv{D[{0> |;|yyaIy?yazYvzݮ[{^=c{ФI{R*y߄yfUy`VyyuKzZi{ <{z%zȎ~+~}͇}W0}3}HtЄ}Zk}=~zɇ}!~Єd*s}Y<9wpSwuuVrUW؈|;,뇔{RsѲ;:8q)PCV:4.8Ȅ2񡂡?Up Vu9S c bփR.ՁNn U388A/ͬδz6߆өn1T\e7݀tXT)$̯̕6;eCʷˆ imw3SƀV7M \lGNػځNāa5tNzlߴS<H6*-N}o2ن N%է>w֣A}⇤\fXMݘ2, KԐ3g°[} 0e6M _1 ? 1ӣǾI^I|B̯dܪwLe1$: rW] 1S{z|diL g0\ U{[G{!{ ޔ`{&yE{xbie{Jr|/c5}~ ~:f#MKx+Ca|uI~.yW ώәߎ%¡唘[w!^T`^H*- 5GȨ瘎=Π4rv_ҍRGf,ދ̋|,ƕ{ Ҙtٕ^1Fő,;',#h%T,Qۥ{[s:9󅼓&^!Փa@!" y .Jl6mHju,bU6+s hܸd-ʥ}wi-sun=0Ľi-_*)U_ˈb$na+;ϧT;ppA7C4.*Iߥa8Mm.ACi7\j|fiԫ)]ޭjʄU]3(í whJch-4x7h׿*P0H됎L랇ڡuÂ,{Bz}8vggҲd[!XTZZ.vlAg {;Sm`vؿ`~?ga. 3Ì{L^WYe4]L7ok!wI~Ira^=C#Zh`Wu}p)"z7ff&3$FJ8Ҷ5m uR_,^VS&aR~PfLL_Dw*`\-9]q  TI6)>u6 D`e͢/xqY%9ʜ;åOd\˾P&eRz;].R<oΡ]P{?: r̨\ʻb Ҥ3|m s؟W9oZt]RnÅ\cW#+nI&gyAjsN06HiD'@J+a5V~cRI̫vwtUc[3+?F|l(iU^+O?Rs1Hqil$Wþh=(RE 1BvџnF/ BsGMY9>ܖ3ȗqI ڣ5V_1ȣβiJiX0WVH[8g_/ n3 ` 38A.|f|ј0I6bv%& ;Y㿜҄#dD.).p'3J12K[Duɥ$s8IƊ.z^48e!R6}vcMiozo0'=~i,3:?-?oS,9w#ROa; ?pB ֞IO ݟe#}ԯN$\l?], y,>&Рq]yh0AqK)ĝBFҍcH:-h-ǟcf)K9T127]qEjL<>h;|U dpG ƫ`&!8al`83>.qɂnA9 ; `HByg KB*k㰗2fF=#OM eT? mTm_OBۊV<ɆF('n3uG~Ȯ#7Њ9[١`Ns.P..콤 'KnpF\? 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+G[Yu?R|^rrH/坑,~$K]Kn`l=Z5[7q|gUnr"~F8ߛ-cY đ\ೖ-K1Es)`[>zyH]PF(볫ܤ;dqFV Lk-zPߔJK{wWy~P'C8d,ߴ. :J@7 dzqF@` V" 6X ##  ZeWŔԃN~a~qfu#E".lйy.?Xϊ ;m HK=`(tu4G!gn_:^!B@zhCLZ8l$@ + @ e!OAx C8~ⷎNs]=/I֣3ѡM*{q6ljK~!}9Ym!!_7Hlް(Qppj`0GXs,D`+/xGF@ҚSШ s=t##URuMT?|zq+[:sMnִ䂹33o\P7.B *OEtO1o,N4GO\ٞ~pc݌)GR0XQAl(f4 M)h@<׹L"]NJYsr,'%hݹv  ݆/U)|JnPW x kFEQ`0|=t[ 1x}fpc3A&ŽpJ ~ 7%1,۰PRND,^HU0uf>7웻ñ]zQZVq6 S d`0XA#GVJ[(9 RWvHo^0x3 bx p`+gQ(^1ױ>9ږ騬*^x#qb ,Y2aHwcVMOb/f=-ȁ/} - `=瀾}k) 4`" C!)p3:mu@XoQv ngn3w:s+*qBV- M$NreO{}v R` 83JyMO4)XZGyQj{DM {_πY ̸Ӻ|)weUefᨈ.A]]dciI~\w<8/t Pg+e >*7E`S# 3\GHpχHn aKS[K 5uk;mɶcVރ iEHD_+߾U\'9GVXJ¬9M<~̨փI+qijL9%A0pcF"((`77Q#'q h[:-H,n#*Z_YXO =Vy!pLYzY*K;x2}{"w7er"Iw:GSy\V[<6'Rչn%:溬'5mDtbZL\&$ ܾ~vן{}߻<%E&gINDHJ"NƄdD] Q!c@ d *>7 8PW% \ h`3^l:93cM|;egA :܂8XJ[7XI|0|N7w[{EkvcJȬi%J-Q#u|FBѵ<~ԠVTw|_JvV{J,͓ɯ)l/` R|Vxfm 96pL1c3Y0ߜ,/NP[@Qt+eKTe9ۏ-p Ȯ|BpW$ %IHO޿y:~0?_(gD,rE}KcШ+)J_*=I,?!4l=Å[Pծ=Ğ [ }g OZO$o!xL=5dbBC) Oմ>RIr\r"#;@V2[kclzi5a#*Xm?;62.#:ĉ֙Li_8L+ endstream endobj 46 0 obj <> endobj 53 0 obj <> endobj 33 0 obj <> endobj 32 0 obj <> endobj 34 0 obj <> endobj 35 0 obj <> endobj 60 0 obj [/View/Design] endobj 61 0 obj <>>> endobj 58 0 obj [/View/Design] endobj 59 0 obj <>>> endobj 56 0 obj [/View/Design] endobj 57 0 obj <>>> endobj 54 0 obj [/View/Design] endobj 55 0 obj <>>> endobj 40 0 obj <> endobj 7 0 obj <> endobj 16 0 obj <> endobj 17 0 obj <>stream %!PS-Adobe-3.0 %%Creator: Adobe Illustrator(R) 24.0 %%AI8_CreatorVersion: 26.0.3 %%For: (Chris McDowell) () %%Title: (2OPFM_2022_PANEL.ai) %%CreationDate: 9/28/22 12:46 PM %%Canvassize: 16383 %%BoundingBox: 0 -365 86 1 %%HiResBoundingBox: 0 -364.251968503901 85.0391235351526 0.000045656255679 %%DocumentProcessColors: Cyan Magenta Yellow Black %AI5_FileFormat 14.0 %AI12_BuildNumber: 778 %AI3_ColorUsage: Color %AI7_ImageSettings: 0 %%CMYKProcessColor: 1 1 1 1 ([Registration]) %AI3_Cropmarks: 0 -364.251968503901 85.0393700787008 0 %AI3_TemplateBox: 43.5 -182.5 43.5 -182.5 %AI3_TileBox: -245.48031496065 -538.12598425195 330.519685039351 195.87401574805 %AI3_DocumentPreview: None %AI5_ArtSize: 14400 14400 %AI5_RulerUnits: 1 %AI24_LargeCanvasScale: 1 %AI9_ColorModel: 2 %AI5_ArtFlags: 0 0 0 1 0 0 1 0 0 %AI5_TargetResolution: 800 %AI5_NumLayers: 4 %AI17_Begin_Content_if_version_gt:24 4 %AI10_OpenToVie: -217 19 1.94981427717988 0 8273.82625345481 8192.06929849859 1484 907 18 1 0 6 53 0 0 0 1 1 0 1 1 0 1 %AI17_Alternate_Content %AI9_OpenToView: -217 19 1.94981427717988 1484 907 18 1 0 6 53 0 0 0 1 1 0 1 1 0 1 %AI17_End_Versioned_Content %AI5_OpenViewLayers: 7767 %AI17_Begin_Content_if_version_gt:24 4 %AI17_Alternate_Content %AI17_End_Versioned_Content %%PageOrigin:-263 -578 %AI7_GridSettings: 72 8 72 8 1 0 0.800000011920929 0.800000011920929 0.800000011920929 0.899999976158142 0.899999976158142 0.899999976158142 %AI9_Flatten: 1 %AI12_CMSettings: 00.MS %%EndComments endstream endobj 18 0 obj <>stream %AI24_ZStandard_Data(/XLnVE? +PRl+p lU o%VTZMߎfP%Cm 5 CVGJǍ˴PZ:Kt8t{OKA뙶t C#دXRAyIWu:;gi2ɝ[}J,8I$"r.Yvf%Vwl#;oS):`A 8LpLP1$B ,`0  ` \c4 948FA8Iqhձ$|ŷ1%ۣt74 D0Ga 4\ XR!OF֓Ѷ;HŜ/1 P D!q@<zPT*/l@2FqfZ5fɠzVDoTZ$5g,,/D ÉAWd1, D680Zqndʩ>lB@$^AX a$A"FF  EqxHG h l"8Tj-3;"m86T5Z)sT _2Gma_^0 `l:2D6D&)Hj3F"jb3@:b*9ȡQQcl&29юLB15oQHhe2̰hÎƫF ;LcJeQ%ba{*+na$уA? E D(Cws]F8،$8<,e*p#xF =()O(V?C-v1/a7k0 ,7oCe, fR{ah/#kiae2(0@A-c 'W^| a0SYauEB8$y 3*2  q0j0ljab !MJ.&1ɹ9(;a92nNꎚ.uu$6́u9nc-qG X$0Q2ʰP pij3, ca"@C0 gD+g$&a0, gXX: EK4`-33g ĠAAUh&{9Ef2: zD#O#QDD,1εXvnY38c`(C 3^H( 5 `q8 bEˆBHCC.JEG( 6^S-*WVPJPc52Vfvv;1\Wgw;1`Xhxx<*p 8٤tVZ^bf>D*r #gzߍPS:.; Ł`0Sra@ P D"\J}aEW'd d|0(hp*p\@ @K14@1,a-խZ{(*(CKD"#Ӂ -5ٶ/P !ı#CqWuc u=́+8yn}z?gE*2<3ҲIٜd*0<1HXd).qûla KvKC;3+jQJº2 `dq1AҁqAC(PG(4H P@dvR @@@{pA$` 0x"hP"x (Xh0k;.{|7BoͲQ#XD=ਠAB*LBa*@(4\P!  880@ $ 6p@^`B "p &c9"L` Th&D@ XE 880zT (`a  pT  !h,NaG2aQ*i{pͽ+z0AL(0q5\04L!T@(T d`, H8p`QPpB0A ` "h@NG6`  8! &H`` 880>`A C&Lh "4 ,TP! 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J2zl-zl/i@i`Pj:Ox"R$gj5B<$ 3{匩_r예EfRGdch.$j8ε%: *h AJQ'.O qoH"lAZ׀$bhD́9Id`,JVj*G0>r0ΈI @$- e9ۛ+%)E$!8UŖjE7m]DE0!aFvHHG!6`m&6!6J5N @S5aq_)Wu>qªVߩ'XI 15Xϴ3 =[e HY&ri"\kPD]8EOCDVt2a5TX]U] :9"|x+U1>G.+"%TD_2^P2^kFW|:.8[2!j@lj^g!S!iW:Jt٩@JO]CZ Z] T^< ڹceN-i 3O"V($ *J{ 1~C @ O\d\6Ә !Ot84Bs|JipNi}43K0"h-ٟSYDno7ph^{?jÛpq/a&Z@@`peV,>uBZ YC~rƨhAW\{Z] qf46^_; U|qjt4n)`:F .T`VJplaҕ j|ʇ ! N QpcYľK @LUP<+W+CLǝ<(,JЊ+OF~Ki#An'R&O*: gl+WYȇ&kBG~)iҺ 6|IZ" L] $բmYQX )1C,#_Ghh t֩ADqg 8`-x"/BȬ?SQk !j.aq,> G<dNg z#JuGU0t4 #>4BCMQ)P+!|Dg8ŐͿcDŽp .GĖZK6c~uDdUKƛ)$dzCl\рrbj endstream endobj 36 0 obj [35 0 R 34 0 R 32 0 R 33 0 R] endobj 62 0 obj <> endobj xref 0 63 0000000004 65535 f 0000000016 00000 n 0000000194 00000 n 0000046999 00000 n 0000000000 00000 f 0000047050 00000 n 0000000000 00000 f 0000460901 00000 n 0000000000 00000 f 0000000000 00000 f 0000000000 00000 f 0000000000 00000 f 0000000000 00000 f 0000000000 00000 f 0000000000 00000 f 0000000000 00000 f 0000460974 00000 n 0000461395 00000 n 0000462927 00000 n 0000528515 00000 n 0000594103 00000 n 0000659691 00000 n 0000725279 00000 n 0000741267 00000 n 0000806855 00000 n 0000872443 00000 n 0000938031 00000 n 0001003619 00000 n 0001069207 00000 n 0001134795 00000 n 0001200383 00000 n 0000000000 00000 f 0000460111 00000 n 0000460042 00000 n 0000460180 00000 n 0000460252 00000 n 0001265971 00000 n 0000047527 00000 n 0000069425 00000 n 0000069191 00000 n 0000460788 00000 n 0000068905 00000 n 0000069048 00000 n 0000067978 00000 n 0000068344 00000 n 0000068392 00000 n 0000459811 00000 n 0000069246 00000 n 0000069460 00000 n 0000069847 00000 n 0000069341 00000 n 0000069978 00000 n 0000069900 00000 n 0000459906 00000 n 0000460672 00000 n 0000460703 00000 n 0000460556 00000 n 0000460587 00000 n 0000460440 00000 n 0000460471 00000 n 0000460324 00000 n 0000460355 00000 n 0001266017 00000 n trailer <]>> startxref 1266213 %%EOF ================================================ FILE: Production Modules/2OPFM/diptrace/_archive/2OPFM_2022_PANEL.dxf ================================================ 0 SECTION 2 HEADER 9 $ACADVER 1 AC1024 9 $ACADMAINTVER 70 6 9 $DWGCODEPAGE 3 UNDEFINED 9 $INSBASE 10 0.0 20 0.0 30 0.0 9 $EXTMIN 10 1.000000000000000E+20 20 1.000000000000000E+20 30 1.000000000000000E+20 9 $EXTMAX 10 -1.000000000000000E+20 20 -1.000000000000000E+20 30 -1.000000000000000E+20 9 $LIMMIN 10 0.0 20 0.0 9 $LIMMAX 10 12.0 20 9.0 9 $ORTHOMODE 70 0 9 $REGENMODE 70 1 9 $FILLMODE 70 1 9 $QTEXTMODE 70 0 9 $MIRRTEXT 70 1 9 $LTSCALE 40 1.0 9 $ATTMODE 70 1 9 $TEXTSIZE 40 0.2 9 $TRACEWID 40 0.05 9 $TEXTSTYLE 7 Standard 9 $CLAYER 8 0 9 $CELTYPE 6 ByLayer 9 $CECOLOR 62 256 9 $CELTSCALE 40 1.0 9 $DISPSILH 70 0 9 $DIMSCALE 40 1.0 9 $DIMASZ 40 0.18 9 $DIMEXO 40 0.0625 9 $DIMDLI 40 0.38 9 $DIMRND 40 0.0 9 $DIMDLE 40 0.0 9 $DIMEXE 40 0.18 9 $DIMTP 40 0.0 9 $DIMTM 40 0.0 9 $DIMTXT 40 0.18 9 $DIMCEN 40 0.09 9 $DIMTSZ 40 0.0 9 $DIMTOL 70 0 9 $DIMLIM 70 0 9 $DIMTIH 70 1 9 $DIMTOH 70 1 9 $DIMSE1 70 0 9 $DIMSE2 70 0 9 $DIMTAD 70 0 9 $DIMZIN 70 0 9 $DIMBLK 1 9 $DIMASO 70 1 9 $DIMSHO 70 1 9 $DIMPOST 1 9 $DIMAPOST 1 9 $DIMALT 70 0 9 $DIMALTD 70 2 9 $DIMALTF 40 25.4 9 $DIMLFAC 40 1.0 9 $DIMTOFL 70 0 9 $DIMTVP 40 0.0 9 $DIMTIX 70 0 9 $DIMSOXD 70 0 9 $DIMSAH 70 0 9 $DIMBLK1 1 9 $DIMBLK2 1 9 $DIMSTYLE 2 Standard 9 $DIMCLRD 70 0 9 $DIMCLRE 70 0 9 $DIMCLRT 70 0 9 $DIMTFAC 40 1.0 9 $DIMGAP 40 0.09 9 $DIMJUST 70 0 9 $DIMSD1 70 0 9 $DIMSD2 70 0 9 $DIMTOLJ 70 1 9 $DIMTZIN 70 0 9 $DIMALTZ 70 0 9 $DIMALTTZ 70 0 9 $DIMUPT 70 0 9 $DIMDEC 70 4 9 $DIMTDEC 70 4 9 $DIMALTU 70 2 9 $DIMALTTD 70 2 9 $DIMTXSTY 7 Standard 9 $DIMAUNIT 70 0 9 $DIMADEC 70 0 9 $DIMALTRND 40 0.0 9 $DIMAZIN 70 0 9 $DIMDSEP 70 46 9 $DIMATFIT 70 3 9 $DIMFRAC 70 0 9 $DIMLDRBLK 1 9 $DIMLUNIT 70 2 9 $DIMLWD 70 -2 9 $DIMLWE 70 -2 9 $DIMTMOVE 70 0 9 $DIMFXL 40 1.0 9 $DIMFXLON 70 0 9 $DIMJOGANG 40 0.7853981633974483 9 $DIMTFILL 70 0 9 $DIMTFILLCLR 70 0 9 $DIMARCSYM 70 0 9 $DIMLTYPE 6 9 $DIMLTEX1 6 9 $DIMLTEX2 6 9 $DIMTXTDIRECTION 70 0 9 $LUNITS 70 2 9 $LUPREC 70 4 9 $SKETCHINC 40 0.1 9 $FILLETRAD 40 0.5 9 $AUNITS 70 0 9 $AUPREC 70 0 9 $MENU 1 . 9 $ELEVATION 40 0.0 9 $PELEVATION 40 0.0 9 $THICKNESS 40 0.0 9 $LIMCHECK 70 0 9 $CHAMFERA 40 0.5 9 $CHAMFERB 40 0.5 9 $CHAMFERC 40 1.0 9 $CHAMFERD 40 0.0 9 $SKPOLY 70 0 9 $TDCREATE 40 2459698.743634259 9 $TDUCREATE 40 2459698.993634259 9 $TDUPDATE 40 2459698.743634259 9 $TDUUPDATE 40 2459698.993634259 9 $TDINDWG 40 0.0000000116 9 $TDUSRTIMER 40 0.0000000116 9 $USRTIMER 70 1 9 $ANGBASE 50 0.0 9 $ANGDIR 70 0 9 $PDMODE 70 0 9 $PDSIZE 40 0.0 9 $PLINEWID 40 0.0 9 $SPLFRAME 70 0 9 $SPLINETYPE 70 6 9 $SPLINESEGS 70 8 9 $HANDSEED 5 121A 9 $SURFTAB1 70 6 9 $SURFTAB2 70 6 9 $SURFTYPE 70 6 9 $SURFU 70 6 9 $SURFV 70 6 9 $UCSBASE 2 9 $UCSNAME 2 9 $UCSORG 10 0.0 20 0.0 30 0.0 9 $UCSXDIR 10 1.0 20 0.0 30 0.0 9 $UCSYDIR 10 0.0 20 1.0 30 0.0 9 $UCSORTHOREF 2 9 $UCSORTHOVIEW 70 0 9 $UCSORGTOP 10 0.0 20 0.0 30 0.0 9 $UCSORGBOTTOM 10 0.0 20 0.0 30 0.0 9 $UCSORGLEFT 10 0.0 20 0.0 30 0.0 9 $UCSORGRIGHT 10 0.0 20 0.0 30 0.0 9 $UCSORGFRONT 10 0.0 20 0.0 30 0.0 9 $UCSORGBACK 10 0.0 20 0.0 30 0.0 9 $PUCSBASE 2 9 $PUCSNAME 2 9 $PUCSORG 10 0.0 20 0.0 30 0.0 9 $PUCSXDIR 10 1.0 20 0.0 30 0.0 9 $PUCSYDIR 10 0.0 20 1.0 30 0.0 9 $PUCSORTHOREF 2 9 $PUCSORTHOVIEW 70 0 9 $PUCSORGTOP 10 0.0 20 0.0 30 0.0 9 $PUCSORGBOTTOM 10 0.0 20 0.0 30 0.0 9 $PUCSORGLEFT 10 0.0 20 0.0 30 0.0 9 $PUCSORGRIGHT 10 0.0 20 0.0 30 0.0 9 $PUCSORGFRONT 10 0.0 20 0.0 30 0.0 9 $PUCSORGBACK 10 0.0 20 0.0 30 0.0 9 $USERI1 70 0 9 $USERI2 70 0 9 $USERI3 70 0 9 $USERI4 70 0 9 $USERI5 70 0 9 $USERR1 40 0.0 9 $USERR2 40 0.0 9 $USERR3 40 0.0 9 $USERR4 40 0.0 9 $USERR5 40 0.0 9 $WORLDVIEW 70 1 9 $SHADEDGE 70 3 9 $SHADEDIF 70 70 9 $TILEMODE 70 1 9 $MAXACTVP 70 64 9 $PINSBASE 10 0.0 20 0.0 30 0.0 9 $PLIMCHECK 70 0 9 $PEXTMIN 10 1.000000000000000E+20 20 1.000000000000000E+20 30 1.000000000000000E+20 9 $PEXTMAX 10 -1.000000000000000E+20 20 -1.000000000000000E+20 30 -1.000000000000000E+20 9 $PLIMMIN 10 0.0 20 0.0 9 $PLIMMAX 10 12.0 20 9.0 9 $UNITMODE 70 0 9 $VISRETAIN 70 1 9 $PLINEGEN 70 0 9 $PSLTSCALE 70 1 9 $TREEDEPTH 70 3020 9 $CMLSTYLE 2 Standard 9 $CMLJUST 70 0 9 $CMLSCALE 40 1.0 9 $PROXYGRAPHICS 70 1 9 $MEASUREMENT 70 0 9 $CELWEIGHT 370 -1 9 $ENDCAPS 280 0 9 $JOINSTYLE 280 0 9 $LWDISPLAY 290 1 9 $INSUNITS 70 4 9 $HYPERLINKBASE 1 9 $STYLESHEET 1 9 $XEDIT 290 1 9 $CEPSNTYPE 380 0 9 $PSTYLEMODE 290 1 9 $FINGERPRINTGUID 2 {B24D42C5-1104-D64E-3009-0008848BA9CF} 9 $VERSIONGUID 2 {FAEB1C32-E019-11D5-929B-00C0DF256EC4} 9 $EXTNAMES 290 1 9 $PSVPSCALE 40 0.0 9 $OLESTARTUP 290 0 9 $SORTENTS 280 127 9 $INDEXCTL 280 0 9 $HIDETEXT 280 1 9 $XCLIPFRAME 280 2 9 $HALOGAP 280 0 9 $OBSCOLOR 70 257 9 $OBSLTYPE 280 0 9 $INTERSECTIONDISPLAY 280 0 9 $INTERSECTIONCOLOR 70 257 9 $DIMASSOC 280 2 9 $PROJECTNAME 1 9 $CAMERADISPLAY 290 0 9 $LENSLENGTH 40 50.0 9 $CAMERAHEIGHT 40 0.0 9 $STEPSPERSEC 40 2.0 9 $STEPSIZE 40 6.0 9 $3DDWFPREC 40 2.0 9 $PSOLWIDTH 40 0.25 9 $PSOLHEIGHT 40 4.0 9 $LOFTANG1 40 1.570796326794897 9 $LOFTANG2 40 1.570796326794897 9 $LOFTMAG1 40 0.0 9 $LOFTMAG2 40 0.0 9 $LOFTPARAM 70 7 9 $LOFTNORMALS 280 1 9 $LATITUDE 40 37.795 9 $LONGITUDE 40 -122.394 9 $NORTHDIRECTION 40 0.0 9 $TIMEZONE 70 -8000 9 $LIGHTGLYPHDISPLAY 280 1 9 $TILEMODELIGHTSYNCH 280 1 9 $CMATERIAL 347 3C 9 $SOLIDHIST 280 1 9 $SHOWHIST 280 1 9 $DWFFRAME 280 2 9 $DGNFRAME 280 2 9 $REALWORLDSCALE 290 1 9 $INTERFERECOLOR 62 256 9 $CSHADOW 280 0 9 $SHADOWPLANELOCATION 40 0.0 0 ENDSEC 0 SECTION 2 CLASSES 0 CLASS 1 ACDBDICTIONARYWDFLT 2 AcDbDictionaryWithDefault 3 ObjectDBX Classes 90 0 91 4 280 0 281 0 0 CLASS 1 VISUALSTYLE 2 AcDbVisualStyle 3 ObjectDBX Classes 90 4095 91 4 280 0 281 0 0 CLASS 1 MATERIAL 2 AcDbMaterial 3 ObjectDBX Classes 90 1153 91 4 280 0 281 0 0 CLASS 1 SUN 2 AcDbSun 3 SCENEOE 90 1024 91 4 280 0 281 0 0 ENDSEC 0 SECTION 2 TABLES 0 TABLE 2 VPORT 5 8 330 0 100 AcDbSymbolTable 70 1 0 VPORT 5 29 330 8 100 AcDbSymbolTableRecord 100 AcDbViewportTableRecord 2 *Active 70 0 10 0.0 20 0.0 11 1.0 21 1.0 12 0.0 22 0.0 13 0.0 23 0.0 14 0.5 24 0.5 15 0.5 25 0.5 16 0.0 26 0.0 36 1.0 17 14.99999999624306 27 -64.24999998393108 37 0.0 40 128.4999999678622 41 0.2334630350193706 42 50.0 43 0.0 44 0.0 50 0.0 51 0.0 71 0 72 100 73 1 74 3 75 0 76 0 77 0 78 0 281 0 65 1 110 0.0 120 0.0 130 0.0 111 1.0 121 0.0 131 0.0 112 0.0 122 1.0 132 0.0 79 0 146 0.0 60 3 61 5 292 1 282 1 141 0.0 142 0.0 63 250 361 3F 0 ENDTAB 0 TABLE 2 LTYPE 5 5 330 0 100 AcDbSymbolTable 70 1 0 LTYPE 5 14 330 5 100 AcDbSymbolTableRecord 100 AcDbLinetypeTableRecord 2 ByBlock 70 0 3 72 65 73 0 40 0.0 0 LTYPE 5 15 330 5 100 AcDbSymbolTableRecord 100 AcDbLinetypeTableRecord 2 ByLayer 70 0 3 72 65 73 0 40 0.0 0 LTYPE 5 16 330 5 100 AcDbSymbolTableRecord 100 AcDbLinetypeTableRecord 2 Continuous 70 0 3 Solid line 72 65 73 0 40 0.0 0 ENDTAB 0 TABLE 2 LAYER 5 2 330 0 100 AcDbSymbolTable 70 5 0 LAYER 5 10 330 2 100 AcDbSymbolTableRecord 100 AcDbLayerTableRecord 2 0 70 0 62 7 6 Continuous 370 -3 390 F 347 3E 0 LAYER 5 40 330 2 100 AcDbSymbolTableRecord 100 AcDbLayerTableRecord 2 Panel 70 0 62 7 6 Continuous 370 -3 390 F 347 3E 0 LAYER 5 4B 330 2 100 AcDbSymbolTableRecord 100 AcDbLayerTableRecord 2 Holes 70 0 62 7 6 Continuous 370 -3 390 F 347 3E 0 LAYER 5 106 330 2 100 AcDbSymbolTableRecord 100 AcDbLayerTableRecord 2 Graphics 70 0 62 7 6 Continuous 370 -3 390 F 347 3E 0 LAYER 5 1217 330 2 100 AcDbSymbolTableRecord 100 AcDbLayerTableRecord 2 Elements 70 1 62 7 6 Continuous 370 -3 390 F 347 3E 0 ENDTAB 0 TABLE 2 STYLE 5 3 330 0 100 AcDbSymbolTable 70 1 0 STYLE 5 11 330 3 100 AcDbSymbolTableRecord 100 AcDbTextStyleTableRecord 2 Standard 70 0 40 0.0 41 1.0 50 0.0 71 0 42 0.2 3 txt 4 0 ENDTAB 0 TABLE 2 VIEW 5 6 330 0 100 AcDbSymbolTable 70 0 0 ENDTAB 0 TABLE 2 UCS 5 7 330 0 100 AcDbSymbolTable 70 0 0 ENDTAB 0 TABLE 2 APPID 5 9 330 0 100 AcDbSymbolTable 70 1 0 APPID 5 12 330 9 100 AcDbSymbolTableRecord 100 AcDbRegAppTableRecord 2 ACAD 70 0 0 ENDTAB 0 TABLE 2 DIMSTYLE 5 A 330 0 100 AcDbSymbolTable 70 1 100 AcDbDimStyleTable 0 DIMSTYLE 105 27 330 A 100 AcDbSymbolTableRecord 100 AcDbDimStyleTableRecord 2 Standard 70 0 178 0 340 11 0 ENDTAB 0 TABLE 2 BLOCK_RECORD 5 1 330 0 100 AcDbSymbolTable 70 8 0 BLOCK_RECORD 5 1F 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 *Model_Space 340 22 70 0 280 1 281 0 0 BLOCK_RECORD 5 1B 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 *Paper_Space 340 1E 70 0 280 1 281 0 0 BLOCK_RECORD 5 23 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 *Paper_Space0 340 26 70 0 280 1 281 0 0 BLOCK_RECORD 5 48A 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 block 2 340 0 102 {BLKREFS 331 48B 102 } 70 0 280 1 281 0 0 BLOCK_RECORD 5 5B1 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 block 3 340 0 102 {BLKREFS 331 5B2 102 } 70 0 280 1 281 0 0 BLOCK_RECORD 5 9E4 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 block 4 340 0 102 {BLKREFS 331 9E5 102 } 70 0 280 1 281 0 0 BLOCK_RECORD 5 C5A 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 block 5 340 0 102 {BLKREFS 331 C5B 102 } 70 0 280 1 281 0 0 BLOCK_RECORD 5 102E 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 block 6 340 0 102 {BLKREFS 331 102F 102 } 70 0 280 1 281 0 0 BLOCK_RECORD 5 1114 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 block 7 340 0 102 {BLKREFS 331 1115 102 } 70 0 280 1 281 0 0 BLOCK_RECORD 5 11FA 330 1 100 AcDbSymbolTableRecord 100 AcDbBlockTableRecord 2 block 8 340 0 102 {BLKREFS 331 11FB 102 } 70 0 280 1 281 0 0 ENDTAB 0 ENDSEC 0 SECTION 2 BLOCKS 0 BLOCK 5 20 330 1F 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 *Model_Space 70 0 10 0.0 20 0.0 30 0.0 3 *Model_Space 1 0 ENDBLK 5 21 330 1F 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 1C 330 1B 100 AcDbEntity 67 1 8 0 100 AcDbBlockBegin 2 *Paper_Space 70 0 10 0.0 20 0.0 30 0.0 3 *Paper_Space 1 0 ENDBLK 5 1D 330 1B 100 AcDbEntity 67 1 8 0 100 AcDbBlockEnd 0 BLOCK 5 24 330 23 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 *Paper_Space0 70 0 10 0.0 20 0.0 30 0.0 3 *Paper_Space0 1 0 ENDBLK 5 25 330 23 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 48C 330 48A 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 block 2 70 0 10 0.0 20 0.0 30 0.0 3 block 2 1 0 POLYLINE 5 48E 330 48A 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 48F 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.75129342598552 30 0.0 0 VERTEX 5 490 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.324021739746705 20 -42.75129342598552 30 0.0 0 VERTEX 5 491 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.717383488487775 20 -42.75129342598552 30 0.0 0 VERTEX 5 492 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.110745237228842 20 -42.75129342598552 30 0.0 0 VERTEX 5 493 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.504106985970554 20 -42.75129342598552 30 0.0 0 VERTEX 5 494 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.897468734711623 20 -42.75129342598552 30 0.0 0 VERTEX 5 495 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.290830483452693 20 -42.75129342598552 30 0.0 0 VERTEX 5 496 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.684192232193761 20 -42.75129342598552 30 0.0 0 VERTEX 5 497 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.75129342598552 30 0.0 0 VERTEX 5 498 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.72123496787672 30 0.0 0 VERTEX 5 499 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.69117650976791 30 0.0 0 VERTEX 5 49A 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.66111805165911 30 0.0 0 VERTEX 5 49B 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.6310595935503 30 0.0 0 VERTEX 5 49C 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.6010011354415 30 0.0 0 VERTEX 5 49D 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.5709426773327 30 0.0 0 VERTEX 5 49E 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.54088421922389 30 0.0 0 VERTEX 5 49F 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A0 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.033456758723633 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A1 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.989359536512436 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A2 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.945262314301237 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A3 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A4 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.857067869878842 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A5 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.812970647667644 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A6 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.768873425456445 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A7 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -42.51082576111509 30 0.0 0 VERTEX 5 4A8 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -42.61506143139067 30 0.0 0 VERTEX 5 4A9 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -42.71929710166626 30 0.0 0 VERTEX 5 4AA 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -42.82353277194186 30 0.0 0 VERTEX 5 4AB 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -42.92776844221744 30 0.0 0 VERTEX 5 4AC 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -43.03200411249303 30 0.0 0 VERTEX 5 4AD 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -43.13623978276863 30 0.0 0 VERTEX 5 4AE 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -43.24047545304422 30 0.0 0 VERTEX 5 4AF 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B0 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.768873425456445 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B1 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.812970647667644 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B2 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.857067869878842 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B3 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B4 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.945262314301237 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B5 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.989359536512436 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B6 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.033456758723633 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B7 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.3447111233198 30 0.0 0 VERTEX 5 4B8 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.31463113336422 30 0.0 0 VERTEX 5 4B9 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.28455114340863 30 0.0 0 VERTEX 5 4BA 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.25447115345305 30 0.0 0 VERTEX 5 4BB 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.22439116349746 30 0.0 0 VERTEX 5 4BC 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.19431117354187 30 0.0 0 VERTEX 5 4BD 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.16423118358628 30 0.0 0 VERTEX 5 4BE 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.13415119363069 30 0.0 0 VERTEX 5 4BF 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C0 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.684192232193761 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C1 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.290830483452693 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C2 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.897468734711623 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C3 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.504106985970554 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C4 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.110745237228842 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C5 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.717383488487775 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C6 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.324021739746705 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C7 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.1040712036751 30 0.0 0 VERTEX 5 4C8 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.13415119363069 30 0.0 0 VERTEX 5 4C9 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.16423118358628 30 0.0 0 VERTEX 5 4CA 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.19431117354187 30 0.0 0 VERTEX 5 4CB 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.22439116349746 30 0.0 0 VERTEX 5 4CC 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.25447115345305 30 0.0 0 VERTEX 5 4CD 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.28455114340863 30 0.0 0 VERTEX 5 4CE 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.31463113336422 30 0.0 0 VERTEX 5 4CF 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D0 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.974757213216833 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D1 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.01885443542803 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D2 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.06295165763923 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D3 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D4 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.15114610206163 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D5 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.19524332427282 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D6 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23934054648402 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D7 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -43.3447111233198 30 0.0 0 VERTEX 5 4D8 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -43.24047545304422 30 0.0 0 VERTEX 5 4D9 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -43.13623978276863 30 0.0 0 VERTEX 5 4DA 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -43.03200411249303 30 0.0 0 VERTEX 5 4DB 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -42.92776844221744 30 0.0 0 VERTEX 5 4DC 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -42.82353277194186 30 0.0 0 VERTEX 5 4DD 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -42.71929710166626 30 0.0 0 VERTEX 5 4DE 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -42.61506143139067 30 0.0 0 VERTEX 5 4DF 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E0 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23934054648402 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E1 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.19524332427282 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E2 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.15114610206163 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E3 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E4 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.06295165763923 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E5 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.01885443542803 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E6 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.974757213216833 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E7 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.51082576111509 30 0.0 0 VERTEX 5 4E8 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.54088421922389 30 0.0 0 VERTEX 5 4E9 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.5709426773327 30 0.0 0 VERTEX 5 4EA 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.6010011354415 30 0.0 0 VERTEX 5 4EB 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.6310595935503 30 0.0 0 VERTEX 5 4EC 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.66111805165911 30 0.0 0 VERTEX 5 4ED 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.69117650976791 30 0.0 0 VERTEX 5 4EE 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.72123496787672 30 0.0 0 VERTEX 5 4EF 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.75129342598552 30 0.0 0 VERTEX 5 4F0 330 48E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -42.75129342598552 30 0.0 0 SEQEND 5 4F2 330 48E 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 4F1 330 48A 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 96 72 1 10 9.930659991005635 20 -42.75129342598552 11 9.324021739746705 21 -42.75129342598552 72 1 10 9.324021739746705 20 -42.75129342598552 11 8.717383488487775 21 -42.75129342598552 72 1 10 8.717383488487775 20 -42.75129342598552 11 8.110745237228842 21 -42.75129342598552 72 1 10 8.110745237228842 20 -42.75129342598552 11 7.504106985970554 21 -42.75129342598552 72 1 10 7.504106985970554 20 -42.75129342598552 11 6.897468734711623 21 -42.75129342598552 72 1 10 6.897468734711623 20 -42.75129342598552 11 6.290830483452693 21 -42.75129342598552 72 1 10 6.290830483452693 20 -42.75129342598552 11 5.684192232193761 21 -42.75129342598552 72 1 10 5.684192232193761 20 -42.75129342598552 11 5.077553980934831 21 -42.75129342598552 72 1 10 5.077553980934831 20 -42.75129342598552 11 5.077553980934831 21 -42.72123496787672 72 1 10 5.077553980934831 20 -42.72123496787672 11 5.077553980934831 21 -42.69117650976791 72 1 10 5.077553980934831 20 -42.69117650976791 11 5.077553980934831 21 -42.66111805165911 72 1 10 5.077553980934831 20 -42.66111805165911 11 5.077553980934831 21 -42.6310595935503 72 1 10 5.077553980934831 20 -42.6310595935503 11 5.077553980934831 21 -42.6010011354415 72 1 10 5.077553980934831 20 -42.6010011354415 11 5.077553980934831 21 -42.5709426773327 72 1 10 5.077553980934831 20 -42.5709426773327 11 5.077553980934831 21 -42.54088421922389 72 1 10 5.077553980934831 20 -42.54088421922389 11 5.077553980934831 21 -42.51082576111509 72 1 10 5.077553980934831 20 -42.51082576111509 11 5.033456758723633 21 -42.51082576111509 72 1 10 5.033456758723633 20 -42.51082576111509 11 4.989359536512436 21 -42.51082576111509 72 1 10 4.989359536512436 20 -42.51082576111509 11 4.945262314301237 21 -42.51082576111509 72 1 10 4.945262314301237 20 -42.51082576111509 11 4.901165092090039 21 -42.51082576111509 72 1 10 4.901165092090039 20 -42.51082576111509 11 4.857067869878842 21 -42.51082576111509 72 1 10 4.857067869878842 20 -42.51082576111509 11 4.812970647667644 21 -42.51082576111509 72 1 10 4.812970647667644 20 -42.51082576111509 11 4.768873425456445 21 -42.51082576111509 72 1 10 4.768873425456445 20 -42.51082576111509 11 4.724776203245248 21 -42.51082576111509 72 1 10 4.724776203245248 20 -42.51082576111509 11 4.724776203245248 21 -42.61506143139067 72 1 10 4.724776203245248 20 -42.61506143139067 11 4.724776203245248 21 -42.71929710166626 72 1 10 4.724776203245248 20 -42.71929710166626 11 4.724776203245248 21 -42.82353277194186 72 1 10 4.724776203245248 20 -42.82353277194186 11 4.724776203245248 21 -42.92776844221744 72 1 10 4.724776203245248 20 -42.92776844221744 11 4.724776203245248 21 -43.03200411249303 72 1 10 4.724776203245248 20 -43.03200411249303 11 4.724776203245248 21 -43.13623978276863 72 1 10 4.724776203245248 20 -43.13623978276863 11 4.724776203245248 21 -43.24047545304422 72 1 10 4.724776203245248 20 -43.24047545304422 11 4.724776203245248 21 -43.3447111233198 72 1 10 4.724776203245248 20 -43.3447111233198 11 4.768873425456445 21 -43.3447111233198 72 1 10 4.768873425456445 20 -43.3447111233198 11 4.812970647667644 21 -43.3447111233198 72 1 10 4.812970647667644 20 -43.3447111233198 11 4.857067869878842 21 -43.3447111233198 72 1 10 4.857067869878842 20 -43.3447111233198 11 4.901165092090039 21 -43.3447111233198 72 1 10 4.901165092090039 20 -43.3447111233198 11 4.945262314301237 21 -43.3447111233198 72 1 10 4.945262314301237 20 -43.3447111233198 11 4.989359536512436 21 -43.3447111233198 72 1 10 4.989359536512436 20 -43.3447111233198 11 5.033456758723633 21 -43.3447111233198 72 1 10 5.033456758723633 20 -43.3447111233198 11 5.077553980934831 21 -43.3447111233198 72 1 10 5.077553980934831 20 -43.3447111233198 11 5.077553980934831 21 -43.31463113336422 72 1 10 5.077553980934831 20 -43.31463113336422 11 5.077553980934831 21 -43.28455114340863 72 1 10 5.077553980934831 20 -43.28455114340863 11 5.077553980934831 21 -43.25447115345305 72 1 10 5.077553980934831 20 -43.25447115345305 11 5.077553980934831 21 -43.22439116349746 72 1 10 5.077553980934831 20 -43.22439116349746 11 5.077553980934831 21 -43.19431117354187 72 1 10 5.077553980934831 20 -43.19431117354187 11 5.077553980934831 21 -43.16423118358628 72 1 10 5.077553980934831 20 -43.16423118358628 11 5.077553980934831 21 -43.13415119363069 72 1 10 5.077553980934831 20 -43.13415119363069 11 5.077553980934831 21 -43.1040712036751 72 1 10 5.077553980934831 20 -43.1040712036751 11 5.684192232193761 21 -43.1040712036751 72 1 10 5.684192232193761 20 -43.1040712036751 11 6.290830483452693 21 -43.1040712036751 72 1 10 6.290830483452693 20 -43.1040712036751 11 6.897468734711623 21 -43.1040712036751 72 1 10 6.897468734711623 20 -43.1040712036751 11 7.504106985970554 21 -43.1040712036751 72 1 10 7.504106985970554 20 -43.1040712036751 11 8.110745237228842 21 -43.1040712036751 72 1 10 8.110745237228842 20 -43.1040712036751 11 8.717383488487775 21 -43.1040712036751 72 1 10 8.717383488487775 20 -43.1040712036751 11 9.324021739746705 21 -43.1040712036751 72 1 10 9.324021739746705 20 -43.1040712036751 11 9.930659991005635 21 -43.1040712036751 72 1 10 9.930659991005635 20 -43.1040712036751 11 9.930659991005635 21 -43.13415119363069 72 1 10 9.930659991005635 20 -43.13415119363069 11 9.930659991005635 21 -43.16423118358628 72 1 10 9.930659991005635 20 -43.16423118358628 11 9.930659991005635 21 -43.19431117354187 72 1 10 9.930659991005635 20 -43.19431117354187 11 9.930659991005635 21 -43.22439116349746 72 1 10 9.930659991005635 20 -43.22439116349746 11 9.930659991005635 21 -43.25447115345305 72 1 10 9.930659991005635 20 -43.25447115345305 11 9.930659991005635 21 -43.28455114340863 72 1 10 9.930659991005635 20 -43.28455114340863 11 9.930659991005635 21 -43.31463113336422 72 1 10 9.930659991005635 20 -43.31463113336422 11 9.930659991005635 21 -43.3447111233198 72 1 10 9.930659991005635 20 -43.3447111233198 11 9.974757213216833 21 -43.3447111233198 72 1 10 9.974757213216833 20 -43.3447111233198 11 10.01885443542803 21 -43.3447111233198 72 1 10 10.01885443542803 20 -43.3447111233198 11 10.06295165763923 21 -43.3447111233198 72 1 10 10.06295165763923 20 -43.3447111233198 11 10.10704887985043 21 -43.3447111233198 72 1 10 10.10704887985043 20 -43.3447111233198 11 10.15114610206163 21 -43.3447111233198 72 1 10 10.15114610206163 20 -43.3447111233198 11 10.19524332427282 21 -43.3447111233198 72 1 10 10.19524332427282 20 -43.3447111233198 11 10.23934054648402 21 -43.3447111233198 72 1 10 10.23934054648402 20 -43.3447111233198 11 10.28343776869522 21 -43.3447111233198 72 1 10 10.28343776869522 20 -43.3447111233198 11 10.28343776869522 21 -43.24047545304422 72 1 10 10.28343776869522 20 -43.24047545304422 11 10.28343776869522 21 -43.13623978276863 72 1 10 10.28343776869522 20 -43.13623978276863 11 10.28343776869522 21 -43.03200411249303 72 1 10 10.28343776869522 20 -43.03200411249303 11 10.28343776869522 21 -42.92776844221744 72 1 10 10.28343776869522 20 -42.92776844221744 11 10.28343776869522 21 -42.82353277194186 72 1 10 10.28343776869522 20 -42.82353277194186 11 10.28343776869522 21 -42.71929710166626 72 1 10 10.28343776869522 20 -42.71929710166626 11 10.28343776869522 21 -42.61506143139067 72 1 10 10.28343776869522 20 -42.61506143139067 11 10.28343776869522 21 -42.51082576111509 72 1 10 10.28343776869522 20 -42.51082576111509 11 10.23934054648402 21 -42.51082576111509 72 1 10 10.23934054648402 20 -42.51082576111509 11 10.19524332427282 21 -42.51082576111509 72 1 10 10.19524332427282 20 -42.51082576111509 11 10.15114610206163 21 -42.51082576111509 72 1 10 10.15114610206163 20 -42.51082576111509 11 10.10704887985043 21 -42.51082576111509 72 1 10 10.10704887985043 20 -42.51082576111509 11 10.06295165763923 21 -42.51082576111509 72 1 10 10.06295165763923 20 -42.51082576111509 11 10.01885443542803 21 -42.51082576111509 72 1 10 10.01885443542803 20 -42.51082576111509 11 9.974757213216833 21 -42.51082576111509 72 1 10 9.974757213216833 20 -42.51082576111509 11 9.930659991005635 21 -42.51082576111509 72 1 10 9.930659991005635 20 -42.51082576111509 11 9.930659991005635 21 -42.54088421922389 72 1 10 9.930659991005635 20 -42.54088421922389 11 9.930659991005635 21 -42.5709426773327 72 1 10 9.930659991005635 20 -42.5709426773327 11 9.930659991005635 21 -42.6010011354415 72 1 10 9.930659991005635 20 -42.6010011354415 11 9.930659991005635 21 -42.6310595935503 72 1 10 9.930659991005635 20 -42.6310595935503 11 9.930659991005635 21 -42.66111805165911 72 1 10 9.930659991005635 20 -42.66111805165911 11 9.930659991005635 21 -42.69117650976791 72 1 10 9.930659991005635 20 -42.69117650976791 11 9.930659991005635 21 -42.72123496787672 72 1 10 9.930659991005635 20 -42.72123496787672 11 9.930659991005635 21 -42.75129342598552 97 0 75 2 76 1 98 0 0 POLYLINE 5 4F3 330 48A 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 4F4 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -41.83386449826349 30 0.0 0 VERTEX 5 4F5 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.108198282824512 20 -41.78769719084487 30 0.0 0 VERTEX 5 4F6 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.171042482663259 20 -41.65569654057827 30 0.0 0 VERTEX 5 4F7 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.317614614458035 20 -41.44761445544471 30 0.0 0 VERTEX 5 4F8 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.569947813298278 20 -41.17320284342649 30 0.0 0 VERTEX 5 4F9 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.950075214275356 20 -40.84221361250557 30 0.0 0 VERTEX 5 4FA 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.480029952479991 20 -40.46439867066396 30 0.0 0 VERTEX 5 4FB 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.181845163002908 20 -40.04950992588362 30 0.0 0 VERTEX 5 4FC 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -39.60729928614652 30 0.0 0 VERTEX 5 4FD 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.073973638536977 20 -39.5717280023911 30 0.0 0 VERTEX 5 4FE 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.063703620491788 20 -39.53860731194766 30 0.0 0 VERTEX 5 4FF 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.047450440521825 20 -39.50864372853874 30 0.0 0 VERTEX 5 500 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.025920612349649 20 -39.48254376588691 30 0.0 0 VERTEX 5 501 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.999820649697821 20 -39.46101393771473 30 0.0 0 VERTEX 5 502 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.969857066288903 20 -39.44476075774477 30 0.0 0 VERTEX 5 503 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.936736375845456 20 -39.4344907396999 30 0.0 0 VERTEX 5 504 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -39.43091039730173 30 0.0 0 VERTEX 5 505 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.865593808334623 20 -39.4344907396999 30 0.0 0 VERTEX 5 506 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.832473117891175 20 -39.44476075774477 30 0.0 0 VERTEX 5 507 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.802509534482257 20 -39.46101393771473 30 0.0 0 VERTEX 5 508 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.776409571830429 20 -39.48254376588691 30 0.0 0 VERTEX 5 509 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.754879743658254 20 -39.50864372853874 30 0.0 0 VERTEX 5 50A 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.738626563688292 20 -39.53860731194766 30 0.0 0 VERTEX 5 50B 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.728356545643102 20 -39.5717280023911 30 0.0 0 VERTEX 5 50C 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -39.60729928614652 30 0.0 0 VERTEX 5 50D 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -39.90766854876674 30 0.0 0 VERTEX 5 50E 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -40.20803781138696 30 0.0 0 VERTEX 5 50F 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -40.50840707400718 30 0.0 0 VERTEX 5 510 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -40.8087763366274 30 0.0 0 VERTEX 5 511 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -41.10914559924762 30 0.0 0 VERTEX 5 512 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -41.40951486186784 30 0.0 0 VERTEX 5 513 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -41.70988412448806 30 0.0 0 VERTEX 5 514 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -42.01025338710829 30 0.0 0 VERTEX 5 515 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.728356545643102 20 -42.0458246708637 30 0.0 0 VERTEX 5 516 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.738626563688292 20 -42.07894536130715 30 0.0 0 VERTEX 5 517 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.754879743658254 20 -42.10890894471606 30 0.0 0 VERTEX 5 518 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.776409571830429 20 -42.13500890736789 30 0.0 0 VERTEX 5 519 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.802509534482257 20 -42.15653873554007 30 0.0 0 VERTEX 5 51A 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.832473117891175 20 -42.17279191551035 30 0.0 0 VERTEX 5 51B 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.865593808334623 20 -42.18306193355522 30 0.0 0 VERTEX 5 51C 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -42.18664227595308 30 0.0 0 VERTEX 5 51D 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.936736375845456 20 -42.18306193355522 30 0.0 0 VERTEX 5 51E 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.969857066288903 20 -42.17279191551035 30 0.0 0 VERTEX 5 51F 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.999820649697821 20 -42.15653873554007 30 0.0 0 VERTEX 5 520 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.025920612349649 20 -42.13500890736789 30 0.0 0 VERTEX 5 521 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.047450440521825 20 -42.10890894471606 30 0.0 0 VERTEX 5 522 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.063703620491788 20 -42.07894536130715 30 0.0 0 VERTEX 5 523 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.073973638536977 20 -42.0458246708637 30 0.0 0 VERTEX 5 524 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -42.01025338710829 30 0.0 0 VERTEX 5 525 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -41.82590309791554 30 0.0 0 VERTEX 5 526 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -41.64155280872281 30 0.0 0 VERTEX 5 527 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -41.45720251953007 30 0.0 0 VERTEX 5 528 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -41.27285223033734 30 0.0 0 VERTEX 5 529 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -41.0885019411446 30 0.0 0 VERTEX 5 52A 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -40.90415165195186 30 0.0 0 VERTEX 5 52B 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -40.71980136275913 30 0.0 0 VERTEX 5 52C 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -40.53545107356639 30 0.0 0 VERTEX 5 52D 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.417112466331416 20 -40.88606797062464 30 0.0 0 VERTEX 5 52E 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.857496011116704 20 -41.20438936844533 30 0.0 0 VERTEX 5 52F 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.389596139448908 20 -41.48596044568232 30 0.0 0 VERTEX 5 530 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.004304375486238 20 -41.72632638098759 30 0.0 0 VERTEX 5 531 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.692512243386908 20 -41.92103235301438 30 0.0 0 VERTEX 5 532 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.445111267308487 20 -42.0656235404156 30 0.0 0 VERTEX 5 533 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.25299297141047 20 -42.15564512184419 30 0.0 0 VERTEX 5 534 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -42.18664227595308 30 0.0 0 VERTEX 5 535 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.14262016360584 20 -42.18306193355522 30 0.0 0 VERTEX 5 536 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.17574085404929 20 -42.17279191551035 30 0.0 0 VERTEX 5 537 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.20570443745821 20 -42.15653873554007 30 0.0 0 VERTEX 5 538 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23180440011004 20 -42.13500890736789 30 0.0 0 VERTEX 5 539 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25333422828221 20 -42.10890894471606 30 0.0 0 VERTEX 5 53A 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.26958740825217 20 -42.07894536130715 30 0.0 0 VERTEX 5 53B 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.27985742629737 20 -42.0458246708637 30 0.0 0 VERTEX 5 53C 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -42.01025338710829 30 0.0 0 VERTEX 5 53D 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.27985742629737 20 -41.97468210335287 30 0.0 0 VERTEX 5 53E 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.26958740825217 20 -41.94156141290942 30 0.0 0 VERTEX 5 53F 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25333422828221 20 -41.9115978295005 30 0.0 0 VERTEX 5 540 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23180440011004 20 -41.88549786684867 30 0.0 0 VERTEX 5 541 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.20570443745821 20 -41.8639680386765 30 0.0 0 VERTEX 5 542 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.17574085404929 20 -41.84771485870653 30 0.0 0 VERTEX 5 543 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.14262016360584 20 -41.83744484066167 30 0.0 0 VERTEX 5 544 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -41.83386449826349 30 0.0 0 VERTEX 5 545 330 4F3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -41.83386449826349 30 0.0 0 SEQEND 5 547 330 4F3 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 546 330 48A 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 80 72 1 10 10.10704887985043 20 -41.83386449826349 11 9.108198282824512 21 -41.78769719084487 72 1 10 9.108198282824512 20 -41.78769719084487 11 8.171042482663259 21 -41.65569654057827 72 1 10 8.171042482663259 20 -41.65569654057827 11 7.317614614458035 21 -41.44761445544471 72 1 10 7.317614614458035 20 -41.44761445544471 11 6.569947813298278 21 -41.17320284342649 72 1 10 6.569947813298278 20 -41.17320284342649 11 5.950075214275356 21 -40.84221361250557 72 1 10 5.950075214275356 20 -40.84221361250557 11 5.480029952479991 21 -40.46439867066396 72 1 10 5.480029952479991 20 -40.46439867066396 11 5.181845163002908 21 -40.04950992588362 72 1 10 5.181845163002908 20 -40.04950992588362 11 5.077553980934831 21 -39.60729928614652 72 1 10 5.077553980934831 20 -39.60729928614652 11 5.073973638536977 21 -39.5717280023911 72 1 10 5.073973638536977 20 -39.5717280023911 11 5.063703620491788 21 -39.53860731194766 72 1 10 5.063703620491788 20 -39.53860731194766 11 5.047450440521825 21 -39.50864372853874 72 1 10 5.047450440521825 20 -39.50864372853874 11 5.025920612349649 21 -39.48254376588691 72 1 10 5.025920612349649 20 -39.48254376588691 11 4.999820649697821 21 -39.46101393771473 72 1 10 4.999820649697821 20 -39.46101393771473 11 4.969857066288903 21 -39.44476075774477 72 1 10 4.969857066288903 20 -39.44476075774477 11 4.936736375845456 21 -39.4344907396999 72 1 10 4.936736375845456 20 -39.4344907396999 11 4.901165092090039 21 -39.43091039730173 72 1 10 4.901165092090039 20 -39.43091039730173 11 4.865593808334623 21 -39.4344907396999 72 1 10 4.865593808334623 20 -39.4344907396999 11 4.832473117891175 21 -39.44476075774477 72 1 10 4.832473117891175 20 -39.44476075774477 11 4.802509534482257 21 -39.46101393771473 72 1 10 4.802509534482257 20 -39.46101393771473 11 4.776409571830429 21 -39.48254376588691 72 1 10 4.776409571830429 20 -39.48254376588691 11 4.754879743658254 21 -39.50864372853874 72 1 10 4.754879743658254 20 -39.50864372853874 11 4.738626563688292 21 -39.53860731194766 72 1 10 4.738626563688292 20 -39.53860731194766 11 4.728356545643102 21 -39.5717280023911 72 1 10 4.728356545643102 20 -39.5717280023911 11 4.724776203245248 21 -39.60729928614652 72 1 10 4.724776203245248 20 -39.60729928614652 11 4.724776203245248 21 -39.90766854876674 72 1 10 4.724776203245248 20 -39.90766854876674 11 4.724776203245248 21 -40.20803781138696 72 1 10 4.724776203245248 20 -40.20803781138696 11 4.724776203245248 21 -40.50840707400718 72 1 10 4.724776203245248 20 -40.50840707400718 11 4.724776203245248 21 -40.8087763366274 72 1 10 4.724776203245248 20 -40.8087763366274 11 4.724776203245248 21 -41.10914559924762 72 1 10 4.724776203245248 20 -41.10914559924762 11 4.724776203245248 21 -41.40951486186784 72 1 10 4.724776203245248 20 -41.40951486186784 11 4.724776203245248 21 -41.70988412448806 72 1 10 4.724776203245248 20 -41.70988412448806 11 4.724776203245248 21 -42.01025338710829 72 1 10 4.724776203245248 20 -42.01025338710829 11 4.728356545643102 21 -42.0458246708637 72 1 10 4.728356545643102 20 -42.0458246708637 11 4.738626563688292 21 -42.07894536130715 72 1 10 4.738626563688292 20 -42.07894536130715 11 4.754879743658254 21 -42.10890894471606 72 1 10 4.754879743658254 20 -42.10890894471606 11 4.776409571830429 21 -42.13500890736789 72 1 10 4.776409571830429 20 -42.13500890736789 11 4.802509534482257 21 -42.15653873554007 72 1 10 4.802509534482257 20 -42.15653873554007 11 4.832473117891175 21 -42.17279191551035 72 1 10 4.832473117891175 20 -42.17279191551035 11 4.865593808334623 21 -42.18306193355522 72 1 10 4.865593808334623 20 -42.18306193355522 11 4.901165092090039 21 -42.18664227595308 72 1 10 4.901165092090039 20 -42.18664227595308 11 4.936736375845456 21 -42.18306193355522 72 1 10 4.936736375845456 20 -42.18306193355522 11 4.969857066288903 21 -42.17279191551035 72 1 10 4.969857066288903 20 -42.17279191551035 11 4.999820649697821 21 -42.15653873554007 72 1 10 4.999820649697821 20 -42.15653873554007 11 5.025920612349649 21 -42.13500890736789 72 1 10 5.025920612349649 20 -42.13500890736789 11 5.047450440521825 21 -42.10890894471606 72 1 10 5.047450440521825 20 -42.10890894471606 11 5.063703620491788 21 -42.07894536130715 72 1 10 5.063703620491788 20 -42.07894536130715 11 5.073973638536977 21 -42.0458246708637 72 1 10 5.073973638536977 20 -42.0458246708637 11 5.077553980934831 21 -42.01025338710829 72 1 10 5.077553980934831 20 -42.01025338710829 11 5.077553980934831 21 -41.82590309791554 72 1 10 5.077553980934831 20 -41.82590309791554 11 5.077553980934831 21 -41.64155280872281 72 1 10 5.077553980934831 20 -41.64155280872281 11 5.077553980934831 21 -41.45720251953007 72 1 10 5.077553980934831 20 -41.45720251953007 11 5.077553980934831 21 -41.27285223033734 72 1 10 5.077553980934831 20 -41.27285223033734 11 5.077553980934831 21 -41.0885019411446 72 1 10 5.077553980934831 20 -41.0885019411446 11 5.077553980934831 21 -40.90415165195186 72 1 10 5.077553980934831 20 -40.90415165195186 11 5.077553980934831 21 -40.71980136275913 72 1 10 5.077553980934831 20 -40.71980136275913 11 5.077553980934831 21 -40.53545107356639 72 1 10 5.077553980934831 20 -40.53545107356639 11 5.417112466331416 21 -40.88606797062464 72 1 10 5.417112466331416 20 -40.88606797062464 11 5.857496011116704 21 -41.20438936844533 72 1 10 5.857496011116704 20 -41.20438936844533 11 6.389596139448908 21 -41.48596044568232 72 1 10 6.389596139448908 20 -41.48596044568232 11 7.004304375486238 21 -41.72632638098759 72 1 10 7.004304375486238 20 -41.72632638098759 11 7.692512243386908 21 -41.92103235301438 72 1 10 7.692512243386908 20 -41.92103235301438 11 8.445111267308487 21 -42.0656235404156 72 1 10 8.445111267308487 20 -42.0656235404156 11 9.25299297141047 21 -42.15564512184419 72 1 10 9.25299297141047 20 -42.15564512184419 11 10.10704887985043 21 -42.18664227595308 72 1 10 10.10704887985043 20 -42.18664227595308 11 10.14262016360584 21 -42.18306193355522 72 1 10 10.14262016360584 20 -42.18306193355522 11 10.17574085404929 21 -42.17279191551035 72 1 10 10.17574085404929 20 -42.17279191551035 11 10.20570443745821 21 -42.15653873554007 72 1 10 10.20570443745821 20 -42.15653873554007 11 10.23180440011004 21 -42.13500890736789 72 1 10 10.23180440011004 20 -42.13500890736789 11 10.25333422828221 21 -42.10890894471606 72 1 10 10.25333422828221 20 -42.10890894471606 11 10.26958740825217 21 -42.07894536130715 72 1 10 10.26958740825217 20 -42.07894536130715 11 10.27985742629737 21 -42.0458246708637 72 1 10 10.27985742629737 20 -42.0458246708637 11 10.28343776869522 21 -42.01025338710829 72 1 10 10.28343776869522 20 -42.01025338710829 11 10.27985742629737 21 -41.97468210335287 72 1 10 10.27985742629737 20 -41.97468210335287 11 10.26958740825217 21 -41.94156141290942 72 1 10 10.26958740825217 20 -41.94156141290942 11 10.25333422828221 21 -41.9115978295005 72 1 10 10.25333422828221 20 -41.9115978295005 11 10.23180440011004 21 -41.88549786684867 72 1 10 10.23180440011004 20 -41.88549786684867 11 10.20570443745821 21 -41.8639680386765 72 1 10 10.20570443745821 20 -41.8639680386765 11 10.17574085404929 21 -41.84771485870653 72 1 10 10.17574085404929 20 -41.84771485870653 11 10.14262016360584 21 -41.83744484066167 72 1 10 10.14262016360584 20 -41.83744484066167 11 10.10704887985043 21 -41.83386449826349 97 0 75 2 76 1 98 0 0 ENDBLK 5 48D 330 48A 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 5B3 330 5B1 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 block 3 70 0 10 0.0 20 0.0 30 0.0 3 block 3 1 0 POLYLINE 5 5B5 330 5B1 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 5B6 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.59296145529015 20 -126.2045262314565 30 0.0 0 VERTEX 5 5B7 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.61177490641663 20 -126.1887400234137 30 0.0 0 VERTEX 5 5B8 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.6342380055728 20 -126.1707050831224 30 0.0 0 VERTEX 5 5B9 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.66035075275865 20 -126.1504173733615 30 0.0 0 VERTEX 5 5BA 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.69011314797419 20 -126.1278728569097 30 0.0 0 VERTEX 5 5BB 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.72352519121942 20 -126.1030674965457 30 0.0 0 VERTEX 5 5BC 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.76058688249433 20 -126.0759972550482 30 0.0 0 VERTEX 5 5BD 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.80129822179893 20 -126.046658095196 30 0.0 0 VERTEX 5 5BE 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.84565920913322 20 -126.0150459797678 30 0.0 0 VERTEX 5 5BF 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.87024857815919 20 -125.9976051838737 30 0.0 0 VERTEX 5 5C0 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.89483794718516 20 -125.9801643879796 30 0.0 0 VERTEX 5 5C1 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.91942731621113 20 -125.9627235920856 30 0.0 0 VERTEX 5 5C2 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.94401668523711 20 -125.9452827961915 30 0.0 0 VERTEX 5 5C3 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.96860605426308 20 -125.9278420002974 30 0.0 0 VERTEX 5 5C4 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.99319542328905 20 -125.9104012044033 30 0.0 0 VERTEX 5 5C5 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.01778479231502 20 -125.8929604085093 30 0.0 0 VERTEX 5 5C6 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.04237416134099 20 -125.8755196126152 30 0.0 0 VERTEX 5 5C7 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.10232723366198 20 -125.8321036714936 30 0.0 0 VERTEX 5 5C8 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.15790597673501 20 -125.7897071287431 30 0.0 0 VERTEX 5 5C9 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.2091124091707 20 -125.7483320029744 30 0.0 0 VERTEX 5 5CA 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.2559485495797 20 -125.7079803127981 30 0.0 0 VERTEX 5 5CB 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.29841641657262 20 -125.6686540768249 30 0.0 0 VERTEX 5 5CC 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.33651802876013 20 -125.6303553136652 30 0.0 0 VERTEX 5 5CD 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.37025540475284 20 -125.5930860419299 30 0.0 0 VERTEX 5 5CE 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.3996305631614 20 -125.5568482802296 30 0.0 0 VERTEX 5 5CF 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.4384521464757 20 -125.5020638604418 30 0.0 0 VERTEX 5 5D0 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.47210406795149 20 -125.4453294627797 30 0.0 0 VERTEX 5 5D1 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.50058430897814 20 -125.3866491244646 30 0.0 0 VERTEX 5 5D2 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.523890850945 20 -125.3260268827178 30 0.0 0 VERTEX 5 5D3 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.54202167524145 20 -125.2634667747606 30 0.0 0 VERTEX 5 5D4 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55497476325684 20 -125.1989728378142 30 0.0 0 VERTEX 5 5D5 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56274809638054 20 -125.1325491090998 30 0.0 0 VERTEX 5 5D6 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56533965600191 20 -125.0641996258388 30 0.0 0 VERTEX 5 5D7 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56167419552225 20 -124.9759863410505 30 0.0 0 VERTEX 5 5D8 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55067915982367 20 -124.8922139996611 30 0.0 0 VERTEX 5 5D9 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.53235656751681 20 -124.8128826016707 30 0.0 0 VERTEX 5 5DA 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.50670843721232 20 -124.7379921470793 30 0.0 0 VERTEX 5 5DB 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.47373678752082 20 -124.6675426358867 30 0.0 0 VERTEX 5 5DC 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.43344363705295 20 -124.6015340680932 30 0.0 0 VERTEX 5 5DD 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.38583100441936 20 -124.5399664436986 30 0.0 0 VERTEX 5 5DE 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.33090090823066 20 -124.4828397627029 30 0.0 0 VERTEX 5 5DF 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.26972052064304 20 -124.4313651914878 30 0.0 0 VERTEX 5 5E0 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.20348351341253 20 -124.3867538964346 30 0.0 0 VERTEX 5 5E1 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.13218786792847 20 -124.3490058775435 30 0.0 0 VERTEX 5 5E2 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.05583156558025 20 -124.3181211348144 30 0.0 0 VERTEX 5 5E3 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.97441258775721 20 -124.2940996682474 30 0.0 0 VERTEX 5 5E4 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.88792891584873 20 -124.2769414778423 30 0.0 0 VERTEX 5 5E5 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.79637853124417 20 -124.2666465635993 30 0.0 0 VERTEX 5 5E6 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.69975941533289 20 -124.2632149255183 30 0.0 0 VERTEX 5 5E7 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.57907946994714 20 -124.2690530839124 30 0.0 0 VERTEX 5 5E8 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.46793140398406 20 -124.2865689048351 30 0.0 0 VERTEX 5 5E9 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.36631925466491 20 -124.315764406897 30 0.0 0 VERTEX 5 5EA 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.27424705921097 20 -124.3566416087089 30 0.0 0 VERTEX 5 5EB 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.19171885484351 20 -124.4092025288813 30 0.0 0 VERTEX 5 5EC 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.11873867878381 20 -124.4734491860248 30 0.0 0 VERTEX 5 5ED 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.05531056825313 20 -124.5493835987501 30 0.0 0 VERTEX 5 5EE 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.00143856047275 20 -124.6370077856679 30 0.0 0 VERTEX 5 5EF 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.97697232669557 20 -124.6880137027804 30 0.0 0 VERTEX 5 5F0 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.95537655724262 20 -124.7428448870479 30 0.0 0 VERTEX 5 5F1 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.93664721489263 20 -124.8014993198598 30 0.0 0 VERTEX 5 5F2 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.92078026242434 20 -124.8639749826055 30 0.0 0 VERTEX 5 5F3 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.90777166261646 20 -124.9302698566742 30 0.0 0 VERTEX 5 5F4 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.89761737824773 20 -125.0003819234554 30 0.0 0 VERTEX 5 5F5 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.89031337209687 20 -125.0743091643385 30 0.0 0 VERTEX 5 5F6 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.88585560694262 20 -125.1520495607127 30 0.0 0 VERTEX 5 5F7 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.94549882253101 20 -125.1520495607127 30 0.0 0 VERTEX 5 5F8 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.00514203811939 20 -125.1520495607127 30 0.0 0 VERTEX 5 5F9 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.06478525370778 20 -125.1520495607127 30 0.0 0 VERTEX 5 5FA 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.12442846929617 20 -125.1520495607127 30 0.0 0 VERTEX 5 5FB 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.18407168488456 20 -125.1520495607127 30 0.0 0 VERTEX 5 5FC 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.24371490047294 20 -125.1520495607127 30 0.0 0 VERTEX 5 5FD 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.30335811606133 20 -125.1520495607127 30 0.0 0 VERTEX 5 5FE 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.36300133164972 20 -125.1520495607127 30 0.0 0 VERTEX 5 5FF 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.36573015679433 20 -125.1013023621967 30 0.0 0 VERTEX 5 600 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.36965198082476 20 -125.054095806736 30 0.0 0 VERTEX 5 601 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.37476478513036 20 -125.0104339315519 30 0.0 0 VERTEX 5 602 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.3810665511005 20 -124.9703207738658 30 0.0 0 VERTEX 5 603 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.38855526012454 20 -124.9337603708988 30 0.0 0 VERTEX 5 604 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.39722889359185 20 -124.9007567598722 30 0.0 0 VERTEX 5 605 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.40708543289179 20 -124.8713139780074 30 0.0 0 VERTEX 5 606 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.41812285941372 20 -124.8454360625255 30 0.0 0 VERTEX 5 607 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.44057788412734 20 -124.806258530869 30 0.0 0 VERTEX 5 608 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.4675061500101 20 -124.7723112193702 30 0.0 0 VERTEX 5 609 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.49890765706198 20 -124.7435921094183 30 0.0 0 VERTEX 5 60A 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.53478240528299 20 -124.7200991824027 30 0.0 0 VERTEX 5 60B 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.57513039467313 20 -124.7018304197128 30 0.0 0 VERTEX 5 60C 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.6199516252324 20 -124.688783802738 30 0.0 0 VERTEX 5 60D 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.6692460969608 20 -124.6809573128675 30 0.0 0 VERTEX 5 60E 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.72301380985833 20 -124.6783489314909 30 0.0 0 VERTEX 5 60F 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.76272358185242 20 -124.6799883797623 30 0.0 0 VERTEX 5 610 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.80007359801316 20 -124.6849080703171 30 0.0 0 VERTEX 5 611 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.83506183972991 20 -124.6931100217658 30 0.0 0 VERTEX 5 612 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.86768628839204 20 -124.7045962527191 30 0.0 0 VERTEX 5 613 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.8979449253889 20 -124.7193687817877 30 0.0 0 VERTEX 5 614 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.92583573210987 20 -124.737429627582 30 0.0 0 VERTEX 5 615 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.9513566899443 20 -124.7587808087129 30 0.0 0 VERTEX 5 616 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.97450578028157 20 -124.783424343791 30 0.0 0 VERTEX 5 617 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.99509560876763 20 -124.8105463962948 30 0.0 0 VERTEX 5 618 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.01294012678888 20 -124.8393317839625 30 0.0 0 VERTEX 5 619 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.02803933434533 20 -124.8697805067943 30 0.0 0 VERTEX 5 61A 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.04039323143697 20 -124.90189256479 30 0.0 0 VERTEX 5 61B 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.0500018180638 20 -124.9356679579497 30 0.0 0 VERTEX 5 61C 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.05686509422582 20 -124.9711066862734 30 0.0 0 VERTEX 5 61D 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.06098305992303 20 -125.008208749761 30 0.0 0 VERTEX 5 61E 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.06235571515544 20 -125.0469741484126 30 0.0 0 VERTEX 5 61F 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.05995794215511 20 -125.0951375253147 30 0.0 0 VERTEX 5 620 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.05276596889454 20 -125.1423440807754 30 0.0 0 VERTEX 5 621 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.04078181398438 20 -125.1885897775734 30 0.0 0 VERTEX 5 622 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.02400749603525 20 -125.2338705784874 30 0.0 0 VERTEX 5 623 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.00244503365779 20 -125.2781824462962 30 0.0 0 VERTEX 5 624 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.97609644546265 20 -125.3215213437785 30 0.0 0 VERTEX 5 625 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.94496375006044 20 -125.3638832337131 30 0.0 0 VERTEX 5 626 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.90904896606182 20 -125.4052640788786 30 0.0 0 VERTEX 5 627 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.88031202504931 20 -125.4337026019521 30 0.0 0 VERTEX 5 628 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.84409815024147 20 -125.4664387470694 30 0.0 0 VERTEX 5 629 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.8004073416383 20 -125.5034745328411 30 0.0 0 VERTEX 5 62A 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.74923959923979 20 -125.544811977878 30 0.0 0 VERTEX 5 62B 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.69059492304596 20 -125.5904531007905 30 0.0 0 VERTEX 5 62C 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.62447331305679 20 -125.6403999201894 30 0.0 0 VERTEX 5 62D 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.55087476927229 20 -125.6946544546853 30 0.0 0 VERTEX 5 62E 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.46979929169246 20 -125.7532187228888 30 0.0 0 VERTEX 5 62F 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.37653140587187 20 -125.8225219996752 30 0.0 0 VERTEX 5 630 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.29219385350444 20 -125.8909068086223 30 0.0 0 VERTEX 5 631 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.21678663459019 20 -125.9583751683408 30 0.0 0 VERTEX 5 632 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.15030974912911 20 -126.0249290974411 30 0.0 0 VERTEX 5 633 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.0927631971212 20 -126.090570614534 30 0.0 0 VERTEX 5 634 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.04414697856646 20 -126.1553017382302 30 0.0 0 VERTEX 5 635 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.00446109346489 20 -126.2191244871402 30 0.0 0 VERTEX 5 636 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.97370554181649 20 -126.2820408798747 30 0.0 0 VERTEX 5 637 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.94816574361612 20 -126.3383197444032 30 0.0 0 VERTEX 5 638 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.92580525716728 20 -126.3960520085896 30 0.0 0 VERTEX 5 639 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.90662206385932 20 -126.4552376724339 30 0.0 0 VERTEX 5 63A 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.89061414508162 20 -126.515876735936 30 0.0 0 VERTEX 5 63B 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.87777948222353 20 -126.5779691990959 30 0.0 0 VERTEX 5 63C 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.86811605667443 20 -126.6415150619137 30 0.0 0 VERTEX 5 63D 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.86162184982367 20 -126.7065143243893 30 0.0 0 VERTEX 5 63E 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.85829484306062 20 -126.7729669865228 30 0.0 0 VERTEX 5 63F 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.07210608161394 20 -126.7729669865228 30 0.0 0 VERTEX 5 640 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.28591732016725 20 -126.7729669865228 30 0.0 0 VERTEX 5 641 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.49972855872057 20 -126.7729669865228 30 0.0 0 VERTEX 5 642 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.71353979727389 20 -126.7729669865228 30 0.0 0 VERTEX 5 643 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.92735103582721 20 -126.7729669865228 30 0.0 0 VERTEX 5 644 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.14116227438053 20 -126.7729669865228 30 0.0 0 VERTEX 5 645 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.35497351293385 20 -126.7729669865228 30 0.0 0 VERTEX 5 646 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.7729669865228 30 0.0 0 VERTEX 5 647 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.7189220510979 30 0.0 0 VERTEX 5 648 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.6648771156731 30 0.0 0 VERTEX 5 649 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.6108321802482 30 0.0 0 VERTEX 5 64A 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.5567872448233 30 0.0 0 VERTEX 5 64B 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.5027423093985 30 0.0 0 VERTEX 5 64C 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.4486973739736 30 0.0 0 VERTEX 5 64D 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.3946524385488 30 0.0 0 VERTEX 5 64E 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.56878475148716 20 -126.3406075031239 30 0.0 0 VERTEX 5 64F 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.43248816135197 20 -126.3406075031239 30 0.0 0 VERTEX 5 650 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.29619157121677 20 -126.3406075031239 30 0.0 0 VERTEX 5 651 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.15989498108157 20 -126.3406075031239 30 0.0 0 VERTEX 5 652 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.02359839094638 20 -126.3406075031239 30 0.0 0 VERTEX 5 653 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.88730180081118 20 -126.3406075031239 30 0.0 0 VERTEX 5 654 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.75100521067598 20 -126.3406075031239 30 0.0 0 VERTEX 5 655 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.61470862054079 20 -126.3406075031239 30 0.0 0 VERTEX 5 656 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.47841203040559 20 -126.3406075031239 30 0.0 0 VERTEX 5 657 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.49037801782003 20 -126.3215272589584 30 0.0 0 VERTEX 5 658 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.5030202397975 20 -126.3030425049304 30 0.0 0 VERTEX 5 659 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.51633667772735 20 -126.2851512224295 30 0.0 0 VERTEX 5 65A 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.53032531299895 20 -126.2678513928448 30 0.0 0 VERTEX 5 65B 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.54498412700167 20 -126.2511409975658 30 0.0 0 VERTEX 5 65C 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.56031110112486 20 -126.2350180179818 30 0.0 0 VERTEX 5 65D 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.5763042167579 20 -126.2194804354823 30 0.0 0 VERTEX 5 65E 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.59296145529015 20 -126.2045262314565 30 0.0 0 VERTEX 5 65F 330 5B5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 17.59296145529015 20 -126.2045262314565 30 0.0 0 SEQEND 5 661 330 5B5 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 660 330 5B1 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 168 72 1 10 17.59296145529015 20 -126.2045262314565 11 17.61177490641663 21 -126.1887400234137 72 1 10 17.61177490641663 20 -126.1887400234137 11 17.6342380055728 21 -126.1707050831224 72 1 10 17.6342380055728 20 -126.1707050831224 11 17.66035075275865 21 -126.1504173733615 72 1 10 17.66035075275865 20 -126.1504173733615 11 17.69011314797419 21 -126.1278728569097 72 1 10 17.69011314797419 20 -126.1278728569097 11 17.72352519121942 21 -126.1030674965457 72 1 10 17.72352519121942 20 -126.1030674965457 11 17.76058688249433 21 -126.0759972550482 72 1 10 17.76058688249433 20 -126.0759972550482 11 17.80129822179893 21 -126.046658095196 72 1 10 17.80129822179893 20 -126.046658095196 11 17.84565920913322 21 -126.0150459797678 72 1 10 17.84565920913322 20 -126.0150459797678 11 17.87024857815919 21 -125.9976051838737 72 1 10 17.87024857815919 20 -125.9976051838737 11 17.89483794718516 21 -125.9801643879796 72 1 10 17.89483794718516 20 -125.9801643879796 11 17.91942731621113 21 -125.9627235920856 72 1 10 17.91942731621113 20 -125.9627235920856 11 17.94401668523711 21 -125.9452827961915 72 1 10 17.94401668523711 20 -125.9452827961915 11 17.96860605426308 21 -125.9278420002974 72 1 10 17.96860605426308 20 -125.9278420002974 11 17.99319542328905 21 -125.9104012044033 72 1 10 17.99319542328905 20 -125.9104012044033 11 18.01778479231502 21 -125.8929604085093 72 1 10 18.01778479231502 20 -125.8929604085093 11 18.04237416134099 21 -125.8755196126152 72 1 10 18.04237416134099 20 -125.8755196126152 11 18.10232723366198 21 -125.8321036714936 72 1 10 18.10232723366198 20 -125.8321036714936 11 18.15790597673501 21 -125.7897071287431 72 1 10 18.15790597673501 20 -125.7897071287431 11 18.2091124091707 21 -125.7483320029744 72 1 10 18.2091124091707 20 -125.7483320029744 11 18.2559485495797 21 -125.7079803127981 72 1 10 18.2559485495797 20 -125.7079803127981 11 18.29841641657262 21 -125.6686540768249 72 1 10 18.29841641657262 20 -125.6686540768249 11 18.33651802876013 21 -125.6303553136652 72 1 10 18.33651802876013 20 -125.6303553136652 11 18.37025540475284 21 -125.5930860419299 72 1 10 18.37025540475284 20 -125.5930860419299 11 18.3996305631614 21 -125.5568482802296 72 1 10 18.3996305631614 20 -125.5568482802296 11 18.4384521464757 21 -125.5020638604418 72 1 10 18.4384521464757 20 -125.5020638604418 11 18.47210406795149 21 -125.4453294627797 72 1 10 18.47210406795149 20 -125.4453294627797 11 18.50058430897814 21 -125.3866491244646 72 1 10 18.50058430897814 20 -125.3866491244646 11 18.523890850945 21 -125.3260268827178 72 1 10 18.523890850945 20 -125.3260268827178 11 18.54202167524145 21 -125.2634667747606 72 1 10 18.54202167524145 20 -125.2634667747606 11 18.55497476325684 21 -125.1989728378142 72 1 10 18.55497476325684 20 -125.1989728378142 11 18.56274809638054 21 -125.1325491090998 72 1 10 18.56274809638054 20 -125.1325491090998 11 18.56533965600191 21 -125.0641996258388 72 1 10 18.56533965600191 20 -125.0641996258388 11 18.56167419552225 21 -124.9759863410505 72 1 10 18.56167419552225 20 -124.9759863410505 11 18.55067915982367 21 -124.8922139996611 72 1 10 18.55067915982367 20 -124.8922139996611 11 18.53235656751681 21 -124.8128826016707 72 1 10 18.53235656751681 20 -124.8128826016707 11 18.50670843721232 21 -124.7379921470793 72 1 10 18.50670843721232 20 -124.7379921470793 11 18.47373678752082 21 -124.6675426358867 72 1 10 18.47373678752082 20 -124.6675426358867 11 18.43344363705295 21 -124.6015340680932 72 1 10 18.43344363705295 20 -124.6015340680932 11 18.38583100441936 21 -124.5399664436986 72 1 10 18.38583100441936 20 -124.5399664436986 11 18.33090090823066 21 -124.4828397627029 72 1 10 18.33090090823066 20 -124.4828397627029 11 18.26972052064304 21 -124.4313651914878 72 1 10 18.26972052064304 20 -124.4313651914878 11 18.20348351341253 21 -124.3867538964346 72 1 10 18.20348351341253 20 -124.3867538964346 11 18.13218786792847 21 -124.3490058775435 72 1 10 18.13218786792847 20 -124.3490058775435 11 18.05583156558025 21 -124.3181211348144 72 1 10 18.05583156558025 20 -124.3181211348144 11 17.97441258775721 21 -124.2940996682474 72 1 10 17.97441258775721 20 -124.2940996682474 11 17.88792891584873 21 -124.2769414778423 72 1 10 17.88792891584873 20 -124.2769414778423 11 17.79637853124417 21 -124.2666465635993 72 1 10 17.79637853124417 20 -124.2666465635993 11 17.69975941533289 21 -124.2632149255183 72 1 10 17.69975941533289 20 -124.2632149255183 11 17.57907946994714 21 -124.2690530839124 72 1 10 17.57907946994714 20 -124.2690530839124 11 17.46793140398406 21 -124.2865689048351 72 1 10 17.46793140398406 20 -124.2865689048351 11 17.36631925466491 21 -124.315764406897 72 1 10 17.36631925466491 20 -124.315764406897 11 17.27424705921097 21 -124.3566416087089 72 1 10 17.27424705921097 20 -124.3566416087089 11 17.19171885484351 21 -124.4092025288813 72 1 10 17.19171885484351 20 -124.4092025288813 11 17.11873867878381 21 -124.4734491860248 72 1 10 17.11873867878381 20 -124.4734491860248 11 17.05531056825313 21 -124.5493835987501 72 1 10 17.05531056825313 20 -124.5493835987501 11 17.00143856047275 21 -124.6370077856679 72 1 10 17.00143856047275 20 -124.6370077856679 11 16.97697232669557 21 -124.6880137027804 72 1 10 16.97697232669557 20 -124.6880137027804 11 16.95537655724262 21 -124.7428448870479 72 1 10 16.95537655724262 20 -124.7428448870479 11 16.93664721489263 21 -124.8014993198598 72 1 10 16.93664721489263 20 -124.8014993198598 11 16.92078026242434 21 -124.8639749826055 72 1 10 16.92078026242434 20 -124.8639749826055 11 16.90777166261646 21 -124.9302698566742 72 1 10 16.90777166261646 20 -124.9302698566742 11 16.89761737824773 21 -125.0003819234554 72 1 10 16.89761737824773 20 -125.0003819234554 11 16.89031337209687 21 -125.0743091643385 72 1 10 16.89031337209687 20 -125.0743091643385 11 16.88585560694262 21 -125.1520495607127 72 1 10 16.88585560694262 20 -125.1520495607127 11 16.94549882253101 21 -125.1520495607127 72 1 10 16.94549882253101 20 -125.1520495607127 11 17.00514203811939 21 -125.1520495607127 72 1 10 17.00514203811939 20 -125.1520495607127 11 17.06478525370778 21 -125.1520495607127 72 1 10 17.06478525370778 20 -125.1520495607127 11 17.12442846929617 21 -125.1520495607127 72 1 10 17.12442846929617 20 -125.1520495607127 11 17.18407168488456 21 -125.1520495607127 72 1 10 17.18407168488456 20 -125.1520495607127 11 17.24371490047294 21 -125.1520495607127 72 1 10 17.24371490047294 20 -125.1520495607127 11 17.30335811606133 21 -125.1520495607127 72 1 10 17.30335811606133 20 -125.1520495607127 11 17.36300133164972 21 -125.1520495607127 72 1 10 17.36300133164972 20 -125.1520495607127 11 17.36573015679433 21 -125.1013023621967 72 1 10 17.36573015679433 20 -125.1013023621967 11 17.36965198082476 21 -125.054095806736 72 1 10 17.36965198082476 20 -125.054095806736 11 17.37476478513036 21 -125.0104339315519 72 1 10 17.37476478513036 20 -125.0104339315519 11 17.3810665511005 21 -124.9703207738658 72 1 10 17.3810665511005 20 -124.9703207738658 11 17.38855526012454 21 -124.9337603708988 72 1 10 17.38855526012454 20 -124.9337603708988 11 17.39722889359185 21 -124.9007567598722 72 1 10 17.39722889359185 20 -124.9007567598722 11 17.40708543289179 21 -124.8713139780074 72 1 10 17.40708543289179 20 -124.8713139780074 11 17.41812285941372 21 -124.8454360625255 72 1 10 17.41812285941372 20 -124.8454360625255 11 17.44057788412734 21 -124.806258530869 72 1 10 17.44057788412734 20 -124.806258530869 11 17.4675061500101 21 -124.7723112193702 72 1 10 17.4675061500101 20 -124.7723112193702 11 17.49890765706198 21 -124.7435921094183 72 1 10 17.49890765706198 20 -124.7435921094183 11 17.53478240528299 21 -124.7200991824027 72 1 10 17.53478240528299 20 -124.7200991824027 11 17.57513039467313 21 -124.7018304197128 72 1 10 17.57513039467313 20 -124.7018304197128 11 17.6199516252324 21 -124.688783802738 72 1 10 17.6199516252324 20 -124.688783802738 11 17.6692460969608 21 -124.6809573128675 72 1 10 17.6692460969608 20 -124.6809573128675 11 17.72301380985833 21 -124.6783489314909 72 1 10 17.72301380985833 20 -124.6783489314909 11 17.76272358185242 21 -124.6799883797623 72 1 10 17.76272358185242 20 -124.6799883797623 11 17.80007359801316 21 -124.6849080703171 72 1 10 17.80007359801316 20 -124.6849080703171 11 17.83506183972991 21 -124.6931100217658 72 1 10 17.83506183972991 20 -124.6931100217658 11 17.86768628839204 21 -124.7045962527191 72 1 10 17.86768628839204 20 -124.7045962527191 11 17.8979449253889 21 -124.7193687817877 72 1 10 17.8979449253889 20 -124.7193687817877 11 17.92583573210987 21 -124.737429627582 72 1 10 17.92583573210987 20 -124.737429627582 11 17.9513566899443 21 -124.7587808087129 72 1 10 17.9513566899443 20 -124.7587808087129 11 17.97450578028157 21 -124.783424343791 72 1 10 17.97450578028157 20 -124.783424343791 11 17.99509560876763 21 -124.8105463962948 72 1 10 17.99509560876763 20 -124.8105463962948 11 18.01294012678888 21 -124.8393317839625 72 1 10 18.01294012678888 20 -124.8393317839625 11 18.02803933434533 21 -124.8697805067943 72 1 10 18.02803933434533 20 -124.8697805067943 11 18.04039323143697 21 -124.90189256479 72 1 10 18.04039323143697 20 -124.90189256479 11 18.0500018180638 21 -124.9356679579497 72 1 10 18.0500018180638 20 -124.9356679579497 11 18.05686509422582 21 -124.9711066862734 72 1 10 18.05686509422582 20 -124.9711066862734 11 18.06098305992303 21 -125.008208749761 72 1 10 18.06098305992303 20 -125.008208749761 11 18.06235571515544 21 -125.0469741484126 72 1 10 18.06235571515544 20 -125.0469741484126 11 18.05995794215511 21 -125.0951375253147 72 1 10 18.05995794215511 20 -125.0951375253147 11 18.05276596889454 21 -125.1423440807754 72 1 10 18.05276596889454 20 -125.1423440807754 11 18.04078181398438 21 -125.1885897775734 72 1 10 18.04078181398438 20 -125.1885897775734 11 18.02400749603525 21 -125.2338705784874 72 1 10 18.02400749603525 20 -125.2338705784874 11 18.00244503365779 21 -125.2781824462962 72 1 10 18.00244503365779 20 -125.2781824462962 11 17.97609644546265 21 -125.3215213437785 72 1 10 17.97609644546265 20 -125.3215213437785 11 17.94496375006044 21 -125.3638832337131 72 1 10 17.94496375006044 20 -125.3638832337131 11 17.90904896606182 21 -125.4052640788786 72 1 10 17.90904896606182 20 -125.4052640788786 11 17.88031202504931 21 -125.4337026019521 72 1 10 17.88031202504931 20 -125.4337026019521 11 17.84409815024147 21 -125.4664387470694 72 1 10 17.84409815024147 20 -125.4664387470694 11 17.8004073416383 21 -125.5034745328411 72 1 10 17.8004073416383 20 -125.5034745328411 11 17.74923959923979 21 -125.544811977878 72 1 10 17.74923959923979 20 -125.544811977878 11 17.69059492304596 21 -125.5904531007905 72 1 10 17.69059492304596 20 -125.5904531007905 11 17.62447331305679 21 -125.6403999201894 72 1 10 17.62447331305679 20 -125.6403999201894 11 17.55087476927229 21 -125.6946544546853 72 1 10 17.55087476927229 20 -125.6946544546853 11 17.46979929169246 21 -125.7532187228888 72 1 10 17.46979929169246 20 -125.7532187228888 11 17.37653140587187 21 -125.8225219996752 72 1 10 17.37653140587187 20 -125.8225219996752 11 17.29219385350444 21 -125.8909068086223 72 1 10 17.29219385350444 20 -125.8909068086223 11 17.21678663459019 21 -125.9583751683408 72 1 10 17.21678663459019 20 -125.9583751683408 11 17.15030974912911 21 -126.0249290974411 72 1 10 17.15030974912911 20 -126.0249290974411 11 17.0927631971212 21 -126.090570614534 72 1 10 17.0927631971212 20 -126.090570614534 11 17.04414697856646 21 -126.1553017382302 72 1 10 17.04414697856646 20 -126.1553017382302 11 17.00446109346489 21 -126.2191244871402 72 1 10 17.00446109346489 20 -126.2191244871402 11 16.97370554181649 21 -126.2820408798747 72 1 10 16.97370554181649 20 -126.2820408798747 11 16.94816574361612 21 -126.3383197444032 72 1 10 16.94816574361612 20 -126.3383197444032 11 16.92580525716728 21 -126.3960520085896 72 1 10 16.92580525716728 20 -126.3960520085896 11 16.90662206385932 21 -126.4552376724339 72 1 10 16.90662206385932 20 -126.4552376724339 11 16.89061414508162 21 -126.515876735936 72 1 10 16.89061414508162 20 -126.515876735936 11 16.87777948222353 21 -126.5779691990959 72 1 10 16.87777948222353 20 -126.5779691990959 11 16.86811605667443 21 -126.6415150619137 72 1 10 16.86811605667443 20 -126.6415150619137 11 16.86162184982367 21 -126.7065143243893 72 1 10 16.86162184982367 20 -126.7065143243893 11 16.85829484306062 21 -126.7729669865228 72 1 10 16.85829484306062 20 -126.7729669865228 11 17.07210608161394 21 -126.7729669865228 72 1 10 17.07210608161394 20 -126.7729669865228 11 17.28591732016725 21 -126.7729669865228 72 1 10 17.28591732016725 20 -126.7729669865228 11 17.49972855872057 21 -126.7729669865228 72 1 10 17.49972855872057 20 -126.7729669865228 11 17.71353979727389 21 -126.7729669865228 72 1 10 17.71353979727389 20 -126.7729669865228 11 17.92735103582721 21 -126.7729669865228 72 1 10 17.92735103582721 20 -126.7729669865228 11 18.14116227438053 21 -126.7729669865228 72 1 10 18.14116227438053 20 -126.7729669865228 11 18.35497351293385 21 -126.7729669865228 72 1 10 18.35497351293385 20 -126.7729669865228 11 18.56878475148716 21 -126.7729669865228 72 1 10 18.56878475148716 20 -126.7729669865228 11 18.56878475148716 21 -126.7189220510979 72 1 10 18.56878475148716 20 -126.7189220510979 11 18.56878475148716 21 -126.6648771156731 72 1 10 18.56878475148716 20 -126.6648771156731 11 18.56878475148716 21 -126.6108321802482 72 1 10 18.56878475148716 20 -126.6108321802482 11 18.56878475148716 21 -126.5567872448233 72 1 10 18.56878475148716 20 -126.5567872448233 11 18.56878475148716 21 -126.5027423093985 72 1 10 18.56878475148716 20 -126.5027423093985 11 18.56878475148716 21 -126.4486973739736 72 1 10 18.56878475148716 20 -126.4486973739736 11 18.56878475148716 21 -126.3946524385488 72 1 10 18.56878475148716 20 -126.3946524385488 11 18.56878475148716 21 -126.3406075031239 72 1 10 18.56878475148716 20 -126.3406075031239 11 18.43248816135197 21 -126.3406075031239 72 1 10 18.43248816135197 20 -126.3406075031239 11 18.29619157121677 21 -126.3406075031239 72 1 10 18.29619157121677 20 -126.3406075031239 11 18.15989498108157 21 -126.3406075031239 72 1 10 18.15989498108157 20 -126.3406075031239 11 18.02359839094638 21 -126.3406075031239 72 1 10 18.02359839094638 20 -126.3406075031239 11 17.88730180081118 21 -126.3406075031239 72 1 10 17.88730180081118 20 -126.3406075031239 11 17.75100521067598 21 -126.3406075031239 72 1 10 17.75100521067598 20 -126.3406075031239 11 17.61470862054079 21 -126.3406075031239 72 1 10 17.61470862054079 20 -126.3406075031239 11 17.47841203040559 21 -126.3406075031239 72 1 10 17.47841203040559 20 -126.3406075031239 11 17.49037801782003 21 -126.3215272589584 72 1 10 17.49037801782003 20 -126.3215272589584 11 17.5030202397975 21 -126.3030425049304 72 1 10 17.5030202397975 20 -126.3030425049304 11 17.51633667772735 21 -126.2851512224295 72 1 10 17.51633667772735 20 -126.2851512224295 11 17.53032531299895 21 -126.2678513928448 72 1 10 17.53032531299895 20 -126.2678513928448 11 17.54498412700167 21 -126.2511409975658 72 1 10 17.54498412700167 20 -126.2511409975658 11 17.56031110112486 21 -126.2350180179818 72 1 10 17.56031110112486 20 -126.2350180179818 11 17.5763042167579 21 -126.2194804354823 72 1 10 17.5763042167579 20 -126.2194804354823 11 17.59296145529015 21 -126.2045262314565 97 0 75 2 76 1 98 0 0 POLYLINE 5 662 330 5B1 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 663 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.45626982956043 20 -126.2303644475959 30 0.0 0 VERTEX 5 664 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.39849988464215 20 -125.9808103433831 30 0.0 0 VERTEX 5 665 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.34072993972386 20 -125.7312562391703 30 0.0 0 VERTEX 5 666 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.28295999480558 20 -125.4817021349576 30 0.0 0 VERTEX 5 667 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.2251900498873 20 -125.2321480307448 30 0.0 0 VERTEX 5 668 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.16742010496901 20 -124.982593926532 30 0.0 0 VERTEX 5 669 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.10965016005073 20 -124.7330398223192 30 0.0 0 VERTEX 5 66A 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.05188021513245 20 -124.4834857181064 30 0.0 0 VERTEX 5 66B 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.99411027021416 20 -124.2339316138936 30 0.0 0 VERTEX 5 66C 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.89760453293361 20 -124.2339316138936 30 0.0 0 VERTEX 5 66D 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.80109879565304 20 -124.2339316138936 30 0.0 0 VERTEX 5 66E 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.70459305837248 20 -124.2339316138936 30 0.0 0 VERTEX 5 66F 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.60808732109192 20 -124.2339316138936 30 0.0 0 VERTEX 5 670 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.51158158381136 20 -124.2339316138936 30 0.0 0 VERTEX 5 671 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.4150758465308 20 -124.2339316138936 30 0.0 0 VERTEX 5 672 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.31857010925024 20 -124.2339316138936 30 0.0 0 VERTEX 5 673 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -124.2339316138936 30 0.0 0 VERTEX 5 674 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -124.5513110354723 30 0.0 0 VERTEX 5 675 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -124.8686904570509 30 0.0 0 VERTEX 5 676 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -125.1860698786296 30 0.0 0 VERTEX 5 677 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -125.5034493002082 30 0.0 0 VERTEX 5 678 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -125.8208287217868 30 0.0 0 VERTEX 5 679 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -126.1382081433655 30 0.0 0 VERTEX 5 67A 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -126.4555875649441 30 0.0 0 VERTEX 5 67B 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.22206437196968 20 -126.7729669865228 30 0.0 0 VERTEX 5 67C 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.28386077223634 20 -126.7729669865228 30 0.0 0 VERTEX 5 67D 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.34565717250301 20 -126.7729669865228 30 0.0 0 VERTEX 5 67E 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.40745357276968 20 -126.7729669865228 30 0.0 0 VERTEX 5 67F 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.46924997303635 20 -126.7729669865228 30 0.0 0 VERTEX 5 680 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.53104637330302 20 -126.7729669865228 30 0.0 0 VERTEX 5 681 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.59284277356969 20 -126.7729669865228 30 0.0 0 VERTEX 5 682 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.65463917383636 20 -126.7729669865228 30 0.0 0 VERTEX 5 683 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -126.7729669865228 30 0.0 0 VERTEX 5 684 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -126.5582944740981 30 0.0 0 VERTEX 5 685 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -126.3436219616735 30 0.0 0 VERTEX 5 686 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -126.1289494492489 30 0.0 0 VERTEX 5 687 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -125.9142769368242 30 0.0 0 VERTEX 5 688 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -125.6996044243996 30 0.0 0 VERTEX 5 689 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -125.484931911975 30 0.0 0 VERTEX 5 68A 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -125.2702593995504 30 0.0 0 VERTEX 5 68B 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71643557410303 20 -125.0555868871257 30 0.0 0 VERTEX 5 68C 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71641101434029 20 -125.0361268077255 30 0.0 0 VERTEX 5 68D 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71633598931166 20 -125.0148217182042 30 0.0 0 VERTEX 5 68E 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71620848040649 20 -124.9916675813403 30 0.0 0 VERTEX 5 68F 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71602646901416 20 -124.9666603599127 30 0.0 0 VERTEX 5 690 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71578793652402 20 -124.9397960167001 30 0.0 0 VERTEX 5 691 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71549086432543 20 -124.9110705144812 30 0.0 0 VERTEX 5 692 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71513323380778 20 -124.8804798160347 30 0.0 0 VERTEX 5 693 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.7147130263604 20 -124.8480198841394 30 0.0 0 VERTEX 5 694 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71429281891303 20 -124.8155845120069 30 0.0 0 VERTEX 5 695 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71393518839538 20 -124.785068838589 30 0.0 0 VERTEX 5 696 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71363811619679 20 -124.7564708452753 30 0.0 0 VERTEX 5 697 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71339958370665 20 -124.729788513455 30 0.0 0 VERTEX 5 698 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71321757231432 20 -124.7050198245175 30 0.0 0 VERTEX 5 699 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71309006340915 20 -124.6821627598523 30 0.0 0 VERTEX 5 69A 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71301503838052 20 -124.6612153008485 30 0.0 0 VERTEX 5 69B 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.71299047861778 20 -124.6421754288957 30 0.0 0 VERTEX 5 69C 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.77269828974651 20 -124.9085243735991 30 0.0 0 VERTEX 5 69D 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.83240610087525 20 -125.1748733183025 30 0.0 0 VERTEX 5 69E 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.89211391200399 20 -125.4412222630059 30 0.0 0 VERTEX 5 69F 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.95182172313272 20 -125.7075712077093 30 0.0 0 VERTEX 5 6A0 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.01152953426146 20 -125.9739201524126 30 0.0 0 VERTEX 5 6A1 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.0712373453902 20 -126.240269097116 30 0.0 0 VERTEX 5 6A2 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.13094515651893 20 -126.5066180418194 30 0.0 0 VERTEX 5 6A3 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.19065296764767 20 -126.7729669865228 30 0.0 0 VERTEX 5 6A4 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.25511931691541 20 -126.7729669865228 30 0.0 0 VERTEX 5 6A5 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.31958566618314 20 -126.7729669865228 30 0.0 0 VERTEX 5 6A6 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.38405201545088 20 -126.7729669865228 30 0.0 0 VERTEX 5 6A7 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.44851836471862 20 -126.7729669865228 30 0.0 0 VERTEX 5 6A8 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.51298471398636 20 -126.7729669865228 30 0.0 0 VERTEX 5 6A9 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.5774510632541 20 -126.7729669865228 30 0.0 0 VERTEX 5 6AA 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.64191741252183 20 -126.7729669865228 30 0.0 0 VERTEX 5 6AB 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.70638376178957 20 -126.7729669865228 30 0.0 0 VERTEX 5 6AC 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.76652220985396 20 -126.5066180418194 30 0.0 0 VERTEX 5 6AD 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.82666065791835 20 -126.240269097116 30 0.0 0 VERTEX 5 6AE 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.88679910598275 20 -125.9739201524126 30 0.0 0 VERTEX 5 6AF 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.94693755404714 20 -125.7075712077093 30 0.0 0 VERTEX 5 6B0 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.00707600211153 20 -125.4412222630059 30 0.0 0 VERTEX 5 6B1 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.06721445017592 20 -125.1748733183025 30 0.0 0 VERTEX 5 6B2 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.12735289824032 20 -124.9085243735991 30 0.0 0 VERTEX 5 6B3 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18749134630471 20 -124.6421754288957 30 0.0 0 VERTEX 5 6B4 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18746678654197 20 -124.6612153008485 30 0.0 0 VERTEX 5 6B5 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18739176151334 20 -124.6821627598523 30 0.0 0 VERTEX 5 6B6 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18726425260817 20 -124.7050198245175 30 0.0 0 VERTEX 5 6B7 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18708224121584 20 -124.729788513455 30 0.0 0 VERTEX 5 6B8 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.1868437087257 20 -124.7564708452753 30 0.0 0 VERTEX 5 6B9 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18654663652712 20 -124.785068838589 30 0.0 0 VERTEX 5 6BA 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18618900600946 20 -124.8155845120069 30 0.0 0 VERTEX 5 6BB 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18576879856208 20 -124.8480198841394 30 0.0 0 VERTEX 5 6BC 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18534859111471 20 -124.8804798160347 30 0.0 0 VERTEX 5 6BD 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18499096059706 20 -124.9110705144812 30 0.0 0 VERTEX 5 6BE 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18469388839847 20 -124.9397960167001 30 0.0 0 VERTEX 5 6BF 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18445535590833 20 -124.9666603599127 30 0.0 0 VERTEX 5 6C0 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.184273344516 20 -124.9916675813403 30 0.0 0 VERTEX 5 6C1 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18414583561083 20 -125.0148217182042 30 0.0 0 VERTEX 5 6C2 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.1840708105822 20 -125.0361268077255 30 0.0 0 VERTEX 5 6C3 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -125.0555868871257 30 0.0 0 VERTEX 5 6C4 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -125.2702593995504 30 0.0 0 VERTEX 5 6C5 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -125.484931911975 30 0.0 0 VERTEX 5 6C6 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -125.6996044243996 30 0.0 0 VERTEX 5 6C7 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -125.9142769368242 30 0.0 0 VERTEX 5 6C8 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -126.1289494492489 30 0.0 0 VERTEX 5 6C9 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -126.3436219616735 30 0.0 0 VERTEX 5 6CA 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -126.5582944740981 30 0.0 0 VERTEX 5 6CB 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.18404625081946 20 -126.7729669865228 30 0.0 0 VERTEX 5 6CC 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.24584265108613 20 -126.7729669865228 30 0.0 0 VERTEX 5 6CD 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.3076390513528 20 -126.7729669865228 30 0.0 0 VERTEX 5 6CE 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.36943545161947 20 -126.7729669865228 30 0.0 0 VERTEX 5 6CF 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.43123185188614 20 -126.7729669865228 30 0.0 0 VERTEX 5 6D0 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.4930282521528 20 -126.7729669865228 30 0.0 0 VERTEX 5 6D1 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.55482465241947 20 -126.7729669865228 30 0.0 0 VERTEX 5 6D2 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.61662105268614 20 -126.7729669865228 30 0.0 0 VERTEX 5 6D3 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -126.7729669865228 30 0.0 0 VERTEX 5 6D4 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -126.4555875649441 30 0.0 0 VERTEX 5 6D5 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -126.1382081433655 30 0.0 0 VERTEX 5 6D6 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -125.8208287217868 30 0.0 0 VERTEX 5 6D7 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -125.5034493002082 30 0.0 0 VERTEX 5 6D8 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -125.1860698786296 30 0.0 0 VERTEX 5 6D9 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -124.8686904570509 30 0.0 0 VERTEX 5 6DA 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -124.5513110354723 30 0.0 0 VERTEX 5 6DB 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.67841745295281 20 -124.2339316138936 30 0.0 0 VERTEX 5 6DC 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.58298830801139 20 -124.2339316138936 30 0.0 0 VERTEX 5 6DD 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.48755916306997 20 -124.2339316138936 30 0.0 0 VERTEX 5 6DE 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.39213001812855 20 -124.2339316138936 30 0.0 0 VERTEX 5 6DF 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.29670087318713 20 -124.2339316138936 30 0.0 0 VERTEX 5 6E0 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.20127172824571 20 -124.2339316138936 30 0.0 0 VERTEX 5 6E1 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.10584258330429 20 -124.2339316138936 30 0.0 0 VERTEX 5 6E2 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.01041343836287 20 -124.2339316138936 30 0.0 0 VERTEX 5 6E3 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.91498429342145 20 -124.2339316138936 30 0.0 0 VERTEX 5 6E4 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.85764498543882 20 -124.4834857181064 30 0.0 0 VERTEX 5 6E5 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.80030567745619 20 -124.7330398223192 30 0.0 0 VERTEX 5 6E6 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.74296636947357 20 -124.982593926532 30 0.0 0 VERTEX 5 6E7 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.68562706149094 20 -125.2321480307448 30 0.0 0 VERTEX 5 6E8 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.62828775350831 20 -125.4817021349576 30 0.0 0 VERTEX 5 6E9 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.57094844552569 20 -125.7312562391703 30 0.0 0 VERTEX 5 6EA 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.51360913754306 20 -125.9808103433831 30 0.0 0 VERTEX 5 6EB 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.45626982956043 20 -126.2303644475959 30 0.0 0 VERTEX 5 6EC 330 662 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.45626982956043 20 -126.2303644475959 30 0.0 0 SEQEND 5 6EE 330 662 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 6ED 330 5B1 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 136 72 1 10 27.45626982956043 20 -126.2303644475959 11 27.39849988464215 21 -125.9808103433831 72 1 10 27.39849988464215 20 -125.9808103433831 11 27.34072993972386 21 -125.7312562391703 72 1 10 27.34072993972386 20 -125.7312562391703 11 27.28295999480558 21 -125.4817021349576 72 1 10 27.28295999480558 20 -125.4817021349576 11 27.2251900498873 21 -125.2321480307448 72 1 10 27.2251900498873 20 -125.2321480307448 11 27.16742010496901 21 -124.982593926532 72 1 10 27.16742010496901 20 -124.982593926532 11 27.10965016005073 21 -124.7330398223192 72 1 10 27.10965016005073 20 -124.7330398223192 11 27.05188021513245 21 -124.4834857181064 72 1 10 27.05188021513245 20 -124.4834857181064 11 26.99411027021416 21 -124.2339316138936 72 1 10 26.99411027021416 20 -124.2339316138936 11 26.89760453293361 21 -124.2339316138936 72 1 10 26.89760453293361 20 -124.2339316138936 11 26.80109879565304 21 -124.2339316138936 72 1 10 26.80109879565304 20 -124.2339316138936 11 26.70459305837248 21 -124.2339316138936 72 1 10 26.70459305837248 20 -124.2339316138936 11 26.60808732109192 21 -124.2339316138936 72 1 10 26.60808732109192 20 -124.2339316138936 11 26.51158158381136 21 -124.2339316138936 72 1 10 26.51158158381136 20 -124.2339316138936 11 26.4150758465308 21 -124.2339316138936 72 1 10 26.4150758465308 20 -124.2339316138936 11 26.31857010925024 21 -124.2339316138936 72 1 10 26.31857010925024 20 -124.2339316138936 11 26.22206437196968 21 -124.2339316138936 72 1 10 26.22206437196968 20 -124.2339316138936 11 26.22206437196968 21 -124.5513110354723 72 1 10 26.22206437196968 20 -124.5513110354723 11 26.22206437196968 21 -124.8686904570509 72 1 10 26.22206437196968 20 -124.8686904570509 11 26.22206437196968 21 -125.1860698786296 72 1 10 26.22206437196968 20 -125.1860698786296 11 26.22206437196968 21 -125.5034493002082 72 1 10 26.22206437196968 20 -125.5034493002082 11 26.22206437196968 21 -125.8208287217868 72 1 10 26.22206437196968 20 -125.8208287217868 11 26.22206437196968 21 -126.1382081433655 72 1 10 26.22206437196968 20 -126.1382081433655 11 26.22206437196968 21 -126.4555875649441 72 1 10 26.22206437196968 20 -126.4555875649441 11 26.22206437196968 21 -126.7729669865228 72 1 10 26.22206437196968 20 -126.7729669865228 11 26.28386077223634 21 -126.7729669865228 72 1 10 26.28386077223634 20 -126.7729669865228 11 26.34565717250301 21 -126.7729669865228 72 1 10 26.34565717250301 20 -126.7729669865228 11 26.40745357276968 21 -126.7729669865228 72 1 10 26.40745357276968 20 -126.7729669865228 11 26.46924997303635 21 -126.7729669865228 72 1 10 26.46924997303635 20 -126.7729669865228 11 26.53104637330302 21 -126.7729669865228 72 1 10 26.53104637330302 20 -126.7729669865228 11 26.59284277356969 21 -126.7729669865228 72 1 10 26.59284277356969 20 -126.7729669865228 11 26.65463917383636 21 -126.7729669865228 72 1 10 26.65463917383636 20 -126.7729669865228 11 26.71643557410303 21 -126.7729669865228 72 1 10 26.71643557410303 20 -126.7729669865228 11 26.71643557410303 21 -126.5582944740981 72 1 10 26.71643557410303 20 -126.5582944740981 11 26.71643557410303 21 -126.3436219616735 72 1 10 26.71643557410303 20 -126.3436219616735 11 26.71643557410303 21 -126.1289494492489 72 1 10 26.71643557410303 20 -126.1289494492489 11 26.71643557410303 21 -125.9142769368242 72 1 10 26.71643557410303 20 -125.9142769368242 11 26.71643557410303 21 -125.6996044243996 72 1 10 26.71643557410303 20 -125.6996044243996 11 26.71643557410303 21 -125.484931911975 72 1 10 26.71643557410303 20 -125.484931911975 11 26.71643557410303 21 -125.2702593995504 72 1 10 26.71643557410303 20 -125.2702593995504 11 26.71643557410303 21 -125.0555868871257 72 1 10 26.71643557410303 20 -125.0555868871257 11 26.71641101434029 21 -125.0361268077255 72 1 10 26.71641101434029 20 -125.0361268077255 11 26.71633598931166 21 -125.0148217182042 72 1 10 26.71633598931166 20 -125.0148217182042 11 26.71620848040649 21 -124.9916675813403 72 1 10 26.71620848040649 20 -124.9916675813403 11 26.71602646901416 21 -124.9666603599127 72 1 10 26.71602646901416 20 -124.9666603599127 11 26.71578793652402 21 -124.9397960167001 72 1 10 26.71578793652402 20 -124.9397960167001 11 26.71549086432543 21 -124.9110705144812 72 1 10 26.71549086432543 20 -124.9110705144812 11 26.71513323380778 21 -124.8804798160347 72 1 10 26.71513323380778 20 -124.8804798160347 11 26.7147130263604 21 -124.8480198841394 72 1 10 26.7147130263604 20 -124.8480198841394 11 26.71429281891303 21 -124.8155845120069 72 1 10 26.71429281891303 20 -124.8155845120069 11 26.71393518839538 21 -124.785068838589 72 1 10 26.71393518839538 20 -124.785068838589 11 26.71363811619679 21 -124.7564708452753 72 1 10 26.71363811619679 20 -124.7564708452753 11 26.71339958370665 21 -124.729788513455 72 1 10 26.71339958370665 20 -124.729788513455 11 26.71321757231432 21 -124.7050198245175 72 1 10 26.71321757231432 20 -124.7050198245175 11 26.71309006340915 21 -124.6821627598523 72 1 10 26.71309006340915 20 -124.6821627598523 11 26.71301503838052 21 -124.6612153008485 72 1 10 26.71301503838052 20 -124.6612153008485 11 26.71299047861778 21 -124.6421754288957 72 1 10 26.71299047861778 20 -124.6421754288957 11 26.77269828974651 21 -124.9085243735991 72 1 10 26.77269828974651 20 -124.9085243735991 11 26.83240610087525 21 -125.1748733183025 72 1 10 26.83240610087525 20 -125.1748733183025 11 26.89211391200399 21 -125.4412222630059 72 1 10 26.89211391200399 20 -125.4412222630059 11 26.95182172313272 21 -125.7075712077093 72 1 10 26.95182172313272 20 -125.7075712077093 11 27.01152953426146 21 -125.9739201524126 72 1 10 27.01152953426146 20 -125.9739201524126 11 27.0712373453902 21 -126.240269097116 72 1 10 27.0712373453902 20 -126.240269097116 11 27.13094515651893 21 -126.5066180418194 72 1 10 27.13094515651893 20 -126.5066180418194 11 27.19065296764767 21 -126.7729669865228 72 1 10 27.19065296764767 20 -126.7729669865228 11 27.25511931691541 21 -126.7729669865228 72 1 10 27.25511931691541 20 -126.7729669865228 11 27.31958566618314 21 -126.7729669865228 72 1 10 27.31958566618314 20 -126.7729669865228 11 27.38405201545088 21 -126.7729669865228 72 1 10 27.38405201545088 20 -126.7729669865228 11 27.44851836471862 21 -126.7729669865228 72 1 10 27.44851836471862 20 -126.7729669865228 11 27.51298471398636 21 -126.7729669865228 72 1 10 27.51298471398636 20 -126.7729669865228 11 27.5774510632541 21 -126.7729669865228 72 1 10 27.5774510632541 20 -126.7729669865228 11 27.64191741252183 21 -126.7729669865228 72 1 10 27.64191741252183 20 -126.7729669865228 11 27.70638376178957 21 -126.7729669865228 72 1 10 27.70638376178957 20 -126.7729669865228 11 27.76652220985396 21 -126.5066180418194 72 1 10 27.76652220985396 20 -126.5066180418194 11 27.82666065791835 21 -126.240269097116 72 1 10 27.82666065791835 20 -126.240269097116 11 27.88679910598275 21 -125.9739201524126 72 1 10 27.88679910598275 20 -125.9739201524126 11 27.94693755404714 21 -125.7075712077093 72 1 10 27.94693755404714 20 -125.7075712077093 11 28.00707600211153 21 -125.4412222630059 72 1 10 28.00707600211153 20 -125.4412222630059 11 28.06721445017592 21 -125.1748733183025 72 1 10 28.06721445017592 20 -125.1748733183025 11 28.12735289824032 21 -124.9085243735991 72 1 10 28.12735289824032 20 -124.9085243735991 11 28.18749134630471 21 -124.6421754288957 72 1 10 28.18749134630471 20 -124.6421754288957 11 28.18746678654197 21 -124.6612153008485 72 1 10 28.18746678654197 20 -124.6612153008485 11 28.18739176151334 21 -124.6821627598523 72 1 10 28.18739176151334 20 -124.6821627598523 11 28.18726425260817 21 -124.7050198245175 72 1 10 28.18726425260817 20 -124.7050198245175 11 28.18708224121584 21 -124.729788513455 72 1 10 28.18708224121584 20 -124.729788513455 11 28.1868437087257 21 -124.7564708452753 72 1 10 28.1868437087257 20 -124.7564708452753 11 28.18654663652712 21 -124.785068838589 72 1 10 28.18654663652712 20 -124.785068838589 11 28.18618900600946 21 -124.8155845120069 72 1 10 28.18618900600946 20 -124.8155845120069 11 28.18576879856208 21 -124.8480198841394 72 1 10 28.18576879856208 20 -124.8480198841394 11 28.18534859111471 21 -124.8804798160347 72 1 10 28.18534859111471 20 -124.8804798160347 11 28.18499096059706 21 -124.9110705144812 72 1 10 28.18499096059706 20 -124.9110705144812 11 28.18469388839847 21 -124.9397960167001 72 1 10 28.18469388839847 20 -124.9397960167001 11 28.18445535590833 21 -124.9666603599127 72 1 10 28.18445535590833 20 -124.9666603599127 11 28.184273344516 21 -124.9916675813403 72 1 10 28.184273344516 20 -124.9916675813403 11 28.18414583561083 21 -125.0148217182042 72 1 10 28.18414583561083 20 -125.0148217182042 11 28.1840708105822 21 -125.0361268077255 72 1 10 28.1840708105822 20 -125.0361268077255 11 28.18404625081946 21 -125.0555868871257 72 1 10 28.18404625081946 20 -125.0555868871257 11 28.18404625081946 21 -125.2702593995504 72 1 10 28.18404625081946 20 -125.2702593995504 11 28.18404625081946 21 -125.484931911975 72 1 10 28.18404625081946 20 -125.484931911975 11 28.18404625081946 21 -125.6996044243996 72 1 10 28.18404625081946 20 -125.6996044243996 11 28.18404625081946 21 -125.9142769368242 72 1 10 28.18404625081946 20 -125.9142769368242 11 28.18404625081946 21 -126.1289494492489 72 1 10 28.18404625081946 20 -126.1289494492489 11 28.18404625081946 21 -126.3436219616735 72 1 10 28.18404625081946 20 -126.3436219616735 11 28.18404625081946 21 -126.5582944740981 72 1 10 28.18404625081946 20 -126.5582944740981 11 28.18404625081946 21 -126.7729669865228 72 1 10 28.18404625081946 20 -126.7729669865228 11 28.24584265108613 21 -126.7729669865228 72 1 10 28.24584265108613 20 -126.7729669865228 11 28.3076390513528 21 -126.7729669865228 72 1 10 28.3076390513528 20 -126.7729669865228 11 28.36943545161947 21 -126.7729669865228 72 1 10 28.36943545161947 20 -126.7729669865228 11 28.43123185188614 21 -126.7729669865228 72 1 10 28.43123185188614 20 -126.7729669865228 11 28.4930282521528 21 -126.7729669865228 72 1 10 28.4930282521528 20 -126.7729669865228 11 28.55482465241947 21 -126.7729669865228 72 1 10 28.55482465241947 20 -126.7729669865228 11 28.61662105268614 21 -126.7729669865228 72 1 10 28.61662105268614 20 -126.7729669865228 11 28.67841745295281 21 -126.7729669865228 72 1 10 28.67841745295281 20 -126.7729669865228 11 28.67841745295281 21 -126.4555875649441 72 1 10 28.67841745295281 20 -126.4555875649441 11 28.67841745295281 21 -126.1382081433655 72 1 10 28.67841745295281 20 -126.1382081433655 11 28.67841745295281 21 -125.8208287217868 72 1 10 28.67841745295281 20 -125.8208287217868 11 28.67841745295281 21 -125.5034493002082 72 1 10 28.67841745295281 20 -125.5034493002082 11 28.67841745295281 21 -125.1860698786296 72 1 10 28.67841745295281 20 -125.1860698786296 11 28.67841745295281 21 -124.8686904570509 72 1 10 28.67841745295281 20 -124.8686904570509 11 28.67841745295281 21 -124.5513110354723 72 1 10 28.67841745295281 20 -124.5513110354723 11 28.67841745295281 21 -124.2339316138936 72 1 10 28.67841745295281 20 -124.2339316138936 11 28.58298830801139 21 -124.2339316138936 72 1 10 28.58298830801139 20 -124.2339316138936 11 28.48755916306997 21 -124.2339316138936 72 1 10 28.48755916306997 20 -124.2339316138936 11 28.39213001812855 21 -124.2339316138936 72 1 10 28.39213001812855 20 -124.2339316138936 11 28.29670087318713 21 -124.2339316138936 72 1 10 28.29670087318713 20 -124.2339316138936 11 28.20127172824571 21 -124.2339316138936 72 1 10 28.20127172824571 20 -124.2339316138936 11 28.10584258330429 21 -124.2339316138936 72 1 10 28.10584258330429 20 -124.2339316138936 11 28.01041343836287 21 -124.2339316138936 72 1 10 28.01041343836287 20 -124.2339316138936 11 27.91498429342145 21 -124.2339316138936 72 1 10 27.91498429342145 20 -124.2339316138936 11 27.85764498543882 21 -124.4834857181064 72 1 10 27.85764498543882 20 -124.4834857181064 11 27.80030567745619 21 -124.7330398223192 72 1 10 27.80030567745619 20 -124.7330398223192 11 27.74296636947357 21 -124.982593926532 72 1 10 27.74296636947357 20 -124.982593926532 11 27.68562706149094 21 -125.2321480307448 72 1 10 27.68562706149094 20 -125.2321480307448 11 27.62828775350831 21 -125.4817021349576 72 1 10 27.62828775350831 20 -125.4817021349576 11 27.57094844552569 21 -125.7312562391703 72 1 10 27.57094844552569 20 -125.7312562391703 11 27.51360913754306 21 -125.9808103433831 72 1 10 27.51360913754306 20 -125.9808103433831 11 27.45626982956043 21 -126.2303644475959 97 0 75 2 76 1 98 0 0 POLYLINE 5 6EF 330 5B1 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 6F0 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.82502796873908 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F1 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.68875291045066 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F2 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.55247785216225 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F3 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.41620279387383 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F4 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.27992773558542 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F5 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.14365267729701 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F6 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.00737761900859 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F7 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.87110256072018 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F8 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -124.2339316138936 30 0.0 0 VERTEX 5 6F9 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -124.5513110354723 30 0.0 0 VERTEX 5 6FA 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -124.8686904570509 30 0.0 0 VERTEX 5 6FB 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -125.1860698786296 30 0.0 0 VERTEX 5 6FC 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -125.5034493002082 30 0.0 0 VERTEX 5 6FD 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -125.8208287217868 30 0.0 0 VERTEX 5 6FE 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -126.1382081433655 30 0.0 0 VERTEX 5 6FF 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -126.4555875649441 30 0.0 0 VERTEX 5 700 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.73482750243176 20 -126.7729669865228 30 0.0 0 VERTEX 5 701 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.80071495358717 20 -126.7729669865228 30 0.0 0 VERTEX 5 702 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.86660240474257 20 -126.7729669865228 30 0.0 0 VERTEX 5 703 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.93248985589797 20 -126.7729669865228 30 0.0 0 VERTEX 5 704 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.99837730705338 20 -126.7729669865228 30 0.0 0 VERTEX 5 705 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.06426475820878 20 -126.7729669865228 30 0.0 0 VERTEX 5 706 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.13015220936418 20 -126.7729669865228 30 0.0 0 VERTEX 5 707 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.19603966051958 20 -126.7729669865228 30 0.0 0 VERTEX 5 708 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -126.7729669865228 30 0.0 0 VERTEX 5 709 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -126.6588481985739 30 0.0 0 VERTEX 5 70A 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -126.544729410625 30 0.0 0 VERTEX 5 70B 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -126.4306106226761 30 0.0 0 VERTEX 5 70C 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -126.3164918347272 30 0.0 0 VERTEX 5 70D 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -126.2023730467783 30 0.0 0 VERTEX 5 70E 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -126.0882542588294 30 0.0 0 VERTEX 5 70F 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -125.9741354708805 30 0.0 0 VERTEX 5 710 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -125.8600166829316 30 0.0 0 VERTEX 5 711 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.32800834945144 20 -125.8600166829316 30 0.0 0 VERTEX 5 712 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.39408958722789 20 -125.8600166829316 30 0.0 0 VERTEX 5 713 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.46017082500433 20 -125.8600166829316 30 0.0 0 VERTEX 5 714 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.52625206278078 20 -125.8600166829316 30 0.0 0 VERTEX 5 715 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.59233330055723 20 -125.8600166829316 30 0.0 0 VERTEX 5 716 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.65841453833368 20 -125.8600166829316 30 0.0 0 VERTEX 5 717 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.72449577611013 20 -125.8600166829316 30 0.0 0 VERTEX 5 718 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.79057701388658 20 -125.8600166829316 30 0.0 0 VERTEX 5 719 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.89107186221876 20 -125.8571098836159 30 0.0 0 VERTEX 5 71A 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98559364167935 20 -125.8483894856688 30 0.0 0 VERTEX 5 71B 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.07414437087898 20 -125.8338554890904 30 0.0 0 VERTEX 5 71C 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.15672606842829 20 -125.8135078938807 30 0.0 0 VERTEX 5 71D 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.23334075293791 20 -125.7873467000396 30 0.0 0 VERTEX 5 71E 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.30399044301848 20 -125.7553719075671 30 0.0 0 VERTEX 5 71F 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.36867715728063 20 -125.7175835164633 30 0.0 0 VERTEX 5 720 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.42740291433501 20 -125.6739815267281 30 0.0 0 VERTEX 5 721 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.47961158695142 20 -125.62335477198 30 0.0 0 VERTEX 5 722 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.5248722017591 20 -125.5644920858375 30 0.0 0 VERTEX 5 723 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.56318072153678 20 -125.4973934683005 30 0.0 0 VERTEX 5 724 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59453310906319 20 -125.4220589193692 30 0.0 0 VERTEX 5 725 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.61892532711706 20 -125.3384884390434 30 0.0 0 VERTEX 5 726 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.63635333847711 20 -125.2466820273232 30 0.0 0 VERTEX 5 727 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.64681310592207 20 -125.1466396842085 30 0.0 0 VERTEX 5 728 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.65030059223067 20 -125.0383614096995 30 0.0 0 VERTEX 5 729 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.64679662060188 20 -124.9388200184576 30 0.0 0 VERTEX 5 72A 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.63628605145591 20 -124.8459985820227 30 0.0 0 VERTEX 5 72B 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.61877090340341 20 -124.7598991190052 30 0.0 0 VERTEX 5 72C 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59425319505501 20 -124.6805236480159 30 0.0 0 VERTEX 5 72D 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.56273494502136 20 -124.6078741876654 30 0.0 0 VERTEX 5 72E 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.52421817191307 20 -124.5419527565643 30 0.0 0 VERTEX 5 72F 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.4787048943408 20 -124.4827613733232 30 0.0 0 VERTEX 5 730 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.42619713091517 20 -124.4303020565529 30 0.0 0 VERTEX 5 731 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.36774590490728 20 -124.3842777340546 30 0.0 0 VERTEX 5 732 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.30452873918805 20 -124.3443899878895 30 0.0 0 VERTEX 5 733 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.23654361514685 20 -124.3106388180574 30 0.0 0 VERTEX 5 734 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.16378851417305 20 -124.2830242245584 30 0.0 0 VERTEX 5 735 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.086261417656 20 -124.2615462073926 30 0.0 0 VERTEX 5 736 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.00396030698509 20 -124.2462047665598 30 0.0 0 VERTEX 5 737 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.91688316354966 20 -124.2369999020602 30 0.0 0 VERTEX 5 738 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.82502796873908 20 -124.2339316138936 30 0.0 0 VERTEX 5 739 330 6EF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.82502796873908 20 -124.2339316138936 30 0.0 0 SEQEND 5 73A 330 6EF 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 73B 330 5B1 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 73C 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02243194004389 20 -125.3311945259457 30 0.0 0 VERTEX 5 73D 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.99597266469888 20 -125.3525753133659 30 0.0 0 VERTEX 5 73E 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.96698205161645 20 -125.3711118784002 30 0.0 0 VERTEX 5 73F 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9354641380179 20 -125.3868022024378 30 0.0 0 VERTEX 5 740 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.90142296112449 20 -125.3996442668683 30 0.0 0 VERTEX 5 741 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.86486255815749 20 -125.4096360530808 30 0.0 0 VERTEX 5 742 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.82578696633817 20 -125.4167755424648 30 0.0 0 VERTEX 5 743 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.7842002228878 20 -125.4210607164097 30 0.0 0 VERTEX 5 744 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.74010636502767 20 -125.4224895563048 30 0.0 0 VERTEX 5 745 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.68033395835858 20 -125.4224895563048 30 0.0 0 VERTEX 5 746 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.6205615516895 20 -125.4224895563048 30 0.0 0 VERTEX 5 747 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.56078914502041 20 -125.4224895563048 30 0.0 0 VERTEX 5 748 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.50101673835133 20 -125.4224895563048 30 0.0 0 VERTEX 5 749 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.44124433168224 20 -125.4224895563048 30 0.0 0 VERTEX 5 74A 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.38147192501316 20 -125.4224895563048 30 0.0 0 VERTEX 5 74B 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.32169951834407 20 -125.4224895563048 30 0.0 0 VERTEX 5 74C 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -125.4224895563048 30 0.0 0 VERTEX 5 74D 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -125.3290413412674 30 0.0 0 VERTEX 5 74E 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -125.23559312623 30 0.0 0 VERTEX 5 74F 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -125.1421449111926 30 0.0 0 VERTEX 5 750 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -125.0486966961552 30 0.0 0 VERTEX 5 751 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -124.9552484811178 30 0.0 0 VERTEX 5 752 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -124.8618002660804 30 0.0 0 VERTEX 5 753 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -124.768352051043 30 0.0 0 VERTEX 5 754 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.26192711167499 20 -124.6749038360056 30 0.0 0 VERTEX 5 755 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.32169951834407 20 -124.6749038360056 30 0.0 0 VERTEX 5 756 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.38147192501316 20 -124.6749038360056 30 0.0 0 VERTEX 5 757 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.44124433168224 20 -124.6749038360056 30 0.0 0 VERTEX 5 758 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.50101673835133 20 -124.6749038360056 30 0.0 0 VERTEX 5 759 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.56078914502041 20 -124.6749038360056 30 0.0 0 VERTEX 5 75A 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.6205615516895 20 -124.6749038360056 30 0.0 0 VERTEX 5 75B 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.68033395835858 20 -124.6749038360056 30 0.0 0 VERTEX 5 75C 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.74010636502767 20 -124.6749038360056 30 0.0 0 VERTEX 5 75D 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.7842002228878 20 -124.6762203065753 30 0.0 0 VERTEX 5 75E 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.82578696633817 20 -124.6801710640249 30 0.0 0 VERTEX 5 75F 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.86486255815749 20 -124.6867581269649 30 0.0 0 VERTEX 5 760 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.90142296112449 20 -124.695983514006 30 0.0 0 VERTEX 5 761 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9354641380179 20 -124.7078492437588 30 0.0 0 VERTEX 5 762 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.96698205161645 20 -124.7223573348341 30 0.0 0 VERTEX 5 763 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.99597266469888 20 -124.7395098058423 30 0.0 0 VERTEX 5 764 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02243194004389 20 -124.7593086753942 30 0.0 0 VERTEX 5 765 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.04604968448379 20 -124.7822003928754 30 0.0 0 VERTEX 5 766 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.0665183963317 20 -124.808632753412 30 0.0 0 VERTEX 5 767 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.08383807558762 20 -124.8386097942251 30 0.0 0 VERTEX 5 768 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.09800872225156 20 -124.8721355525362 30 0.0 0 VERTEX 5 769 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.10903033632351 20 -124.9092140655664 30 0.0 0 VERTEX 5 76A 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.11690291780348 20 -124.949849370537 30 0.0 0 VERTEX 5 76B 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.12162646669146 20 -124.9940455046694 30 0.0 0 VERTEX 5 76C 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.12320098298745 20 -125.0418065051847 30 0.0 0 VERTEX 5 76D 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.12162646669146 20 -125.0896798750255 30 0.0 0 VERTEX 5 76E 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.11690291780348 20 -125.1342104256532 30 0.0 0 VERTEX 5 76F 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.10903033632351 20 -125.1753981570678 30 0.0 0 VERTEX 5 770 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.09800872225156 20 -125.2132430692695 30 0.0 0 VERTEX 5 771 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.08383807558762 20 -125.2477451622581 30 0.0 0 VERTEX 5 772 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.0665183963317 20 -125.2789044360336 30 0.0 0 VERTEX 5 773 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.04604968448379 20 -125.3067208905962 30 0.0 0 VERTEX 5 774 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02243194004389 20 -125.3311945259457 30 0.0 0 VERTEX 5 775 330 73B 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02243194004389 20 -125.3311945259457 30 0.0 0 SEQEND 5 776 330 73B 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 777 330 5B1 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 72 72 1 10 22.82502796873908 20 -124.2339316138936 11 22.68875291045066 21 -124.2339316138936 72 1 10 22.68875291045066 20 -124.2339316138936 11 22.55247785216225 21 -124.2339316138936 72 1 10 22.55247785216225 20 -124.2339316138936 11 22.41620279387383 21 -124.2339316138936 72 1 10 22.41620279387383 20 -124.2339316138936 11 22.27992773558542 21 -124.2339316138936 72 1 10 22.27992773558542 20 -124.2339316138936 11 22.14365267729701 21 -124.2339316138936 72 1 10 22.14365267729701 20 -124.2339316138936 11 22.00737761900859 21 -124.2339316138936 72 1 10 22.00737761900859 20 -124.2339316138936 11 21.87110256072018 21 -124.2339316138936 72 1 10 21.87110256072018 20 -124.2339316138936 11 21.73482750243176 21 -124.2339316138936 72 1 10 21.73482750243176 20 -124.2339316138936 11 21.73482750243176 21 -124.5513110354723 72 1 10 21.73482750243176 20 -124.5513110354723 11 21.73482750243176 21 -124.8686904570509 72 1 10 21.73482750243176 20 -124.8686904570509 11 21.73482750243176 21 -125.1860698786296 72 1 10 21.73482750243176 20 -125.1860698786296 11 21.73482750243176 21 -125.5034493002082 72 1 10 21.73482750243176 20 -125.5034493002082 11 21.73482750243176 21 -125.8208287217868 72 1 10 21.73482750243176 20 -125.8208287217868 11 21.73482750243176 21 -126.1382081433655 72 1 10 21.73482750243176 20 -126.1382081433655 11 21.73482750243176 21 -126.4555875649441 72 1 10 21.73482750243176 20 -126.4555875649441 11 21.73482750243176 21 -126.7729669865228 72 1 10 21.73482750243176 20 -126.7729669865228 11 21.80071495358717 21 -126.7729669865228 72 1 10 21.80071495358717 20 -126.7729669865228 11 21.86660240474257 21 -126.7729669865228 72 1 10 21.86660240474257 20 -126.7729669865228 11 21.93248985589797 21 -126.7729669865228 72 1 10 21.93248985589797 20 -126.7729669865228 11 21.99837730705338 21 -126.7729669865228 72 1 10 21.99837730705338 20 -126.7729669865228 11 22.06426475820878 21 -126.7729669865228 72 1 10 22.06426475820878 20 -126.7729669865228 11 22.13015220936418 21 -126.7729669865228 72 1 10 22.13015220936418 20 -126.7729669865228 11 22.19603966051958 21 -126.7729669865228 72 1 10 22.19603966051958 20 -126.7729669865228 11 22.26192711167499 21 -126.7729669865228 72 1 10 22.26192711167499 20 -126.7729669865228 11 22.26192711167499 21 -126.6588481985739 72 1 10 22.26192711167499 20 -126.6588481985739 11 22.26192711167499 21 -126.544729410625 72 1 10 22.26192711167499 20 -126.544729410625 11 22.26192711167499 21 -126.4306106226761 72 1 10 22.26192711167499 20 -126.4306106226761 11 22.26192711167499 21 -126.3164918347272 72 1 10 22.26192711167499 20 -126.3164918347272 11 22.26192711167499 21 -126.2023730467783 72 1 10 22.26192711167499 20 -126.2023730467783 11 22.26192711167499 21 -126.0882542588294 72 1 10 22.26192711167499 20 -126.0882542588294 11 22.26192711167499 21 -125.9741354708805 72 1 10 22.26192711167499 20 -125.9741354708805 11 22.26192711167499 21 -125.8600166829316 72 1 10 22.26192711167499 20 -125.8600166829316 11 22.32800834945144 21 -125.8600166829316 72 1 10 22.32800834945144 20 -125.8600166829316 11 22.39408958722789 21 -125.8600166829316 72 1 10 22.39408958722789 20 -125.8600166829316 11 22.46017082500433 21 -125.8600166829316 72 1 10 22.46017082500433 20 -125.8600166829316 11 22.52625206278078 21 -125.8600166829316 72 1 10 22.52625206278078 20 -125.8600166829316 11 22.59233330055723 21 -125.8600166829316 72 1 10 22.59233330055723 20 -125.8600166829316 11 22.65841453833368 21 -125.8600166829316 72 1 10 22.65841453833368 20 -125.8600166829316 11 22.72449577611013 21 -125.8600166829316 72 1 10 22.72449577611013 20 -125.8600166829316 11 22.79057701388658 21 -125.8600166829316 72 1 10 22.79057701388658 20 -125.8600166829316 11 22.89107186221876 21 -125.8571098836159 72 1 10 22.89107186221876 20 -125.8571098836159 11 22.98559364167935 21 -125.8483894856688 72 1 10 22.98559364167935 20 -125.8483894856688 11 23.07414437087898 21 -125.8338554890904 72 1 10 23.07414437087898 20 -125.8338554890904 11 23.15672606842829 21 -125.8135078938807 72 1 10 23.15672606842829 20 -125.8135078938807 11 23.23334075293791 21 -125.7873467000396 72 1 10 23.23334075293791 20 -125.7873467000396 11 23.30399044301848 21 -125.7553719075671 72 1 10 23.30399044301848 20 -125.7553719075671 11 23.36867715728063 21 -125.7175835164633 72 1 10 23.36867715728063 20 -125.7175835164633 11 23.42740291433501 21 -125.6739815267281 72 1 10 23.42740291433501 20 -125.6739815267281 11 23.47961158695142 21 -125.62335477198 72 1 10 23.47961158695142 20 -125.62335477198 11 23.5248722017591 21 -125.5644920858375 72 1 10 23.5248722017591 20 -125.5644920858375 11 23.56318072153678 21 -125.4973934683005 72 1 10 23.56318072153678 20 -125.4973934683005 11 23.59453310906319 21 -125.4220589193692 72 1 10 23.59453310906319 20 -125.4220589193692 11 23.61892532711706 21 -125.3384884390434 72 1 10 23.61892532711706 20 -125.3384884390434 11 23.63635333847711 21 -125.2466820273232 72 1 10 23.63635333847711 20 -125.2466820273232 11 23.64681310592207 21 -125.1466396842085 72 1 10 23.64681310592207 20 -125.1466396842085 11 23.65030059223067 21 -125.0383614096995 72 1 10 23.65030059223067 20 -125.0383614096995 11 23.64679662060188 21 -124.9388200184576 72 1 10 23.64679662060188 20 -124.9388200184576 11 23.63628605145591 21 -124.8459985820227 72 1 10 23.63628605145591 20 -124.8459985820227 11 23.61877090340341 21 -124.7598991190052 72 1 10 23.61877090340341 20 -124.7598991190052 11 23.59425319505501 21 -124.6805236480159 72 1 10 23.59425319505501 20 -124.6805236480159 11 23.56273494502136 21 -124.6078741876654 72 1 10 23.56273494502136 20 -124.6078741876654 11 23.52421817191307 21 -124.5419527565643 72 1 10 23.52421817191307 20 -124.5419527565643 11 23.4787048943408 21 -124.4827613733232 72 1 10 23.4787048943408 20 -124.4827613733232 11 23.42619713091517 21 -124.4303020565529 72 1 10 23.42619713091517 20 -124.4303020565529 11 23.36774590490728 21 -124.3842777340546 72 1 10 23.36774590490728 20 -124.3842777340546 11 23.30452873918805 21 -124.3443899878895 72 1 10 23.30452873918805 20 -124.3443899878895 11 23.23654361514685 21 -124.3106388180574 72 1 10 23.23654361514685 20 -124.3106388180574 11 23.16378851417305 21 -124.2830242245584 72 1 10 23.16378851417305 20 -124.2830242245584 11 23.086261417656 21 -124.2615462073926 72 1 10 23.086261417656 20 -124.2615462073926 11 23.00396030698509 21 -124.2462047665598 72 1 10 23.00396030698509 20 -124.2462047665598 11 22.91688316354966 21 -124.2369999020602 72 1 10 22.91688316354966 20 -124.2369999020602 11 22.82502796873908 21 -124.2339316138936 97 0 92 1 93 56 72 1 10 23.02243194004389 20 -125.3311945259457 11 22.99597266469888 21 -125.3525753133659 72 1 10 22.99597266469888 20 -125.3525753133659 11 22.96698205161645 21 -125.3711118784002 72 1 10 22.96698205161645 20 -125.3711118784002 11 22.9354641380179 21 -125.3868022024378 72 1 10 22.9354641380179 20 -125.3868022024378 11 22.90142296112449 21 -125.3996442668683 72 1 10 22.90142296112449 20 -125.3996442668683 11 22.86486255815749 21 -125.4096360530808 72 1 10 22.86486255815749 20 -125.4096360530808 11 22.82578696633817 21 -125.4167755424648 72 1 10 22.82578696633817 20 -125.4167755424648 11 22.7842002228878 21 -125.4210607164097 72 1 10 22.7842002228878 20 -125.4210607164097 11 22.74010636502767 21 -125.4224895563048 72 1 10 22.74010636502767 20 -125.4224895563048 11 22.68033395835858 21 -125.4224895563048 72 1 10 22.68033395835858 20 -125.4224895563048 11 22.6205615516895 21 -125.4224895563048 72 1 10 22.6205615516895 20 -125.4224895563048 11 22.56078914502041 21 -125.4224895563048 72 1 10 22.56078914502041 20 -125.4224895563048 11 22.50101673835133 21 -125.4224895563048 72 1 10 22.50101673835133 20 -125.4224895563048 11 22.44124433168224 21 -125.4224895563048 72 1 10 22.44124433168224 20 -125.4224895563048 11 22.38147192501316 21 -125.4224895563048 72 1 10 22.38147192501316 20 -125.4224895563048 11 22.32169951834407 21 -125.4224895563048 72 1 10 22.32169951834407 20 -125.4224895563048 11 22.26192711167499 21 -125.4224895563048 72 1 10 22.26192711167499 20 -125.4224895563048 11 22.26192711167499 21 -125.3290413412674 72 1 10 22.26192711167499 20 -125.3290413412674 11 22.26192711167499 21 -125.23559312623 72 1 10 22.26192711167499 20 -125.23559312623 11 22.26192711167499 21 -125.1421449111926 72 1 10 22.26192711167499 20 -125.1421449111926 11 22.26192711167499 21 -125.0486966961552 72 1 10 22.26192711167499 20 -125.0486966961552 11 22.26192711167499 21 -124.9552484811178 72 1 10 22.26192711167499 20 -124.9552484811178 11 22.26192711167499 21 -124.8618002660804 72 1 10 22.26192711167499 20 -124.8618002660804 11 22.26192711167499 21 -124.768352051043 72 1 10 22.26192711167499 20 -124.768352051043 11 22.26192711167499 21 -124.6749038360056 72 1 10 22.26192711167499 20 -124.6749038360056 11 22.32169951834407 21 -124.6749038360056 72 1 10 22.32169951834407 20 -124.6749038360056 11 22.38147192501316 21 -124.6749038360056 72 1 10 22.38147192501316 20 -124.6749038360056 11 22.44124433168224 21 -124.6749038360056 72 1 10 22.44124433168224 20 -124.6749038360056 11 22.50101673835133 21 -124.6749038360056 72 1 10 22.50101673835133 20 -124.6749038360056 11 22.56078914502041 21 -124.6749038360056 72 1 10 22.56078914502041 20 -124.6749038360056 11 22.6205615516895 21 -124.6749038360056 72 1 10 22.6205615516895 20 -124.6749038360056 11 22.68033395835858 21 -124.6749038360056 72 1 10 22.68033395835858 20 -124.6749038360056 11 22.74010636502767 21 -124.6749038360056 72 1 10 22.74010636502767 20 -124.6749038360056 11 22.7842002228878 21 -124.6762203065753 72 1 10 22.7842002228878 20 -124.6762203065753 11 22.82578696633817 21 -124.6801710640249 72 1 10 22.82578696633817 20 -124.6801710640249 11 22.86486255815749 21 -124.6867581269649 72 1 10 22.86486255815749 20 -124.6867581269649 11 22.90142296112449 21 -124.695983514006 72 1 10 22.90142296112449 20 -124.695983514006 11 22.9354641380179 21 -124.7078492437588 72 1 10 22.9354641380179 20 -124.7078492437588 11 22.96698205161645 21 -124.7223573348341 72 1 10 22.96698205161645 20 -124.7223573348341 11 22.99597266469888 21 -124.7395098058423 72 1 10 22.99597266469888 20 -124.7395098058423 11 23.02243194004389 21 -124.7593086753942 72 1 10 23.02243194004389 20 -124.7593086753942 11 23.04604968448379 21 -124.7822003928754 72 1 10 23.04604968448379 20 -124.7822003928754 11 23.0665183963317 21 -124.808632753412 72 1 10 23.0665183963317 20 -124.808632753412 11 23.08383807558762 21 -124.8386097942251 72 1 10 23.08383807558762 20 -124.8386097942251 11 23.09800872225156 21 -124.8721355525362 72 1 10 23.09800872225156 20 -124.8721355525362 11 23.10903033632351 21 -124.9092140655664 72 1 10 23.10903033632351 20 -124.9092140655664 11 23.11690291780348 21 -124.949849370537 72 1 10 23.11690291780348 20 -124.949849370537 11 23.12162646669146 21 -124.9940455046694 72 1 10 23.12162646669146 20 -124.9940455046694 11 23.12320098298745 21 -125.0418065051847 72 1 10 23.12320098298745 20 -125.0418065051847 11 23.12162646669146 21 -125.0896798750255 72 1 10 23.12162646669146 20 -125.0896798750255 11 23.11690291780348 21 -125.1342104256532 72 1 10 23.11690291780348 20 -125.1342104256532 11 23.10903033632351 21 -125.1753981570678 72 1 10 23.10903033632351 20 -125.1753981570678 11 23.09800872225156 21 -125.2132430692695 72 1 10 23.09800872225156 20 -125.2132430692695 11 23.08383807558762 21 -125.2477451622581 72 1 10 23.08383807558762 20 -125.2477451622581 11 23.0665183963317 21 -125.2789044360336 72 1 10 23.0665183963317 20 -125.2789044360336 11 23.04604968448379 21 -125.3067208905962 72 1 10 23.04604968448379 20 -125.3067208905962 11 23.02243194004389 21 -125.3311945259457 97 0 75 2 76 1 98 0 0 POLYLINE 5 778 330 5B1 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 779 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -126.7729669865228 30 0.0 0 VERTEX 5 77A 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14165733581443 20 -126.7729669865228 30 0.0 0 VERTEX 5 77B 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.20754478696983 20 -126.7729669865228 30 0.0 0 VERTEX 5 77C 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.27343223812524 20 -126.7729669865228 30 0.0 0 VERTEX 5 77D 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.33931968928064 20 -126.7729669865228 30 0.0 0 VERTEX 5 77E 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.40520714043604 20 -126.7729669865228 30 0.0 0 VERTEX 5 77F 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.47109459159145 20 -126.7729669865228 30 0.0 0 VERTEX 5 780 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.53698204274685 20 -126.7729669865228 30 0.0 0 VERTEX 5 781 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -126.7729669865228 30 0.0 0 VERTEX 5 782 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -126.639900173405 30 0.0 0 VERTEX 5 783 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -126.5068333602872 30 0.0 0 VERTEX 5 784 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -126.3737665471694 30 0.0 0 VERTEX 5 785 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -126.2406997340517 30 0.0 0 VERTEX 5 786 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -126.1076329209339 30 0.0 0 VERTEX 5 787 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -125.9745661078161 30 0.0 0 VERTEX 5 788 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -125.8414992946983 30 0.0 0 VERTEX 5 789 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -125.7084324815806 30 0.0 0 VERTEX 5 78A 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.74347245339401 20 -125.7084324815806 30 0.0 0 VERTEX 5 78B 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.88407541288577 20 -125.7084324815806 30 0.0 0 VERTEX 5 78C 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.02467837237753 20 -125.7084324815806 30 0.0 0 VERTEX 5 78D 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.16528133186929 20 -125.7084324815806 30 0.0 0 VERTEX 5 78E 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.30588429136105 20 -125.7084324815806 30 0.0 0 VERTEX 5 78F 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.44648725085281 20 -125.7084324815806 30 0.0 0 VERTEX 5 790 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.58709021034457 20 -125.7084324815806 30 0.0 0 VERTEX 5 791 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.7084324815806 30 0.0 0 VERTEX 5 792 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.6533109538166 30 0.0 0 VERTEX 5 793 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.5981894260526 30 0.0 0 VERTEX 5 794 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.5430678982886 30 0.0 0 VERTEX 5 795 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.4879463705246 30 0.0 0 VERTEX 5 796 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.4328248427606 30 0.0 0 VERTEX 5 797 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.3777033149966 30 0.0 0 VERTEX 5 798 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.3225817872326 30 0.0 0 VERTEX 5 799 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72769316983632 20 -125.2674602594686 30 0.0 0 VERTEX 5 79A 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.58709021034457 20 -125.2674602594686 30 0.0 0 VERTEX 5 79B 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.44648725085281 20 -125.2674602594686 30 0.0 0 VERTEX 5 79C 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.30588429136105 20 -125.2674602594686 30 0.0 0 VERTEX 5 79D 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.16528133186929 20 -125.2674602594686 30 0.0 0 VERTEX 5 79E 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.02467837237753 20 -125.2674602594686 30 0.0 0 VERTEX 5 79F 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.88407541288577 20 -125.2674602594686 30 0.0 0 VERTEX 5 7A0 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.74347245339401 20 -125.2674602594686 30 0.0 0 VERTEX 5 7A1 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -125.2674602594686 30 0.0 0 VERTEX 5 7A2 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -125.1944672988749 30 0.0 0 VERTEX 5 7A3 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -125.1214743382811 30 0.0 0 VERTEX 5 7A4 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -125.0484813776874 30 0.0 0 VERTEX 5 7A5 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -124.9754884170937 30 0.0 0 VERTEX 5 7A6 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -124.9024954564999 30 0.0 0 VERTEX 5 7A7 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -124.8295024959062 30 0.0 0 VERTEX 5 7A8 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -124.7565095353125 30 0.0 0 VERTEX 5 7A9 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60286949390225 20 -124.6835165747187 30 0.0 0 VERTEX 5 7AA 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.7632817524342 20 -124.6835165747187 30 0.0 0 VERTEX 5 7AB 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.92369401096614 20 -124.6835165747187 30 0.0 0 VERTEX 5 7AC 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.08410626949809 20 -124.6835165747187 30 0.0 0 VERTEX 5 7AD 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.24451852803004 20 -124.6835165747187 30 0.0 0 VERTEX 5 7AE 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.40493078656198 20 -124.6835165747187 30 0.0 0 VERTEX 5 7AF 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.56534304509393 20 -124.6835165747187 30 0.0 0 VERTEX 5 7B0 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72575530362587 20 -124.6835165747187 30 0.0 0 VERTEX 5 7B1 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.6835165747187 30 0.0 0 VERTEX 5 7B2 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.6277490915513 30 0.0 0 VERTEX 5 7B3 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.5719816083838 30 0.0 0 VERTEX 5 7B4 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.5162141252163 30 0.0 0 VERTEX 5 7B5 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.4604466420488 30 0.0 0 VERTEX 5 7B6 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.4046791588813 30 0.0 0 VERTEX 5 7B7 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.3489116757139 30 0.0 0 VERTEX 5 7B8 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.2931441925464 30 0.0 0 VERTEX 5 7B9 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88616756215782 20 -124.2373767093789 30 0.0 0 VERTEX 5 7BA 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.65986785247047 20 -124.2373767093789 30 0.0 0 VERTEX 5 7BB 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43356814278312 20 -124.2373767093789 30 0.0 0 VERTEX 5 7BC 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.20726843309577 20 -124.2373767093789 30 0.0 0 VERTEX 5 7BD 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98096872340842 20 -124.2373767093789 30 0.0 0 VERTEX 5 7BE 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.75466901372107 20 -124.2373767093789 30 0.0 0 VERTEX 5 7BF 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.52836930403373 20 -124.2373767093789 30 0.0 0 VERTEX 5 7C0 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.30206959434638 20 -124.2373767093789 30 0.0 0 VERTEX 5 7C1 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -124.2373767093789 30 0.0 0 VERTEX 5 7C2 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -124.5543254940219 30 0.0 0 VERTEX 5 7C3 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -124.8712742786649 30 0.0 0 VERTEX 5 7C4 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -125.1882230633078 30 0.0 0 VERTEX 5 7C5 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -125.5051718479508 30 0.0 0 VERTEX 5 7C6 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -125.8221206325938 30 0.0 0 VERTEX 5 7C7 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -126.1390694172368 30 0.0 0 VERTEX 5 7C8 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -126.4560182018798 30 0.0 0 VERTEX 5 7C9 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -126.7729669865228 30 0.0 0 VERTEX 5 7CA 330 778 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.07576988465903 20 -126.7729669865228 30 0.0 0 SEQEND 5 7CC 330 778 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 7CB 330 5B1 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 80 72 1 10 24.07576988465903 20 -126.7729669865228 11 24.14165733581443 21 -126.7729669865228 72 1 10 24.14165733581443 20 -126.7729669865228 11 24.20754478696983 21 -126.7729669865228 72 1 10 24.20754478696983 20 -126.7729669865228 11 24.27343223812524 21 -126.7729669865228 72 1 10 24.27343223812524 20 -126.7729669865228 11 24.33931968928064 21 -126.7729669865228 72 1 10 24.33931968928064 20 -126.7729669865228 11 24.40520714043604 21 -126.7729669865228 72 1 10 24.40520714043604 20 -126.7729669865228 11 24.47109459159145 21 -126.7729669865228 72 1 10 24.47109459159145 20 -126.7729669865228 11 24.53698204274685 21 -126.7729669865228 72 1 10 24.53698204274685 20 -126.7729669865228 11 24.60286949390225 21 -126.7729669865228 72 1 10 24.60286949390225 20 -126.7729669865228 11 24.60286949390225 21 -126.639900173405 72 1 10 24.60286949390225 20 -126.639900173405 11 24.60286949390225 21 -126.5068333602872 72 1 10 24.60286949390225 20 -126.5068333602872 11 24.60286949390225 21 -126.3737665471694 72 1 10 24.60286949390225 20 -126.3737665471694 11 24.60286949390225 21 -126.2406997340517 72 1 10 24.60286949390225 20 -126.2406997340517 11 24.60286949390225 21 -126.1076329209339 72 1 10 24.60286949390225 20 -126.1076329209339 11 24.60286949390225 21 -125.9745661078161 72 1 10 24.60286949390225 20 -125.9745661078161 11 24.60286949390225 21 -125.8414992946983 72 1 10 24.60286949390225 20 -125.8414992946983 11 24.60286949390225 21 -125.7084324815806 72 1 10 24.60286949390225 20 -125.7084324815806 11 24.74347245339401 21 -125.7084324815806 72 1 10 24.74347245339401 20 -125.7084324815806 11 24.88407541288577 21 -125.7084324815806 72 1 10 24.88407541288577 20 -125.7084324815806 11 25.02467837237753 21 -125.7084324815806 72 1 10 25.02467837237753 20 -125.7084324815806 11 25.16528133186929 21 -125.7084324815806 72 1 10 25.16528133186929 20 -125.7084324815806 11 25.30588429136105 21 -125.7084324815806 72 1 10 25.30588429136105 20 -125.7084324815806 11 25.44648725085281 21 -125.7084324815806 72 1 10 25.44648725085281 20 -125.7084324815806 11 25.58709021034457 21 -125.7084324815806 72 1 10 25.58709021034457 20 -125.7084324815806 11 25.72769316983632 21 -125.7084324815806 72 1 10 25.72769316983632 20 -125.7084324815806 11 25.72769316983632 21 -125.6533109538166 72 1 10 25.72769316983632 20 -125.6533109538166 11 25.72769316983632 21 -125.5981894260526 72 1 10 25.72769316983632 20 -125.5981894260526 11 25.72769316983632 21 -125.5430678982886 72 1 10 25.72769316983632 20 -125.5430678982886 11 25.72769316983632 21 -125.4879463705246 72 1 10 25.72769316983632 20 -125.4879463705246 11 25.72769316983632 21 -125.4328248427606 72 1 10 25.72769316983632 20 -125.4328248427606 11 25.72769316983632 21 -125.3777033149966 72 1 10 25.72769316983632 20 -125.3777033149966 11 25.72769316983632 21 -125.3225817872326 72 1 10 25.72769316983632 20 -125.3225817872326 11 25.72769316983632 21 -125.2674602594686 72 1 10 25.72769316983632 20 -125.2674602594686 11 25.58709021034457 21 -125.2674602594686 72 1 10 25.58709021034457 20 -125.2674602594686 11 25.44648725085281 21 -125.2674602594686 72 1 10 25.44648725085281 20 -125.2674602594686 11 25.30588429136105 21 -125.2674602594686 72 1 10 25.30588429136105 20 -125.2674602594686 11 25.16528133186929 21 -125.2674602594686 72 1 10 25.16528133186929 20 -125.2674602594686 11 25.02467837237753 21 -125.2674602594686 72 1 10 25.02467837237753 20 -125.2674602594686 11 24.88407541288577 21 -125.2674602594686 72 1 10 24.88407541288577 20 -125.2674602594686 11 24.74347245339401 21 -125.2674602594686 72 1 10 24.74347245339401 20 -125.2674602594686 11 24.60286949390225 21 -125.2674602594686 72 1 10 24.60286949390225 20 -125.2674602594686 11 24.60286949390225 21 -125.1944672988749 72 1 10 24.60286949390225 20 -125.1944672988749 11 24.60286949390225 21 -125.1214743382811 72 1 10 24.60286949390225 20 -125.1214743382811 11 24.60286949390225 21 -125.0484813776874 72 1 10 24.60286949390225 20 -125.0484813776874 11 24.60286949390225 21 -124.9754884170937 72 1 10 24.60286949390225 20 -124.9754884170937 11 24.60286949390225 21 -124.9024954564999 72 1 10 24.60286949390225 20 -124.9024954564999 11 24.60286949390225 21 -124.8295024959062 72 1 10 24.60286949390225 20 -124.8295024959062 11 24.60286949390225 21 -124.7565095353125 72 1 10 24.60286949390225 20 -124.7565095353125 11 24.60286949390225 21 -124.6835165747187 72 1 10 24.60286949390225 20 -124.6835165747187 11 24.7632817524342 21 -124.6835165747187 72 1 10 24.7632817524342 20 -124.6835165747187 11 24.92369401096614 21 -124.6835165747187 72 1 10 24.92369401096614 20 -124.6835165747187 11 25.08410626949809 21 -124.6835165747187 72 1 10 25.08410626949809 20 -124.6835165747187 11 25.24451852803004 21 -124.6835165747187 72 1 10 25.24451852803004 20 -124.6835165747187 11 25.40493078656198 21 -124.6835165747187 72 1 10 25.40493078656198 20 -124.6835165747187 11 25.56534304509393 21 -124.6835165747187 72 1 10 25.56534304509393 20 -124.6835165747187 11 25.72575530362587 21 -124.6835165747187 72 1 10 25.72575530362587 20 -124.6835165747187 11 25.88616756215782 21 -124.6835165747187 72 1 10 25.88616756215782 20 -124.6835165747187 11 25.88616756215782 21 -124.6277490915513 72 1 10 25.88616756215782 20 -124.6277490915513 11 25.88616756215782 21 -124.5719816083838 72 1 10 25.88616756215782 20 -124.5719816083838 11 25.88616756215782 21 -124.5162141252163 72 1 10 25.88616756215782 20 -124.5162141252163 11 25.88616756215782 21 -124.4604466420488 72 1 10 25.88616756215782 20 -124.4604466420488 11 25.88616756215782 21 -124.4046791588813 72 1 10 25.88616756215782 20 -124.4046791588813 11 25.88616756215782 21 -124.3489116757139 72 1 10 25.88616756215782 20 -124.3489116757139 11 25.88616756215782 21 -124.2931441925464 72 1 10 25.88616756215782 20 -124.2931441925464 11 25.88616756215782 21 -124.2373767093789 72 1 10 25.88616756215782 20 -124.2373767093789 11 25.65986785247047 21 -124.2373767093789 72 1 10 25.65986785247047 20 -124.2373767093789 11 25.43356814278312 21 -124.2373767093789 72 1 10 25.43356814278312 20 -124.2373767093789 11 25.20726843309577 21 -124.2373767093789 72 1 10 25.20726843309577 20 -124.2373767093789 11 24.98096872340842 21 -124.2373767093789 72 1 10 24.98096872340842 20 -124.2373767093789 11 24.75466901372107 21 -124.2373767093789 72 1 10 24.75466901372107 20 -124.2373767093789 11 24.52836930403373 21 -124.2373767093789 72 1 10 24.52836930403373 20 -124.2373767093789 11 24.30206959434638 21 -124.2373767093789 72 1 10 24.30206959434638 20 -124.2373767093789 11 24.07576988465903 21 -124.2373767093789 72 1 10 24.07576988465903 20 -124.2373767093789 11 24.07576988465903 21 -124.5543254940219 72 1 10 24.07576988465903 20 -124.5543254940219 11 24.07576988465903 21 -124.8712742786649 72 1 10 24.07576988465903 20 -124.8712742786649 11 24.07576988465903 21 -125.1882230633078 72 1 10 24.07576988465903 20 -125.1882230633078 11 24.07576988465903 21 -125.5051718479508 72 1 10 24.07576988465903 20 -125.5051718479508 11 24.07576988465903 21 -125.8221206325938 72 1 10 24.07576988465903 20 -125.8221206325938 11 24.07576988465903 21 -126.1390694172368 72 1 10 24.07576988465903 20 -126.1390694172368 11 24.07576988465903 21 -126.4560182018798 72 1 10 24.07576988465903 20 -126.4560182018798 11 24.07576988465903 21 -126.7729669865228 97 0 75 2 76 1 98 0 0 POLYLINE 5 7CD 330 5B1 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 7CE 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10185224242334 20 -124.1564169654755 30 0.0 0 VERTEX 5 7CF 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96976243685334 20 -124.1610439574881 30 0.0 0 VERTEX 5 7D0 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.84569862717163 20 -124.1749262792662 30 0.0 0 VERTEX 5 7D1 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.72966081337821 20 -124.1980659494205 30 0.0 0 VERTEX 5 7D2 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.62164899547308 20 -124.2304649865616 30 0.0 0 VERTEX 5 7D3 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.52166317345625 20 -124.2721254093002 30 0.0 0 VERTEX 5 7D4 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42970334732771 20 -124.3230492362468 30 0.0 0 VERTEX 5 7D5 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.34576951708746 20 -124.3832384860122 30 0.0 0 VERTEX 5 7D6 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.26986168273551 20 -124.452695177207 30 0.0 0 VERTEX 5 7D7 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.17944441156789 20 -124.5455347811377 30 0.0 0 VERTEX 5 7D8 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.10107622728589 20 -124.6492567150064 30 0.0 0 VERTEX 5 7D9 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.03475914850015 20 -124.7638589602026 30 0.0 0 VERTEX 5 7DA 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.9804951938213 20 -124.8893394981156 30 0.0 0 VERTEX 5 7DB 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.93828638185998 20 -125.0256963101348 30 0.0 0 VERTEX 5 7DC 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.90813473122682 20 -125.1729273776495 30 0.0 0 VERTEX 5 7DD 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.89004226053245 20 -125.3310306820491 30 0.0 0 VERTEX 5 7DE 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.88401098838752 20 -125.5000042047229 30 0.0 0 VERTEX 5 7DF 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.89004226053245 20 -125.6659750440759 30 0.0 0 VERTEX 5 7E0 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.90813473122682 20 -125.8219214630111 30 0.0 0 VERTEX 5 7E1 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.93828638185998 20 -125.9678474987497 30 0.0 0 VERTEX 5 7E2 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.9804951938213 20 -126.103757188513 30 0.0 0 VERTEX 5 7E3 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.03475914850015 20 -126.2296545695223 30 0.0 0 VERTEX 5 7E4 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.10107622728589 20 -126.3455436789989 30 0.0 0 VERTEX 5 7E5 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.17944441156789 20 -126.451428554164 30 0.0 0 VERTEX 5 7E6 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.26986168273551 20 -126.5473132322389 30 0.0 0 VERTEX 5 7E7 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.34576951708746 20 -126.6167699234337 30 0.0 0 VERTEX 5 7E8 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42970334732771 20 -126.6769591731991 30 0.0 0 VERTEX 5 7E9 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.52166317345625 20 -126.7278830001457 30 0.0 0 VERTEX 5 7EA 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.62164899547308 20 -126.7695434228843 30 0.0 0 VERTEX 5 7EB 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.72966081337821 20 -126.8019424600254 30 0.0 0 VERTEX 5 7EC 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.84569862717163 20 -126.8250821301797 30 0.0 0 VERTEX 5 7ED 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96976243685334 20 -126.8389644519578 30 0.0 0 VERTEX 5 7EE 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10185224242334 20 -126.8435914439704 30 0.0 0 VERTEX 5 7EF 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.23394204799335 20 -126.8389644519578 30 0.0 0 VERTEX 5 7F0 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.35800585767506 20 -126.8250821301797 30 0.0 0 VERTEX 5 7F1 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.47404367146848 20 -126.8019424600254 30 0.0 0 VERTEX 5 7F2 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.5820554893736 20 -126.7695434228843 30 0.0 0 VERTEX 5 7F3 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.68204131139044 20 -126.7278830001457 30 0.0 0 VERTEX 5 7F4 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.77400113751898 20 -126.6769591731991 30 0.0 0 VERTEX 5 7F5 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.85793496775922 20 -126.6167699234337 30 0.0 0 VERTEX 5 7F6 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.93384280211118 20 -126.5473132322389 30 0.0 0 VERTEX 5 7F7 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.023889321792 20 -126.451428554164 30 0.0 0 VERTEX 5 7F8 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.10192308957865 20 -126.3455436789989 30 0.0 0 VERTEX 5 7F9 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.16794612408177 20 -126.2296545695223 30 0.0 0 VERTEX 5 7FA 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.22196044391198 20 -126.103757188513 30 0.0 0 VERTEX 5 7FB 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.26396806767993 20 -125.9678474987497 30 0.0 0 VERTEX 5 7FC 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.29397101399624 20 -125.8219214630111 30 0.0 0 VERTEX 5 7FD 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.31197130147157 20 -125.6659750440759 30 0.0 0 VERTEX 5 7FE 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.31797094871654 20 -125.5000042047229 30 0.0 0 VERTEX 5 7FF 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.31197130147157 20 -125.3310306820491 30 0.0 0 VERTEX 5 800 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.29397101399624 20 -125.1729273776495 30 0.0 0 VERTEX 5 801 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.26396806767993 20 -125.0256963101348 30 0.0 0 VERTEX 5 802 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.22196044391198 20 -124.8893394981156 30 0.0 0 VERTEX 5 803 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.16794612408177 20 -124.7638589602026 30 0.0 0 VERTEX 5 804 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.10192308957865 20 -124.6492567150064 30 0.0 0 VERTEX 5 805 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.023889321792 20 -124.5455347811377 30 0.0 0 VERTEX 5 806 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.93384280211118 20 -124.452695177207 30 0.0 0 VERTEX 5 807 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.85793496775922 20 -124.3832384860122 30 0.0 0 VERTEX 5 808 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.77400113751898 20 -124.3230492362468 30 0.0 0 VERTEX 5 809 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.68204131139044 20 -124.2721254093002 30 0.0 0 VERTEX 5 80A 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.5820554893736 20 -124.2304649865616 30 0.0 0 VERTEX 5 80B 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.47404367146848 20 -124.1980659494205 30 0.0 0 VERTEX 5 80C 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.35800585767506 20 -124.1749262792662 30 0.0 0 VERTEX 5 80D 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.23394204799335 20 -124.1610439574881 30 0.0 0 VERTEX 5 80E 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10185224242334 20 -124.1564169654755 30 0.0 0 VERTEX 5 80F 330 7CD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10185224242334 20 -124.1564169654755 30 0.0 0 SEQEND 5 810 330 7CD 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 811 330 5B1 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 812 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.60225236165588 20 -126.1614625378909 30 0.0 0 VERTEX 5 813 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.55391033771252 20 -126.2159650250599 30 0.0 0 VERTEX 5 814 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.50151292500165 20 -126.2632005139397 30 0.0 0 VERTEX 5 815 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44505810491265 20 -126.3031690045303 30 0.0 0 VERTEX 5 816 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.38454385883487 20 -126.3358704968317 30 0.0 0 VERTEX 5 817 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.31996816815769 20 -126.3613049908439 30 0.0 0 VERTEX 5 818 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.25132901427047 20 -126.3794724865669 30 0.0 0 VERTEX 5 819 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.17862437856256 20 -126.3903729840007 30 0.0 0 VERTEX 5 81A 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10185224242334 20 -126.3940064831453 30 0.0 0 VERTEX 5 81B 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.0250397340714 20 -126.3903729840007 30 0.0 0 VERTEX 5 81C 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.95221398172535 20 -126.3794724865669 30 0.0 0 VERTEX 5 81D 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.88337296677453 20 -126.3613049908439 30 0.0 0 VERTEX 5 81E 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.81851467060833 20 -126.3358704968317 30 0.0 0 VERTEX 5 81F 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.75763707461609 20 -126.3031690045303 30 0.0 0 VERTEX 5 820 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.70073816018719 20 -126.2632005139397 30 0.0 0 VERTEX 5 821 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.647815908711 20 -126.2159650250599 30 0.0 0 VERTEX 5 822 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.59886830157686 20 -126.1614625378909 30 0.0 0 VERTEX 5 823 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.5548461043943 20 -126.1002582634108 30 0.0 0 VERTEX 5 824 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.51670008277281 20 -126.0329174125975 30 0.0 0 VERTEX 5 825 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.48442821810175 20 -125.9594399854512 30 0.0 0 VERTEX 5 826 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4580284917705 20 -125.8798259819717 30 0.0 0 VERTEX 5 827 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4374988851684 20 -125.7940754021592 30 0.0 0 VERTEX 5 828 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42283737968484 20 -125.7021882460135 30 0.0 0 VERTEX 5 829 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.41404195670917 20 -125.6041645135348 30 0.0 0 VERTEX 5 82A 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.41111059763075 20 -125.5000042047229 30 0.0 0 VERTEX 5 82B 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.41404195670917 20 -125.3958438959111 30 0.0 0 VERTEX 5 82C 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42283737968484 20 -125.2978201634323 30 0.0 0 VERTEX 5 82D 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4374988851684 20 -125.2059330072867 30 0.0 0 VERTEX 5 82E 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4580284917705 20 -125.1201824274741 30 0.0 0 VERTEX 5 82F 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.48442821810175 20 -125.0405684239947 30 0.0 0 VERTEX 5 830 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.51670008277281 20 -124.9670909968484 30 0.0 0 VERTEX 5 831 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.5548461043943 20 -124.8997501460351 30 0.0 0 VERTEX 5 832 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.59886830157686 20 -124.838545871555 30 0.0 0 VERTEX 5 833 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.647815908711 20 -124.784043384386 30 0.0 0 VERTEX 5 834 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.70073816018719 20 -124.7368078955062 30 0.0 0 VERTEX 5 835 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.75763707461609 20 -124.6968394049156 30 0.0 0 VERTEX 5 836 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.81851467060833 20 -124.6641379126142 30 0.0 0 VERTEX 5 837 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.88337296677453 20 -124.638703418602 30 0.0 0 VERTEX 5 838 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.95221398172535 20 -124.620535922879 30 0.0 0 VERTEX 5 839 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.0250397340714 20 -124.6096354254452 30 0.0 0 VERTEX 5 83A 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10185224242334 20 -124.6060019263006 30 0.0 0 VERTEX 5 83B 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.17862437856256 20 -124.6096512378952 30 0.0 0 VERTEX 5 83C 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.25132901427047 20 -124.6205978269385 30 0.0 0 VERTEX 5 83D 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.31996816815769 20 -124.6388396748199 30 0.0 0 VERTEX 5 83E 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.38454385883487 20 -124.6643747629288 30 0.0 0 VERTEX 5 83F 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44505810491265 20 -124.6972010726545 30 0.0 0 VERTEX 5 840 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.50151292500165 20 -124.7373165853864 30 0.0 0 VERTEX 5 841 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.55391033771252 20 -124.7847192825139 30 0.0 0 VERTEX 5 842 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.60225236165588 20 -124.8394071454263 30 0.0 0 VERTEX 5 843 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.64566897564768 20 -124.9007722358871 30 0.0 0 VERTEX 5 844 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.68329015850384 20 -124.9682052699194 30 0.0 0 VERTEX 5 845 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.715117928835 20 -125.0417022103019 30 0.0 0 VERTEX 5 846 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7411543052518 20 -125.1212590198133 30 0.0 0 VERTEX 5 847 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.76140130636487 20 -125.2068716612324 30 0.0 0 VERTEX 5 848 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.77586095078484 20 -125.2985360973379 30 0.0 0 VERTEX 5 849 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.78453525712236 20 -125.3962482909085 30 0.0 0 VERTEX 5 84A 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.78742624398806 20 -125.5000042047229 30 0.0 0 VERTEX 5 84B 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.78453525712236 20 -125.6041645135348 30 0.0 0 VERTEX 5 84C 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.77586095078484 20 -125.7021882460135 30 0.0 0 VERTEX 5 84D 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.76140130636487 20 -125.7940754021592 30 0.0 0 VERTEX 5 84E 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7411543052518 20 -125.8798259819717 30 0.0 0 VERTEX 5 84F 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.715117928835 20 -125.9594399854512 30 0.0 0 VERTEX 5 850 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.68329015850384 20 -126.0329174125975 30 0.0 0 VERTEX 5 851 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.64566897564768 20 -126.1002582634108 30 0.0 0 VERTEX 5 852 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.60225236165588 20 -126.1614625378909 30 0.0 0 VERTEX 5 853 330 811 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.60225236165588 20 -126.1614625378909 30 0.0 0 SEQEND 5 854 330 811 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 855 330 5B1 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 64 72 1 10 20.10185224242334 20 -124.1564169654755 11 19.96976243685334 21 -124.1610439574881 72 1 10 19.96976243685334 20 -124.1610439574881 11 19.84569862717163 21 -124.1749262792662 72 1 10 19.84569862717163 20 -124.1749262792662 11 19.72966081337821 21 -124.1980659494205 72 1 10 19.72966081337821 20 -124.1980659494205 11 19.62164899547308 21 -124.2304649865616 72 1 10 19.62164899547308 20 -124.2304649865616 11 19.52166317345625 21 -124.2721254093002 72 1 10 19.52166317345625 20 -124.2721254093002 11 19.42970334732771 21 -124.3230492362468 72 1 10 19.42970334732771 20 -124.3230492362468 11 19.34576951708746 21 -124.3832384860122 72 1 10 19.34576951708746 20 -124.3832384860122 11 19.26986168273551 21 -124.452695177207 72 1 10 19.26986168273551 20 -124.452695177207 11 19.17944441156789 21 -124.5455347811377 72 1 10 19.17944441156789 20 -124.5455347811377 11 19.10107622728589 21 -124.6492567150064 72 1 10 19.10107622728589 20 -124.6492567150064 11 19.03475914850015 21 -124.7638589602026 72 1 10 19.03475914850015 20 -124.7638589602026 11 18.9804951938213 21 -124.8893394981156 72 1 10 18.9804951938213 20 -124.8893394981156 11 18.93828638185998 21 -125.0256963101348 72 1 10 18.93828638185998 20 -125.0256963101348 11 18.90813473122682 21 -125.1729273776495 72 1 10 18.90813473122682 20 -125.1729273776495 11 18.89004226053245 21 -125.3310306820491 72 1 10 18.89004226053245 20 -125.3310306820491 11 18.88401098838752 21 -125.5000042047229 72 1 10 18.88401098838752 20 -125.5000042047229 11 18.89004226053245 21 -125.6659750440759 72 1 10 18.89004226053245 20 -125.6659750440759 11 18.90813473122682 21 -125.8219214630111 72 1 10 18.90813473122682 20 -125.8219214630111 11 18.93828638185998 21 -125.9678474987497 72 1 10 18.93828638185998 20 -125.9678474987497 11 18.9804951938213 21 -126.103757188513 72 1 10 18.9804951938213 20 -126.103757188513 11 19.03475914850015 21 -126.2296545695223 72 1 10 19.03475914850015 20 -126.2296545695223 11 19.10107622728589 21 -126.3455436789989 72 1 10 19.10107622728589 20 -126.3455436789989 11 19.17944441156789 21 -126.451428554164 72 1 10 19.17944441156789 20 -126.451428554164 11 19.26986168273551 21 -126.5473132322389 72 1 10 19.26986168273551 20 -126.5473132322389 11 19.34576951708746 21 -126.6167699234337 72 1 10 19.34576951708746 20 -126.6167699234337 11 19.42970334732771 21 -126.6769591731991 72 1 10 19.42970334732771 20 -126.6769591731991 11 19.52166317345625 21 -126.7278830001457 72 1 10 19.52166317345625 20 -126.7278830001457 11 19.62164899547308 21 -126.7695434228843 72 1 10 19.62164899547308 20 -126.7695434228843 11 19.72966081337821 21 -126.8019424600254 72 1 10 19.72966081337821 20 -126.8019424600254 11 19.84569862717163 21 -126.8250821301797 72 1 10 19.84569862717163 20 -126.8250821301797 11 19.96976243685334 21 -126.8389644519578 72 1 10 19.96976243685334 20 -126.8389644519578 11 20.10185224242334 21 -126.8435914439704 72 1 10 20.10185224242334 20 -126.8435914439704 11 20.23394204799335 21 -126.8389644519578 72 1 10 20.23394204799335 20 -126.8389644519578 11 20.35800585767506 21 -126.8250821301797 72 1 10 20.35800585767506 20 -126.8250821301797 11 20.47404367146848 21 -126.8019424600254 72 1 10 20.47404367146848 20 -126.8019424600254 11 20.5820554893736 21 -126.7695434228843 72 1 10 20.5820554893736 20 -126.7695434228843 11 20.68204131139044 21 -126.7278830001457 72 1 10 20.68204131139044 20 -126.7278830001457 11 20.77400113751898 21 -126.6769591731991 72 1 10 20.77400113751898 20 -126.6769591731991 11 20.85793496775922 21 -126.6167699234337 72 1 10 20.85793496775922 20 -126.6167699234337 11 20.93384280211118 21 -126.5473132322389 72 1 10 20.93384280211118 20 -126.5473132322389 11 21.023889321792 21 -126.451428554164 72 1 10 21.023889321792 20 -126.451428554164 11 21.10192308957865 21 -126.3455436789989 72 1 10 21.10192308957865 20 -126.3455436789989 11 21.16794612408177 21 -126.2296545695223 72 1 10 21.16794612408177 20 -126.2296545695223 11 21.22196044391198 21 -126.103757188513 72 1 10 21.22196044391198 20 -126.103757188513 11 21.26396806767993 21 -125.9678474987497 72 1 10 21.26396806767993 20 -125.9678474987497 11 21.29397101399624 21 -125.8219214630111 72 1 10 21.29397101399624 20 -125.8219214630111 11 21.31197130147157 21 -125.6659750440759 72 1 10 21.31197130147157 20 -125.6659750440759 11 21.31797094871654 21 -125.5000042047229 72 1 10 21.31797094871654 20 -125.5000042047229 11 21.31197130147157 21 -125.3310306820491 72 1 10 21.31197130147157 20 -125.3310306820491 11 21.29397101399624 21 -125.1729273776495 72 1 10 21.29397101399624 20 -125.1729273776495 11 21.26396806767993 21 -125.0256963101348 72 1 10 21.26396806767993 20 -125.0256963101348 11 21.22196044391198 21 -124.8893394981156 72 1 10 21.22196044391198 20 -124.8893394981156 11 21.16794612408177 21 -124.7638589602026 72 1 10 21.16794612408177 20 -124.7638589602026 11 21.10192308957865 21 -124.6492567150064 72 1 10 21.10192308957865 20 -124.6492567150064 11 21.023889321792 21 -124.5455347811377 72 1 10 21.023889321792 20 -124.5455347811377 11 20.93384280211118 21 -124.452695177207 72 1 10 20.93384280211118 20 -124.452695177207 11 20.85793496775922 21 -124.3832384860122 72 1 10 20.85793496775922 20 -124.3832384860122 11 20.77400113751898 21 -124.3230492362468 72 1 10 20.77400113751898 20 -124.3230492362468 11 20.68204131139044 21 -124.2721254093002 72 1 10 20.68204131139044 20 -124.2721254093002 11 20.5820554893736 21 -124.2304649865616 72 1 10 20.5820554893736 20 -124.2304649865616 11 20.47404367146848 21 -124.1980659494205 72 1 10 20.47404367146848 20 -124.1980659494205 11 20.35800585767506 21 -124.1749262792662 72 1 10 20.35800585767506 20 -124.1749262792662 11 20.23394204799335 21 -124.1610439574881 72 1 10 20.23394204799335 20 -124.1610439574881 11 20.10185224242334 21 -124.1564169654755 97 0 92 1 93 64 72 1 10 20.60225236165588 20 -126.1614625378909 11 20.55391033771252 21 -126.2159650250599 72 1 10 20.55391033771252 20 -126.2159650250599 11 20.50151292500165 21 -126.2632005139397 72 1 10 20.50151292500165 20 -126.2632005139397 11 20.44505810491265 21 -126.3031690045303 72 1 10 20.44505810491265 20 -126.3031690045303 11 20.38454385883487 21 -126.3358704968317 72 1 10 20.38454385883487 20 -126.3358704968317 11 20.31996816815769 21 -126.3613049908439 72 1 10 20.31996816815769 20 -126.3613049908439 11 20.25132901427047 21 -126.3794724865669 72 1 10 20.25132901427047 20 -126.3794724865669 11 20.17862437856256 21 -126.3903729840007 72 1 10 20.17862437856256 20 -126.3903729840007 11 20.10185224242334 21 -126.3940064831453 72 1 10 20.10185224242334 20 -126.3940064831453 11 20.0250397340714 21 -126.3903729840007 72 1 10 20.0250397340714 20 -126.3903729840007 11 19.95221398172535 21 -126.3794724865669 72 1 10 19.95221398172535 20 -126.3794724865669 11 19.88337296677453 21 -126.3613049908439 72 1 10 19.88337296677453 20 -126.3613049908439 11 19.81851467060833 21 -126.3358704968317 72 1 10 19.81851467060833 20 -126.3358704968317 11 19.75763707461609 21 -126.3031690045303 72 1 10 19.75763707461609 20 -126.3031690045303 11 19.70073816018719 21 -126.2632005139397 72 1 10 19.70073816018719 20 -126.2632005139397 11 19.647815908711 21 -126.2159650250599 72 1 10 19.647815908711 20 -126.2159650250599 11 19.59886830157686 21 -126.1614625378909 72 1 10 19.59886830157686 20 -126.1614625378909 11 19.5548461043943 21 -126.1002582634108 72 1 10 19.5548461043943 20 -126.1002582634108 11 19.51670008277281 21 -126.0329174125975 72 1 10 19.51670008277281 20 -126.0329174125975 11 19.48442821810175 21 -125.9594399854512 72 1 10 19.48442821810175 20 -125.9594399854512 11 19.4580284917705 21 -125.8798259819717 72 1 10 19.4580284917705 20 -125.8798259819717 11 19.4374988851684 21 -125.7940754021592 72 1 10 19.4374988851684 20 -125.7940754021592 11 19.42283737968484 21 -125.7021882460135 72 1 10 19.42283737968484 20 -125.7021882460135 11 19.41404195670917 21 -125.6041645135348 72 1 10 19.41404195670917 20 -125.6041645135348 11 19.41111059763075 21 -125.5000042047229 72 1 10 19.41111059763075 20 -125.5000042047229 11 19.41404195670917 21 -125.3958438959111 72 1 10 19.41404195670917 20 -125.3958438959111 11 19.42283737968484 21 -125.2978201634323 72 1 10 19.42283737968484 20 -125.2978201634323 11 19.4374988851684 21 -125.2059330072867 72 1 10 19.4374988851684 20 -125.2059330072867 11 19.4580284917705 21 -125.1201824274741 72 1 10 19.4580284917705 20 -125.1201824274741 11 19.48442821810175 21 -125.0405684239947 72 1 10 19.48442821810175 20 -125.0405684239947 11 19.51670008277281 21 -124.9670909968484 72 1 10 19.51670008277281 20 -124.9670909968484 11 19.5548461043943 21 -124.8997501460351 72 1 10 19.5548461043943 20 -124.8997501460351 11 19.59886830157686 21 -124.838545871555 72 1 10 19.59886830157686 20 -124.838545871555 11 19.647815908711 21 -124.784043384386 72 1 10 19.647815908711 20 -124.784043384386 11 19.70073816018719 21 -124.7368078955062 72 1 10 19.70073816018719 20 -124.7368078955062 11 19.75763707461609 21 -124.6968394049156 72 1 10 19.75763707461609 20 -124.6968394049156 11 19.81851467060833 21 -124.6641379126142 72 1 10 19.81851467060833 20 -124.6641379126142 11 19.88337296677453 21 -124.638703418602 72 1 10 19.88337296677453 20 -124.638703418602 11 19.95221398172535 21 -124.620535922879 72 1 10 19.95221398172535 20 -124.620535922879 11 20.0250397340714 21 -124.6096354254452 72 1 10 20.0250397340714 20 -124.6096354254452 11 20.10185224242334 21 -124.6060019263006 72 1 10 20.10185224242334 20 -124.6060019263006 11 20.17862437856256 21 -124.6096512378952 72 1 10 20.17862437856256 20 -124.6096512378952 11 20.25132901427047 21 -124.6205978269385 72 1 10 20.25132901427047 20 -124.6205978269385 11 20.31996816815769 21 -124.6388396748199 72 1 10 20.31996816815769 20 -124.6388396748199 11 20.38454385883487 21 -124.6643747629288 72 1 10 20.38454385883487 20 -124.6643747629288 11 20.44505810491265 21 -124.6972010726545 72 1 10 20.44505810491265 20 -124.6972010726545 11 20.50151292500165 21 -124.7373165853864 72 1 10 20.50151292500165 20 -124.7373165853864 11 20.55391033771252 21 -124.7847192825139 72 1 10 20.55391033771252 20 -124.7847192825139 11 20.60225236165588 21 -124.8394071454263 72 1 10 20.60225236165588 20 -124.8394071454263 11 20.64566897564768 21 -124.9007722358871 72 1 10 20.64566897564768 20 -124.9007722358871 11 20.68329015850384 21 -124.9682052699194 72 1 10 20.68329015850384 20 -124.9682052699194 11 20.715117928835 21 -125.0417022103019 72 1 10 20.715117928835 20 -125.0417022103019 11 20.7411543052518 21 -125.1212590198133 72 1 10 20.7411543052518 20 -125.1212590198133 11 20.76140130636487 21 -125.2068716612324 72 1 10 20.76140130636487 20 -125.2068716612324 11 20.77586095078484 21 -125.2985360973379 72 1 10 20.77586095078484 20 -125.2985360973379 11 20.78453525712236 21 -125.3962482909085 72 1 10 20.78453525712236 20 -125.3962482909085 11 20.78742624398806 21 -125.5000042047229 72 1 10 20.78742624398806 20 -125.5000042047229 11 20.78453525712236 21 -125.6041645135348 72 1 10 20.78453525712236 20 -125.6041645135348 11 20.77586095078484 21 -125.7021882460135 72 1 10 20.77586095078484 20 -125.7021882460135 11 20.76140130636487 21 -125.7940754021592 72 1 10 20.76140130636487 20 -125.7940754021592 11 20.7411543052518 21 -125.8798259819717 72 1 10 20.7411543052518 20 -125.8798259819717 11 20.715117928835 21 -125.9594399854512 72 1 10 20.715117928835 20 -125.9594399854512 11 20.68329015850384 21 -126.0329174125975 72 1 10 20.68329015850384 20 -126.0329174125975 11 20.64566897564768 21 -126.1002582634108 72 1 10 20.64566897564768 20 -126.1002582634108 11 20.60225236165588 21 -126.1614625378909 97 0 75 2 76 1 98 0 0 ENDBLK 5 5B4 330 5B1 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 9E6 330 9E4 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 block 4 70 0 10 0.0 20 0.0 30 0.0 3 block 4 1 0 POLYLINE 5 9E8 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 9E9 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.11730887410192 30 0.0 0 VERTEX 5 9EA 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.67187923388326 20 -72.11730887410192 30 0.0 0 VERTEX 5 9EB 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.73016594312434 20 -72.11730887410192 30 0.0 0 VERTEX 5 9EC 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.78845265236541 20 -72.11730887410192 30 0.0 0 VERTEX 5 9ED 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.84673936160648 20 -72.11730887410192 30 0.0 0 VERTEX 5 9EE 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.90502607084755 20 -72.11730887410192 30 0.0 0 VERTEX 5 9EF 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.96331278008862 20 -72.11730887410192 30 0.0 0 VERTEX 5 9F0 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.02159948932969 20 -72.11730887410192 30 0.0 0 VERTEX 5 9F1 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.07988619857076 20 -72.11730887410192 30 0.0 0 VERTEX 5 9F2 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.12777538086148 20 -72.11844737050056 30 0.0 0 VERTEX 5 9F3 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.17170606769521 20 -72.12186285969648 30 0.0 0 VERTEX 5 9F4 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.21167624046134 20 -72.12755534168969 30 0.0 0 VERTEX 5 9F5 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.24768388054921 20 -72.13552481648017 30 0.0 0 VERTEX 5 9F6 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.2797269693482 20 -72.14577128406795 30 0.0 0 VERTEX 5 9F7 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.30780348824767 20 -72.158294744453 30 0.0 0 VERTEX 5 9F8 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.33191141863698 20 -72.17309519763533 30 0.0 0 VERTEX 5 9F9 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.3520487419055 20 -72.19017264361496 30 0.0 0 VERTEX 5 9FA 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.36911003900003 20 -72.2106655787905 30 0.0 0 VERTEX 5 9FB 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.3839912366078 20 -72.2357124995606 30 0.0 0 VERTEX 5 9FC 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.39669233472881 20 -72.26531340592527 30 0.0 0 VERTEX 5 9FD 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.40721333336306 20 -72.2994682978845 30 0.0 0 VERTEX 5 9FE 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.41555423251055 20 -72.3381771754383 30 0.0 0 VERTEX 5 9FF 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42171503217129 20 -72.38144003858666 30 0.0 0 VERTEX 5 A00 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42569573234526 20 -72.4292568873296 30 0.0 0 VERTEX 5 A01 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42749633303247 20 -72.4816277216671 30 0.0 0 VERTEX 5 A02 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42788390627456 20 -72.5081764887503 30 0.0 0 VERTEX 5 A03 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42827147951665 20 -72.53472525583351 30 0.0 0 VERTEX 5 A04 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42865905275874 20 -72.5612740229167 30 0.0 0 VERTEX 5 A05 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42904662600083 20 -72.58782278999992 30 0.0 0 VERTEX 5 A06 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42943419924292 20 -72.61437155708312 30 0.0 0 VERTEX 5 A07 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42982177248501 20 -72.64092032416633 30 0.0 0 VERTEX 5 A08 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4302093457271 20 -72.66746909124953 30 0.0 0 VERTEX 5 A09 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.43059691896919 20 -72.69401785833274 30 0.0 0 VERTEX 5 A0A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.43125094881522 20 -72.71913744908574 30 0.0 0 VERTEX 5 A0B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.43243789186912 20 -72.74411169987296 30 0.0 0 VERTEX 5 A0C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4341577481309 20 -72.76894061069439 30 0.0 0 VERTEX 5 A0D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.43641051760055 20 -72.79362418155003 30 0.0 0 VERTEX 5 A0E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.43919620027808 20 -72.81816241243989 30 0.0 0 VERTEX 5 A0F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.44251479616348 20 -72.84255530336397 30 0.0 0 VERTEX 5 A10 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.44636630525676 20 -72.86680285432226 30 0.0 0 VERTEX 5 A11 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45075072755791 20 -72.89090506531477 30 0.0 0 VERTEX 5 A12 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45326995363149 20 -72.90299250580247 30 0.0 0 VERTEX 5 A13 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45617675294717 20 -72.91600043274013 30 0.0 0 VERTEX 5 A14 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45947112550494 20 -72.92992884612777 30 0.0 0 VERTEX 5 A15 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.46315307130481 20 -72.94477774596537 30 0.0 0 VERTEX 5 A16 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.46722259034675 20 -72.96054713225293 30 0.0 0 VERTEX 5 A17 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4716796826308 20 -72.97723700499046 30 0.0 0 VERTEX 5 A18 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.47652434815693 20 -72.99484736417794 30 0.0 0 VERTEX 5 A19 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.48175658692515 20 -73.0133782098154 30 0.0 0 VERTEX 5 A1A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.54764403808056 20 -73.0133782098154 30 0.0 0 VERTEX 5 A1B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.61353148923596 20 -73.0133782098154 30 0.0 0 VERTEX 5 A1C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.67941894039136 20 -73.0133782098154 30 0.0 0 VERTEX 5 A1D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.74530639154677 20 -73.0133782098154 30 0.0 0 VERTEX 5 A1E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.81119384270217 20 -73.0133782098154 30 0.0 0 VERTEX 5 A1F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.87708129385757 20 -73.0133782098154 30 0.0 0 VERTEX 5 A20 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.94296874501298 20 -73.0133782098154 30 0.0 0 VERTEX 5 A21 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -73.0133782098154 30 0.0 0 VERTEX 5 A22 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -73.00620810483673 30 0.0 0 VERTEX 5 A23 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -72.99903799985805 30 0.0 0 VERTEX 5 A24 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -72.99186789487938 30 0.0 0 VERTEX 5 A25 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -72.9846977899007 30 0.0 0 VERTEX 5 A26 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -72.97752768492202 30 0.0 0 VERTEX 5 A27 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -72.97035757994334 30 0.0 0 VERTEX 5 A28 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -72.96318747496467 30 0.0 0 VERTEX 5 A29 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.00885619616838 20 -72.95601736998599 30 0.0 0 VERTEX 5 A2A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.99232814871683 20 -72.94482619262062 30 0.0 0 VERTEX 5 A2B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.97736856172936 20 -72.93218161559741 30 0.0 0 VERTEX 5 A2C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96397945381662 20 -72.91808363891637 30 0.0 0 VERTEX 5 A2D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.95216284358924 20 -72.9025322625775 30 0.0 0 VERTEX 5 A2E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.94192074965784 20 -72.88552748658076 30 0.0 0 VERTEX 5 A2F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.93325519063308 20 -72.8670693109262 30 0.0 0 VERTEX 5 A30 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.92616818512558 20 -72.84715773561379 30 0.0 0 VERTEX 5 A31 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.92066175174598 20 -72.82579276064355 30 0.0 0 VERTEX 5 A32 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.91769809489739 20 -72.81026560763229 30 0.0 0 VERTEX 5 A33 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.91513614156534 20 -72.79158942202905 30 0.0 0 VERTEX 5 A34 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.9129738731392 20 -72.76976420383383 30 0.0 0 VERTEX 5 A35 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.91120927100833 20 -72.7447899530466 30 0.0 0 VERTEX 5 A36 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90984031656209 20 -72.71666666966742 30 0.0 0 VERTEX 5 A37 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90886499118985 20 -72.68539435369622 30 0.0 0 VERTEX 5 A38 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90828127628097 20 -72.65097300513305 30 0.0 0 VERTEX 5 A39 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.61340262397789 30 0.0 0 VERTEX 5 A3A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.59421774849442 30 0.0 0 VERTEX 5 A3B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.57503287301093 30 0.0 0 VERTEX 5 A3C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.55584799752744 30 0.0 0 VERTEX 5 A3D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.53666312204396 30 0.0 0 VERTEX 5 A3E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.51747824656047 30 0.0 0 VERTEX 5 A3F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.49829337107698 30 0.0 0 VERTEX 5 A40 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.4791084955935 30 0.0 0 VERTEX 5 A41 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90808715322482 20 -72.45992362011002 30 0.0 0 VERTEX 5 A42 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90705396101435 20 -72.40177888648367 30 0.0 0 VERTEX 5 A43 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90395573012337 20 -72.34748969917187 30 0.0 0 VERTEX 5 A44 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.89879447916251 20 -72.29705202095334 30 0.0 0 VERTEX 5 A45 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.8915722267424 20 -72.25046181460682 30 0.0 0 VERTEX 5 A46 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.8822909914737 20 -72.20771504291103 30 0.0 0 VERTEX 5 A47 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.87095279196701 20 -72.1688076686447 30 0.0 0 VERTEX 5 A48 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.857559646833 20 -72.13373565458657 30 0.0 0 VERTEX 5 A49 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.84211357468229 20 -72.10249496351534 30 0.0 0 VERTEX 5 A4A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.82420412468558 20 -72.07412204528751 30 0.0 0 VERTEX 5 A4B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.80341815453273 20 -72.04740035055983 30 0.0 0 VERTEX 5 A4C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.7797536456131 20 -72.02233391655358 30 0.0 0 VERTEX 5 A4D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.75320857931606 20 -71.99892678049002 30 0.0 0 VERTEX 5 A4E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.72378093703097 20 -71.97718297959044 30 0.0 0 VERTEX 5 A4F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.69146870014719 20 -71.95710655107611 30 0.0 0 VERTEX 5 A50 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.6562698500541 20 -71.93870153216828 30 0.0 0 VERTEX 5 A51 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.61818236814105 20 -71.92197196008826 30 0.0 0 VERTEX 5 A52 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.66379489406959 20 -71.90425596027748 30 0.0 0 VERTEX 5 A53 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.70606460078509 20 -71.88366142169994 30 0.0 0 VERTEX 5 A54 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.74499148828757 20 -71.86018430713435 30 0.0 0 VERTEX 5 A55 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.78057555657701 20 -71.83382057935943 30 0.0 0 VERTEX 5 A56 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.81281680565342 20 -71.80456620115392 30 0.0 0 VERTEX 5 A57 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.8417152355168 20 -71.77241713529654 30 0.0 0 VERTEX 5 A58 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.86727084616716 20 -71.73736934456603 30 0.0 0 VERTEX 5 A59 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.88948363760447 20 -71.69941879174111 30 0.0 0 VERTEX 5 A5A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90874118307085 20 -71.66004848276896 30 0.0 0 VERTEX 5 A5B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.92543105580837 20 -71.62048842439702 30 0.0 0 VERTEX 5 A5C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.93955325581705 20 -71.58074265384658 30 0.0 0 VERTEX 5 A5D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.95110778309688 20 -71.54081520833893 30 0.0 0 VERTEX 5 A5E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96009463764785 20 -71.5007101250953 30 0.0 0 VERTEX 5 A5F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96651381946998 20 -71.460431441337 30 0.0 0 VERTEX 5 A60 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.97036532856325 20 -71.41998319428527 30 0.0 0 VERTEX 5 A61 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.97164916492768 20 -71.3793694211614 30 0.0 0 VERTEX 5 A62 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.97098706063911 20 -71.34611079232451 30 0.0 0 VERTEX 5 A63 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96900074777339 20 -71.31377264993756 30 0.0 0 VERTEX 5 A64 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96569022633054 20 -71.2823549940006 30 0.0 0 VERTEX 5 A65 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.96105549631054 20 -71.25185782451359 30 0.0 0 VERTEX 5 A66 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.95509655771339 20 -71.22228114147656 30 0.0 0 VERTEX 5 A67 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.94781341053911 20 -71.19362494488948 30 0.0 0 VERTEX 5 A68 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.93920605478768 20 -71.16588923475237 30 0.0 0 VERTEX 5 A69 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.92927449045911 20 -71.13907401106523 30 0.0 0 VERTEX 5 A6A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.91821216773933 20 -71.11300971053464 30 0.0 0 VERTEX 5 A6B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.90621119107387 20 -71.08752676986718 30 0.0 0 VERTEX 5 A6C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.89326954185208 20 -71.06262518906286 30 0.0 0 VERTEX 5 A6D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.87938520146333 20 -71.03830496812166 30 0.0 0 VERTEX 5 A6E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.86455615129699 20 -71.01456610704362 30 0.0 0 VERTEX 5 A6F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.84878037274241 20 -70.99140860582871 30 0.0 0 VERTEX 5 A70 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.83205584718897 20 -70.96883246447693 30 0.0 0 VERTEX 5 A71 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.81438055602603 20 -70.94683768298829 30 0.0 0 VERTEX 5 A72 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.79187708465714 20 -70.92128207233793 30 0.0 0 VERTEX 5 A73 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.76816244690672 20 -70.89732520131122 30 0.0 0 VERTEX 5 A74 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.74323664277477 20 -70.87496706990811 30 0.0 0 VERTEX 5 A75 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.71709967226128 20 -70.85420767812863 30 0.0 0 VERTEX 5 A76 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.68975153536626 20 -70.83504702597278 30 0.0 0 VERTEX 5 A77 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.66119223208971 20 -70.81748511344054 30 0.0 0 VERTEX 5 A78 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.63142176243163 20 -70.80152194053194 30 0.0 0 VERTEX 5 A79 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.60044012639201 20 -70.78715750724696 30 0.0 0 VERTEX 5 A7A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.56722220620293 20 -70.77436759025797 30 0.0 0 VERTEX 5 A7B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.5306150387562 20 -70.76312796623733 30 0.0 0 VERTEX 5 A7C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49062064266245 20 -70.75343863518508 30 0.0 0 VERTEX 5 A7D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.44724103653231 20 -70.74529959710117 30 0.0 0 VERTEX 5 A7E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.40047823897642 20 -70.73871085198563 30 0.0 0 VERTEX 5 A7F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.35033426860542 20 -70.73367239983845 30 0.0 0 VERTEX 5 A80 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.29681114402993 20 -70.73018424065964 30 0.0 0 VERTEX 5 A81 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.23991088386061 20 -70.72824637444918 30 0.0 0 VERTEX 5 A82 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.10329131602368 20 -70.72824637444918 30 0.0 0 VERTEX 5 A83 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.96667174818674 20 -70.72824637444918 30 0.0 0 VERTEX 5 A84 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.8300521803498 20 -70.72824637444918 30 0.0 0 VERTEX 5 A85 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.69343261251286 20 -70.72824637444918 30 0.0 0 VERTEX 5 A86 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55681304467592 20 -70.72824637444918 30 0.0 0 VERTEX 5 A87 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.42019347683898 20 -70.72824637444918 30 0.0 0 VERTEX 5 A88 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.28357390900204 20 -70.72824637444918 30 0.0 0 VERTEX 5 A89 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -70.72824637444918 30 0.0 0 VERTEX 5 A8A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -71.01388785386996 30 0.0 0 VERTEX 5 A8B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -71.29952933329074 30 0.0 0 VERTEX 5 A8C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -71.58517081271151 30 0.0 0 VERTEX 5 A8D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -71.8708122921323 30 0.0 0 VERTEX 5 A8E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -72.15645377155307 30 0.0 0 VERTEX 5 A8F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -72.44209525097385 30 0.0 0 VERTEX 5 A90 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -72.72773673039462 30 0.0 0 VERTEX 5 A91 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1469543411651 20 -73.0133782098154 30 0.0 0 VERTEX 5 A92 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.20528411409974 20 -73.0133782098154 30 0.0 0 VERTEX 5 A93 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.26361388703438 20 -73.0133782098154 30 0.0 0 VERTEX 5 A94 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.32194365996901 20 -73.0133782098154 30 0.0 0 VERTEX 5 A95 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.38027343290365 20 -73.0133782098154 30 0.0 0 VERTEX 5 A96 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.43860320583828 20 -73.0133782098154 30 0.0 0 VERTEX 5 A97 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.49693297877292 20 -73.0133782098154 30 0.0 0 VERTEX 5 A98 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55526275170756 20 -73.0133782098154 30 0.0 0 VERTEX 5 A99 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -73.0133782098154 30 0.0 0 VERTEX 5 A9A 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.90136954285121 30 0.0 0 VERTEX 5 A9B 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.78936087588703 30 0.0 0 VERTEX 5 A9C 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.67735220892284 30 0.0 0 VERTEX 5 A9D 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.56534354195865 30 0.0 0 VERTEX 5 A9E 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.45333487499448 30 0.0 0 VERTEX 5 A9F 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.3413262080303 30 0.0 0 VERTEX 5 AA0 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.22931754106611 30 0.0 0 VERTEX 5 AA1 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.11730887410192 30 0.0 0 VERTEX 5 AA2 330 9E8 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -72.11730887410192 30 0.0 0 SEQEND 5 AA3 330 9E8 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 AA4 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 AA5 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.12512137434996 30 0.0 0 VERTEX 5 AA6 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.6794799757976 20 -71.12512137434996 30 0.0 0 VERTEX 5 AA7 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.745367426953 20 -71.12512137434996 30 0.0 0 VERTEX 5 AA8 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.8112548781084 20 -71.12512137434996 30 0.0 0 VERTEX 5 AA9 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.87714232926381 20 -71.12512137434996 30 0.0 0 VERTEX 5 AAA 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.94302978041921 20 -71.12512137434996 30 0.0 0 VERTEX 5 AAB 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.00891723157461 20 -71.12512137434996 30 0.0 0 VERTEX 5 AAC 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.07480468273002 20 -71.12512137434996 30 0.0 0 VERTEX 5 AAD 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.14069213388542 20 -71.12512137434996 30 0.0 0 VERTEX 5 AAE 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.1763572830354 20 -71.12575118086836 30 0.0 0 VERTEX 5 AAF 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.20971516022857 20 -71.12764060042356 30 0.0 0 VERTEX 5 AB0 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.24076778407555 20 -71.13078963301554 30 0.0 0 VERTEX 5 AB1 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.26951717318698 20 -71.13519827864432 30 0.0 0 VERTEX 5 AB2 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.2959653461735 20 -71.14086653730989 30 0.0 0 VERTEX 5 AB3 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.32011432164574 20 -71.14779440901226 30 0.0 0 VERTEX 5 AB4 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.34196611821434 20 -71.15598189375143 30 0.0 0 VERTEX 5 AB5 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.36152275448993 20 -71.16542899152739 30 0.0 0 VERTEX 5 AB6 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.39222952304797 20 -71.18538901349505 30 0.0 0 VERTEX 5 AB7 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.41884860506832 20 -71.20961234112572 30 0.0 0 VERTEX 5 AB8 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.44137798194037 20 -71.23809897441937 30 0.0 0 VERTEX 5 AB9 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45981563505347 20 -71.27084891337603 30 0.0 0 VERTEX 5 ABA 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.47415954579699 20 -71.30786215799569 30 0.0 0 VERTEX 5 ABB 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.48440769556029 20 -71.34913870827833 30 0.0 0 VERTEX 5 ABC 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49055806573273 20 -71.39467856422398 30 0.0 0 VERTEX 5 ABD 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49260863770369 20 -71.44448172583263 30 0.0 0 VERTEX 5 ABE 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49049313375728 20 -71.49055449498614 30 0.0 0 VERTEX 5 ABF 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.48414662191805 20 -71.53265463840823 30 0.0 0 VERTEX 5 AC0 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.47356910218599 20 -71.5707821560989 30 0.0 0 VERTEX 5 AC1 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45876057456111 20 -71.60493704805813 30 0.0 0 VERTEX 5 AC2 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.43972103904341 20 -71.63511931428594 30 0.0 0 VERTEX 5 AC3 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.41645049563289 20 -71.66132895478232 30 0.0 0 VERTEX 5 AC4 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.38894894432954 20 -71.68356596954727 30 0.0 0 VERTEX 5 AC5 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.35721638513337 20 -71.70183035858079 30 0.0 0 VERTEX 5 AC6 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.33684389372577 20 -71.71055075652782 30 0.0 0 VERTEX 5 AC7 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.3140934789891 20 -71.7181084347486 30 0.0 0 VERTEX 5 AC8 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.28896110370207 20 -71.72450339324308 30 0.0 0 VERTEX 5 AC9 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.26144273064343 20 -71.72973563201131 30 0.0 0 VERTEX 5 ACA 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.23153432259189 20 -71.73380515105326 30 0.0 0 VERTEX 5 ACB 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.19923184232619 20 -71.73671195036894 30 0.0 0 VERTEX 5 ACC 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.16453125262505 20 -71.73845602995836 30 0.0 0 VERTEX 5 ACD 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.12742851626721 20 -71.73903738982149 30 0.0 0 VERTEX 5 ACE 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.06319901731408 20 -71.73903738982149 30 0.0 0 VERTEX 5 ACF 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.99896951836095 20 -71.73903738982149 30 0.0 0 VERTEX 5 AD0 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.93474001940783 20 -71.73903738982149 30 0.0 0 VERTEX 5 AD1 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.8705105204547 20 -71.73903738982149 30 0.0 0 VERTEX 5 AD2 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.80628102150158 20 -71.73903738982149 30 0.0 0 VERTEX 5 AD3 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.74205152254845 20 -71.73903738982149 30 0.0 0 VERTEX 5 AD4 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.67782202359532 20 -71.73903738982149 30 0.0 0 VERTEX 5 AD5 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.73903738982149 30 0.0 0 VERTEX 5 AD6 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.66229788788755 30 0.0 0 VERTEX 5 AD7 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.5855583859536 30 0.0 0 VERTEX 5 AD8 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.50881888401966 30 0.0 0 VERTEX 5 AD9 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.43207938208573 30 0.0 0 VERTEX 5 ADA 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.35533988015179 30 0.0 0 VERTEX 5 ADB 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.27860037821785 30 0.0 0 VERTEX 5 ADC 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.2018608762839 30 0.0 0 VERTEX 5 ADD 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.12512137434996 30 0.0 0 VERTEX 5 ADE 330 AA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.61359252464219 20 -71.12512137434996 30 0.0 0 SEQEND 5 ADF 330 AA4 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 AE0 330 9E4 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 184 72 1 10 18.61359252464219 20 -72.11730887410192 11 18.67187923388326 21 -72.11730887410192 72 1 10 18.67187923388326 20 -72.11730887410192 11 18.73016594312434 21 -72.11730887410192 72 1 10 18.73016594312434 20 -72.11730887410192 11 18.78845265236541 21 -72.11730887410192 72 1 10 18.78845265236541 20 -72.11730887410192 11 18.84673936160648 21 -72.11730887410192 72 1 10 18.84673936160648 20 -72.11730887410192 11 18.90502607084755 21 -72.11730887410192 72 1 10 18.90502607084755 20 -72.11730887410192 11 18.96331278008862 21 -72.11730887410192 72 1 10 18.96331278008862 20 -72.11730887410192 11 19.02159948932969 21 -72.11730887410192 72 1 10 19.02159948932969 20 -72.11730887410192 11 19.07988619857076 21 -72.11730887410192 72 1 10 19.07988619857076 20 -72.11730887410192 11 19.12777538086148 21 -72.11844737050056 72 1 10 19.12777538086148 20 -72.11844737050056 11 19.17170606769521 21 -72.12186285969648 72 1 10 19.17170606769521 20 -72.12186285969648 11 19.21167624046134 21 -72.12755534168969 72 1 10 19.21167624046134 20 -72.12755534168969 11 19.24768388054921 21 -72.13552481648017 72 1 10 19.24768388054921 20 -72.13552481648017 11 19.2797269693482 21 -72.14577128406795 72 1 10 19.2797269693482 20 -72.14577128406795 11 19.30780348824767 21 -72.158294744453 72 1 10 19.30780348824767 20 -72.158294744453 11 19.33191141863698 21 -72.17309519763533 72 1 10 19.33191141863698 20 -72.17309519763533 11 19.3520487419055 21 -72.19017264361496 72 1 10 19.3520487419055 20 -72.19017264361496 11 19.36911003900003 21 -72.2106655787905 72 1 10 19.36911003900003 20 -72.2106655787905 11 19.3839912366078 21 -72.2357124995606 72 1 10 19.3839912366078 20 -72.2357124995606 11 19.39669233472881 21 -72.26531340592527 72 1 10 19.39669233472881 20 -72.26531340592527 11 19.40721333336306 21 -72.2994682978845 72 1 10 19.40721333336306 20 -72.2994682978845 11 19.41555423251055 21 -72.3381771754383 72 1 10 19.41555423251055 20 -72.3381771754383 11 19.42171503217129 21 -72.38144003858666 72 1 10 19.42171503217129 20 -72.38144003858666 11 19.42569573234526 21 -72.4292568873296 72 1 10 19.42569573234526 20 -72.4292568873296 11 19.42749633303247 21 -72.4816277216671 72 1 10 19.42749633303247 20 -72.4816277216671 11 19.42788390627456 21 -72.5081764887503 72 1 10 19.42788390627456 20 -72.5081764887503 11 19.42827147951665 21 -72.53472525583351 72 1 10 19.42827147951665 20 -72.53472525583351 11 19.42865905275874 21 -72.5612740229167 72 1 10 19.42865905275874 20 -72.5612740229167 11 19.42904662600083 21 -72.58782278999992 72 1 10 19.42904662600083 20 -72.58782278999992 11 19.42943419924292 21 -72.61437155708312 72 1 10 19.42943419924292 20 -72.61437155708312 11 19.42982177248501 21 -72.64092032416633 72 1 10 19.42982177248501 20 -72.64092032416633 11 19.4302093457271 21 -72.66746909124953 72 1 10 19.4302093457271 20 -72.66746909124953 11 19.43059691896919 21 -72.69401785833274 72 1 10 19.43059691896919 20 -72.69401785833274 11 19.43125094881522 21 -72.71913744908574 72 1 10 19.43125094881522 20 -72.71913744908574 11 19.43243789186912 21 -72.74411169987296 72 1 10 19.43243789186912 20 -72.74411169987296 11 19.4341577481309 21 -72.76894061069439 72 1 10 19.4341577481309 20 -72.76894061069439 11 19.43641051760055 21 -72.79362418155003 72 1 10 19.43641051760055 20 -72.79362418155003 11 19.43919620027808 21 -72.81816241243989 72 1 10 19.43919620027808 20 -72.81816241243989 11 19.44251479616348 21 -72.84255530336397 72 1 10 19.44251479616348 20 -72.84255530336397 11 19.44636630525676 21 -72.86680285432226 72 1 10 19.44636630525676 20 -72.86680285432226 11 19.45075072755791 21 -72.89090506531477 72 1 10 19.45075072755791 20 -72.89090506531477 11 19.45326995363149 21 -72.90299250580247 72 1 10 19.45326995363149 20 -72.90299250580247 11 19.45617675294717 21 -72.91600043274013 72 1 10 19.45617675294717 20 -72.91600043274013 11 19.45947112550494 21 -72.92992884612777 72 1 10 19.45947112550494 20 -72.92992884612777 11 19.46315307130481 21 -72.94477774596537 72 1 10 19.46315307130481 20 -72.94477774596537 11 19.46722259034675 21 -72.96054713225293 72 1 10 19.46722259034675 20 -72.96054713225293 11 19.4716796826308 21 -72.97723700499046 72 1 10 19.4716796826308 20 -72.97723700499046 11 19.47652434815693 21 -72.99484736417794 72 1 10 19.47652434815693 20 -72.99484736417794 11 19.48175658692515 21 -73.0133782098154 72 1 10 19.48175658692515 20 -73.0133782098154 11 19.54764403808056 21 -73.0133782098154 72 1 10 19.54764403808056 20 -73.0133782098154 11 19.61353148923596 21 -73.0133782098154 72 1 10 19.61353148923596 20 -73.0133782098154 11 19.67941894039136 21 -73.0133782098154 72 1 10 19.67941894039136 20 -73.0133782098154 11 19.74530639154677 21 -73.0133782098154 72 1 10 19.74530639154677 20 -73.0133782098154 11 19.81119384270217 21 -73.0133782098154 72 1 10 19.81119384270217 20 -73.0133782098154 11 19.87708129385757 21 -73.0133782098154 72 1 10 19.87708129385757 20 -73.0133782098154 11 19.94296874501298 21 -73.0133782098154 72 1 10 19.94296874501298 20 -73.0133782098154 11 20.00885619616838 21 -73.0133782098154 72 1 10 20.00885619616838 20 -73.0133782098154 11 20.00885619616838 21 -73.00620810483673 72 1 10 20.00885619616838 20 -73.00620810483673 11 20.00885619616838 21 -72.99903799985805 72 1 10 20.00885619616838 20 -72.99903799985805 11 20.00885619616838 21 -72.99186789487938 72 1 10 20.00885619616838 20 -72.99186789487938 11 20.00885619616838 21 -72.9846977899007 72 1 10 20.00885619616838 20 -72.9846977899007 11 20.00885619616838 21 -72.97752768492202 72 1 10 20.00885619616838 20 -72.97752768492202 11 20.00885619616838 21 -72.97035757994334 72 1 10 20.00885619616838 20 -72.97035757994334 11 20.00885619616838 21 -72.96318747496467 72 1 10 20.00885619616838 20 -72.96318747496467 11 20.00885619616838 21 -72.95601736998599 72 1 10 20.00885619616838 20 -72.95601736998599 11 19.99232814871683 21 -72.94482619262062 72 1 10 19.99232814871683 20 -72.94482619262062 11 19.97736856172936 21 -72.93218161559741 72 1 10 19.97736856172936 20 -72.93218161559741 11 19.96397945381662 21 -72.91808363891637 72 1 10 19.96397945381662 20 -72.91808363891637 11 19.95216284358924 21 -72.9025322625775 72 1 10 19.95216284358924 20 -72.9025322625775 11 19.94192074965784 21 -72.88552748658076 72 1 10 19.94192074965784 20 -72.88552748658076 11 19.93325519063308 21 -72.8670693109262 72 1 10 19.93325519063308 20 -72.8670693109262 11 19.92616818512558 21 -72.84715773561379 72 1 10 19.92616818512558 20 -72.84715773561379 11 19.92066175174598 21 -72.82579276064355 72 1 10 19.92066175174598 20 -72.82579276064355 11 19.91769809489739 21 -72.81026560763229 72 1 10 19.91769809489739 20 -72.81026560763229 11 19.91513614156534 21 -72.79158942202905 72 1 10 19.91513614156534 20 -72.79158942202905 11 19.9129738731392 21 -72.76976420383383 72 1 10 19.9129738731392 20 -72.76976420383383 11 19.91120927100833 21 -72.7447899530466 72 1 10 19.91120927100833 20 -72.7447899530466 11 19.90984031656209 21 -72.71666666966742 72 1 10 19.90984031656209 20 -72.71666666966742 11 19.90886499118985 21 -72.68539435369622 72 1 10 19.90886499118985 20 -72.68539435369622 11 19.90828127628097 21 -72.65097300513305 72 1 10 19.90828127628097 20 -72.65097300513305 11 19.90808715322482 21 -72.61340262397789 72 1 10 19.90808715322482 20 -72.61340262397789 11 19.90808715322482 21 -72.59421774849442 72 1 10 19.90808715322482 20 -72.59421774849442 11 19.90808715322482 21 -72.57503287301093 72 1 10 19.90808715322482 20 -72.57503287301093 11 19.90808715322482 21 -72.55584799752744 72 1 10 19.90808715322482 20 -72.55584799752744 11 19.90808715322482 21 -72.53666312204396 72 1 10 19.90808715322482 20 -72.53666312204396 11 19.90808715322482 21 -72.51747824656047 72 1 10 19.90808715322482 20 -72.51747824656047 11 19.90808715322482 21 -72.49829337107698 72 1 10 19.90808715322482 20 -72.49829337107698 11 19.90808715322482 21 -72.4791084955935 72 1 10 19.90808715322482 20 -72.4791084955935 11 19.90808715322482 21 -72.45992362011002 72 1 10 19.90808715322482 20 -72.45992362011002 11 19.90705396101435 21 -72.40177888648367 72 1 10 19.90705396101435 20 -72.40177888648367 11 19.90395573012337 21 -72.34748969917187 72 1 10 19.90395573012337 20 -72.34748969917187 11 19.89879447916251 21 -72.29705202095334 72 1 10 19.89879447916251 20 -72.29705202095334 11 19.8915722267424 21 -72.25046181460682 72 1 10 19.8915722267424 20 -72.25046181460682 11 19.8822909914737 21 -72.20771504291103 72 1 10 19.8822909914737 20 -72.20771504291103 11 19.87095279196701 21 -72.1688076686447 72 1 10 19.87095279196701 20 -72.1688076686447 11 19.857559646833 21 -72.13373565458657 72 1 10 19.857559646833 20 -72.13373565458657 11 19.84211357468229 21 -72.10249496351534 72 1 10 19.84211357468229 20 -72.10249496351534 11 19.82420412468558 21 -72.07412204528751 72 1 10 19.82420412468558 20 -72.07412204528751 11 19.80341815453273 21 -72.04740035055983 72 1 10 19.80341815453273 20 -72.04740035055983 11 19.7797536456131 21 -72.02233391655358 72 1 10 19.7797536456131 20 -72.02233391655358 11 19.75320857931606 21 -71.99892678049002 72 1 10 19.75320857931606 20 -71.99892678049002 11 19.72378093703097 21 -71.97718297959044 72 1 10 19.72378093703097 20 -71.97718297959044 11 19.69146870014719 21 -71.95710655107611 72 1 10 19.69146870014719 20 -71.95710655107611 11 19.6562698500541 21 -71.93870153216828 72 1 10 19.6562698500541 20 -71.93870153216828 11 19.61818236814105 21 -71.92197196008826 72 1 10 19.61818236814105 20 -71.92197196008826 11 19.66379489406959 21 -71.90425596027748 72 1 10 19.66379489406959 20 -71.90425596027748 11 19.70606460078509 21 -71.88366142169994 72 1 10 19.70606460078509 20 -71.88366142169994 11 19.74499148828757 21 -71.86018430713435 72 1 10 19.74499148828757 20 -71.86018430713435 11 19.78057555657701 21 -71.83382057935943 72 1 10 19.78057555657701 20 -71.83382057935943 11 19.81281680565342 21 -71.80456620115392 72 1 10 19.81281680565342 20 -71.80456620115392 11 19.8417152355168 21 -71.77241713529654 72 1 10 19.8417152355168 20 -71.77241713529654 11 19.86727084616716 21 -71.73736934456603 72 1 10 19.86727084616716 20 -71.73736934456603 11 19.88948363760447 21 -71.69941879174111 72 1 10 19.88948363760447 20 -71.69941879174111 11 19.90874118307085 21 -71.66004848276896 72 1 10 19.90874118307085 20 -71.66004848276896 11 19.92543105580837 21 -71.62048842439702 72 1 10 19.92543105580837 20 -71.62048842439702 11 19.93955325581705 21 -71.58074265384658 72 1 10 19.93955325581705 20 -71.58074265384658 11 19.95110778309688 21 -71.54081520833893 72 1 10 19.95110778309688 20 -71.54081520833893 11 19.96009463764785 21 -71.5007101250953 72 1 10 19.96009463764785 20 -71.5007101250953 11 19.96651381946998 21 -71.460431441337 72 1 10 19.96651381946998 20 -71.460431441337 11 19.97036532856325 21 -71.41998319428527 72 1 10 19.97036532856325 20 -71.41998319428527 11 19.97164916492768 21 -71.3793694211614 72 1 10 19.97164916492768 20 -71.3793694211614 11 19.97098706063911 21 -71.34611079232451 72 1 10 19.97098706063911 20 -71.34611079232451 11 19.96900074777339 21 -71.31377264993756 72 1 10 19.96900074777339 20 -71.31377264993756 11 19.96569022633054 21 -71.2823549940006 72 1 10 19.96569022633054 20 -71.2823549940006 11 19.96105549631054 21 -71.25185782451359 72 1 10 19.96105549631054 20 -71.25185782451359 11 19.95509655771339 21 -71.22228114147656 72 1 10 19.95509655771339 20 -71.22228114147656 11 19.94781341053911 21 -71.19362494488948 72 1 10 19.94781341053911 20 -71.19362494488948 11 19.93920605478768 21 -71.16588923475237 72 1 10 19.93920605478768 20 -71.16588923475237 11 19.92927449045911 21 -71.13907401106523 72 1 10 19.92927449045911 20 -71.13907401106523 11 19.91821216773933 21 -71.11300971053464 72 1 10 19.91821216773933 20 -71.11300971053464 11 19.90621119107387 21 -71.08752676986718 72 1 10 19.90621119107387 20 -71.08752676986718 11 19.89326954185208 21 -71.06262518906286 72 1 10 19.89326954185208 20 -71.06262518906286 11 19.87938520146333 21 -71.03830496812166 72 1 10 19.87938520146333 20 -71.03830496812166 11 19.86455615129699 21 -71.01456610704362 72 1 10 19.86455615129699 20 -71.01456610704362 11 19.84878037274241 21 -70.99140860582871 72 1 10 19.84878037274241 20 -70.99140860582871 11 19.83205584718897 21 -70.96883246447693 72 1 10 19.83205584718897 20 -70.96883246447693 11 19.81438055602603 21 -70.94683768298829 72 1 10 19.81438055602603 20 -70.94683768298829 11 19.79187708465714 21 -70.92128207233793 72 1 10 19.79187708465714 20 -70.92128207233793 11 19.76816244690672 21 -70.89732520131122 72 1 10 19.76816244690672 20 -70.89732520131122 11 19.74323664277477 21 -70.87496706990811 72 1 10 19.74323664277477 20 -70.87496706990811 11 19.71709967226128 21 -70.85420767812863 72 1 10 19.71709967226128 20 -70.85420767812863 11 19.68975153536626 21 -70.83504702597278 72 1 10 19.68975153536626 20 -70.83504702597278 11 19.66119223208971 21 -70.81748511344054 72 1 10 19.66119223208971 20 -70.81748511344054 11 19.63142176243163 21 -70.80152194053194 72 1 10 19.63142176243163 20 -70.80152194053194 11 19.60044012639201 21 -70.78715750724696 72 1 10 19.60044012639201 20 -70.78715750724696 11 19.56722220620293 21 -70.77436759025797 72 1 10 19.56722220620293 20 -70.77436759025797 11 19.5306150387562 21 -70.76312796623733 72 1 10 19.5306150387562 20 -70.76312796623733 11 19.49062064266245 21 -70.75343863518508 72 1 10 19.49062064266245 20 -70.75343863518508 11 19.44724103653231 21 -70.74529959710117 72 1 10 19.44724103653231 20 -70.74529959710117 11 19.40047823897642 21 -70.73871085198563 72 1 10 19.40047823897642 20 -70.73871085198563 11 19.35033426860542 21 -70.73367239983845 72 1 10 19.35033426860542 20 -70.73367239983845 11 19.29681114402993 21 -70.73018424065964 72 1 10 19.29681114402993 20 -70.73018424065964 11 19.23991088386061 21 -70.72824637444918 72 1 10 19.23991088386061 20 -70.72824637444918 11 19.10329131602368 21 -70.72824637444918 72 1 10 19.10329131602368 20 -70.72824637444918 11 18.96667174818674 21 -70.72824637444918 72 1 10 18.96667174818674 20 -70.72824637444918 11 18.8300521803498 21 -70.72824637444918 72 1 10 18.8300521803498 20 -70.72824637444918 11 18.69343261251286 21 -70.72824637444918 72 1 10 18.69343261251286 20 -70.72824637444918 11 18.55681304467592 21 -70.72824637444918 72 1 10 18.55681304467592 20 -70.72824637444918 11 18.42019347683898 21 -70.72824637444918 72 1 10 18.42019347683898 20 -70.72824637444918 11 18.28357390900204 21 -70.72824637444918 72 1 10 18.28357390900204 20 -70.72824637444918 11 18.1469543411651 21 -70.72824637444918 72 1 10 18.1469543411651 20 -70.72824637444918 11 18.1469543411651 21 -71.01388785386996 72 1 10 18.1469543411651 20 -71.01388785386996 11 18.1469543411651 21 -71.29952933329074 72 1 10 18.1469543411651 20 -71.29952933329074 11 18.1469543411651 21 -71.58517081271151 72 1 10 18.1469543411651 20 -71.58517081271151 11 18.1469543411651 21 -71.8708122921323 72 1 10 18.1469543411651 20 -71.8708122921323 11 18.1469543411651 21 -72.15645377155307 72 1 10 18.1469543411651 20 -72.15645377155307 11 18.1469543411651 21 -72.44209525097385 72 1 10 18.1469543411651 20 -72.44209525097385 11 18.1469543411651 21 -72.72773673039462 72 1 10 18.1469543411651 20 -72.72773673039462 11 18.1469543411651 21 -73.0133782098154 72 1 10 18.1469543411651 20 -73.0133782098154 11 18.20528411409974 21 -73.0133782098154 72 1 10 18.20528411409974 20 -73.0133782098154 11 18.26361388703438 21 -73.0133782098154 72 1 10 18.26361388703438 20 -73.0133782098154 11 18.32194365996901 21 -73.0133782098154 72 1 10 18.32194365996901 20 -73.0133782098154 11 18.38027343290365 21 -73.0133782098154 72 1 10 18.38027343290365 20 -73.0133782098154 11 18.43860320583828 21 -73.0133782098154 72 1 10 18.43860320583828 20 -73.0133782098154 11 18.49693297877292 21 -73.0133782098154 72 1 10 18.49693297877292 20 -73.0133782098154 11 18.55526275170756 21 -73.0133782098154 72 1 10 18.55526275170756 20 -73.0133782098154 11 18.61359252464219 21 -73.0133782098154 72 1 10 18.61359252464219 20 -73.0133782098154 11 18.61359252464219 21 -72.90136954285121 72 1 10 18.61359252464219 20 -72.90136954285121 11 18.61359252464219 21 -72.78936087588703 72 1 10 18.61359252464219 20 -72.78936087588703 11 18.61359252464219 21 -72.67735220892284 72 1 10 18.61359252464219 20 -72.67735220892284 11 18.61359252464219 21 -72.56534354195865 72 1 10 18.61359252464219 20 -72.56534354195865 11 18.61359252464219 21 -72.45333487499448 72 1 10 18.61359252464219 20 -72.45333487499448 11 18.61359252464219 21 -72.3413262080303 72 1 10 18.61359252464219 20 -72.3413262080303 11 18.61359252464219 21 -72.22931754106611 72 1 10 18.61359252464219 20 -72.22931754106611 11 18.61359252464219 21 -72.11730887410192 97 0 92 1 93 56 72 1 10 18.61359252464219 20 -71.12512137434996 11 18.6794799757976 21 -71.12512137434996 72 1 10 18.6794799757976 20 -71.12512137434996 11 18.745367426953 21 -71.12512137434996 72 1 10 18.745367426953 20 -71.12512137434996 11 18.8112548781084 21 -71.12512137434996 72 1 10 18.8112548781084 20 -71.12512137434996 11 18.87714232926381 21 -71.12512137434996 72 1 10 18.87714232926381 20 -71.12512137434996 11 18.94302978041921 21 -71.12512137434996 72 1 10 18.94302978041921 20 -71.12512137434996 11 19.00891723157461 21 -71.12512137434996 72 1 10 19.00891723157461 20 -71.12512137434996 11 19.07480468273002 21 -71.12512137434996 72 1 10 19.07480468273002 20 -71.12512137434996 11 19.14069213388542 21 -71.12512137434996 72 1 10 19.14069213388542 20 -71.12512137434996 11 19.1763572830354 21 -71.12575118086836 72 1 10 19.1763572830354 20 -71.12575118086836 11 19.20971516022857 21 -71.12764060042356 72 1 10 19.20971516022857 20 -71.12764060042356 11 19.24076778407555 21 -71.13078963301554 72 1 10 19.24076778407555 20 -71.13078963301554 11 19.26951717318698 21 -71.13519827864432 72 1 10 19.26951717318698 20 -71.13519827864432 11 19.2959653461735 21 -71.14086653730989 72 1 10 19.2959653461735 20 -71.14086653730989 11 19.32011432164574 21 -71.14779440901226 72 1 10 19.32011432164574 20 -71.14779440901226 11 19.34196611821434 21 -71.15598189375143 72 1 10 19.34196611821434 20 -71.15598189375143 11 19.36152275448993 21 -71.16542899152739 72 1 10 19.36152275448993 20 -71.16542899152739 11 19.39222952304797 21 -71.18538901349505 72 1 10 19.39222952304797 20 -71.18538901349505 11 19.41884860506832 21 -71.20961234112572 72 1 10 19.41884860506832 20 -71.20961234112572 11 19.44137798194037 21 -71.23809897441937 72 1 10 19.44137798194037 20 -71.23809897441937 11 19.45981563505347 21 -71.27084891337603 72 1 10 19.45981563505347 20 -71.27084891337603 11 19.47415954579699 21 -71.30786215799569 72 1 10 19.47415954579699 20 -71.30786215799569 11 19.48440769556029 21 -71.34913870827833 72 1 10 19.48440769556029 20 -71.34913870827833 11 19.49055806573273 21 -71.39467856422398 72 1 10 19.49055806573273 20 -71.39467856422398 11 19.49260863770369 21 -71.44448172583263 72 1 10 19.49260863770369 20 -71.44448172583263 11 19.49049313375728 21 -71.49055449498614 72 1 10 19.49049313375728 20 -71.49055449498614 11 19.48414662191805 21 -71.53265463840823 72 1 10 19.48414662191805 20 -71.53265463840823 11 19.47356910218599 21 -71.5707821560989 72 1 10 19.47356910218599 20 -71.5707821560989 11 19.45876057456111 21 -71.60493704805813 72 1 10 19.45876057456111 20 -71.60493704805813 11 19.43972103904341 21 -71.63511931428594 72 1 10 19.43972103904341 20 -71.63511931428594 11 19.41645049563289 21 -71.66132895478232 72 1 10 19.41645049563289 20 -71.66132895478232 11 19.38894894432954 21 -71.68356596954727 72 1 10 19.38894894432954 20 -71.68356596954727 11 19.35721638513337 21 -71.70183035858079 72 1 10 19.35721638513337 20 -71.70183035858079 11 19.33684389372577 21 -71.71055075652782 72 1 10 19.33684389372577 20 -71.71055075652782 11 19.3140934789891 21 -71.7181084347486 72 1 10 19.3140934789891 20 -71.7181084347486 11 19.28896110370207 21 -71.72450339324308 72 1 10 19.28896110370207 20 -71.72450339324308 11 19.26144273064343 21 -71.72973563201131 72 1 10 19.26144273064343 20 -71.72973563201131 11 19.23153432259189 21 -71.73380515105326 72 1 10 19.23153432259189 20 -71.73380515105326 11 19.19923184232619 21 -71.73671195036894 72 1 10 19.19923184232619 20 -71.73671195036894 11 19.16453125262505 21 -71.73845602995836 72 1 10 19.16453125262505 20 -71.73845602995836 11 19.12742851626721 21 -71.73903738982149 72 1 10 19.12742851626721 20 -71.73903738982149 11 19.06319901731408 21 -71.73903738982149 72 1 10 19.06319901731408 20 -71.73903738982149 11 18.99896951836095 21 -71.73903738982149 72 1 10 18.99896951836095 20 -71.73903738982149 11 18.93474001940783 21 -71.73903738982149 72 1 10 18.93474001940783 20 -71.73903738982149 11 18.8705105204547 21 -71.73903738982149 72 1 10 18.8705105204547 20 -71.73903738982149 11 18.80628102150158 21 -71.73903738982149 72 1 10 18.80628102150158 20 -71.73903738982149 11 18.74205152254845 21 -71.73903738982149 72 1 10 18.74205152254845 20 -71.73903738982149 11 18.67782202359532 21 -71.73903738982149 72 1 10 18.67782202359532 20 -71.73903738982149 11 18.61359252464219 21 -71.73903738982149 72 1 10 18.61359252464219 20 -71.73903738982149 11 18.61359252464219 21 -71.66229788788755 72 1 10 18.61359252464219 20 -71.66229788788755 11 18.61359252464219 21 -71.5855583859536 72 1 10 18.61359252464219 20 -71.5855583859536 11 18.61359252464219 21 -71.50881888401966 72 1 10 18.61359252464219 20 -71.50881888401966 11 18.61359252464219 21 -71.43207938208573 72 1 10 18.61359252464219 20 -71.43207938208573 11 18.61359252464219 21 -71.35533988015179 72 1 10 18.61359252464219 20 -71.35533988015179 11 18.61359252464219 21 -71.27860037821785 72 1 10 18.61359252464219 20 -71.27860037821785 11 18.61359252464219 21 -71.2018608762839 72 1 10 18.61359252464219 20 -71.2018608762839 11 18.61359252464219 21 -71.12512137434996 97 0 75 2 76 1 98 0 0 POLYLINE 5 AE1 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 AE2 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.08252020414649 20 -70.72824637444918 30 0.0 0 VERTEX 5 AE3 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.98054537778309 20 -71.01388785386996 30 0.0 0 VERTEX 5 AE4 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.8785705514197 20 -71.29952933329074 30 0.0 0 VERTEX 5 AE5 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7765957250563 20 -71.58517081271151 30 0.0 0 VERTEX 5 AE6 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.67462089869291 20 -71.8708122921323 30 0.0 0 VERTEX 5 AE7 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.57264607232952 20 -72.15645377155307 30 0.0 0 VERTEX 5 AE8 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.47067124596612 20 -72.44209525097385 30 0.0 0 VERTEX 5 AE9 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.36869641960272 20 -72.72773673039462 30 0.0 0 VERTEX 5 AEA 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.26672159323933 20 -73.0133782098154 30 0.0 0 VERTEX 5 AEB 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.32916394890948 20 -73.0133782098154 30 0.0 0 VERTEX 5 AEC 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.39160630457964 20 -73.0133782098154 30 0.0 0 VERTEX 5 AED 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.45404866024979 20 -73.0133782098154 30 0.0 0 VERTEX 5 AEE 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.51649101591994 20 -73.0133782098154 30 0.0 0 VERTEX 5 AEF 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.5789333715901 20 -73.0133782098154 30 0.0 0 VERTEX 5 AF0 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.64137572726025 20 -73.0133782098154 30 0.0 0 VERTEX 5 AF1 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7038180829304 20 -73.0133782098154 30 0.0 0 VERTEX 5 AF2 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.76626043860055 20 -73.0133782098154 30 0.0 0 VERTEX 5 AF3 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7856175688583 20 -72.95466086363868 30 0.0 0 VERTEX 5 AF4 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.80497469911605 20 -72.89594351746194 30 0.0 0 VERTEX 5 AF5 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.8243318293738 20 -72.83722617128522 30 0.0 0 VERTEX 5 AF6 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.84368895963155 20 -72.77850882510849 30 0.0 0 VERTEX 5 AF7 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.86304608988929 20 -72.71979147893177 30 0.0 0 VERTEX 5 AF8 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.88240322014704 20 -72.66107413275505 30 0.0 0 VERTEX 5 AF9 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.90176035040479 20 -72.60235678657831 30 0.0 0 VERTEX 5 AFA 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.92111748066253 20 -72.54363944040159 30 0.0 0 VERTEX 5 AFB 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02630055219657 20 -72.54363944040159 30 0.0 0 VERTEX 5 AFC 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.1314836237306 20 -72.54363944040159 30 0.0 0 VERTEX 5 AFD 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.23666669526464 20 -72.54363944040159 30 0.0 0 VERTEX 5 AFE 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.34184976679867 20 -72.54363944040159 30 0.0 0 VERTEX 5 AFF 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.44703283833271 20 -72.54363944040159 30 0.0 0 VERTEX 5 B00 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.55221590986674 20 -72.54363944040159 30 0.0 0 VERTEX 5 B01 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.65739898140077 20 -72.54363944040159 30 0.0 0 VERTEX 5 B02 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.76258205293481 20 -72.54363944040159 30 0.0 0 VERTEX 5 B03 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.78144395071655 20 -72.60235678657831 30 0.0 0 VERTEX 5 B04 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.80030584849829 20 -72.66107413275505 30 0.0 0 VERTEX 5 B05 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.81916774628004 20 -72.71979147893177 30 0.0 0 VERTEX 5 B06 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.83802964406178 20 -72.77850882510849 30 0.0 0 VERTEX 5 B07 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.85689154184352 20 -72.83722617128522 30 0.0 0 VERTEX 5 B08 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.87575343962526 20 -72.89594351746194 30 0.0 0 VERTEX 5 B09 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.89461533740701 20 -72.95466086363868 30 0.0 0 VERTEX 5 B0A 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.91347723518875 20 -73.0133782098154 30 0.0 0 VERTEX 5 B0B 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.97820196661788 20 -73.0133782098154 30 0.0 0 VERTEX 5 B0C 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.04292669804702 20 -73.0133782098154 30 0.0 0 VERTEX 5 B0D 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.10765142947615 20 -73.0133782098154 30 0.0 0 VERTEX 5 B0E 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17237616090528 20 -73.0133782098154 30 0.0 0 VERTEX 5 B0F 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.23710089233441 20 -73.0133782098154 30 0.0 0 VERTEX 5 B10 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.30182562376354 20 -73.0133782098154 30 0.0 0 VERTEX 5 B11 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36655035519267 20 -73.0133782098154 30 0.0 0 VERTEX 5 B12 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.4312750866218 20 -73.0133782098154 30 0.0 0 VERTEX 5 B13 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.33020459782329 20 -72.72773673039462 30 0.0 0 VERTEX 5 B14 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.22913410902477 20 -72.44209525097385 30 0.0 0 VERTEX 5 B15 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.12806362022625 20 -72.15645377155307 30 0.0 0 VERTEX 5 B16 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.02699313142773 20 -71.8708122921323 30 0.0 0 VERTEX 5 B17 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.92592264262922 20 -71.58517081271151 30 0.0 0 VERTEX 5 B18 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.8248521538307 20 -71.29952933329074 30 0.0 0 VERTEX 5 B19 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.72378166503218 20 -71.01388785386996 30 0.0 0 VERTEX 5 B1A 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.62271117623366 20 -70.72824637444918 30 0.0 0 VERTEX 5 B1B 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.55518730472277 20 -70.72824637444918 30 0.0 0 VERTEX 5 B1C 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.48766343321187 20 -70.72824637444918 30 0.0 0 VERTEX 5 B1D 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.42013956170097 20 -70.72824637444918 30 0.0 0 VERTEX 5 B1E 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.35261569019008 20 -70.72824637444918 30 0.0 0 VERTEX 5 B1F 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.28509181867918 20 -70.72824637444918 30 0.0 0 VERTEX 5 B20 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.21756794716828 20 -70.72824637444918 30 0.0 0 VERTEX 5 B21 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.15004407565739 20 -70.72824637444918 30 0.0 0 VERTEX 5 B22 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.08252020414649 20 -70.72824637444918 30 0.0 0 VERTEX 5 B23 330 AE1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.08252020414649 20 -70.72824637444918 30 0.0 0 SEQEND 5 B24 330 AE1 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 B25 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 B26 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.05099758045645 20 -72.14986502643752 30 0.0 0 VERTEX 5 B27 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.08805388876967 20 -72.03746878623126 30 0.0 0 VERTEX 5 B28 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.12511019708289 20 -71.92507254602498 30 0.0 0 VERTEX 5 B29 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.16216650539611 20 -71.8126763058187 30 0.0 0 VERTEX 5 B2A 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.19922281370933 20 -71.70028006561243 30 0.0 0 VERTEX 5 B2B 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.23627912202255 20 -71.58788382540615 30 0.0 0 VERTEX 5 B2C 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.27333543033577 20 -71.47548758519987 30 0.0 0 VERTEX 5 B2D 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.31039173864898 20 -71.36309134499359 30 0.0 0 VERTEX 5 B2E 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.3474480469622 20 -71.25069510478733 30 0.0 0 VERTEX 5 B2F 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.38353542217019 20 -71.36309134499359 30 0.0 0 VERTEX 5 B30 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.41962279737819 20 -71.47548758519987 30 0.0 0 VERTEX 5 B31 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.45571017258618 20 -71.58788382540615 30 0.0 0 VERTEX 5 B32 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.49179754779417 20 -71.70028006561243 30 0.0 0 VERTEX 5 B33 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.52788492300216 20 -71.8126763058187 30 0.0 0 VERTEX 5 B34 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.56397229821016 20 -71.92507254602498 30 0.0 0 VERTEX 5 B35 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.60005967341815 20 -72.03746878623126 30 0.0 0 VERTEX 5 B36 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.63614704862614 20 -72.14986502643752 30 0.0 0 VERTEX 5 B37 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.56300336510493 20 -72.14986502643752 30 0.0 0 VERTEX 5 B38 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.48985968158372 20 -72.14986502643752 30 0.0 0 VERTEX 5 B39 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.41671599806251 20 -72.14986502643752 30 0.0 0 VERTEX 5 B3A 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.3435723145413 20 -72.14986502643752 30 0.0 0 VERTEX 5 B3B 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.27042863102008 20 -72.14986502643752 30 0.0 0 VERTEX 5 B3C 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.19728494749888 20 -72.14986502643752 30 0.0 0 VERTEX 5 B3D 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.12414126397767 20 -72.14986502643752 30 0.0 0 VERTEX 5 B3E 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.05099758045645 20 -72.14986502643752 30 0.0 0 VERTEX 5 B3F 330 B25 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.05099758045645 20 -72.14986502643752 30 0.0 0 SEQEND 5 B40 330 B25 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 B41 330 9E4 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 64 72 1 10 21.08252020414649 20 -70.72824637444918 11 20.98054537778309 21 -71.01388785386996 72 1 10 20.98054537778309 20 -71.01388785386996 11 20.8785705514197 21 -71.29952933329074 72 1 10 20.8785705514197 20 -71.29952933329074 11 20.7765957250563 21 -71.58517081271151 72 1 10 20.7765957250563 20 -71.58517081271151 11 20.67462089869291 21 -71.8708122921323 72 1 10 20.67462089869291 20 -71.8708122921323 11 20.57264607232952 21 -72.15645377155307 72 1 10 20.57264607232952 20 -72.15645377155307 11 20.47067124596612 21 -72.44209525097385 72 1 10 20.47067124596612 20 -72.44209525097385 11 20.36869641960272 21 -72.72773673039462 72 1 10 20.36869641960272 20 -72.72773673039462 11 20.26672159323933 21 -73.0133782098154 72 1 10 20.26672159323933 20 -73.0133782098154 11 20.32916394890948 21 -73.0133782098154 72 1 10 20.32916394890948 20 -73.0133782098154 11 20.39160630457964 21 -73.0133782098154 72 1 10 20.39160630457964 20 -73.0133782098154 11 20.45404866024979 21 -73.0133782098154 72 1 10 20.45404866024979 20 -73.0133782098154 11 20.51649101591994 21 -73.0133782098154 72 1 10 20.51649101591994 20 -73.0133782098154 11 20.5789333715901 21 -73.0133782098154 72 1 10 20.5789333715901 20 -73.0133782098154 11 20.64137572726025 21 -73.0133782098154 72 1 10 20.64137572726025 20 -73.0133782098154 11 20.7038180829304 21 -73.0133782098154 72 1 10 20.7038180829304 20 -73.0133782098154 11 20.76626043860055 21 -73.0133782098154 72 1 10 20.76626043860055 20 -73.0133782098154 11 20.7856175688583 21 -72.95466086363868 72 1 10 20.7856175688583 20 -72.95466086363868 11 20.80497469911605 21 -72.89594351746194 72 1 10 20.80497469911605 20 -72.89594351746194 11 20.8243318293738 21 -72.83722617128522 72 1 10 20.8243318293738 20 -72.83722617128522 11 20.84368895963155 21 -72.77850882510849 72 1 10 20.84368895963155 20 -72.77850882510849 11 20.86304608988929 21 -72.71979147893177 72 1 10 20.86304608988929 20 -72.71979147893177 11 20.88240322014704 21 -72.66107413275505 72 1 10 20.88240322014704 20 -72.66107413275505 11 20.90176035040479 21 -72.60235678657831 72 1 10 20.90176035040479 20 -72.60235678657831 11 20.92111748066253 21 -72.54363944040159 72 1 10 20.92111748066253 20 -72.54363944040159 11 21.02630055219657 21 -72.54363944040159 72 1 10 21.02630055219657 20 -72.54363944040159 11 21.1314836237306 21 -72.54363944040159 72 1 10 21.1314836237306 20 -72.54363944040159 11 21.23666669526464 21 -72.54363944040159 72 1 10 21.23666669526464 20 -72.54363944040159 11 21.34184976679867 21 -72.54363944040159 72 1 10 21.34184976679867 20 -72.54363944040159 11 21.44703283833271 21 -72.54363944040159 72 1 10 21.44703283833271 20 -72.54363944040159 11 21.55221590986674 21 -72.54363944040159 72 1 10 21.55221590986674 20 -72.54363944040159 11 21.65739898140077 21 -72.54363944040159 72 1 10 21.65739898140077 20 -72.54363944040159 11 21.76258205293481 21 -72.54363944040159 72 1 10 21.76258205293481 20 -72.54363944040159 11 21.78144395071655 21 -72.60235678657831 72 1 10 21.78144395071655 20 -72.60235678657831 11 21.80030584849829 21 -72.66107413275505 72 1 10 21.80030584849829 20 -72.66107413275505 11 21.81916774628004 21 -72.71979147893177 72 1 10 21.81916774628004 20 -72.71979147893177 11 21.83802964406178 21 -72.77850882510849 72 1 10 21.83802964406178 20 -72.77850882510849 11 21.85689154184352 21 -72.83722617128522 72 1 10 21.85689154184352 20 -72.83722617128522 11 21.87575343962526 21 -72.89594351746194 72 1 10 21.87575343962526 20 -72.89594351746194 11 21.89461533740701 21 -72.95466086363868 72 1 10 21.89461533740701 20 -72.95466086363868 11 21.91347723518875 21 -73.0133782098154 72 1 10 21.91347723518875 20 -73.0133782098154 11 21.97820196661788 21 -73.0133782098154 72 1 10 21.97820196661788 20 -73.0133782098154 11 22.04292669804702 21 -73.0133782098154 72 1 10 22.04292669804702 20 -73.0133782098154 11 22.10765142947615 21 -73.0133782098154 72 1 10 22.10765142947615 20 -73.0133782098154 11 22.17237616090528 21 -73.0133782098154 72 1 10 22.17237616090528 20 -73.0133782098154 11 22.23710089233441 21 -73.0133782098154 72 1 10 22.23710089233441 20 -73.0133782098154 11 22.30182562376354 21 -73.0133782098154 72 1 10 22.30182562376354 20 -73.0133782098154 11 22.36655035519267 21 -73.0133782098154 72 1 10 22.36655035519267 20 -73.0133782098154 11 22.4312750866218 21 -73.0133782098154 72 1 10 22.4312750866218 20 -73.0133782098154 11 22.33020459782329 21 -72.72773673039462 72 1 10 22.33020459782329 20 -72.72773673039462 11 22.22913410902477 21 -72.44209525097385 72 1 10 22.22913410902477 20 -72.44209525097385 11 22.12806362022625 21 -72.15645377155307 72 1 10 22.12806362022625 20 -72.15645377155307 11 22.02699313142773 21 -71.8708122921323 72 1 10 22.02699313142773 20 -71.8708122921323 11 21.92592264262922 21 -71.58517081271151 72 1 10 21.92592264262922 20 -71.58517081271151 11 21.8248521538307 21 -71.29952933329074 72 1 10 21.8248521538307 20 -71.29952933329074 11 21.72378166503218 21 -71.01388785386996 72 1 10 21.72378166503218 20 -71.01388785386996 11 21.62271117623366 21 -70.72824637444918 72 1 10 21.62271117623366 20 -70.72824637444918 11 21.55518730472277 21 -70.72824637444918 72 1 10 21.55518730472277 20 -70.72824637444918 11 21.48766343321187 21 -70.72824637444918 72 1 10 21.48766343321187 20 -70.72824637444918 11 21.42013956170097 21 -70.72824637444918 72 1 10 21.42013956170097 20 -70.72824637444918 11 21.35261569019008 21 -70.72824637444918 72 1 10 21.35261569019008 20 -70.72824637444918 11 21.28509181867918 21 -70.72824637444918 72 1 10 21.28509181867918 20 -70.72824637444918 11 21.21756794716828 21 -70.72824637444918 72 1 10 21.21756794716828 20 -70.72824637444918 11 21.15004407565739 21 -70.72824637444918 72 1 10 21.15004407565739 20 -70.72824637444918 11 21.08252020414649 21 -70.72824637444918 97 0 92 1 93 24 72 1 10 21.05099758045645 20 -72.14986502643752 11 21.08805388876967 21 -72.03746878623126 72 1 10 21.08805388876967 20 -72.03746878623126 11 21.12511019708289 21 -71.92507254602498 72 1 10 21.12511019708289 20 -71.92507254602498 11 21.16216650539611 21 -71.8126763058187 72 1 10 21.16216650539611 20 -71.8126763058187 11 21.19922281370933 21 -71.70028006561243 72 1 10 21.19922281370933 20 -71.70028006561243 11 21.23627912202255 21 -71.58788382540615 72 1 10 21.23627912202255 20 -71.58788382540615 11 21.27333543033577 21 -71.47548758519987 72 1 10 21.27333543033577 20 -71.47548758519987 11 21.31039173864898 21 -71.36309134499359 72 1 10 21.31039173864898 20 -71.36309134499359 11 21.3474480469622 21 -71.25069510478733 72 1 10 21.3474480469622 20 -71.25069510478733 11 21.38353542217019 21 -71.36309134499359 72 1 10 21.38353542217019 20 -71.36309134499359 11 21.41962279737819 21 -71.47548758519987 72 1 10 21.41962279737819 20 -71.47548758519987 11 21.45571017258618 21 -71.58788382540615 72 1 10 21.45571017258618 20 -71.58788382540615 11 21.49179754779417 21 -71.70028006561243 72 1 10 21.49179754779417 20 -71.70028006561243 11 21.52788492300216 21 -71.8126763058187 72 1 10 21.52788492300216 20 -71.8126763058187 11 21.56397229821016 21 -71.92507254602498 72 1 10 21.56397229821016 20 -71.92507254602498 11 21.60005967341815 21 -72.03746878623126 72 1 10 21.60005967341815 20 -72.03746878623126 11 21.63614704862614 21 -72.14986502643752 72 1 10 21.63614704862614 20 -72.14986502643752 11 21.56300336510493 21 -72.14986502643752 72 1 10 21.56300336510493 20 -72.14986502643752 11 21.48985968158372 21 -72.14986502643752 72 1 10 21.48985968158372 20 -72.14986502643752 11 21.41671599806251 21 -72.14986502643752 72 1 10 21.41671599806251 20 -72.14986502643752 11 21.3435723145413 21 -72.14986502643752 72 1 10 21.3435723145413 20 -72.14986502643752 11 21.27042863102008 21 -72.14986502643752 72 1 10 21.27042863102008 20 -72.14986502643752 11 21.19728494749888 21 -72.14986502643752 72 1 10 21.19728494749888 20 -72.14986502643752 11 21.12414126397767 21 -72.14986502643752 72 1 10 21.12414126397767 20 -72.14986502643752 11 21.05099758045645 21 -72.14986502643752 97 0 75 2 76 1 98 0 0 POLYLINE 5 B42 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 B43 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -73.0133782098154 30 0.0 0 VERTEX 5 B44 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -72.77831503848745 30 0.0 0 VERTEX 5 B45 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -72.5432518671595 30 0.0 0 VERTEX 5 B46 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -72.30818869583155 30 0.0 0 VERTEX 5 B47 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -72.0731255245036 30 0.0 0 VERTEX 5 B48 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -71.83806235317563 30 0.0 0 VERTEX 5 B49 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -71.60299918184768 30 0.0 0 VERTEX 5 B4A 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -71.36793601051973 30 0.0 0 VERTEX 5 B4B 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -71.13287283919178 30 0.0 0 VERTEX 5 B4C 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.54991912252921 20 -71.13287283919178 30 0.0 0 VERTEX 5 B4D 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.63537902241018 20 -71.13287283919178 30 0.0 0 VERTEX 5 B4E 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.72083892229116 20 -71.13287283919178 30 0.0 0 VERTEX 5 B4F 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.80629882217214 20 -71.13287283919178 30 0.0 0 VERTEX 5 B50 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.89175872205312 20 -71.13287283919178 30 0.0 0 VERTEX 5 B51 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.9772186219341 20 -71.13287283919178 30 0.0 0 VERTEX 5 B52 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.06267852181508 20 -71.13287283919178 30 0.0 0 VERTEX 5 B53 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -71.13287283919178 30 0.0 0 VERTEX 5 B54 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -71.08229453109895 30 0.0 0 VERTEX 5 B55 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -71.03171622300613 30 0.0 0 VERTEX 5 B56 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -70.9811379149133 30 0.0 0 VERTEX 5 B57 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -70.93055960682048 30 0.0 0 VERTEX 5 B58 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -70.87998129872766 30 0.0 0 VERTEX 5 B59 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -70.82940299063483 30 0.0 0 VERTEX 5 B5A 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -70.77882468254201 30 0.0 0 VERTEX 5 B5B 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14813842169606 20 -70.72824637444918 30 0.0 0 VERTEX 5 B5C 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.91675719616796 20 -70.72824637444918 30 0.0 0 VERTEX 5 B5D 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.68537597063987 20 -70.72824637444918 30 0.0 0 VERTEX 5 B5E 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.45399474511178 20 -70.72824637444918 30 0.0 0 VERTEX 5 B5F 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.22261351958369 20 -70.72824637444918 30 0.0 0 VERTEX 5 B60 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9912322940556 20 -70.72824637444918 30 0.0 0 VERTEX 5 B61 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.75985106852751 20 -70.72824637444918 30 0.0 0 VERTEX 5 B62 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.52846984299941 20 -70.72824637444918 30 0.0 0 VERTEX 5 B63 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -70.72824637444918 30 0.0 0 VERTEX 5 B64 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -70.77882468254201 30 0.0 0 VERTEX 5 B65 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -70.82940299063483 30 0.0 0 VERTEX 5 B66 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -70.87998129872766 30 0.0 0 VERTEX 5 B67 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -70.93055960682048 30 0.0 0 VERTEX 5 B68 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -70.9811379149133 30 0.0 0 VERTEX 5 B69 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -71.03171622300613 30 0.0 0 VERTEX 5 B6A 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -71.08229453109895 30 0.0 0 VERTEX 5 B6B 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.29708861747132 20 -71.13287283919178 30 0.0 0 VERTEX 5 B6C 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.38293609059439 20 -71.13287283919178 30 0.0 0 VERTEX 5 B6D 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.46878356371746 20 -71.13287283919178 30 0.0 0 VERTEX 5 B6E 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.55463103684053 20 -71.13287283919178 30 0.0 0 VERTEX 5 B6F 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.6404785099636 20 -71.13287283919178 30 0.0 0 VERTEX 5 B70 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.72632598308667 20 -71.13287283919178 30 0.0 0 VERTEX 5 B71 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.81217345620974 20 -71.13287283919178 30 0.0 0 VERTEX 5 B72 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.89802092933281 20 -71.13287283919178 30 0.0 0 VERTEX 5 B73 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -71.13287283919178 30 0.0 0 VERTEX 5 B74 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -71.36793601051973 30 0.0 0 VERTEX 5 B75 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -71.60299918184768 30 0.0 0 VERTEX 5 B76 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -71.83806235317563 30 0.0 0 VERTEX 5 B77 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -72.0731255245036 30 0.0 0 VERTEX 5 B78 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -72.30818869583155 30 0.0 0 VERTEX 5 B79 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -72.5432518671595 30 0.0 0 VERTEX 5 B7A 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -72.77831503848745 30 0.0 0 VERTEX 5 B7B 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.98386840245588 20 -73.0133782098154 30 0.0 0 VERTEX 5 B7C 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.04394225497992 20 -73.0133782098154 30 0.0 0 VERTEX 5 B7D 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.10401610750396 20 -73.0133782098154 30 0.0 0 VERTEX 5 B7E 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.16408996002801 20 -73.0133782098154 30 0.0 0 VERTEX 5 B7F 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.22416381255205 20 -73.0133782098154 30 0.0 0 VERTEX 5 B80 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.28423766507609 20 -73.0133782098154 30 0.0 0 VERTEX 5 B81 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.34431151760014 20 -73.0133782098154 30 0.0 0 VERTEX 5 B82 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.40438537012419 20 -73.0133782098154 30 0.0 0 VERTEX 5 B83 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -73.0133782098154 30 0.0 0 VERTEX 5 B84 330 B42 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46445922264823 20 -73.0133782098154 30 0.0 0 SEQEND 5 B86 330 B42 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 B85 330 9E4 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 23.46445922264823 20 -73.0133782098154 11 23.46445922264823 21 -72.77831503848745 72 1 10 23.46445922264823 20 -72.77831503848745 11 23.46445922264823 21 -72.5432518671595 72 1 10 23.46445922264823 20 -72.5432518671595 11 23.46445922264823 21 -72.30818869583155 72 1 10 23.46445922264823 20 -72.30818869583155 11 23.46445922264823 21 -72.0731255245036 72 1 10 23.46445922264823 20 -72.0731255245036 11 23.46445922264823 21 -71.83806235317563 72 1 10 23.46445922264823 20 -71.83806235317563 11 23.46445922264823 21 -71.60299918184768 72 1 10 23.46445922264823 20 -71.60299918184768 11 23.46445922264823 21 -71.36793601051973 72 1 10 23.46445922264823 20 -71.36793601051973 11 23.46445922264823 21 -71.13287283919178 72 1 10 23.46445922264823 20 -71.13287283919178 11 23.54991912252921 21 -71.13287283919178 72 1 10 23.54991912252921 20 -71.13287283919178 11 23.63537902241018 21 -71.13287283919178 72 1 10 23.63537902241018 20 -71.13287283919178 11 23.72083892229116 21 -71.13287283919178 72 1 10 23.72083892229116 20 -71.13287283919178 11 23.80629882217214 21 -71.13287283919178 72 1 10 23.80629882217214 20 -71.13287283919178 11 23.89175872205312 21 -71.13287283919178 72 1 10 23.89175872205312 20 -71.13287283919178 11 23.9772186219341 21 -71.13287283919178 72 1 10 23.9772186219341 20 -71.13287283919178 11 24.06267852181508 21 -71.13287283919178 72 1 10 24.06267852181508 20 -71.13287283919178 11 24.14813842169606 21 -71.13287283919178 72 1 10 24.14813842169606 20 -71.13287283919178 11 24.14813842169606 21 -71.08229453109895 72 1 10 24.14813842169606 20 -71.08229453109895 11 24.14813842169606 21 -71.03171622300613 72 1 10 24.14813842169606 20 -71.03171622300613 11 24.14813842169606 21 -70.9811379149133 72 1 10 24.14813842169606 20 -70.9811379149133 11 24.14813842169606 21 -70.93055960682048 72 1 10 24.14813842169606 20 -70.93055960682048 11 24.14813842169606 21 -70.87998129872766 72 1 10 24.14813842169606 20 -70.87998129872766 11 24.14813842169606 21 -70.82940299063483 72 1 10 24.14813842169606 20 -70.82940299063483 11 24.14813842169606 21 -70.77882468254201 72 1 10 24.14813842169606 20 -70.77882468254201 11 24.14813842169606 21 -70.72824637444918 72 1 10 24.14813842169606 20 -70.72824637444918 11 23.91675719616796 21 -70.72824637444918 72 1 10 23.91675719616796 20 -70.72824637444918 11 23.68537597063987 21 -70.72824637444918 72 1 10 23.68537597063987 20 -70.72824637444918 11 23.45399474511178 21 -70.72824637444918 72 1 10 23.45399474511178 20 -70.72824637444918 11 23.22261351958369 21 -70.72824637444918 72 1 10 23.22261351958369 20 -70.72824637444918 11 22.9912322940556 21 -70.72824637444918 72 1 10 22.9912322940556 20 -70.72824637444918 11 22.75985106852751 21 -70.72824637444918 72 1 10 22.75985106852751 20 -70.72824637444918 11 22.52846984299941 21 -70.72824637444918 72 1 10 22.52846984299941 20 -70.72824637444918 11 22.29708861747132 21 -70.72824637444918 72 1 10 22.29708861747132 20 -70.72824637444918 11 22.29708861747132 21 -70.77882468254201 72 1 10 22.29708861747132 20 -70.77882468254201 11 22.29708861747132 21 -70.82940299063483 72 1 10 22.29708861747132 20 -70.82940299063483 11 22.29708861747132 21 -70.87998129872766 72 1 10 22.29708861747132 20 -70.87998129872766 11 22.29708861747132 21 -70.93055960682048 72 1 10 22.29708861747132 20 -70.93055960682048 11 22.29708861747132 21 -70.9811379149133 72 1 10 22.29708861747132 20 -70.9811379149133 11 22.29708861747132 21 -71.03171622300613 72 1 10 22.29708861747132 20 -71.03171622300613 11 22.29708861747132 21 -71.08229453109895 72 1 10 22.29708861747132 20 -71.08229453109895 11 22.29708861747132 21 -71.13287283919178 72 1 10 22.29708861747132 20 -71.13287283919178 11 22.38293609059439 21 -71.13287283919178 72 1 10 22.38293609059439 20 -71.13287283919178 11 22.46878356371746 21 -71.13287283919178 72 1 10 22.46878356371746 20 -71.13287283919178 11 22.55463103684053 21 -71.13287283919178 72 1 10 22.55463103684053 20 -71.13287283919178 11 22.6404785099636 21 -71.13287283919178 72 1 10 22.6404785099636 20 -71.13287283919178 11 22.72632598308667 21 -71.13287283919178 72 1 10 22.72632598308667 20 -71.13287283919178 11 22.81217345620974 21 -71.13287283919178 72 1 10 22.81217345620974 20 -71.13287283919178 11 22.89802092933281 21 -71.13287283919178 72 1 10 22.89802092933281 20 -71.13287283919178 11 22.98386840245588 21 -71.13287283919178 72 1 10 22.98386840245588 20 -71.13287283919178 11 22.98386840245588 21 -71.36793601051973 72 1 10 22.98386840245588 20 -71.36793601051973 11 22.98386840245588 21 -71.60299918184768 72 1 10 22.98386840245588 20 -71.60299918184768 11 22.98386840245588 21 -71.83806235317563 72 1 10 22.98386840245588 20 -71.83806235317563 11 22.98386840245588 21 -72.0731255245036 72 1 10 22.98386840245588 20 -72.0731255245036 11 22.98386840245588 21 -72.30818869583155 72 1 10 22.98386840245588 20 -72.30818869583155 11 22.98386840245588 21 -72.5432518671595 72 1 10 22.98386840245588 20 -72.5432518671595 11 22.98386840245588 21 -72.77831503848745 72 1 10 22.98386840245588 20 -72.77831503848745 11 22.98386840245588 21 -73.0133782098154 72 1 10 22.98386840245588 20 -73.0133782098154 11 23.04394225497992 21 -73.0133782098154 72 1 10 23.04394225497992 20 -73.0133782098154 11 23.10401610750396 21 -73.0133782098154 72 1 10 23.10401610750396 20 -73.0133782098154 11 23.16408996002801 21 -73.0133782098154 72 1 10 23.16408996002801 20 -73.0133782098154 11 23.22416381255205 21 -73.0133782098154 72 1 10 23.22416381255205 20 -73.0133782098154 11 23.28423766507609 21 -73.0133782098154 72 1 10 23.28423766507609 20 -73.0133782098154 11 23.34431151760014 21 -73.0133782098154 72 1 10 23.34431151760014 20 -73.0133782098154 11 23.40438537012419 21 -73.0133782098154 72 1 10 23.40438537012419 20 -73.0133782098154 11 23.46445922264823 21 -73.0133782098154 97 0 75 2 76 1 98 0 0 POLYLINE 5 B87 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 B88 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -73.0133782098154 30 0.0 0 VERTEX 5 B89 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.4477325378321 20 -73.0133782098154 30 0.0 0 VERTEX 5 B8A 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.50703124387196 20 -73.0133782098154 30 0.0 0 VERTEX 5 B8B 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.56632994991182 20 -73.0133782098154 30 0.0 0 VERTEX 5 B8C 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.62562865595169 20 -73.0133782098154 30 0.0 0 VERTEX 5 B8D 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.68492736199155 20 -73.0133782098154 30 0.0 0 VERTEX 5 B8E 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.74422606803141 20 -73.0133782098154 30 0.0 0 VERTEX 5 B8F 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.80352477407127 20 -73.0133782098154 30 0.0 0 VERTEX 5 B90 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -73.0133782098154 30 0.0 0 VERTEX 5 B91 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -72.72773673039462 30 0.0 0 VERTEX 5 B92 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -72.44209525097385 30 0.0 0 VERTEX 5 B93 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -72.15645377155307 30 0.0 0 VERTEX 5 B94 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -71.8708122921323 30 0.0 0 VERTEX 5 B95 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -71.58517081271151 30 0.0 0 VERTEX 5 B96 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -71.29952933329074 30 0.0 0 VERTEX 5 B97 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -71.01388785386996 30 0.0 0 VERTEX 5 B98 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86282348011114 20 -70.72824637444918 30 0.0 0 VERTEX 5 B99 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.80352477407127 20 -70.72824637444918 30 0.0 0 VERTEX 5 B9A 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.74422606803141 20 -70.72824637444918 30 0.0 0 VERTEX 5 B9B 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.68492736199155 20 -70.72824637444918 30 0.0 0 VERTEX 5 B9C 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.62562865595169 20 -70.72824637444918 30 0.0 0 VERTEX 5 B9D 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.56632994991182 20 -70.72824637444918 30 0.0 0 VERTEX 5 B9E 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.50703124387196 20 -70.72824637444918 30 0.0 0 VERTEX 5 B9F 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.4477325378321 20 -70.72824637444918 30 0.0 0 VERTEX 5 BA0 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -70.72824637444918 30 0.0 0 VERTEX 5 BA1 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -71.01388785386996 30 0.0 0 VERTEX 5 BA2 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -71.29952933329074 30 0.0 0 VERTEX 5 BA3 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -71.58517081271151 30 0.0 0 VERTEX 5 BA4 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -71.8708122921323 30 0.0 0 VERTEX 5 BA5 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -72.15645377155307 30 0.0 0 VERTEX 5 BA6 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -72.44209525097385 30 0.0 0 VERTEX 5 BA7 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -72.72773673039462 30 0.0 0 VERTEX 5 BA8 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -73.0133782098154 30 0.0 0 VERTEX 5 BA9 330 B87 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38843383179223 20 -73.0133782098154 30 0.0 0 SEQEND 5 BAB 330 B87 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 BAA 330 9E4 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 32 72 1 10 24.38843383179223 20 -73.0133782098154 11 24.4477325378321 21 -73.0133782098154 72 1 10 24.4477325378321 20 -73.0133782098154 11 24.50703124387196 21 -73.0133782098154 72 1 10 24.50703124387196 20 -73.0133782098154 11 24.56632994991182 21 -73.0133782098154 72 1 10 24.56632994991182 20 -73.0133782098154 11 24.62562865595169 21 -73.0133782098154 72 1 10 24.62562865595169 20 -73.0133782098154 11 24.68492736199155 21 -73.0133782098154 72 1 10 24.68492736199155 20 -73.0133782098154 11 24.74422606803141 21 -73.0133782098154 72 1 10 24.74422606803141 20 -73.0133782098154 11 24.80352477407127 21 -73.0133782098154 72 1 10 24.80352477407127 20 -73.0133782098154 11 24.86282348011114 21 -73.0133782098154 72 1 10 24.86282348011114 20 -73.0133782098154 11 24.86282348011114 21 -72.72773673039462 72 1 10 24.86282348011114 20 -72.72773673039462 11 24.86282348011114 21 -72.44209525097385 72 1 10 24.86282348011114 20 -72.44209525097385 11 24.86282348011114 21 -72.15645377155307 72 1 10 24.86282348011114 20 -72.15645377155307 11 24.86282348011114 21 -71.8708122921323 72 1 10 24.86282348011114 20 -71.8708122921323 11 24.86282348011114 21 -71.58517081271151 72 1 10 24.86282348011114 20 -71.58517081271151 11 24.86282348011114 21 -71.29952933329074 72 1 10 24.86282348011114 20 -71.29952933329074 11 24.86282348011114 21 -71.01388785386996 72 1 10 24.86282348011114 20 -71.01388785386996 11 24.86282348011114 21 -70.72824637444918 72 1 10 24.86282348011114 20 -70.72824637444918 11 24.80352477407127 21 -70.72824637444918 72 1 10 24.80352477407127 20 -70.72824637444918 11 24.74422606803141 21 -70.72824637444918 72 1 10 24.74422606803141 20 -70.72824637444918 11 24.68492736199155 21 -70.72824637444918 72 1 10 24.68492736199155 20 -70.72824637444918 11 24.62562865595169 21 -70.72824637444918 72 1 10 24.62562865595169 20 -70.72824637444918 11 24.56632994991182 21 -70.72824637444918 72 1 10 24.56632994991182 20 -70.72824637444918 11 24.50703124387196 21 -70.72824637444918 72 1 10 24.50703124387196 20 -70.72824637444918 11 24.4477325378321 21 -70.72824637444918 72 1 10 24.4477325378321 20 -70.72824637444918 11 24.38843383179223 21 -70.72824637444918 72 1 10 24.38843383179223 20 -70.72824637444918 11 24.38843383179223 21 -71.01388785386996 72 1 10 24.38843383179223 20 -71.01388785386996 11 24.38843383179223 21 -71.29952933329074 72 1 10 24.38843383179223 20 -71.29952933329074 11 24.38843383179223 21 -71.58517081271151 72 1 10 24.38843383179223 20 -71.58517081271151 11 24.38843383179223 21 -71.8708122921323 72 1 10 24.38843383179223 20 -71.8708122921323 11 24.38843383179223 21 -72.15645377155307 72 1 10 24.38843383179223 20 -72.15645377155307 11 24.38843383179223 21 -72.44209525097385 72 1 10 24.38843383179223 20 -72.44209525097385 11 24.38843383179223 21 -72.72773673039462 72 1 10 24.38843383179223 20 -72.72773673039462 11 24.38843383179223 21 -73.0133782098154 97 0 75 2 76 1 98 0 0 POLYLINE 5 BAC 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 BAD 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.32009887037182 20 -70.65848319087287 30 0.0 0 VERTEX 5 BAE 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.20123500168815 20 -70.66264960322535 30 0.0 0 VERTEX 5 BAF 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.08958968463843 20 -70.67514884028277 30 0.0 0 VERTEX 5 BB0 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.98516291922264 20 -70.69598090204514 30 0.0 0 VERTEX 5 BB1 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88795470544079 20 -70.72514578851246 30 0.0 0 VERTEX 5 BB2 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.79796504329288 20 -70.76264349968473 30 0.0 0 VERTEX 5 BB3 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.7151939327789 20 -70.80847403556194 30 0.0 0 VERTEX 5 BB4 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.63964137389886 20 -70.86263739614411 30 0.0 0 VERTEX 5 BB5 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.57130736665276 20 -70.92513358143121 30 0.0 0 VERTEX 5 BB6 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.48991698581374 20 -71.008704061757 30 0.0 0 VERTEX 5 BB7 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.41937865575325 20 -71.10206076644558 30 0.0 0 VERTEX 5 BB8 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.35969237647129 20 -71.20520369549693 30 0.0 0 VERTEX 5 BB9 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.31085814796788 20 -71.31813284891109 30 0.0 0 VERTEX 5 BBA 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.272875970243 20 -71.44084822668803 30 0.0 0 VERTEX 5 BBB 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.24574584329666 20 -71.57334982882776 30 0.0 0 VERTEX 5 BBC 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.22946776712885 20 -71.71563765533027 30 0.0 0 VERTEX 5 BBD 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.22404174173958 20 -71.86771170619556 30 0.0 0 VERTEX 5 BBE 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.22946776712885 20 -72.01707274436623 30 0.0 0 VERTEX 5 BBF 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.24574584329666 20 -72.1574227046583 30 0.0 0 VERTEX 5 BC0 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.272875970243 20 -72.28876158707175 30 0.0 0 VERTEX 5 BC1 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.31085814796788 20 -72.4110893916066 30 0.0 0 VERTEX 5 BC2 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.35969237647129 20 -72.52440611826285 30 0.0 0 VERTEX 5 BC3 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.41937865575325 20 -72.62871176704047 30 0.0 0 VERTEX 5 BC4 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.48991698581374 20 -72.7240063379395 30 0.0 0 VERTEX 5 BC5 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.57130736665276 20 -72.81028983095992 30 0.0 0 VERTEX 5 BC6 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.63964137389886 20 -72.87278601624703 30 0.0 0 VERTEX 5 BC7 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.7151939327789 20 -72.9269493768292 30 0.0 0 VERTEX 5 BC8 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.79796504329288 20 -72.97277991270641 30 0.0 0 VERTEX 5 BC9 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.88795470544079 20 -73.01027762387868 30 0.0 0 VERTEX 5 BCA 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.98516291922264 20 -73.03944251034599 30 0.0 0 VERTEX 5 BCB 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.08958968463843 20 -73.06027457210837 30 0.0 0 VERTEX 5 BCC 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.20123500168815 20 -73.07277380916578 30 0.0 0 VERTEX 5 BCD 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.32009887037182 20 -73.07694022151826 30 0.0 0 VERTEX 5 BCE 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.43896273905548 20 -73.07277380916578 30 0.0 0 VERTEX 5 BCF 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.55060805610521 20 -73.06027457210837 30 0.0 0 VERTEX 5 BD0 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.655034821521 20 -73.03944251034599 30 0.0 0 VERTEX 5 BD1 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.75224303530284 20 -73.01027762387868 30 0.0 0 VERTEX 5 BD2 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.84223269745076 20 -72.97277991270641 30 0.0 0 VERTEX 5 BD3 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.92500380796473 20 -72.9269493768292 30 0.0 0 VERTEX 5 BD4 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.00055636684477 20 -72.87278601624703 30 0.0 0 VERTEX 5 BD5 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.06889037409087 20 -72.81028983095992 30 0.0 0 VERTEX 5 BD6 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.14991740501544 20 -72.7240063379395 30 0.0 0 VERTEX 5 BD7 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.22014083181673 20 -72.62871176704047 30 0.0 0 VERTEX 5 BD8 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.27956065449474 20 -72.52440611826285 30 0.0 0 VERTEX 5 BD9 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.32817687304949 20 -72.4110893916066 30 0.0 0 VERTEX 5 BDA 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.36598948748095 20 -72.28876158707175 30 0.0 0 VERTEX 5 BDB 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.39299849778914 20 -72.1574227046583 30 0.0 0 VERTEX 5 BDC 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.40920390397405 20 -72.01707274436623 30 0.0 0 VERTEX 5 BDD 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.41460570603569 20 -71.86771170619556 30 0.0 0 VERTEX 5 BDE 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.40920390397405 20 -71.71563765533027 30 0.0 0 VERTEX 5 BDF 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.39299849778914 20 -71.57334982882776 30 0.0 0 VERTEX 5 BE0 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.36598948748095 20 -71.44084822668803 30 0.0 0 VERTEX 5 BE1 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.32817687304949 20 -71.31813284891109 30 0.0 0 VERTEX 5 BE2 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.27956065449474 20 -71.20520369549693 30 0.0 0 VERTEX 5 BE3 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.22014083181673 20 -71.10206076644558 30 0.0 0 VERTEX 5 BE4 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.14991740501544 20 -71.008704061757 30 0.0 0 VERTEX 5 BE5 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.06889037409087 20 -70.92513358143121 30 0.0 0 VERTEX 5 BE6 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.00055636684477 20 -70.86263739614411 30 0.0 0 VERTEX 5 BE7 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.92500380796473 20 -70.80847403556194 30 0.0 0 VERTEX 5 BE8 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.84223269745076 20 -70.76264349968473 30 0.0 0 VERTEX 5 BE9 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.75224303530284 20 -70.72514578851246 30 0.0 0 VERTEX 5 BEA 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.655034821521 20 -70.69598090204514 30 0.0 0 VERTEX 5 BEB 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.55060805610521 20 -70.67514884028277 30 0.0 0 VERTEX 5 BEC 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.43896273905548 20 -70.66264960322535 30 0.0 0 VERTEX 5 BED 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.32009887037182 20 -70.65848319087287 30 0.0 0 VERTEX 5 BEE 330 BAC 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.32009887037182 20 -70.65848319087287 30 0.0 0 SEQEND 5 BEF 330 BAC 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 BF0 330 9E4 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 BF1 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.77037285029397 20 -72.46302420604674 30 0.0 0 VERTEX 5 BF2 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.72688356631928 20 -72.51207644449883 30 0.0 0 VERTEX 5 BF3 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.67974261570427 20 -72.55458838449064 30 0.0 0 VERTEX 5 BF4 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.6289479798383 20 -72.59056002602217 30 0.0 0 VERTEX 5 BF5 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.57449764011074 20 -72.61999136909344 30 0.0 0 VERTEX 5 BF6 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.51638957791094 20 -72.64288241370441 30 0.0 0 VERTEX 5 BF7 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.45462177462828 20 -72.6592331598551 30 0.0 0 VERTEX 5 BF8 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.38919221165212 20 -72.66904360754553 30 0.0 0 VERTEX 5 BF9 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.32009887037182 20 -72.67231375677567 30 0.0 0 VERTEX 5 BFA 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.25096549331391 20 -72.66904360754553 30 0.0 0 VERTEX 5 BFB 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.18541716874533 20 -72.6592331598551 30 0.0 0 VERTEX 5 BFC 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.1234538966661 20 -72.64288241370441 30 0.0 0 VERTEX 5 BFD 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.0650756770762 20 -72.61999136909344 30 0.0 0 VERTEX 5 BFE 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.01028250997564 20 -72.59056002602217 30 0.0 0 VERTEX 5 BFF 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.95907439536442 20 -72.55458838449064 30 0.0 0 VERTEX 5 C00 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.91145133324254 20 -72.51207644449883 30 0.0 0 VERTEX 5 C01 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.86741332360999 20 -72.46302420604674 30 0.0 0 VERTEX 5 C02 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.82780818293385 20 -72.40794035901462 30 0.0 0 VERTEX 5 C03 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.79348372768121 20 -72.3473335932827 30 0.0 0 VERTEX 5 C04 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.76443995785204 20 -72.28120390885098 30 0.0 0 VERTEX 5 C05 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.74067687344636 20 -72.20955130571949 30 0.0 0 VERTEX 5 C06 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72219447446416 20 -72.1323757838882 30 0.0 0 VERTEX 5 C07 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.70899276090545 20 -72.0496773433571 30 0.0 0 VERTEX 5 C08 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.70107173277023 20 -71.96145598412623 30 0.0 0 VERTEX 5 C09 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.69843139005848 20 -71.86771170619556 30 0.0 0 VERTEX 5 C0A 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.70107173277023 20 -71.7739674282649 30 0.0 0 VERTEX 5 C0B 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.70899276090545 20 -71.68574606903402 30 0.0 0 VERTEX 5 C0C 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.72219447446416 20 -71.60304762850295 30 0.0 0 VERTEX 5 C0D 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.74067687344636 20 -71.52587210667166 30 0.0 0 VERTEX 5 C0E 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.76443995785204 20 -71.45421950354016 30 0.0 0 VERTEX 5 C0F 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.79348372768121 20 -71.38808981910844 30 0.0 0 VERTEX 5 C10 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.82780818293385 20 -71.32748305337653 30 0.0 0 VERTEX 5 C11 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.86741332360999 20 -71.2723992063444 30 0.0 0 VERTEX 5 C12 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.91145133324254 20 -71.2233469678923 30 0.0 0 VERTEX 5 C13 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.95907439536442 20 -71.18083502790049 30 0.0 0 VERTEX 5 C14 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.01028250997564 20 -71.14486338636895 30 0.0 0 VERTEX 5 C15 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.0650756770762 20 -71.1154320432977 30 0.0 0 VERTEX 5 C16 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.1234538966661 20 -71.09254099868673 30 0.0 0 VERTEX 5 C17 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.18541716874533 20 -71.07619025253602 30 0.0 0 VERTEX 5 C18 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.25096549331391 20 -71.06637980484561 30 0.0 0 VERTEX 5 C19 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.32009887037182 20 -71.06310965561546 30 0.0 0 VERTEX 5 C1A 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.38919221165212 20 -71.06639561729558 30 0.0 0 VERTEX 5 C1B 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.45462177462828 20 -71.07625215659553 30 0.0 0 VERTEX 5 C1C 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.51638957791094 20 -71.09267725490464 30 0.0 0 VERTEX 5 C1D 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.57449764011074 20 -71.11566889361231 30 0.0 0 VERTEX 5 C1E 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.6289479798383 20 -71.14522505410788 30 0.0 0 VERTEX 5 C1F 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.67974261570427 20 -71.18134371778073 30 0.0 0 VERTEX 5 C20 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.72688356631928 20 -71.22402286602022 30 0.0 0 VERTEX 5 C21 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.77037285029397 20 -71.27326048021571 30 0.0 0 VERTEX 5 C22 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.80943666688458 20 -71.32849807809127 30 0.0 0 VERTEX 5 C23 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.8432985238665 20 -71.38917986885183 30 0.0 0 VERTEX 5 C24 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.87195640262911 20 -71.455307871108 30 0.0 0 VERTEX 5 C25 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.89540828456176 20 -71.52688410347045 30 0.0 0 VERTEX 5 C26 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.91365215105381 20 -71.6039105845498 30 0.0 0 VERTEX 5 C27 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.92668598349464 20 -71.68638933295667 30 0.0 0 VERTEX 5 C28 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.9345077632736 20 -71.7743223673017 30 0.0 0 VERTEX 5 C29 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.93711547178006 20 -71.86771170619556 30 0.0 0 VERTEX 5 C2A 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.9345077632736 20 -71.96145598412623 30 0.0 0 VERTEX 5 C2B 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.92668598349464 20 -72.0496773433571 30 0.0 0 VERTEX 5 C2C 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.91365215105381 20 -72.1323757838882 30 0.0 0 VERTEX 5 C2D 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.89540828456176 20 -72.20955130571949 30 0.0 0 VERTEX 5 C2E 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.87195640262911 20 -72.28120390885098 30 0.0 0 VERTEX 5 C2F 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.8432985238665 20 -72.3473335932827 30 0.0 0 VERTEX 5 C30 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.80943666688458 20 -72.40794035901462 30 0.0 0 VERTEX 5 C31 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.77037285029397 20 -72.46302420604674 30 0.0 0 VERTEX 5 C32 330 BF0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.77037285029397 20 -72.46302420604674 30 0.0 0 SEQEND 5 C33 330 BF0 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 C34 330 9E4 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 64 72 1 10 26.32009887037182 20 -70.65848319087287 11 26.20123500168815 21 -70.66264960322535 72 1 10 26.20123500168815 20 -70.66264960322535 11 26.08958968463843 21 -70.67514884028277 72 1 10 26.08958968463843 20 -70.67514884028277 11 25.98516291922264 21 -70.69598090204514 72 1 10 25.98516291922264 20 -70.69598090204514 11 25.88795470544079 21 -70.72514578851246 72 1 10 25.88795470544079 20 -70.72514578851246 11 25.79796504329288 21 -70.76264349968473 72 1 10 25.79796504329288 20 -70.76264349968473 11 25.7151939327789 21 -70.80847403556194 72 1 10 25.7151939327789 20 -70.80847403556194 11 25.63964137389886 21 -70.86263739614411 72 1 10 25.63964137389886 20 -70.86263739614411 11 25.57130736665276 21 -70.92513358143121 72 1 10 25.57130736665276 20 -70.92513358143121 11 25.48991698581374 21 -71.008704061757 72 1 10 25.48991698581374 20 -71.008704061757 11 25.41937865575325 21 -71.10206076644558 72 1 10 25.41937865575325 20 -71.10206076644558 11 25.35969237647129 21 -71.20520369549693 72 1 10 25.35969237647129 20 -71.20520369549693 11 25.31085814796788 21 -71.31813284891109 72 1 10 25.31085814796788 20 -71.31813284891109 11 25.272875970243 21 -71.44084822668803 72 1 10 25.272875970243 20 -71.44084822668803 11 25.24574584329666 21 -71.57334982882776 72 1 10 25.24574584329666 20 -71.57334982882776 11 25.22946776712885 21 -71.71563765533027 72 1 10 25.22946776712885 20 -71.71563765533027 11 25.22404174173958 21 -71.86771170619556 72 1 10 25.22404174173958 20 -71.86771170619556 11 25.22946776712885 21 -72.01707274436623 72 1 10 25.22946776712885 20 -72.01707274436623 11 25.24574584329666 21 -72.1574227046583 72 1 10 25.24574584329666 20 -72.1574227046583 11 25.272875970243 21 -72.28876158707175 72 1 10 25.272875970243 20 -72.28876158707175 11 25.31085814796788 21 -72.4110893916066 72 1 10 25.31085814796788 20 -72.4110893916066 11 25.35969237647129 21 -72.52440611826285 72 1 10 25.35969237647129 20 -72.52440611826285 11 25.41937865575325 21 -72.62871176704047 72 1 10 25.41937865575325 20 -72.62871176704047 11 25.48991698581374 21 -72.7240063379395 72 1 10 25.48991698581374 20 -72.7240063379395 11 25.57130736665276 21 -72.81028983095992 72 1 10 25.57130736665276 20 -72.81028983095992 11 25.63964137389886 21 -72.87278601624703 72 1 10 25.63964137389886 20 -72.87278601624703 11 25.7151939327789 21 -72.9269493768292 72 1 10 25.7151939327789 20 -72.9269493768292 11 25.79796504329288 21 -72.97277991270641 72 1 10 25.79796504329288 20 -72.97277991270641 11 25.88795470544079 21 -73.01027762387868 72 1 10 25.88795470544079 20 -73.01027762387868 11 25.98516291922264 21 -73.03944251034599 72 1 10 25.98516291922264 20 -73.03944251034599 11 26.08958968463843 21 -73.06027457210837 72 1 10 26.08958968463843 20 -73.06027457210837 11 26.20123500168815 21 -73.07277380916578 72 1 10 26.20123500168815 20 -73.07277380916578 11 26.32009887037182 21 -73.07694022151826 72 1 10 26.32009887037182 20 -73.07694022151826 11 26.43896273905548 21 -73.07277380916578 72 1 10 26.43896273905548 20 -73.07277380916578 11 26.55060805610521 21 -73.06027457210837 72 1 10 26.55060805610521 20 -73.06027457210837 11 26.655034821521 21 -73.03944251034599 72 1 10 26.655034821521 20 -73.03944251034599 11 26.75224303530284 21 -73.01027762387868 72 1 10 26.75224303530284 20 -73.01027762387868 11 26.84223269745076 21 -72.97277991270641 72 1 10 26.84223269745076 20 -72.97277991270641 11 26.92500380796473 21 -72.9269493768292 72 1 10 26.92500380796473 20 -72.9269493768292 11 27.00055636684477 21 -72.87278601624703 72 1 10 27.00055636684477 20 -72.87278601624703 11 27.06889037409087 21 -72.81028983095992 72 1 10 27.06889037409087 20 -72.81028983095992 11 27.14991740501544 21 -72.7240063379395 72 1 10 27.14991740501544 20 -72.7240063379395 11 27.22014083181673 21 -72.62871176704047 72 1 10 27.22014083181673 20 -72.62871176704047 11 27.27956065449474 21 -72.52440611826285 72 1 10 27.27956065449474 20 -72.52440611826285 11 27.32817687304949 21 -72.4110893916066 72 1 10 27.32817687304949 20 -72.4110893916066 11 27.36598948748095 21 -72.28876158707175 72 1 10 27.36598948748095 20 -72.28876158707175 11 27.39299849778914 21 -72.1574227046583 72 1 10 27.39299849778914 20 -72.1574227046583 11 27.40920390397405 21 -72.01707274436623 72 1 10 27.40920390397405 20 -72.01707274436623 11 27.41460570603569 21 -71.86771170619556 72 1 10 27.41460570603569 20 -71.86771170619556 11 27.40920390397405 21 -71.71563765533027 72 1 10 27.40920390397405 20 -71.71563765533027 11 27.39299849778914 21 -71.57334982882776 72 1 10 27.39299849778914 20 -71.57334982882776 11 27.36598948748095 21 -71.44084822668803 72 1 10 27.36598948748095 20 -71.44084822668803 11 27.32817687304949 21 -71.31813284891109 72 1 10 27.32817687304949 20 -71.31813284891109 11 27.27956065449474 21 -71.20520369549693 72 1 10 27.27956065449474 20 -71.20520369549693 11 27.22014083181673 21 -71.10206076644558 72 1 10 27.22014083181673 20 -71.10206076644558 11 27.14991740501544 21 -71.008704061757 72 1 10 27.14991740501544 20 -71.008704061757 11 27.06889037409087 21 -70.92513358143121 72 1 10 27.06889037409087 20 -70.92513358143121 11 27.00055636684477 21 -70.86263739614411 72 1 10 27.00055636684477 20 -70.86263739614411 11 26.92500380796473 21 -70.80847403556194 72 1 10 26.92500380796473 20 -70.80847403556194 11 26.84223269745076 21 -70.76264349968473 72 1 10 26.84223269745076 20 -70.76264349968473 11 26.75224303530284 21 -70.72514578851246 72 1 10 26.75224303530284 20 -70.72514578851246 11 26.655034821521 21 -70.69598090204514 72 1 10 26.655034821521 20 -70.69598090204514 11 26.55060805610521 21 -70.67514884028277 72 1 10 26.55060805610521 20 -70.67514884028277 11 26.43896273905548 21 -70.66264960322535 72 1 10 26.43896273905548 20 -70.66264960322535 11 26.32009887037182 21 -70.65848319087287 97 0 92 1 93 64 72 1 10 26.77037285029397 20 -72.46302420604674 11 26.72688356631928 21 -72.51207644449883 72 1 10 26.72688356631928 20 -72.51207644449883 11 26.67974261570427 21 -72.55458838449064 72 1 10 26.67974261570427 20 -72.55458838449064 11 26.6289479798383 21 -72.59056002602217 72 1 10 26.6289479798383 20 -72.59056002602217 11 26.57449764011074 21 -72.61999136909344 72 1 10 26.57449764011074 20 -72.61999136909344 11 26.51638957791094 21 -72.64288241370441 72 1 10 26.51638957791094 20 -72.64288241370441 11 26.45462177462828 21 -72.6592331598551 72 1 10 26.45462177462828 20 -72.6592331598551 11 26.38919221165212 21 -72.66904360754553 72 1 10 26.38919221165212 20 -72.66904360754553 11 26.32009887037182 21 -72.67231375677567 72 1 10 26.32009887037182 20 -72.67231375677567 11 26.25096549331391 21 -72.66904360754553 72 1 10 26.25096549331391 20 -72.66904360754553 11 26.18541716874533 21 -72.6592331598551 72 1 10 26.18541716874533 20 -72.6592331598551 11 26.1234538966661 21 -72.64288241370441 72 1 10 26.1234538966661 20 -72.64288241370441 11 26.0650756770762 21 -72.61999136909344 72 1 10 26.0650756770762 20 -72.61999136909344 11 26.01028250997564 21 -72.59056002602217 72 1 10 26.01028250997564 20 -72.59056002602217 11 25.95907439536442 21 -72.55458838449064 72 1 10 25.95907439536442 20 -72.55458838449064 11 25.91145133324254 21 -72.51207644449883 72 1 10 25.91145133324254 20 -72.51207644449883 11 25.86741332360999 21 -72.46302420604674 72 1 10 25.86741332360999 20 -72.46302420604674 11 25.82780818293385 21 -72.40794035901462 72 1 10 25.82780818293385 20 -72.40794035901462 11 25.79348372768121 21 -72.3473335932827 72 1 10 25.79348372768121 20 -72.3473335932827 11 25.76443995785204 21 -72.28120390885098 72 1 10 25.76443995785204 20 -72.28120390885098 11 25.74067687344636 21 -72.20955130571949 72 1 10 25.74067687344636 20 -72.20955130571949 11 25.72219447446416 21 -72.1323757838882 72 1 10 25.72219447446416 20 -72.1323757838882 11 25.70899276090545 21 -72.0496773433571 72 1 10 25.70899276090545 20 -72.0496773433571 11 25.70107173277023 21 -71.96145598412623 72 1 10 25.70107173277023 20 -71.96145598412623 11 25.69843139005848 21 -71.86771170619556 72 1 10 25.69843139005848 20 -71.86771170619556 11 25.70107173277023 21 -71.7739674282649 72 1 10 25.70107173277023 20 -71.7739674282649 11 25.70899276090545 21 -71.68574606903402 72 1 10 25.70899276090545 20 -71.68574606903402 11 25.72219447446416 21 -71.60304762850295 72 1 10 25.72219447446416 20 -71.60304762850295 11 25.74067687344636 21 -71.52587210667166 72 1 10 25.74067687344636 20 -71.52587210667166 11 25.76443995785204 21 -71.45421950354016 72 1 10 25.76443995785204 20 -71.45421950354016 11 25.79348372768121 21 -71.38808981910844 72 1 10 25.79348372768121 20 -71.38808981910844 11 25.82780818293385 21 -71.32748305337653 72 1 10 25.82780818293385 20 -71.32748305337653 11 25.86741332360999 21 -71.2723992063444 72 1 10 25.86741332360999 20 -71.2723992063444 11 25.91145133324254 21 -71.2233469678923 72 1 10 25.91145133324254 20 -71.2233469678923 11 25.95907439536442 21 -71.18083502790049 72 1 10 25.95907439536442 20 -71.18083502790049 11 26.01028250997564 21 -71.14486338636895 72 1 10 26.01028250997564 20 -71.14486338636895 11 26.0650756770762 21 -71.1154320432977 72 1 10 26.0650756770762 20 -71.1154320432977 11 26.1234538966661 21 -71.09254099868673 72 1 10 26.1234538966661 20 -71.09254099868673 11 26.18541716874533 21 -71.07619025253602 72 1 10 26.18541716874533 20 -71.07619025253602 11 26.25096549331391 21 -71.06637980484561 72 1 10 26.25096549331391 20 -71.06637980484561 11 26.32009887037182 21 -71.06310965561546 72 1 10 26.32009887037182 20 -71.06310965561546 11 26.38919221165212 21 -71.06639561729558 72 1 10 26.38919221165212 20 -71.06639561729558 11 26.45462177462828 21 -71.07625215659553 72 1 10 26.45462177462828 20 -71.07625215659553 11 26.51638957791094 21 -71.09267725490464 72 1 10 26.51638957791094 20 -71.09267725490464 11 26.57449764011074 21 -71.11566889361231 72 1 10 26.57449764011074 20 -71.11566889361231 11 26.6289479798383 21 -71.14522505410788 72 1 10 26.6289479798383 20 -71.14522505410788 11 26.67974261570427 21 -71.18134371778073 72 1 10 26.67974261570427 20 -71.18134371778073 11 26.72688356631928 21 -71.22402286602022 72 1 10 26.72688356631928 20 -71.22402286602022 11 26.77037285029397 21 -71.27326048021571 72 1 10 26.77037285029397 20 -71.27326048021571 11 26.80943666688458 21 -71.32849807809127 72 1 10 26.80943666688458 20 -71.32849807809127 11 26.8432985238665 21 -71.38917986885183 72 1 10 26.8432985238665 20 -71.38917986885183 11 26.87195640262911 21 -71.455307871108 72 1 10 26.87195640262911 20 -71.455307871108 11 26.89540828456176 21 -71.52688410347045 72 1 10 26.89540828456176 20 -71.52688410347045 11 26.91365215105381 21 -71.6039105845498 72 1 10 26.91365215105381 20 -71.6039105845498 11 26.92668598349464 21 -71.68638933295667 72 1 10 26.92668598349464 20 -71.68638933295667 11 26.9345077632736 21 -71.7743223673017 72 1 10 26.9345077632736 20 -71.7743223673017 11 26.93711547178006 21 -71.86771170619556 72 1 10 26.93711547178006 20 -71.86771170619556 11 26.9345077632736 21 -71.96145598412623 72 1 10 26.9345077632736 20 -71.96145598412623 11 26.92668598349464 21 -72.0496773433571 72 1 10 26.92668598349464 20 -72.0496773433571 11 26.91365215105381 21 -72.1323757838882 72 1 10 26.91365215105381 20 -72.1323757838882 11 26.89540828456176 21 -72.20955130571949 72 1 10 26.89540828456176 20 -72.20955130571949 11 26.87195640262911 21 -72.28120390885098 72 1 10 26.87195640262911 20 -72.28120390885098 11 26.8432985238665 21 -72.3473335932827 72 1 10 26.8432985238665 20 -72.3473335932827 11 26.80943666688458 21 -72.40794035901462 72 1 10 26.80943666688458 20 -72.40794035901462 11 26.77037285029397 21 -72.46302420604674 97 0 75 2 76 1 98 0 0 ENDBLK 5 9E7 330 9E4 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 C5C 330 C5A 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 block 5 70 0 10 0.0 20 0.0 30 0.0 3 block 5 1 0 POLYLINE 5 C5E 330 C5A 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 C5F 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -27.2932295529855 30 0.0 0 VERTEX 5 C60 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.03998751544011 20 -27.2932295529855 30 0.0 0 VERTEX 5 C61 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.09657320878534 20 -27.2932295529855 30 0.0 0 VERTEX 5 C62 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.15315890213057 20 -27.2932295529855 30 0.0 0 VERTEX 5 C63 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.2097445954758 20 -27.2932295529855 30 0.0 0 VERTEX 5 C64 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.26633028882102 20 -27.2932295529855 30 0.0 0 VERTEX 5 C65 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.32291598216625 20 -27.2932295529855 30 0.0 0 VERTEX 5 C66 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.37950167551148 20 -27.2932295529855 30 0.0 0 VERTEX 5 C67 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -27.2932295529855 30 0.0 0 VERTEX 5 C68 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -27.01223895246981 30 0.0 0 VERTEX 5 C69 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -26.73124835195412 30 0.0 0 VERTEX 5 C6A 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -26.45025775143843 30 0.0 0 VERTEX 5 C6B 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -26.16926715092274 30 0.0 0 VERTEX 5 C6C 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -25.88827655040705 30 0.0 0 VERTEX 5 C6D 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -25.60728594989136 30 0.0 0 VERTEX 5 C6E 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -25.32629534937567 30 0.0 0 VERTEX 5 C6F 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.43608736885671 20 -25.04530474885998 30 0.0 0 VERTEX 5 C70 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.38996615304793 20 -25.04530474885998 30 0.0 0 VERTEX 5 C71 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.34384493723914 20 -25.04530474885998 30 0.0 0 VERTEX 5 C72 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.29772372143036 20 -25.04530474885998 30 0.0 0 VERTEX 5 C73 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.25160250562158 20 -25.04530474885998 30 0.0 0 VERTEX 5 C74 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.2054812898128 20 -25.04530474885998 30 0.0 0 VERTEX 5 C75 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.15936007400402 20 -25.04530474885998 30 0.0 0 VERTEX 5 C76 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.11323885819523 20 -25.04530474885998 30 0.0 0 VERTEX 5 C77 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.06711764238645 20 -25.04530474885998 30 0.0 0 VERTEX 5 C78 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.06685118578251 20 -25.05315310701231 30 0.0 0 VERTEX 5 C79 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.0660518159707 20 -25.06197039826987 30 0.0 0 VERTEX 5 C7A 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.06471953295102 20 -25.07175662263266 30 0.0 0 VERTEX 5 C7B 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.06285433672345 20 -25.08251178010068 30 0.0 0 VERTEX 5 C7C 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.06045622728802 20 -25.09423587067392 30 0.0 0 VERTEX 5 C7D 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05752520464471 20 -25.10692889435239 30 0.0 0 VERTEX 5 C7E 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05406126879353 20 -25.12059085113608 30 0.0 0 VERTEX 5 C7F 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05006441973446 20 -25.135221741025 30 0.0 0 VERTEX 5 C80 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.04232170220541 20 -25.15978419524249 30 0.0 0 VERTEX 5 C81 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.03369483321783 20 -25.18308703642319 30 0.0 0 VERTEX 5 C82 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.02418784999301 20 -25.20513026456709 30 0.0 0 VERTEX 5 C83 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.01380478975221 20 -25.2259138796742 30 0.0 0 VERTEX 5 C84 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.00254968971671 20 -25.24543788174451 30 0.0 0 VERTEX 5 C85 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.99042658710777 20 -25.26370227077803 30 0.0 0 VERTEX 5 C86 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.97743951914668 20 -25.28070704677476 30 0.0 0 VERTEX 5 C87 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.96359252305469 20 -25.29645220973469 30 0.0 0 VERTEX 5 C88 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.94189649594016 20 -25.31762339808389 30 0.0 0 VERTEX 5 C89 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.91866632474236 20 -25.33695361353316 30 0.0 0 VERTEX 5 C8A 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.89390200946128 20 -25.3544428560825 30 0.0 0 VERTEX 5 C8B 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86760355009692 20 -25.37009112573191 30 0.0 0 VERTEX 5 C8C 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.83977094664929 20 -25.38389842248138 30 0.0 0 VERTEX 5 C8D 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.81040419911838 20 -25.39586474633093 30 0.0 0 VERTEX 5 C8E 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.7795033075042 20 -25.40599009728055 30 0.0 0 VERTEX 5 C8F 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.74706827180674 20 -25.41427447533023 30 0.0 0 VERTEX 5 C90 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.72419270321064 20 -25.41878001426954 30 0.0 0 VERTEX 5 C91 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69742121608727 20 -25.42299487327728 30 0.0 0 VERTEX 5 C92 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.66674977321537 20 -25.42691905235344 30 0.0 0 VERTEX 5 C93 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.63217433737366 20 -25.43055255149804 30 0.0 0 VERTEX 5 C94 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.59369087134087 20 -25.43389537071107 30 0.0 0 VERTEX 5 C95 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.55129533789572 20 -25.43694750999254 30 0.0 0 VERTEX 5 C96 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.50498369981696 20 -25.43970896934243 30 0.0 0 VERTEX 5 C97 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.44217974876076 30 0.0 0 VERTEX 5 C98 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.47977435324355 30 0.0 0 VERTEX 5 C99 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.51736895772634 30 0.0 0 VERTEX 5 C9A 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.55496356220912 30 0.0 0 VERTEX 5 C9B 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.59255816669192 30 0.0 0 VERTEX 5 C9C 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.6301527711747 30 0.0 0 VERTEX 5 C9D 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.66774737565749 30 0.0 0 VERTEX 5 C9E 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.70534198014028 30 0.0 0 VERTEX 5 C9F 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.45475191988329 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA0 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.52083315765974 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA1 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.58691439543619 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA2 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.65299563321264 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA3 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.71907687098909 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA4 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.78515810876554 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA5 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.85123934654198 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA6 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.91732058431843 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA7 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -25.74293658462307 30 0.0 0 VERTEX 5 CA8 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -25.93672320566837 30 0.0 0 VERTEX 5 CA9 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -26.13050982671368 30 0.0 0 VERTEX 5 CAA 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -26.32429644775898 30 0.0 0 VERTEX 5 CAB 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -26.51808306880428 30 0.0 0 VERTEX 5 CAC 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -26.71186968984959 30 0.0 0 VERTEX 5 CAD 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -26.90565631089489 30 0.0 0 VERTEX 5 CAE 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -27.09944293194019 30 0.0 0 VERTEX 5 CAF 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -27.2932295529855 30 0.0 0 VERTEX 5 CB0 330 C5E 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98340182209488 20 -27.2932295529855 30 0.0 0 SEQEND 5 CB2 330 C5E 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 CB1 330 C5A 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 80 72 1 10 24.98340182209488 20 -27.2932295529855 11 25.03998751544011 21 -27.2932295529855 72 1 10 25.03998751544011 20 -27.2932295529855 11 25.09657320878534 21 -27.2932295529855 72 1 10 25.09657320878534 20 -27.2932295529855 11 25.15315890213057 21 -27.2932295529855 72 1 10 25.15315890213057 20 -27.2932295529855 11 25.2097445954758 21 -27.2932295529855 72 1 10 25.2097445954758 20 -27.2932295529855 11 25.26633028882102 21 -27.2932295529855 72 1 10 25.26633028882102 20 -27.2932295529855 11 25.32291598216625 21 -27.2932295529855 72 1 10 25.32291598216625 20 -27.2932295529855 11 25.37950167551148 21 -27.2932295529855 72 1 10 25.37950167551148 20 -27.2932295529855 11 25.43608736885671 21 -27.2932295529855 72 1 10 25.43608736885671 20 -27.2932295529855 11 25.43608736885671 21 -27.01223895246981 72 1 10 25.43608736885671 20 -27.01223895246981 11 25.43608736885671 21 -26.73124835195412 72 1 10 25.43608736885671 20 -26.73124835195412 11 25.43608736885671 21 -26.45025775143843 72 1 10 25.43608736885671 20 -26.45025775143843 11 25.43608736885671 21 -26.16926715092274 72 1 10 25.43608736885671 20 -26.16926715092274 11 25.43608736885671 21 -25.88827655040705 72 1 10 25.43608736885671 20 -25.88827655040705 11 25.43608736885671 21 -25.60728594989136 72 1 10 25.43608736885671 20 -25.60728594989136 11 25.43608736885671 21 -25.32629534937567 72 1 10 25.43608736885671 20 -25.32629534937567 11 25.43608736885671 21 -25.04530474885998 72 1 10 25.43608736885671 20 -25.04530474885998 11 25.38996615304793 21 -25.04530474885998 72 1 10 25.38996615304793 20 -25.04530474885998 11 25.34384493723914 21 -25.04530474885998 72 1 10 25.34384493723914 20 -25.04530474885998 11 25.29772372143036 21 -25.04530474885998 72 1 10 25.29772372143036 20 -25.04530474885998 11 25.25160250562158 21 -25.04530474885998 72 1 10 25.25160250562158 20 -25.04530474885998 11 25.2054812898128 21 -25.04530474885998 72 1 10 25.2054812898128 20 -25.04530474885998 11 25.15936007400402 21 -25.04530474885998 72 1 10 25.15936007400402 20 -25.04530474885998 11 25.11323885819523 21 -25.04530474885998 72 1 10 25.11323885819523 20 -25.04530474885998 11 25.06711764238645 21 -25.04530474885998 72 1 10 25.06711764238645 20 -25.04530474885998 11 25.06685118578251 21 -25.05315310701231 72 1 10 25.06685118578251 20 -25.05315310701231 11 25.0660518159707 21 -25.06197039826987 72 1 10 25.0660518159707 20 -25.06197039826987 11 25.06471953295102 21 -25.07175662263266 72 1 10 25.06471953295102 20 -25.07175662263266 11 25.06285433672345 21 -25.08251178010068 72 1 10 25.06285433672345 20 -25.08251178010068 11 25.06045622728802 21 -25.09423587067392 72 1 10 25.06045622728802 20 -25.09423587067392 11 25.05752520464471 21 -25.10692889435239 72 1 10 25.05752520464471 20 -25.10692889435239 11 25.05406126879353 21 -25.12059085113608 72 1 10 25.05406126879353 20 -25.12059085113608 11 25.05006441973446 21 -25.135221741025 72 1 10 25.05006441973446 20 -25.135221741025 11 25.04232170220541 21 -25.15978419524249 72 1 10 25.04232170220541 20 -25.15978419524249 11 25.03369483321783 21 -25.18308703642319 72 1 10 25.03369483321783 20 -25.18308703642319 11 25.02418784999301 21 -25.20513026456709 72 1 10 25.02418784999301 20 -25.20513026456709 11 25.01380478975221 21 -25.2259138796742 72 1 10 25.01380478975221 20 -25.2259138796742 11 25.00254968971671 21 -25.24543788174451 72 1 10 25.00254968971671 20 -25.24543788174451 11 24.99042658710777 21 -25.26370227077803 72 1 10 24.99042658710777 20 -25.26370227077803 11 24.97743951914668 21 -25.28070704677476 72 1 10 24.97743951914668 20 -25.28070704677476 11 24.96359252305469 21 -25.29645220973469 72 1 10 24.96359252305469 20 -25.29645220973469 11 24.94189649594016 21 -25.31762339808389 72 1 10 24.94189649594016 20 -25.31762339808389 11 24.91866632474236 21 -25.33695361353316 72 1 10 24.91866632474236 20 -25.33695361353316 11 24.89390200946128 21 -25.3544428560825 72 1 10 24.89390200946128 20 -25.3544428560825 11 24.86760355009692 21 -25.37009112573191 72 1 10 24.86760355009692 20 -25.37009112573191 11 24.83977094664929 21 -25.38389842248138 72 1 10 24.83977094664929 20 -25.38389842248138 11 24.81040419911838 21 -25.39586474633093 72 1 10 24.81040419911838 20 -25.39586474633093 11 24.7795033075042 21 -25.40599009728055 72 1 10 24.7795033075042 20 -25.40599009728055 11 24.74706827180674 21 -25.41427447533023 72 1 10 24.74706827180674 20 -25.41427447533023 11 24.72419270321064 21 -25.41878001426954 72 1 10 24.72419270321064 20 -25.41878001426954 11 24.69742121608727 21 -25.42299487327728 72 1 10 24.69742121608727 20 -25.42299487327728 11 24.66674977321537 21 -25.42691905235344 72 1 10 24.66674977321537 20 -25.42691905235344 11 24.63217433737366 21 -25.43055255149804 72 1 10 24.63217433737366 20 -25.43055255149804 11 24.59369087134087 21 -25.43389537071107 72 1 10 24.59369087134087 20 -25.43389537071107 11 24.55129533789572 21 -25.43694750999254 72 1 10 24.55129533789572 20 -25.43694750999254 11 24.50498369981696 21 -25.43970896934243 72 1 10 24.50498369981696 20 -25.43970896934243 11 24.45475191988329 21 -25.44217974876076 72 1 10 24.45475191988329 20 -25.44217974876076 11 24.45475191988329 21 -25.47977435324355 72 1 10 24.45475191988329 20 -25.47977435324355 11 24.45475191988329 21 -25.51736895772634 72 1 10 24.45475191988329 20 -25.51736895772634 11 24.45475191988329 21 -25.55496356220912 72 1 10 24.45475191988329 20 -25.55496356220912 11 24.45475191988329 21 -25.59255816669192 72 1 10 24.45475191988329 20 -25.59255816669192 11 24.45475191988329 21 -25.6301527711747 72 1 10 24.45475191988329 20 -25.6301527711747 11 24.45475191988329 21 -25.66774737565749 72 1 10 24.45475191988329 20 -25.66774737565749 11 24.45475191988329 21 -25.70534198014028 72 1 10 24.45475191988329 20 -25.70534198014028 11 24.45475191988329 21 -25.74293658462307 72 1 10 24.45475191988329 20 -25.74293658462307 11 24.52083315765974 21 -25.74293658462307 72 1 10 24.52083315765974 20 -25.74293658462307 11 24.58691439543619 21 -25.74293658462307 72 1 10 24.58691439543619 20 -25.74293658462307 11 24.65299563321264 21 -25.74293658462307 72 1 10 24.65299563321264 20 -25.74293658462307 11 24.71907687098909 21 -25.74293658462307 72 1 10 24.71907687098909 20 -25.74293658462307 11 24.78515810876554 21 -25.74293658462307 72 1 10 24.78515810876554 20 -25.74293658462307 11 24.85123934654198 21 -25.74293658462307 72 1 10 24.85123934654198 20 -25.74293658462307 11 24.91732058431843 21 -25.74293658462307 72 1 10 24.91732058431843 20 -25.74293658462307 11 24.98340182209488 21 -25.74293658462307 72 1 10 24.98340182209488 20 -25.74293658462307 11 24.98340182209488 21 -25.93672320566837 72 1 10 24.98340182209488 20 -25.93672320566837 11 24.98340182209488 21 -26.13050982671368 72 1 10 24.98340182209488 20 -26.13050982671368 11 24.98340182209488 21 -26.32429644775898 72 1 10 24.98340182209488 20 -26.32429644775898 11 24.98340182209488 21 -26.51808306880428 72 1 10 24.98340182209488 20 -26.51808306880428 11 24.98340182209488 21 -26.71186968984959 72 1 10 24.98340182209488 20 -26.71186968984959 11 24.98340182209488 21 -26.90565631089489 72 1 10 24.98340182209488 20 -26.90565631089489 11 24.98340182209488 21 -27.09944293194019 72 1 10 24.98340182209488 20 -27.09944293194019 11 24.98340182209488 21 -27.2932295529855 97 0 75 2 76 1 98 0 0 POLYLINE 5 CB3 330 C5A 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 CB4 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89993014342825 20 -27.35679156468836 30 0.0 0 VERTEX 5 CB5 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.01879401211191 20 -27.35262515233588 30 0.0 0 VERTEX 5 CB6 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.13043932916164 20 -27.34012591527846 30 0.0 0 VERTEX 5 CB7 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.23486609457742 20 -27.31929385351609 30 0.0 0 VERTEX 5 CB8 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.33207430835927 20 -27.29012896704877 30 0.0 0 VERTEX 5 CB9 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.42206397050719 20 -27.2526312558765 30 0.0 0 VERTEX 5 CBA 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.50483508102116 20 -27.20680071999929 30 0.0 0 VERTEX 5 CBB 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.5803876399012 20 -27.15263735941713 30 0.0 0 VERTEX 5 CBC 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.6487216471473 20 -27.09014117413002 30 0.0 0 VERTEX 5 CBD 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.72974867807187 20 -27.0038576811096 30 0.0 0 VERTEX 5 CBE 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.79997210487316 20 -26.90856311021057 30 0.0 0 VERTEX 5 CBF 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.85939192755118 20 -26.80425746143294 30 0.0 0 VERTEX 5 CC0 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.90800814610592 20 -26.69094073477669 30 0.0 0 VERTEX 5 CC1 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.94582076053738 20 -26.56861293024184 30 0.0 0 VERTEX 5 CC2 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.97282977084557 20 -26.43727404782839 30 0.0 0 VERTEX 5 CC3 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.98903517703048 20 -26.29692408753633 30 0.0 0 VERTEX 5 CC4 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.99443697909212 20 -26.14756304936566 30 0.0 0 VERTEX 5 CC5 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.98903517703048 20 -25.99548899850036 30 0.0 0 VERTEX 5 CC6 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.97282977084557 20 -25.85320117199785 30 0.0 0 VERTEX 5 CC7 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.94582076053738 20 -25.72069956985812 30 0.0 0 VERTEX 5 CC8 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.90800814610592 20 -25.59798419208118 30 0.0 0 VERTEX 5 CC9 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.85939192755118 20 -25.48505503866703 30 0.0 0 VERTEX 5 CCA 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.79997210487316 20 -25.38191210961567 30 0.0 0 VERTEX 5 CCB 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.72974867807187 20 -25.2885554049271 30 0.0 0 VERTEX 5 CCC 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.6487216471473 20 -25.20498492460131 30 0.0 0 VERTEX 5 CCD 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.5803876399012 20 -25.1424887393142 30 0.0 0 VERTEX 5 CCE 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.50483508102116 20 -25.08832537873203 30 0.0 0 VERTEX 5 CCF 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.42206397050719 20 -25.04249484285482 30 0.0 0 VERTEX 5 CD0 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.33207430835927 20 -25.00499713168255 30 0.0 0 VERTEX 5 CD1 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.23486609457742 20 -24.97583224521524 30 0.0 0 VERTEX 5 CD2 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.13043932916164 20 -24.95500018345287 30 0.0 0 VERTEX 5 CD3 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.01879401211191 20 -24.94250094639544 30 0.0 0 VERTEX 5 CD4 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89993014342825 20 -24.93833453404297 30 0.0 0 VERTEX 5 CD5 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.78106627474459 20 -24.94250094639544 30 0.0 0 VERTEX 5 CD6 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.66942095769486 20 -24.95500018345287 30 0.0 0 VERTEX 5 CD7 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.56499419227907 20 -24.97583224521524 30 0.0 0 VERTEX 5 CD8 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.46778597849722 20 -25.00499713168255 30 0.0 0 VERTEX 5 CD9 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.37779631634931 20 -25.04249484285482 30 0.0 0 VERTEX 5 CDA 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.29502520583533 20 -25.08832537873203 30 0.0 0 VERTEX 5 CDB 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.2194726469553 20 -25.1424887393142 30 0.0 0 VERTEX 5 CDC 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.1511386397092 20 -25.20498492460131 30 0.0 0 VERTEX 5 CDD 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.06974825887017 20 -25.2885554049271 30 0.0 0 VERTEX 5 CDE 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.99920992880968 20 -25.38191210961567 30 0.0 0 VERTEX 5 CDF 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.93952364952773 20 -25.48505503866703 30 0.0 0 VERTEX 5 CE0 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.89068942102431 20 -25.59798419208118 30 0.0 0 VERTEX 5 CE1 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.85270724329943 20 -25.72069956985812 30 0.0 0 VERTEX 5 CE2 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.82557711635309 20 -25.85320117199785 30 0.0 0 VERTEX 5 CE3 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.80929904018528 20 -25.99548899850036 30 0.0 0 VERTEX 5 CE4 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.80387301479601 20 -26.14756304936566 30 0.0 0 VERTEX 5 CE5 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.80929904018528 20 -26.29692408753633 30 0.0 0 VERTEX 5 CE6 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.82557711635309 20 -26.43727404782839 30 0.0 0 VERTEX 5 CE7 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.85270724329943 20 -26.56861293024184 30 0.0 0 VERTEX 5 CE8 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.89068942102431 20 -26.69094073477669 30 0.0 0 VERTEX 5 CE9 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.93952364952773 20 -26.80425746143294 30 0.0 0 VERTEX 5 CEA 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.99920992880968 20 -26.90856311021057 30 0.0 0 VERTEX 5 CEB 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.06974825887017 20 -27.0038576811096 30 0.0 0 VERTEX 5 CEC 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.1511386397092 20 -27.09014117413002 30 0.0 0 VERTEX 5 CED 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.2194726469553 20 -27.15263735941713 30 0.0 0 VERTEX 5 CEE 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.29502520583533 20 -27.20680071999929 30 0.0 0 VERTEX 5 CEF 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.37779631634931 20 -27.2526312558765 30 0.0 0 VERTEX 5 CF0 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.46778597849722 20 -27.29012896704877 30 0.0 0 VERTEX 5 CF1 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.56499419227907 20 -27.31929385351609 30 0.0 0 VERTEX 5 CF2 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.66942095769486 20 -27.34012591527846 30 0.0 0 VERTEX 5 CF3 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.78106627474459 20 -27.35262515233588 30 0.0 0 VERTEX 5 CF4 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89993014342825 20 -27.35679156468836 30 0.0 0 VERTEX 5 CF5 330 CB3 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89993014342825 20 -27.35679156468836 30 0.0 0 SEQEND 5 CF6 330 CB3 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 CF7 330 C5A 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 CF8 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44724459666642 20 -25.55225054951449 30 0.0 0 VERTEX 5 CF9 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.49128260629897 20 -25.5031983110624 30 0.0 0 VERTEX 5 CFA 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.53890566842085 20 -25.46068637107059 30 0.0 0 VERTEX 5 CFB 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.59011378303207 20 -25.42471472953905 30 0.0 0 VERTEX 5 CFC 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.64490695013263 20 -25.3952833864678 30 0.0 0 VERTEX 5 CFD 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.70328516972253 20 -25.37239234185682 30 0.0 0 VERTEX 5 CFE 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.76524844180176 20 -25.35604159570612 30 0.0 0 VERTEX 5 CFF 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.83079676637034 20 -25.3462311480157 30 0.0 0 VERTEX 5 D00 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89993014342825 20 -25.34296099878556 30 0.0 0 VERTEX 5 D01 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.96902348470855 20 -25.34624696046568 30 0.0 0 VERTEX 5 D02 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.03445304768471 20 -25.35610349976562 30 0.0 0 VERTEX 5 D03 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.09622085096737 20 -25.37252859807474 30 0.0 0 VERTEX 5 D04 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.15432891316717 20 -25.39552023678241 30 0.0 0 VERTEX 5 D05 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.20877925289473 20 -25.42507639727798 30 0.0 0 VERTEX 5 D06 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.2595738887607 20 -25.46119506095083 30 0.0 0 VERTEX 5 D07 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.30671483937571 20 -25.50387420919031 30 0.0 0 VERTEX 5 D08 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.3502041233504 20 -25.55311182338581 30 0.0 0 VERTEX 5 D09 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.38926793994101 20 -25.60834942126137 30 0.0 0 VERTEX 5 D0A 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.42312979692294 20 -25.66903121202192 30 0.0 0 VERTEX 5 D0B 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.45178767568554 20 -25.7351592142781 30 0.0 0 VERTEX 5 D0C 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.47523955761819 20 -25.80673544664054 30 0.0 0 VERTEX 5 D0D 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.49348342411025 20 -25.88376192771988 30 0.0 0 VERTEX 5 D0E 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.50651725655107 20 -25.96624067612676 30 0.0 0 VERTEX 5 D0F 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.51433903633003 20 -26.05417371047181 30 0.0 0 VERTEX 5 D10 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.5169467448365 20 -26.14756304936566 30 0.0 0 VERTEX 5 D11 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.51433903633003 20 -26.24130732729633 30 0.0 0 VERTEX 5 D12 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.50651725655107 20 -26.3295286865272 30 0.0 0 VERTEX 5 D13 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.49348342411025 20 -26.41222712705829 30 0.0 0 VERTEX 5 D14 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.47523955761819 20 -26.48940264888958 30 0.0 0 VERTEX 5 D15 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.45178767568554 20 -26.56105525202108 30 0.0 0 VERTEX 5 D16 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.42312979692294 20 -26.62718493645279 30 0.0 0 VERTEX 5 D17 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.38926793994101 20 -26.68779170218471 30 0.0 0 VERTEX 5 D18 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.3502041233504 20 -26.74287554921683 30 0.0 0 VERTEX 5 D19 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.30671483937571 20 -26.79192778766893 30 0.0 0 VERTEX 5 D1A 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.2595738887607 20 -26.83443972766074 30 0.0 0 VERTEX 5 D1B 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.20877925289473 20 -26.87041136919228 30 0.0 0 VERTEX 5 D1C 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.15432891316717 20 -26.89984271226353 30 0.0 0 VERTEX 5 D1D 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.09622085096737 20 -26.92273375687451 30 0.0 0 VERTEX 5 D1E 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.03445304768471 20 -26.9390845030252 30 0.0 0 VERTEX 5 D1F 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.96902348470855 20 -26.94889495071562 30 0.0 0 VERTEX 5 D20 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89993014342825 20 -26.95216509994576 30 0.0 0 VERTEX 5 D21 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.83079676637034 20 -26.94889495071562 30 0.0 0 VERTEX 5 D22 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.76524844180176 20 -26.9390845030252 30 0.0 0 VERTEX 5 D23 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.70328516972253 20 -26.92273375687451 30 0.0 0 VERTEX 5 D24 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.64490695013263 20 -26.89984271226353 30 0.0 0 VERTEX 5 D25 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.59011378303207 20 -26.87041136919228 30 0.0 0 VERTEX 5 D26 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.53890566842085 20 -26.83443972766074 30 0.0 0 VERTEX 5 D27 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.49128260629897 20 -26.79192778766893 30 0.0 0 VERTEX 5 D28 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44724459666642 20 -26.74287554921683 30 0.0 0 VERTEX 5 D29 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.40763945599029 20 -26.68779170218471 30 0.0 0 VERTEX 5 D2A 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.37331500073764 20 -26.62718493645279 30 0.0 0 VERTEX 5 D2B 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.34427123090847 20 -26.56105525202108 30 0.0 0 VERTEX 5 D2C 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.32050814650279 20 -26.48940264888958 30 0.0 0 VERTEX 5 D2D 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.3020257475206 20 -26.41222712705829 30 0.0 0 VERTEX 5 D2E 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.28882403396188 20 -26.3295286865272 30 0.0 0 VERTEX 5 D2F 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.28090300582666 20 -26.24130732729633 30 0.0 0 VERTEX 5 D30 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.27826266311492 20 -26.14756304936566 30 0.0 0 VERTEX 5 D31 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.28090300582666 20 -26.053818771435 30 0.0 0 VERTEX 5 D32 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.28882403396188 20 -25.96559741220412 30 0.0 0 VERTEX 5 D33 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.3020257475206 20 -25.88289897167304 30 0.0 0 VERTEX 5 D34 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.32050814650279 20 -25.80572344984175 30 0.0 0 VERTEX 5 D35 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.34427123090847 20 -25.73407084671025 30 0.0 0 VERTEX 5 D36 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.37331500073764 20 -25.66794116227854 30 0.0 0 VERTEX 5 D37 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.40763945599029 20 -25.60733439654662 30 0.0 0 VERTEX 5 D38 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44724459666642 20 -25.55225054951449 30 0.0 0 VERTEX 5 D39 330 CF7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44724459666642 20 -25.55225054951449 30 0.0 0 SEQEND 5 D3A 330 CF7 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 D3B 330 C5A 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 64 72 1 10 20.89993014342825 20 -27.35679156468836 11 21.01879401211191 21 -27.35262515233588 72 1 10 21.01879401211191 20 -27.35262515233588 11 21.13043932916164 21 -27.34012591527846 72 1 10 21.13043932916164 20 -27.34012591527846 11 21.23486609457742 21 -27.31929385351609 72 1 10 21.23486609457742 20 -27.31929385351609 11 21.33207430835927 21 -27.29012896704877 72 1 10 21.33207430835927 20 -27.29012896704877 11 21.42206397050719 21 -27.2526312558765 72 1 10 21.42206397050719 20 -27.2526312558765 11 21.50483508102116 21 -27.20680071999929 72 1 10 21.50483508102116 20 -27.20680071999929 11 21.5803876399012 21 -27.15263735941713 72 1 10 21.5803876399012 20 -27.15263735941713 11 21.6487216471473 21 -27.09014117413002 72 1 10 21.6487216471473 20 -27.09014117413002 11 21.72974867807187 21 -27.0038576811096 72 1 10 21.72974867807187 20 -27.0038576811096 11 21.79997210487316 21 -26.90856311021057 72 1 10 21.79997210487316 20 -26.90856311021057 11 21.85939192755118 21 -26.80425746143294 72 1 10 21.85939192755118 20 -26.80425746143294 11 21.90800814610592 21 -26.69094073477669 72 1 10 21.90800814610592 20 -26.69094073477669 11 21.94582076053738 21 -26.56861293024184 72 1 10 21.94582076053738 20 -26.56861293024184 11 21.97282977084557 21 -26.43727404782839 72 1 10 21.97282977084557 20 -26.43727404782839 11 21.98903517703048 21 -26.29692408753633 72 1 10 21.98903517703048 20 -26.29692408753633 11 21.99443697909212 21 -26.14756304936566 72 1 10 21.99443697909212 20 -26.14756304936566 11 21.98903517703048 21 -25.99548899850036 72 1 10 21.98903517703048 20 -25.99548899850036 11 21.97282977084557 21 -25.85320117199785 72 1 10 21.97282977084557 20 -25.85320117199785 11 21.94582076053738 21 -25.72069956985812 72 1 10 21.94582076053738 20 -25.72069956985812 11 21.90800814610592 21 -25.59798419208118 72 1 10 21.90800814610592 20 -25.59798419208118 11 21.85939192755118 21 -25.48505503866703 72 1 10 21.85939192755118 20 -25.48505503866703 11 21.79997210487316 21 -25.38191210961567 72 1 10 21.79997210487316 20 -25.38191210961567 11 21.72974867807187 21 -25.2885554049271 72 1 10 21.72974867807187 20 -25.2885554049271 11 21.6487216471473 21 -25.20498492460131 72 1 10 21.6487216471473 20 -25.20498492460131 11 21.5803876399012 21 -25.1424887393142 72 1 10 21.5803876399012 20 -25.1424887393142 11 21.50483508102116 21 -25.08832537873203 72 1 10 21.50483508102116 20 -25.08832537873203 11 21.42206397050719 21 -25.04249484285482 72 1 10 21.42206397050719 20 -25.04249484285482 11 21.33207430835927 21 -25.00499713168255 72 1 10 21.33207430835927 20 -25.00499713168255 11 21.23486609457742 21 -24.97583224521524 72 1 10 21.23486609457742 20 -24.97583224521524 11 21.13043932916164 21 -24.95500018345287 72 1 10 21.13043932916164 20 -24.95500018345287 11 21.01879401211191 21 -24.94250094639544 72 1 10 21.01879401211191 20 -24.94250094639544 11 20.89993014342825 21 -24.93833453404297 72 1 10 20.89993014342825 20 -24.93833453404297 11 20.78106627474459 21 -24.94250094639544 72 1 10 20.78106627474459 20 -24.94250094639544 11 20.66942095769486 21 -24.95500018345287 72 1 10 20.66942095769486 20 -24.95500018345287 11 20.56499419227907 21 -24.97583224521524 72 1 10 20.56499419227907 20 -24.97583224521524 11 20.46778597849722 21 -25.00499713168255 72 1 10 20.46778597849722 20 -25.00499713168255 11 20.37779631634931 21 -25.04249484285482 72 1 10 20.37779631634931 20 -25.04249484285482 11 20.29502520583533 21 -25.08832537873203 72 1 10 20.29502520583533 20 -25.08832537873203 11 20.2194726469553 21 -25.1424887393142 72 1 10 20.2194726469553 20 -25.1424887393142 11 20.1511386397092 21 -25.20498492460131 72 1 10 20.1511386397092 20 -25.20498492460131 11 20.06974825887017 21 -25.2885554049271 72 1 10 20.06974825887017 20 -25.2885554049271 11 19.99920992880968 21 -25.38191210961567 72 1 10 19.99920992880968 20 -25.38191210961567 11 19.93952364952773 21 -25.48505503866703 72 1 10 19.93952364952773 20 -25.48505503866703 11 19.89068942102431 21 -25.59798419208118 72 1 10 19.89068942102431 20 -25.59798419208118 11 19.85270724329943 21 -25.72069956985812 72 1 10 19.85270724329943 20 -25.72069956985812 11 19.82557711635309 21 -25.85320117199785 72 1 10 19.82557711635309 20 -25.85320117199785 11 19.80929904018528 21 -25.99548899850036 72 1 10 19.80929904018528 20 -25.99548899850036 11 19.80387301479601 21 -26.14756304936566 72 1 10 19.80387301479601 20 -26.14756304936566 11 19.80929904018528 21 -26.29692408753633 72 1 10 19.80929904018528 20 -26.29692408753633 11 19.82557711635309 21 -26.43727404782839 72 1 10 19.82557711635309 20 -26.43727404782839 11 19.85270724329943 21 -26.56861293024184 72 1 10 19.85270724329943 20 -26.56861293024184 11 19.89068942102431 21 -26.69094073477669 72 1 10 19.89068942102431 20 -26.69094073477669 11 19.93952364952773 21 -26.80425746143294 72 1 10 19.93952364952773 20 -26.80425746143294 11 19.99920992880968 21 -26.90856311021057 72 1 10 19.99920992880968 20 -26.90856311021057 11 20.06974825887017 21 -27.0038576811096 72 1 10 20.06974825887017 20 -27.0038576811096 11 20.1511386397092 21 -27.09014117413002 72 1 10 20.1511386397092 20 -27.09014117413002 11 20.2194726469553 21 -27.15263735941713 72 1 10 20.2194726469553 20 -27.15263735941713 11 20.29502520583533 21 -27.20680071999929 72 1 10 20.29502520583533 20 -27.20680071999929 11 20.37779631634931 21 -27.2526312558765 72 1 10 20.37779631634931 20 -27.2526312558765 11 20.46778597849722 21 -27.29012896704877 72 1 10 20.46778597849722 20 -27.29012896704877 11 20.56499419227907 21 -27.31929385351609 72 1 10 20.56499419227907 20 -27.31929385351609 11 20.66942095769486 21 -27.34012591527846 72 1 10 20.66942095769486 20 -27.34012591527846 11 20.78106627474459 21 -27.35262515233588 72 1 10 20.78106627474459 20 -27.35262515233588 11 20.89993014342825 21 -27.35679156468836 97 0 92 1 93 64 72 1 10 20.44724459666642 20 -25.55225054951449 11 20.49128260629897 21 -25.5031983110624 72 1 10 20.49128260629897 20 -25.5031983110624 11 20.53890566842085 21 -25.46068637107059 72 1 10 20.53890566842085 20 -25.46068637107059 11 20.59011378303207 21 -25.42471472953905 72 1 10 20.59011378303207 20 -25.42471472953905 11 20.64490695013263 21 -25.3952833864678 72 1 10 20.64490695013263 20 -25.3952833864678 11 20.70328516972253 21 -25.37239234185682 72 1 10 20.70328516972253 20 -25.37239234185682 11 20.76524844180176 21 -25.35604159570612 72 1 10 20.76524844180176 20 -25.35604159570612 11 20.83079676637034 21 -25.3462311480157 72 1 10 20.83079676637034 20 -25.3462311480157 11 20.89993014342825 21 -25.34296099878556 72 1 10 20.89993014342825 20 -25.34296099878556 11 20.96902348470855 21 -25.34624696046568 72 1 10 20.96902348470855 20 -25.34624696046568 11 21.03445304768471 21 -25.35610349976562 72 1 10 21.03445304768471 20 -25.35610349976562 11 21.09622085096737 21 -25.37252859807474 72 1 10 21.09622085096737 20 -25.37252859807474 11 21.15432891316717 21 -25.39552023678241 72 1 10 21.15432891316717 20 -25.39552023678241 11 21.20877925289473 21 -25.42507639727798 72 1 10 21.20877925289473 20 -25.42507639727798 11 21.2595738887607 21 -25.46119506095083 72 1 10 21.2595738887607 20 -25.46119506095083 11 21.30671483937571 21 -25.50387420919031 72 1 10 21.30671483937571 20 -25.50387420919031 11 21.3502041233504 21 -25.55311182338581 72 1 10 21.3502041233504 20 -25.55311182338581 11 21.38926793994101 21 -25.60834942126137 72 1 10 21.38926793994101 20 -25.60834942126137 11 21.42312979692294 21 -25.66903121202192 72 1 10 21.42312979692294 20 -25.66903121202192 11 21.45178767568554 21 -25.7351592142781 72 1 10 21.45178767568554 20 -25.7351592142781 11 21.47523955761819 21 -25.80673544664054 72 1 10 21.47523955761819 20 -25.80673544664054 11 21.49348342411025 21 -25.88376192771988 72 1 10 21.49348342411025 20 -25.88376192771988 11 21.50651725655107 21 -25.96624067612676 72 1 10 21.50651725655107 20 -25.96624067612676 11 21.51433903633003 21 -26.05417371047181 72 1 10 21.51433903633003 20 -26.05417371047181 11 21.5169467448365 21 -26.14756304936566 72 1 10 21.5169467448365 20 -26.14756304936566 11 21.51433903633003 21 -26.24130732729633 72 1 10 21.51433903633003 20 -26.24130732729633 11 21.50651725655107 21 -26.3295286865272 72 1 10 21.50651725655107 20 -26.3295286865272 11 21.49348342411025 21 -26.41222712705829 72 1 10 21.49348342411025 20 -26.41222712705829 11 21.47523955761819 21 -26.48940264888958 72 1 10 21.47523955761819 20 -26.48940264888958 11 21.45178767568554 21 -26.56105525202108 72 1 10 21.45178767568554 20 -26.56105525202108 11 21.42312979692294 21 -26.62718493645279 72 1 10 21.42312979692294 20 -26.62718493645279 11 21.38926793994101 21 -26.68779170218471 72 1 10 21.38926793994101 20 -26.68779170218471 11 21.3502041233504 21 -26.74287554921683 72 1 10 21.3502041233504 20 -26.74287554921683 11 21.30671483937571 21 -26.79192778766893 72 1 10 21.30671483937571 20 -26.79192778766893 11 21.2595738887607 21 -26.83443972766074 72 1 10 21.2595738887607 20 -26.83443972766074 11 21.20877925289473 21 -26.87041136919228 72 1 10 21.20877925289473 20 -26.87041136919228 11 21.15432891316717 21 -26.89984271226353 72 1 10 21.15432891316717 20 -26.89984271226353 11 21.09622085096737 21 -26.92273375687451 72 1 10 21.09622085096737 20 -26.92273375687451 11 21.03445304768471 21 -26.9390845030252 72 1 10 21.03445304768471 20 -26.9390845030252 11 20.96902348470855 21 -26.94889495071562 72 1 10 20.96902348470855 20 -26.94889495071562 11 20.89993014342825 21 -26.95216509994576 72 1 10 20.89993014342825 20 -26.95216509994576 11 20.83079676637034 21 -26.94889495071562 72 1 10 20.83079676637034 20 -26.94889495071562 11 20.76524844180176 21 -26.9390845030252 72 1 10 20.76524844180176 20 -26.9390845030252 11 20.70328516972253 21 -26.92273375687451 72 1 10 20.70328516972253 20 -26.92273375687451 11 20.64490695013263 21 -26.89984271226353 72 1 10 20.64490695013263 20 -26.89984271226353 11 20.59011378303207 21 -26.87041136919228 72 1 10 20.59011378303207 20 -26.87041136919228 11 20.53890566842085 21 -26.83443972766074 72 1 10 20.53890566842085 20 -26.83443972766074 11 20.49128260629897 21 -26.79192778766893 72 1 10 20.49128260629897 20 -26.79192778766893 11 20.44724459666642 21 -26.74287554921683 72 1 10 20.44724459666642 20 -26.74287554921683 11 20.40763945599029 21 -26.68779170218471 72 1 10 20.40763945599029 20 -26.68779170218471 11 20.37331500073764 21 -26.62718493645279 72 1 10 20.37331500073764 20 -26.62718493645279 11 20.34427123090847 21 -26.56105525202108 72 1 10 20.34427123090847 20 -26.56105525202108 11 20.32050814650279 21 -26.48940264888958 72 1 10 20.32050814650279 20 -26.48940264888958 11 20.3020257475206 21 -26.41222712705829 72 1 10 20.3020257475206 20 -26.41222712705829 11 20.28882403396188 21 -26.3295286865272 72 1 10 20.28882403396188 20 -26.3295286865272 11 20.28090300582666 21 -26.24130732729633 72 1 10 20.28090300582666 20 -26.24130732729633 11 20.27826266311492 21 -26.14756304936566 72 1 10 20.27826266311492 20 -26.14756304936566 11 20.28090300582666 21 -26.053818771435 72 1 10 20.28090300582666 20 -26.053818771435 11 20.28882403396188 21 -25.96559741220412 72 1 10 20.28882403396188 20 -25.96559741220412 11 20.3020257475206 21 -25.88289897167304 72 1 10 20.3020257475206 20 -25.88289897167304 11 20.32050814650279 21 -25.80572344984175 72 1 10 20.32050814650279 20 -25.80572344984175 11 20.34427123090847 21 -25.73407084671025 72 1 10 20.34427123090847 20 -25.73407084671025 11 20.37331500073764 21 -25.66794116227854 72 1 10 20.37331500073764 20 -25.66794116227854 11 20.40763945599029 21 -25.60733439654662 72 1 10 20.40763945599029 20 -25.60733439654662 11 20.44724459666642 21 -25.55225054951449 97 0 75 2 76 1 98 0 0 POLYLINE 5 D3C 330 C5A 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 D3D 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.47157427975341 30 0.0 0 VERTEX 5 D3E 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.90346848656886 20 -26.47157427975341 30 0.0 0 VERTEX 5 D3F 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.96293944738298 20 -26.47157427975341 30 0.0 0 VERTEX 5 D40 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02241040819711 20 -26.47157427975341 30 0.0 0 VERTEX 5 D41 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.08188136901123 20 -26.47157427975341 30 0.0 0 VERTEX 5 D42 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.14135232982536 20 -26.47157427975341 30 0.0 0 VERTEX 5 D43 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.20082329063948 20 -26.47157427975341 30 0.0 0 VERTEX 5 D44 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.26029425145361 20 -26.47157427975341 30 0.0 0 VERTEX 5 D45 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.31976521226774 20 -26.47157427975341 30 0.0 0 VERTEX 5 D46 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.41022319208317 20 -26.4689581603693 30 0.0 0 VERTEX 5 D47 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.49530359316461 20 -26.46110980221696 30 0.0 0 VERTEX 5 D48 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.57500641551203 20 -26.44802920529641 30 0.0 0 VERTEX 5 D49 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.64933165912545 20 -26.42971636960763 30 0.0 0 VERTEX 5 D4A 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.71827932400486 20 -26.40617129515062 30 0.0 0 VERTEX 5 D4B 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.78184941015026 20 -26.37739398192539 30 0.0 0 VERTEX 5 D4C 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.84004191756166 20 -26.34338442993194 30 0.0 0 VERTEX 5 D4D 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.89285684623905 20 -26.30414263917027 30 0.0 0 VERTEX 5 D4E 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.93990695937544 20 -26.25857855989699 30 0.0 0 VERTEX 5 D4F 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.98067717482359 20 -26.20560214236873 30 0.0 0 VERTEX 5 D50 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.01516951119412 20 -26.14521338658549 30 0.0 0 VERTEX 5 D51 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.04338598709768 20 -26.07741229254726 30 0.0 0 VERTEX 5 D52 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.0653286211449 20 -26.00219886025405 30 0.0 0 VERTEX 5 D53 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.0809994319464 20 -25.91957308970586 30 0.0 0 VERTEX 5 D54 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.09040043811284 20 -25.82953498090269 30 0.0 0 VERTEX 5 D55 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.09353365825485 20 -25.73208453384453 30 0.0 0 VERTEX 5 D56 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.09038428922776 20 -25.64248244493871 30 0.0 0 VERTEX 5 D57 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.08093483640605 20 -25.55893618794055 30 0.0 0 VERTEX 5 D58 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.06518328117911 20 -25.48144576285006 30 0.0 0 VERTEX 5 D59 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.04312760493629 20 -25.41001116966724 30 0.0 0 VERTEX 5 D5A 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.01476578906695 20 -25.34463240839208 30 0.0 0 VERTEX 5 D5B 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.98009581496045 20 -25.28530947902459 30 0.0 0 VERTEX 5 D5C 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.93911566400617 20 -25.23204238156476 30 0.0 0 VERTEX 5 D5D 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.89182331759347 20 -25.1848311160126 30 0.0 0 VERTEX 5 D5E 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.83922639886476 20 -25.14340922576416 30 0.0 0 VERTEX 5 D5F 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.78233387670288 20 -25.10751025421552 30 0.0 0 VERTEX 5 D60 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.72114575110782 20 -25.07713420136667 30 0.0 0 VERTEX 5 D61 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.65566202207959 20 -25.05228106721761 30 0.0 0 VERTEX 5 D62 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.5858826896182 20 -25.03295085176834 30 0.0 0 VERTEX 5 D63 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.51180775372363 20 -25.01914355501886 30 0.0 0 VERTEX 5 D64 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.43343721439589 20 -25.01085917696917 30 0.0 0 VERTEX 5 D65 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.35077107163498 20 -25.00809771761928 30 0.0 0 VERTEX 5 D66 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.22812567236009 20 -25.00809771761928 30 0.0 0 VERTEX 5 D67 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.1054802730852 20 -25.00809771761928 30 0.0 0 VERTEX 5 D68 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9828348738103 20 -25.00809771761928 30 0.0 0 VERTEX 5 D69 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.86018947453541 20 -25.00809771761928 30 0.0 0 VERTEX 5 D6A 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.73754407526051 20 -25.00809771761928 30 0.0 0 VERTEX 5 D6B 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.61489867598562 20 -25.00809771761928 30 0.0 0 VERTEX 5 D6C 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.49225327671072 20 -25.00809771761928 30 0.0 0 VERTEX 5 D6D 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -25.00809771761928 30 0.0 0 VERTEX 5 D6E 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -25.29373919704006 30 0.0 0 VERTEX 5 D6F 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -25.57938067646083 30 0.0 0 VERTEX 5 D70 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -25.86502215588161 30 0.0 0 VERTEX 5 D71 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -26.15066363530239 30 0.0 0 VERTEX 5 D72 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -26.43630511472317 30 0.0 0 VERTEX 5 D73 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -26.72194659414394 30 0.0 0 VERTEX 5 D74 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -27.00758807356472 30 0.0 0 VERTEX 5 D75 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.36960787743583 20 -27.2932295529855 30 0.0 0 VERTEX 5 D76 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.42890658347569 20 -27.2932295529855 30 0.0 0 VERTEX 5 D77 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48820528951556 20 -27.2932295529855 30 0.0 0 VERTEX 5 D78 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.54750399555542 20 -27.2932295529855 30 0.0 0 VERTEX 5 D79 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.60680270159528 20 -27.2932295529855 30 0.0 0 VERTEX 5 D7A 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.66610140763514 20 -27.2932295529855 30 0.0 0 VERTEX 5 D7B 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.72540011367501 20 -27.2932295529855 30 0.0 0 VERTEX 5 D7C 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.78469881971487 20 -27.2932295529855 30 0.0 0 VERTEX 5 D7D 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -27.2932295529855 30 0.0 0 VERTEX 5 D7E 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -27.19052264383149 30 0.0 0 VERTEX 5 D7F 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -27.08781573467747 30 0.0 0 VERTEX 5 D80 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.98510882552347 30 0.0 0 VERTEX 5 D81 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.88240191636945 30 0.0 0 VERTEX 5 D82 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.77969500721544 30 0.0 0 VERTEX 5 D83 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.67698809806143 30 0.0 0 VERTEX 5 D84 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.57428118890742 30 0.0 0 VERTEX 5 D85 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.47157427975341 30 0.0 0 VERTEX 5 D86 330 D3C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.47157427975341 30 0.0 0 SEQEND 5 D87 330 D3C 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 D88 330 C5A 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 D89 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.40497271752006 30 0.0 0 VERTEX 5 D8A 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.89778407901819 20 -25.40497271752006 30 0.0 0 VERTEX 5 D8B 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.95157063228166 20 -25.40497271752006 30 0.0 0 VERTEX 5 D8C 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.00535718554512 20 -25.40497271752006 30 0.0 0 VERTEX 5 D8D 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.05914373880858 20 -25.40497271752006 30 0.0 0 VERTEX 5 D8E 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.11293029207205 20 -25.40497271752006 30 0.0 0 VERTEX 5 D8F 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.16671684533551 20 -25.40497271752006 30 0.0 0 VERTEX 5 D90 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.22050339859898 20 -25.40497271752006 30 0.0 0 VERTEX 5 D91 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.27428995186244 20 -25.40497271752006 30 0.0 0 VERTEX 5 D92 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.31403303093202 20 -25.40615966057396 30 0.0 0 VERTEX 5 D93 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.35148700554051 20 -25.40972048973567 30 0.0 0 VERTEX 5 D94 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.38665591290917 20 -25.41565520500518 30 0.0 0 VERTEX 5 D95 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.41954379025928 20 -25.4239638063825 30 0.0 0 VERTEX 5 D96 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.45015467481211 20 -25.43464629386762 30 0.0 0 VERTEX 5 D97 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.47849260378893 20 -25.44770266746055 30 0.0 0 VERTEX 5 D98 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.504561614411 20 -25.46313292716128 30 0.0 0 VERTEX 5 D99 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.52836574389961 20 -25.48093707296982 30 0.0 0 VERTEX 5 D9A 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.54962541468169 20 -25.50152690145588 30 0.0 0 VERTEX 5 D9B 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.56805701196288 20 -25.52531420918919 30 0.0 0 VERTEX 5 D9C 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.58365851713256 20 -25.55229899616975 30 0.0 0 VERTEX 5 D9D 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59642791158008 20 -25.58248126239756 30 0.0 0 VERTEX 5 D9E 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.60636317669482 20 -25.61586100787261 30 0.0 0 VERTEX 5 D9F 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.61346229386613 20 -25.65243823259491 30 0.0 0 VERTEX 5 DA0 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.61772324448339 20 -25.69221293656446 30 0.0 0 VERTEX 5 DA1 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.61914400993594 20 -25.73518511978126 30 0.0 0 VERTEX 5 DA2 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.61772324448339 20 -25.77825419630858 30 0.0 0 VERTEX 5 DA3 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.61346229386613 20 -25.81831958020969 30 0.0 0 VERTEX 5 DA4 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.60636317669482 20 -25.85538127148461 30 0.0 0 VERTEX 5 DA5 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59642791158008 20 -25.88943927013332 30 0.0 0 VERTEX 5 DA6 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.58365851713256 20 -25.92049357615583 30 0.0 0 VERTEX 5 DA7 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.56805701196288 20 -25.94854418955214 30 0.0 0 VERTEX 5 DA8 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.54962541468169 20 -25.97359111032224 30 0.0 0 VERTEX 5 DA9 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.52836574389961 20 -25.99563433846615 30 0.0 0 VERTEX 5 DAA 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.504561614411 20 -26.01489188393252 30 0.0 0 VERTEX 5 DAB 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.47849260378893 20 -26.03158175667005 30 0.0 0 VERTEX 5 DAC 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.45015467481211 20 -26.04570395667873 30 0.0 0 VERTEX 5 DAD 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.41954379025928 20 -26.05725848395855 30 0.0 0 VERTEX 5 DAE 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.38665591290917 20 -26.06624533850953 30 0.0 0 VERTEX 5 DAF 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.35148700554051 20 -26.07266452033165 30 0.0 0 VERTEX 5 DB0 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.31403303093202 20 -26.07651602942493 30 0.0 0 VERTEX 5 DB1 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.27428995186244 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB2 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.22050339859898 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB3 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.16671684533551 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB4 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.11293029207205 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB5 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.05914373880858 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB6 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.00535718554512 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB7 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.95157063228166 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB8 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.89778407901819 20 -26.07779986578936 30 0.0 0 VERTEX 5 DB9 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -26.07779986578936 30 0.0 0 VERTEX 5 DBA 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.99369647225569 30 0.0 0 VERTEX 5 DBB 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.90959307872203 30 0.0 0 VERTEX 5 DBC 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.82548968518837 30 0.0 0 VERTEX 5 DBD 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.74138629165471 30 0.0 0 VERTEX 5 DBE 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.65728289812105 30 0.0 0 VERTEX 5 DBF 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.57317950458738 30 0.0 0 VERTEX 5 DC0 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.48907611105372 30 0.0 0 VERTEX 5 DC1 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.40497271752006 30 0.0 0 VERTEX 5 DC2 330 D88 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.84399752575473 20 -25.40497271752006 30 0.0 0 SEQEND 5 DC3 330 D88 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 DC4 330 C5A 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 72 72 1 10 22.84399752575473 20 -26.47157427975341 11 22.90346848656886 21 -26.47157427975341 72 1 10 22.90346848656886 20 -26.47157427975341 11 22.96293944738298 21 -26.47157427975341 72 1 10 22.96293944738298 20 -26.47157427975341 11 23.02241040819711 21 -26.47157427975341 72 1 10 23.02241040819711 20 -26.47157427975341 11 23.08188136901123 21 -26.47157427975341 72 1 10 23.08188136901123 20 -26.47157427975341 11 23.14135232982536 21 -26.47157427975341 72 1 10 23.14135232982536 20 -26.47157427975341 11 23.20082329063948 21 -26.47157427975341 72 1 10 23.20082329063948 20 -26.47157427975341 11 23.26029425145361 21 -26.47157427975341 72 1 10 23.26029425145361 20 -26.47157427975341 11 23.31976521226774 21 -26.47157427975341 72 1 10 23.31976521226774 20 -26.47157427975341 11 23.41022319208317 21 -26.4689581603693 72 1 10 23.41022319208317 20 -26.4689581603693 11 23.49530359316461 21 -26.46110980221696 72 1 10 23.49530359316461 20 -26.46110980221696 11 23.57500641551203 21 -26.44802920529641 72 1 10 23.57500641551203 20 -26.44802920529641 11 23.64933165912545 21 -26.42971636960763 72 1 10 23.64933165912545 20 -26.42971636960763 11 23.71827932400486 21 -26.40617129515062 72 1 10 23.71827932400486 20 -26.40617129515062 11 23.78184941015026 21 -26.37739398192539 72 1 10 23.78184941015026 20 -26.37739398192539 11 23.84004191756166 21 -26.34338442993194 72 1 10 23.84004191756166 20 -26.34338442993194 11 23.89285684623905 21 -26.30414263917027 72 1 10 23.89285684623905 20 -26.30414263917027 11 23.93990695937544 21 -26.25857855989699 72 1 10 23.93990695937544 20 -26.25857855989699 11 23.98067717482359 21 -26.20560214236873 72 1 10 23.98067717482359 20 -26.20560214236873 11 24.01516951119412 21 -26.14521338658549 72 1 10 24.01516951119412 20 -26.14521338658549 11 24.04338598709768 21 -26.07741229254726 72 1 10 24.04338598709768 20 -26.07741229254726 11 24.0653286211449 21 -26.00219886025405 72 1 10 24.0653286211449 20 -26.00219886025405 11 24.0809994319464 21 -25.91957308970586 72 1 10 24.0809994319464 20 -25.91957308970586 11 24.09040043811284 21 -25.82953498090269 72 1 10 24.09040043811284 20 -25.82953498090269 11 24.09353365825485 21 -25.73208453384453 72 1 10 24.09353365825485 20 -25.73208453384453 11 24.09038428922776 21 -25.64248244493871 72 1 10 24.09038428922776 20 -25.64248244493871 11 24.08093483640605 21 -25.55893618794055 72 1 10 24.08093483640605 20 -25.55893618794055 11 24.06518328117911 21 -25.48144576285006 72 1 10 24.06518328117911 20 -25.48144576285006 11 24.04312760493629 21 -25.41001116966724 72 1 10 24.04312760493629 20 -25.41001116966724 11 24.01476578906695 21 -25.34463240839208 72 1 10 24.01476578906695 20 -25.34463240839208 11 23.98009581496045 21 -25.28530947902459 72 1 10 23.98009581496045 20 -25.28530947902459 11 23.93911566400617 21 -25.23204238156476 72 1 10 23.93911566400617 20 -25.23204238156476 11 23.89182331759347 21 -25.1848311160126 72 1 10 23.89182331759347 20 -25.1848311160126 11 23.83922639886476 21 -25.14340922576416 72 1 10 23.83922639886476 20 -25.14340922576416 11 23.78233387670288 21 -25.10751025421552 72 1 10 23.78233387670288 20 -25.10751025421552 11 23.72114575110782 21 -25.07713420136667 72 1 10 23.72114575110782 20 -25.07713420136667 11 23.65566202207959 21 -25.05228106721761 72 1 10 23.65566202207959 20 -25.05228106721761 11 23.5858826896182 21 -25.03295085176834 72 1 10 23.5858826896182 20 -25.03295085176834 11 23.51180775372363 21 -25.01914355501886 72 1 10 23.51180775372363 20 -25.01914355501886 11 23.43343721439589 21 -25.01085917696917 72 1 10 23.43343721439589 20 -25.01085917696917 11 23.35077107163498 21 -25.00809771761928 72 1 10 23.35077107163498 20 -25.00809771761928 11 23.22812567236009 21 -25.00809771761928 72 1 10 23.22812567236009 20 -25.00809771761928 11 23.1054802730852 21 -25.00809771761928 72 1 10 23.1054802730852 20 -25.00809771761928 11 22.9828348738103 21 -25.00809771761928 72 1 10 22.9828348738103 20 -25.00809771761928 11 22.86018947453541 21 -25.00809771761928 72 1 10 22.86018947453541 20 -25.00809771761928 11 22.73754407526051 21 -25.00809771761928 72 1 10 22.73754407526051 20 -25.00809771761928 11 22.61489867598562 21 -25.00809771761928 72 1 10 22.61489867598562 20 -25.00809771761928 11 22.49225327671072 21 -25.00809771761928 72 1 10 22.49225327671072 20 -25.00809771761928 11 22.36960787743583 21 -25.00809771761928 72 1 10 22.36960787743583 20 -25.00809771761928 11 22.36960787743583 21 -25.29373919704006 72 1 10 22.36960787743583 20 -25.29373919704006 11 22.36960787743583 21 -25.57938067646083 72 1 10 22.36960787743583 20 -25.57938067646083 11 22.36960787743583 21 -25.86502215588161 72 1 10 22.36960787743583 20 -25.86502215588161 11 22.36960787743583 21 -26.15066363530239 72 1 10 22.36960787743583 20 -26.15066363530239 11 22.36960787743583 21 -26.43630511472317 72 1 10 22.36960787743583 20 -26.43630511472317 11 22.36960787743583 21 -26.72194659414394 72 1 10 22.36960787743583 20 -26.72194659414394 11 22.36960787743583 21 -27.00758807356472 72 1 10 22.36960787743583 20 -27.00758807356472 11 22.36960787743583 21 -27.2932295529855 72 1 10 22.36960787743583 20 -27.2932295529855 11 22.42890658347569 21 -27.2932295529855 72 1 10 22.42890658347569 20 -27.2932295529855 11 22.48820528951556 21 -27.2932295529855 72 1 10 22.48820528951556 20 -27.2932295529855 11 22.54750399555542 21 -27.2932295529855 72 1 10 22.54750399555542 20 -27.2932295529855 11 22.60680270159528 21 -27.2932295529855 72 1 10 22.60680270159528 20 -27.2932295529855 11 22.66610140763514 21 -27.2932295529855 72 1 10 22.66610140763514 20 -27.2932295529855 11 22.72540011367501 21 -27.2932295529855 72 1 10 22.72540011367501 20 -27.2932295529855 11 22.78469881971487 21 -27.2932295529855 72 1 10 22.78469881971487 20 -27.2932295529855 11 22.84399752575473 21 -27.2932295529855 72 1 10 22.84399752575473 20 -27.2932295529855 11 22.84399752575473 21 -27.19052264383149 72 1 10 22.84399752575473 20 -27.19052264383149 11 22.84399752575473 21 -27.08781573467747 72 1 10 22.84399752575473 20 -27.08781573467747 11 22.84399752575473 21 -26.98510882552347 72 1 10 22.84399752575473 20 -26.98510882552347 11 22.84399752575473 21 -26.88240191636945 72 1 10 22.84399752575473 20 -26.88240191636945 11 22.84399752575473 21 -26.77969500721544 72 1 10 22.84399752575473 20 -26.77969500721544 11 22.84399752575473 21 -26.67698809806143 72 1 10 22.84399752575473 20 -26.67698809806143 11 22.84399752575473 21 -26.57428118890742 72 1 10 22.84399752575473 20 -26.57428118890742 11 22.84399752575473 21 -26.47157427975341 97 0 92 1 93 56 72 1 10 22.84399752575473 20 -25.40497271752006 11 22.89778407901819 21 -25.40497271752006 72 1 10 22.89778407901819 20 -25.40497271752006 11 22.95157063228166 21 -25.40497271752006 72 1 10 22.95157063228166 20 -25.40497271752006 11 23.00535718554512 21 -25.40497271752006 72 1 10 23.00535718554512 20 -25.40497271752006 11 23.05914373880858 21 -25.40497271752006 72 1 10 23.05914373880858 20 -25.40497271752006 11 23.11293029207205 21 -25.40497271752006 72 1 10 23.11293029207205 20 -25.40497271752006 11 23.16671684533551 21 -25.40497271752006 72 1 10 23.16671684533551 20 -25.40497271752006 11 23.22050339859898 21 -25.40497271752006 72 1 10 23.22050339859898 20 -25.40497271752006 11 23.27428995186244 21 -25.40497271752006 72 1 10 23.27428995186244 20 -25.40497271752006 11 23.31403303093202 21 -25.40615966057396 72 1 10 23.31403303093202 20 -25.40615966057396 11 23.35148700554051 21 -25.40972048973567 72 1 10 23.35148700554051 20 -25.40972048973567 11 23.38665591290917 21 -25.41565520500518 72 1 10 23.38665591290917 20 -25.41565520500518 11 23.41954379025928 21 -25.4239638063825 72 1 10 23.41954379025928 20 -25.4239638063825 11 23.45015467481211 21 -25.43464629386762 72 1 10 23.45015467481211 20 -25.43464629386762 11 23.47849260378893 21 -25.44770266746055 72 1 10 23.47849260378893 20 -25.44770266746055 11 23.504561614411 21 -25.46313292716128 72 1 10 23.504561614411 20 -25.46313292716128 11 23.52836574389961 21 -25.48093707296982 72 1 10 23.52836574389961 20 -25.48093707296982 11 23.54962541468169 21 -25.50152690145588 72 1 10 23.54962541468169 20 -25.50152690145588 11 23.56805701196288 21 -25.52531420918919 72 1 10 23.56805701196288 20 -25.52531420918919 11 23.58365851713256 21 -25.55229899616975 72 1 10 23.58365851713256 20 -25.55229899616975 11 23.59642791158008 21 -25.58248126239756 72 1 10 23.59642791158008 20 -25.58248126239756 11 23.60636317669482 21 -25.61586100787261 72 1 10 23.60636317669482 20 -25.61586100787261 11 23.61346229386613 21 -25.65243823259491 72 1 10 23.61346229386613 20 -25.65243823259491 11 23.61772324448339 21 -25.69221293656446 72 1 10 23.61772324448339 20 -25.69221293656446 11 23.61914400993594 21 -25.73518511978126 72 1 10 23.61914400993594 20 -25.73518511978126 11 23.61772324448339 21 -25.77825419630858 72 1 10 23.61772324448339 20 -25.77825419630858 11 23.61346229386613 21 -25.81831958020969 72 1 10 23.61346229386613 20 -25.81831958020969 11 23.60636317669482 21 -25.85538127148461 72 1 10 23.60636317669482 20 -25.85538127148461 11 23.59642791158008 21 -25.88943927013332 72 1 10 23.59642791158008 20 -25.88943927013332 11 23.58365851713256 21 -25.92049357615583 72 1 10 23.58365851713256 20 -25.92049357615583 11 23.56805701196288 21 -25.94854418955214 72 1 10 23.56805701196288 20 -25.94854418955214 11 23.54962541468169 21 -25.97359111032224 72 1 10 23.54962541468169 20 -25.97359111032224 11 23.52836574389961 21 -25.99563433846615 72 1 10 23.52836574389961 20 -25.99563433846615 11 23.504561614411 21 -26.01489188393252 72 1 10 23.504561614411 20 -26.01489188393252 11 23.47849260378893 21 -26.03158175667005 72 1 10 23.47849260378893 20 -26.03158175667005 11 23.45015467481211 21 -26.04570395667873 72 1 10 23.45015467481211 20 -26.04570395667873 11 23.41954379025928 21 -26.05725848395855 72 1 10 23.41954379025928 20 -26.05725848395855 11 23.38665591290917 21 -26.06624533850953 72 1 10 23.38665591290917 20 -26.06624533850953 11 23.35148700554051 21 -26.07266452033165 72 1 10 23.35148700554051 20 -26.07266452033165 11 23.31403303093202 21 -26.07651602942493 72 1 10 23.31403303093202 20 -26.07651602942493 11 23.27428995186244 21 -26.07779986578936 72 1 10 23.27428995186244 20 -26.07779986578936 11 23.22050339859898 21 -26.07779986578936 72 1 10 23.22050339859898 20 -26.07779986578936 11 23.16671684533551 21 -26.07779986578936 72 1 10 23.16671684533551 20 -26.07779986578936 11 23.11293029207205 21 -26.07779986578936 72 1 10 23.11293029207205 20 -26.07779986578936 11 23.05914373880858 21 -26.07779986578936 72 1 10 23.05914373880858 20 -26.07779986578936 11 23.00535718554512 21 -26.07779986578936 72 1 10 23.00535718554512 20 -26.07779986578936 11 22.95157063228166 21 -26.07779986578936 72 1 10 22.95157063228166 20 -26.07779986578936 11 22.89778407901819 21 -26.07779986578936 72 1 10 22.89778407901819 20 -26.07779986578936 11 22.84399752575473 21 -26.07779986578936 72 1 10 22.84399752575473 20 -26.07779986578936 11 22.84399752575473 21 -25.99369647225569 72 1 10 22.84399752575473 20 -25.99369647225569 11 22.84399752575473 21 -25.90959307872203 72 1 10 22.84399752575473 20 -25.90959307872203 11 22.84399752575473 21 -25.82548968518837 72 1 10 22.84399752575473 20 -25.82548968518837 11 22.84399752575473 21 -25.74138629165471 72 1 10 22.84399752575473 20 -25.74138629165471 11 22.84399752575473 21 -25.65728289812105 72 1 10 22.84399752575473 20 -25.65728289812105 11 22.84399752575473 21 -25.57317950458738 72 1 10 22.84399752575473 20 -25.57317950458738 11 22.84399752575473 21 -25.48907611105372 72 1 10 22.84399752575473 20 -25.48907611105372 11 22.84399752575473 21 -25.40497271752006 97 0 75 2 76 1 98 0 0 ENDBLK 5 C5D 330 C5A 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 1030 330 102E 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 block 6 70 0 10 0.0 20 0.0 30 0.0 3 block 6 1 0 POLYLINE 5 1032 330 102E 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 1033 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59130333204577 20 -113.1621764853685 30 0.0 0 VERTEX 5 1034 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.53930392206528 20 -112.937577791577 30 0.0 0 VERTEX 5 1035 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.48730451208479 20 -112.7129790977855 30 0.0 0 VERTEX 5 1036 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.4353051021043 20 -112.488380403994 30 0.0 0 VERTEX 5 1037 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.38330569212381 20 -112.2637817102025 30 0.0 0 VERTEX 5 1038 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.33130628214332 20 -112.0391830164109 30 0.0 0 VERTEX 5 1039 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.27930687216283 20 -111.8145843226194 30 0.0 0 VERTEX 5 103A 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.22730746218234 20 -111.5899856288279 30 0.0 0 VERTEX 5 103B 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.17530805220185 20 -111.3653869350364 30 0.0 0 VERTEX 5 103C 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.08844858227999 20 -111.3653869350364 30 0.0 0 VERTEX 5 103D 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.00158911235813 20 -111.3653869350364 30 0.0 0 VERTEX 5 103E 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.91472964243627 20 -111.3653869350364 30 0.0 0 VERTEX 5 103F 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.82787017251441 20 -111.3653869350364 30 0.0 0 VERTEX 5 1040 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.74101070259254 20 -111.3653869350364 30 0.0 0 VERTEX 5 1041 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.65415123267068 20 -111.3653869350364 30 0.0 0 VERTEX 5 1042 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.56729176274882 20 -111.3653869350364 30 0.0 0 VERTEX 5 1043 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -111.3653869350364 30 0.0 0 VERTEX 5 1044 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -111.6510284144572 30 0.0 0 VERTEX 5 1045 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -111.936669893878 30 0.0 0 VERTEX 5 1046 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -112.2223113732988 30 0.0 0 VERTEX 5 1047 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -112.5079528527195 30 0.0 0 VERTEX 5 1048 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -112.7935943321403 30 0.0 0 VERTEX 5 1049 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -113.0792358115611 30 0.0 0 VERTEX 5 104A 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -113.3648772909819 30 0.0 0 VERTEX 5 104B 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -113.6505187704026 30 0.0 0 VERTEX 5 104C 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.53604905306696 20 -113.6505187704026 30 0.0 0 VERTEX 5 104D 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.59166581330696 20 -113.6505187704026 30 0.0 0 VERTEX 5 104E 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.64728257354697 20 -113.6505187704026 30 0.0 0 VERTEX 5 104F 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.70289933378697 20 -113.6505187704026 30 0.0 0 VERTEX 5 1050 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.75851609402697 20 -113.6505187704026 30 0.0 0 VERTEX 5 1051 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.81413285426697 20 -113.6505187704026 30 0.0 0 VERTEX 5 1052 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.86974961450698 20 -113.6505187704026 30 0.0 0 VERTEX 5 1053 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -113.6505187704026 30 0.0 0 VERTEX 5 1054 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -113.4573135092205 30 0.0 0 VERTEX 5 1055 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -113.2641082480383 30 0.0 0 VERTEX 5 1056 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -113.0709029868561 30 0.0 0 VERTEX 5 1057 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -112.877697725674 30 0.0 0 VERTEX 5 1058 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -112.6844924644918 30 0.0 0 VERTEX 5 1059 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -112.4912872033096 30 0.0 0 VERTEX 5 105A 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -112.2980819421275 30 0.0 0 VERTEX 5 105B 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -112.1048766809453 30 0.0 0 VERTEX 5 105C 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92534215141935 20 -112.0873786910832 30 0.0 0 VERTEX 5 105D 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92526948143646 20 -112.0682133288359 30 0.0 0 VERTEX 5 105E 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9251483647983 20 -112.047376556982 30 0.0 0 VERTEX 5 105F 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92497880150488 20 -112.0248643383004 30 0.0 0 VERTEX 5 1060 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92476079155621 20 -112.0006726355697 30 0.0 0 VERTEX 5 1061 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92449433495227 20 -111.9747974115686 30 0.0 0 VERTEX 5 1062 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92417943169307 20 -111.947234629076 30 0.0 0 VERTEX 5 1063 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92381608177861 20 -111.9179802508705 30 0.0 0 VERTEX 5 1064 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92345273186416 20 -111.8888564094861 30 0.0 0 VERTEX 5 1065 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92313782860495 20 -111.8614322382571 30 0.0 0 VERTEX 5 1066 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92287137200102 20 -111.8357117744049 30 0.0 0 VERTEX 5 1067 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92265336205234 20 -111.8116990551505 30 0.0 0 VERTEX 5 1068 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92248379875893 20 -111.7893981177155 30 0.0 0 VERTEX 5 1069 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92236268212077 20 -111.7688129993209 30 0.0 0 VERTEX 5 106A 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92229001213788 20 -111.7499477371881 30 0.0 0 VERTEX 5 106B 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92226578881025 20 -111.7328063685383 30 0.0 0 VERTEX 5 106C 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.97600927838015 20 -111.9725204187714 30 0.0 0 VERTEX 5 106D 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02975276795005 20 -112.2122344690044 30 0.0 0 VERTEX 5 106E 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.08349625751994 20 -112.4519485192374 30 0.0 0 VERTEX 5 106F 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.13723974708984 20 -112.6916625694705 30 0.0 0 VERTEX 5 1070 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.19098323665974 20 -112.9313766197035 30 0.0 0 VERTEX 5 1071 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.24472672622964 20 -113.1710906699366 30 0.0 0 VERTEX 5 1072 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.29847021579953 20 -113.4108047201696 30 0.0 0 VERTEX 5 1073 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.35221370536943 20 -113.6505187704026 30 0.0 0 VERTEX 5 1074 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.41022050060232 20 -113.6505187704026 30 0.0 0 VERTEX 5 1075 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46822729583522 20 -113.6505187704026 30 0.0 0 VERTEX 5 1076 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.52623409106812 20 -113.6505187704026 30 0.0 0 VERTEX 5 1077 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.58424088630101 20 -113.6505187704026 30 0.0 0 VERTEX 5 1078 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.6422476815339 20 -113.6505187704026 30 0.0 0 VERTEX 5 1079 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.7002544767668 20 -113.6505187704026 30 0.0 0 VERTEX 5 107A 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.75826127199969 20 -113.6505187704026 30 0.0 0 VERTEX 5 107B 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.81626806723258 20 -113.6505187704026 30 0.0 0 VERTEX 5 107C 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.87039913004457 20 -113.4108047201696 30 0.0 0 VERTEX 5 107D 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.92453019285656 20 -113.1710906699366 30 0.0 0 VERTEX 5 107E 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.97866125566855 20 -112.9313766197035 30 0.0 0 VERTEX 5 107F 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.03279231848054 20 -112.6916625694705 30 0.0 0 VERTEX 5 1080 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.08692338129253 20 -112.4519485192374 30 0.0 0 VERTEX 5 1081 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14105444410451 20 -112.2122344690044 30 0.0 0 VERTEX 5 1082 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.1951855069165 20 -111.9725204187714 30 0.0 0 VERTEX 5 1083 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24931656972849 20 -111.7328063685383 30 0.0 0 VERTEX 5 1084 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24929234640086 20 -111.7499477371881 30 0.0 0 VERTEX 5 1085 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24921967641797 20 -111.7688129993209 30 0.0 0 VERTEX 5 1086 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24909855977981 20 -111.7893981177155 30 0.0 0 VERTEX 5 1087 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2489289964864 20 -111.8116990551505 30 0.0 0 VERTEX 5 1088 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24871098653772 20 -111.8357117744049 30 0.0 0 VERTEX 5 1089 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24844452993378 20 -111.8614322382571 30 0.0 0 VERTEX 5 108A 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24812962667459 20 -111.8888564094861 30 0.0 0 VERTEX 5 108B 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24776627676013 20 -111.9179802508705 30 0.0 0 VERTEX 5 108C 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24740292684567 20 -111.947234629076 30 0.0 0 VERTEX 5 108D 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24708802358647 20 -111.9747974115686 30 0.0 0 VERTEX 5 108E 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24682156698253 20 -112.0006726355697 30 0.0 0 VERTEX 5 108F 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24660355703385 20 -112.0248643383004 30 0.0 0 VERTEX 5 1090 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24643399374044 20 -112.047376556982 30 0.0 0 VERTEX 5 1091 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24631287710229 20 -112.0682133288359 30 0.0 0 VERTEX 5 1092 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2462402071194 20 -112.0873786910832 30 0.0 0 VERTEX 5 1093 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -112.1048766809453 30 0.0 0 VERTEX 5 1094 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -112.2980819421275 30 0.0 0 VERTEX 5 1095 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -112.4912872033096 30 0.0 0 VERTEX 5 1096 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -112.6844924644918 30 0.0 0 VERTEX 5 1097 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -112.877697725674 30 0.0 0 VERTEX 5 1098 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -113.0709029868561 30 0.0 0 VERTEX 5 1099 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -113.2641082480383 30 0.0 0 VERTEX 5 109A 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -113.4573135092205 30 0.0 0 VERTEX 5 109B 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -113.6505187704026 30 0.0 0 VERTEX 5 109C 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.30183274403177 20 -113.6505187704026 30 0.0 0 VERTEX 5 109D 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.35744950427177 20 -113.6505187704026 30 0.0 0 VERTEX 5 109E 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.41306626451177 20 -113.6505187704026 30 0.0 0 VERTEX 5 109F 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.46868302475177 20 -113.6505187704026 30 0.0 0 VERTEX 5 10A0 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.52429978499178 20 -113.6505187704026 30 0.0 0 VERTEX 5 10A1 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.57991654523178 20 -113.6505187704026 30 0.0 0 VERTEX 5 10A2 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.63553330547178 20 -113.6505187704026 30 0.0 0 VERTEX 5 10A3 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -113.6505187704026 30 0.0 0 VERTEX 5 10A4 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -113.3648772909819 30 0.0 0 VERTEX 5 10A5 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -113.0792358115611 30 0.0 0 VERTEX 5 10A6 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -112.7935943321403 30 0.0 0 VERTEX 5 10A7 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -112.5079528527195 30 0.0 0 VERTEX 5 10A8 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -112.2223113732988 30 0.0 0 VERTEX 5 10A9 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -111.936669893878 30 0.0 0 VERTEX 5 10AA 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -111.6510284144572 30 0.0 0 VERTEX 5 10AB 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -111.3653869350364 30 0.0 0 VERTEX 5 10AC 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60525952889515 20 -111.3653869350364 30 0.0 0 VERTEX 5 10AD 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.51936899207851 20 -111.3653869350364 30 0.0 0 VERTEX 5 10AE 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.43347845526188 20 -111.3653869350364 30 0.0 0 VERTEX 5 10AF 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.34758791844524 20 -111.3653869350364 30 0.0 0 VERTEX 5 10B0 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2616973816286 20 -111.3653869350364 30 0.0 0 VERTEX 5 10B1 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.17580684481197 20 -111.3653869350364 30 0.0 0 VERTEX 5 10B2 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.08991630799533 20 -111.3653869350364 30 0.0 0 VERTEX 5 10B3 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.0040257711787 20 -111.3653869350364 30 0.0 0 VERTEX 5 10B4 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.95243546628708 20 -111.5899856288279 30 0.0 0 VERTEX 5 10B5 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.90084516139547 20 -111.8145843226194 30 0.0 0 VERTEX 5 10B6 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.84925485650385 20 -112.0391830164109 30 0.0 0 VERTEX 5 10B7 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.79766455161224 20 -112.2637817102025 30 0.0 0 VERTEX 5 10B8 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.74607424672062 20 -112.488380403994 30 0.0 0 VERTEX 5 10B9 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.694483941829 20 -112.7129790977855 30 0.0 0 VERTEX 5 10BA 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.64289363693739 20 -112.937577791577 30 0.0 0 VERTEX 5 10BB 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59130333204577 20 -113.1621764853685 30 0.0 0 VERTEX 5 10BC 330 1032 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59130333204577 20 -113.1621764853685 30 0.0 0 SEQEND 5 10BE 330 1032 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 10BD 330 102E 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 136 72 1 10 23.59130333204577 20 -113.1621764853685 11 23.53930392206528 21 -112.937577791577 72 1 10 23.53930392206528 20 -112.937577791577 11 23.48730451208479 21 -112.7129790977855 72 1 10 23.48730451208479 20 -112.7129790977855 11 23.4353051021043 21 -112.488380403994 72 1 10 23.4353051021043 20 -112.488380403994 11 23.38330569212381 21 -112.2637817102025 72 1 10 23.38330569212381 20 -112.2637817102025 11 23.33130628214332 21 -112.0391830164109 72 1 10 23.33130628214332 20 -112.0391830164109 11 23.27930687216283 21 -111.8145843226194 72 1 10 23.27930687216283 20 -111.8145843226194 11 23.22730746218234 21 -111.5899856288279 72 1 10 23.22730746218234 20 -111.5899856288279 11 23.17530805220185 21 -111.3653869350364 72 1 10 23.17530805220185 20 -111.3653869350364 11 23.08844858227999 21 -111.3653869350364 72 1 10 23.08844858227999 20 -111.3653869350364 11 23.00158911235813 21 -111.3653869350364 72 1 10 23.00158911235813 20 -111.3653869350364 11 22.91472964243627 21 -111.3653869350364 72 1 10 22.91472964243627 20 -111.3653869350364 11 22.82787017251441 21 -111.3653869350364 72 1 10 22.82787017251441 20 -111.3653869350364 11 22.74101070259254 21 -111.3653869350364 72 1 10 22.74101070259254 20 -111.3653869350364 11 22.65415123267068 21 -111.3653869350364 72 1 10 22.65415123267068 20 -111.3653869350364 11 22.56729176274882 21 -111.3653869350364 72 1 10 22.56729176274882 20 -111.3653869350364 11 22.48043229282696 21 -111.3653869350364 72 1 10 22.48043229282696 20 -111.3653869350364 11 22.48043229282696 21 -111.6510284144572 72 1 10 22.48043229282696 20 -111.6510284144572 11 22.48043229282696 21 -111.936669893878 72 1 10 22.48043229282696 20 -111.936669893878 11 22.48043229282696 21 -112.2223113732988 72 1 10 22.48043229282696 20 -112.2223113732988 11 22.48043229282696 21 -112.5079528527195 72 1 10 22.48043229282696 20 -112.5079528527195 11 22.48043229282696 21 -112.7935943321403 72 1 10 22.48043229282696 20 -112.7935943321403 11 22.48043229282696 21 -113.0792358115611 72 1 10 22.48043229282696 20 -113.0792358115611 11 22.48043229282696 21 -113.3648772909819 72 1 10 22.48043229282696 20 -113.3648772909819 11 22.48043229282696 21 -113.6505187704026 72 1 10 22.48043229282696 20 -113.6505187704026 11 22.53604905306696 21 -113.6505187704026 72 1 10 22.53604905306696 20 -113.6505187704026 11 22.59166581330696 21 -113.6505187704026 72 1 10 22.59166581330696 20 -113.6505187704026 11 22.64728257354697 21 -113.6505187704026 72 1 10 22.64728257354697 20 -113.6505187704026 11 22.70289933378697 21 -113.6505187704026 72 1 10 22.70289933378697 20 -113.6505187704026 11 22.75851609402697 21 -113.6505187704026 72 1 10 22.75851609402697 20 -113.6505187704026 11 22.81413285426697 21 -113.6505187704026 72 1 10 22.81413285426697 20 -113.6505187704026 11 22.86974961450698 21 -113.6505187704026 72 1 10 22.86974961450698 20 -113.6505187704026 11 22.92536637474698 21 -113.6505187704026 72 1 10 22.92536637474698 20 -113.6505187704026 11 22.92536637474698 21 -113.4573135092205 72 1 10 22.92536637474698 20 -113.4573135092205 11 22.92536637474698 21 -113.2641082480383 72 1 10 22.92536637474698 20 -113.2641082480383 11 22.92536637474698 21 -113.0709029868561 72 1 10 22.92536637474698 20 -113.0709029868561 11 22.92536637474698 21 -112.877697725674 72 1 10 22.92536637474698 20 -112.877697725674 11 22.92536637474698 21 -112.6844924644918 72 1 10 22.92536637474698 20 -112.6844924644918 11 22.92536637474698 21 -112.4912872033096 72 1 10 22.92536637474698 20 -112.4912872033096 11 22.92536637474698 21 -112.2980819421275 72 1 10 22.92536637474698 20 -112.2980819421275 11 22.92536637474698 21 -112.1048766809453 72 1 10 22.92536637474698 20 -112.1048766809453 11 22.92534215141935 21 -112.0873786910832 72 1 10 22.92534215141935 20 -112.0873786910832 11 22.92526948143646 21 -112.0682133288359 72 1 10 22.92526948143646 20 -112.0682133288359 11 22.9251483647983 21 -112.047376556982 72 1 10 22.9251483647983 20 -112.047376556982 11 22.92497880150488 21 -112.0248643383004 72 1 10 22.92497880150488 20 -112.0248643383004 11 22.92476079155621 21 -112.0006726355697 72 1 10 22.92476079155621 20 -112.0006726355697 11 22.92449433495227 21 -111.9747974115686 72 1 10 22.92449433495227 20 -111.9747974115686 11 22.92417943169307 21 -111.947234629076 72 1 10 22.92417943169307 20 -111.947234629076 11 22.92381608177861 21 -111.9179802508705 72 1 10 22.92381608177861 20 -111.9179802508705 11 22.92345273186416 21 -111.8888564094861 72 1 10 22.92345273186416 20 -111.8888564094861 11 22.92313782860495 21 -111.8614322382571 72 1 10 22.92313782860495 20 -111.8614322382571 11 22.92287137200102 21 -111.8357117744049 72 1 10 22.92287137200102 20 -111.8357117744049 11 22.92265336205234 21 -111.8116990551505 72 1 10 22.92265336205234 20 -111.8116990551505 11 22.92248379875893 21 -111.7893981177155 72 1 10 22.92248379875893 20 -111.7893981177155 11 22.92236268212077 21 -111.7688129993209 72 1 10 22.92236268212077 20 -111.7688129993209 11 22.92229001213788 21 -111.7499477371881 72 1 10 22.92229001213788 20 -111.7499477371881 11 22.92226578881025 21 -111.7328063685383 72 1 10 22.92226578881025 20 -111.7328063685383 11 22.97600927838015 21 -111.9725204187714 72 1 10 22.97600927838015 20 -111.9725204187714 11 23.02975276795005 21 -112.2122344690044 72 1 10 23.02975276795005 20 -112.2122344690044 11 23.08349625751994 21 -112.4519485192374 72 1 10 23.08349625751994 20 -112.4519485192374 11 23.13723974708984 21 -112.6916625694705 72 1 10 23.13723974708984 20 -112.6916625694705 11 23.19098323665974 21 -112.9313766197035 72 1 10 23.19098323665974 20 -112.9313766197035 11 23.24472672622964 21 -113.1710906699366 72 1 10 23.24472672622964 20 -113.1710906699366 11 23.29847021579953 21 -113.4108047201696 72 1 10 23.29847021579953 20 -113.4108047201696 11 23.35221370536943 21 -113.6505187704026 72 1 10 23.35221370536943 20 -113.6505187704026 11 23.41022050060232 21 -113.6505187704026 72 1 10 23.41022050060232 20 -113.6505187704026 11 23.46822729583522 21 -113.6505187704026 72 1 10 23.46822729583522 20 -113.6505187704026 11 23.52623409106812 21 -113.6505187704026 72 1 10 23.52623409106812 20 -113.6505187704026 11 23.58424088630101 21 -113.6505187704026 72 1 10 23.58424088630101 20 -113.6505187704026 11 23.6422476815339 21 -113.6505187704026 72 1 10 23.6422476815339 20 -113.6505187704026 11 23.7002544767668 21 -113.6505187704026 72 1 10 23.7002544767668 20 -113.6505187704026 11 23.75826127199969 21 -113.6505187704026 72 1 10 23.75826127199969 20 -113.6505187704026 11 23.81626806723258 21 -113.6505187704026 72 1 10 23.81626806723258 20 -113.6505187704026 11 23.87039913004457 21 -113.4108047201696 72 1 10 23.87039913004457 20 -113.4108047201696 11 23.92453019285656 21 -113.1710906699366 72 1 10 23.92453019285656 20 -113.1710906699366 11 23.97866125566855 21 -112.9313766197035 72 1 10 23.97866125566855 20 -112.9313766197035 11 24.03279231848054 21 -112.6916625694705 72 1 10 24.03279231848054 20 -112.6916625694705 11 24.08692338129253 21 -112.4519485192374 72 1 10 24.08692338129253 20 -112.4519485192374 11 24.14105444410451 21 -112.2122344690044 72 1 10 24.14105444410451 20 -112.2122344690044 11 24.1951855069165 21 -111.9725204187714 72 1 10 24.1951855069165 20 -111.9725204187714 11 24.24931656972849 21 -111.7328063685383 72 1 10 24.24931656972849 20 -111.7328063685383 11 24.24929234640086 21 -111.7499477371881 72 1 10 24.24929234640086 20 -111.7499477371881 11 24.24921967641797 21 -111.7688129993209 72 1 10 24.24921967641797 20 -111.7688129993209 11 24.24909855977981 21 -111.7893981177155 72 1 10 24.24909855977981 20 -111.7893981177155 11 24.2489289964864 21 -111.8116990551505 72 1 10 24.2489289964864 20 -111.8116990551505 11 24.24871098653772 21 -111.8357117744049 72 1 10 24.24871098653772 20 -111.8357117744049 11 24.24844452993378 21 -111.8614322382571 72 1 10 24.24844452993378 20 -111.8614322382571 11 24.24812962667459 21 -111.8888564094861 72 1 10 24.24812962667459 20 -111.8888564094861 11 24.24776627676013 21 -111.9179802508705 72 1 10 24.24776627676013 20 -111.9179802508705 11 24.24740292684567 21 -111.947234629076 72 1 10 24.24740292684567 20 -111.947234629076 11 24.24708802358647 21 -111.9747974115686 72 1 10 24.24708802358647 20 -111.9747974115686 11 24.24682156698253 21 -112.0006726355697 72 1 10 24.24682156698253 20 -112.0006726355697 11 24.24660355703385 21 -112.0248643383004 72 1 10 24.24660355703385 20 -112.0248643383004 11 24.24643399374044 21 -112.047376556982 72 1 10 24.24643399374044 20 -112.047376556982 11 24.24631287710229 21 -112.0682133288359 72 1 10 24.24631287710229 20 -112.0682133288359 11 24.2462402071194 21 -112.0873786910832 72 1 10 24.2462402071194 20 -112.0873786910832 11 24.24621598379176 21 -112.1048766809453 72 1 10 24.24621598379176 20 -112.1048766809453 11 24.24621598379176 21 -112.2980819421275 72 1 10 24.24621598379176 20 -112.2980819421275 11 24.24621598379176 21 -112.4912872033096 72 1 10 24.24621598379176 20 -112.4912872033096 11 24.24621598379176 21 -112.6844924644918 72 1 10 24.24621598379176 20 -112.6844924644918 11 24.24621598379176 21 -112.877697725674 72 1 10 24.24621598379176 20 -112.877697725674 11 24.24621598379176 21 -113.0709029868561 72 1 10 24.24621598379176 20 -113.0709029868561 11 24.24621598379176 21 -113.2641082480383 72 1 10 24.24621598379176 20 -113.2641082480383 11 24.24621598379176 21 -113.4573135092205 72 1 10 24.24621598379176 20 -113.4573135092205 11 24.24621598379176 21 -113.6505187704026 72 1 10 24.24621598379176 20 -113.6505187704026 11 24.30183274403177 21 -113.6505187704026 72 1 10 24.30183274403177 20 -113.6505187704026 11 24.35744950427177 21 -113.6505187704026 72 1 10 24.35744950427177 20 -113.6505187704026 11 24.41306626451177 21 -113.6505187704026 72 1 10 24.41306626451177 20 -113.6505187704026 11 24.46868302475177 21 -113.6505187704026 72 1 10 24.46868302475177 20 -113.6505187704026 11 24.52429978499178 21 -113.6505187704026 72 1 10 24.52429978499178 20 -113.6505187704026 11 24.57991654523178 21 -113.6505187704026 72 1 10 24.57991654523178 20 -113.6505187704026 11 24.63553330547178 21 -113.6505187704026 72 1 10 24.63553330547178 20 -113.6505187704026 11 24.69115006571178 21 -113.6505187704026 72 1 10 24.69115006571178 20 -113.6505187704026 11 24.69115006571178 21 -113.3648772909819 72 1 10 24.69115006571178 20 -113.3648772909819 11 24.69115006571178 21 -113.0792358115611 72 1 10 24.69115006571178 20 -113.0792358115611 11 24.69115006571178 21 -112.7935943321403 72 1 10 24.69115006571178 20 -112.7935943321403 11 24.69115006571178 21 -112.5079528527195 72 1 10 24.69115006571178 20 -112.5079528527195 11 24.69115006571178 21 -112.2223113732988 72 1 10 24.69115006571178 20 -112.2223113732988 11 24.69115006571178 21 -111.936669893878 72 1 10 24.69115006571178 20 -111.936669893878 11 24.69115006571178 21 -111.6510284144572 72 1 10 24.69115006571178 20 -111.6510284144572 11 24.69115006571178 21 -111.3653869350364 72 1 10 24.69115006571178 20 -111.3653869350364 11 24.60525952889515 21 -111.3653869350364 72 1 10 24.60525952889515 20 -111.3653869350364 11 24.51936899207851 21 -111.3653869350364 72 1 10 24.51936899207851 20 -111.3653869350364 11 24.43347845526188 21 -111.3653869350364 72 1 10 24.43347845526188 20 -111.3653869350364 11 24.34758791844524 21 -111.3653869350364 72 1 10 24.34758791844524 20 -111.3653869350364 11 24.2616973816286 21 -111.3653869350364 72 1 10 24.2616973816286 20 -111.3653869350364 11 24.17580684481197 21 -111.3653869350364 72 1 10 24.17580684481197 20 -111.3653869350364 11 24.08991630799533 21 -111.3653869350364 72 1 10 24.08991630799533 20 -111.3653869350364 11 24.0040257711787 21 -111.3653869350364 72 1 10 24.0040257711787 20 -111.3653869350364 11 23.95243546628708 21 -111.5899856288279 72 1 10 23.95243546628708 20 -111.5899856288279 11 23.90084516139547 21 -111.8145843226194 72 1 10 23.90084516139547 20 -111.8145843226194 11 23.84925485650385 21 -112.0391830164109 72 1 10 23.84925485650385 20 -112.0391830164109 11 23.79766455161224 21 -112.2637817102025 72 1 10 23.79766455161224 20 -112.2637817102025 11 23.74607424672062 21 -112.488380403994 72 1 10 23.74607424672062 20 -112.488380403994 11 23.694483941829 21 -112.7129790977855 72 1 10 23.694483941829 20 -112.7129790977855 11 23.64289363693739 21 -112.937577791577 72 1 10 23.64289363693739 20 -112.937577791577 11 23.59130333204577 21 -113.1621764853685 97 0 75 2 76 1 98 0 0 POLYLINE 5 10BF 330 102E 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 10C0 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C1 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.60806596028724 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C2 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.6673646663271 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C3 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.72666337236696 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C4 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.78596207840683 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C5 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.84526078444669 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C6 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.90455949048655 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C7 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.96385819652642 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C8 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -113.6505187704026 30 0.0 0 VERTEX 5 10C9 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -113.5307586385967 30 0.0 0 VERTEX 5 10CA 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -113.4109985067906 30 0.0 0 VERTEX 5 10CB 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -113.2912383749847 30 0.0 0 VERTEX 5 10CC 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -113.1714782431787 30 0.0 0 VERTEX 5 10CD 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -113.0517181113727 30 0.0 0 VERTEX 5 10CE 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.9319579795667 30 0.0 0 VERTEX 5 10CF 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.8121978477607 30 0.0 0 VERTEX 5 10D0 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D1 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.14969956610886 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D2 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.27624222965144 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D3 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.40278489319403 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D4 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.52932755673661 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D5 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.65587022027919 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D6 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.78241288382178 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D7 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.90895554736436 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D8 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.6924377159547 30 0.0 0 VERTEX 5 10D9 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.6428283409671 30 0.0 0 VERTEX 5 10DA 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.5932189659795 30 0.0 0 VERTEX 5 10DB 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.5436095909919 30 0.0 0 VERTEX 5 10DC 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.4940002160043 30 0.0 0 VERTEX 5 10DD 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.4443908410167 30 0.0 0 VERTEX 5 10DE 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.3947814660291 30 0.0 0 VERTEX 5 10DF 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.3451720910415 30 0.0 0 VERTEX 5 10E0 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E1 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.90895554736436 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E2 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.78241288382178 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E3 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.65587022027919 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E4 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.52932755673661 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E5 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.40278489319403 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E6 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.27624222965144 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E7 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.14969956610886 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E8 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.2955627160539 30 0.0 0 VERTEX 5 10E9 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.2298690515195 30 0.0 0 VERTEX 5 10EA 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.1641753869852 30 0.0 0 VERTEX 5 10EB 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.0984817224508 30 0.0 0 VERTEX 5 10EC 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -112.0327880579164 30 0.0 0 VERTEX 5 10ED 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -111.9670943933821 30 0.0 0 VERTEX 5 10EE 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -111.9014007288477 30 0.0 0 VERTEX 5 10EF 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -111.8357070643134 30 0.0 0 VERTEX 5 10F0 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -111.770013399779 30 0.0 0 VERTEX 5 10F1 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.16752793524503 20 -111.770013399779 30 0.0 0 VERTEX 5 10F2 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.31189896792378 20 -111.770013399779 30 0.0 0 VERTEX 5 10F3 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.45627000060253 20 -111.770013399779 30 0.0 0 VERTEX 5 10F4 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.60064103328128 20 -111.770013399779 30 0.0 0 VERTEX 5 10F5 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.74501206596003 20 -111.770013399779 30 0.0 0 VERTEX 5 10F6 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.88938309863878 20 -111.770013399779 30 0.0 0 VERTEX 5 10F7 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03375413131754 20 -111.770013399779 30 0.0 0 VERTEX 5 10F8 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.770013399779 30 0.0 0 VERTEX 5 10F9 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.7198226649283 30 0.0 0 VERTEX 5 10FA 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.6696319300776 30 0.0 0 VERTEX 5 10FB 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.6194411952268 30 0.0 0 VERTEX 5 10FC 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.5692504603761 30 0.0 0 VERTEX 5 10FD 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.5190597255254 30 0.0 0 VERTEX 5 10FE 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.4688689906746 30 0.0 0 VERTEX 5 10FF 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.4186782558239 30 0.0 0 VERTEX 5 1100 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -111.3684875209731 30 0.0 0 VERTEX 5 1101 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.97445542527767 20 -111.3684875209731 30 0.0 0 VERTEX 5 1102 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.77078568655906 20 -111.3684875209731 30 0.0 0 VERTEX 5 1103 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.56711594784045 20 -111.3684875209731 30 0.0 0 VERTEX 5 1104 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.36344620912183 20 -111.3684875209731 30 0.0 0 VERTEX 5 1105 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.15977647040322 20 -111.3684875209731 30 0.0 0 VERTEX 5 1106 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.9561067316846 20 -111.3684875209731 30 0.0 0 VERTEX 5 1107 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.75243699296599 20 -111.3684875209731 30 0.0 0 VERTEX 5 1108 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -111.3684875209731 30 0.0 0 VERTEX 5 1109 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -111.6537414271518 30 0.0 0 VERTEX 5 110A 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -111.9389953333305 30 0.0 0 VERTEX 5 110B 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -112.2242492395092 30 0.0 0 VERTEX 5 110C 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -112.5095031456879 30 0.0 0 VERTEX 5 110D 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -112.7947570518666 30 0.0 0 VERTEX 5 110E 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -113.0800109580453 30 0.0 0 VERTEX 5 110F 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -113.365264864224 30 0.0 0 VERTEX 5 1110 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -113.6505187704026 30 0.0 0 VERTEX 5 1111 330 10BF 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -113.6505187704026 30 0.0 0 SEQEND 5 1113 330 10BF 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 1112 330 102E 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 80 72 1 10 20.54876725424738 20 -113.6505187704026 11 20.60806596028724 21 -113.6505187704026 72 1 10 20.60806596028724 20 -113.6505187704026 11 20.6673646663271 21 -113.6505187704026 72 1 10 20.6673646663271 20 -113.6505187704026 11 20.72666337236696 21 -113.6505187704026 72 1 10 20.72666337236696 20 -113.6505187704026 11 20.78596207840683 21 -113.6505187704026 72 1 10 20.78596207840683 20 -113.6505187704026 11 20.84526078444669 21 -113.6505187704026 72 1 10 20.84526078444669 20 -113.6505187704026 11 20.90455949048655 21 -113.6505187704026 72 1 10 20.90455949048655 20 -113.6505187704026 11 20.96385819652642 21 -113.6505187704026 72 1 10 20.96385819652642 20 -113.6505187704026 11 21.02315690256628 21 -113.6505187704026 72 1 10 21.02315690256628 20 -113.6505187704026 11 21.02315690256628 21 -113.5307586385967 72 1 10 21.02315690256628 20 -113.5307586385967 11 21.02315690256628 21 -113.4109985067906 72 1 10 21.02315690256628 20 -113.4109985067906 11 21.02315690256628 21 -113.2912383749847 72 1 10 21.02315690256628 20 -113.2912383749847 11 21.02315690256628 21 -113.1714782431787 72 1 10 21.02315690256628 20 -113.1714782431787 11 21.02315690256628 21 -113.0517181113727 72 1 10 21.02315690256628 20 -113.0517181113727 11 21.02315690256628 21 -112.9319579795667 72 1 10 21.02315690256628 20 -112.9319579795667 11 21.02315690256628 21 -112.8121978477607 72 1 10 21.02315690256628 20 -112.8121978477607 11 21.02315690256628 21 -112.6924377159547 72 1 10 21.02315690256628 20 -112.6924377159547 11 21.14969956610886 21 -112.6924377159547 72 1 10 21.14969956610886 20 -112.6924377159547 11 21.27624222965144 21 -112.6924377159547 72 1 10 21.27624222965144 20 -112.6924377159547 11 21.40278489319403 21 -112.6924377159547 72 1 10 21.40278489319403 20 -112.6924377159547 11 21.52932755673661 21 -112.6924377159547 72 1 10 21.52932755673661 20 -112.6924377159547 11 21.65587022027919 21 -112.6924377159547 72 1 10 21.65587022027919 20 -112.6924377159547 11 21.78241288382178 21 -112.6924377159547 72 1 10 21.78241288382178 20 -112.6924377159547 11 21.90895554736436 21 -112.6924377159547 72 1 10 21.90895554736436 20 -112.6924377159547 11 22.03549821090694 21 -112.6924377159547 72 1 10 22.03549821090694 20 -112.6924377159547 11 22.03549821090694 21 -112.6428283409671 72 1 10 22.03549821090694 20 -112.6428283409671 11 22.03549821090694 21 -112.5932189659795 72 1 10 22.03549821090694 20 -112.5932189659795 11 22.03549821090694 21 -112.5436095909919 72 1 10 22.03549821090694 20 -112.5436095909919 11 22.03549821090694 21 -112.4940002160043 72 1 10 22.03549821090694 20 -112.4940002160043 11 22.03549821090694 21 -112.4443908410167 72 1 10 22.03549821090694 20 -112.4443908410167 11 22.03549821090694 21 -112.3947814660291 72 1 10 22.03549821090694 20 -112.3947814660291 11 22.03549821090694 21 -112.3451720910415 72 1 10 22.03549821090694 20 -112.3451720910415 11 22.03549821090694 21 -112.2955627160539 72 1 10 22.03549821090694 20 -112.2955627160539 11 21.90895554736436 21 -112.2955627160539 72 1 10 21.90895554736436 20 -112.2955627160539 11 21.78241288382178 21 -112.2955627160539 72 1 10 21.78241288382178 20 -112.2955627160539 11 21.65587022027919 21 -112.2955627160539 72 1 10 21.65587022027919 20 -112.2955627160539 11 21.52932755673661 21 -112.2955627160539 72 1 10 21.52932755673661 20 -112.2955627160539 11 21.40278489319403 21 -112.2955627160539 72 1 10 21.40278489319403 20 -112.2955627160539 11 21.27624222965144 21 -112.2955627160539 72 1 10 21.27624222965144 20 -112.2955627160539 11 21.14969956610886 21 -112.2955627160539 72 1 10 21.14969956610886 20 -112.2955627160539 11 21.02315690256628 21 -112.2955627160539 72 1 10 21.02315690256628 20 -112.2955627160539 11 21.02315690256628 21 -112.2298690515195 72 1 10 21.02315690256628 20 -112.2298690515195 11 21.02315690256628 21 -112.1641753869852 72 1 10 21.02315690256628 20 -112.1641753869852 11 21.02315690256628 21 -112.0984817224508 72 1 10 21.02315690256628 20 -112.0984817224508 11 21.02315690256628 21 -112.0327880579164 72 1 10 21.02315690256628 20 -112.0327880579164 11 21.02315690256628 21 -111.9670943933821 72 1 10 21.02315690256628 20 -111.9670943933821 11 21.02315690256628 21 -111.9014007288477 72 1 10 21.02315690256628 20 -111.9014007288477 11 21.02315690256628 21 -111.8357070643134 72 1 10 21.02315690256628 20 -111.8357070643134 11 21.02315690256628 21 -111.770013399779 72 1 10 21.02315690256628 20 -111.770013399779 11 21.16752793524503 21 -111.770013399779 72 1 10 21.16752793524503 20 -111.770013399779 11 21.31189896792378 21 -111.770013399779 72 1 10 21.31189896792378 20 -111.770013399779 11 21.45627000060253 21 -111.770013399779 72 1 10 21.45627000060253 20 -111.770013399779 11 21.60064103328128 21 -111.770013399779 72 1 10 21.60064103328128 20 -111.770013399779 11 21.74501206596003 21 -111.770013399779 72 1 10 21.74501206596003 20 -111.770013399779 11 21.88938309863878 21 -111.770013399779 72 1 10 21.88938309863878 20 -111.770013399779 11 22.03375413131754 21 -111.770013399779 72 1 10 22.03375413131754 20 -111.770013399779 11 22.17812516399629 21 -111.770013399779 72 1 10 22.17812516399629 20 -111.770013399779 11 22.17812516399629 21 -111.7198226649283 72 1 10 22.17812516399629 20 -111.7198226649283 11 22.17812516399629 21 -111.6696319300776 72 1 10 22.17812516399629 20 -111.6696319300776 11 22.17812516399629 21 -111.6194411952268 72 1 10 22.17812516399629 20 -111.6194411952268 11 22.17812516399629 21 -111.5692504603761 72 1 10 22.17812516399629 20 -111.5692504603761 11 22.17812516399629 21 -111.5190597255254 72 1 10 22.17812516399629 20 -111.5190597255254 11 22.17812516399629 21 -111.4688689906746 72 1 10 22.17812516399629 20 -111.4688689906746 11 22.17812516399629 21 -111.4186782558239 72 1 10 22.17812516399629 20 -111.4186782558239 11 22.17812516399629 21 -111.3684875209731 72 1 10 22.17812516399629 20 -111.3684875209731 11 21.97445542527767 21 -111.3684875209731 72 1 10 21.97445542527767 20 -111.3684875209731 11 21.77078568655906 21 -111.3684875209731 72 1 10 21.77078568655906 20 -111.3684875209731 11 21.56711594784045 21 -111.3684875209731 72 1 10 21.56711594784045 20 -111.3684875209731 11 21.36344620912183 21 -111.3684875209731 72 1 10 21.36344620912183 20 -111.3684875209731 11 21.15977647040322 21 -111.3684875209731 72 1 10 21.15977647040322 20 -111.3684875209731 11 20.9561067316846 21 -111.3684875209731 72 1 10 20.9561067316846 20 -111.3684875209731 11 20.75243699296599 21 -111.3684875209731 72 1 10 20.75243699296599 20 -111.3684875209731 11 20.54876725424738 21 -111.3684875209731 72 1 10 20.54876725424738 20 -111.3684875209731 11 20.54876725424738 21 -111.6537414271518 72 1 10 20.54876725424738 20 -111.6537414271518 11 20.54876725424738 21 -111.9389953333305 72 1 10 20.54876725424738 20 -111.9389953333305 11 20.54876725424738 21 -112.2242492395092 72 1 10 20.54876725424738 20 -112.2242492395092 11 20.54876725424738 21 -112.5095031456879 72 1 10 20.54876725424738 20 -112.5095031456879 11 20.54876725424738 21 -112.7947570518666 72 1 10 20.54876725424738 20 -112.7947570518666 11 20.54876725424738 21 -113.0800109580453 72 1 10 20.54876725424738 20 -113.0800109580453 11 20.54876725424738 21 -113.365264864224 72 1 10 20.54876725424738 20 -113.365264864224 11 20.54876725424738 21 -113.6505187704026 97 0 75 2 76 1 98 0 0 ENDBLK 5 1031 330 102E 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 1116 330 1114 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 block 7 70 0 10 0.0 20 0.0 30 0.0 3 block 7 1 0 POLYLINE 5 1118 330 1114 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 1119 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59130333204577 20 -57.28192701551256 30 0.0 0 VERTEX 5 111A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.53930392206528 20 -57.05732832172105 30 0.0 0 VERTEX 5 111B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.48730451208479 20 -56.83272962792955 30 0.0 0 VERTEX 5 111C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.4353051021043 20 -56.60813093413803 30 0.0 0 VERTEX 5 111D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.38330569212381 20 -56.38353224034653 30 0.0 0 VERTEX 5 111E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.33130628214332 20 -56.15893354655502 30 0.0 0 VERTEX 5 111F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.27930687216283 20 -55.93433485276351 30 0.0 0 VERTEX 5 1120 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.22730746218234 20 -55.70973615897201 30 0.0 0 VERTEX 5 1121 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.17530805220185 20 -55.4851374651805 30 0.0 0 VERTEX 5 1122 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.08844858227999 20 -55.4851374651805 30 0.0 0 VERTEX 5 1123 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.00158911235813 20 -55.4851374651805 30 0.0 0 VERTEX 5 1124 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.91472964243627 20 -55.4851374651805 30 0.0 0 VERTEX 5 1125 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.82787017251441 20 -55.4851374651805 30 0.0 0 VERTEX 5 1126 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.74101070259254 20 -55.4851374651805 30 0.0 0 VERTEX 5 1127 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.65415123267068 20 -55.4851374651805 30 0.0 0 VERTEX 5 1128 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.56729176274882 20 -55.4851374651805 30 0.0 0 VERTEX 5 1129 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -55.4851374651805 30 0.0 0 VERTEX 5 112A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -55.77077894460128 30 0.0 0 VERTEX 5 112B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -56.05642042402206 30 0.0 0 VERTEX 5 112C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -56.34206190344283 30 0.0 0 VERTEX 5 112D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -56.62770338286361 30 0.0 0 VERTEX 5 112E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -56.91334486228439 30 0.0 0 VERTEX 5 112F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -57.19898634170517 30 0.0 0 VERTEX 5 1130 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -57.48462782112594 30 0.0 0 VERTEX 5 1131 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.48043229282696 20 -57.77026930054672 30 0.0 0 VERTEX 5 1132 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.53604905306696 20 -57.77026930054672 30 0.0 0 VERTEX 5 1133 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.59166581330696 20 -57.77026930054672 30 0.0 0 VERTEX 5 1134 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.64728257354697 20 -57.77026930054672 30 0.0 0 VERTEX 5 1135 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.70289933378697 20 -57.77026930054672 30 0.0 0 VERTEX 5 1136 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.75851609402697 20 -57.77026930054672 30 0.0 0 VERTEX 5 1137 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.81413285426697 20 -57.77026930054672 30 0.0 0 VERTEX 5 1138 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.86974961450698 20 -57.77026930054672 30 0.0 0 VERTEX 5 1139 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -57.77026930054672 30 0.0 0 VERTEX 5 113A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -57.57706403936455 30 0.0 0 VERTEX 5 113B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -57.38385877818239 30 0.0 0 VERTEX 5 113C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -57.19065351700021 30 0.0 0 VERTEX 5 113D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -56.99744825581805 30 0.0 0 VERTEX 5 113E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -56.80424299463589 30 0.0 0 VERTEX 5 113F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -56.61103773345371 30 0.0 0 VERTEX 5 1140 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -56.41783247227155 30 0.0 0 VERTEX 5 1141 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92536637474698 20 -56.22462721108938 30 0.0 0 VERTEX 5 1142 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92534215141935 20 -56.20712922122728 30 0.0 0 VERTEX 5 1143 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92526948143646 20 -56.18796385897995 30 0.0 0 VERTEX 5 1144 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9251483647983 20 -56.1671270871261 30 0.0 0 VERTEX 5 1145 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92497880150488 20 -56.14461486844445 30 0.0 0 VERTEX 5 1146 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92476079155621 20 -56.12042316571375 30 0.0 0 VERTEX 5 1147 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92449433495227 20 -56.09454794171272 30 0.0 0 VERTEX 5 1148 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92417943169307 20 -56.06698515922009 30 0.0 0 VERTEX 5 1149 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92381608177861 20 -56.03773078101457 30 0.0 0 VERTEX 5 114A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92345273186416 20 -56.00860693963019 30 0.0 0 VERTEX 5 114B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92313782860495 20 -55.98118276840122 30 0.0 0 VERTEX 5 114C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92287137200102 20 -55.95546230454894 30 0.0 0 VERTEX 5 114D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92265336205234 20 -55.93144958529462 30 0.0 0 VERTEX 5 114E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92248379875893 20 -55.90914864785953 30 0.0 0 VERTEX 5 114F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92236268212077 20 -55.88856352946495 30 0.0 0 VERTEX 5 1150 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92229001213788 20 -55.86969826733215 30 0.0 0 VERTEX 5 1151 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.92226578881025 20 -55.85255689868239 30 0.0 0 VERTEX 5 1152 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.97600927838015 20 -56.09227094891543 30 0.0 0 VERTEX 5 1153 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02975276795005 20 -56.33198499914847 30 0.0 0 VERTEX 5 1154 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.08349625751994 20 -56.57169904938151 30 0.0 0 VERTEX 5 1155 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.13723974708984 20 -56.81141309961456 30 0.0 0 VERTEX 5 1156 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.19098323665974 20 -57.0511271498476 30 0.0 0 VERTEX 5 1157 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.24472672622964 20 -57.29084120008064 30 0.0 0 VERTEX 5 1158 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.29847021579953 20 -57.53055525031368 30 0.0 0 VERTEX 5 1159 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.35221370536943 20 -57.77026930054672 30 0.0 0 VERTEX 5 115A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.41022050060232 20 -57.77026930054672 30 0.0 0 VERTEX 5 115B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.46822729583522 20 -57.77026930054672 30 0.0 0 VERTEX 5 115C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.52623409106812 20 -57.77026930054672 30 0.0 0 VERTEX 5 115D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.58424088630101 20 -57.77026930054672 30 0.0 0 VERTEX 5 115E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.6422476815339 20 -57.77026930054672 30 0.0 0 VERTEX 5 115F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.7002544767668 20 -57.77026930054672 30 0.0 0 VERTEX 5 1160 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.75826127199969 20 -57.77026930054672 30 0.0 0 VERTEX 5 1161 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.81626806723258 20 -57.77026930054672 30 0.0 0 VERTEX 5 1162 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.87039913004457 20 -57.53055525031368 30 0.0 0 VERTEX 5 1163 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.92453019285656 20 -57.29084120008064 30 0.0 0 VERTEX 5 1164 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.97866125566855 20 -57.0511271498476 30 0.0 0 VERTEX 5 1165 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.03279231848054 20 -56.81141309961456 30 0.0 0 VERTEX 5 1166 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.08692338129253 20 -56.57169904938151 30 0.0 0 VERTEX 5 1167 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.14105444410451 20 -56.33198499914847 30 0.0 0 VERTEX 5 1168 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.1951855069165 20 -56.09227094891543 30 0.0 0 VERTEX 5 1169 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24931656972849 20 -55.85255689868239 30 0.0 0 VERTEX 5 116A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24929234640086 20 -55.86969826733215 30 0.0 0 VERTEX 5 116B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24921967641797 20 -55.88856352946495 30 0.0 0 VERTEX 5 116C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24909855977981 20 -55.90914864785953 30 0.0 0 VERTEX 5 116D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2489289964864 20 -55.93144958529462 30 0.0 0 VERTEX 5 116E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24871098653772 20 -55.95546230454894 30 0.0 0 VERTEX 5 116F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24844452993378 20 -55.98118276840122 30 0.0 0 VERTEX 5 1170 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24812962667459 20 -56.00860693963019 30 0.0 0 VERTEX 5 1171 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24776627676013 20 -56.03773078101457 30 0.0 0 VERTEX 5 1172 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24740292684567 20 -56.06698515922009 30 0.0 0 VERTEX 5 1173 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24708802358647 20 -56.09454794171272 30 0.0 0 VERTEX 5 1174 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24682156698253 20 -56.12042316571375 30 0.0 0 VERTEX 5 1175 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24660355703385 20 -56.14461486844445 30 0.0 0 VERTEX 5 1176 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24643399374044 20 -56.1671270871261 30 0.0 0 VERTEX 5 1177 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24631287710229 20 -56.18796385897995 30 0.0 0 VERTEX 5 1178 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2462402071194 20 -56.20712922122728 30 0.0 0 VERTEX 5 1179 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -56.22462721108938 30 0.0 0 VERTEX 5 117A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -56.41783247227155 30 0.0 0 VERTEX 5 117B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -56.61103773345371 30 0.0 0 VERTEX 5 117C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -56.80424299463589 30 0.0 0 VERTEX 5 117D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -56.99744825581805 30 0.0 0 VERTEX 5 117E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -57.19065351700021 30 0.0 0 VERTEX 5 117F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -57.38385877818239 30 0.0 0 VERTEX 5 1180 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -57.57706403936455 30 0.0 0 VERTEX 5 1181 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24621598379176 20 -57.77026930054672 30 0.0 0 VERTEX 5 1182 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.30183274403177 20 -57.77026930054672 30 0.0 0 VERTEX 5 1183 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.35744950427177 20 -57.77026930054672 30 0.0 0 VERTEX 5 1184 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.41306626451177 20 -57.77026930054672 30 0.0 0 VERTEX 5 1185 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.46868302475177 20 -57.77026930054672 30 0.0 0 VERTEX 5 1186 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.52429978499178 20 -57.77026930054672 30 0.0 0 VERTEX 5 1187 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.57991654523178 20 -57.77026930054672 30 0.0 0 VERTEX 5 1188 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.63553330547178 20 -57.77026930054672 30 0.0 0 VERTEX 5 1189 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -57.77026930054672 30 0.0 0 VERTEX 5 118A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -57.48462782112594 30 0.0 0 VERTEX 5 118B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -57.19898634170517 30 0.0 0 VERTEX 5 118C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -56.91334486228439 30 0.0 0 VERTEX 5 118D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -56.62770338286361 30 0.0 0 VERTEX 5 118E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -56.34206190344283 30 0.0 0 VERTEX 5 118F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -56.05642042402206 30 0.0 0 VERTEX 5 1190 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -55.77077894460128 30 0.0 0 VERTEX 5 1191 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69115006571178 20 -55.4851374651805 30 0.0 0 VERTEX 5 1192 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60525952889515 20 -55.4851374651805 30 0.0 0 VERTEX 5 1193 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.51936899207851 20 -55.4851374651805 30 0.0 0 VERTEX 5 1194 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.43347845526188 20 -55.4851374651805 30 0.0 0 VERTEX 5 1195 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.34758791844524 20 -55.4851374651805 30 0.0 0 VERTEX 5 1196 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2616973816286 20 -55.4851374651805 30 0.0 0 VERTEX 5 1197 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.17580684481197 20 -55.4851374651805 30 0.0 0 VERTEX 5 1198 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.08991630799533 20 -55.4851374651805 30 0.0 0 VERTEX 5 1199 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.0040257711787 20 -55.4851374651805 30 0.0 0 VERTEX 5 119A 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.95243546628708 20 -55.70973615897201 30 0.0 0 VERTEX 5 119B 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.90084516139547 20 -55.93433485276351 30 0.0 0 VERTEX 5 119C 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.84925485650385 20 -56.15893354655502 30 0.0 0 VERTEX 5 119D 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.79766455161224 20 -56.38353224034653 30 0.0 0 VERTEX 5 119E 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.74607424672062 20 -56.60813093413803 30 0.0 0 VERTEX 5 119F 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.694483941829 20 -56.83272962792955 30 0.0 0 VERTEX 5 11A0 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.64289363693739 20 -57.05732832172105 30 0.0 0 VERTEX 5 11A1 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59130333204577 20 -57.28192701551256 30 0.0 0 VERTEX 5 11A2 330 1118 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.59130333204577 20 -57.28192701551256 30 0.0 0 SEQEND 5 11A4 330 1118 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 11A3 330 1114 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 136 72 1 10 23.59130333204577 20 -57.28192701551256 11 23.53930392206528 21 -57.05732832172105 72 1 10 23.53930392206528 20 -57.05732832172105 11 23.48730451208479 21 -56.83272962792955 72 1 10 23.48730451208479 20 -56.83272962792955 11 23.4353051021043 21 -56.60813093413803 72 1 10 23.4353051021043 20 -56.60813093413803 11 23.38330569212381 21 -56.38353224034653 72 1 10 23.38330569212381 20 -56.38353224034653 11 23.33130628214332 21 -56.15893354655502 72 1 10 23.33130628214332 20 -56.15893354655502 11 23.27930687216283 21 -55.93433485276351 72 1 10 23.27930687216283 20 -55.93433485276351 11 23.22730746218234 21 -55.70973615897201 72 1 10 23.22730746218234 20 -55.70973615897201 11 23.17530805220185 21 -55.4851374651805 72 1 10 23.17530805220185 20 -55.4851374651805 11 23.08844858227999 21 -55.4851374651805 72 1 10 23.08844858227999 20 -55.4851374651805 11 23.00158911235813 21 -55.4851374651805 72 1 10 23.00158911235813 20 -55.4851374651805 11 22.91472964243627 21 -55.4851374651805 72 1 10 22.91472964243627 20 -55.4851374651805 11 22.82787017251441 21 -55.4851374651805 72 1 10 22.82787017251441 20 -55.4851374651805 11 22.74101070259254 21 -55.4851374651805 72 1 10 22.74101070259254 20 -55.4851374651805 11 22.65415123267068 21 -55.4851374651805 72 1 10 22.65415123267068 20 -55.4851374651805 11 22.56729176274882 21 -55.4851374651805 72 1 10 22.56729176274882 20 -55.4851374651805 11 22.48043229282696 21 -55.4851374651805 72 1 10 22.48043229282696 20 -55.4851374651805 11 22.48043229282696 21 -55.77077894460128 72 1 10 22.48043229282696 20 -55.77077894460128 11 22.48043229282696 21 -56.05642042402206 72 1 10 22.48043229282696 20 -56.05642042402206 11 22.48043229282696 21 -56.34206190344283 72 1 10 22.48043229282696 20 -56.34206190344283 11 22.48043229282696 21 -56.62770338286361 72 1 10 22.48043229282696 20 -56.62770338286361 11 22.48043229282696 21 -56.91334486228439 72 1 10 22.48043229282696 20 -56.91334486228439 11 22.48043229282696 21 -57.19898634170517 72 1 10 22.48043229282696 20 -57.19898634170517 11 22.48043229282696 21 -57.48462782112594 72 1 10 22.48043229282696 20 -57.48462782112594 11 22.48043229282696 21 -57.77026930054672 72 1 10 22.48043229282696 20 -57.77026930054672 11 22.53604905306696 21 -57.77026930054672 72 1 10 22.53604905306696 20 -57.77026930054672 11 22.59166581330696 21 -57.77026930054672 72 1 10 22.59166581330696 20 -57.77026930054672 11 22.64728257354697 21 -57.77026930054672 72 1 10 22.64728257354697 20 -57.77026930054672 11 22.70289933378697 21 -57.77026930054672 72 1 10 22.70289933378697 20 -57.77026930054672 11 22.75851609402697 21 -57.77026930054672 72 1 10 22.75851609402697 20 -57.77026930054672 11 22.81413285426697 21 -57.77026930054672 72 1 10 22.81413285426697 20 -57.77026930054672 11 22.86974961450698 21 -57.77026930054672 72 1 10 22.86974961450698 20 -57.77026930054672 11 22.92536637474698 21 -57.77026930054672 72 1 10 22.92536637474698 20 -57.77026930054672 11 22.92536637474698 21 -57.57706403936455 72 1 10 22.92536637474698 20 -57.57706403936455 11 22.92536637474698 21 -57.38385877818239 72 1 10 22.92536637474698 20 -57.38385877818239 11 22.92536637474698 21 -57.19065351700021 72 1 10 22.92536637474698 20 -57.19065351700021 11 22.92536637474698 21 -56.99744825581805 72 1 10 22.92536637474698 20 -56.99744825581805 11 22.92536637474698 21 -56.80424299463589 72 1 10 22.92536637474698 20 -56.80424299463589 11 22.92536637474698 21 -56.61103773345371 72 1 10 22.92536637474698 20 -56.61103773345371 11 22.92536637474698 21 -56.41783247227155 72 1 10 22.92536637474698 20 -56.41783247227155 11 22.92536637474698 21 -56.22462721108938 72 1 10 22.92536637474698 20 -56.22462721108938 11 22.92534215141935 21 -56.20712922122728 72 1 10 22.92534215141935 20 -56.20712922122728 11 22.92526948143646 21 -56.18796385897995 72 1 10 22.92526948143646 20 -56.18796385897995 11 22.9251483647983 21 -56.1671270871261 72 1 10 22.9251483647983 20 -56.1671270871261 11 22.92497880150488 21 -56.14461486844445 72 1 10 22.92497880150488 20 -56.14461486844445 11 22.92476079155621 21 -56.12042316571375 72 1 10 22.92476079155621 20 -56.12042316571375 11 22.92449433495227 21 -56.09454794171272 72 1 10 22.92449433495227 20 -56.09454794171272 11 22.92417943169307 21 -56.06698515922009 72 1 10 22.92417943169307 20 -56.06698515922009 11 22.92381608177861 21 -56.03773078101457 72 1 10 22.92381608177861 20 -56.03773078101457 11 22.92345273186416 21 -56.00860693963019 72 1 10 22.92345273186416 20 -56.00860693963019 11 22.92313782860495 21 -55.98118276840122 72 1 10 22.92313782860495 20 -55.98118276840122 11 22.92287137200102 21 -55.95546230454894 72 1 10 22.92287137200102 20 -55.95546230454894 11 22.92265336205234 21 -55.93144958529462 72 1 10 22.92265336205234 20 -55.93144958529462 11 22.92248379875893 21 -55.90914864785953 72 1 10 22.92248379875893 20 -55.90914864785953 11 22.92236268212077 21 -55.88856352946495 72 1 10 22.92236268212077 20 -55.88856352946495 11 22.92229001213788 21 -55.86969826733215 72 1 10 22.92229001213788 20 -55.86969826733215 11 22.92226578881025 21 -55.85255689868239 72 1 10 22.92226578881025 20 -55.85255689868239 11 22.97600927838015 21 -56.09227094891543 72 1 10 22.97600927838015 20 -56.09227094891543 11 23.02975276795005 21 -56.33198499914847 72 1 10 23.02975276795005 20 -56.33198499914847 11 23.08349625751994 21 -56.57169904938151 72 1 10 23.08349625751994 20 -56.57169904938151 11 23.13723974708984 21 -56.81141309961456 72 1 10 23.13723974708984 20 -56.81141309961456 11 23.19098323665974 21 -57.0511271498476 72 1 10 23.19098323665974 20 -57.0511271498476 11 23.24472672622964 21 -57.29084120008064 72 1 10 23.24472672622964 20 -57.29084120008064 11 23.29847021579953 21 -57.53055525031368 72 1 10 23.29847021579953 20 -57.53055525031368 11 23.35221370536943 21 -57.77026930054672 72 1 10 23.35221370536943 20 -57.77026930054672 11 23.41022050060232 21 -57.77026930054672 72 1 10 23.41022050060232 20 -57.77026930054672 11 23.46822729583522 21 -57.77026930054672 72 1 10 23.46822729583522 20 -57.77026930054672 11 23.52623409106812 21 -57.77026930054672 72 1 10 23.52623409106812 20 -57.77026930054672 11 23.58424088630101 21 -57.77026930054672 72 1 10 23.58424088630101 20 -57.77026930054672 11 23.6422476815339 21 -57.77026930054672 72 1 10 23.6422476815339 20 -57.77026930054672 11 23.7002544767668 21 -57.77026930054672 72 1 10 23.7002544767668 20 -57.77026930054672 11 23.75826127199969 21 -57.77026930054672 72 1 10 23.75826127199969 20 -57.77026930054672 11 23.81626806723258 21 -57.77026930054672 72 1 10 23.81626806723258 20 -57.77026930054672 11 23.87039913004457 21 -57.53055525031368 72 1 10 23.87039913004457 20 -57.53055525031368 11 23.92453019285656 21 -57.29084120008064 72 1 10 23.92453019285656 20 -57.29084120008064 11 23.97866125566855 21 -57.0511271498476 72 1 10 23.97866125566855 20 -57.0511271498476 11 24.03279231848054 21 -56.81141309961456 72 1 10 24.03279231848054 20 -56.81141309961456 11 24.08692338129253 21 -56.57169904938151 72 1 10 24.08692338129253 20 -56.57169904938151 11 24.14105444410451 21 -56.33198499914847 72 1 10 24.14105444410451 20 -56.33198499914847 11 24.1951855069165 21 -56.09227094891543 72 1 10 24.1951855069165 20 -56.09227094891543 11 24.24931656972849 21 -55.85255689868239 72 1 10 24.24931656972849 20 -55.85255689868239 11 24.24929234640086 21 -55.86969826733215 72 1 10 24.24929234640086 20 -55.86969826733215 11 24.24921967641797 21 -55.88856352946495 72 1 10 24.24921967641797 20 -55.88856352946495 11 24.24909855977981 21 -55.90914864785953 72 1 10 24.24909855977981 20 -55.90914864785953 11 24.2489289964864 21 -55.93144958529462 72 1 10 24.2489289964864 20 -55.93144958529462 11 24.24871098653772 21 -55.95546230454894 72 1 10 24.24871098653772 20 -55.95546230454894 11 24.24844452993378 21 -55.98118276840122 72 1 10 24.24844452993378 20 -55.98118276840122 11 24.24812962667459 21 -56.00860693963019 72 1 10 24.24812962667459 20 -56.00860693963019 11 24.24776627676013 21 -56.03773078101457 72 1 10 24.24776627676013 20 -56.03773078101457 11 24.24740292684567 21 -56.06698515922009 72 1 10 24.24740292684567 20 -56.06698515922009 11 24.24708802358647 21 -56.09454794171272 72 1 10 24.24708802358647 20 -56.09454794171272 11 24.24682156698253 21 -56.12042316571375 72 1 10 24.24682156698253 20 -56.12042316571375 11 24.24660355703385 21 -56.14461486844445 72 1 10 24.24660355703385 20 -56.14461486844445 11 24.24643399374044 21 -56.1671270871261 72 1 10 24.24643399374044 20 -56.1671270871261 11 24.24631287710229 21 -56.18796385897995 72 1 10 24.24631287710229 20 -56.18796385897995 11 24.2462402071194 21 -56.20712922122728 72 1 10 24.2462402071194 20 -56.20712922122728 11 24.24621598379176 21 -56.22462721108938 72 1 10 24.24621598379176 20 -56.22462721108938 11 24.24621598379176 21 -56.41783247227155 72 1 10 24.24621598379176 20 -56.41783247227155 11 24.24621598379176 21 -56.61103773345371 72 1 10 24.24621598379176 20 -56.61103773345371 11 24.24621598379176 21 -56.80424299463589 72 1 10 24.24621598379176 20 -56.80424299463589 11 24.24621598379176 21 -56.99744825581805 72 1 10 24.24621598379176 20 -56.99744825581805 11 24.24621598379176 21 -57.19065351700021 72 1 10 24.24621598379176 20 -57.19065351700021 11 24.24621598379176 21 -57.38385877818239 72 1 10 24.24621598379176 20 -57.38385877818239 11 24.24621598379176 21 -57.57706403936455 72 1 10 24.24621598379176 20 -57.57706403936455 11 24.24621598379176 21 -57.77026930054672 72 1 10 24.24621598379176 20 -57.77026930054672 11 24.30183274403177 21 -57.77026930054672 72 1 10 24.30183274403177 20 -57.77026930054672 11 24.35744950427177 21 -57.77026930054672 72 1 10 24.35744950427177 20 -57.77026930054672 11 24.41306626451177 21 -57.77026930054672 72 1 10 24.41306626451177 20 -57.77026930054672 11 24.46868302475177 21 -57.77026930054672 72 1 10 24.46868302475177 20 -57.77026930054672 11 24.52429978499178 21 -57.77026930054672 72 1 10 24.52429978499178 20 -57.77026930054672 11 24.57991654523178 21 -57.77026930054672 72 1 10 24.57991654523178 20 -57.77026930054672 11 24.63553330547178 21 -57.77026930054672 72 1 10 24.63553330547178 20 -57.77026930054672 11 24.69115006571178 21 -57.77026930054672 72 1 10 24.69115006571178 20 -57.77026930054672 11 24.69115006571178 21 -57.48462782112594 72 1 10 24.69115006571178 20 -57.48462782112594 11 24.69115006571178 21 -57.19898634170517 72 1 10 24.69115006571178 20 -57.19898634170517 11 24.69115006571178 21 -56.91334486228439 72 1 10 24.69115006571178 20 -56.91334486228439 11 24.69115006571178 21 -56.62770338286361 72 1 10 24.69115006571178 20 -56.62770338286361 11 24.69115006571178 21 -56.34206190344283 72 1 10 24.69115006571178 20 -56.34206190344283 11 24.69115006571178 21 -56.05642042402206 72 1 10 24.69115006571178 20 -56.05642042402206 11 24.69115006571178 21 -55.77077894460128 72 1 10 24.69115006571178 20 -55.77077894460128 11 24.69115006571178 21 -55.4851374651805 72 1 10 24.69115006571178 20 -55.4851374651805 11 24.60525952889515 21 -55.4851374651805 72 1 10 24.60525952889515 20 -55.4851374651805 11 24.51936899207851 21 -55.4851374651805 72 1 10 24.51936899207851 20 -55.4851374651805 11 24.43347845526188 21 -55.4851374651805 72 1 10 24.43347845526188 20 -55.4851374651805 11 24.34758791844524 21 -55.4851374651805 72 1 10 24.34758791844524 20 -55.4851374651805 11 24.2616973816286 21 -55.4851374651805 72 1 10 24.2616973816286 20 -55.4851374651805 11 24.17580684481197 21 -55.4851374651805 72 1 10 24.17580684481197 20 -55.4851374651805 11 24.08991630799533 21 -55.4851374651805 72 1 10 24.08991630799533 20 -55.4851374651805 11 24.0040257711787 21 -55.4851374651805 72 1 10 24.0040257711787 20 -55.4851374651805 11 23.95243546628708 21 -55.70973615897201 72 1 10 23.95243546628708 20 -55.70973615897201 11 23.90084516139547 21 -55.93433485276351 72 1 10 23.90084516139547 20 -55.93433485276351 11 23.84925485650385 21 -56.15893354655502 72 1 10 23.84925485650385 20 -56.15893354655502 11 23.79766455161224 21 -56.38353224034653 72 1 10 23.79766455161224 20 -56.38353224034653 11 23.74607424672062 21 -56.60813093413803 72 1 10 23.74607424672062 20 -56.60813093413803 11 23.694483941829 21 -56.83272962792955 72 1 10 23.694483941829 20 -56.83272962792955 11 23.64289363693739 21 -57.05732832172105 72 1 10 23.64289363693739 20 -57.05732832172105 11 23.59130333204577 21 -57.28192701551256 97 0 75 2 76 1 98 0 0 POLYLINE 5 11A5 330 1114 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 11A6 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -57.77026930054672 30 0.0 0 VERTEX 5 11A7 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.60806596028724 20 -57.77026930054672 30 0.0 0 VERTEX 5 11A8 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.6673646663271 20 -57.77026930054672 30 0.0 0 VERTEX 5 11A9 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.72666337236696 20 -57.77026930054672 30 0.0 0 VERTEX 5 11AA 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.78596207840683 20 -57.77026930054672 30 0.0 0 VERTEX 5 11AB 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.84526078444669 20 -57.77026930054672 30 0.0 0 VERTEX 5 11AC 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.90455949048655 20 -57.77026930054672 30 0.0 0 VERTEX 5 11AD 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.96385819652642 20 -57.77026930054672 30 0.0 0 VERTEX 5 11AE 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -57.77026930054672 30 0.0 0 VERTEX 5 11AF 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -57.65050916874072 30 0.0 0 VERTEX 5 11B0 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -57.53074903693472 30 0.0 0 VERTEX 5 11B1 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -57.41098890512873 30 0.0 0 VERTEX 5 11B2 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -57.29122877332273 30 0.0 0 VERTEX 5 11B3 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -57.17146864151673 30 0.0 0 VERTEX 5 11B4 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -57.05170850971074 30 0.0 0 VERTEX 5 11B5 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.93194837790474 30 0.0 0 VERTEX 5 11B6 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.81218824609874 30 0.0 0 VERTEX 5 11B7 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.14969956610886 20 -56.81218824609874 30 0.0 0 VERTEX 5 11B8 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.27624222965144 20 -56.81218824609874 30 0.0 0 VERTEX 5 11B9 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.40278489319403 20 -56.81218824609874 30 0.0 0 VERTEX 5 11BA 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.52932755673661 20 -56.81218824609874 30 0.0 0 VERTEX 5 11BB 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.65587022027919 20 -56.81218824609874 30 0.0 0 VERTEX 5 11BC 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.78241288382178 20 -56.81218824609874 30 0.0 0 VERTEX 5 11BD 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.90895554736436 20 -56.81218824609874 30 0.0 0 VERTEX 5 11BE 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.81218824609874 30 0.0 0 VERTEX 5 11BF 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.76257887111115 30 0.0 0 VERTEX 5 11C0 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.71296949612354 30 0.0 0 VERTEX 5 11C1 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.66336012113594 30 0.0 0 VERTEX 5 11C2 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.61375074614835 30 0.0 0 VERTEX 5 11C3 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.56414137116075 30 0.0 0 VERTEX 5 11C4 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.51453199617315 30 0.0 0 VERTEX 5 11C5 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.46492262118556 30 0.0 0 VERTEX 5 11C6 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03549821090694 20 -56.41531324619796 30 0.0 0 VERTEX 5 11C7 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.90895554736436 20 -56.41531324619796 30 0.0 0 VERTEX 5 11C8 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.78241288382178 20 -56.41531324619796 30 0.0 0 VERTEX 5 11C9 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.65587022027919 20 -56.41531324619796 30 0.0 0 VERTEX 5 11CA 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.52932755673661 20 -56.41531324619796 30 0.0 0 VERTEX 5 11CB 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.40278489319403 20 -56.41531324619796 30 0.0 0 VERTEX 5 11CC 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.27624222965144 20 -56.41531324619796 30 0.0 0 VERTEX 5 11CD 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.14969956610886 20 -56.41531324619796 30 0.0 0 VERTEX 5 11CE 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.41531324619796 30 0.0 0 VERTEX 5 11CF 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.3496195816636 30 0.0 0 VERTEX 5 11D0 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.28392591712925 30 0.0 0 VERTEX 5 11D1 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.21823225259489 30 0.0 0 VERTEX 5 11D2 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.15253858806053 30 0.0 0 VERTEX 5 11D3 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.08684492352617 30 0.0 0 VERTEX 5 11D4 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -56.02115125899181 30 0.0 0 VERTEX 5 11D5 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -55.95545759445746 30 0.0 0 VERTEX 5 11D6 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.02315690256628 20 -55.8897639299231 30 0.0 0 VERTEX 5 11D7 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.16752793524503 20 -55.8897639299231 30 0.0 0 VERTEX 5 11D8 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.31189896792378 20 -55.8897639299231 30 0.0 0 VERTEX 5 11D9 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.45627000060253 20 -55.8897639299231 30 0.0 0 VERTEX 5 11DA 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.60064103328128 20 -55.8897639299231 30 0.0 0 VERTEX 5 11DB 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.74501206596003 20 -55.8897639299231 30 0.0 0 VERTEX 5 11DC 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.88938309863878 20 -55.8897639299231 30 0.0 0 VERTEX 5 11DD 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.03375413131754 20 -55.8897639299231 30 0.0 0 VERTEX 5 11DE 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.8897639299231 30 0.0 0 VERTEX 5 11DF 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.83957319507236 30 0.0 0 VERTEX 5 11E0 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.78938246022163 30 0.0 0 VERTEX 5 11E1 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.73919172537089 30 0.0 0 VERTEX 5 11E2 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.68900099052016 30 0.0 0 VERTEX 5 11E3 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.63881025566943 30 0.0 0 VERTEX 5 11E4 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.5886195208187 30 0.0 0 VERTEX 5 11E5 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.53842878596796 30 0.0 0 VERTEX 5 11E6 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.17812516399629 20 -55.48823805111723 30 0.0 0 VERTEX 5 11E7 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.97445542527767 20 -55.48823805111723 30 0.0 0 VERTEX 5 11E8 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.77078568655906 20 -55.48823805111723 30 0.0 0 VERTEX 5 11E9 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.56711594784045 20 -55.48823805111723 30 0.0 0 VERTEX 5 11EA 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.36344620912183 20 -55.48823805111723 30 0.0 0 VERTEX 5 11EB 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.15977647040322 20 -55.48823805111723 30 0.0 0 VERTEX 5 11EC 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.9561067316846 20 -55.48823805111723 30 0.0 0 VERTEX 5 11ED 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.75243699296599 20 -55.48823805111723 30 0.0 0 VERTEX 5 11EE 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -55.48823805111723 30 0.0 0 VERTEX 5 11EF 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -55.77349195729592 30 0.0 0 VERTEX 5 11F0 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -56.0587458634746 30 0.0 0 VERTEX 5 11F1 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -56.34399976965329 30 0.0 0 VERTEX 5 11F2 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -56.62925367583198 30 0.0 0 VERTEX 5 11F3 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -56.91450758201066 30 0.0 0 VERTEX 5 11F4 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -57.19976148818935 30 0.0 0 VERTEX 5 11F5 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -57.48501539436803 30 0.0 0 VERTEX 5 11F6 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -57.77026930054672 30 0.0 0 VERTEX 5 11F7 330 11A5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54876725424738 20 -57.77026930054672 30 0.0 0 SEQEND 5 11F9 330 11A5 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 11F8 330 1114 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 80 72 1 10 20.54876725424738 20 -57.77026930054672 11 20.60806596028724 21 -57.77026930054672 72 1 10 20.60806596028724 20 -57.77026930054672 11 20.6673646663271 21 -57.77026930054672 72 1 10 20.6673646663271 20 -57.77026930054672 11 20.72666337236696 21 -57.77026930054672 72 1 10 20.72666337236696 20 -57.77026930054672 11 20.78596207840683 21 -57.77026930054672 72 1 10 20.78596207840683 20 -57.77026930054672 11 20.84526078444669 21 -57.77026930054672 72 1 10 20.84526078444669 20 -57.77026930054672 11 20.90455949048655 21 -57.77026930054672 72 1 10 20.90455949048655 20 -57.77026930054672 11 20.96385819652642 21 -57.77026930054672 72 1 10 20.96385819652642 20 -57.77026930054672 11 21.02315690256628 21 -57.77026930054672 72 1 10 21.02315690256628 20 -57.77026930054672 11 21.02315690256628 21 -57.65050916874072 72 1 10 21.02315690256628 20 -57.65050916874072 11 21.02315690256628 21 -57.53074903693472 72 1 10 21.02315690256628 20 -57.53074903693472 11 21.02315690256628 21 -57.41098890512873 72 1 10 21.02315690256628 20 -57.41098890512873 11 21.02315690256628 21 -57.29122877332273 72 1 10 21.02315690256628 20 -57.29122877332273 11 21.02315690256628 21 -57.17146864151673 72 1 10 21.02315690256628 20 -57.17146864151673 11 21.02315690256628 21 -57.05170850971074 72 1 10 21.02315690256628 20 -57.05170850971074 11 21.02315690256628 21 -56.93194837790474 72 1 10 21.02315690256628 20 -56.93194837790474 11 21.02315690256628 21 -56.81218824609874 72 1 10 21.02315690256628 20 -56.81218824609874 11 21.14969956610886 21 -56.81218824609874 72 1 10 21.14969956610886 20 -56.81218824609874 11 21.27624222965144 21 -56.81218824609874 72 1 10 21.27624222965144 20 -56.81218824609874 11 21.40278489319403 21 -56.81218824609874 72 1 10 21.40278489319403 20 -56.81218824609874 11 21.52932755673661 21 -56.81218824609874 72 1 10 21.52932755673661 20 -56.81218824609874 11 21.65587022027919 21 -56.81218824609874 72 1 10 21.65587022027919 20 -56.81218824609874 11 21.78241288382178 21 -56.81218824609874 72 1 10 21.78241288382178 20 -56.81218824609874 11 21.90895554736436 21 -56.81218824609874 72 1 10 21.90895554736436 20 -56.81218824609874 11 22.03549821090694 21 -56.81218824609874 72 1 10 22.03549821090694 20 -56.81218824609874 11 22.03549821090694 21 -56.76257887111115 72 1 10 22.03549821090694 20 -56.76257887111115 11 22.03549821090694 21 -56.71296949612354 72 1 10 22.03549821090694 20 -56.71296949612354 11 22.03549821090694 21 -56.66336012113594 72 1 10 22.03549821090694 20 -56.66336012113594 11 22.03549821090694 21 -56.61375074614835 72 1 10 22.03549821090694 20 -56.61375074614835 11 22.03549821090694 21 -56.56414137116075 72 1 10 22.03549821090694 20 -56.56414137116075 11 22.03549821090694 21 -56.51453199617315 72 1 10 22.03549821090694 20 -56.51453199617315 11 22.03549821090694 21 -56.46492262118556 72 1 10 22.03549821090694 20 -56.46492262118556 11 22.03549821090694 21 -56.41531324619796 72 1 10 22.03549821090694 20 -56.41531324619796 11 21.90895554736436 21 -56.41531324619796 72 1 10 21.90895554736436 20 -56.41531324619796 11 21.78241288382178 21 -56.41531324619796 72 1 10 21.78241288382178 20 -56.41531324619796 11 21.65587022027919 21 -56.41531324619796 72 1 10 21.65587022027919 20 -56.41531324619796 11 21.52932755673661 21 -56.41531324619796 72 1 10 21.52932755673661 20 -56.41531324619796 11 21.40278489319403 21 -56.41531324619796 72 1 10 21.40278489319403 20 -56.41531324619796 11 21.27624222965144 21 -56.41531324619796 72 1 10 21.27624222965144 20 -56.41531324619796 11 21.14969956610886 21 -56.41531324619796 72 1 10 21.14969956610886 20 -56.41531324619796 11 21.02315690256628 21 -56.41531324619796 72 1 10 21.02315690256628 20 -56.41531324619796 11 21.02315690256628 21 -56.3496195816636 72 1 10 21.02315690256628 20 -56.3496195816636 11 21.02315690256628 21 -56.28392591712925 72 1 10 21.02315690256628 20 -56.28392591712925 11 21.02315690256628 21 -56.21823225259489 72 1 10 21.02315690256628 20 -56.21823225259489 11 21.02315690256628 21 -56.15253858806053 72 1 10 21.02315690256628 20 -56.15253858806053 11 21.02315690256628 21 -56.08684492352617 72 1 10 21.02315690256628 20 -56.08684492352617 11 21.02315690256628 21 -56.02115125899181 72 1 10 21.02315690256628 20 -56.02115125899181 11 21.02315690256628 21 -55.95545759445746 72 1 10 21.02315690256628 20 -55.95545759445746 11 21.02315690256628 21 -55.8897639299231 72 1 10 21.02315690256628 20 -55.8897639299231 11 21.16752793524503 21 -55.8897639299231 72 1 10 21.16752793524503 20 -55.8897639299231 11 21.31189896792378 21 -55.8897639299231 72 1 10 21.31189896792378 20 -55.8897639299231 11 21.45627000060253 21 -55.8897639299231 72 1 10 21.45627000060253 20 -55.8897639299231 11 21.60064103328128 21 -55.8897639299231 72 1 10 21.60064103328128 20 -55.8897639299231 11 21.74501206596003 21 -55.8897639299231 72 1 10 21.74501206596003 20 -55.8897639299231 11 21.88938309863878 21 -55.8897639299231 72 1 10 21.88938309863878 20 -55.8897639299231 11 22.03375413131754 21 -55.8897639299231 72 1 10 22.03375413131754 20 -55.8897639299231 11 22.17812516399629 21 -55.8897639299231 72 1 10 22.17812516399629 20 -55.8897639299231 11 22.17812516399629 21 -55.83957319507236 72 1 10 22.17812516399629 20 -55.83957319507236 11 22.17812516399629 21 -55.78938246022163 72 1 10 22.17812516399629 20 -55.78938246022163 11 22.17812516399629 21 -55.73919172537089 72 1 10 22.17812516399629 20 -55.73919172537089 11 22.17812516399629 21 -55.68900099052016 72 1 10 22.17812516399629 20 -55.68900099052016 11 22.17812516399629 21 -55.63881025566943 72 1 10 22.17812516399629 20 -55.63881025566943 11 22.17812516399629 21 -55.5886195208187 72 1 10 22.17812516399629 20 -55.5886195208187 11 22.17812516399629 21 -55.53842878596796 72 1 10 22.17812516399629 20 -55.53842878596796 11 22.17812516399629 21 -55.48823805111723 72 1 10 22.17812516399629 20 -55.48823805111723 11 21.97445542527767 21 -55.48823805111723 72 1 10 21.97445542527767 20 -55.48823805111723 11 21.77078568655906 21 -55.48823805111723 72 1 10 21.77078568655906 20 -55.48823805111723 11 21.56711594784045 21 -55.48823805111723 72 1 10 21.56711594784045 20 -55.48823805111723 11 21.36344620912183 21 -55.48823805111723 72 1 10 21.36344620912183 20 -55.48823805111723 11 21.15977647040322 21 -55.48823805111723 72 1 10 21.15977647040322 20 -55.48823805111723 11 20.9561067316846 21 -55.48823805111723 72 1 10 20.9561067316846 20 -55.48823805111723 11 20.75243699296599 21 -55.48823805111723 72 1 10 20.75243699296599 20 -55.48823805111723 11 20.54876725424738 21 -55.48823805111723 72 1 10 20.54876725424738 20 -55.48823805111723 11 20.54876725424738 21 -55.77349195729592 72 1 10 20.54876725424738 20 -55.77349195729592 11 20.54876725424738 21 -56.0587458634746 72 1 10 20.54876725424738 20 -56.0587458634746 11 20.54876725424738 21 -56.34399976965329 72 1 10 20.54876725424738 20 -56.34399976965329 11 20.54876725424738 21 -56.62925367583198 72 1 10 20.54876725424738 20 -56.62925367583198 11 20.54876725424738 21 -56.91450758201066 72 1 10 20.54876725424738 20 -56.91450758201066 11 20.54876725424738 21 -57.19976148818935 72 1 10 20.54876725424738 20 -57.19976148818935 11 20.54876725424738 21 -57.48501539436803 72 1 10 20.54876725424738 20 -57.48501539436803 11 20.54876725424738 21 -57.77026930054672 97 0 75 2 76 1 98 0 0 ENDBLK 5 1117 330 1114 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 BLOCK 5 11FC 330 11FA 100 AcDbEntity 8 0 100 AcDbBlockBegin 2 block 8 70 0 10 0.0 20 0.0 30 0.0 3 block 8 1 0 POLYLINE 5 11FE 330 11FA 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 11FF 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.81155122813832 20 -40.24513746899024 30 0.0 0 VERTEX 5 1200 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.81155122813832 20 -40.64976393373284 30 0.0 0 VERTEX 5 1201 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.12787202909049 20 -40.64976393373284 30 0.0 0 VERTEX 5 1202 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.12787202909049 20 -42.53026930435646 30 0.0 0 VERTEX 5 1203 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.64728120889813 20 -42.53026930435646 30 0.0 0 VERTEX 5 1204 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.64728120889813 20 -40.64976393373284 30 0.0 0 VERTEX 5 1205 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.96050142391358 20 -40.64976393373284 30 0.0 0 VERTEX 5 1206 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.96050142391358 20 -40.24513746899024 30 0.0 0 VERTEX 5 1207 330 11FE 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.81155122813832 20 -40.24513746899024 30 0.0 0 SEQEND 5 1208 330 11FE 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 1209 330 11FA 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 8 72 1 10 20.81155122813832 20 -40.24513746899024 11 20.81155122813832 21 -40.64976393373284 72 1 10 20.81155122813832 20 -40.64976393373284 11 20.12787202909049 21 -40.64976393373284 72 1 10 20.12787202909049 20 -40.64976393373284 11 20.12787202909049 21 -42.53026930435646 72 1 10 20.12787202909049 20 -42.53026930435646 11 19.64728120889813 21 -42.53026930435646 72 1 10 19.64728120889813 20 -42.53026930435646 11 19.64728120889813 21 -40.64976393373284 72 1 10 19.64728120889813 20 -40.64976393373284 11 18.96050142391358 21 -40.64976393373284 72 1 10 18.96050142391358 20 -40.64976393373284 11 18.96050142391358 21 -40.24513746899024 72 1 10 18.96050142391358 20 -40.24513746899024 11 20.81155122813832 21 -40.24513746899024 97 0 75 2 76 1 98 0 0 SPLINE 5 120A 330 11FA 100 AcDbEntity 8 Graphics 370 0 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 74 73 70 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 8.0 40 8.0 40 8.0 40 9.0 40 9.0 40 9.0 40 10.0 40 10.0 40 10.0 40 11.0 40 11.0 40 11.0 40 12.0 40 12.0 40 12.0 40 13.0 40 13.0 40 13.0 40 14.0 40 14.0 40 14.0 40 15.0 40 15.0 40 15.0 40 16.0 40 16.0 40 16.0 40 17.0 40 17.0 40 17.0 40 18.0 40 18.0 40 18.0 40 19.0 40 19.0 40 19.0 40 20.0 40 20.0 40 20.0 40 21.0 40 21.0 40 21.0 40 22.0 40 22.0 40 22.0 40 23.0 40 23.0 40 23.0 40 23.0 10 22.554941798449 20 -40.30404860178802 30 0.0 10 22.63917438306335 20 -40.34022210438314 30 0.0 10 22.71048785960803 20 -40.39344882963025 30 0.0 10 22.76888222808301 20 -40.46372877752935 30 0.0 10 22.81728581965077 20 -40.52160638168154 30 0.0 10 22.85552637953704 20 -40.58568515770719 30 0.0 10 22.88377616251609 20 -40.65596510560628 30 0.0 10 22.91202594549514 20 -40.72624505350539 30 0.0 10 22.92615083698466 20 -40.80634352353744 30 0.0 10 22.92615083698466 20 -40.89626051570247 30 0.0 10 22.92615083698466 20 -41.00478102348784 30 0.0 10 22.89876232787693 20 -41.11157898353058 30 0.0 10 22.84398530966146 20 -41.21630988628218 30 0.0 10 22.78920829144598 20 -41.32138529858229 30 0.0 10 22.69877453495818 20 -41.39545485151517 30 0.0 10 22.57268404019803 20 -41.43886305462932 30 0.0 10 22.67810396204668 20 -41.48123772909788 30 0.0 10 22.75269027930234 20 -41.54152690008976 30 0.0 10 22.79661524673927 20 -41.61938605805641 30 0.0 10 22.84054021417621 20 -41.69758972557158 30 0.0 10 22.8625888252818 20 -41.81661777458696 30 0.0 10 22.8625888252818 20 -41.97681471465108 30 0.0 10 22.8625888252818 20 -41.97681471465108 30 0.0 10 22.8625888252818 20 -42.13029371851896 30 0.0 10 22.8625888252818 20 -42.13029371851896 30 0.0 10 22.8625888252818 20 -42.23468011172203 30 0.0 10 22.8667229398641 20 -42.30547682394391 30 0.0 10 22.87516342380297 20 -42.34268385518461 30 0.0 10 22.88773802232413 20 -42.40159498798238 30 0.0 10 22.91719358872302 20 -42.44500319109653 30 0.0 10 22.96335786822536 20 -42.47290846452705 30 0.0 10 22.96335786822536 20 -42.47290846452705 30 0.0 10 22.96335786822536 20 -42.53026930435646 30 0.0 10 22.96335786822536 20 -42.53026930435646 30 0.0 10 22.96335786822536 20 -42.53026930435646 30 0.0 10 22.43625825898214 20 -42.53026930435646 30 0.0 10 22.43625825898214 20 -42.53026930435646 30 0.0 10 22.42178885794409 20 -42.47962640072329 30 0.0 10 22.41145357148834 20 -42.43880201922308 30 0.0 10 22.40525239961489 20 -42.40779615985583 30 0.0 10 22.39285005586799 20 -42.34371738383018 30 0.0 10 22.38613211967175 20 -42.27808831483618 30 0.0 10 22.38509859102618 20 -42.2109089528738 30 0.0 10 22.38509859102618 20 -42.2109089528738 30 0.0 10 22.38199800508945 20 -41.99851881620815 30 0.0 10 22.38199800508945 20 -41.99851881620815 30 0.0 10 22.38010320257257 20 -41.85279127718208 30 0.0 10 22.35495400553024 20 -41.75563958449803 30 0.0 10 22.30655041396248 20 -41.70706373815602 30 0.0 10 22.25814682239472 20 -41.65848789181399 30 0.0 10 22.16736855635839 20 -41.63419996864298 30 0.0 10 22.03438787062775 20 -41.63419996864298 30 0.0 10 22.03438787062775 20 -41.63419996864298 30 0.0 10 21.56809419669918 20 -41.63419996864298 30 0.0 10 21.56809419669918 20 -41.63419996864298 30 0.0 10 21.56809419669918 20 -41.63419996864298 30 0.0 10 21.56809419669918 20 -42.53026930435646 30 0.0 10 21.56809419669918 20 -42.53026930435646 30 0.0 10 21.56809419669918 20 -42.53026930435646 30 0.0 10 21.10145601322209 20 -42.53026930435646 30 0.0 10 21.10145601322209 20 -42.53026930435646 30 0.0 10 21.10145601322209 20 -42.53026930435646 30 0.0 10 21.10145601322209 20 -40.24513746899024 30 0.0 10 21.10145601322209 20 -40.24513746899024 30 0.0 10 21.10145601322209 20 -40.24513746899024 30 0.0 10 22.1944125559176 20 -40.24513746899024 30 0.0 10 22.1944125559176 20 -40.24513746899024 30 0.0 10 22.35064763617368 20 -40.24823805492697 30 0.0 10 22.4708814686089 20 -40.26787509919289 30 0.0 10 22.554941798449 20 -40.30404860178802 30 0.0 0 SPLINE 5 120B 330 11FA 100 AcDbEntity 8 Graphics 370 0 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 26 73 22 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 7.0 10 21.56809419669918 20 -40.64201246889102 30 0.0 10 21.56809419669918 20 -40.64201246889102 30 0.0 10 21.56809419669918 20 -41.25592848436255 30 0.0 10 21.56809419669918 20 -41.25592848436255 30 0.0 10 21.56809419669918 20 -41.25592848436255 30 0.0 10 22.08193018832419 20 -41.25592848436255 30 0.0 10 22.08193018832419 20 -41.25592848436255 30 0.0 10 22.18407726946185 20 -41.25592848436255 30 0.0 10 22.2605583892344 20 -41.24352614061565 30 0.0 10 22.31171805719036 20 -41.21872145312185 30 0.0 10 22.4019795589039 20 -41.1753132500077 30 0.0 10 22.44711030976067 20 -41.08953037242498 30 0.0 10 22.44711030976067 20 -40.96137282037368 30 0.0 10 22.44711030976067 20 -40.82287998186664 30 0.0 10 22.403357597098 20 -40.7298624037649 30 0.0 10 22.31602442654692 20 -40.68232008606845 30 0.0 10 22.26693181588211 20 -40.6554483412835 30 0.0 10 22.19337902727203 20 -40.64201246889102 30 0.0 10 22.0951938059424 20 -40.64201246889102 30 0.0 10 22.0951938059424 20 -40.64201246889102 30 0.0 10 21.56809419669918 20 -40.64201246889102 30 0.0 10 21.56809419669918 20 -40.64201246889102 30 0.0 0 HATCH 5 120C 330 11FA 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 1 72 4 94 3 73 0 74 1 95 74 96 70 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 8.0 40 8.0 40 8.0 40 9.0 40 9.0 40 9.0 40 10.0 40 10.0 40 10.0 40 11.0 40 11.0 40 11.0 40 12.0 40 12.0 40 12.0 40 13.0 40 13.0 40 13.0 40 14.0 40 14.0 40 14.0 40 15.0 40 15.0 40 15.0 40 16.0 40 16.0 40 16.0 40 17.0 40 17.0 40 17.0 40 18.0 40 18.0 40 18.0 40 19.0 40 19.0 40 19.0 40 20.0 40 20.0 40 20.0 40 21.0 40 21.0 40 21.0 40 22.0 40 22.0 40 22.0 40 23.0 40 23.0 40 23.0 40 23.0 10 22.554941798449 20 -40.30404860178802 10 22.63917438306335 20 -40.34022210438314 10 22.71048785960803 20 -40.39344882963025 10 22.76888222808301 20 -40.46372877752935 10 22.81728581965077 20 -40.52160638168154 10 22.85552637953704 20 -40.58568515770719 10 22.88377616251609 20 -40.65596510560628 10 22.91202594549514 20 -40.72624505350539 10 22.92615083698466 20 -40.80634352353744 10 22.92615083698466 20 -40.89626051570247 10 22.92615083698466 20 -41.00478102348784 10 22.89876232787693 20 -41.11157898353058 10 22.84398530966146 20 -41.21630988628218 10 22.78920829144598 20 -41.32138529858229 10 22.69877453495818 20 -41.39545485151517 10 22.57268404019803 20 -41.43886305462932 10 22.67810396204668 20 -41.48123772909788 10 22.75269027930234 20 -41.54152690008976 10 22.79661524673927 20 -41.61938605805641 10 22.84054021417621 20 -41.69758972557158 10 22.8625888252818 20 -41.81661777458696 10 22.8625888252818 20 -41.97681471465108 10 22.8625888252818 20 -41.97681471465108 10 22.8625888252818 20 -42.13029371851896 10 22.8625888252818 20 -42.13029371851896 10 22.8625888252818 20 -42.23468011172203 10 22.8667229398641 20 -42.30547682394391 10 22.87516342380297 20 -42.34268385518461 10 22.88773802232413 20 -42.40159498798238 10 22.91719358872302 20 -42.44500319109653 10 22.96335786822536 20 -42.47290846452705 10 22.96335786822536 20 -42.47290846452705 10 22.96335786822536 20 -42.53026930435646 10 22.96335786822536 20 -42.53026930435646 10 22.96335786822536 20 -42.53026930435646 10 22.43625825898214 20 -42.53026930435646 10 22.43625825898214 20 -42.53026930435646 10 22.42178885794409 20 -42.47962640072329 10 22.41145357148834 20 -42.43880201922308 10 22.40525239961489 20 -42.40779615985583 10 22.39285005586799 20 -42.34371738383018 10 22.38613211967175 20 -42.27808831483618 10 22.38509859102618 20 -42.2109089528738 10 22.38509859102618 20 -42.2109089528738 10 22.38199800508945 20 -41.99851881620815 10 22.38199800508945 20 -41.99851881620815 10 22.38010320257257 20 -41.85279127718208 10 22.35495400553024 20 -41.75563958449803 10 22.30655041396248 20 -41.70706373815602 10 22.25814682239472 20 -41.65848789181399 10 22.16736855635839 20 -41.63419996864298 10 22.03438787062775 20 -41.63419996864298 10 22.03438787062775 20 -41.63419996864298 10 21.56809419669918 20 -41.63419996864298 10 21.56809419669918 20 -41.63419996864298 10 21.56809419669918 20 -41.63419996864298 10 21.56809419669918 20 -42.53026930435646 10 21.56809419669918 20 -42.53026930435646 10 21.56809419669918 20 -42.53026930435646 10 21.10145601322209 20 -42.53026930435646 10 21.10145601322209 20 -42.53026930435646 10 21.10145601322209 20 -42.53026930435646 10 21.10145601322209 20 -40.24513746899024 10 21.10145601322209 20 -40.24513746899024 10 21.10145601322209 20 -40.24513746899024 10 22.1944125559176 20 -40.24513746899024 10 22.1944125559176 20 -40.24513746899024 10 22.35064763617368 20 -40.24823805492697 10 22.4708814686089 20 -40.26787509919289 10 22.554941798449 20 -40.30404860178802 97 0 97 0 92 1 93 1 72 4 94 3 73 0 74 1 95 26 96 22 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 7.0 10 21.56809419669918 20 -40.64201246889102 10 21.56809419669918 20 -40.64201246889102 10 21.56809419669918 20 -41.25592848436255 10 21.56809419669918 20 -41.25592848436255 10 21.56809419669918 20 -41.25592848436255 10 22.08193018832419 20 -41.25592848436255 10 22.08193018832419 20 -41.25592848436255 10 22.18407726946185 20 -41.25592848436255 10 22.2605583892344 20 -41.24352614061565 10 22.31171805719036 20 -41.21872145312185 10 22.4019795589039 20 -41.1753132500077 10 22.44711030976067 20 -41.08953037242498 10 22.44711030976067 20 -40.96137282037368 10 22.44711030976067 20 -40.82287998186664 10 22.403357597098 20 -40.7298624037649 10 22.31602442654692 20 -40.68232008606845 10 22.26693181588211 20 -40.6554483412835 10 22.19337902727203 20 -40.64201246889102 10 22.0951938059424 20 -40.64201246889102 10 22.0951938059424 20 -40.64201246889102 10 21.56809419669918 20 -40.64201246889102 10 21.56809419669918 20 -40.64201246889102 97 0 97 0 75 2 76 1 98 0 0 POLYLINE 5 120D 330 11FA 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 120E 330 120D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.81911958676142 20 -42.53026930435646 30 0.0 0 VERTEX 5 120F 330 120D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.34472993844252 20 -42.53026930435646 30 0.0 0 VERTEX 5 1210 330 120D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.34472993844252 20 -40.24513746899024 30 0.0 0 VERTEX 5 1211 330 120D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.81911958676142 20 -40.24513746899024 30 0.0 0 VERTEX 5 1212 330 120D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.81911958676142 20 -42.53026930435646 30 0.0 0 SEQEND 5 1213 330 120D 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 1214 330 11FA 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 4 72 1 10 23.81911958676142 20 -42.53026930435646 11 23.34472993844252 21 -42.53026930435646 72 1 10 23.34472993844252 20 -42.53026930435646 11 23.34472993844252 21 -40.24513746899024 72 1 10 23.34472993844252 20 -40.24513746899024 11 23.81911958676142 21 -40.24513746899024 72 1 10 23.81911958676142 20 -40.24513746899024 11 23.81911958676142 21 -42.53026930435646 97 0 75 2 76 1 98 0 0 SPLINE 5 1215 330 11FA 100 AcDbEntity 8 Graphics 370 0 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 74 73 70 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 8.0 40 8.0 40 8.0 40 9.0 40 9.0 40 9.0 40 10.0 40 10.0 40 10.0 40 11.0 40 11.0 40 11.0 40 12.0 40 12.0 40 12.0 40 13.0 40 13.0 40 13.0 40 14.0 40 14.0 40 14.0 40 15.0 40 15.0 40 15.0 40 16.0 40 16.0 40 16.0 40 17.0 40 17.0 40 17.0 40 18.0 40 18.0 40 18.0 40 19.0 40 19.0 40 19.0 40 20.0 40 20.0 40 20.0 40 21.0 40 21.0 40 21.0 40 22.0 40 22.0 40 22.0 40 23.0 40 23.0 40 23.0 40 23.0 10 25.80194429329697 20 -40.95827223443696 30 0.0 10 25.76577079070184 20 -40.80220940895514 30 0.0 10 25.67740409150518 20 -40.69317213684699 30 0.0 10 25.53684419570699 20 -40.63116041811249 30 0.0 10 25.4582960186433 20 -40.59705397280852 30 0.0 10 25.37096284809221 20 -40.58000075015653 30 0.0 10 25.27484468405374 20 -40.58000075015653 30 0.0 10 25.0908765851414 20 -40.58000075015653 30 0.0 10 24.93963689333893 20 -40.64941942418432 30 0.0 10 24.8212978634206 20 -40.78808451746562 30 0.0 10 24.70295883350227 20 -40.92692186552119 30 0.0 10 24.64387544593023 20 -41.13552239715307 30 0.0 10 24.64387544593023 20 -41.41405836713552 30 0.0 10 24.64387544593023 20 -41.69466139440912 30 0.0 10 24.70795422195588 20 -41.8930988943595 30 0.0 10 24.83611177400718 20 -42.00971537653521 30 0.0 10 24.96426932605847 20 -42.12633185871092 30 0.0 10 25.10999686508454 20 -42.18455397241164 30 0.0 10 25.27329439108538 20 -42.18455397241164 30 0.0 10 25.4334913311495 20 -42.18455397241164 30 0.0 10 25.56474946913752 20 -42.13856194768356 30 0.0 10 25.66706880504944 20 -42.04675015300165 30 0.0 10 25.76938814096136 20 -41.95476610354547 30 0.0 10 25.83243338834143 20 -41.83436001633599 30 0.0 10 25.85620454718965 20 -41.68535963659894 30 0.0 10 25.85620454718965 20 -41.68535963659894 30 0.0 10 25.32755464497806 20 -41.68535963659894 30 0.0 10 25.32755464497806 20 -41.68535963659894 30 0.0 10 25.32755464497806 20 -41.68535963659894 30 0.0 10 25.32755464497806 20 -41.30398756638179 30 0.0 10 25.32755464497806 20 -41.30398756638179 30 0.0 10 25.32755464497806 20 -41.30398756638179 30 0.0 10 26.2794345275526 20 -41.30398756638179 30 0.0 10 26.2794345275526 20 -41.30398756638179 30 0.0 10 26.2794345275526 20 -41.30398756638179 30 0.0 10 26.2794345275526 20 -42.53026930435646 30 0.0 10 26.2794345275526 20 -42.53026930435646 30 0.0 10 26.2794345275526 20 -42.53026930435646 30 0.0 10 25.96317476200666 20 -42.53026930435646 30 0.0 10 25.96317476200666 20 -42.53026930435646 30 0.0 10 25.96317476200666 20 -42.53026930435646 30 0.0 10 25.91511567998742 20 -42.24501539817778 30 0.0 10 25.91511567998742 20 -42.24501539817778 30 0.0 10 25.82313163053125 20 -42.35301914164036 30 0.0 10 25.74044933888526 20 -42.42915575186438 30 0.0 10 25.66706880504944 20 -42.47342522884984 30 0.0 10 25.54097831028929 20 -42.55059536771944 30 0.0 10 25.38594901345305 20 -42.58918043715423 30 0.0 10 25.20198091454071 20 -42.58918043715423 30 0.0 10 24.89915702138725 20 -42.58918043715423 30 0.0 10 24.65111014644926 20 -42.48427727962838 30 0.0 10 24.45784028972674 20 -42.27464321935092 30 0.0 10 24.25630220383963 20 -42.0639756304279 30 0.0 10 24.15553316089607 20 -41.77579339308675 30 0.0 10 24.15553316089607 20 -41.41009650732748 30 0.0 10 24.15553316089607 20 -41.04043776176017 30 0.0 10 24.2573357324852 20 -40.74398729525442 30 0.0 10 24.46094087566347 20 -40.52091736258449 30 0.0 10 24.66454601884173 20 -40.29784742991457 30 0.0 10 24.93378023101401 20 -40.18622633619248 30 0.0 10 25.26864351218029 20 -40.18622633619248 30 0.0 10 25.55906506158685 20 -40.18622633619248 30 0.0 10 25.79229802593827 20 -40.25995137957682 30 0.0 10 25.9685146600088 20 -40.40705695679699 30 0.0 10 26.14473129407932 20 -40.55450704356568 30 0.0 10 26.24584484657141 20 -40.7381306329295 30 0.0 10 26.27168306271078 20 -40.95827223443696 30 0.0 10 26.27168306271078 20 -40.95827223443696 30 0.0 10 25.80194429329697 20 -40.95827223443696 30 0.0 10 25.80194429329697 20 -40.95827223443696 30 0.0 0 HATCH 5 1216 330 11FA 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 1 72 4 94 3 73 0 74 1 95 74 96 70 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 8.0 40 8.0 40 8.0 40 9.0 40 9.0 40 9.0 40 10.0 40 10.0 40 10.0 40 11.0 40 11.0 40 11.0 40 12.0 40 12.0 40 12.0 40 13.0 40 13.0 40 13.0 40 14.0 40 14.0 40 14.0 40 15.0 40 15.0 40 15.0 40 16.0 40 16.0 40 16.0 40 17.0 40 17.0 40 17.0 40 18.0 40 18.0 40 18.0 40 19.0 40 19.0 40 19.0 40 20.0 40 20.0 40 20.0 40 21.0 40 21.0 40 21.0 40 22.0 40 22.0 40 22.0 40 23.0 40 23.0 40 23.0 40 23.0 10 25.80194429329697 20 -40.95827223443696 10 25.76577079070184 20 -40.80220940895514 10 25.67740409150518 20 -40.69317213684699 10 25.53684419570699 20 -40.63116041811249 10 25.4582960186433 20 -40.59705397280852 10 25.37096284809221 20 -40.58000075015653 10 25.27484468405374 20 -40.58000075015653 10 25.0908765851414 20 -40.58000075015653 10 24.93963689333893 20 -40.64941942418432 10 24.8212978634206 20 -40.78808451746562 10 24.70295883350227 20 -40.92692186552119 10 24.64387544593023 20 -41.13552239715307 10 24.64387544593023 20 -41.41405836713552 10 24.64387544593023 20 -41.69466139440912 10 24.70795422195588 20 -41.8930988943595 10 24.83611177400718 20 -42.00971537653521 10 24.96426932605847 20 -42.12633185871092 10 25.10999686508454 20 -42.18455397241164 10 25.27329439108538 20 -42.18455397241164 10 25.4334913311495 20 -42.18455397241164 10 25.56474946913752 20 -42.13856194768356 10 25.66706880504944 20 -42.04675015300165 10 25.76938814096136 20 -41.95476610354547 10 25.83243338834143 20 -41.83436001633599 10 25.85620454718965 20 -41.68535963659894 10 25.85620454718965 20 -41.68535963659894 10 25.32755464497806 20 -41.68535963659894 10 25.32755464497806 20 -41.68535963659894 10 25.32755464497806 20 -41.68535963659894 10 25.32755464497806 20 -41.30398756638179 10 25.32755464497806 20 -41.30398756638179 10 25.32755464497806 20 -41.30398756638179 10 26.2794345275526 20 -41.30398756638179 10 26.2794345275526 20 -41.30398756638179 10 26.2794345275526 20 -41.30398756638179 10 26.2794345275526 20 -42.53026930435646 10 26.2794345275526 20 -42.53026930435646 10 26.2794345275526 20 -42.53026930435646 10 25.96317476200666 20 -42.53026930435646 10 25.96317476200666 20 -42.53026930435646 10 25.96317476200666 20 -42.53026930435646 10 25.91511567998742 20 -42.24501539817778 10 25.91511567998742 20 -42.24501539817778 10 25.82313163053125 20 -42.35301914164036 10 25.74044933888526 20 -42.42915575186438 10 25.66706880504944 20 -42.47342522884984 10 25.54097831028929 20 -42.55059536771944 10 25.38594901345305 20 -42.58918043715423 10 25.20198091454071 20 -42.58918043715423 10 24.89915702138725 20 -42.58918043715423 10 24.65111014644926 20 -42.48427727962838 10 24.45784028972674 20 -42.27464321935092 10 24.25630220383963 20 -42.0639756304279 10 24.15553316089607 20 -41.77579339308675 10 24.15553316089607 20 -41.41009650732748 10 24.15553316089607 20 -41.04043776176017 10 24.2573357324852 20 -40.74398729525442 10 24.46094087566347 20 -40.52091736258449 10 24.66454601884173 20 -40.29784742991457 10 24.93378023101401 20 -40.18622633619248 10 25.26864351218029 20 -40.18622633619248 10 25.55906506158685 20 -40.18622633619248 10 25.79229802593827 20 -40.25995137957682 10 25.9685146600088 20 -40.40705695679699 10 26.14473129407932 20 -40.55450704356568 10 26.24584484657141 20 -40.7381306329295 10 26.27168306271078 20 -40.95827223443696 10 26.27168306271078 20 -40.95827223443696 10 25.80194429329697 20 -40.95827223443696 10 25.80194429329697 20 -40.95827223443696 97 0 97 0 75 2 76 1 98 0 0 ENDBLK 5 11FD 330 11FA 100 AcDbEntity 8 0 100 AcDbBlockEnd 0 ENDSEC 0 SECTION 2 ENTITIES 0 POLYLINE 5 41 330 1F 100 AcDbEntity 8 Panel 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 42 330 41 100 AcDbEntity 8 Panel 370 0 100 AcDbVertex 100 AcDb2dVertex 10 0.0 20 0.0000161065124161 30 0.0 0 VERTEX 5 43 330 41 100 AcDbEntity 8 Panel 370 0 100 AcDbVertex 100 AcDb2dVertex 10 0.0 20 -128.4999999678622 30 0.0 0 VERTEX 5 44 330 41 100 AcDbEntity 8 Panel 370 0 100 AcDbVertex 100 AcDb2dVertex 10 29.99991301740108 20 -128.4999999678622 30 0.0 0 VERTEX 5 45 330 41 100 AcDbEntity 8 Panel 370 0 100 AcDbVertex 100 AcDb2dVertex 10 29.99991301740108 20 0.0000161065124161 30 0.0 0 VERTEX 5 46 330 41 100 AcDbEntity 8 Panel 370 0 100 AcDbVertex 100 AcDb2dVertex 10 0.0 20 0.0000161065124161 30 0.0 0 SEQEND 5 47 330 41 100 AcDbEntity 8 Panel 370 0 0 SPLINE 5 48 330 1F 100 AcDbEntity 8 Panel 370 0 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 23 73 19 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 6.0 10 8.900059676593147 20 -127.0999131626566 30 0.0 10 8.900059676593147 20 -127.0999131626566 30 0.0 10 6.100230575731246 20 -127.0999131626566 30 0.0 10 6.100230575731246 20 -127.0999131626566 30 0.0 10 5.216563583764662 20 -127.0999131626566 30 0.0 10 4.500005254679479 20 -126.3836778112732 30 0.0 10 4.500005254679479 20 -125.5000108193066 30 0.0 10 4.500005254679479 20 -124.61634382734 30 0.0 10 5.216563583764662 20 -123.9000869441098 30 0.0 10 6.100230575731246 20 -123.9000869441098 30 0.0 10 6.100230575731246 20 -123.9000869441098 30 0.0 10 8.900059676593147 20 -123.9000869441098 30 0.0 10 8.900059676593147 20 -123.9000869441098 30 0.0 10 9.78372666855973 20 -123.9000869441098 30 0.0 10 10.49996201994317 20 -124.61634382734 30 0.0 10 10.49996201994317 20 -125.5000108193066 30 0.0 10 10.49996201994317 20 -126.3836778112732 30 0.0 10 9.78372666855973 20 -127.0999131626566 30 0.0 10 8.900059676593147 20 -127.0999131626566 30 0.0 0 SPLINE 5 49 330 1F 100 AcDbEntity 8 Panel 370 0 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 23 73 19 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 6.0 10 8.900059676593147 20 -4.59989691723995 30 0.0 10 8.900059676593147 20 -4.59989691723995 30 0.0 10 6.100230575731246 20 -4.59989691723995 30 0.0 10 6.100230575731246 20 -4.59989691723995 30 0.0 10 5.216563583764662 20 -4.59989691723995 30 0.0 10 4.500005254679479 20 -3.883467779235463 30 0.0 10 4.500005254679479 20 -3.000016105736708 30 0.0 10 4.500005254679479 20 -2.116349113770124 30 0.0 10 5.216563583764662 20 -1.399919975765638 30 0.0 10 6.100230575731246 20 -1.399919975765638 30 0.0 10 6.100230575731246 20 -1.399919975765638 30 0.0 10 8.900059676593147 20 -1.399919975765638 30 0.0 10 8.900059676593147 20 -1.399919975765638 30 0.0 10 9.78372666855973 20 -1.399919975765638 30 0.0 10 10.49996201994317 20 -2.116349113770124 30 0.0 10 10.49996201994317 20 -3.000016105736708 30 0.0 10 10.49996201994317 20 -3.883467779235463 30 0.0 10 9.78372666855973 20 -4.59989691723995 30 0.0 10 8.900059676593147 20 -4.59989691723995 30 0.0 0 HATCH 5 4A 330 1F 100 AcDbEntity 8 Panel 62 7 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 3 92 1 93 4 72 1 10 0.0 20 0.0000161065124161 11 0.0 21 -128.4999999678622 72 1 10 0.0 20 -128.4999999678622 11 29.99991301740108 21 -128.4999999678622 72 1 10 29.99991301740108 20 -128.4999999678622 11 29.99991301740108 21 0.0000161065124189 72 1 10 29.99991301740108 20 0.0000161065124161 11 0.0 21 0.0000161065124161 97 0 92 1 93 1 72 4 94 3 73 0 74 1 95 23 96 19 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 6.0 10 8.900059676593147 20 -127.0999131626566 10 8.900059676593147 20 -127.0999131626566 10 6.100230575731246 20 -127.0999131626566 10 6.100230575731246 20 -127.0999131626566 10 5.216563583764662 20 -127.0999131626566 10 4.500005254679479 20 -126.3836778112732 10 4.500005254679479 20 -125.5000108193066 10 4.500005254679479 20 -124.61634382734 10 5.216563583764662 20 -123.9000869441098 10 6.100230575731246 20 -123.9000869441098 10 6.100230575731246 20 -123.9000869441098 10 8.900059676593147 20 -123.9000869441098 10 8.900059676593147 20 -123.9000869441098 10 9.78372666855973 20 -123.9000869441098 10 10.49996201994317 20 -124.61634382734 10 10.49996201994317 20 -125.5000108193066 10 10.49996201994317 20 -126.3836778112732 10 9.78372666855973 20 -127.0999131626566 10 8.900059676593147 20 -127.0999131626566 97 0 97 0 92 1 93 1 72 4 94 3 73 0 74 1 95 23 96 19 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 6.0 10 8.900059676593147 20 -4.59989691723995 10 8.900059676593147 20 -4.59989691723995 10 6.100230575731246 20 -4.59989691723995 10 6.100230575731246 20 -4.59989691723995 10 5.216563583764662 20 -4.59989691723995 10 4.500005254679479 20 -3.883467779235463 10 4.500005254679479 20 -3.000016105736708 10 4.500005254679479 20 -2.116349113770124 10 5.216563583764662 20 -1.399919975765638 10 6.100230575731246 20 -1.399919975765638 10 6.100230575731246 20 -1.399919975765638 10 8.900059676593147 20 -1.399919975765638 10 8.900059676593147 20 -1.399919975765638 10 9.78372666855973 20 -1.399919975765638 10 10.49996201994317 20 -2.116349113770124 10 10.49996201994317 20 -3.000016105736708 10 10.49996201994317 20 -3.883467779235463 10 9.78372666855973 20 -4.59989691723995 10 8.900059676593147 20 -4.59989691723995 97 0 97 0 75 2 76 1 98 0 0 SPLINE 5 4C 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 29 73 25 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 8.0 40 8.0 40 8.0 40 8.0 10 22.61979460556333 20 -104.9966391025271 30 0.0 10 22.61979460556333 20 -104.9966391025271 30 0.0 10 22.61979260534892 20 -104.9966391025271 30 0.0 10 22.61979260534892 20 -104.9966391025271 30 0.0 10 22.06744911409592 20 -104.9966391025271 30 0.0 10 21.6196862445949 20 -104.5488762330267 30 0.0 10 21.6196862445949 20 -103.9965327417737 30 0.0 10 21.6196862445949 20 -103.9965327417737 30 0.0 10 21.6196862445949 20 -80.68804552735372 30 0.0 10 21.6196862445949 20 -80.68804552735372 30 0.0 10 21.6196862445949 20 -80.13570203610072 30 0.0 10 22.06744911409592 20 -79.6879391665997 30 0.0 10 22.61979260534892 20 -79.6879391665997 30 0.0 10 22.61979260534892 20 -79.6879391665997 30 0.0 10 22.61979460556333 20 -79.6879391665997 30 0.0 10 22.61979460556333 20 -79.6879391665997 30 0.0 10 23.17213809681633 20 -79.6879391665997 30 0.0 10 23.61990096631735 20 -80.13570203610072 30 0.0 10 23.61990096631735 20 -80.68804552735372 30 0.0 10 23.61990096631735 20 -80.68804552735372 30 0.0 10 23.61990096631735 20 -103.9965327417737 30 0.0 10 23.61990096631735 20 -103.9965327417737 30 0.0 10 23.61990096631735 20 -104.5488762330267 30 0.0 10 23.17213809681633 20 -104.9966391025271 30 0.0 10 22.61979460556333 20 -104.9966391025271 30 0.0 0 SPLINE 5 4D 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 29 73 25 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 5.0 40 5.0 40 5.0 40 6.0 40 6.0 40 6.0 40 7.0 40 7.0 40 7.0 40 8.0 40 8.0 40 8.0 40 8.0 10 7.379741692707754 20 -104.9966391025271 30 0.0 10 7.379741692707754 20 -104.9966391025271 30 0.0 10 7.379739692493347 20 -104.9966391025271 30 0.0 10 7.379739692493347 20 -104.9966391025271 30 0.0 10 6.827396201240349 20 -104.9966391025271 30 0.0 10 6.379633331739329 20 -104.5488762330267 30 0.0 10 6.379633331739329 20 -103.9965327417737 30 0.0 10 6.379633331739329 20 -103.9965327417737 30 0.0 10 6.379633331739329 20 -80.68804552735372 30 0.0 10 6.379633331739329 20 -80.68804552735372 30 0.0 10 6.379633331739329 20 -80.13570203610072 30 0.0 10 6.827396201240349 20 -79.6879391665997 30 0.0 10 7.379739692492705 20 -79.6879391665997 30 0.0 10 7.379739692492705 20 -79.6879391665997 30 0.0 10 7.379741692707754 20 -79.6879391665997 30 0.0 10 7.379741692707754 20 -79.6879391665997 30 0.0 10 7.93208518396011 20 -79.6879391665997 30 0.0 10 8.379848053461131 20 -80.13570203610072 30 0.0 10 8.379848053461131 20 -80.68804552735372 30 0.0 10 8.379848053461131 20 -80.68804552735372 30 0.0 10 8.379848053461131 20 -103.9965327417737 30 0.0 10 8.379848053461131 20 -103.9965327417737 30 0.0 10 8.379848053461131 20 -104.5488762330267 30 0.0 10 7.93208518396011 20 -104.9966391025271 30 0.0 10 7.379741692707754 20 -104.9966391025271 30 0.0 0 POLYLINE 5 4E 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 4F 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.55496797874972 20 -49.00787776551284 30 0.0 0 VERTEX 5 50 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.49046524927386 20 -49.64775797637593 30 0.0 0 VERTEX 5 51 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.30546754912454 20 -50.24372504511347 30 0.0 0 VERTEX 5 52 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.01274061072111 20 -50.78301739727624 30 0.0 0 VERTEX 5 53 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.62505016648162 20 -51.25287345841627 30 0.0 0 VERTEX 5 54 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.155161948825413 20 -51.64053165408401 30 0.0 0 VERTEX 5 55 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.61584169017183 20 -51.93323040983118 30 0.0 0 VERTEX 5 56 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.01985512293764 20 -52.11820815120853 30 0.0 0 VERTEX 5 57 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 7.37996797954347 20 -52.18270330376749 30 0.0 0 VERTEX 5 58 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.740080836148659 20 -52.11820815120853 30 0.0 0 VERTEX 5 59 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.144094268915111 20 -51.93323040983118 30 0.0 0 VERTEX 5 5A 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.604774010260886 20 -51.64053165408401 30 0.0 0 VERTEX 5 5B 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.13488579260468 20 -51.25287345841627 30 0.0 0 VERTEX 5 5C 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.747195348365834 20 -50.78301739727624 30 0.0 0 VERTEX 5 5D 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.454468409962403 20 -50.24372504511347 30 0.0 0 VERTEX 5 5E 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.269470709813085 20 -49.64775797637593 30 0.0 0 VERTEX 5 5F 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.20496798033722 20 -49.00787776551284 30 0.0 0 VERTEX 5 60 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.269470709813085 20 -48.36798372191638 30 0.0 0 VERTEX 5 61 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.454468409962403 20 -47.77197768629792 30 0.0 0 VERTEX 5 62 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.747195348365834 20 -47.23262954840103 30 0.0 0 VERTEX 5 63 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.13488579260468 20 -46.76270919796991 30 0.0 0 VERTEX 5 64 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.604774010260886 20 -46.3749865247475 30 0.0 0 VERTEX 5 65 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.144094268915111 20 -46.08223141847768 30 0.0 0 VERTEX 5 66 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.740080836148659 20 -45.89721376890371 30 0.0 0 VERTEX 5 67 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 7.37996797954347 20 -45.83270346576948 30 0.0 0 VERTEX 5 68 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.01985512293764 20 -45.89721376890371 30 0.0 0 VERTEX 5 69 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.61584169017183 20 -46.08223141847768 30 0.0 0 VERTEX 5 6A 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.155161948825413 20 -46.3749865247475 30 0.0 0 VERTEX 5 6B 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.62505016648162 20 -46.76270919796991 30 0.0 0 VERTEX 5 6C 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.01274061072111 20 -47.23262954840103 30 0.0 0 VERTEX 5 6D 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.30546754912454 20 -47.77197768629792 30 0.0 0 VERTEX 5 6E 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.49046524927386 20 -48.36798372191638 30 0.0 0 VERTEX 5 6F 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.55496797874972 20 -49.00787776551284 30 0.0 0 VERTEX 5 70 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.55496797874972 20 -49.00787776551284 30 0.0 0 SEQEND 5 71 330 4E 100 AcDbEntity 8 Holes 62 1 370 9 0 POLYLINE 5 72 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 73 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.79496797493934 20 -33.7678096069039 30 0.0 0 VERTEX 5 74 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.73046524546347 20 -34.40768915492396 30 0.0 0 VERTEX 5 75 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.54546754531415 20 -35.00365572554841 30 0.0 0 VERTEX 5 76 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.25274060691072 20 -35.54294772079624 30 0.0 0 VERTEX 5 77 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.86505016267188 20 -36.01280354268489 30 0.0 0 VERTEX 5 78 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.39516194501567 20 -36.40046159323335 30 0.0 0 VERTEX 5 79 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.85584168636144 20 -36.69316027445937 30 0.0 0 VERTEX 5 7A 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.25985511912726 20 -36.87813798838195 30 0.0 0 VERTEX 5 7B 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 22.61996797573309 20 -36.94263313701851 30 0.0 0 VERTEX 5 7C 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.98008083233827 20 -36.87813798838195 30 0.0 0 VERTEX 5 7D 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.38409426510409 20 -36.69316027445937 30 0.0 0 VERTEX 5 7E 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.8447740064505 20 -36.40046159323335 30 0.0 0 VERTEX 5 7F 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.37488578879429 20 -36.01280354268489 30 0.0 0 VERTEX 5 80 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.98719534455545 20 -35.54294772079624 30 0.0 0 VERTEX 5 81 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.69446840615202 20 -35.00365572554841 30 0.0 0 VERTEX 5 82 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.5094707060027 20 -34.40768915492396 30 0.0 0 VERTEX 5 83 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.44496797652684 20 -33.7678096069039 30 0.0 0 VERTEX 5 84 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.5094707060027 20 -33.1279149004641 30 0.0 0 VERTEX 5 85 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.69446840615202 20 -32.53190836673286 30 0.0 0 VERTEX 5 86 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.98719534455545 20 -31.99255987192071 30 0.0 0 VERTEX 5 87 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.37488578879429 20 -31.52263928223852 30 0.0 0 VERTEX 5 88 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.8447740064505 20 -31.13491646389651 30 0.0 0 VERTEX 5 89 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.38409426510409 20 -30.84216128310586 30 0.0 0 VERTEX 5 8A 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.98008083233827 20 -30.65714360607712 30 0.0 0 VERTEX 5 8B 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 22.61996797573309 20 -30.59263329902051 30 0.0 0 VERTEX 5 8C 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.25985511912726 20 -30.65714360607712 30 0.0 0 VERTEX 5 8D 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.85584168636144 20 -30.84216128310586 30 0.0 0 VERTEX 5 8E 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.39516194501567 20 -31.13491646389651 30 0.0 0 VERTEX 5 8F 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.86505016267188 20 -31.52263928223852 30 0.0 0 VERTEX 5 90 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.25274060691072 20 -31.99255987192071 30 0.0 0 VERTEX 5 91 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.54546754531415 20 -32.53190836673286 30 0.0 0 VERTEX 5 92 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.73046524546347 20 -33.1279149004641 30 0.0 0 VERTEX 5 93 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.79496797493934 20 -33.7678096069039 30 0.0 0 VERTEX 5 94 330 72 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.79496797493934 20 -33.7678096069039 30 0.0 0 SEQEND 5 95 330 72 100 AcDbEntity 8 Holes 62 1 370 9 0 POLYLINE 5 96 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 97 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.79496797493934 20 -18.52773944015492 30 0.0 0 VERTEX 5 98 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.73046524546347 20 -19.16761898817499 30 0.0 0 VERTEX 5 99 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.54546754531415 20 -19.76358555879943 30 0.0 0 VERTEX 5 9A 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.25274060691072 20 -20.30287755404695 30 0.0 0 VERTEX 5 9B 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.86505016267188 20 -20.77273337593591 30 0.0 0 VERTEX 5 9C 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.39516194501567 20 -21.16039142648437 30 0.0 0 VERTEX 5 9D 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.85584168636144 20 -21.45309010771039 30 0.0 0 VERTEX 5 9E 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.25985511912726 20 -21.63806782163297 30 0.0 0 VERTEX 5 9F 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 22.61996797573309 20 -21.70256297026954 30 0.0 0 VERTEX 5 A0 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.98008083233827 20 -21.63806782163297 30 0.0 0 VERTEX 5 A1 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.38409426510409 20 -21.45309010771039 30 0.0 0 VERTEX 5 A2 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.8447740064505 20 -21.16039142648437 30 0.0 0 VERTEX 5 A3 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.37488578879429 20 -20.77273337593591 30 0.0 0 VERTEX 5 A4 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.98719534455545 20 -20.30287755404695 30 0.0 0 VERTEX 5 A5 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.69446840615202 20 -19.76358555879943 30 0.0 0 VERTEX 5 A6 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.5094707060027 20 -19.16761898817499 30 0.0 0 VERTEX 5 A7 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.44496797652684 20 -18.52773944015492 30 0.0 0 VERTEX 5 A8 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.5094707060027 20 -17.88784473371512 30 0.0 0 VERTEX 5 A9 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.69446840615202 20 -17.29183819998388 30 0.0 0 VERTEX 5 AA 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.98719534455545 20 -16.75248970517173 30 0.0 0 VERTEX 5 AB 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.37488578879429 20 -16.28256911548955 30 0.0 0 VERTEX 5 AC 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.8447740064505 20 -15.89484629714754 30 0.0 0 VERTEX 5 AD 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.38409426510409 20 -15.60209111635689 30 0.0 0 VERTEX 5 AE 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.98008083233827 20 -15.41707343932815 30 0.0 0 VERTEX 5 AF 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 22.61996797573309 20 -15.35256313227153 30 0.0 0 VERTEX 5 B0 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.25985511912726 20 -15.41707343932815 30 0.0 0 VERTEX 5 B1 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.85584168636144 20 -15.60209111635689 30 0.0 0 VERTEX 5 B2 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.39516194501567 20 -15.89484629714754 30 0.0 0 VERTEX 5 B3 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.86505016267188 20 -16.28256911548955 30 0.0 0 VERTEX 5 B4 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.25274060691072 20 -16.75248970517173 30 0.0 0 VERTEX 5 B5 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.54546754531415 20 -17.29183819998388 30 0.0 0 VERTEX 5 B6 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.73046524546347 20 -17.88784473371512 30 0.0 0 VERTEX 5 B7 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.79496797493934 20 -18.52773944015492 30 0.0 0 VERTEX 5 B8 330 96 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.79496797493934 20 -18.52773944015492 30 0.0 0 SEQEND 5 B9 330 96 100 AcDbEntity 8 Holes 62 1 370 9 0 POLYLINE 5 BA 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 BB 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.76996770579784 20 -49.00787639243604 30 0.0 0 VERTEX 5 BC 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.70597287182887 20 -49.64271817644163 30 0.0 0 VERTEX 5 BD 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.52243184648458 20 -50.23399259109487 30 0.0 0 VERTEX 5 BE 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.23200984460383 20 -50.76903854678432 30 0.0 0 VERTEX 5 BF 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.84737208102804 20 -51.23519495389951 30 0.0 0 VERTEX 5 C0 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.38118377059732 20 -51.61980072282996 30 0.0 0 VERTEX 5 C1 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.84611012815309 20 -51.91019476396455 30 0.0 0 VERTEX 5 C2 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.25481636853548 20 -52.09371598769314 30 0.0 0 VERTEX 5 C3 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 22.61996770658462 20 -52.15770330440525 30 0.0 0 VERTEX 5 C4 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.98511904463439 20 -52.09371598769314 30 0.0 0 VERTEX 5 C5 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.39382528501678 20 -51.91019476396455 30 0.0 0 VERTEX 5 C6 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.85875164257191 20 -51.61980072282996 30 0.0 0 VERTEX 5 C7 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.39256333214184 20 -51.23519495389951 30 0.0 0 VERTEX 5 C8 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.00792556856604 20 -50.76903854678432 30 0.0 0 VERTEX 5 C9 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.71750356668529 20 -50.23399259109487 30 0.0 0 VERTEX 5 CA 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.53396254134037 20 -49.64271817644163 30 0.0 0 VERTEX 5 CB 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.46996770737267 20 -49.00787639243604 30 0.0 0 VERTEX 5 CC 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.53396254134037 20 -48.37302088461586 30 0.0 0 VERTEX 5 CD 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 19.71750356668529 20 -47.78170780990818 30 0.0 0 VERTEX 5 CE 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.00792556856604 20 -47.24660650774268 30 0.0 0 VERTEX 5 CF 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.39256333214184 20 -46.78038631755096 30 0.0 0 VERTEX 5 D0 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 20.85875164257191 20 -46.39571657876335 30 0.0 0 VERTEX 5 D1 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.39382528501678 20 -46.10526663081018 30 0.0 0 VERTEX 5 D2 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 21.98511904463439 20 -45.92170581312308 30 0.0 0 VERTEX 5 D3 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 22.61996770658462 20 -45.85770346513139 30 0.0 0 VERTEX 5 D4 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.25481636853548 20 -45.92170581312308 30 0.0 0 VERTEX 5 D5 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 23.84611012815309 20 -46.10526663081018 30 0.0 0 VERTEX 5 D6 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.38118377059732 20 -46.39571657876335 30 0.0 0 VERTEX 5 D7 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 24.84737208102804 20 -46.78038631755096 30 0.0 0 VERTEX 5 D8 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.23200984460383 20 -47.24660650774268 30 0.0 0 VERTEX 5 D9 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.52243184648458 20 -47.78170780990818 30 0.0 0 VERTEX 5 DA 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.70597287182887 20 -48.37302088461586 30 0.0 0 VERTEX 5 DB 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.76996770579784 20 -49.00787639243604 30 0.0 0 VERTEX 5 DC 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 25.76996770579784 20 -49.00787639243604 30 0.0 0 SEQEND 5 DD 330 BA 100 AcDbEntity 8 Holes 62 1 370 9 0 POLYLINE 5 DE 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 DF 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.55496770960125 20 -33.7678096069039 30 0.0 0 VERTEX 5 E0 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.49046498012539 20 -34.40768915492396 30 0.0 0 VERTEX 5 E1 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.30546727997607 20 -35.00365572554841 30 0.0 0 VERTEX 5 E2 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.01274034157328 20 -35.54294772079624 30 0.0 0 VERTEX 5 E3 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.62504989733379 20 -36.01280354268489 30 0.0 0 VERTEX 5 E4 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.155161679677585 20 -36.40046159323335 30 0.0 0 VERTEX 5 E5 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.615841421024001 20 -36.69316027445937 30 0.0 0 VERTEX 5 E6 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.019854853789813 20 -36.87813798838195 30 0.0 0 VERTEX 5 E7 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 7.379967710395642 20 -36.94263313701851 30 0.0 0 VERTEX 5 E8 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.74008056700083 20 -36.87813798838195 30 0.0 0 VERTEX 5 E9 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.144093999766642 20 -36.69316027445937 30 0.0 0 VERTEX 5 EA 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.604773741113058 20 -36.40046159323335 30 0.0 0 VERTEX 5 EB 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.134885523456853 20 -36.01280354268489 30 0.0 0 VERTEX 5 EC 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.747195079217364 20 -35.54294772079624 30 0.0 0 VERTEX 5 ED 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.454468140814575 20 -35.00365572554841 30 0.0 0 VERTEX 5 EE 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.269470440665257 20 -34.40768915492396 30 0.0 0 VERTEX 5 EF 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.204967711189393 20 -33.7678096069039 30 0.0 0 VERTEX 5 F0 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.269470440665257 20 -33.1279149004641 30 0.0 0 VERTEX 5 F1 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.454468140814575 20 -32.53190836673286 30 0.0 0 VERTEX 5 F2 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 4.747195079217364 20 -31.99255987192071 30 0.0 0 VERTEX 5 F3 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.134885523456853 20 -31.52263928223852 30 0.0 0 VERTEX 5 F4 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 5.604773741113058 20 -31.13491646389651 30 0.0 0 VERTEX 5 F5 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.144093999766642 20 -30.84216128310586 30 0.0 0 VERTEX 5 F6 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 6.74008056700083 20 -30.65714360607712 30 0.0 0 VERTEX 5 F7 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 7.379967710395642 20 -30.59263329902051 30 0.0 0 VERTEX 5 F8 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.019854853789813 20 -30.65714360607712 30 0.0 0 VERTEX 5 F9 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 8.615841421024001 20 -30.84216128310586 30 0.0 0 VERTEX 5 FA 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.155161679677585 20 -31.13491646389651 30 0.0 0 VERTEX 5 FB 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 9.62504989733379 20 -31.52263928223852 30 0.0 0 VERTEX 5 FC 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.01274034157328 20 -31.99255987192071 30 0.0 0 VERTEX 5 FD 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.30546727997607 20 -32.53190836673286 30 0.0 0 VERTEX 5 FE 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.49046498012539 20 -33.1279149004641 30 0.0 0 VERTEX 5 FF 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.55496770960125 20 -33.7678096069039 30 0.0 0 VERTEX 5 100 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbVertex 100 AcDb2dVertex 10 10.55496770960125 20 -33.7678096069039 30 0.0 0 SEQEND 5 101 330 DE 100 AcDbEntity 8 Holes 62 1 370 9 0 SPLINE 5 102 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 17 73 13 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 4.0 10 8.904999997773634 20 -18.52819725778256 30 0.0 10 8.904999997773634 20 -19.37036435961662 30 0.0 10 8.222185054212881 20 -20.05299995644864 30 0.0 10 7.379982065206684 20 -20.05299995644864 30 0.0 10 6.537814942097101 20 -20.05299995644864 30 0.0 10 5.854999998536346 20 -19.37036435961662 30 0.0 10 5.854999998536346 20 -18.52819725778256 30 0.0 10 5.854999998536346 20 -17.68581231055233 30 0.0 10 6.537814942097101 20 -17.00300003426144 30 0.0 10 7.379982065206684 20 -17.00300003426144 30 0.0 10 8.222185054212881 20 -17.00300003426144 30 0.0 10 8.904999997773634 20 -17.68581231055233 30 0.0 10 8.904999997773634 20 -18.52819725778256 30 0.0 0 SPLINE 5 103 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 17 73 13 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 4.0 10 25.86999999353217 20 -64.24799998392484 30 0.0 10 25.86999999353217 20 -66.04292542032695 30 0.0 10 24.41492543074608 20 -67.49799998311305 30 0.0 10 22.61999999434429 20 -67.49799998311305 30 0.0 10 20.82507455794378 20 -67.49799998311305 30 0.0 10 19.36999999515768 20 -66.04292542032695 30 0.0 10 19.36999999515768 20 -64.24799998392484 30 0.0 10 19.36999999515768 20 -62.45307454752369 30 0.0 10 20.82507455794378 20 -60.99799998473792 30 0.0 10 22.61999999434429 20 -60.99799998473792 30 0.0 10 24.41492543074608 20 -60.99799998473792 30 0.0 10 25.86999999353217 20 -62.45307454752369 30 0.0 10 25.86999999353217 20 -64.24799998392484 30 0.0 0 SPLINE 5 104 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 17 73 13 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 4.0 10 10.62999999734255 20 -64.24799998392484 30 0.0 10 10.62999999734255 20 -66.04292542032695 30 0.0 10 9.174925434556462 20 -67.49799998311305 30 0.0 10 7.379999998154349 20 -67.49799998311305 30 0.0 10 5.58507456175384 20 -67.49799998311305 30 0.0 10 4.129999998967748 20 -66.04292542032695 30 0.0 10 4.129999998967748 20 -64.24799998392484 30 0.0 10 4.129999998967748 20 -62.45307454752369 30 0.0 10 5.58507456175384 20 -60.99799998473792 30 0.0 10 7.379999998154349 20 -60.99799998473792 30 0.0 10 9.174925434556462 20 -60.99799998473792 30 0.0 10 10.62999999734255 20 -62.45307454752369 30 0.0 10 10.62999999734255 20 -64.24799998392484 30 0.0 0 SPLINE 5 105 330 1F 100 AcDbEntity 8 Holes 62 1 370 9 100 AcDbSpline 210 0.0 220 0.0 230 1.0 70 11 71 3 72 17 73 13 74 0 42 0.0000000001 43 0.0000000001 12 1.0 22 0.0 32 0.0 13 1.0 23 0.0 33 0.0 40 0.0 40 0.0 40 0.0 40 0.0 40 1.0 40 1.0 40 1.0 40 2.0 40 2.0 40 2.0 40 3.0 40 3.0 40 3.0 40 4.0 40 4.0 40 4.0 40 4.0 10 16.60028805571356 20 -109.9679675678604 30 0.0 10 16.60028805571356 20 -110.851640623195 30 0.0 10 15.88372583367003 20 -111.5682028452385 30 0.0 10 15.00005277833575 20 -111.5682028452385 30 0.0 10 14.11637972300114 20 -111.5682028452385 30 0.0 10 13.39978222318009 20 -110.851640623195 30 0.0 10 13.39978222318009 20 -109.9679675678604 30 0.0 10 13.39978222318009 20 -109.0842945125258 30 0.0 10 14.11637972300114 20 -108.3676970127048 30 0.0 10 15.00005277833575 20 -108.3676970127048 30 0.0 10 15.88372583367003 20 -108.3676970127048 30 0.0 10 16.60028805571356 20 -109.0842945125258 30 0.0 10 16.60028805571356 20 -109.9679675678604 30 0.0 0 POLYLINE 5 107 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 108 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.965132648747659 20 -65.90121543083173 30 0.0 0 VERTEX 5 109 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.925835682628604 20 -65.89276720888543 30 0.0 0 VERTEX 5 10A 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.886272259905612 20 -65.88821288685575 30 0.0 0 VERTEX 5 10B 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.846692688297532 20 -65.88753833446826 30 0.0 0 VERTEX 5 10C 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.807347275523216 20 -65.8907294214485 30 0.0 0 VERTEX 5 10D 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.768486329301513 20 -65.897772017522 30 0.0 0 VERTEX 5 10E 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.730360157351273 20 -65.90865199241433 30 0.0 0 VERTEX 5 10F 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.693219067391348 20 -65.92335521585105 30 0.0 0 VERTEX 5 110 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.657313367140586 20 -65.94186755755767 30 0.0 0 VERTEX 5 111 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.590766839612565 20 -65.98982705478554 30 0.0 0 VERTEX 5 112 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.536737716637689 20 -66.04836407174545 30 0.0 0 VERTEX 5 113 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.495825525574817 20 -66.11523391341032 30 0.0 0 VERTEX 5 114 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.468629793782809 20 -66.18819188475304 30 0.0 0 VERTEX 5 115 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.455750048620521 20 -66.26499329074647 30 0.0 0 VERTEX 5 116 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.457785817446815 20 -66.34339343636354 30 0.0 0 VERTEX 5 117 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.475336627620548 20 -66.42114762657712 30 0.0 0 VERTEX 5 118 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.50900200650058 20 -66.4960111663601 30 0.0 0 VERTEX 5 119 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.530819823123476 20 -66.52993257235579 30 0.0 0 VERTEX 5 11A 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.555580774053497 20 -66.56119344953338 30 0.0 0 VERTEX 5 11B 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.58309510989087 20 -66.58965249514834 30 0.0 0 VERTEX 5 11C 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.613173081235822 20 -66.61516840645619 30 0.0 0 VERTEX 5 11D 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.645624938688579 20 -66.63759988071239 30 0.0 0 VERTEX 5 11E 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.680260932849367 20 -66.65680561517244 30 0.0 0 VERTEX 5 11F 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.716891314318413 20 -66.67264430709184 30 0.0 0 VERTEX 5 120 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.755326333695943 20 -66.68497465372606 30 0.0 0 VERTEX 5 121 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.768405248440972 20 -66.6882448029562 30 0.0 0 VERTEX 5 122 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.781538665673169 20 -66.69107893228899 30 0.0 0 VERTEX 5 123 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.794716492339355 20 -66.69347704172442 30 0.0 0 VERTEX 5 124 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.807928635386352 20 -66.6954391312625 30 0.0 0 VERTEX 5 125 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.82116500176098 20 -66.69696520090324 30 0.0 0 VERTEX 5 126 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.834415498410058 20 -66.69805525064662 30 0.0 0 VERTEX 5 127 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.847670032280408 20 -66.69870928049265 30 0.0 0 VERTEX 5 128 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.860918510318851 20 -66.69892729044132 30 0.0 0 VERTEX 5 129 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.887213941767254 20 -66.69806467082958 30 0.0 0 VERTEX 5 12A 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.913345865754149 20 -66.69548219495607 30 0.0 0 VERTEX 5 12B 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.939247668128553 20 -66.69118793726332 30 0.0 0 VERTEX 5 12C 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.964852734739482 20 -66.6851899721939 30 0.0 0 VERTEX 5 12D 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.990094451435951 20 -66.67749637419031 30 0.0 0 VERTEX 5 12E 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.014906204066976 20 -66.66811521769512 30 0.0 0 VERTEX 5 12F 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.039221378481571 20 -66.65705457715087 30 0.0 0 VERTEX 5 130 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.062973360528754 20 -66.64432252700011 30 0.0 0 VERTEX 5 131 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.096902168096769 20 -66.62250504681232 30 0.0 0 VERTEX 5 132 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.128182558510499 20 -66.59774645092804 30 0.0 0 VERTEX 5 133 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.156669191804158 20 -66.57023850735769 30 0.0 0 VERTEX 5 134 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.182216728011964 20 -66.54017298411165 30 0.0 0 VERTEX 5 135 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.204679827168132 20 -66.50774164920037 30 0.0 0 VERTEX 5 136 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.223913149306878 20 -66.47313627063421 30 0.0 0 VERTEX 5 137 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.239771354462419 20 -66.43654861642364 30 0.0 0 VERTEX 5 138 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.25210910266897 20 -66.39817045457902 30 0.0 0 VERTEX 5 139 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.260649171399202 20 -66.35871805544099 30 0.0 0 VERTEX 5 13A 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.265232763283094 20 -66.31906783246066 30 0.0 0 VERTEX 5 13B 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.265892176090818 20 -66.27945798169304 30 0.0 0 VERTEX 5 13C 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.262659707592547 20 -66.24012669919317 30 0.0 0 VERTEX 5 13D 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.255567655558459 20 -66.20131218101609 30 0.0 0 VERTEX 5 13E 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.244648317758726 20 -66.16325262321685 30 0.0 0 VERTEX 5 13F 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.229933991963522 20 -66.12618622185045 30 0.0 0 VERTEX 5 140 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.211456975943022 20 -66.09035117297194 30 0.0 0 VERTEX 5 141 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.189639159320127 20 -66.05642236540392 30 0.0 0 VERTEX 5 142 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.164878208390105 20 -66.02514197499019 30 0.0 0 VERTEX 5 143 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.137363872552732 20 -65.99665534169654 30 0.0 0 VERTEX 5 144 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.10728590120778 20 -65.97110780548873 30 0.0 0 VERTEX 5 145 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.074834043755024 20 -65.94864470633256 30 0.0 0 VERTEX 5 146 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.040198049594236 20 -65.92941138419381 30 0.0 0 VERTEX 5 147 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.003567668125189 20 -65.91355317903827 30 0.0 0 VERTEX 5 148 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.965132648747659 20 -65.90121543083173 30 0.0 0 VERTEX 5 149 330 107 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.965132648747659 20 -65.90121543083173 30 0.0 0 SEQEND 5 14B 330 107 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 14A 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 3.965132648747659 20 -65.90121543083173 11 3.925835682628604 21 -65.89276720888543 72 1 10 3.925835682628604 20 -65.89276720888543 11 3.886272259905612 21 -65.88821288685575 72 1 10 3.886272259905612 20 -65.88821288685575 11 3.846692688297532 21 -65.88753833446826 72 1 10 3.846692688297532 20 -65.88753833446826 11 3.807347275523216 21 -65.8907294214485 72 1 10 3.807347275523216 20 -65.8907294214485 11 3.768486329301513 21 -65.897772017522 72 1 10 3.768486329301513 20 -65.897772017522 11 3.730360157351273 21 -65.90865199241433 72 1 10 3.730360157351273 20 -65.90865199241433 11 3.693219067391348 21 -65.92335521585105 72 1 10 3.693219067391348 20 -65.92335521585105 11 3.657313367140586 21 -65.94186755755767 72 1 10 3.657313367140586 20 -65.94186755755767 11 3.590766839612565 21 -65.98982705478554 72 1 10 3.590766839612565 20 -65.98982705478554 11 3.536737716637689 21 -66.04836407174545 72 1 10 3.536737716637689 20 -66.04836407174545 11 3.495825525574817 21 -66.11523391341032 72 1 10 3.495825525574817 20 -66.11523391341032 11 3.468629793782809 21 -66.18819188475304 72 1 10 3.468629793782809 20 -66.18819188475304 11 3.455750048620521 21 -66.26499329074647 72 1 10 3.455750048620521 20 -66.26499329074647 11 3.457785817446815 21 -66.34339343636354 72 1 10 3.457785817446815 20 -66.34339343636354 11 3.475336627620548 21 -66.42114762657712 72 1 10 3.475336627620548 20 -66.42114762657712 11 3.50900200650058 21 -66.4960111663601 72 1 10 3.50900200650058 20 -66.4960111663601 11 3.530819823123476 21 -66.52993257235579 72 1 10 3.530819823123476 20 -66.52993257235579 11 3.555580774053497 21 -66.56119344953338 72 1 10 3.555580774053497 20 -66.56119344953338 11 3.58309510989087 21 -66.58965249514834 72 1 10 3.58309510989087 20 -66.58965249514834 11 3.613173081235822 21 -66.61516840645619 72 1 10 3.613173081235822 20 -66.61516840645619 11 3.645624938688579 21 -66.63759988071239 72 1 10 3.645624938688579 20 -66.63759988071239 11 3.680260932849367 21 -66.65680561517244 72 1 10 3.680260932849367 20 -66.65680561517244 11 3.716891314318413 21 -66.67264430709184 72 1 10 3.716891314318413 20 -66.67264430709184 11 3.755326333695943 21 -66.68497465372606 72 1 10 3.755326333695943 20 -66.68497465372606 11 3.768405248440972 21 -66.6882448029562 72 1 10 3.768405248440972 20 -66.6882448029562 11 3.781538665673169 21 -66.69107893228899 72 1 10 3.781538665673169 20 -66.69107893228899 11 3.794716492339355 21 -66.69347704172442 72 1 10 3.794716492339355 20 -66.69347704172442 11 3.807928635386352 21 -66.6954391312625 72 1 10 3.807928635386352 20 -66.6954391312625 11 3.82116500176098 21 -66.69696520090324 72 1 10 3.82116500176098 20 -66.69696520090324 11 3.834415498410058 21 -66.69805525064662 72 1 10 3.834415498410058 20 -66.69805525064662 11 3.847670032280408 21 -66.69870928049265 72 1 10 3.847670032280408 20 -66.69870928049265 11 3.860918510318851 21 -66.69892729044132 72 1 10 3.860918510318851 20 -66.69892729044132 11 3.887213941767254 21 -66.69806467082958 72 1 10 3.887213941767254 20 -66.69806467082958 11 3.913345865754149 21 -66.69548219495607 72 1 10 3.913345865754149 20 -66.69548219495607 11 3.939247668128553 21 -66.69118793726332 72 1 10 3.939247668128553 20 -66.69118793726332 11 3.964852734739482 21 -66.6851899721939 72 1 10 3.964852734739482 20 -66.6851899721939 11 3.990094451435951 21 -66.67749637419031 72 1 10 3.990094451435951 20 -66.67749637419031 11 4.014906204066976 21 -66.66811521769512 72 1 10 4.014906204066976 20 -66.66811521769512 11 4.039221378481571 21 -66.65705457715087 72 1 10 4.039221378481571 20 -66.65705457715087 11 4.062973360528754 21 -66.64432252700011 72 1 10 4.062973360528754 20 -66.64432252700011 11 4.096902168096769 21 -66.62250504681232 72 1 10 4.096902168096769 20 -66.62250504681232 11 4.128182558510499 21 -66.59774645092804 72 1 10 4.128182558510499 20 -66.59774645092804 11 4.156669191804158 21 -66.57023850735769 72 1 10 4.156669191804158 20 -66.57023850735769 11 4.182216728011964 21 -66.54017298411165 72 1 10 4.182216728011964 20 -66.54017298411165 11 4.204679827168132 21 -66.50774164920037 72 1 10 4.204679827168132 20 -66.50774164920037 11 4.223913149306878 21 -66.47313627063421 72 1 10 4.223913149306878 20 -66.47313627063421 11 4.239771354462419 21 -66.43654861642364 72 1 10 4.239771354462419 20 -66.43654861642364 11 4.25210910266897 21 -66.39817045457902 72 1 10 4.25210910266897 20 -66.39817045457902 11 4.260649171399202 21 -66.35871805544099 72 1 10 4.260649171399202 20 -66.35871805544099 11 4.265232763283094 21 -66.31906783246066 72 1 10 4.265232763283094 20 -66.31906783246066 11 4.265892176090818 21 -66.27945798169304 72 1 10 4.265892176090818 20 -66.27945798169304 11 4.262659707592547 21 -66.24012669919317 72 1 10 4.262659707592547 20 -66.24012669919317 11 4.255567655558459 21 -66.20131218101609 72 1 10 4.255567655558459 20 -66.20131218101609 11 4.244648317758726 21 -66.16325262321685 72 1 10 4.244648317758726 20 -66.16325262321685 11 4.229933991963522 21 -66.12618622185045 72 1 10 4.229933991963522 20 -66.12618622185045 11 4.211456975943022 21 -66.09035117297194 72 1 10 4.211456975943022 20 -66.09035117297194 11 4.189639159320127 21 -66.05642236540392 72 1 10 4.189639159320127 20 -66.05642236540392 11 4.164878208390105 21 -66.02514197499019 72 1 10 4.164878208390105 20 -66.02514197499019 11 4.137363872552732 21 -65.99665534169654 72 1 10 4.137363872552732 20 -65.99665534169654 11 4.10728590120778 21 -65.97110780548873 72 1 10 4.10728590120778 20 -65.97110780548873 11 4.074834043755024 21 -65.94864470633256 72 1 10 4.074834043755024 20 -65.94864470633256 11 4.040198049594236 21 -65.92941138419381 72 1 10 4.040198049594236 20 -65.92941138419381 11 4.003567668125189 21 -65.91355317903827 72 1 10 4.003567668125189 20 -65.91355317903827 11 3.965132648747659 21 -65.90121543083173 97 0 75 2 76 1 98 0 0 POLYLINE 5 14C 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 14D 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.062973360528754 20 -61.8778606683827 30 0.0 0 VERTEX 5 14E 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.027025269454638 20 -61.85929180557827 30 0.0 0 VERTEX 5 14F 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.989878123662805 20 -61.84454820992885 30 0.0 0 VERTEX 5 150 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.951770119208288 20 -61.83364401170888 30 0.0 0 VERTEX 5 151 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.912939452146124 20 -61.82659334119283 30 0.0 0 VERTEX 5 152 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.873624318531346 20 -61.82341032865514 30 0.0 0 VERTEX 5 153 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.834062914418989 20 -61.82410910437026 30 0.0 0 VERTEX 5 154 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.79449343586409 20 -61.82870379861265 30 0.0 0 VERTEX 5 155 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.755154078921681 20 -61.83720854165675 30 0.0 0 VERTEX 5 156 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.716775917077062 20 -61.84954628986331 30 0.0 0 VERTEX 5 157 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.680188262866475 20 -61.86540449501884 30 0.0 0 VERTEX 5 158 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.645582884300331 20 -61.88463781715759 30 0.0 0 VERTEX 5 159 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.613151549389039 20 -61.90710091631376 30 0.0 0 VERTEX 5 15A 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.583086026143009 20 -61.93264845252156 30 0.0 0 VERTEX 5 15B 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.555578082572649 20 -61.96113508581522 30 0.0 0 VERTEX 5 15C 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.53081948668837 20 -61.99241547622896 30 0.0 0 VERTEX 5 15D 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.50900200650058 20 -62.02634428379697 30 0.0 0 VERTEX 5 15E 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.49052499048008 20 -62.06217899624037 30 0.0 0 VERTEX 5 15F 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.475810664684876 20 -62.09924304256103 30 0.0 0 VERTEX 5 160 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.464891326885143 20 -62.13729620809327 30 0.0 0 VERTEX 5 161 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.457799274851054 20 -62.17609827817142 30 0.0 0 VERTEX 5 162 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.454566806352785 20 -62.21540903812982 30 0.0 0 VERTEX 5 163 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.455226219160509 20 -62.25498827330279 30 0.0 0 VERTEX 5 164 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.4598098110444 20 -62.29459576902499 30 0.0 0 VERTEX 5 165 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.468349879774632 20 -62.33399131062978 30 0.0 0 VERTEX 5 166 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.480680226408852 20 -62.37242633000731 30 0.0 0 VERTEX 5 167 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.496518918328245 20 -62.40905671147635 30 0.0 0 VERTEX 5 168 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.515724652788301 20 -62.44369270563715 30 0.0 0 VERTEX 5 169 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.538156127044507 20 -62.4761445630899 30 0.0 0 VERTEX 5 16A 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.563672038352351 20 -62.50622253443485 30 0.0 0 VERTEX 5 16B 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.59213108396732 20 -62.53373687027255 30 0.0 0 VERTEX 5 16C 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.623391961144902 20 -62.55849782120224 30 0.0 0 VERTEX 5 16D 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.657313367140586 20 -62.58031563782514 30 0.0 0 VERTEX 5 16E 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.68147546358196 20 -62.59323070867388 30 0.0 0 VERTEX 5 16F 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.706109914912132 20 -62.60434517883476 30 0.0 0 VERTEX 5 170 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.731140013926939 20 -62.6136832716367 30 0.0 0 VERTEX 5 171 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.756489053422215 20 -62.62126921040605 30 0.0 0 VERTEX 5 172 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.782080326193799 20 -62.62712721847172 30 0.0 0 VERTEX 5 173 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.807837125037525 20 -62.63128151916038 30 0.0 0 VERTEX 5 174 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.833682742749231 20 -62.63375633579966 30 0.0 0 VERTEX 5 175 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.859540472124751 20 -62.63457589171783 30 0.0 0 VERTEX 5 176 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.911845701616578 20 -62.63119875612399 30 0.0 0 VERTEX 5 177 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.963143644401097 20 -62.62118846598062 30 0.0 0 VERTEX 5 178 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.012749991472741 20 -62.60472669624495 30 0.0 0 VERTEX 5 179 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.059980433825944 20 -62.5819951218742 30 0.0 0 VERTEX 5 17A 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.104150662455139 20 -62.55317541782562 30 0.0 0 VERTEX 5 17B 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.144576368354762 20 -62.51844925905643 30 0.0 0 VERTEX 5 17C 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.180573242519245 20 -62.47799832052386 30 0.0 0 VERTEX 5 17D 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.211456975943022 20 -62.43200427718514 30 0.0 0 VERTEX 5 17E 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.229933991963522 20 -62.3961127072085 30 0.0 0 VERTEX 5 17F 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.244648317758726 20 -62.35900593362971 30 0.0 0 VERTEX 5 180 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.255567655558459 20 -62.32092215250282 30 0.0 0 VERTEX 5 181 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.262659707592547 20 -62.28209955988321 30 0.0 0 VERTEX 5 182 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.265892176090818 20 -62.24277635182588 30 0.0 0 VERTEX 5 183 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.265232763283094 20 -62.2031907243859 30 0.0 0 VERTEX 5 184 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.260649171399202 20 -62.16358087361828 30 0.0 0 VERTEX 5 185 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.25210910266897 20 -62.12418499557806 30 0.0 0 VERTEX 5 186 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.239771354462419 20 -62.08574997620053 30 0.0 0 VERTEX 5 187 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.223913149306878 20 -62.04911959473149 30 0.0 0 VERTEX 5 188 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.204679827168132 20 -62.0144836005707 30 0.0 0 VERTEX 5 189 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.182216728011964 20 -61.98203174311794 30 0.0 0 VERTEX 5 18A 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.156669191804158 20 -61.95195377177267 30 0.0 0 VERTEX 5 18B 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.128182558510499 20 -61.92443943593562 30 0.0 0 VERTEX 5 18C 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.096902168096769 20 -61.89967848500559 30 0.0 0 VERTEX 5 18D 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.062973360528754 20 -61.8778606683827 30 0.0 0 VERTEX 5 18E 330 14C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.062973360528754 20 -61.8778606683827 30 0.0 0 SEQEND 5 190 330 14C 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 18F 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 4.062973360528754 20 -61.8778606683827 11 4.027025269454638 21 -61.85929180557827 72 1 10 4.027025269454638 20 -61.85929180557827 11 3.989878123662805 21 -61.84454820992885 72 1 10 3.989878123662805 20 -61.84454820992885 11 3.951770119208288 21 -61.83364401170888 72 1 10 3.951770119208288 20 -61.83364401170888 11 3.912939452146124 21 -61.82659334119283 72 1 10 3.912939452146124 20 -61.82659334119283 11 3.873624318531346 21 -61.82341032865514 72 1 10 3.873624318531346 20 -61.82341032865514 11 3.834062914418989 21 -61.82410910437026 72 1 10 3.834062914418989 20 -61.82410910437026 11 3.79449343586409 21 -61.82870379861265 72 1 10 3.79449343586409 20 -61.82870379861265 11 3.755154078921681 21 -61.83720854165675 72 1 10 3.755154078921681 20 -61.83720854165675 11 3.716775917077062 21 -61.84954628986331 72 1 10 3.716775917077062 20 -61.84954628986331 11 3.680188262866475 21 -61.86540449501884 72 1 10 3.680188262866475 20 -61.86540449501884 11 3.645582884300331 21 -61.88463781715759 72 1 10 3.645582884300331 20 -61.88463781715759 11 3.613151549389039 21 -61.90710091631376 72 1 10 3.613151549389039 20 -61.90710091631376 11 3.583086026143009 21 -61.93264845252156 72 1 10 3.583086026143009 20 -61.93264845252156 11 3.555578082572649 21 -61.96113508581522 72 1 10 3.555578082572649 20 -61.96113508581522 11 3.53081948668837 21 -61.99241547622896 72 1 10 3.53081948668837 20 -61.99241547622896 11 3.50900200650058 21 -62.02634428379697 72 1 10 3.50900200650058 20 -62.02634428379697 11 3.49052499048008 21 -62.06217899624037 72 1 10 3.49052499048008 20 -62.06217899624037 11 3.475810664684876 21 -62.09924304256103 72 1 10 3.475810664684876 20 -62.09924304256103 11 3.464891326885143 21 -62.13729620809327 72 1 10 3.464891326885143 20 -62.13729620809327 11 3.457799274851054 21 -62.17609827817142 72 1 10 3.457799274851054 20 -62.17609827817142 11 3.454566806352785 21 -62.21540903812982 72 1 10 3.454566806352785 20 -62.21540903812982 11 3.455226219160509 21 -62.25498827330279 72 1 10 3.455226219160509 20 -62.25498827330279 11 3.4598098110444 21 -62.29459576902499 72 1 10 3.4598098110444 20 -62.29459576902499 11 3.468349879774632 21 -62.33399131062978 72 1 10 3.468349879774632 20 -62.33399131062978 11 3.480680226408852 21 -62.37242633000731 72 1 10 3.480680226408852 20 -62.37242633000731 11 3.496518918328245 21 -62.40905671147635 72 1 10 3.496518918328245 20 -62.40905671147635 11 3.515724652788301 21 -62.44369270563715 72 1 10 3.515724652788301 20 -62.44369270563715 11 3.538156127044507 21 -62.4761445630899 72 1 10 3.538156127044507 20 -62.4761445630899 11 3.563672038352351 21 -62.50622253443485 72 1 10 3.563672038352351 20 -62.50622253443485 11 3.59213108396732 21 -62.53373687027255 72 1 10 3.59213108396732 20 -62.53373687027255 11 3.623391961144902 21 -62.55849782120224 72 1 10 3.623391961144902 20 -62.55849782120224 11 3.657313367140586 21 -62.58031563782514 72 1 10 3.657313367140586 20 -62.58031563782514 11 3.68147546358196 21 -62.59323070867388 72 1 10 3.68147546358196 20 -62.59323070867388 11 3.706109914912132 21 -62.60434517883476 72 1 10 3.706109914912132 20 -62.60434517883476 11 3.731140013926939 21 -62.6136832716367 72 1 10 3.731140013926939 20 -62.6136832716367 11 3.756489053422215 21 -62.62126921040605 72 1 10 3.756489053422215 20 -62.62126921040605 11 3.782080326193799 21 -62.62712721847172 72 1 10 3.782080326193799 20 -62.62712721847172 11 3.807837125037525 21 -62.63128151916038 72 1 10 3.807837125037525 20 -62.63128151916038 11 3.833682742749231 21 -62.63375633579966 72 1 10 3.833682742749231 20 -62.63375633579966 11 3.859540472124751 21 -62.63457589171783 72 1 10 3.859540472124751 20 -62.63457589171783 11 3.911845701616578 21 -62.63119875612399 72 1 10 3.911845701616578 20 -62.63119875612399 11 3.963143644401097 21 -62.62118846598062 72 1 10 3.963143644401097 20 -62.62118846598062 11 4.012749991472741 21 -62.60472669624495 72 1 10 4.012749991472741 20 -62.60472669624495 11 4.059980433825944 21 -62.5819951218742 72 1 10 4.059980433825944 20 -62.5819951218742 11 4.104150662455139 21 -62.55317541782562 72 1 10 4.104150662455139 20 -62.55317541782562 11 4.144576368354762 21 -62.51844925905643 72 1 10 4.144576368354762 20 -62.51844925905643 11 4.180573242519245 21 -62.47799832052386 72 1 10 4.180573242519245 20 -62.47799832052386 11 4.211456975943022 21 -62.43200427718514 72 1 10 4.211456975943022 20 -62.43200427718514 11 4.229933991963522 21 -62.3961127072085 72 1 10 4.229933991963522 20 -62.3961127072085 11 4.244648317758726 21 -62.35900593362971 72 1 10 4.244648317758726 20 -62.35900593362971 11 4.255567655558459 21 -62.32092215250282 72 1 10 4.255567655558459 20 -62.32092215250282 11 4.262659707592547 21 -62.28209955988321 72 1 10 4.262659707592547 20 -62.28209955988321 11 4.265892176090818 21 -62.24277635182588 72 1 10 4.265892176090818 20 -62.24277635182588 11 4.265232763283094 21 -62.2031907243859 72 1 10 4.265232763283094 20 -62.2031907243859 11 4.260649171399202 21 -62.16358087361828 72 1 10 4.260649171399202 20 -62.16358087361828 11 4.25210910266897 21 -62.12418499557806 72 1 10 4.25210910266897 20 -62.12418499557806 11 4.239771354462419 21 -62.08574997620053 72 1 10 4.239771354462419 20 -62.08574997620053 11 4.223913149306878 21 -62.04911959473149 72 1 10 4.223913149306878 20 -62.04911959473149 11 4.204679827168132 21 -62.0144836005707 72 1 10 4.204679827168132 20 -62.0144836005707 11 4.182216728011964 21 -61.98203174311794 72 1 10 4.182216728011964 20 -61.98203174311794 11 4.156669191804158 21 -61.95195377177267 72 1 10 4.156669191804158 20 -61.95195377177267 11 4.128182558510499 21 -61.92443943593562 72 1 10 4.128182558510499 20 -61.92443943593562 11 4.096902168096769 21 -61.89967848500559 72 1 10 4.096902168096769 20 -61.89967848500559 11 4.062973360528754 21 -61.8778606683827 97 0 75 2 76 1 98 0 0 POLYLINE 5 191 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 192 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.870675997045579 20 -67.90847878346575 30 0.0 0 VERTEX 5 193 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.885676082408925 20 -67.95524490331832 30 0.0 0 VERTEX 5 194 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.904962435131252 20 -67.99982057830461 30 0.0 0 VERTEX 5 195 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.928358174455589 20 -68.0419754344858 30 0.0 0 VERTEX 5 196 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.955686419624966 20 -68.08147909792311 30 0.0 0 VERTEX 5 197 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.986770289882414 20 -68.11810119467766 30 0.0 0 VERTEX 5 198 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.021432904470963 20 -68.15161135081068 30 0.0 0 VERTEX 5 199 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.059497382633643 20 -68.18177919238332 30 0.0 0 VERTEX 5 19A 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.100786843613485 20 -68.20837434545676 30 0.0 0 VERTEX 5 19B 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.129381640793717 20 -68.2236574989074 30 0.0 0 VERTEX 5 19C 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.158831319578248 20 -68.23699622566302 30 0.0 0 VERTEX 5 19D 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.189027884298059 20 -68.24836176052206 30 0.0 0 VERTEX 5 19E 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.219863339284128 20 -68.25772533828297 30 0.0 0 VERTEX 5 19F 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.251229688867435 20 -68.26505819374415 30 0.0 0 VERTEX 5 1A0 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.283018937378962 20 -68.27033156170408 30 0.0 0 VERTEX 5 1A1 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.315123089149687 20 -68.2735166769612 30 0.0 0 VERTEX 5 1A2 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.34743414851059 20 -68.27458477431391 30 0.0 0 VERTEX 5 1A3 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.412761561377699 20 -68.27022095866299 30 0.0 0 VERTEX 5 1A4 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.476210404721784 20 -68.25741783659609 30 0.0 0 VERTEX 5 1A5 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.537030512365283 20 -68.23660789544194 30 0.0 0 VERTEX 5 1A6 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.594471718130634 20 -68.20822362252927 30 0.0 0 VERTEX 5 1A7 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.647783855840276 20 -68.17269750518683 30 0.0 0 VERTEX 5 1A8 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.696216759316644 20 -68.13046203074336 30 0.0 0 VERTEX 5 1A9 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.739020262382179 20 -68.0819496865276 30 0.0 0 VERTEX 5 1AA 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.775444198859317 20 -68.02759295986827 30 0.0 0 VERTEX 5 1AB 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.797899938497542 20 -67.98391468347279 30 0.0 0 VERTEX 5 1AC 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.8157777215399 20 -67.93875727013388 30 0.0 0 VERTEX 5 1AD 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.829039446710642 20 -67.89240786721446 30 0.0 0 VERTEX 5 1AE 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.837647012734012 20 -67.8451536220775 30 0.0 0 VERTEX 5 1AF 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.841562318334258 20 -67.79728168208598 30 0.0 0 VERTEX 5 1B0 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.84074726223563 20 -67.74907919460281 30 0.0 0 VERTEX 5 1B1 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.835163743162374 20 -67.70083330699099 30 0.0 0 VERTEX 5 1B2 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.824773659838738 20 -67.65283116661344 30 0.0 0 VERTEX 5 1B3 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.809773574475392 20 -67.60606504676088 30 0.0 0 VERTEX 5 1B4 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.790487221753065 20 -67.56148937177458 30 0.0 0 VERTEX 5 1B5 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.767091482428728 20 -67.51933451559339 30 0.0 0 VERTEX 5 1B6 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.739763237259351 20 -67.47983085215608 30 0.0 0 VERTEX 5 1B7 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.708679367001903 20 -67.44320875540153 30 0.0 0 VERTEX 5 1B8 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.674016752413354 20 -67.40969859926852 30 0.0 0 VERTEX 5 1B9 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.635952274250673 20 -67.37953075769589 30 0.0 0 VERTEX 5 1BA 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.594662813270832 20 -67.35293560462244 30 0.0 0 VERTEX 5 1BB 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.5660680160906 20 -67.33765152597526 30 0.0 0 VERTEX 5 1BC 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.536618337306067 20 -67.32431036006511 30 0.0 0 VERTEX 5 1BD 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.506421772586258 20 -67.31294137674624 30 0.0 0 VERTEX 5 1BE 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.475586317600189 20 -67.30357384587285 30 0.0 0 VERTEX 5 1BF 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.444219968016881 20 -67.29623703729915 30 0.0 0 VERTEX 5 1C0 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.412430719505354 20 -67.29096022087938 30 0.0 0 VERTEX 5 1C1 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.380326567734629 20 -67.28777266646777 30 0.0 0 VERTEX 5 1C2 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.348015508373726 20 -67.28670364391851 30 0.0 0 VERTEX 5 1C3 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.282688095506617 20 -67.29107456676104 30 0.0 0 VERTEX 5 1C4 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.219239252162533 20 -67.30388302973525 30 0.0 0 VERTEX 5 1C5 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.158419144519033 20 -67.32469679783873 30 0.0 0 VERTEX 5 1C6 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.100977938753682 20 -67.35308363606907 30 0.0 0 VERTEX 5 1C7 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.047665801044041 20 -67.38861130942388 30 0.0 0 VERTEX 5 1C8 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.999232897567673 20 -67.43084758290073 30 0.0 0 VERTEX 5 1C9 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.956429394502138 20 -67.47936022149722 30 0.0 0 VERTEX 5 1CA 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.920005458025 20 -67.53371699021092 30 0.0 0 VERTEX 5 1CB 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.897549718386775 20 -67.57738908461133 30 0.0 0 VERTEX 5 1CC 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.879671935344416 20 -67.62254359619746 30 0.0 0 VERTEX 5 1CD 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.866410210173675 20 -67.66889262062737 30 0.0 0 VERTEX 5 1CE 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.857802644150305 20 -67.71614825355914 30 0.0 0 VERTEX 5 1CF 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.853887338550058 20 -67.76402259065081 30 0.0 0 VERTEX 5 1D0 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.854702394648686 20 -67.81222772756043 30 0.0 0 VERTEX 5 1D1 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.860285913721942 20 -67.86047575994606 30 0.0 0 VERTEX 5 1D2 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.870675997045579 20 -67.90847878346575 30 0.0 0 VERTEX 5 1D3 330 191 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.870675997045579 20 -67.90847878346575 30 0.0 0 SEQEND 5 1D4 330 191 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 1D5 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 1D6 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.072752379102265 20 -67.62191143463332 30 0.0 0 VERTEX 5 1D7 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.096962627818182 20 -67.58584104939818 30 0.0 0 VERTEX 5 1D8 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.12513969875995 20 -67.55412379799934 30 0.0 0 VERTEX 5 1D9 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.156756986877932 20 -67.52689997387597 30 0.0 0 VERTEX 5 1DA 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.191287887122489 20 -67.5043098704673 30 0.0 0 VERTEX 5 1DB 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.228205794443984 20 -67.4864937812125 30 0.0 0 VERTEX 5 1DC 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.266984103792781 20 -67.47359199955078 30 0.0 0 VERTEX 5 1DD 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.307096210119241 20 -67.46574481892131 30 0.0 0 VERTEX 5 1DE 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.348015508373726 20 -67.4630925327633 30 0.0 0 VERTEX 5 1DF 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.368240725313682 20 -67.463739161037 30 0.0 0 VERTEX 5 1E0 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.388470484127569 20 -67.46568981178147 30 0.0 0 VERTEX 5 1E1 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.408642712538334 20 -67.46896063388184 30 0.0 0 VERTEX 5 1E2 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.428695338268921 20 -67.47356777622313 30 0.0 0 VERTEX 5 1E3 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.448566289042279 20 -67.4795273876905 30 0.0 0 VERTEX 5 1E4 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.468193492581353 20 -67.48685561716898 30 0.0 0 VERTEX 5 1E5 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.487514876609089 20 -67.4955686135437 30 0.0 0 VERTEX 5 1E6 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.506468368848436 20 -67.5056825256997 30 0.0 0 VERTEX 5 1E7 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.55865942067617 20 -67.54326304196243 30 0.0 0 VERTEX 5 1E8 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.601023118949411 20 -67.58908377916718 30 0.0 0 VERTEX 5 1E9 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.633092407632279 20 -67.64140091005088 30 0.0 0 VERTEX 5 1EA 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.654400230688895 20 -67.69847060735046 30 0.0 0 VERTEX 5 1EB 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.66447953208338 20 -67.75854904380282 30 0.0 0 VERTEX 5 1EC 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.662863255779857 20 -67.8198923921449 30 0.0 0 VERTEX 5 1ED 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.649084345742446 20 -67.88075682511361 30 0.0 0 VERTEX 5 1EE 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.622675745935269 20 -67.93939851544587 30 0.0 0 VERTEX 5 1EF 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.598466422415893 20 -67.97546267663155 30 0.0 0 VERTEX 5 1F0 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.570291790628643 20 -68.00717673189689 30 0.0 0 VERTEX 5 1F1 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.538677950970498 20 -68.03439937849738 30 0.0 0 VERTEX 5 1F2 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.504151003838436 20 -68.0569893136885 30 0.0 0 VERTEX 5 1F3 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.467237049629436 20 -68.07480523472576 30 0.0 0 VERTEX 5 1F4 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.428462188740475 20 -68.08770583886461 30 0.0 0 VERTEX 5 1F5 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.388352521568534 20 -68.09554982336057 30 0.0 0 VERTEX 5 1F6 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.34743414851059 20 -68.09819588546911 30 0.0 0 VERTEX 5 1F7 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.327208931570635 20 -68.09755014033756 30 0.0 0 VERTEX 5 1F8 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.306979172756748 20 -68.09560163436689 30 0.0 0 VERTEX 5 1F9 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.286806944345983 20 -68.092333461693 30 0.0 0 VERTEX 5 1FA 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.266754318615396 20 -68.08772871645182 30 0.0 0 VERTEX 5 1FB 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.246883367842038 20 -68.08177049277927 30 0.0 0 VERTEX 5 1FC 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.227256164302964 20 -68.07444188481129 30 0.0 0 VERTEX 5 1FD 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.207934780275226 20 -68.0657259866838 30 0.0 0 VERTEX 5 1FE 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.188981288035881 20 -68.05560589253271 30 0.0 0 VERTEX 5 1FF 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.136790194153757 20 -68.01803160031945 30 0.0 0 VERTEX 5 200 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.094426201499799 20 -67.9722140592482 30 0.0 0 VERTEX 5 201 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.062356113783555 20 -67.91989810588737 30 0.0 0 VERTEX 5 202 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.041046734714574 20 -67.86282857680536 30 0.0 0 VERTEX 5 203 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.030964868002405 20 -67.80275030857054 30 0.0 0 VERTEX 5 204 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.032577317356598 20 -67.74140813775134 30 0.0 0 VERTEX 5 205 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.046350886486701 20 -67.68054690091613 30 0.0 0 VERTEX 5 206 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.072752379102265 20 -67.62191143463332 30 0.0 0 VERTEX 5 207 330 1D5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.072752379102265 20 -67.62191143463332 30 0.0 0 SEQEND 5 208 330 1D5 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 209 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 64 72 1 10 4.870675997045579 20 -67.90847878346575 11 4.885676082408925 21 -67.95524490331832 72 1 10 4.885676082408925 20 -67.95524490331832 11 4.904962435131252 21 -67.99982057830461 72 1 10 4.904962435131252 20 -67.99982057830461 11 4.928358174455589 21 -68.0419754344858 72 1 10 4.928358174455589 20 -68.0419754344858 11 4.955686419624966 21 -68.08147909792311 72 1 10 4.955686419624966 20 -68.08147909792311 11 4.986770289882414 21 -68.11810119467766 72 1 10 4.986770289882414 20 -68.11810119467766 11 5.021432904470963 21 -68.15161135081068 72 1 10 5.021432904470963 20 -68.15161135081068 11 5.059497382633643 21 -68.18177919238332 72 1 10 5.059497382633643 20 -68.18177919238332 11 5.100786843613485 21 -68.20837434545676 72 1 10 5.100786843613485 20 -68.20837434545676 11 5.129381640793717 21 -68.2236574989074 72 1 10 5.129381640793717 20 -68.2236574989074 11 5.158831319578248 21 -68.23699622566302 72 1 10 5.158831319578248 20 -68.23699622566302 11 5.189027884298059 21 -68.24836176052206 72 1 10 5.189027884298059 20 -68.24836176052206 11 5.219863339284128 21 -68.25772533828297 72 1 10 5.219863339284128 20 -68.25772533828297 11 5.251229688867435 21 -68.26505819374415 72 1 10 5.251229688867435 20 -68.26505819374415 11 5.283018937378962 21 -68.27033156170408 72 1 10 5.283018937378962 20 -68.27033156170408 11 5.315123089149687 21 -68.2735166769612 72 1 10 5.315123089149687 20 -68.2735166769612 11 5.34743414851059 21 -68.27458477431391 72 1 10 5.34743414851059 20 -68.27458477431391 11 5.412761561377699 21 -68.27022095866299 72 1 10 5.412761561377699 20 -68.27022095866299 11 5.476210404721784 21 -68.25741783659609 72 1 10 5.476210404721784 20 -68.25741783659609 11 5.537030512365283 21 -68.23660789544194 72 1 10 5.537030512365283 20 -68.23660789544194 11 5.594471718130634 21 -68.20822362252927 72 1 10 5.594471718130634 20 -68.20822362252927 11 5.647783855840276 21 -68.17269750518683 72 1 10 5.647783855840276 20 -68.17269750518683 11 5.696216759316644 21 -68.13046203074336 72 1 10 5.696216759316644 20 -68.13046203074336 11 5.739020262382179 21 -68.0819496865276 72 1 10 5.739020262382179 20 -68.0819496865276 11 5.775444198859317 21 -68.02759295986827 72 1 10 5.775444198859317 20 -68.02759295986827 11 5.797899938497542 21 -67.98391468347279 72 1 10 5.797899938497542 20 -67.98391468347279 11 5.8157777215399 21 -67.93875727013388 72 1 10 5.8157777215399 20 -67.93875727013388 11 5.829039446710642 21 -67.89240786721446 72 1 10 5.829039446710642 20 -67.89240786721446 11 5.837647012734012 21 -67.8451536220775 72 1 10 5.837647012734012 20 -67.8451536220775 11 5.841562318334258 21 -67.79728168208598 72 1 10 5.841562318334258 20 -67.79728168208598 11 5.84074726223563 21 -67.74907919460281 72 1 10 5.84074726223563 20 -67.74907919460281 11 5.835163743162374 21 -67.70083330699099 72 1 10 5.835163743162374 20 -67.70083330699099 11 5.824773659838738 21 -67.65283116661344 72 1 10 5.824773659838738 20 -67.65283116661344 11 5.809773574475392 21 -67.60606504676088 72 1 10 5.809773574475392 20 -67.60606504676088 11 5.790487221753065 21 -67.56148937177458 72 1 10 5.790487221753065 20 -67.56148937177458 11 5.767091482428728 21 -67.51933451559339 72 1 10 5.767091482428728 20 -67.51933451559339 11 5.739763237259351 21 -67.47983085215608 72 1 10 5.739763237259351 20 -67.47983085215608 11 5.708679367001903 21 -67.44320875540153 72 1 10 5.708679367001903 20 -67.44320875540153 11 5.674016752413354 21 -67.40969859926852 72 1 10 5.674016752413354 20 -67.40969859926852 11 5.635952274250673 21 -67.37953075769589 72 1 10 5.635952274250673 20 -67.37953075769589 11 5.594662813270832 21 -67.35293560462244 72 1 10 5.594662813270832 20 -67.35293560462244 11 5.5660680160906 21 -67.33765152597526 72 1 10 5.5660680160906 20 -67.33765152597526 11 5.536618337306067 21 -67.32431036006511 72 1 10 5.536618337306067 20 -67.32431036006511 11 5.506421772586258 21 -67.31294137674624 72 1 10 5.506421772586258 20 -67.31294137674624 11 5.475586317600189 21 -67.30357384587285 72 1 10 5.475586317600189 20 -67.30357384587285 11 5.444219968016881 21 -67.29623703729915 72 1 10 5.444219968016881 20 -67.29623703729915 11 5.412430719505354 21 -67.29096022087938 72 1 10 5.412430719505354 20 -67.29096022087938 11 5.380326567734629 21 -67.28777266646777 72 1 10 5.380326567734629 20 -67.28777266646777 11 5.348015508373726 21 -67.28670364391851 72 1 10 5.348015508373726 20 -67.28670364391851 11 5.282688095506617 21 -67.29107456676104 72 1 10 5.282688095506617 20 -67.29107456676104 11 5.219239252162533 21 -67.30388302973525 72 1 10 5.219239252162533 20 -67.30388302973525 11 5.158419144519033 21 -67.32469679783873 72 1 10 5.158419144519033 20 -67.32469679783873 11 5.100977938753682 21 -67.35308363606907 72 1 10 5.100977938753682 20 -67.35308363606907 11 5.047665801044041 21 -67.38861130942388 72 1 10 5.047665801044041 20 -67.38861130942388 11 4.999232897567673 21 -67.43084758290073 72 1 10 4.999232897567673 20 -67.43084758290073 11 4.956429394502138 21 -67.47936022149722 72 1 10 4.956429394502138 20 -67.47936022149722 11 4.920005458025 21 -67.53371699021092 72 1 10 4.920005458025 20 -67.53371699021092 11 4.897549718386775 21 -67.57738908461133 72 1 10 4.897549718386775 20 -67.57738908461133 11 4.879671935344416 21 -67.62254359619746 72 1 10 4.879671935344416 20 -67.62254359619746 11 4.866410210173675 21 -67.66889262062737 72 1 10 4.866410210173675 20 -67.66889262062737 11 4.857802644150305 21 -67.71614825355914 72 1 10 4.857802644150305 20 -67.71614825355914 11 4.853887338550058 21 -67.76402259065081 72 1 10 4.853887338550058 20 -67.76402259065081 11 4.854702394648686 21 -67.81222772756043 72 1 10 4.854702394648686 20 -67.81222772756043 11 4.860285913721942 21 -67.86047575994606 72 1 10 4.860285913721942 20 -67.86047575994606 11 4.870675997045579 21 -67.90847878346575 97 0 92 1 93 48 72 1 10 5.072752379102265 20 -67.62191143463332 11 5.096962627818182 21 -67.58584104939818 72 1 10 5.096962627818182 20 -67.58584104939818 11 5.12513969875995 21 -67.55412379799934 72 1 10 5.12513969875995 20 -67.55412379799934 11 5.156756986877932 21 -67.52689997387597 72 1 10 5.156756986877932 20 -67.52689997387597 11 5.191287887122489 21 -67.5043098704673 72 1 10 5.191287887122489 20 -67.5043098704673 11 5.228205794443984 21 -67.4864937812125 72 1 10 5.228205794443984 20 -67.4864937812125 11 5.266984103792781 21 -67.47359199955078 72 1 10 5.266984103792781 20 -67.47359199955078 11 5.307096210119241 21 -67.46574481892131 72 1 10 5.307096210119241 20 -67.46574481892131 11 5.348015508373726 21 -67.4630925327633 72 1 10 5.348015508373726 20 -67.4630925327633 11 5.368240725313682 21 -67.463739161037 72 1 10 5.368240725313682 20 -67.463739161037 11 5.388470484127569 21 -67.46568981178147 72 1 10 5.388470484127569 20 -67.46568981178147 11 5.408642712538334 21 -67.46896063388184 72 1 10 5.408642712538334 20 -67.46896063388184 11 5.428695338268921 21 -67.47356777622313 72 1 10 5.428695338268921 20 -67.47356777622313 11 5.448566289042279 21 -67.4795273876905 72 1 10 5.448566289042279 20 -67.4795273876905 11 5.468193492581353 21 -67.48685561716898 72 1 10 5.468193492581353 20 -67.48685561716898 11 5.487514876609089 21 -67.4955686135437 72 1 10 5.487514876609089 20 -67.4955686135437 11 5.506468368848436 21 -67.5056825256997 72 1 10 5.506468368848436 20 -67.5056825256997 11 5.55865942067617 21 -67.54326304196243 72 1 10 5.55865942067617 20 -67.54326304196243 11 5.601023118949411 21 -67.58908377916718 72 1 10 5.601023118949411 20 -67.58908377916718 11 5.633092407632279 21 -67.64140091005088 72 1 10 5.633092407632279 20 -67.64140091005088 11 5.654400230688895 21 -67.69847060735046 72 1 10 5.654400230688895 20 -67.69847060735046 11 5.66447953208338 21 -67.75854904380282 72 1 10 5.66447953208338 20 -67.75854904380282 11 5.662863255779857 21 -67.8198923921449 72 1 10 5.662863255779857 20 -67.8198923921449 11 5.649084345742446 21 -67.88075682511361 72 1 10 5.649084345742446 20 -67.88075682511361 11 5.622675745935269 21 -67.93939851544587 72 1 10 5.622675745935269 20 -67.93939851544587 11 5.598466422415893 21 -67.97546267663155 72 1 10 5.598466422415893 20 -67.97546267663155 11 5.570291790628643 21 -68.00717673189689 72 1 10 5.570291790628643 20 -68.00717673189689 11 5.538677950970498 21 -68.03439937849738 72 1 10 5.538677950970498 20 -68.03439937849738 11 5.504151003838436 21 -68.0569893136885 72 1 10 5.504151003838436 20 -68.0569893136885 11 5.467237049629436 21 -68.07480523472576 72 1 10 5.467237049629436 20 -68.07480523472576 11 5.428462188740475 21 -68.08770583886461 72 1 10 5.428462188740475 20 -68.08770583886461 11 5.388352521568534 21 -68.09554982336057 72 1 10 5.388352521568534 20 -68.09554982336057 11 5.34743414851059 21 -68.09819588546911 72 1 10 5.34743414851059 20 -68.09819588546911 11 5.327208931570635 21 -68.09755014033756 72 1 10 5.327208931570635 20 -68.09755014033756 11 5.306979172756748 21 -68.09560163436689 72 1 10 5.306979172756748 20 -68.09560163436689 11 5.286806944345983 21 -68.092333461693 72 1 10 5.286806944345983 20 -68.092333461693 11 5.266754318615396 21 -68.08772871645182 72 1 10 5.266754318615396 20 -68.08772871645182 11 5.246883367842038 21 -68.08177049277927 72 1 10 5.246883367842038 20 -68.08177049277927 11 5.227256164302964 21 -68.07444188481129 72 1 10 5.227256164302964 20 -68.07444188481129 11 5.207934780275226 21 -68.0657259866838 72 1 10 5.207934780275226 20 -68.0657259866838 11 5.188981288035881 21 -68.05560589253271 72 1 10 5.188981288035881 20 -68.05560589253271 11 5.136790194153757 21 -68.01803160031945 72 1 10 5.136790194153757 20 -68.01803160031945 11 5.094426201499799 21 -67.9722140592482 72 1 10 5.094426201499799 20 -67.9722140592482 11 5.062356113783555 21 -67.91989810588737 72 1 10 5.062356113783555 20 -67.91989810588737 11 5.041046734714574 21 -67.86282857680536 72 1 10 5.041046734714574 20 -67.86282857680536 11 5.030964868002405 21 -67.80275030857054 72 1 10 5.030964868002405 20 -67.80275030857054 11 5.032577317356598 21 -67.74140813775134 72 1 10 5.032577317356598 20 -67.74140813775134 11 5.046350886486701 21 -67.68054690091613 72 1 10 5.046350886486701 20 -67.68054690091613 11 5.072752379102265 21 -67.62191143463332 97 0 75 2 76 1 98 0 0 POLYLINE 5 20A 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 20B 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.721392143166232 20 -64.26117772507854 30 0.0 0 VERTEX 5 20C 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.713139053581402 20 -64.17949632787284 30 0.0 0 VERTEX 5 20D 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.689473871791562 20 -64.10336812852647 30 0.0 0 VERTEX 5 20E 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.652037728243691 20 -64.03443829470767 30 0.0 0 VERTEX 5 20F 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.602471753384765 20 -63.97435199408503 30 0.0 0 VERTEX 5 210 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.542417077661762 20 -63.92475439432582 30 0.0 0 VERTEX 5 211 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.473514831521659 20 -63.88729066309926 30 0.0 0 VERTEX 5 212 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.397406145411434 20 -63.86360596807295 30 0.0 0 VERTEX 5 213 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.315732149778064 20 -63.85534547691611 30 0.0 0 VERTEX 5 214 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.234058154144694 20 -63.86360596807295 30 0.0 0 VERTEX 5 215 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.15794946803447 20 -63.88729066309926 30 0.0 0 VERTEX 5 216 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.089047221894367 20 -63.92475439432582 30 0.0 0 VERTEX 5 217 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.028992546171364 20 -63.97435199408503 30 0.0 0 VERTEX 5 218 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.979426571312438 20 -64.03443829470767 30 0.0 0 VERTEX 5 219 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.941990427764566 20 -64.10336812852647 30 0.0 0 VERTEX 5 21A 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.918325245974726 20 -64.17949632787284 30 0.0 0 VERTEX 5 21B 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.910072156389896 20 -64.26117772507854 30 0.0 0 VERTEX 5 21C 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.918325245974726 20 -64.3428517207116 30 0.0 0 VERTEX 5 21D 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.941990427764566 20 -64.41896040682214 30 0.0 0 VERTEX 5 21E 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.979426571312438 20 -64.48786265296256 30 0.0 0 VERTEX 5 21F 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.028992546171364 20 -64.54791732868524 30 0.0 0 VERTEX 5 220 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.089047221894367 20 -64.59748330354417 30 0.0 0 VERTEX 5 221 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.15794946803447 20 -64.63491944709203 30 0.0 0 VERTEX 5 222 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.234058154144694 20 -64.65858462888188 30 0.0 0 VERTEX 5 223 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.315732149778064 20 -64.66683771846671 30 0.0 0 VERTEX 5 224 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.397406145411434 20 -64.65858462888188 30 0.0 0 VERTEX 5 225 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.473514831521659 20 -64.63491944709203 30 0.0 0 VERTEX 5 226 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.542417077661762 20 -64.59748330354417 30 0.0 0 VERTEX 5 227 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.602471753384765 20 -64.54791732868524 30 0.0 0 VERTEX 5 228 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.652037728243691 20 -64.48786265296256 30 0.0 0 VERTEX 5 229 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.689473871791562 20 -64.41896040682214 30 0.0 0 VERTEX 5 22A 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.713139053581402 20 -64.3428517207116 30 0.0 0 VERTEX 5 22B 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.721392143166232 20 -64.26117772507854 30 0.0 0 VERTEX 5 22C 330 20A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.721392143166232 20 -64.26117772507854 30 0.0 0 SEQEND 5 22E 330 20A 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 22D 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 32 72 1 10 3.721392143166232 20 -64.26117772507854 11 3.713139053581402 21 -64.17949632787284 72 1 10 3.713139053581402 20 -64.17949632787284 11 3.689473871791562 21 -64.10336812852647 72 1 10 3.689473871791562 20 -64.10336812852647 11 3.652037728243691 21 -64.03443829470767 72 1 10 3.652037728243691 20 -64.03443829470767 11 3.602471753384765 21 -63.97435199408503 72 1 10 3.602471753384765 20 -63.97435199408503 11 3.542417077661762 21 -63.92475439432582 72 1 10 3.542417077661762 20 -63.92475439432582 11 3.473514831521659 21 -63.88729066309926 72 1 10 3.473514831521659 20 -63.88729066309926 11 3.397406145411434 21 -63.86360596807295 72 1 10 3.397406145411434 20 -63.86360596807295 11 3.315732149778064 21 -63.85534547691611 72 1 10 3.315732149778064 20 -63.85534547691611 11 3.234058154144694 21 -63.86360596807295 72 1 10 3.234058154144694 20 -63.86360596807295 11 3.15794946803447 21 -63.88729066309926 72 1 10 3.15794946803447 20 -63.88729066309926 11 3.089047221894367 21 -63.92475439432582 72 1 10 3.089047221894367 20 -63.92475439432582 11 3.028992546171364 21 -63.97435199408503 72 1 10 3.028992546171364 20 -63.97435199408503 11 2.979426571312438 21 -64.03443829470767 72 1 10 2.979426571312438 20 -64.03443829470767 11 2.941990427764566 21 -64.10336812852647 72 1 10 2.941990427764566 20 -64.10336812852647 11 2.918325245974726 21 -64.17949632787284 72 1 10 2.918325245974726 20 -64.17949632787284 11 2.910072156389896 21 -64.26117772507854 72 1 10 2.910072156389896 20 -64.26117772507854 11 2.918325245974726 21 -64.3428517207116 72 1 10 2.918325245974726 20 -64.3428517207116 11 2.941990427764566 21 -64.41896040682214 72 1 10 2.941990427764566 20 -64.41896040682214 11 2.979426571312438 21 -64.48786265296256 72 1 10 2.979426571312438 20 -64.48786265296256 11 3.028992546171364 21 -64.54791732868524 72 1 10 3.028992546171364 20 -64.54791732868524 11 3.089047221894367 21 -64.59748330354417 72 1 10 3.089047221894367 20 -64.59748330354417 11 3.15794946803447 21 -64.63491944709203 72 1 10 3.15794946803447 20 -64.63491944709203 11 3.234058154144694 21 -64.65858462888188 72 1 10 3.234058154144694 20 -64.65858462888188 11 3.315732149778064 21 -64.66683771846671 72 1 10 3.315732149778064 20 -64.66683771846671 11 3.397406145411434 21 -64.65858462888188 72 1 10 3.397406145411434 20 -64.65858462888188 11 3.473514831521659 21 -64.63491944709203 72 1 10 3.473514831521659 20 -64.63491944709203 11 3.542417077661762 21 -64.59748330354417 72 1 10 3.542417077661762 20 -64.59748330354417 11 3.602471753384765 21 -64.54791732868524 72 1 10 3.602471753384765 20 -64.54791732868524 11 3.652037728243691 21 -64.48786265296256 72 1 10 3.652037728243691 20 -64.48786265296256 11 3.689473871791562 21 -64.41896040682214 72 1 10 3.689473871791562 20 -64.41896040682214 11 3.713139053581402 21 -64.3428517207116 72 1 10 3.713139053581402 20 -64.3428517207116 11 3.721392143166232 21 -64.26117772507854 97 0 75 2 76 1 98 0 0 POLYLINE 5 22F 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 230 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.242746309452561 20 -61.13354778879447 30 0.0 0 VERTEX 5 231 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.255825224197589 20 -61.13681793802461 30 0.0 0 VERTEX 5 232 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.268958641429786 20 -61.1396520673574 30 0.0 0 VERTEX 5 233 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.282136468095972 20 -61.14205017679284 30 0.0 0 VERTEX 5 234 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.29534861114297 20 -61.14401226633092 30 0.0 0 VERTEX 5 235 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.308584977517596 20 -61.14553833597165 30 0.0 0 VERTEX 5 236 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.321835474166675 20 -61.14662838571503 30 0.0 0 VERTEX 5 237 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.335090008037025 20 -61.14728241556106 30 0.0 0 VERTEX 5 238 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.348338486075469 20 -61.14750042550973 30 0.0 0 VERTEX 5 239 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.374641319096202 20 -61.146637805898 30 0.0 0 VERTEX 5 23A 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.400792756319245 20 -61.14405533002449 30 0.0 0 VERTEX 5 23B 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.42672214637234 20 -61.13976107233174 30 0.0 0 VERTEX 5 23C 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.452358837883231 20 -61.1337631072623 30 0.0 0 VERTEX 5 23D 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.477632179479661 20 -61.12606950925872 30 0.0 0 VERTEX 5 23E 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.502471519789377 20 -61.11668835276353 30 0.0 0 VERTEX 5 23F 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.526806207440119 20 -61.10562771221929 30 0.0 0 VERTEX 5 240 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.550565591059634 20 -61.09289566206853 30 0.0 0 VERTEX 5 241 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.584494398627649 20 -61.07107784544563 30 0.0 0 VERTEX 5 242 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.615774789041378 20 -61.04631689451593 30 0.0 0 VERTEX 5 243 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.644261422335038 20 -61.01880255867823 30 0.0 0 VERTEX 5 244 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.669808958542844 20 -60.98872458733328 30 0.0 0 VERTEX 5 245 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.692272057699012 20 -60.95627272988052 30 0.0 0 VERTEX 5 246 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.711505379837758 20 -60.92163673571974 30 0.0 0 VERTEX 5 247 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.727363584993299 20 -60.88500635425069 30 0.0 0 VERTEX 5 248 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.73970133319985 20 -60.84657133487316 30 0.0 0 VERTEX 5 249 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.748241401930082 20 -60.80717545683295 30 0.0 0 VERTEX 5 24A 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.752824993813974 20 -60.76756560606533 30 0.0 0 VERTEX 5 24B 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.753484406621697 20 -60.72797997862534 30 0.0 0 VERTEX 5 24C 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.750251938123427 20 -60.68865677056802 30 0.0 0 VERTEX 5 24D 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.743159886089339 20 -60.6498341779484 30 0.0 0 VERTEX 5 24E 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.732240548289606 20 -60.61175039682151 30 0.0 0 VERTEX 5 24F 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.717526222494402 20 -60.5746436232424 30 0.0 0 VERTEX 5 250 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.699049206473902 20 -60.53875205326609 30 0.0 0 VERTEX 5 251 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.677231389851007 20 -60.50482324569808 30 0.0 0 VERTEX 5 252 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.652470438920985 20 -60.47354285528434 30 0.0 0 VERTEX 5 253 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.624956103083612 20 -60.44505622199068 30 0.0 0 VERTEX 5 254 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.59487813173866 20 -60.41950868578288 30 0.0 0 VERTEX 5 255 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.562426274285903 20 -60.39704558662671 30 0.0 0 VERTEX 5 256 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.527790280125115 20 -60.37781226448796 30 0.0 0 VERTEX 5 257 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.491159898656069 20 -60.36195405933243 30 0.0 0 VERTEX 5 258 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.452724879278539 20 -60.34961631112587 30 0.0 0 VERTEX 5 259 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.413279545277746 20 -60.34118221945403 30 0.0 0 VERTEX 5 25A 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.373646480487816 20 -60.33666221380516 30 0.0 0 VERTEX 5 25B 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.334057825131874 20 -60.33603005224103 30 0.0 0 VERTEX 5 25C 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.294745719433051 20 -60.33925949282334 30 0.0 0 VERTEX 5 25D 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.255942303614471 20 -60.34632429361385 30 0.0 0 VERTEX 5 25E 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.217879717899262 20 -60.35719821267427 30 0.0 0 VERTEX 5 25F 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.18079010251055 20 -60.37185500806635 30 0.0 0 VERTEX 5 260 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.144905597671466 20 -60.39026843785182 30 0.0 0 VERTEX 5 261 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.11097679010345 20 -60.41208625447472 30 0.0 0 VERTEX 5 262 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.079696399689721 20 -60.43684720540474 30 0.0 0 VERTEX 5 263 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.051209766396061 20 -60.46436154124179 30 0.0 0 VERTEX 5 264 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.025662230188256 20 -60.49443951258706 30 0.0 0 VERTEX 5 265 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.003199131032088 20 -60.52689137003982 30 0.0 0 VERTEX 5 266 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.983965808893341 20 -60.56152736420061 30 0.0 0 VERTEX 5 267 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.9681076037378 20 -60.59815774566965 30 0.0 0 VERTEX 5 268 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.955769855531249 20 -60.63659276504718 30 0.0 0 VERTEX 5 269 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.947229786801016 20 -60.6760451641852 30 0.0 0 VERTEX 5 26A 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.942646194917126 20 -60.71569538716554 30 0.0 0 VERTEX 5 26B 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.941986782109402 20 -60.75530523793316 30 0.0 0 VERTEX 5 26C 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.945219250607672 20 -60.79463652043302 30 0.0 0 VERTEX 5 26D 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.95231130264176 20 -60.8334510386101 30 0.0 0 VERTEX 5 26E 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.963230640441494 20 -60.87151059640935 30 0.0 0 VERTEX 5 26F 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.977944966236698 20 -60.90857699777575 30 0.0 0 VERTEX 5 270 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.996421982257197 20 -60.94441204665426 30 0.0 0 VERTEX 5 271 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.018239798880093 20 -60.97834085422227 30 0.0 0 VERTEX 5 272 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.043000749810115 20 -61.009621244636 30 0.0 0 VERTEX 5 273 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.070515085647488 20 -61.03810787792966 30 0.0 0 VERTEX 5 274 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.100593056992439 20 -61.06365541413746 30 0.0 0 VERTEX 5 275 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.133044914445196 20 -61.08611851329363 30 0.0 0 VERTEX 5 276 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.167680908605984 20 -61.10535183543238 30 0.0 0 VERTEX 5 277 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.20431129007503 20 -61.12121004058793 30 0.0 0 VERTEX 5 278 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.242746309452561 20 -61.13354778879447 30 0.0 0 VERTEX 5 279 330 22F 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.242746309452561 20 -61.13354778879447 30 0.0 0 SEQEND 5 27B 330 22F 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 27A 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 72 72 1 10 5.242746309452561 20 -61.13354778879447 11 5.255825224197589 21 -61.13681793802461 72 1 10 5.255825224197589 20 -61.13681793802461 11 5.268958641429786 21 -61.1396520673574 72 1 10 5.268958641429786 20 -61.1396520673574 11 5.282136468095972 21 -61.14205017679284 72 1 10 5.282136468095972 20 -61.14205017679284 11 5.29534861114297 21 -61.14401226633092 72 1 10 5.29534861114297 20 -61.14401226633092 11 5.308584977517596 21 -61.14553833597165 72 1 10 5.308584977517596 20 -61.14553833597165 11 5.321835474166675 21 -61.14662838571503 72 1 10 5.321835474166675 20 -61.14662838571503 11 5.335090008037025 21 -61.14728241556106 72 1 10 5.335090008037025 20 -61.14728241556106 11 5.348338486075469 21 -61.14750042550973 72 1 10 5.348338486075469 20 -61.14750042550973 11 5.374641319096202 21 -61.146637805898 72 1 10 5.374641319096202 20 -61.146637805898 11 5.400792756319245 21 -61.14405533002449 72 1 10 5.400792756319245 20 -61.14405533002449 11 5.42672214637234 21 -61.13976107233174 72 1 10 5.42672214637234 20 -61.13976107233174 11 5.452358837883231 21 -61.1337631072623 72 1 10 5.452358837883231 20 -61.1337631072623 11 5.477632179479661 21 -61.12606950925872 72 1 10 5.477632179479661 20 -61.12606950925872 11 5.502471519789377 21 -61.11668835276353 72 1 10 5.502471519789377 20 -61.11668835276353 11 5.526806207440119 21 -61.10562771221929 72 1 10 5.526806207440119 20 -61.10562771221929 11 5.550565591059634 21 -61.09289566206853 72 1 10 5.550565591059634 20 -61.09289566206853 11 5.584494398627649 21 -61.07107784544563 72 1 10 5.584494398627649 20 -61.07107784544563 11 5.615774789041378 21 -61.04631689451593 72 1 10 5.615774789041378 20 -61.04631689451593 11 5.644261422335038 21 -61.01880255867823 72 1 10 5.644261422335038 20 -61.01880255867823 11 5.669808958542844 21 -60.98872458733328 72 1 10 5.669808958542844 20 -60.98872458733328 11 5.692272057699012 21 -60.95627272988052 72 1 10 5.692272057699012 20 -60.95627272988052 11 5.711505379837758 21 -60.92163673571974 72 1 10 5.711505379837758 20 -60.92163673571974 11 5.727363584993299 21 -60.88500635425069 72 1 10 5.727363584993299 20 -60.88500635425069 11 5.73970133319985 21 -60.84657133487316 72 1 10 5.73970133319985 20 -60.84657133487316 11 5.748241401930082 21 -60.80717545683295 72 1 10 5.748241401930082 20 -60.80717545683295 11 5.752824993813974 21 -60.76756560606533 72 1 10 5.752824993813974 20 -60.76756560606533 11 5.753484406621697 21 -60.72797997862534 72 1 10 5.753484406621697 20 -60.72797997862534 11 5.750251938123427 21 -60.68865677056802 72 1 10 5.750251938123427 20 -60.68865677056802 11 5.743159886089339 21 -60.6498341779484 72 1 10 5.743159886089339 20 -60.6498341779484 11 5.732240548289606 21 -60.61175039682151 72 1 10 5.732240548289606 20 -60.61175039682151 11 5.717526222494402 21 -60.5746436232424 72 1 10 5.717526222494402 20 -60.5746436232424 11 5.699049206473902 21 -60.53875205326609 72 1 10 5.699049206473902 20 -60.53875205326609 11 5.677231389851007 21 -60.50482324569808 72 1 10 5.677231389851007 20 -60.50482324569808 11 5.652470438920985 21 -60.47354285528434 72 1 10 5.652470438920985 20 -60.47354285528434 11 5.624956103083612 21 -60.44505622199068 72 1 10 5.624956103083612 20 -60.44505622199068 11 5.59487813173866 21 -60.41950868578288 72 1 10 5.59487813173866 20 -60.41950868578288 11 5.562426274285903 21 -60.39704558662671 72 1 10 5.562426274285903 20 -60.39704558662671 11 5.527790280125115 21 -60.37781226448796 72 1 10 5.527790280125115 20 -60.37781226448796 11 5.491159898656069 21 -60.36195405933243 72 1 10 5.491159898656069 20 -60.36195405933243 11 5.452724879278539 21 -60.34961631112587 72 1 10 5.452724879278539 20 -60.34961631112587 11 5.413279545277746 21 -60.34118221945403 72 1 10 5.413279545277746 20 -60.34118221945403 11 5.373646480487816 21 -60.33666221380516 72 1 10 5.373646480487816 20 -60.33666221380516 11 5.334057825131874 21 -60.33603005224103 72 1 10 5.334057825131874 20 -60.33603005224103 11 5.294745719433051 21 -60.33925949282334 72 1 10 5.294745719433051 20 -60.33925949282334 11 5.255942303614471 21 -60.34632429361385 72 1 10 5.255942303614471 20 -60.34632429361385 11 5.217879717899262 21 -60.35719821267427 72 1 10 5.217879717899262 20 -60.35719821267427 11 5.18079010251055 21 -60.37185500806635 72 1 10 5.18079010251055 20 -60.37185500806635 11 5.144905597671466 21 -60.39026843785182 72 1 10 5.144905597671466 20 -60.39026843785182 11 5.11097679010345 21 -60.41208625447472 72 1 10 5.11097679010345 20 -60.41208625447472 11 5.079696399689721 21 -60.43684720540474 72 1 10 5.079696399689721 20 -60.43684720540474 11 5.051209766396061 21 -60.46436154124179 72 1 10 5.051209766396061 20 -60.46436154124179 11 5.025662230188256 21 -60.49443951258706 72 1 10 5.025662230188256 20 -60.49443951258706 11 5.003199131032088 21 -60.52689137003982 72 1 10 5.003199131032088 20 -60.52689137003982 11 4.983965808893341 21 -60.56152736420061 72 1 10 4.983965808893341 20 -60.56152736420061 11 4.9681076037378 21 -60.59815774566965 72 1 10 4.9681076037378 20 -60.59815774566965 11 4.955769855531249 21 -60.63659276504718 72 1 10 4.955769855531249 20 -60.63659276504718 11 4.947229786801016 21 -60.6760451641852 72 1 10 4.947229786801016 20 -60.6760451641852 11 4.942646194917126 21 -60.71569538716554 72 1 10 4.942646194917126 20 -60.71569538716554 11 4.941986782109402 21 -60.75530523793316 72 1 10 4.941986782109402 20 -60.75530523793316 11 4.945219250607672 21 -60.79463652043302 72 1 10 4.945219250607672 20 -60.79463652043302 11 4.95231130264176 21 -60.8334510386101 72 1 10 4.95231130264176 20 -60.8334510386101 11 4.963230640441494 21 -60.87151059640935 72 1 10 4.963230640441494 20 -60.87151059640935 11 4.977944966236698 21 -60.90857699777575 72 1 10 4.977944966236698 20 -60.90857699777575 11 4.996421982257197 21 -60.94441204665426 72 1 10 4.996421982257197 20 -60.94441204665426 11 5.018239798880093 21 -60.97834085422227 72 1 10 5.018239798880093 20 -60.97834085422227 11 5.043000749810115 21 -61.009621244636 72 1 10 5.043000749810115 20 -61.009621244636 11 5.070515085647488 21 -61.03810787792966 72 1 10 5.070515085647488 20 -61.03810787792966 11 5.100593056992439 21 -61.06365541413746 72 1 10 5.100593056992439 20 -61.06365541413746 11 5.133044914445196 21 -61.08611851329363 72 1 10 5.133044914445196 20 -61.08611851329363 11 5.167680908605984 21 -61.10535183543238 72 1 10 5.167680908605984 20 -61.10535183543238 11 5.20431129007503 21 -61.12121004058793 72 1 10 5.20431129007503 20 -61.12121004058793 11 5.242746309452561 21 -61.13354778879447 97 0 75 2 76 1 98 0 0 POLYLINE 5 27C 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 27D 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.68787772186553 30 0.0 0 VERTEX 5 27E 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.64195029267779 30 0.0 0 VERTEX 5 27F 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.59602286349005 30 0.0 0 VERTEX 5 280 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.55009543430232 30 0.0 0 VERTEX 5 281 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.50416800511458 30 0.0 0 VERTEX 5 282 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.45824057592684 30 0.0 0 VERTEX 5 283 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.41231314673911 30 0.0 0 VERTEX 5 284 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.36638571755137 30 0.0 0 VERTEX 5 285 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.32045828836362 30 0.0 0 VERTEX 5 286 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.08924204256104 20 -71.32045828836362 30 0.0 0 VERTEX 5 287 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.92219797521999 20 -71.32045828836362 30 0.0 0 VERTEX 5 288 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.755153907878938 20 -71.32045828836362 30 0.0 0 VERTEX 5 289 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.588109840537888 20 -71.32045828836362 30 0.0 0 VERTEX 5 28A 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.421065773196837 20 -71.32045828836362 30 0.0 0 VERTEX 5 28B 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.254021705855784 20 -71.32045828836362 30 0.0 0 VERTEX 5 28C 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.086977638514734 20 -71.32045828836362 30 0.0 0 VERTEX 5 28D 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.32045828836362 30 0.0 0 VERTEX 5 28E 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.36541678444614 30 0.0 0 VERTEX 5 28F 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.41037528052865 30 0.0 0 VERTEX 5 290 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.45533377661117 30 0.0 0 VERTEX 5 291 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.50029227269367 30 0.0 0 VERTEX 5 292 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.54525076877619 30 0.0 0 VERTEX 5 293 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.5902092648587 30 0.0 0 VERTEX 5 294 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.6351677609412 30 0.0 0 VERTEX 5 295 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.919933571173681 20 -71.68012625702372 30 0.0 0 VERTEX 5 296 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.017279050478772 20 -71.68012625702372 30 0.0 0 VERTEX 5 297 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.114624529783862 20 -71.68012625702372 30 0.0 0 VERTEX 5 298 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.211970009088954 20 -71.68012625702372 30 0.0 0 VERTEX 5 299 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.309315488394045 20 -71.68012625702372 30 0.0 0 VERTEX 5 29A 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.406660967699136 20 -71.68012625702372 30 0.0 0 VERTEX 5 29B 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.504006447004226 20 -71.68012625702372 30 0.0 0 VERTEX 5 29C 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.601351926309317 20 -71.68012625702372 30 0.0 0 VERTEX 5 29D 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.698697405614407 20 -71.68012625702372 30 0.0 0 VERTEX 5 29E 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.593988034709595 20 -71.80337454800853 30 0.0 0 VERTEX 5 29F 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.489278663804782 20 -71.92662283899334 30 0.0 0 VERTEX 5 2A0 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.38456929289997 20 -72.04987112997816 30 0.0 0 VERTEX 5 2A1 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.279859921995158 20 -72.17311942096296 30 0.0 0 VERTEX 5 2A2 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.175150551090345 20 -72.29636771194778 30 0.0 0 VERTEX 5 2A3 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.070441180185535 20 -72.41961600293259 30 0.0 0 VERTEX 5 2A4 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.965731809280722 20 -72.5428642939174 30 0.0 0 VERTEX 5 2A5 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.66611258490222 30 0.0 0 VERTEX 5 2A6 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.70913321477427 30 0.0 0 VERTEX 5 2A7 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.75215384464633 30 0.0 0 VERTEX 5 2A8 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.79517447451839 30 0.0 0 VERTEX 5 2A9 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.83819510439045 30 0.0 0 VERTEX 5 2AA 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.88121573426251 30 0.0 0 VERTEX 5 2AB 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.92423636413456 30 0.0 0 VERTEX 5 2AC 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -72.96725699400662 30 0.0 0 VERTEX 5 2AD 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.86102243837591 20 -73.01027762387868 30 0.0 0 VERTEX 5 2AE 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.039112343116543 20 -73.01027762387868 30 0.0 0 VERTEX 5 2AF 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.217202247857177 20 -73.01027762387868 30 0.0 0 VERTEX 5 2B0 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.395292152597811 20 -73.01027762387868 30 0.0 0 VERTEX 5 2B1 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.573382057338444 20 -73.01027762387868 30 0.0 0 VERTEX 5 2B2 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.751471962079078 20 -73.01027762387868 30 0.0 0 VERTEX 5 2B3 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.929561866819713 20 -73.01027762387868 30 0.0 0 VERTEX 5 2B4 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10765177156035 20 -73.01027762387868 30 0.0 0 VERTEX 5 2B5 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -73.01027762387868 30 0.0 0 VERTEX 5 2B6 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.96493155455407 30 0.0 0 VERTEX 5 2B7 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.91958548522948 30 0.0 0 VERTEX 5 2B8 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.87423941590487 30 0.0 0 VERTEX 5 2B9 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.82889334658027 30 0.0 0 VERTEX 5 2BA 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.78354727725568 30 0.0 0 VERTEX 5 2BB 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.73820120793107 30 0.0 0 VERTEX 5 2BC 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.69285513860648 30 0.0 0 VERTEX 5 2BD 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28574167630098 20 -72.64750906928187 30 0.0 0 VERTEX 5 2BE 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.17840542008866 20 -72.64750906928187 30 0.0 0 VERTEX 5 2BF 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.07106916387635 20 -72.64750906928187 30 0.0 0 VERTEX 5 2C0 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.963732907664033 20 -72.64750906928187 30 0.0 0 VERTEX 5 2C1 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.85639665145172 20 -72.64750906928187 30 0.0 0 VERTEX 5 2C2 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.749060395239404 20 -72.64750906928187 30 0.0 0 VERTEX 5 2C3 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.641724139027088 20 -72.64750906928187 30 0.0 0 VERTEX 5 2C4 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.534387882814773 20 -72.64750906928187 30 0.0 0 VERTEX 5 2C5 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.427051626602458 20 -72.64750906928187 30 0.0 0 VERTEX 5 2C6 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.530705937014911 20 -72.52755515085482 30 0.0 0 VERTEX 5 2C7 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.634360247427367 20 -72.40760123242778 30 0.0 0 VERTEX 5 2C8 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.73801455783982 20 -72.28764731400074 30 0.0 0 VERTEX 5 2C9 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.841668868252276 20 -72.16769339557369 30 0.0 0 VERTEX 5 2CA 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.94532317866473 20 -72.04773947714665 30 0.0 0 VERTEX 5 2CB 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.04897748907718 20 -71.9277855587196 30 0.0 0 VERTEX 5 2CC 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.15263179948964 20 -71.80783164029258 30 0.0 0 VERTEX 5 2CD 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.68787772186553 30 0.0 0 VERTEX 5 2CE 330 27C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25628610990209 20 -71.68787772186553 30 0.0 0 SEQEND 5 2D0 330 27C 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 2CF 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 80 72 1 10 10.25628610990209 20 -71.68787772186553 11 10.25628610990209 21 -71.64195029267779 72 1 10 10.25628610990209 20 -71.64195029267779 11 10.25628610990209 21 -71.59602286349005 72 1 10 10.25628610990209 20 -71.59602286349005 11 10.25628610990209 21 -71.55009543430232 72 1 10 10.25628610990209 20 -71.55009543430232 11 10.25628610990209 21 -71.50416800511458 72 1 10 10.25628610990209 20 -71.50416800511458 11 10.25628610990209 21 -71.45824057592684 72 1 10 10.25628610990209 20 -71.45824057592684 11 10.25628610990209 21 -71.41231314673911 72 1 10 10.25628610990209 20 -71.41231314673911 11 10.25628610990209 21 -71.36638571755137 72 1 10 10.25628610990209 20 -71.36638571755137 11 10.25628610990209 21 -71.32045828836362 72 1 10 10.25628610990209 20 -71.32045828836362 11 10.08924204256104 21 -71.32045828836362 72 1 10 10.08924204256104 20 -71.32045828836362 11 9.92219797521999 21 -71.32045828836362 72 1 10 9.92219797521999 20 -71.32045828836362 11 9.755153907878938 21 -71.32045828836362 72 1 10 9.755153907878938 20 -71.32045828836362 11 9.588109840537888 21 -71.32045828836362 72 1 10 9.588109840537888 20 -71.32045828836362 11 9.421065773196837 21 -71.32045828836362 72 1 10 9.421065773196837 20 -71.32045828836362 11 9.254021705855784 21 -71.32045828836362 72 1 10 9.254021705855784 20 -71.32045828836362 11 9.086977638514734 21 -71.32045828836362 72 1 10 9.086977638514734 20 -71.32045828836362 11 8.919933571173681 21 -71.32045828836362 72 1 10 8.919933571173681 20 -71.32045828836362 11 8.919933571173681 21 -71.36541678444614 72 1 10 8.919933571173681 20 -71.36541678444614 11 8.919933571173681 21 -71.41037528052865 72 1 10 8.919933571173681 20 -71.41037528052865 11 8.919933571173681 21 -71.45533377661117 72 1 10 8.919933571173681 20 -71.45533377661117 11 8.919933571173681 21 -71.50029227269367 72 1 10 8.919933571173681 20 -71.50029227269367 11 8.919933571173681 21 -71.54525076877619 72 1 10 8.919933571173681 20 -71.54525076877619 11 8.919933571173681 21 -71.5902092648587 72 1 10 8.919933571173681 20 -71.5902092648587 11 8.919933571173681 21 -71.6351677609412 72 1 10 8.919933571173681 20 -71.6351677609412 11 8.919933571173681 21 -71.68012625702372 72 1 10 8.919933571173681 20 -71.68012625702372 11 9.017279050478772 21 -71.68012625702372 72 1 10 9.017279050478772 20 -71.68012625702372 11 9.114624529783862 21 -71.68012625702372 72 1 10 9.114624529783862 20 -71.68012625702372 11 9.211970009088954 21 -71.68012625702372 72 1 10 9.211970009088954 20 -71.68012625702372 11 9.309315488394045 21 -71.68012625702372 72 1 10 9.309315488394045 20 -71.68012625702372 11 9.406660967699136 21 -71.68012625702372 72 1 10 9.406660967699136 20 -71.68012625702372 11 9.504006447004226 21 -71.68012625702372 72 1 10 9.504006447004226 20 -71.68012625702372 11 9.601351926309317 21 -71.68012625702372 72 1 10 9.601351926309317 20 -71.68012625702372 11 9.698697405614407 21 -71.68012625702372 72 1 10 9.698697405614407 20 -71.68012625702372 11 9.593988034709595 21 -71.80337454800853 72 1 10 9.593988034709595 20 -71.80337454800853 11 9.489278663804782 21 -71.92662283899334 72 1 10 9.489278663804782 20 -71.92662283899334 11 9.38456929289997 21 -72.04987112997816 72 1 10 9.38456929289997 20 -72.04987112997816 11 9.279859921995158 21 -72.17311942096296 72 1 10 9.279859921995158 20 -72.17311942096296 11 9.175150551090345 21 -72.29636771194778 72 1 10 9.175150551090345 20 -72.29636771194778 11 9.070441180185535 21 -72.41961600293259 72 1 10 9.070441180185535 20 -72.41961600293259 11 8.965731809280722 21 -72.5428642939174 72 1 10 8.965731809280722 20 -72.5428642939174 11 8.86102243837591 21 -72.66611258490222 72 1 10 8.86102243837591 20 -72.66611258490222 11 8.86102243837591 21 -72.70913321477427 72 1 10 8.86102243837591 20 -72.70913321477427 11 8.86102243837591 21 -72.75215384464633 72 1 10 8.86102243837591 20 -72.75215384464633 11 8.86102243837591 21 -72.79517447451839 72 1 10 8.86102243837591 20 -72.79517447451839 11 8.86102243837591 21 -72.83819510439045 72 1 10 8.86102243837591 20 -72.83819510439045 11 8.86102243837591 21 -72.88121573426251 72 1 10 8.86102243837591 20 -72.88121573426251 11 8.86102243837591 21 -72.92423636413456 72 1 10 8.86102243837591 20 -72.92423636413456 11 8.86102243837591 21 -72.96725699400662 72 1 10 8.86102243837591 20 -72.96725699400662 11 8.86102243837591 21 -73.01027762387868 72 1 10 8.86102243837591 20 -73.01027762387868 11 9.039112343116543 21 -73.01027762387868 72 1 10 9.039112343116543 20 -73.01027762387868 11 9.217202247857177 21 -73.01027762387868 72 1 10 9.217202247857177 20 -73.01027762387868 11 9.395292152597811 21 -73.01027762387868 72 1 10 9.395292152597811 20 -73.01027762387868 11 9.573382057338444 21 -73.01027762387868 72 1 10 9.573382057338444 20 -73.01027762387868 11 9.751471962079078 21 -73.01027762387868 72 1 10 9.751471962079078 20 -73.01027762387868 11 9.929561866819713 21 -73.01027762387868 72 1 10 9.929561866819713 20 -73.01027762387868 11 10.10765177156035 21 -73.01027762387868 72 1 10 10.10765177156035 20 -73.01027762387868 11 10.28574167630098 21 -73.01027762387868 72 1 10 10.28574167630098 20 -73.01027762387868 11 10.28574167630098 21 -72.96493155455407 72 1 10 10.28574167630098 20 -72.96493155455407 11 10.28574167630098 21 -72.91958548522948 72 1 10 10.28574167630098 20 -72.91958548522948 11 10.28574167630098 21 -72.87423941590487 72 1 10 10.28574167630098 20 -72.87423941590487 11 10.28574167630098 21 -72.82889334658027 72 1 10 10.28574167630098 20 -72.82889334658027 11 10.28574167630098 21 -72.78354727725568 72 1 10 10.28574167630098 20 -72.78354727725568 11 10.28574167630098 21 -72.73820120793107 72 1 10 10.28574167630098 20 -72.73820120793107 11 10.28574167630098 21 -72.69285513860648 72 1 10 10.28574167630098 20 -72.69285513860648 11 10.28574167630098 21 -72.64750906928187 72 1 10 10.28574167630098 20 -72.64750906928187 11 10.17840542008866 21 -72.64750906928187 72 1 10 10.17840542008866 20 -72.64750906928187 11 10.07106916387635 21 -72.64750906928187 72 1 10 10.07106916387635 20 -72.64750906928187 11 9.963732907664033 21 -72.64750906928187 72 1 10 9.963732907664033 20 -72.64750906928187 11 9.85639665145172 21 -72.64750906928187 72 1 10 9.85639665145172 20 -72.64750906928187 11 9.749060395239404 21 -72.64750906928187 72 1 10 9.749060395239404 20 -72.64750906928187 11 9.641724139027088 21 -72.64750906928187 72 1 10 9.641724139027088 20 -72.64750906928187 11 9.534387882814773 21 -72.64750906928187 72 1 10 9.534387882814773 20 -72.64750906928187 11 9.427051626602458 21 -72.64750906928187 72 1 10 9.427051626602458 20 -72.64750906928187 11 9.530705937014911 21 -72.52755515085482 72 1 10 9.530705937014911 20 -72.52755515085482 11 9.634360247427367 21 -72.40760123242778 72 1 10 9.634360247427367 20 -72.40760123242778 11 9.73801455783982 21 -72.28764731400074 72 1 10 9.73801455783982 20 -72.28764731400074 11 9.841668868252276 21 -72.16769339557369 72 1 10 9.841668868252276 20 -72.16769339557369 11 9.94532317866473 21 -72.04773947714665 72 1 10 9.94532317866473 20 -72.04773947714665 11 10.04897748907718 21 -71.9277855587196 72 1 10 10.04897748907718 20 -71.9277855587196 11 10.15263179948964 21 -71.80783164029258 72 1 10 10.15263179948964 20 -71.80783164029258 11 10.25628610990209 21 -71.68787772186553 97 0 75 2 76 1 98 0 0 POLYLINE 5 2D1 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 2D2 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.245983190476 30 0.0 0 VERTEX 5 2D3 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.972177122779752 20 -72.21682906993207 30 0.0 0 VERTEX 5 2D4 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.000922138234805 20 -72.18767494938815 30 0.0 0 VERTEX 5 2D5 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.029667153689858 20 -72.15852082884422 30 0.0 0 VERTEX 5 2D6 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.058412169144912 20 -72.1293667083003 30 0.0 0 VERTEX 5 2D7 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.087157184599965 20 -72.10021258775636 30 0.0 0 VERTEX 5 2D8 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.115902200055018 20 -72.07105846721244 30 0.0 0 VERTEX 5 2D9 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.144647215510072 20 -72.04190434666852 30 0.0 0 VERTEX 5 2DA 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.173392230965125 20 -72.01275022612458 30 0.0 0 VERTEX 5 2DB 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.261392888766475 20 -72.13744115084384 30 0.0 0 VERTEX 5 2DC 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.349393546567826 20 -72.26213207556312 30 0.0 0 VERTEX 5 2DD 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.437394204369177 20 -72.38682300028238 30 0.0 0 VERTEX 5 2DE 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.525394862170527 20 -72.51151392500164 30 0.0 0 VERTEX 5 2DF 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.613395519971878 20 -72.6362048497209 30 0.0 0 VERTEX 5 2E0 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.701396177773228 20 -72.76089577444016 30 0.0 0 VERTEX 5 2E1 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.789396835574578 20 -72.88558669915942 30 0.0 0 VERTEX 5 2E2 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.87739749337593 20 -73.01027762387868 30 0.0 0 VERTEX 5 2E3 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.954136995309869 20 -73.01027762387868 30 0.0 0 VERTEX 5 2E4 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.03087649724381 20 -73.01027762387868 30 0.0 0 VERTEX 5 2E5 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.107615999177749 20 -73.01027762387868 30 0.0 0 VERTEX 5 2E6 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.18435550111169 20 -73.01027762387868 30 0.0 0 VERTEX 5 2E7 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.26109500304563 20 -73.01027762387868 30 0.0 0 VERTEX 5 2E8 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.33783450497957 20 -73.01027762387868 30 0.0 0 VERTEX 5 2E9 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.414574006913511 20 -73.01027762387868 30 0.0 0 VERTEX 5 2EA 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.49131350884745 20 -73.01027762387868 30 0.0 0 VERTEX 5 2EB 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.368086749709421 20 -72.84211390050491 30 0.0 0 VERTEX 5 2EC 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.24485999057139 20 -72.67395017713116 30 0.0 0 VERTEX 5 2ED 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.12163323143336 20 -72.50578645375741 30 0.0 0 VERTEX 5 2EE 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.99840647229533 20 -72.33762273038364 30 0.0 0 VERTEX 5 2EF 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.8751797131573 20 -72.16945900700989 30 0.0 0 VERTEX 5 2F0 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.75195295401927 20 -72.00129528363613 30 0.0 0 VERTEX 5 2F1 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.628726194881239 20 -71.83313156026237 30 0.0 0 VERTEX 5 2F2 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.505499435743209 20 -71.66496783688862 30 0.0 0 VERTEX 5 2F3 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.622718809628835 20 -71.5474900808416 30 0.0 0 VERTEX 5 2F4 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.739938183514461 20 -71.43001232479457 30 0.0 0 VERTEX 5 2F5 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.857157557400087 20 -71.31253456874755 30 0.0 0 VERTEX 5 2F6 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.974376931285712 20 -71.19505681270054 30 0.0 0 VERTEX 5 2F7 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.091596305171338 20 -71.07757905665352 30 0.0 0 VERTEX 5 2F8 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.208815679056964 20 -70.9601013006065 30 0.0 0 VERTEX 5 2F9 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.326035052942589 20 -70.84262354455947 30 0.0 0 VERTEX 5 2FA 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.443254426828215 20 -70.72514578851246 30 0.0 0 VERTEX 5 2FB 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.366148883498967 20 -70.72514578851246 30 0.0 0 VERTEX 5 2FC 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.289043340169719 20 -70.72514578851246 30 0.0 0 VERTEX 5 2FD 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.211937796840472 20 -70.72514578851246 30 0.0 0 VERTEX 5 2FE 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.134832253511224 20 -70.72514578851246 30 0.0 0 VERTEX 5 2FF 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.057726710181975 20 -70.72514578851246 30 0.0 0 VERTEX 5 300 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.980621166852727 20 -70.72514578851246 30 0.0 0 VERTEX 5 301 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.90351562352348 20 -70.72514578851246 30 0.0 0 VERTEX 5 302 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.826410080194232 20 -70.72514578851246 30 0.0 0 VERTEX 5 303 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.71603783358554 20 -70.84283886302731 30 0.0 0 VERTEX 5 304 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.605665586976849 20 -70.96053193754216 30 0.0 0 VERTEX 5 305 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.495293340368157 20 -71.078225012057 30 0.0 0 VERTEX 5 306 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.384921093759465 20 -71.19591808657185 30 0.0 0 VERTEX 5 307 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.274548847150774 20 -71.3136111610867 30 0.0 0 VERTEX 5 308 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.164176600542082 20 -71.43130423560154 30 0.0 0 VERTEX 5 309 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.05380435393339 20 -71.54899731011639 30 0.0 0 VERTEX 5 30A 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -71.66669038463124 30 0.0 0 VERTEX 5 30B 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -71.54899731011639 30 0.0 0 VERTEX 5 30C 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -71.43130423560154 30 0.0 0 VERTEX 5 30D 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -71.3136111610867 30 0.0 0 VERTEX 5 30E 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -71.19591808657185 30 0.0 0 VERTEX 5 30F 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -71.078225012057 30 0.0 0 VERTEX 5 310 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -70.96053193754216 30 0.0 0 VERTEX 5 311 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -70.84283886302731 30 0.0 0 VERTEX 5 312 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -70.72514578851246 30 0.0 0 VERTEX 5 313 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.884714761147971 20 -70.72514578851246 30 0.0 0 VERTEX 5 314 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.825997414971245 20 -70.72514578851246 30 0.0 0 VERTEX 5 315 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.767280068794518 20 -70.72514578851246 30 0.0 0 VERTEX 5 316 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.708562722617791 20 -70.72514578851246 30 0.0 0 VERTEX 5 317 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.649845376441064 20 -70.72514578851246 30 0.0 0 VERTEX 5 318 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.591128030264337 20 -70.72514578851246 30 0.0 0 VERTEX 5 319 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.53241068408761 20 -70.72514578851246 30 0.0 0 VERTEX 5 31A 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -70.72514578851246 30 0.0 0 VERTEX 5 31B 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -71.01078726793324 30 0.0 0 VERTEX 5 31C 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -71.29642874735401 30 0.0 0 VERTEX 5 31D 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -71.58207022677479 30 0.0 0 VERTEX 5 31E 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -71.86771170619556 30 0.0 0 VERTEX 5 31F 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -72.15335318561634 30 0.0 0 VERTEX 5 320 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -72.43899466503713 30 0.0 0 VERTEX 5 321 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -72.7246361444579 30 0.0 0 VERTEX 5 322 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.473693337910883 20 -73.01027762387868 30 0.0 0 VERTEX 5 323 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.53241068408761 20 -73.01027762387868 30 0.0 0 VERTEX 5 324 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.591128030264337 20 -73.01027762387868 30 0.0 0 VERTEX 5 325 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.649845376441064 20 -73.01027762387868 30 0.0 0 VERTEX 5 326 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.708562722617791 20 -73.01027762387868 30 0.0 0 VERTEX 5 327 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.767280068794518 20 -73.01027762387868 30 0.0 0 VERTEX 5 328 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.825997414971245 20 -73.01027762387868 30 0.0 0 VERTEX 5 329 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.884714761147971 20 -73.01027762387868 30 0.0 0 VERTEX 5 32A 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -73.01027762387868 30 0.0 0 VERTEX 5 32B 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.91474081970334 30 0.0 0 VERTEX 5 32C 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.819204015528 30 0.0 0 VERTEX 5 32D 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.72366721135268 30 0.0 0 VERTEX 5 32E 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.62813040717734 30 0.0 0 VERTEX 5 32F 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.532593603002 30 0.0 0 VERTEX 5 330 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.43705679882667 30 0.0 0 VERTEX 5 331 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.34151999465134 30 0.0 0 VERTEX 5 332 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.245983190476 30 0.0 0 VERTEX 5 333 330 2D1 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.943432107324698 20 -72.245983190476 30 0.0 0 SEQEND 5 335 330 2D1 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 334 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 96 72 1 10 4.943432107324698 20 -72.245983190476 11 4.972177122779752 21 -72.21682906993207 72 1 10 4.972177122779752 20 -72.21682906993207 11 5.000922138234805 21 -72.18767494938815 72 1 10 5.000922138234805 20 -72.18767494938815 11 5.029667153689858 21 -72.15852082884422 72 1 10 5.029667153689858 20 -72.15852082884422 11 5.058412169144912 21 -72.1293667083003 72 1 10 5.058412169144912 20 -72.1293667083003 11 5.087157184599965 21 -72.10021258775636 72 1 10 5.087157184599965 20 -72.10021258775636 11 5.115902200055018 21 -72.07105846721244 72 1 10 5.115902200055018 20 -72.07105846721244 11 5.144647215510072 21 -72.04190434666852 72 1 10 5.144647215510072 20 -72.04190434666852 11 5.173392230965125 21 -72.01275022612458 72 1 10 5.173392230965125 20 -72.01275022612458 11 5.261392888766475 21 -72.13744115084384 72 1 10 5.261392888766475 20 -72.13744115084384 11 5.349393546567826 21 -72.26213207556312 72 1 10 5.349393546567826 20 -72.26213207556312 11 5.437394204369177 21 -72.38682300028238 72 1 10 5.437394204369177 20 -72.38682300028238 11 5.525394862170527 21 -72.51151392500164 72 1 10 5.525394862170527 20 -72.51151392500164 11 5.613395519971878 21 -72.6362048497209 72 1 10 5.613395519971878 20 -72.6362048497209 11 5.701396177773228 21 -72.76089577444016 72 1 10 5.701396177773228 20 -72.76089577444016 11 5.789396835574578 21 -72.88558669915942 72 1 10 5.789396835574578 20 -72.88558669915942 11 5.87739749337593 21 -73.01027762387868 72 1 10 5.87739749337593 20 -73.01027762387868 11 5.954136995309869 21 -73.01027762387868 72 1 10 5.954136995309869 20 -73.01027762387868 11 6.03087649724381 21 -73.01027762387868 72 1 10 6.03087649724381 20 -73.01027762387868 11 6.107615999177749 21 -73.01027762387868 72 1 10 6.107615999177749 20 -73.01027762387868 11 6.18435550111169 21 -73.01027762387868 72 1 10 6.18435550111169 20 -73.01027762387868 11 6.26109500304563 21 -73.01027762387868 72 1 10 6.26109500304563 20 -73.01027762387868 11 6.33783450497957 21 -73.01027762387868 72 1 10 6.33783450497957 20 -73.01027762387868 11 6.414574006913511 21 -73.01027762387868 72 1 10 6.414574006913511 20 -73.01027762387868 11 6.49131350884745 21 -73.01027762387868 72 1 10 6.49131350884745 20 -73.01027762387868 11 6.368086749709421 21 -72.84211390050491 72 1 10 6.368086749709421 20 -72.84211390050491 11 6.24485999057139 21 -72.67395017713116 72 1 10 6.24485999057139 20 -72.67395017713116 11 6.12163323143336 21 -72.50578645375741 72 1 10 6.12163323143336 20 -72.50578645375741 11 5.99840647229533 21 -72.33762273038364 72 1 10 5.99840647229533 20 -72.33762273038364 11 5.8751797131573 21 -72.16945900700989 72 1 10 5.8751797131573 20 -72.16945900700989 11 5.75195295401927 21 -72.00129528363613 72 1 10 5.75195295401927 20 -72.00129528363613 11 5.628726194881239 21 -71.83313156026237 72 1 10 5.628726194881239 20 -71.83313156026237 11 5.505499435743209 21 -71.66496783688862 72 1 10 5.505499435743209 20 -71.66496783688862 11 5.622718809628835 21 -71.5474900808416 72 1 10 5.622718809628835 20 -71.5474900808416 11 5.739938183514461 21 -71.43001232479457 72 1 10 5.739938183514461 20 -71.43001232479457 11 5.857157557400087 21 -71.31253456874755 72 1 10 5.857157557400087 20 -71.31253456874755 11 5.974376931285712 21 -71.19505681270054 72 1 10 5.974376931285712 20 -71.19505681270054 11 6.091596305171338 21 -71.07757905665352 72 1 10 6.091596305171338 20 -71.07757905665352 11 6.208815679056964 21 -70.9601013006065 72 1 10 6.208815679056964 20 -70.9601013006065 11 6.326035052942589 21 -70.84262354455947 72 1 10 6.326035052942589 20 -70.84262354455947 11 6.443254426828215 21 -70.72514578851246 72 1 10 6.443254426828215 20 -70.72514578851246 11 6.366148883498967 21 -70.72514578851246 72 1 10 6.366148883498967 20 -70.72514578851246 11 6.289043340169719 21 -70.72514578851246 72 1 10 6.289043340169719 20 -70.72514578851246 11 6.211937796840472 21 -70.72514578851246 72 1 10 6.211937796840472 20 -70.72514578851246 11 6.134832253511224 21 -70.72514578851246 72 1 10 6.134832253511224 20 -70.72514578851246 11 6.057726710181975 21 -70.72514578851246 72 1 10 6.057726710181975 20 -70.72514578851246 11 5.980621166852727 21 -70.72514578851246 72 1 10 5.980621166852727 20 -70.72514578851246 11 5.90351562352348 21 -70.72514578851246 72 1 10 5.90351562352348 20 -70.72514578851246 11 5.826410080194232 21 -70.72514578851246 72 1 10 5.826410080194232 20 -70.72514578851246 11 5.71603783358554 21 -70.84283886302731 72 1 10 5.71603783358554 20 -70.84283886302731 11 5.605665586976849 21 -70.96053193754216 72 1 10 5.605665586976849 20 -70.96053193754216 11 5.495293340368157 21 -71.078225012057 72 1 10 5.495293340368157 20 -71.078225012057 11 5.384921093759465 21 -71.19591808657185 72 1 10 5.384921093759465 20 -71.19591808657185 11 5.274548847150774 21 -71.3136111610867 72 1 10 5.274548847150774 20 -71.3136111610867 11 5.164176600542082 21 -71.43130423560154 72 1 10 5.164176600542082 20 -71.43130423560154 11 5.05380435393339 21 -71.54899731011639 72 1 10 5.05380435393339 20 -71.54899731011639 11 4.943432107324698 21 -71.66669038463124 72 1 10 4.943432107324698 20 -71.66669038463124 11 4.943432107324698 21 -71.54899731011639 72 1 10 4.943432107324698 20 -71.54899731011639 11 4.943432107324698 21 -71.43130423560154 72 1 10 4.943432107324698 20 -71.43130423560154 11 4.943432107324698 21 -71.3136111610867 72 1 10 4.943432107324698 20 -71.3136111610867 11 4.943432107324698 21 -71.19591808657185 72 1 10 4.943432107324698 20 -71.19591808657185 11 4.943432107324698 21 -71.078225012057 72 1 10 4.943432107324698 20 -71.078225012057 11 4.943432107324698 21 -70.96053193754216 72 1 10 4.943432107324698 20 -70.96053193754216 11 4.943432107324698 21 -70.84283886302731 72 1 10 4.943432107324698 20 -70.84283886302731 11 4.943432107324698 21 -70.72514578851246 72 1 10 4.943432107324698 20 -70.72514578851246 11 4.884714761147971 21 -70.72514578851246 72 1 10 4.884714761147971 20 -70.72514578851246 11 4.825997414971245 21 -70.72514578851246 72 1 10 4.825997414971245 20 -70.72514578851246 11 4.767280068794518 21 -70.72514578851246 72 1 10 4.767280068794518 20 -70.72514578851246 11 4.708562722617791 21 -70.72514578851246 72 1 10 4.708562722617791 20 -70.72514578851246 11 4.649845376441064 21 -70.72514578851246 72 1 10 4.649845376441064 20 -70.72514578851246 11 4.591128030264337 21 -70.72514578851246 72 1 10 4.591128030264337 20 -70.72514578851246 11 4.53241068408761 21 -70.72514578851246 72 1 10 4.53241068408761 20 -70.72514578851246 11 4.473693337910883 21 -70.72514578851246 72 1 10 4.473693337910883 20 -70.72514578851246 11 4.473693337910883 21 -71.01078726793324 72 1 10 4.473693337910883 20 -71.01078726793324 11 4.473693337910883 21 -71.29642874735401 72 1 10 4.473693337910883 20 -71.29642874735401 11 4.473693337910883 21 -71.58207022677479 72 1 10 4.473693337910883 20 -71.58207022677479 11 4.473693337910883 21 -71.86771170619556 72 1 10 4.473693337910883 20 -71.86771170619556 11 4.473693337910883 21 -72.15335318561634 72 1 10 4.473693337910883 20 -72.15335318561634 11 4.473693337910883 21 -72.43899466503713 72 1 10 4.473693337910883 20 -72.43899466503713 11 4.473693337910883 21 -72.7246361444579 72 1 10 4.473693337910883 20 -72.7246361444579 11 4.473693337910883 21 -73.01027762387868 72 1 10 4.473693337910883 20 -73.01027762387868 11 4.53241068408761 21 -73.01027762387868 72 1 10 4.53241068408761 20 -73.01027762387868 11 4.591128030264337 21 -73.01027762387868 72 1 10 4.591128030264337 20 -73.01027762387868 11 4.649845376441064 21 -73.01027762387868 72 1 10 4.649845376441064 20 -73.01027762387868 11 4.708562722617791 21 -73.01027762387868 72 1 10 4.708562722617791 20 -73.01027762387868 11 4.767280068794518 21 -73.01027762387868 72 1 10 4.767280068794518 20 -73.01027762387868 11 4.825997414971245 21 -73.01027762387868 72 1 10 4.825997414971245 20 -73.01027762387868 11 4.884714761147971 21 -73.01027762387868 72 1 10 4.884714761147971 20 -73.01027762387868 11 4.943432107324698 21 -73.01027762387868 72 1 10 4.943432107324698 20 -73.01027762387868 11 4.943432107324698 21 -72.91474081970334 72 1 10 4.943432107324698 20 -72.91474081970334 11 4.943432107324698 21 -72.819204015528 72 1 10 4.943432107324698 20 -72.819204015528 11 4.943432107324698 21 -72.72366721135268 72 1 10 4.943432107324698 20 -72.72366721135268 11 4.943432107324698 21 -72.62813040717734 72 1 10 4.943432107324698 20 -72.62813040717734 11 4.943432107324698 21 -72.532593603002 72 1 10 4.943432107324698 20 -72.532593603002 11 4.943432107324698 21 -72.43705679882667 72 1 10 4.943432107324698 20 -72.43705679882667 11 4.943432107324698 21 -72.34151999465134 72 1 10 4.943432107324698 20 -72.34151999465134 11 4.943432107324698 21 -72.245983190476 97 0 75 2 76 1 98 0 0 POLYLINE 5 336 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 337 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.208912486845794 20 -61.09289566206853 30 0.0 0 VERTEX 5 338 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.232664468892978 20 -61.10562771221929 30 0.0 0 VERTEX 5 339 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.256979643307574 20 -61.11668835276353 30 0.0 0 VERTEX 5 33A 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.281791395938598 20 -61.12606950925872 30 0.0 0 VERTEX 5 33B 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.307033112635066 20 -61.1337631072623 30 0.0 0 VERTEX 5 33C 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.332638179245995 20 -61.13976107233174 30 0.0 0 VERTEX 5 33D 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.3585399816204 20 -61.14405533002449 30 0.0 0 VERTEX 5 33E 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.384671905607295 20 -61.146637805898 30 0.0 0 VERTEX 5 33F 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.410967337055697 20 -61.14750042550973 30 0.0 0 VERTEX 5 340 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.424216151529246 20 -61.14728241556106 30 0.0 0 VERTEX 5 341 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.437473040445338 20 -61.14662838571503 30 0.0 0 VERTEX 5 342 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.450729929361431 20 -61.14553833597165 30 0.0 0 VERTEX 5 343 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.463978743834979 20 -61.14401226633092 30 0.0 0 VERTEX 5 344 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.477211409423441 20 -61.14205017679284 30 0.0 0 VERTEX 5 345 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.490419851684273 20 -61.1396520673574 30 0.0 0 VERTEX 5 346 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.503595996174928 20 -61.13681793802461 30 0.0 0 VERTEX 5 347 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.516731768452868 20 -61.13354778879447 30 0.0 0 VERTEX 5 348 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.555166787830398 20 -61.12121004058793 30 0.0 0 VERTEX 5 349 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.591797169299443 20 -61.10535183543238 30 0.0 0 VERTEX 5 34A 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.626433163460232 20 -61.08611851329363 30 0.0 0 VERTEX 5 34B 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.658885020912988 20 -61.06365541413746 30 0.0 0 VERTEX 5 34C 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.68896299225794 20 -61.03810787792966 30 0.0 0 VERTEX 5 34D 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.716477328095314 20 -61.009621244636 30 0.0 0 VERTEX 5 34E 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.741238279025335 20 -60.97834085422227 30 0.0 0 VERTEX 5 34F 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.763056095648231 20 -60.94441204665426 30 0.0 0 VERTEX 5 350 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.78153311166873 20 -60.90857699777575 30 0.0 0 VERTEX 5 351 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.796247437463935 20 -60.87151059640935 30 0.0 0 VERTEX 5 352 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.807166775263667 20 -60.8334510386101 30 0.0 0 VERTEX 5 353 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.814258827297756 20 -60.79463652043302 30 0.0 0 VERTEX 5 354 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.817491295796026 20 -60.75530523793316 30 0.0 0 VERTEX 5 355 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.816831882988302 20 -60.71569538716554 30 0.0 0 VERTEX 5 356 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.812248291104412 20 -60.6760451641852 30 0.0 0 VERTEX 5 357 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.803708222374178 20 -60.63659276504718 30 0.0 0 VERTEX 5 358 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.791370474167628 20 -60.59815774566965 30 0.0 0 VERTEX 5 359 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.775512269012086 20 -60.56152736420061 30 0.0 0 VERTEX 5 35A 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.75627894687334 20 -60.52689137003982 30 0.0 0 VERTEX 5 35B 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.733815847717173 20 -60.49443951258706 30 0.0 0 VERTEX 5 35C 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.708268311509366 20 -60.46436154124179 30 0.0 0 VERTEX 5 35D 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.679781678215708 20 -60.43684720540474 30 0.0 0 VERTEX 5 35E 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.648501287801977 20 -60.41208625447472 30 0.0 0 VERTEX 5 35F 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.614572480233964 20 -60.39026843785182 30 0.0 0 VERTEX 5 360 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.57860319374817 20 -60.37174903100797 30 0.0 0 VERTEX 5 361 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.54140457338512 20 -60.35702864938086 30 0.0 0 VERTEX 5 362 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.503232982695575 20 -60.34612747907685 30 0.0 0 VERTEX 5 363 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.464344785230287 20 -60.3390657062023 30 0.0 0 VERTEX 5 364 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.424996344540016 20 -60.33586351686356 30 0.0 0 VERTEX 5 365 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.385444024175522 20 -60.33654109716733 30 0.0 0 VERTEX 5 366 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.34594418768756 20 -60.341118633219 30 0.0 0 VERTEX 5 367 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.30675319862689 20 -60.34961631112587 30 0.0 0 VERTEX 5 368 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.26831817924936 20 -60.36195405933243 30 0.0 0 VERTEX 5 369 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.231687797780314 20 -60.37781226448796 30 0.0 0 VERTEX 5 36A 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.197051803619525 20 -60.39704558662671 30 0.0 0 VERTEX 5 36B 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.164599946166769 20 -60.41950868578288 30 0.0 0 VERTEX 5 36C 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.134521974821817 20 -60.44505622199068 30 0.0 0 VERTEX 5 36D 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.107007638984443 20 -60.47354285528434 30 0.0 0 VERTEX 5 36E 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.082246688054422 20 -60.50482324569808 30 0.0 0 VERTEX 5 36F 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.060428871431526 20 -60.53875205326609 30 0.0 0 VERTEX 5 370 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.041951855411027 20 -60.5746436232424 30 0.0 0 VERTEX 5 371 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.027237529615823 20 -60.61175039682151 30 0.0 0 VERTEX 5 372 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.016318191816088 20 -60.6498341779484 30 0.0 0 VERTEX 5 373 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.009226139782001 20 -60.68865677056802 30 0.0 0 VERTEX 5 374 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.005993671283731 20 -60.72797997862534 30 0.0 0 VERTEX 5 375 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.006653084091456 20 -60.76756560606533 30 0.0 0 VERTEX 5 376 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.011236675975345 20 -60.80717545683295 30 0.0 0 VERTEX 5 377 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.01977674470558 20 -60.84657133487316 30 0.0 0 VERTEX 5 378 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.032114492912129 20 -60.88500635425069 30 0.0 0 VERTEX 5 379 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.047972698067671 20 -60.92163673571974 30 0.0 0 VERTEX 5 37A 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.067206020206417 20 -60.95627272988052 30 0.0 0 VERTEX 5 37B 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.089669119362584 20 -60.98872458733328 30 0.0 0 VERTEX 5 37C 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.115216655570391 20 -61.01880255867823 30 0.0 0 VERTEX 5 37D 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.14370328886405 20 -61.04631689451593 30 0.0 0 VERTEX 5 37E 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.17498367927778 20 -61.07107784544563 30 0.0 0 VERTEX 5 37F 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.208912486845794 20 -61.09289566206853 30 0.0 0 VERTEX 5 380 330 336 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.208912486845794 20 -61.09289566206853 30 0.0 0 SEQEND 5 382 330 336 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 381 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 72 72 1 10 9.208912486845794 20 -61.09289566206853 11 9.232664468892978 21 -61.10562771221929 72 1 10 9.232664468892978 20 -61.10562771221929 11 9.256979643307574 21 -61.11668835276353 72 1 10 9.256979643307574 20 -61.11668835276353 11 9.281791395938598 21 -61.12606950925872 72 1 10 9.281791395938598 20 -61.12606950925872 11 9.307033112635066 21 -61.1337631072623 72 1 10 9.307033112635066 20 -61.1337631072623 11 9.332638179245995 21 -61.13976107233174 72 1 10 9.332638179245995 20 -61.13976107233174 11 9.3585399816204 21 -61.14405533002449 72 1 10 9.3585399816204 20 -61.14405533002449 11 9.384671905607295 21 -61.146637805898 72 1 10 9.384671905607295 20 -61.146637805898 11 9.410967337055697 21 -61.14750042550973 72 1 10 9.410967337055697 20 -61.14750042550973 11 9.424216151529246 21 -61.14728241556106 72 1 10 9.424216151529246 20 -61.14728241556106 11 9.437473040445338 21 -61.14662838571503 72 1 10 9.437473040445338 20 -61.14662838571503 11 9.450729929361431 21 -61.14553833597165 72 1 10 9.450729929361431 20 -61.14553833597165 11 9.463978743834979 21 -61.14401226633092 72 1 10 9.463978743834979 20 -61.14401226633092 11 9.477211409423441 21 -61.14205017679284 72 1 10 9.477211409423441 20 -61.14205017679284 11 9.490419851684273 21 -61.1396520673574 72 1 10 9.490419851684273 20 -61.1396520673574 11 9.503595996174928 21 -61.13681793802461 72 1 10 9.503595996174928 20 -61.13681793802461 11 9.516731768452868 21 -61.13354778879447 72 1 10 9.516731768452868 20 -61.13354778879447 11 9.555166787830398 21 -61.12121004058793 72 1 10 9.555166787830398 20 -61.12121004058793 11 9.591797169299443 21 -61.10535183543238 72 1 10 9.591797169299443 20 -61.10535183543238 11 9.626433163460232 21 -61.08611851329363 72 1 10 9.626433163460232 20 -61.08611851329363 11 9.658885020912988 21 -61.06365541413746 72 1 10 9.658885020912988 20 -61.06365541413746 11 9.68896299225794 21 -61.03810787792966 72 1 10 9.68896299225794 20 -61.03810787792966 11 9.716477328095314 21 -61.009621244636 72 1 10 9.716477328095314 20 -61.009621244636 11 9.741238279025335 21 -60.97834085422227 72 1 10 9.741238279025335 20 -60.97834085422227 11 9.763056095648231 21 -60.94441204665426 72 1 10 9.763056095648231 20 -60.94441204665426 11 9.78153311166873 21 -60.90857699777575 72 1 10 9.78153311166873 20 -60.90857699777575 11 9.796247437463935 21 -60.87151059640935 72 1 10 9.796247437463935 20 -60.87151059640935 11 9.807166775263667 21 -60.8334510386101 72 1 10 9.807166775263667 20 -60.8334510386101 11 9.814258827297756 21 -60.79463652043302 72 1 10 9.814258827297756 20 -60.79463652043302 11 9.817491295796026 21 -60.75530523793316 72 1 10 9.817491295796026 20 -60.75530523793316 11 9.816831882988302 21 -60.71569538716554 72 1 10 9.816831882988302 20 -60.71569538716554 11 9.812248291104412 21 -60.6760451641852 72 1 10 9.812248291104412 20 -60.6760451641852 11 9.803708222374178 21 -60.63659276504718 72 1 10 9.803708222374178 20 -60.63659276504718 11 9.791370474167628 21 -60.59815774566965 72 1 10 9.791370474167628 20 -60.59815774566965 11 9.775512269012086 21 -60.56152736420061 72 1 10 9.775512269012086 20 -60.56152736420061 11 9.75627894687334 21 -60.52689137003982 72 1 10 9.75627894687334 20 -60.52689137003982 11 9.733815847717173 21 -60.49443951258706 72 1 10 9.733815847717173 20 -60.49443951258706 11 9.708268311509366 21 -60.46436154124179 72 1 10 9.708268311509366 20 -60.46436154124179 11 9.679781678215708 21 -60.43684720540474 72 1 10 9.679781678215708 20 -60.43684720540474 11 9.648501287801977 21 -60.41208625447472 72 1 10 9.648501287801977 20 -60.41208625447472 11 9.614572480233964 21 -60.39026843785182 72 1 10 9.614572480233964 20 -60.39026843785182 11 9.57860319374817 21 -60.37174903100797 72 1 10 9.57860319374817 20 -60.37174903100797 11 9.54140457338512 21 -60.35702864938086 72 1 10 9.54140457338512 20 -60.35702864938086 11 9.503232982695575 21 -60.34612747907685 72 1 10 9.503232982695575 20 -60.34612747907685 11 9.464344785230287 21 -60.3390657062023 72 1 10 9.464344785230287 20 -60.3390657062023 11 9.424996344540016 21 -60.33586351686356 72 1 10 9.424996344540016 20 -60.33586351686356 11 9.385444024175522 21 -60.33654109716733 72 1 10 9.385444024175522 20 -60.33654109716733 11 9.34594418768756 21 -60.341118633219 72 1 10 9.34594418768756 20 -60.341118633219 11 9.30675319862689 21 -60.34961631112587 72 1 10 9.30675319862689 20 -60.34961631112587 11 9.26831817924936 21 -60.36195405933243 72 1 10 9.26831817924936 20 -60.36195405933243 11 9.231687797780314 21 -60.37781226448796 72 1 10 9.231687797780314 20 -60.37781226448796 11 9.197051803619525 21 -60.39704558662671 72 1 10 9.197051803619525 20 -60.39704558662671 11 9.164599946166769 21 -60.41950868578288 72 1 10 9.164599946166769 20 -60.41950868578288 11 9.134521974821817 21 -60.44505622199068 72 1 10 9.134521974821817 20 -60.44505622199068 11 9.107007638984443 21 -60.47354285528434 72 1 10 9.107007638984443 20 -60.47354285528434 11 9.082246688054422 21 -60.50482324569808 72 1 10 9.082246688054422 20 -60.50482324569808 11 9.060428871431526 21 -60.53875205326609 72 1 10 9.060428871431526 20 -60.53875205326609 11 9.041951855411027 21 -60.5746436232424 72 1 10 9.041951855411027 20 -60.5746436232424 11 9.027237529615823 21 -60.61175039682151 72 1 10 9.027237529615823 20 -60.61175039682151 11 9.016318191816088 21 -60.6498341779484 72 1 10 9.016318191816088 20 -60.6498341779484 11 9.009226139782001 21 -60.68865677056802 72 1 10 9.009226139782001 20 -60.68865677056802 11 9.005993671283731 21 -60.72797997862534 72 1 10 9.005993671283731 20 -60.72797997862534 11 9.006653084091456 21 -60.76756560606533 72 1 10 9.006653084091456 20 -60.76756560606533 11 9.011236675975345 21 -60.80717545683295 72 1 10 9.011236675975345 20 -60.80717545683295 11 9.01977674470558 21 -60.84657133487316 72 1 10 9.01977674470558 20 -60.84657133487316 11 9.032114492912129 21 -60.88500635425069 72 1 10 9.032114492912129 20 -60.88500635425069 11 9.047972698067671 21 -60.92163673571974 72 1 10 9.047972698067671 20 -60.92163673571974 11 9.067206020206417 21 -60.95627272988052 72 1 10 9.067206020206417 20 -60.95627272988052 11 9.089669119362584 21 -60.98872458733328 72 1 10 9.089669119362584 20 -60.98872458733328 11 9.115216655570391 21 -61.01880255867823 72 1 10 9.115216655570391 20 -61.01880255867823 11 9.14370328886405 21 -61.04631689451593 72 1 10 9.14370328886405 20 -61.04631689451593 11 9.17498367927778 21 -61.07107784544563 72 1 10 9.17498367927778 20 -61.07107784544563 11 9.208912486845794 21 -61.09289566206853 97 0 75 2 76 1 98 0 0 POLYLINE 5 383 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 384 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.060428871431526 20 -67.98343114211673 30 0.0 0 VERTEX 5 385 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.082246688054422 20 -68.01735994968475 30 0.0 0 VERTEX 5 386 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.107007638984443 20 -68.04864034009847 30 0.0 0 VERTEX 5 387 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.134521974821817 20 -68.07712697339213 30 0.0 0 VERTEX 5 388 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.164599946166769 20 -68.10267450959994 30 0.0 0 VERTEX 5 389 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.197051803619525 20 -68.1251376087561 30 0.0 0 VERTEX 5 38A 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.231687797780314 20 -68.14437093089485 30 0.0 0 VERTEX 5 38B 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.26831817924936 20 -68.16022913605039 30 0.0 0 VERTEX 5 38C 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.30675319862689 20 -68.17256688425694 30 0.0 0 VERTEX 5 38D 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.319832113371918 20 -68.17583703348708 30 0.0 0 VERTEX 5 38E 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.332965530604115 20 -68.17867116281987 30 0.0 0 VERTEX 5 38F 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.346143357270302 20 -68.1810692722553 30 0.0 0 VERTEX 5 390 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.359355500317298 20 -68.18303136179338 30 0.0 0 VERTEX 5 391 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.372591866691925 20 -68.18455743143411 30 0.0 0 VERTEX 5 392 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.385842363341004 20 -68.1856474811775 30 0.0 0 VERTEX 5 393 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.399096897211354 20 -68.18630151102353 30 0.0 0 VERTEX 5 394 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.412345375249798 20 -68.1865195209722 30 0.0 0 VERTEX 5 395 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.438648208270532 20 -68.18565690136046 30 0.0 0 VERTEX 5 396 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.464799645493574 20 -68.18307442548695 30 0.0 0 VERTEX 5 397 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.49072903554667 20 -68.1787801677942 30 0.0 0 VERTEX 5 398 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.51636572705756 20 -68.17278220272478 30 0.0 0 VERTEX 5 399 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.541639068653991 20 -68.16508860472119 30 0.0 0 VERTEX 5 39A 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.566478408963706 20 -68.155707448226 30 0.0 0 VERTEX 5 39B 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.590813096614449 20 -68.14464680768175 30 0.0 0 VERTEX 5 39C 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.614572480233964 20 -68.13191475753099 30 0.0 0 VERTEX 5 39D 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.648501287801977 20 -68.1100969409081 30 0.0 0 VERTEX 5 39E 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.679781678215708 20 -68.08533598997808 30 0.0 0 VERTEX 5 39F 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.708268311509366 20 -68.0578216541407 30 0.0 0 VERTEX 5 3A0 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.733815847717173 20 -68.02774368279574 30 0.0 0 VERTEX 5 3A1 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.75627894687334 20 -67.99529182534299 30 0.0 0 VERTEX 5 3A2 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.775512269012086 20 -67.96065583118221 30 0.0 0 VERTEX 5 3A3 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.791370474167628 20 -67.92402544971316 30 0.0 0 VERTEX 5 3A4 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.803708222374178 20 -67.88559043033563 30 0.0 0 VERTEX 5 3A5 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.812248291104412 20 -67.84619455229542 30 0.0 0 VERTEX 5 3A6 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.816831882988302 20 -67.8065847015278 30 0.0 0 VERTEX 5 3A7 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.817491295796026 20 -67.7669990740878 30 0.0 0 VERTEX 5 3A8 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.814258827297756 20 -67.7276758660305 30 0.0 0 VERTEX 5 3A9 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.807166775263667 20 -67.68885327341087 30 0.0 0 VERTEX 5 3AA 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.796247437463935 20 -67.65076949228398 30 0.0 0 VERTEX 5 3AB 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.78153311166873 20 -67.61366271870487 30 0.0 0 VERTEX 5 3AC 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.763056095648231 20 -67.57777114872856 30 0.0 0 VERTEX 5 3AD 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.741238279025335 20 -67.54384974273287 30 0.0 0 VERTEX 5 3AE 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.716477328095314 20 -67.51258886555529 30 0.0 0 VERTEX 5 3AF 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.68896299225794 20 -67.48412981994032 30 0.0 0 VERTEX 5 3B0 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.658885020912988 20 -67.45861390863247 30 0.0 0 VERTEX 5 3B1 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.626433163460232 20 -67.43618243437628 30 0.0 0 VERTEX 5 3B2 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.591797169299443 20 -67.41697669991622 30 0.0 0 VERTEX 5 3B3 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.555166787830398 20 -67.40113800799682 30 0.0 0 VERTEX 5 3B4 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.516731768452868 20 -67.3888076613626 30 0.0 0 VERTEX 5 3B5 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.477074480335306 20 -67.38021813667179 30 0.0 0 VERTEX 5 3B6 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.437314243075315 20 -67.3756113307656 30 0.0 0 VERTEX 5 3B7 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.397671085232206 20 -67.3749488900419 30 0.0 0 VERTEX 5 3B8 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.358365035365289 20 -67.37819246089867 30 0.0 0 VERTEX 5 3B9 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.319616122033878 20 -67.3853036897338 30 0.0 0 VERTEX 5 3BA 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.281644373797283 20 -67.39624422294521 30 0.0 0 VERTEX 5 3BB 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.244669819214819 20 -67.41097570693083 30 0.0 0 VERTEX 5 3BC 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.208912486845794 20 -67.42945978808855 30 0.0 0 VERTEX 5 3BD 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.17498367927778 20 -67.45127726827634 30 0.0 0 VERTEX 5 3BE 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.14370328886405 20 -67.47603586416062 30 0.0 0 VERTEX 5 3BF 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.115216655570391 20 -67.50354380773098 30 0.0 0 VERTEX 5 3C0 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.089669119362584 20 -67.53360933097701 30 0.0 0 VERTEX 5 3C1 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.067206020206417 20 -67.56604066588831 30 0.0 0 VERTEX 5 3C2 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.047972698067671 20 -67.60064604445445 30 0.0 0 VERTEX 5 3C3 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.032114492912129 20 -67.63723369866503 30 0.0 0 VERTEX 5 3C4 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.01977674470558 20 -67.67561186050965 30 0.0 0 VERTEX 5 3C5 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.011236675975345 20 -67.71506425964768 30 0.0 0 VERTEX 5 3C6 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.006653084091456 20 -67.754714482628 30 0.0 0 VERTEX 5 3C7 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.005993671283731 20 -67.79432433339562 30 0.0 0 VERTEX 5 3C8 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.009226139782001 20 -67.8336556158955 30 0.0 0 VERTEX 5 3C9 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.016318191816088 20 -67.87247013407257 30 0.0 0 VERTEX 5 3CA 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.027237529615823 20 -67.91052969187182 30 0.0 0 VERTEX 5 3CB 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.041951855411027 20 -67.94759609323822 30 0.0 0 VERTEX 5 3CC 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.060428871431526 20 -67.98343114211673 30 0.0 0 VERTEX 5 3CD 330 383 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.060428871431526 20 -67.98343114211673 30 0.0 0 SEQEND 5 3CF 330 383 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 3CE 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 72 72 1 10 9.060428871431526 20 -67.98343114211673 11 9.082246688054422 21 -68.01735994968475 72 1 10 9.082246688054422 20 -68.01735994968475 11 9.107007638984443 21 -68.04864034009847 72 1 10 9.107007638984443 20 -68.04864034009847 11 9.134521974821817 21 -68.07712697339213 72 1 10 9.134521974821817 20 -68.07712697339213 11 9.164599946166769 21 -68.10267450959994 72 1 10 9.164599946166769 20 -68.10267450959994 11 9.197051803619525 21 -68.1251376087561 72 1 10 9.197051803619525 20 -68.1251376087561 11 9.231687797780314 21 -68.14437093089485 72 1 10 9.231687797780314 20 -68.14437093089485 11 9.26831817924936 21 -68.16022913605039 72 1 10 9.26831817924936 20 -68.16022913605039 11 9.30675319862689 21 -68.17256688425694 72 1 10 9.30675319862689 20 -68.17256688425694 11 9.319832113371918 21 -68.17583703348708 72 1 10 9.319832113371918 20 -68.17583703348708 11 9.332965530604115 21 -68.17867116281987 72 1 10 9.332965530604115 20 -68.17867116281987 11 9.346143357270302 21 -68.1810692722553 72 1 10 9.346143357270302 20 -68.1810692722553 11 9.359355500317298 21 -68.18303136179338 72 1 10 9.359355500317298 20 -68.18303136179338 11 9.372591866691925 21 -68.18455743143411 72 1 10 9.372591866691925 20 -68.18455743143411 11 9.385842363341004 21 -68.1856474811775 72 1 10 9.385842363341004 20 -68.1856474811775 11 9.399096897211354 21 -68.18630151102353 72 1 10 9.399096897211354 20 -68.18630151102353 11 9.412345375249798 21 -68.1865195209722 72 1 10 9.412345375249798 20 -68.1865195209722 11 9.438648208270532 21 -68.18565690136046 72 1 10 9.438648208270532 20 -68.18565690136046 11 9.464799645493574 21 -68.18307442548695 72 1 10 9.464799645493574 20 -68.18307442548695 11 9.49072903554667 21 -68.1787801677942 72 1 10 9.49072903554667 20 -68.1787801677942 11 9.51636572705756 21 -68.17278220272478 72 1 10 9.51636572705756 20 -68.17278220272478 11 9.541639068653991 21 -68.16508860472119 72 1 10 9.541639068653991 20 -68.16508860472119 11 9.566478408963706 21 -68.155707448226 72 1 10 9.566478408963706 20 -68.155707448226 11 9.590813096614449 21 -68.14464680768175 72 1 10 9.590813096614449 20 -68.14464680768175 11 9.614572480233964 21 -68.13191475753099 72 1 10 9.614572480233964 20 -68.13191475753099 11 9.648501287801977 21 -68.1100969409081 72 1 10 9.648501287801977 20 -68.1100969409081 11 9.679781678215708 21 -68.08533598997808 72 1 10 9.679781678215708 20 -68.08533598997808 11 9.708268311509366 21 -68.0578216541407 72 1 10 9.708268311509366 20 -68.0578216541407 11 9.733815847717173 21 -68.02774368279574 72 1 10 9.733815847717173 20 -68.02774368279574 11 9.75627894687334 21 -67.99529182534299 72 1 10 9.75627894687334 20 -67.99529182534299 11 9.775512269012086 21 -67.96065583118221 72 1 10 9.775512269012086 20 -67.96065583118221 11 9.791370474167628 21 -67.92402544971316 72 1 10 9.791370474167628 20 -67.92402544971316 11 9.803708222374178 21 -67.88559043033563 72 1 10 9.803708222374178 20 -67.88559043033563 11 9.812248291104412 21 -67.84619455229542 72 1 10 9.812248291104412 20 -67.84619455229542 11 9.816831882988302 21 -67.8065847015278 72 1 10 9.816831882988302 20 -67.8065847015278 11 9.817491295796026 21 -67.7669990740878 72 1 10 9.817491295796026 20 -67.7669990740878 11 9.814258827297756 21 -67.7276758660305 72 1 10 9.814258827297756 20 -67.7276758660305 11 9.807166775263667 21 -67.68885327341087 72 1 10 9.807166775263667 20 -67.68885327341087 11 9.796247437463935 21 -67.65076949228398 72 1 10 9.796247437463935 20 -67.65076949228398 11 9.78153311166873 21 -67.61366271870487 72 1 10 9.78153311166873 20 -67.61366271870487 11 9.763056095648231 21 -67.57777114872856 72 1 10 9.763056095648231 20 -67.57777114872856 11 9.741238279025335 21 -67.54384974273287 72 1 10 9.741238279025335 20 -67.54384974273287 11 9.716477328095314 21 -67.51258886555529 72 1 10 9.716477328095314 20 -67.51258886555529 11 9.68896299225794 21 -67.48412981994032 72 1 10 9.68896299225794 20 -67.48412981994032 11 9.658885020912988 21 -67.45861390863247 72 1 10 9.658885020912988 20 -67.45861390863247 11 9.626433163460232 21 -67.43618243437628 72 1 10 9.626433163460232 20 -67.43618243437628 11 9.591797169299443 21 -67.41697669991622 72 1 10 9.591797169299443 20 -67.41697669991622 11 9.555166787830398 21 -67.40113800799682 72 1 10 9.555166787830398 20 -67.40113800799682 11 9.516731768452868 21 -67.3888076613626 72 1 10 9.516731768452868 20 -67.3888076613626 11 9.477074480335306 21 -67.38021813667179 72 1 10 9.477074480335306 20 -67.38021813667179 11 9.437314243075315 21 -67.3756113307656 72 1 10 9.437314243075315 20 -67.3756113307656 11 9.397671085232206 21 -67.3749488900419 72 1 10 9.397671085232206 20 -67.3749488900419 11 9.358365035365289 21 -67.37819246089867 72 1 10 9.358365035365289 20 -67.37819246089867 11 9.319616122033878 21 -67.3853036897338 72 1 10 9.319616122033878 20 -67.3853036897338 11 9.281644373797283 21 -67.39624422294521 72 1 10 9.281644373797283 20 -67.39624422294521 11 9.244669819214819 21 -67.41097570693083 72 1 10 9.244669819214819 20 -67.41097570693083 11 9.208912486845794 21 -67.42945978808855 72 1 10 9.208912486845794 20 -67.42945978808855 11 9.17498367927778 21 -67.45127726827634 72 1 10 9.17498367927778 20 -67.45127726827634 11 9.14370328886405 21 -67.47603586416062 72 1 10 9.14370328886405 20 -67.47603586416062 11 9.115216655570391 21 -67.50354380773098 72 1 10 9.115216655570391 20 -67.50354380773098 11 9.089669119362584 21 -67.53360933097701 72 1 10 9.089669119362584 20 -67.53360933097701 11 9.067206020206417 21 -67.56604066588831 72 1 10 9.067206020206417 20 -67.56604066588831 11 9.047972698067671 21 -67.60064604445445 72 1 10 9.047972698067671 20 -67.60064604445445 11 9.032114492912129 21 -67.63723369866503 72 1 10 9.032114492912129 20 -67.63723369866503 11 9.01977674470558 21 -67.67561186050965 72 1 10 9.01977674470558 20 -67.67561186050965 11 9.011236675975345 21 -67.71506425964768 72 1 10 9.011236675975345 20 -67.71506425964768 11 9.006653084091456 21 -67.754714482628 72 1 10 9.006653084091456 20 -67.754714482628 11 9.005993671283731 21 -67.79432433339562 72 1 10 9.005993671283731 20 -67.79432433339562 11 9.009226139782001 21 -67.8336556158955 72 1 10 9.009226139782001 20 -67.8336556158955 11 9.016318191816088 21 -67.87247013407257 72 1 10 9.016318191816088 20 -67.87247013407257 11 9.027237529615823 21 -67.91052969187182 72 1 10 9.027237529615823 20 -67.91052969187182 11 9.041951855411027 21 -67.94759609323822 72 1 10 9.041951855411027 20 -67.94759609323822 11 9.060428871431526 21 -67.98343114211673 97 0 75 2 76 1 98 0 0 POLYLINE 5 3D0 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 3D1 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D2 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.324021739746705 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D3 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.717383488487775 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D4 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.110745237228842 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D5 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.504106985970554 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D6 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.897468734711623 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D7 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.290830483452693 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D8 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.684192232193761 20 -113.3074518556121 30 0.0 0 VERTEX 5 3D9 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.3074518556121 30 0.0 0 VERTEX 5 3DA 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.2773933975033 30 0.0 0 VERTEX 5 3DB 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.2473349393945 30 0.0 0 VERTEX 5 3DC 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.2172764812857 30 0.0 0 VERTEX 5 3DD 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.1872180231769 30 0.0 0 VERTEX 5 3DE 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.1571595650681 30 0.0 0 VERTEX 5 3DF 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.1271011069593 30 0.0 0 VERTEX 5 3E0 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.0970426488505 30 0.0 0 VERTEX 5 3E1 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E2 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.033456758723633 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E3 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.989359536512436 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E4 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.945262314301237 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E5 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E6 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.857067869878842 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E7 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.812970647667644 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E8 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.768873425456445 20 -113.0669841907417 30 0.0 0 VERTEX 5 3E9 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.0669841907417 30 0.0 0 VERTEX 5 3EA 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.1712198610173 30 0.0 0 VERTEX 5 3EB 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.2754555312928 30 0.0 0 VERTEX 5 3EC 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.3796912015684 30 0.0 0 VERTEX 5 3ED 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.483926871844 30 0.0 0 VERTEX 5 3EE 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.5881625421196 30 0.0 0 VERTEX 5 3EF 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.6923982123952 30 0.0 0 VERTEX 5 3F0 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.7966338826708 30 0.0 0 VERTEX 5 3F1 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F2 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.768873425456445 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F3 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.812970647667644 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F4 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.857067869878842 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F5 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F6 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.945262314301237 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F7 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.989359536512436 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F8 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.033456758723633 20 -113.9008695529464 30 0.0 0 VERTEX 5 3F9 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.9008695529464 30 0.0 0 VERTEX 5 3FA 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.8707895629908 30 0.0 0 VERTEX 5 3FB 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.8407095730352 30 0.0 0 VERTEX 5 3FC 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.8106295830796 30 0.0 0 VERTEX 5 3FD 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.7805495931241 30 0.0 0 VERTEX 5 3FE 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.7504696031685 30 0.0 0 VERTEX 5 3FF 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.7203896132129 30 0.0 0 VERTEX 5 400 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.6903096232573 30 0.0 0 VERTEX 5 401 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -113.6602296333017 30 0.0 0 VERTEX 5 402 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.684192232193761 20 -113.6602296333017 30 0.0 0 VERTEX 5 403 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.290830483452693 20 -113.6602296333017 30 0.0 0 VERTEX 5 404 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.897468734711623 20 -113.6602296333017 30 0.0 0 VERTEX 5 405 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.504106985970554 20 -113.6602296333017 30 0.0 0 VERTEX 5 406 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.110745237228842 20 -113.6602296333017 30 0.0 0 VERTEX 5 407 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.717383488487775 20 -113.6602296333017 30 0.0 0 VERTEX 5 408 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.324021739746705 20 -113.6602296333017 30 0.0 0 VERTEX 5 409 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.6602296333017 30 0.0 0 VERTEX 5 40A 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.6903096232573 30 0.0 0 VERTEX 5 40B 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.7203896132129 30 0.0 0 VERTEX 5 40C 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.7504696031685 30 0.0 0 VERTEX 5 40D 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.7805495931241 30 0.0 0 VERTEX 5 40E 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.8106295830796 30 0.0 0 VERTEX 5 40F 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.8407095730352 30 0.0 0 VERTEX 5 410 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.8707895629908 30 0.0 0 VERTEX 5 411 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.9008695529464 30 0.0 0 VERTEX 5 412 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.974757213216833 20 -113.9008695529464 30 0.0 0 VERTEX 5 413 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.01885443542803 20 -113.9008695529464 30 0.0 0 VERTEX 5 414 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.06295165763923 20 -113.9008695529464 30 0.0 0 VERTEX 5 415 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -113.9008695529464 30 0.0 0 VERTEX 5 416 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.15114610206163 20 -113.9008695529464 30 0.0 0 VERTEX 5 417 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.19524332427282 20 -113.9008695529464 30 0.0 0 VERTEX 5 418 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23934054648402 20 -113.9008695529464 30 0.0 0 VERTEX 5 419 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.9008695529464 30 0.0 0 VERTEX 5 41A 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.7966338826708 30 0.0 0 VERTEX 5 41B 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.6923982123952 30 0.0 0 VERTEX 5 41C 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.5881625421196 30 0.0 0 VERTEX 5 41D 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.483926871844 30 0.0 0 VERTEX 5 41E 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.3796912015684 30 0.0 0 VERTEX 5 41F 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.2754555312928 30 0.0 0 VERTEX 5 420 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.1712198610173 30 0.0 0 VERTEX 5 421 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -113.0669841907417 30 0.0 0 VERTEX 5 422 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23934054648402 20 -113.0669841907417 30 0.0 0 VERTEX 5 423 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.19524332427282 20 -113.0669841907417 30 0.0 0 VERTEX 5 424 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.15114610206163 20 -113.0669841907417 30 0.0 0 VERTEX 5 425 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -113.0669841907417 30 0.0 0 VERTEX 5 426 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.06295165763923 20 -113.0669841907417 30 0.0 0 VERTEX 5 427 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.01885443542803 20 -113.0669841907417 30 0.0 0 VERTEX 5 428 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.974757213216833 20 -113.0669841907417 30 0.0 0 VERTEX 5 429 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.0669841907417 30 0.0 0 VERTEX 5 42A 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.0970426488505 30 0.0 0 VERTEX 5 42B 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.1271011069593 30 0.0 0 VERTEX 5 42C 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.1571595650681 30 0.0 0 VERTEX 5 42D 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.1872180231769 30 0.0 0 VERTEX 5 42E 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.2172764812857 30 0.0 0 VERTEX 5 42F 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.2473349393945 30 0.0 0 VERTEX 5 430 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.2773933975033 30 0.0 0 VERTEX 5 431 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.3074518556121 30 0.0 0 VERTEX 5 432 330 3D0 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.930659991005635 20 -113.3074518556121 30 0.0 0 SEQEND 5 434 330 3D0 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 433 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 96 72 1 10 9.930659991005635 20 -113.3074518556121 11 9.324021739746705 21 -113.3074518556121 72 1 10 9.324021739746705 20 -113.3074518556121 11 8.717383488487775 21 -113.3074518556121 72 1 10 8.717383488487775 20 -113.3074518556121 11 8.110745237228842 21 -113.3074518556121 72 1 10 8.110745237228842 20 -113.3074518556121 11 7.504106985970554 21 -113.3074518556121 72 1 10 7.504106985970554 20 -113.3074518556121 11 6.897468734711623 21 -113.3074518556121 72 1 10 6.897468734711623 20 -113.3074518556121 11 6.290830483452693 21 -113.3074518556121 72 1 10 6.290830483452693 20 -113.3074518556121 11 5.684192232193761 21 -113.3074518556121 72 1 10 5.684192232193761 20 -113.3074518556121 11 5.077553980934831 21 -113.3074518556121 72 1 10 5.077553980934831 20 -113.3074518556121 11 5.077553980934831 21 -113.2773933975033 72 1 10 5.077553980934831 20 -113.2773933975033 11 5.077553980934831 21 -113.2473349393945 72 1 10 5.077553980934831 20 -113.2473349393945 11 5.077553980934831 21 -113.2172764812857 72 1 10 5.077553980934831 20 -113.2172764812857 11 5.077553980934831 21 -113.1872180231769 72 1 10 5.077553980934831 20 -113.1872180231769 11 5.077553980934831 21 -113.1571595650681 72 1 10 5.077553980934831 20 -113.1571595650681 11 5.077553980934831 21 -113.1271011069593 72 1 10 5.077553980934831 20 -113.1271011069593 11 5.077553980934831 21 -113.0970426488505 72 1 10 5.077553980934831 20 -113.0970426488505 11 5.077553980934831 21 -113.0669841907417 72 1 10 5.077553980934831 20 -113.0669841907417 11 5.033456758723633 21 -113.0669841907417 72 1 10 5.033456758723633 20 -113.0669841907417 11 4.989359536512436 21 -113.0669841907417 72 1 10 4.989359536512436 20 -113.0669841907417 11 4.945262314301237 21 -113.0669841907417 72 1 10 4.945262314301237 20 -113.0669841907417 11 4.901165092090039 21 -113.0669841907417 72 1 10 4.901165092090039 20 -113.0669841907417 11 4.857067869878842 21 -113.0669841907417 72 1 10 4.857067869878842 20 -113.0669841907417 11 4.812970647667644 21 -113.0669841907417 72 1 10 4.812970647667644 20 -113.0669841907417 11 4.768873425456445 21 -113.0669841907417 72 1 10 4.768873425456445 20 -113.0669841907417 11 4.724776203245248 21 -113.0669841907417 72 1 10 4.724776203245248 20 -113.0669841907417 11 4.724776203245248 21 -113.1712198610173 72 1 10 4.724776203245248 20 -113.1712198610173 11 4.724776203245248 21 -113.2754555312928 72 1 10 4.724776203245248 20 -113.2754555312928 11 4.724776203245248 21 -113.3796912015684 72 1 10 4.724776203245248 20 -113.3796912015684 11 4.724776203245248 21 -113.483926871844 72 1 10 4.724776203245248 20 -113.483926871844 11 4.724776203245248 21 -113.5881625421196 72 1 10 4.724776203245248 20 -113.5881625421196 11 4.724776203245248 21 -113.6923982123952 72 1 10 4.724776203245248 20 -113.6923982123952 11 4.724776203245248 21 -113.7966338826708 72 1 10 4.724776203245248 20 -113.7966338826708 11 4.724776203245248 21 -113.9008695529464 72 1 10 4.724776203245248 20 -113.9008695529464 11 4.768873425456445 21 -113.9008695529464 72 1 10 4.768873425456445 20 -113.9008695529464 11 4.812970647667644 21 -113.9008695529464 72 1 10 4.812970647667644 20 -113.9008695529464 11 4.857067869878842 21 -113.9008695529464 72 1 10 4.857067869878842 20 -113.9008695529464 11 4.901165092090039 21 -113.9008695529464 72 1 10 4.901165092090039 20 -113.9008695529464 11 4.945262314301237 21 -113.9008695529464 72 1 10 4.945262314301237 20 -113.9008695529464 11 4.989359536512436 21 -113.9008695529464 72 1 10 4.989359536512436 20 -113.9008695529464 11 5.033456758723633 21 -113.9008695529464 72 1 10 5.033456758723633 20 -113.9008695529464 11 5.077553980934831 21 -113.9008695529464 72 1 10 5.077553980934831 20 -113.9008695529464 11 5.077553980934831 21 -113.8707895629908 72 1 10 5.077553980934831 20 -113.8707895629908 11 5.077553980934831 21 -113.8407095730352 72 1 10 5.077553980934831 20 -113.8407095730352 11 5.077553980934831 21 -113.8106295830796 72 1 10 5.077553980934831 20 -113.8106295830796 11 5.077553980934831 21 -113.7805495931241 72 1 10 5.077553980934831 20 -113.7805495931241 11 5.077553980934831 21 -113.7504696031685 72 1 10 5.077553980934831 20 -113.7504696031685 11 5.077553980934831 21 -113.7203896132129 72 1 10 5.077553980934831 20 -113.7203896132129 11 5.077553980934831 21 -113.6903096232573 72 1 10 5.077553980934831 20 -113.6903096232573 11 5.077553980934831 21 -113.6602296333017 72 1 10 5.077553980934831 20 -113.6602296333017 11 5.684192232193761 21 -113.6602296333017 72 1 10 5.684192232193761 20 -113.6602296333017 11 6.290830483452693 21 -113.6602296333017 72 1 10 6.290830483452693 20 -113.6602296333017 11 6.897468734711623 21 -113.6602296333017 72 1 10 6.897468734711623 20 -113.6602296333017 11 7.504106985970554 21 -113.6602296333017 72 1 10 7.504106985970554 20 -113.6602296333017 11 8.110745237228842 21 -113.6602296333017 72 1 10 8.110745237228842 20 -113.6602296333017 11 8.717383488487775 21 -113.6602296333017 72 1 10 8.717383488487775 20 -113.6602296333017 11 9.324021739746705 21 -113.6602296333017 72 1 10 9.324021739746705 20 -113.6602296333017 11 9.930659991005635 21 -113.6602296333017 72 1 10 9.930659991005635 20 -113.6602296333017 11 9.930659991005635 21 -113.6903096232573 72 1 10 9.930659991005635 20 -113.6903096232573 11 9.930659991005635 21 -113.7203896132129 72 1 10 9.930659991005635 20 -113.7203896132129 11 9.930659991005635 21 -113.7504696031685 72 1 10 9.930659991005635 20 -113.7504696031685 11 9.930659991005635 21 -113.7805495931241 72 1 10 9.930659991005635 20 -113.7805495931241 11 9.930659991005635 21 -113.8106295830796 72 1 10 9.930659991005635 20 -113.8106295830796 11 9.930659991005635 21 -113.8407095730352 72 1 10 9.930659991005635 20 -113.8407095730352 11 9.930659991005635 21 -113.8707895629908 72 1 10 9.930659991005635 20 -113.8707895629908 11 9.930659991005635 21 -113.9008695529464 72 1 10 9.930659991005635 20 -113.9008695529464 11 9.974757213216833 21 -113.9008695529464 72 1 10 9.974757213216833 20 -113.9008695529464 11 10.01885443542803 21 -113.9008695529464 72 1 10 10.01885443542803 20 -113.9008695529464 11 10.06295165763923 21 -113.9008695529464 72 1 10 10.06295165763923 20 -113.9008695529464 11 10.10704887985043 21 -113.9008695529464 72 1 10 10.10704887985043 20 -113.9008695529464 11 10.15114610206163 21 -113.9008695529464 72 1 10 10.15114610206163 20 -113.9008695529464 11 10.19524332427282 21 -113.9008695529464 72 1 10 10.19524332427282 20 -113.9008695529464 11 10.23934054648402 21 -113.9008695529464 72 1 10 10.23934054648402 20 -113.9008695529464 11 10.28343776869522 21 -113.9008695529464 72 1 10 10.28343776869522 20 -113.9008695529464 11 10.28343776869522 21 -113.7966338826708 72 1 10 10.28343776869522 20 -113.7966338826708 11 10.28343776869522 21 -113.6923982123952 72 1 10 10.28343776869522 20 -113.6923982123952 11 10.28343776869522 21 -113.5881625421196 72 1 10 10.28343776869522 20 -113.5881625421196 11 10.28343776869522 21 -113.483926871844 72 1 10 10.28343776869522 20 -113.483926871844 11 10.28343776869522 21 -113.3796912015684 72 1 10 10.28343776869522 20 -113.3796912015684 11 10.28343776869522 21 -113.2754555312928 72 1 10 10.28343776869522 20 -113.2754555312928 11 10.28343776869522 21 -113.1712198610173 72 1 10 10.28343776869522 20 -113.1712198610173 11 10.28343776869522 21 -113.0669841907417 72 1 10 10.28343776869522 20 -113.0669841907417 11 10.23934054648402 21 -113.0669841907417 72 1 10 10.23934054648402 20 -113.0669841907417 11 10.19524332427282 21 -113.0669841907417 72 1 10 10.19524332427282 20 -113.0669841907417 11 10.15114610206163 21 -113.0669841907417 72 1 10 10.15114610206163 20 -113.0669841907417 11 10.10704887985043 21 -113.0669841907417 72 1 10 10.10704887985043 20 -113.0669841907417 11 10.06295165763923 21 -113.0669841907417 72 1 10 10.06295165763923 20 -113.0669841907417 11 10.01885443542803 21 -113.0669841907417 72 1 10 10.01885443542803 20 -113.0669841907417 11 9.974757213216833 21 -113.0669841907417 72 1 10 9.974757213216833 20 -113.0669841907417 11 9.930659991005635 21 -113.0669841907417 72 1 10 9.930659991005635 20 -113.0669841907417 11 9.930659991005635 21 -113.0970426488505 72 1 10 9.930659991005635 20 -113.0970426488505 11 9.930659991005635 21 -113.1271011069593 72 1 10 9.930659991005635 20 -113.1271011069593 11 9.930659991005635 21 -113.1571595650681 72 1 10 9.930659991005635 20 -113.1571595650681 11 9.930659991005635 21 -113.1872180231769 72 1 10 9.930659991005635 20 -113.1872180231769 11 9.930659991005635 21 -113.2172764812857 72 1 10 9.930659991005635 20 -113.2172764812857 11 9.930659991005635 21 -113.2473349393945 72 1 10 9.930659991005635 20 -113.2473349393945 11 9.930659991005635 21 -113.2773933975033 72 1 10 9.930659991005635 20 -113.2773933975033 11 9.930659991005635 21 -113.3074518556121 97 0 75 2 76 1 98 0 0 POLYLINE 5 435 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 436 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -112.3900229278901 30 0.0 0 VERTEX 5 437 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.108198282824512 20 -112.3438556204718 30 0.0 0 VERTEX 5 438 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.171042482663259 20 -112.2118549702049 30 0.0 0 VERTEX 5 439 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.317614614458035 20 -112.0037728850713 30 0.0 0 VERTEX 5 43A 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.569947813298278 20 -111.7293612730531 30 0.0 0 VERTEX 5 43B 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.950075214275356 20 -111.3983720421322 30 0.0 0 VERTEX 5 43C 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.480029952479991 20 -111.0205571002905 30 0.0 0 VERTEX 5 43D 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.181845163002908 20 -110.6056683555102 30 0.0 0 VERTEX 5 43E 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -110.1634577157731 30 0.0 0 VERTEX 5 43F 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.073973638536977 20 -110.1278864320177 30 0.0 0 VERTEX 5 440 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.063703620491788 20 -110.0947657415742 30 0.0 0 VERTEX 5 441 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.047450440521825 20 -110.0648021581653 30 0.0 0 VERTEX 5 442 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.025920612349649 20 -110.0387021955135 30 0.0 0 VERTEX 5 443 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.999820649697821 20 -110.0171723673413 30 0.0 0 VERTEX 5 444 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.969857066288903 20 -110.0009191873714 30 0.0 0 VERTEX 5 445 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.936736375845456 20 -109.9906491693262 30 0.0 0 VERTEX 5 446 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -109.9870688269283 30 0.0 0 VERTEX 5 447 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.865593808334623 20 -109.9906491693262 30 0.0 0 VERTEX 5 448 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.832473117891175 20 -110.0009191873714 30 0.0 0 VERTEX 5 449 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.802509534482257 20 -110.0171723673413 30 0.0 0 VERTEX 5 44A 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.776409571830429 20 -110.0387021955135 30 0.0 0 VERTEX 5 44B 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.754879743658254 20 -110.0648021581653 30 0.0 0 VERTEX 5 44C 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.738626563688292 20 -110.0947657415742 30 0.0 0 VERTEX 5 44D 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.728356545643102 20 -110.1278864320177 30 0.0 0 VERTEX 5 44E 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -110.1634577157731 30 0.0 0 VERTEX 5 44F 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -110.4638269783933 30 0.0 0 VERTEX 5 450 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -110.7641962410136 30 0.0 0 VERTEX 5 451 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -111.0645655036338 30 0.0 0 VERTEX 5 452 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -111.364934766254 30 0.0 0 VERTEX 5 453 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -111.6653040288742 30 0.0 0 VERTEX 5 454 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -111.9656732914944 30 0.0 0 VERTEX 5 455 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -112.2660425541146 30 0.0 0 VERTEX 5 456 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.724776203245248 20 -112.5664118167349 30 0.0 0 VERTEX 5 457 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.728356545643102 20 -112.6019831004903 30 0.0 0 VERTEX 5 458 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.738626563688292 20 -112.6351037909337 30 0.0 0 VERTEX 5 459 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.754879743658254 20 -112.6650673743427 30 0.0 0 VERTEX 5 45A 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.776409571830429 20 -112.6911673369945 30 0.0 0 VERTEX 5 45B 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.802509534482257 20 -112.7126971651667 30 0.0 0 VERTEX 5 45C 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.832473117891175 20 -112.7289503451366 30 0.0 0 VERTEX 5 45D 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.865593808334623 20 -112.7392203631818 30 0.0 0 VERTEX 5 45E 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.901165092090039 20 -112.7428007055797 30 0.0 0 VERTEX 5 45F 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.936736375845456 20 -112.7392203631818 30 0.0 0 VERTEX 5 460 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.969857066288903 20 -112.7289503451366 30 0.0 0 VERTEX 5 461 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.999820649697821 20 -112.7126971651667 30 0.0 0 VERTEX 5 462 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.025920612349649 20 -112.6911673369945 30 0.0 0 VERTEX 5 463 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.047450440521825 20 -112.6650673743427 30 0.0 0 VERTEX 5 464 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.063703620491788 20 -112.6351037909337 30 0.0 0 VERTEX 5 465 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.073973638536977 20 -112.6019831004903 30 0.0 0 VERTEX 5 466 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -112.5664118167349 30 0.0 0 VERTEX 5 467 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -112.3820615275421 30 0.0 0 VERTEX 5 468 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -112.1977112383494 30 0.0 0 VERTEX 5 469 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -112.0133609491567 30 0.0 0 VERTEX 5 46A 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -111.8290106599639 30 0.0 0 VERTEX 5 46B 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -111.6446603707712 30 0.0 0 VERTEX 5 46C 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -111.4603100815785 30 0.0 0 VERTEX 5 46D 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -111.2759597923857 30 0.0 0 VERTEX 5 46E 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.077553980934831 20 -111.091609503193 30 0.0 0 VERTEX 5 46F 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.417112466331416 20 -111.4422264002512 30 0.0 0 VERTEX 5 470 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.857496011116704 20 -111.7605477980722 30 0.0 0 VERTEX 5 471 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.389596139448908 20 -112.0421188753089 30 0.0 0 VERTEX 5 472 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.004304375486238 20 -112.2824848106142 30 0.0 0 VERTEX 5 473 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.692512243386908 20 -112.477190782641 30 0.0 0 VERTEX 5 474 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.445111267308487 20 -112.6217819700422 30 0.0 0 VERTEX 5 475 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.25299297141047 20 -112.7118035514708 30 0.0 0 VERTEX 5 476 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -112.7428007055797 30 0.0 0 VERTEX 5 477 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.14262016360584 20 -112.7392203631818 30 0.0 0 VERTEX 5 478 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.17574085404929 20 -112.7289503451366 30 0.0 0 VERTEX 5 479 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.20570443745821 20 -112.7126971651667 30 0.0 0 VERTEX 5 47A 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23180440011004 20 -112.6911673369945 30 0.0 0 VERTEX 5 47B 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25333422828221 20 -112.6650673743427 30 0.0 0 VERTEX 5 47C 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.26958740825217 20 -112.6351037909337 30 0.0 0 VERTEX 5 47D 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.27985742629737 20 -112.6019831004903 30 0.0 0 VERTEX 5 47E 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.28343776869522 20 -112.5664118167349 30 0.0 0 VERTEX 5 47F 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.27985742629737 20 -112.5308405329795 30 0.0 0 VERTEX 5 480 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.26958740825217 20 -112.497719842536 30 0.0 0 VERTEX 5 481 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.25333422828221 20 -112.4677562591271 30 0.0 0 VERTEX 5 482 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.23180440011004 20 -112.4416562964753 30 0.0 0 VERTEX 5 483 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.20570443745821 20 -112.4201264683031 30 0.0 0 VERTEX 5 484 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.17574085404929 20 -112.4038732883331 30 0.0 0 VERTEX 5 485 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.14262016360584 20 -112.3936032702879 30 0.0 0 VERTEX 5 486 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -112.3900229278901 30 0.0 0 VERTEX 5 487 330 435 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.10704887985043 20 -112.3900229278901 30 0.0 0 SEQEND 5 489 330 435 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 488 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 80 72 1 10 10.10704887985043 20 -112.3900229278901 11 9.108198282824512 21 -112.3438556204718 72 1 10 9.108198282824512 20 -112.3438556204718 11 8.171042482663259 21 -112.2118549702049 72 1 10 8.171042482663259 20 -112.2118549702049 11 7.317614614458035 21 -112.0037728850713 72 1 10 7.317614614458035 20 -112.0037728850713 11 6.569947813298278 21 -111.7293612730531 72 1 10 6.569947813298278 20 -111.7293612730531 11 5.950075214275356 21 -111.3983720421322 72 1 10 5.950075214275356 20 -111.3983720421322 11 5.480029952479991 21 -111.0205571002905 72 1 10 5.480029952479991 20 -111.0205571002905 11 5.181845163002908 21 -110.6056683555102 72 1 10 5.181845163002908 20 -110.6056683555102 11 5.077553980934831 21 -110.1634577157731 72 1 10 5.077553980934831 20 -110.1634577157731 11 5.073973638536977 21 -110.1278864320177 72 1 10 5.073973638536977 20 -110.1278864320177 11 5.063703620491788 21 -110.0947657415742 72 1 10 5.063703620491788 20 -110.0947657415742 11 5.047450440521825 21 -110.0648021581653 72 1 10 5.047450440521825 20 -110.0648021581653 11 5.025920612349649 21 -110.0387021955135 72 1 10 5.025920612349649 20 -110.0387021955135 11 4.999820649697821 21 -110.0171723673413 72 1 10 4.999820649697821 20 -110.0171723673413 11 4.969857066288903 21 -110.0009191873714 72 1 10 4.969857066288903 20 -110.0009191873714 11 4.936736375845456 21 -109.9906491693262 72 1 10 4.936736375845456 20 -109.9906491693262 11 4.901165092090039 21 -109.9870688269283 72 1 10 4.901165092090039 20 -109.9870688269283 11 4.865593808334623 21 -109.9906491693262 72 1 10 4.865593808334623 20 -109.9906491693262 11 4.832473117891175 21 -110.0009191873714 72 1 10 4.832473117891175 20 -110.0009191873714 11 4.802509534482257 21 -110.0171723673413 72 1 10 4.802509534482257 20 -110.0171723673413 11 4.776409571830429 21 -110.0387021955135 72 1 10 4.776409571830429 20 -110.0387021955135 11 4.754879743658254 21 -110.0648021581653 72 1 10 4.754879743658254 20 -110.0648021581653 11 4.738626563688292 21 -110.0947657415742 72 1 10 4.738626563688292 20 -110.0947657415742 11 4.728356545643102 21 -110.1278864320177 72 1 10 4.728356545643102 20 -110.1278864320177 11 4.724776203245248 21 -110.1634577157731 72 1 10 4.724776203245248 20 -110.1634577157731 11 4.724776203245248 21 -110.4638269783933 72 1 10 4.724776203245248 20 -110.4638269783933 11 4.724776203245248 21 -110.7641962410136 72 1 10 4.724776203245248 20 -110.7641962410136 11 4.724776203245248 21 -111.0645655036338 72 1 10 4.724776203245248 20 -111.0645655036338 11 4.724776203245248 21 -111.364934766254 72 1 10 4.724776203245248 20 -111.364934766254 11 4.724776203245248 21 -111.6653040288742 72 1 10 4.724776203245248 20 -111.6653040288742 11 4.724776203245248 21 -111.9656732914944 72 1 10 4.724776203245248 20 -111.9656732914944 11 4.724776203245248 21 -112.2660425541146 72 1 10 4.724776203245248 20 -112.2660425541146 11 4.724776203245248 21 -112.5664118167349 72 1 10 4.724776203245248 20 -112.5664118167349 11 4.728356545643102 21 -112.6019831004903 72 1 10 4.728356545643102 20 -112.6019831004903 11 4.738626563688292 21 -112.6351037909337 72 1 10 4.738626563688292 20 -112.6351037909337 11 4.754879743658254 21 -112.6650673743427 72 1 10 4.754879743658254 20 -112.6650673743427 11 4.776409571830429 21 -112.6911673369945 72 1 10 4.776409571830429 20 -112.6911673369945 11 4.802509534482257 21 -112.7126971651667 72 1 10 4.802509534482257 20 -112.7126971651667 11 4.832473117891175 21 -112.7289503451366 72 1 10 4.832473117891175 20 -112.7289503451366 11 4.865593808334623 21 -112.7392203631818 72 1 10 4.865593808334623 20 -112.7392203631818 11 4.901165092090039 21 -112.7428007055797 72 1 10 4.901165092090039 20 -112.7428007055797 11 4.936736375845456 21 -112.7392203631818 72 1 10 4.936736375845456 20 -112.7392203631818 11 4.969857066288903 21 -112.7289503451366 72 1 10 4.969857066288903 20 -112.7289503451366 11 4.999820649697821 21 -112.7126971651667 72 1 10 4.999820649697821 20 -112.7126971651667 11 5.025920612349649 21 -112.6911673369945 72 1 10 5.025920612349649 20 -112.6911673369945 11 5.047450440521825 21 -112.6650673743427 72 1 10 5.047450440521825 20 -112.6650673743427 11 5.063703620491788 21 -112.6351037909337 72 1 10 5.063703620491788 20 -112.6351037909337 11 5.073973638536977 21 -112.6019831004903 72 1 10 5.073973638536977 20 -112.6019831004903 11 5.077553980934831 21 -112.5664118167349 72 1 10 5.077553980934831 20 -112.5664118167349 11 5.077553980934831 21 -112.3820615275421 72 1 10 5.077553980934831 20 -112.3820615275421 11 5.077553980934831 21 -112.1977112383494 72 1 10 5.077553980934831 20 -112.1977112383494 11 5.077553980934831 21 -112.0133609491567 72 1 10 5.077553980934831 20 -112.0133609491567 11 5.077553980934831 21 -111.8290106599639 72 1 10 5.077553980934831 20 -111.8290106599639 11 5.077553980934831 21 -111.6446603707712 72 1 10 5.077553980934831 20 -111.6446603707712 11 5.077553980934831 21 -111.4603100815785 72 1 10 5.077553980934831 20 -111.4603100815785 11 5.077553980934831 21 -111.2759597923857 72 1 10 5.077553980934831 20 -111.2759597923857 11 5.077553980934831 21 -111.091609503193 72 1 10 5.077553980934831 20 -111.091609503193 11 5.417112466331416 21 -111.4422264002512 72 1 10 5.417112466331416 20 -111.4422264002512 11 5.857496011116704 21 -111.7605477980722 72 1 10 5.857496011116704 20 -111.7605477980722 11 6.389596139448908 21 -112.0421188753089 72 1 10 6.389596139448908 20 -112.0421188753089 11 7.004304375486238 21 -112.2824848106142 72 1 10 7.004304375486238 20 -112.2824848106142 11 7.692512243386908 21 -112.477190782641 72 1 10 7.692512243386908 20 -112.477190782641 11 8.445111267308487 21 -112.6217819700422 72 1 10 8.445111267308487 20 -112.6217819700422 11 9.25299297141047 21 -112.7118035514708 72 1 10 9.25299297141047 20 -112.7118035514708 11 10.10704887985043 21 -112.7428007055797 72 1 10 10.10704887985043 20 -112.7428007055797 11 10.14262016360584 21 -112.7392203631818 72 1 10 10.14262016360584 20 -112.7392203631818 11 10.17574085404929 21 -112.7289503451366 72 1 10 10.17574085404929 20 -112.7289503451366 11 10.20570443745821 21 -112.7126971651667 72 1 10 10.20570443745821 20 -112.7126971651667 11 10.23180440011004 21 -112.6911673369945 72 1 10 10.23180440011004 20 -112.6911673369945 11 10.25333422828221 21 -112.6650673743427 72 1 10 10.25333422828221 20 -112.6650673743427 11 10.26958740825217 21 -112.6351037909337 72 1 10 10.26958740825217 20 -112.6351037909337 11 10.27985742629737 21 -112.6019831004903 72 1 10 10.27985742629737 20 -112.6019831004903 11 10.28343776869522 21 -112.5664118167349 72 1 10 10.28343776869522 20 -112.5664118167349 11 10.27985742629737 21 -112.5308405329795 72 1 10 10.27985742629737 20 -112.5308405329795 11 10.26958740825217 21 -112.497719842536 72 1 10 10.26958740825217 20 -112.497719842536 11 10.25333422828221 21 -112.4677562591271 72 1 10 10.25333422828221 20 -112.4677562591271 11 10.23180440011004 21 -112.4416562964753 72 1 10 10.23180440011004 20 -112.4416562964753 11 10.20570443745821 21 -112.4201264683031 72 1 10 10.20570443745821 20 -112.4201264683031 11 10.17574085404929 21 -112.4038732883331 72 1 10 10.17574085404929 20 -112.4038732883331 11 10.14262016360584 21 -112.3936032702879 72 1 10 10.14262016360584 20 -112.3936032702879 11 10.10704887985043 21 -112.3900229278901 97 0 75 2 76 1 98 0 0 INSERT 5 48B 330 1F 100 AcDbEntity 8 Graphics 100 AcDbBlockReference 2 block 2 10 0.0 20 0.0 30 0.0 0 POLYLINE 5 548 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 549 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.49081081401837 20 -1.187163797704678 30 0.0 0 VERTEX 5 54A 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 15.90150569941961 20 -1.776468912303445 30 0.0 0 VERTEX 5 54B 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 15.31220058482084 20 -2.365774026902213 30 0.0 0 VERTEX 5 54C 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 14.72289547022207 20 -2.95507914150098 30 0.0 0 VERTEX 5 54D 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 14.1335903556233 20 -3.544384256099748 30 0.0 0 VERTEX 5 54E 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 13.54428524102454 20 -4.133689370698515 30 0.0 0 VERTEX 5 54F 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 12.95498012642577 20 -4.722994485297283 30 0.0 0 VERTEX 5 550 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 12.365675011827 20 -5.31229959989605 30 0.0 0 VERTEX 5 551 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.77636989722824 20 -5.901604714494818 30 0.0 0 VERTEX 5 552 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.44772575964807 20 -5.901604714494818 30 0.0 0 VERTEX 5 553 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.119081622067904 20 -5.901604714494818 30 0.0 0 VERTEX 5 554 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.790437484488381 20 -5.901604714494818 30 0.0 0 VERTEX 5 555 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.461793346908216 20 -5.901604714494818 30 0.0 0 VERTEX 5 556 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.13314920932805 20 -5.901604714494818 30 0.0 0 VERTEX 5 557 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 3.804505071747885 20 -5.901604714494818 30 0.0 0 VERTEX 5 558 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.47586093416772 20 -5.901604714494818 30 0.0 0 VERTEX 5 559 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -5.901604714494818 30 0.0 0 VERTEX 5 55A 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -20.48574896404974 30 0.0 0 VERTEX 5 55B 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -35.06989321360466 30 0.0 0 VERTEX 5 55C 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -49.65403746315958 30 0.0 0 VERTEX 5 55D 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -64.23818171271449 30 0.0 0 VERTEX 5 55E 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -78.82232596226942 30 0.0 0 VERTEX 5 55F 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -93.40647021182433 30 0.0 0 VERTEX 5 560 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -107.9906144613793 30 0.0 0 VERTEX 5 561 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.147216796587554 20 -122.5747587109342 30 0.0 0 VERTEX 5 562 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.610657415296347 20 -122.5747587109342 30 0.0 0 VERTEX 5 563 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.074098034004498 20 -122.5747587109342 30 0.0 0 VERTEX 5 564 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.53753865271329 20 -122.5747587109342 30 0.0 0 VERTEX 5 565 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 15.00097927142208 20 -122.5747587109342 30 0.0 0 VERTEX 5 566 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.46441989013088 20 -122.5747587109342 30 0.0 0 VERTEX 5 567 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.92786050883967 20 -122.5747587109342 30 0.0 0 VERTEX 5 568 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.39130112754846 20 -122.5747587109342 30 0.0 0 VERTEX 5 569 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -122.5747587109342 30 0.0 0 VERTEX 5 56A 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -107.4013093467805 30 0.0 0 VERTEX 5 56B 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -92.2278599826268 30 0.0 0 VERTEX 5 56C 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -77.05441061847311 30 0.0 0 VERTEX 5 56D 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -61.88096125431942 30 0.0 0 VERTEX 5 56E 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -46.70751189016574 30 0.0 0 VERTEX 5 56F 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -31.53406252601205 30 0.0 0 VERTEX 5 570 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -16.36061316185836 30 0.0 0 VERTEX 5 571 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.85474174625725 20 -1.187163797704678 30 0.0 0 VERTEX 5 572 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.30925037972739 20 -1.187163797704678 30 0.0 0 VERTEX 5 573 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.76375901319754 20 -1.187163797704678 30 0.0 0 VERTEX 5 574 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.21826764666768 20 -1.187163797704678 30 0.0 0 VERTEX 5 575 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.67277628013781 20 -1.187163797704678 30 0.0 0 VERTEX 5 576 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.12728491360796 20 -1.187163797704678 30 0.0 0 VERTEX 5 577 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.5817935470781 20 -1.187163797704678 30 0.0 0 VERTEX 5 578 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.03630218054824 20 -1.187163797704678 30 0.0 0 VERTEX 5 579 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.49081081401837 20 -1.187163797704678 30 0.0 0 VERTEX 5 57A 330 548 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.49081081401837 20 -1.187163797704678 30 0.0 0 SEQEND 5 57B 330 548 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 57C 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 57D 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -122.2219809332446 30 0.0 0 VERTEX 5 57E 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.12671779428127 20 -122.2219809332446 30 0.0 0 VERTEX 5 57F 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.75147161999488 20 -122.2219809332446 30 0.0 0 VERTEX 5 580 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.37622544570848 20 -122.2219809332446 30 0.0 0 VERTEX 5 581 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 15.00097927142208 20 -122.2219809332446 30 0.0 0 VERTEX 5 582 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.62573309713569 20 -122.2219809332446 30 0.0 0 VERTEX 5 583 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.250486922849289 20 -122.2219809332446 30 0.0 0 VERTEX 5 584 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.875240748563535 20 -122.2219809332446 30 0.0 0 VERTEX 5 585 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -122.2219809332446 30 0.0 0 VERTEX 5 586 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -107.7260311281121 30 0.0 0 VERTEX 5 587 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -93.23008132297954 30 0.0 0 VERTEX 5 588 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -78.73413151784702 30 0.0 0 VERTEX 5 589 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -64.23818171271449 30 0.0 0 VERTEX 5 58A 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -49.74223190758197 30 0.0 0 VERTEX 5 58B 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -35.24628210244945 30 0.0 0 VERTEX 5 58C 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -20.75033229731692 30 0.0 0 VERTEX 5 58D 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 1.499994574277137 20 -6.254382492184401 30 0.0 0 VERTEX 5 58E 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 2.802800495717929 20 -6.254382492184401 30 0.0 0 VERTEX 5 58F 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 4.105606417158721 20 -6.254382492184401 30 0.0 0 VERTEX 5 590 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 5.408412338599512 20 -6.254382492184401 30 0.0 0 VERTEX 5 591 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.711218260040304 20 -6.254382492184401 30 0.0 0 VERTEX 5 592 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.014024181480455 20 -6.254382492184401 30 0.0 0 VERTEX 5 593 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 9.316830102921246 20 -6.254382492184401 30 0.0 0 VERTEX 5 594 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.61963602436204 20 -6.254382492184401 30 0.0 0 VERTEX 5 595 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.92244194580283 20 -6.254382492184401 30 0.0 0 VERTEX 5 596 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 12.5117470604016 20 -5.665077377585634 30 0.0 0 VERTEX 5 597 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 13.10105217500036 20 -5.075772262986866 30 0.0 0 VERTEX 5 598 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 13.69035728959913 20 -4.486467148388098 30 0.0 0 VERTEX 5 599 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 14.2796624041979 20 -3.897162033789331 30 0.0 0 VERTEX 5 59A 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 14.86896751879667 20 -3.307856919190564 30 0.0 0 VERTEX 5 59B 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 15.45827263339543 20 -2.718551804591796 30 0.0 0 VERTEX 5 59C 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.0475777479942 20 -2.129246689993029 30 0.0 0 VERTEX 5 59D 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 16.63688286259297 20 -1.539941575394261 30 0.0 0 VERTEX 5 59E 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.12001800083981 20 -1.539941575394261 30 0.0 0 VERTEX 5 59F 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.60315313908664 20 -1.539941575394261 30 0.0 0 VERTEX 5 5A0 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.08628827733348 20 -1.539941575394261 30 0.0 0 VERTEX 5 5A1 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.56942341558032 20 -1.539941575394261 30 0.0 0 VERTEX 5 5A2 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.05255855382716 20 -1.539941575394261 30 0.0 0 VERTEX 5 5A3 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.53569369207399 20 -1.539941575394261 30 0.0 0 VERTEX 5 5A4 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.01882883032084 20 -1.539941575394261 30 0.0 0 VERTEX 5 5A5 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -1.539941575394261 30 0.0 0 VERTEX 5 5A6 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -16.62519649512555 30 0.0 0 VERTEX 5 5A7 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -31.71045141485684 30 0.0 0 VERTEX 5 5A8 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -46.79570633458813 30 0.0 0 VERTEX 5 5A9 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -61.88096125431942 30 0.0 0 VERTEX 5 5AA 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -76.96621617405071 30 0.0 0 VERTEX 5 5AB 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -92.05147109378201 30 0.0 0 VERTEX 5 5AC 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -107.1367260135133 30 0.0 0 VERTEX 5 5AD 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -122.2219809332446 30 0.0 0 VERTEX 5 5AE 330 57C 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 28.50196396856767 20 -122.2219809332446 30 0.0 0 SEQEND 5 5AF 330 57C 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 5B0 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 48 72 1 10 16.49081081401837 20 -1.187163797704678 11 15.90150569941961 21 -1.776468912303445 72 1 10 15.90150569941961 20 -1.776468912303445 11 15.31220058482084 21 -2.365774026902213 72 1 10 15.31220058482084 20 -2.365774026902213 11 14.72289547022207 21 -2.95507914150098 72 1 10 14.72289547022207 20 -2.95507914150098 11 14.1335903556233 21 -3.544384256099748 72 1 10 14.1335903556233 20 -3.544384256099748 11 13.54428524102454 21 -4.133689370698515 72 1 10 13.54428524102454 20 -4.133689370698515 11 12.95498012642577 21 -4.722994485297283 72 1 10 12.95498012642577 20 -4.722994485297283 11 12.365675011827 21 -5.31229959989605 72 1 10 12.365675011827 20 -5.31229959989605 11 11.77636989722824 21 -5.901604714494818 72 1 10 11.77636989722824 20 -5.901604714494818 11 10.44772575964807 21 -5.901604714494818 72 1 10 10.44772575964807 20 -5.901604714494818 11 9.119081622067904 21 -5.901604714494818 72 1 10 9.119081622067904 20 -5.901604714494818 11 7.790437484488381 21 -5.901604714494818 72 1 10 7.790437484488381 20 -5.901604714494818 11 6.461793346908216 21 -5.901604714494818 72 1 10 6.461793346908216 20 -5.901604714494818 11 5.13314920932805 21 -5.901604714494818 72 1 10 5.13314920932805 20 -5.901604714494818 11 3.804505071747885 21 -5.901604714494818 72 1 10 3.804505071747885 20 -5.901604714494818 11 2.47586093416772 21 -5.901604714494818 72 1 10 2.47586093416772 20 -5.901604714494818 11 1.147216796587554 21 -5.901604714494818 72 1 10 1.147216796587554 20 -5.901604714494818 11 1.147216796587554 21 -20.48574896404974 72 1 10 1.147216796587554 20 -20.48574896404974 11 1.147216796587554 21 -35.06989321360466 72 1 10 1.147216796587554 20 -35.06989321360466 11 1.147216796587554 21 -49.65403746315958 72 1 10 1.147216796587554 20 -49.65403746315958 11 1.147216796587554 21 -64.23818171271449 72 1 10 1.147216796587554 20 -64.23818171271449 11 1.147216796587554 21 -78.82232596226942 72 1 10 1.147216796587554 20 -78.82232596226942 11 1.147216796587554 21 -93.40647021182433 72 1 10 1.147216796587554 20 -93.40647021182433 11 1.147216796587554 21 -107.9906144613793 72 1 10 1.147216796587554 20 -107.9906144613793 11 1.147216796587554 21 -122.5747587109342 72 1 10 1.147216796587554 20 -122.5747587109342 11 4.610657415296347 21 -122.5747587109342 72 1 10 4.610657415296347 20 -122.5747587109342 11 8.074098034004498 21 -122.5747587109342 72 1 10 8.074098034004498 20 -122.5747587109342 11 11.53753865271329 21 -122.5747587109342 72 1 10 11.53753865271329 20 -122.5747587109342 11 15.00097927142208 21 -122.5747587109342 72 1 10 15.00097927142208 20 -122.5747587109342 11 18.46441989013088 21 -122.5747587109342 72 1 10 18.46441989013088 20 -122.5747587109342 11 21.92786050883967 21 -122.5747587109342 72 1 10 21.92786050883967 20 -122.5747587109342 11 25.39130112754846 21 -122.5747587109342 72 1 10 25.39130112754846 20 -122.5747587109342 11 28.85474174625725 21 -122.5747587109342 72 1 10 28.85474174625725 20 -122.5747587109342 11 28.85474174625725 21 -107.4013093467805 72 1 10 28.85474174625725 20 -107.4013093467805 11 28.85474174625725 21 -92.2278599826268 72 1 10 28.85474174625725 20 -92.2278599826268 11 28.85474174625725 21 -77.05441061847311 72 1 10 28.85474174625725 20 -77.05441061847311 11 28.85474174625725 21 -61.88096125431942 72 1 10 28.85474174625725 20 -61.88096125431942 11 28.85474174625725 21 -46.70751189016574 72 1 10 28.85474174625725 20 -46.70751189016574 11 28.85474174625725 21 -31.53406252601205 72 1 10 28.85474174625725 20 -31.53406252601205 11 28.85474174625725 21 -16.36061316185836 72 1 10 28.85474174625725 20 -16.36061316185836 11 28.85474174625725 21 -1.187163797704677 72 1 10 28.85474174625725 20 -1.187163797704678 11 27.30925037972739 21 -1.187163797704678 72 1 10 27.30925037972739 20 -1.187163797704678 11 25.76375901319754 21 -1.187163797704678 72 1 10 25.76375901319754 20 -1.187163797704678 11 24.21826764666768 21 -1.187163797704678 72 1 10 24.21826764666768 20 -1.187163797704678 11 22.67277628013781 21 -1.187163797704678 72 1 10 22.67277628013781 20 -1.187163797704678 11 21.12728491360796 21 -1.187163797704678 72 1 10 21.12728491360796 20 -1.187163797704678 11 19.5817935470781 21 -1.187163797704678 72 1 10 19.5817935470781 20 -1.187163797704678 11 18.03630218054824 21 -1.187163797704678 72 1 10 18.03630218054824 20 -1.187163797704678 11 16.49081081401837 21 -1.187163797704678 97 0 92 1 93 48 72 1 10 28.50196396856767 20 -122.2219809332446 11 25.12671779428127 21 -122.2219809332446 72 1 10 25.12671779428127 20 -122.2219809332446 11 21.75147161999488 21 -122.2219809332446 72 1 10 21.75147161999488 20 -122.2219809332446 11 18.37622544570848 21 -122.2219809332446 72 1 10 18.37622544570848 20 -122.2219809332446 11 15.00097927142208 21 -122.2219809332446 72 1 10 15.00097927142208 20 -122.2219809332446 11 11.62573309713569 21 -122.2219809332446 72 1 10 11.62573309713569 20 -122.2219809332446 11 8.250486922849289 21 -122.2219809332446 72 1 10 8.250486922849289 20 -122.2219809332446 11 4.875240748563535 21 -122.2219809332446 72 1 10 4.875240748563535 20 -122.2219809332446 11 1.499994574277137 21 -122.2219809332446 72 1 10 1.499994574277137 20 -122.2219809332446 11 1.499994574277137 21 -107.7260311281121 72 1 10 1.499994574277137 20 -107.7260311281121 11 1.499994574277137 21 -93.23008132297954 72 1 10 1.499994574277137 20 -93.23008132297954 11 1.499994574277137 21 -78.73413151784702 72 1 10 1.499994574277137 20 -78.73413151784702 11 1.499994574277137 21 -64.23818171271449 72 1 10 1.499994574277137 20 -64.23818171271449 11 1.499994574277137 21 -49.74223190758197 72 1 10 1.499994574277137 20 -49.74223190758197 11 1.499994574277137 21 -35.24628210244945 72 1 10 1.499994574277137 20 -35.24628210244945 11 1.499994574277137 21 -20.75033229731692 72 1 10 1.499994574277137 20 -20.75033229731692 11 1.499994574277137 21 -6.254382492184401 72 1 10 1.499994574277137 20 -6.254382492184401 11 2.802800495717929 21 -6.254382492184401 72 1 10 2.802800495717929 20 -6.254382492184401 11 4.105606417158721 21 -6.254382492184401 72 1 10 4.105606417158721 20 -6.254382492184401 11 5.408412338599512 21 -6.254382492184401 72 1 10 5.408412338599512 20 -6.254382492184401 11 6.711218260040304 21 -6.254382492184401 72 1 10 6.711218260040304 20 -6.254382492184401 11 8.014024181480455 21 -6.254382492184401 72 1 10 8.014024181480455 20 -6.254382492184401 11 9.316830102921246 21 -6.254382492184401 72 1 10 9.316830102921246 20 -6.254382492184401 11 10.61963602436204 21 -6.254382492184401 72 1 10 10.61963602436204 20 -6.254382492184401 11 11.92244194580283 21 -6.254382492184401 72 1 10 11.92244194580283 20 -6.254382492184401 11 12.5117470604016 21 -5.665077377585634 72 1 10 12.5117470604016 20 -5.665077377585634 11 13.10105217500036 21 -5.075772262986866 72 1 10 13.10105217500036 20 -5.075772262986866 11 13.69035728959913 21 -4.486467148388098 72 1 10 13.69035728959913 20 -4.486467148388098 11 14.2796624041979 21 -3.897162033789331 72 1 10 14.2796624041979 20 -3.897162033789331 11 14.86896751879667 21 -3.307856919190564 72 1 10 14.86896751879667 20 -3.307856919190564 11 15.45827263339543 21 -2.718551804591796 72 1 10 15.45827263339543 20 -2.718551804591796 11 16.0475777479942 21 -2.129246689993029 72 1 10 16.0475777479942 20 -2.129246689993029 11 16.63688286259297 21 -1.539941575394261 72 1 10 16.63688286259297 20 -1.539941575394261 11 18.12001800083981 21 -1.539941575394261 72 1 10 18.12001800083981 20 -1.539941575394261 11 19.60315313908664 21 -1.539941575394261 72 1 10 19.60315313908664 20 -1.539941575394261 11 21.08628827733348 21 -1.539941575394261 72 1 10 21.08628827733348 20 -1.539941575394261 11 22.56942341558032 21 -1.539941575394261 72 1 10 22.56942341558032 20 -1.539941575394261 11 24.05255855382716 21 -1.539941575394261 72 1 10 24.05255855382716 20 -1.539941575394261 11 25.53569369207399 21 -1.539941575394261 72 1 10 25.53569369207399 20 -1.539941575394261 11 27.01882883032084 21 -1.539941575394261 72 1 10 27.01882883032084 20 -1.539941575394261 11 28.50196396856767 21 -1.539941575394261 72 1 10 28.50196396856767 20 -1.539941575394261 11 28.50196396856767 21 -16.62519649512555 72 1 10 28.50196396856767 20 -16.62519649512555 11 28.50196396856767 21 -31.71045141485684 72 1 10 28.50196396856767 20 -31.71045141485684 11 28.50196396856767 21 -46.79570633458813 72 1 10 28.50196396856767 20 -46.79570633458813 11 28.50196396856767 21 -61.88096125431942 72 1 10 28.50196396856767 20 -61.88096125431942 11 28.50196396856767 21 -76.96621617405071 72 1 10 28.50196396856767 20 -76.96621617405071 11 28.50196396856767 21 -92.05147109378201 72 1 10 28.50196396856767 20 -92.05147109378201 11 28.50196396856767 21 -107.1367260135133 72 1 10 28.50196396856767 20 -107.1367260135133 11 28.50196396856767 21 -122.2219809332446 97 0 75 2 76 1 98 0 0 INSERT 5 5B2 330 1F 100 AcDbEntity 8 Graphics 100 AcDbBlockReference 2 block 3 10 0.0 20 0.0 30 0.0 0 POLYLINE 5 856 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 857 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -73.01027762387868 30 0.0 0 VERTEX 5 858 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -72.7246361444579 30 0.0 0 VERTEX 5 859 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -72.43899466503713 30 0.0 0 VERTEX 5 85A 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -72.15335318561634 30 0.0 0 VERTEX 5 85B 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -71.86771170619556 30 0.0 0 VERTEX 5 85C 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -71.58207022677479 30 0.0 0 VERTEX 5 85D 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -71.29642874735401 30 0.0 0 VERTEX 5 85E 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -71.01078726793324 30 0.0 0 VERTEX 5 85F 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -70.72514578851246 30 0.0 0 VERTEX 5 860 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.533523048809347 20 -70.72514578851246 30 0.0 0 VERTEX 5 861 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.474224342769483 20 -70.72514578851246 30 0.0 0 VERTEX 5 862 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.41492563672962 20 -70.72514578851246 30 0.0 0 VERTEX 5 863 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.355626930689759 20 -70.72514578851246 30 0.0 0 VERTEX 5 864 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.296328224649896 20 -70.72514578851246 30 0.0 0 VERTEX 5 865 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.237029518610033 20 -70.72514578851246 30 0.0 0 VERTEX 5 866 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.17773081257017 20 -70.72514578851246 30 0.0 0 VERTEX 5 867 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -70.72514578851246 30 0.0 0 VERTEX 5 868 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -70.83405386953991 30 0.0 0 VERTEX 5 869 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -70.94296195056738 30 0.0 0 VERTEX 5 86A 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -71.05187003159485 30 0.0 0 VERTEX 5 86B 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -71.1607781126223 30 0.0 0 VERTEX 5 86C 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -71.26968619364976 30 0.0 0 VERTEX 5 86D 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -71.37859427467723 30 0.0 0 VERTEX 5 86E 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -71.48750235570468 30 0.0 0 VERTEX 5 86F 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -71.59641043673214 30 0.0 0 VERTEX 5 870 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.007392372671347 20 -71.59641043673214 30 0.0 0 VERTEX 5 871 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.896352638813031 20 -71.59641043673214 30 0.0 0 VERTEX 5 872 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.785312904954072 20 -71.59641043673214 30 0.0 0 VERTEX 5 873 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.674273171095114 20 -71.59641043673214 30 0.0 0 VERTEX 5 874 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.563233437236154 20 -71.59641043673214 30 0.0 0 VERTEX 5 875 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.452193703377196 20 -71.59641043673214 30 0.0 0 VERTEX 5 876 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.341153969518237 20 -71.59641043673214 30 0.0 0 VERTEX 5 877 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -71.59641043673214 30 0.0 0 VERTEX 5 878 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -71.48750235570468 30 0.0 0 VERTEX 5 879 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -71.37859427467723 30 0.0 0 VERTEX 5 87A 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -71.26968619364976 30 0.0 0 VERTEX 5 87B 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -71.1607781126223 30 0.0 0 VERTEX 5 87C 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -71.05187003159485 30 0.0 0 VERTEX 5 87D 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -70.94296195056738 30 0.0 0 VERTEX 5 87E 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -70.83405386953991 30 0.0 0 VERTEX 5 87F 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -70.72514578851246 30 0.0 0 VERTEX 5 880 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.170815529619415 20 -70.72514578851246 30 0.0 0 VERTEX 5 881 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.111516823579552 20 -70.72514578851246 30 0.0 0 VERTEX 5 882 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.05221811753969 20 -70.72514578851246 30 0.0 0 VERTEX 5 883 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.992919411499827 20 -70.72514578851246 30 0.0 0 VERTEX 5 884 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.933620705459964 20 -70.72514578851246 30 0.0 0 VERTEX 5 885 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.874321999420101 20 -70.72514578851246 30 0.0 0 VERTEX 5 886 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.815023293380238 20 -70.72514578851246 30 0.0 0 VERTEX 5 887 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -70.72514578851246 30 0.0 0 VERTEX 5 888 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -71.01078726793324 30 0.0 0 VERTEX 5 889 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -71.29642874735401 30 0.0 0 VERTEX 5 88A 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -71.58207022677479 30 0.0 0 VERTEX 5 88B 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -71.86771170619556 30 0.0 0 VERTEX 5 88C 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -72.15335318561634 30 0.0 0 VERTEX 5 88D 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -72.43899466503713 30 0.0 0 VERTEX 5 88E 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -72.7246361444579 30 0.0 0 VERTEX 5 88F 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.755724587340375 20 -73.01027762387868 30 0.0 0 VERTEX 5 890 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.815023293380238 20 -73.01027762387868 30 0.0 0 VERTEX 5 891 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.874321999420101 20 -73.01027762387868 30 0.0 0 VERTEX 5 892 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.933620705459964 20 -73.01027762387868 30 0.0 0 VERTEX 5 893 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.992919411499827 20 -73.01027762387868 30 0.0 0 VERTEX 5 894 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.05221811753969 20 -73.01027762387868 30 0.0 0 VERTEX 5 895 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.111516823579552 20 -73.01027762387868 30 0.0 0 VERTEX 5 896 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.170815529619415 20 -73.01027762387868 30 0.0 0 VERTEX 5 897 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -73.01027762387868 30 0.0 0 VERTEX 5 898 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -72.88276602723087 30 0.0 0 VERTEX 5 899 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -72.75525443058305 30 0.0 0 VERTEX 5 89A 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -72.62774283393524 30 0.0 0 VERTEX 5 89B 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -72.50023123728744 30 0.0 0 VERTEX 5 89C 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -72.37271964063963 30 0.0 0 VERTEX 5 89D 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -72.24520804399182 30 0.0 0 VERTEX 5 89E 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -72.11769644734402 30 0.0 0 VERTEX 5 89F 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.230114235659278 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A0 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.341153969518237 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A1 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.452193703377196 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A2 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.563233437236154 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A3 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.674273171095114 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A4 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.785312904954072 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A5 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.896352638813031 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A6 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.007392372671347 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A7 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -71.9901848506962 30 0.0 0 VERTEX 5 8A8 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -72.11769644734402 30 0.0 0 VERTEX 5 8A9 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -72.24520804399182 30 0.0 0 VERTEX 5 8AA 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -72.37271964063963 30 0.0 0 VERTEX 5 8AB 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -72.50023123728744 30 0.0 0 VERTEX 5 8AC 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -72.62774283393524 30 0.0 0 VERTEX 5 8AD 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -72.75525443058305 30 0.0 0 VERTEX 5 8AE 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -72.88276602723087 30 0.0 0 VERTEX 5 8AF 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.118432106530307 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B0 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.17773081257017 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B1 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.237029518610033 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B2 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.296328224649896 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B3 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.355626930689759 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B4 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.41492563672962 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B5 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.474224342769483 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B6 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.533523048809347 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B7 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -73.01027762387868 30 0.0 0 VERTEX 5 8B8 330 856 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 8.59282175484921 20 -73.01027762387868 30 0.0 0 SEQEND 5 8BA 330 856 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 8B9 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 96 72 1 10 8.59282175484921 20 -73.01027762387868 11 8.59282175484921 21 -72.7246361444579 72 1 10 8.59282175484921 20 -72.7246361444579 11 8.59282175484921 21 -72.43899466503713 72 1 10 8.59282175484921 20 -72.43899466503713 11 8.59282175484921 21 -72.15335318561634 72 1 10 8.59282175484921 20 -72.15335318561634 11 8.59282175484921 21 -71.86771170619556 72 1 10 8.59282175484921 20 -71.86771170619556 11 8.59282175484921 21 -71.58207022677479 72 1 10 8.59282175484921 20 -71.58207022677479 11 8.59282175484921 21 -71.29642874735401 72 1 10 8.59282175484921 20 -71.29642874735401 11 8.59282175484921 21 -71.01078726793324 72 1 10 8.59282175484921 20 -71.01078726793324 11 8.59282175484921 21 -70.72514578851246 72 1 10 8.59282175484921 20 -70.72514578851246 11 8.533523048809347 21 -70.72514578851246 72 1 10 8.533523048809347 20 -70.72514578851246 11 8.474224342769483 21 -70.72514578851246 72 1 10 8.474224342769483 20 -70.72514578851246 11 8.41492563672962 21 -70.72514578851246 72 1 10 8.41492563672962 20 -70.72514578851246 11 8.355626930689759 21 -70.72514578851246 72 1 10 8.355626930689759 20 -70.72514578851246 11 8.296328224649896 21 -70.72514578851246 72 1 10 8.296328224649896 20 -70.72514578851246 11 8.237029518610033 21 -70.72514578851246 72 1 10 8.237029518610033 20 -70.72514578851246 11 8.17773081257017 21 -70.72514578851246 72 1 10 8.17773081257017 20 -70.72514578851246 11 8.118432106530307 21 -70.72514578851246 72 1 10 8.118432106530307 20 -70.72514578851246 11 8.118432106530307 21 -70.83405386953991 72 1 10 8.118432106530307 20 -70.83405386953991 11 8.118432106530307 21 -70.94296195056738 72 1 10 8.118432106530307 20 -70.94296195056738 11 8.118432106530307 21 -71.05187003159485 72 1 10 8.118432106530307 20 -71.05187003159485 11 8.118432106530307 21 -71.1607781126223 72 1 10 8.118432106530307 20 -71.1607781126223 11 8.118432106530307 21 -71.26968619364976 72 1 10 8.118432106530307 20 -71.26968619364976 11 8.118432106530307 21 -71.37859427467723 72 1 10 8.118432106530307 20 -71.37859427467723 11 8.118432106530307 21 -71.48750235570468 72 1 10 8.118432106530307 20 -71.48750235570468 11 8.118432106530307 21 -71.59641043673214 72 1 10 8.118432106530307 20 -71.59641043673214 11 8.007392372671347 21 -71.59641043673214 72 1 10 8.007392372671347 20 -71.59641043673214 11 7.896352638813031 21 -71.59641043673214 72 1 10 7.896352638813031 20 -71.59641043673214 11 7.785312904954072 21 -71.59641043673214 72 1 10 7.785312904954072 20 -71.59641043673214 11 7.674273171095114 21 -71.59641043673214 72 1 10 7.674273171095114 20 -71.59641043673214 11 7.563233437236154 21 -71.59641043673214 72 1 10 7.563233437236154 20 -71.59641043673214 11 7.452193703377196 21 -71.59641043673214 72 1 10 7.452193703377196 20 -71.59641043673214 11 7.341153969518237 21 -71.59641043673214 72 1 10 7.341153969518237 20 -71.59641043673214 11 7.230114235659278 21 -71.59641043673214 72 1 10 7.230114235659278 20 -71.59641043673214 11 7.230114235659278 21 -71.48750235570468 72 1 10 7.230114235659278 20 -71.48750235570468 11 7.230114235659278 21 -71.37859427467723 72 1 10 7.230114235659278 20 -71.37859427467723 11 7.230114235659278 21 -71.26968619364976 72 1 10 7.230114235659278 20 -71.26968619364976 11 7.230114235659278 21 -71.1607781126223 72 1 10 7.230114235659278 20 -71.1607781126223 11 7.230114235659278 21 -71.05187003159485 72 1 10 7.230114235659278 20 -71.05187003159485 11 7.230114235659278 21 -70.94296195056738 72 1 10 7.230114235659278 20 -70.94296195056738 11 7.230114235659278 21 -70.83405386953991 72 1 10 7.230114235659278 20 -70.83405386953991 11 7.230114235659278 21 -70.72514578851246 72 1 10 7.230114235659278 20 -70.72514578851246 11 7.170815529619415 21 -70.72514578851246 72 1 10 7.170815529619415 20 -70.72514578851246 11 7.111516823579552 21 -70.72514578851246 72 1 10 7.111516823579552 20 -70.72514578851246 11 7.05221811753969 21 -70.72514578851246 72 1 10 7.05221811753969 20 -70.72514578851246 11 6.992919411499827 21 -70.72514578851246 72 1 10 6.992919411499827 20 -70.72514578851246 11 6.933620705459964 21 -70.72514578851246 72 1 10 6.933620705459964 20 -70.72514578851246 11 6.874321999420101 21 -70.72514578851246 72 1 10 6.874321999420101 20 -70.72514578851246 11 6.815023293380238 21 -70.72514578851246 72 1 10 6.815023293380238 20 -70.72514578851246 11 6.755724587340375 21 -70.72514578851246 72 1 10 6.755724587340375 20 -70.72514578851246 11 6.755724587340375 21 -71.01078726793324 72 1 10 6.755724587340375 20 -71.01078726793324 11 6.755724587340375 21 -71.29642874735401 72 1 10 6.755724587340375 20 -71.29642874735401 11 6.755724587340375 21 -71.58207022677479 72 1 10 6.755724587340375 20 -71.58207022677479 11 6.755724587340375 21 -71.86771170619556 72 1 10 6.755724587340375 20 -71.86771170619556 11 6.755724587340375 21 -72.15335318561634 72 1 10 6.755724587340375 20 -72.15335318561634 11 6.755724587340375 21 -72.43899466503713 72 1 10 6.755724587340375 20 -72.43899466503713 11 6.755724587340375 21 -72.7246361444579 72 1 10 6.755724587340375 20 -72.7246361444579 11 6.755724587340375 21 -73.01027762387868 72 1 10 6.755724587340375 20 -73.01027762387868 11 6.815023293380238 21 -73.01027762387868 72 1 10 6.815023293380238 20 -73.01027762387868 11 6.874321999420101 21 -73.01027762387868 72 1 10 6.874321999420101 20 -73.01027762387868 11 6.933620705459964 21 -73.01027762387868 72 1 10 6.933620705459964 20 -73.01027762387868 11 6.992919411499827 21 -73.01027762387868 72 1 10 6.992919411499827 20 -73.01027762387868 11 7.05221811753969 21 -73.01027762387868 72 1 10 7.05221811753969 20 -73.01027762387868 11 7.111516823579552 21 -73.01027762387868 72 1 10 7.111516823579552 20 -73.01027762387868 11 7.170815529619415 21 -73.01027762387868 72 1 10 7.170815529619415 20 -73.01027762387868 11 7.230114235659278 21 -73.01027762387868 72 1 10 7.230114235659278 20 -73.01027762387868 11 7.230114235659278 21 -72.88276602723087 72 1 10 7.230114235659278 20 -72.88276602723087 11 7.230114235659278 21 -72.75525443058305 72 1 10 7.230114235659278 20 -72.75525443058305 11 7.230114235659278 21 -72.62774283393524 72 1 10 7.230114235659278 20 -72.62774283393524 11 7.230114235659278 21 -72.50023123728744 72 1 10 7.230114235659278 20 -72.50023123728744 11 7.230114235659278 21 -72.37271964063963 72 1 10 7.230114235659278 20 -72.37271964063963 11 7.230114235659278 21 -72.24520804399182 72 1 10 7.230114235659278 20 -72.24520804399182 11 7.230114235659278 21 -72.11769644734402 72 1 10 7.230114235659278 20 -72.11769644734402 11 7.230114235659278 21 -71.9901848506962 72 1 10 7.230114235659278 20 -71.9901848506962 11 7.341153969518237 21 -71.9901848506962 72 1 10 7.341153969518237 20 -71.9901848506962 11 7.452193703377196 21 -71.9901848506962 72 1 10 7.452193703377196 20 -71.9901848506962 11 7.563233437236154 21 -71.9901848506962 72 1 10 7.563233437236154 20 -71.9901848506962 11 7.674273171095114 21 -71.9901848506962 72 1 10 7.674273171095114 20 -71.9901848506962 11 7.785312904954072 21 -71.9901848506962 72 1 10 7.785312904954072 20 -71.9901848506962 11 7.896352638813031 21 -71.9901848506962 72 1 10 7.896352638813031 20 -71.9901848506962 11 8.007392372671347 21 -71.9901848506962 72 1 10 8.007392372671347 20 -71.9901848506962 11 8.118432106530307 21 -71.9901848506962 72 1 10 8.118432106530307 20 -71.9901848506962 11 8.118432106530307 21 -72.11769644734402 72 1 10 8.118432106530307 20 -72.11769644734402 11 8.118432106530307 21 -72.24520804399182 72 1 10 8.118432106530307 20 -72.24520804399182 11 8.118432106530307 21 -72.37271964063963 72 1 10 8.118432106530307 20 -72.37271964063963 11 8.118432106530307 21 -72.50023123728744 72 1 10 8.118432106530307 20 -72.50023123728744 11 8.118432106530307 21 -72.62774283393524 72 1 10 8.118432106530307 20 -72.62774283393524 11 8.118432106530307 21 -72.75525443058305 72 1 10 8.118432106530307 20 -72.75525443058305 11 8.118432106530307 21 -72.88276602723087 72 1 10 8.118432106530307 20 -72.88276602723087 11 8.118432106530307 21 -73.01027762387868 72 1 10 8.118432106530307 20 -73.01027762387868 11 8.17773081257017 21 -73.01027762387868 72 1 10 8.17773081257017 20 -73.01027762387868 11 8.237029518610033 21 -73.01027762387868 72 1 10 8.237029518610033 20 -73.01027762387868 11 8.296328224649896 21 -73.01027762387868 72 1 10 8.296328224649896 20 -73.01027762387868 11 8.355626930689759 21 -73.01027762387868 72 1 10 8.355626930689759 20 -73.01027762387868 11 8.41492563672962 21 -73.01027762387868 72 1 10 8.41492563672962 20 -73.01027762387868 11 8.474224342769483 21 -73.01027762387868 72 1 10 8.474224342769483 20 -73.01027762387868 11 8.533523048809347 21 -73.01027762387868 72 1 10 8.533523048809347 20 -73.01027762387868 11 8.59282175484921 21 -73.01027762387868 97 0 75 2 76 1 98 0 0 POLYLINE 5 8BB 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 8BC 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.379739038953035 20 -52.19318049502262 30 0.0 0 VERTEX 5 8BD 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.344167755197619 20 -52.1967608374208 30 0.0 0 VERTEX 5 8BE 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.31104706475417 20 -52.20703085546566 30 0.0 0 VERTEX 5 8BF 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.281083481345252 20 -52.22328403543563 30 0.0 0 VERTEX 5 8C0 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.254983518693425 20 -52.2448138636078 30 0.0 0 VERTEX 5 8C1 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.23345369052125 20 -52.27091382625963 30 0.0 0 VERTEX 5 8C2 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.217200510551287 20 -52.30087740966854 30 0.0 0 VERTEX 5 8C3 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.206930492506098 20 -52.333998100112 30 0.0 0 VERTEX 5 8C4 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -52.36956938386741 30 0.0 0 VERTEX 5 8C5 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -53.30286997414922 30 0.0 0 VERTEX 5 8C6 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -54.23617056443103 30 0.0 0 VERTEX 5 8C7 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -55.16947115471284 30 0.0 0 VERTEX 5 8C8 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -56.10277174499466 30 0.0 0 VERTEX 5 8C9 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -57.03607233527647 30 0.0 0 VERTEX 5 8CA 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -57.96937292555828 30 0.0 0 VERTEX 5 8CB 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -58.90267351584009 30 0.0 0 VERTEX 5 8CC 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.203350150108244 20 -59.8359741061219 30 0.0 0 VERTEX 5 8CD 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.154892098107703 20 -59.8639271533378 30 0.0 0 VERTEX 5 8CE 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.110798534628282 20 -59.89784317637147 30 0.0 0 VERTEX 5 8CF 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.071715667399796 20 -59.93719733645854 30 0.0 0 VERTEX 5 8D0 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.038289704152058 20 -59.98146479483336 30 0.0 0 VERTEX 5 8D1 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.011166852614883 20 -60.03012071273061 30 0.0 0 VERTEX 5 8D2 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.990993320518083 20 -60.08264025138494 30 0.0 0 VERTEX 5 8D3 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.978415315591473 20 -60.13849857203104 30 0.0 0 VERTEX 5 8D4 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.974079045564866 20 -60.19717083590357 30 0.0 0 VERTEX 5 8D5 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 6.982332135149697 20 -60.27884483153694 30 0.0 0 VERTEX 5 8D6 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.005997316939537 20 -60.35495351764716 30 0.0 0 VERTEX 5 8D7 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.043433460487408 20 -60.42385576378727 30 0.0 0 VERTEX 5 8D8 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.092999435346335 20 -60.48391043951027 30 0.0 0 VERTEX 5 8D9 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.153054111069338 20 -60.5334764143692 30 0.0 0 VERTEX 5 8DA 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.22195635720944 20 -60.57091255791707 30 0.0 0 VERTEX 5 8DB 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.298065043319665 20 -60.59457773970691 30 0.0 0 VERTEX 5 8DC 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.379739038953035 20 -60.60283082929173 30 0.0 0 VERTEX 5 8DD 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.461413034586405 20 -60.59457773970691 30 0.0 0 VERTEX 5 8DE 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.537521720696629 20 -60.57091255791707 30 0.0 0 VERTEX 5 8DF 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.606423966836733 20 -60.5334764143692 30 0.0 0 VERTEX 5 8E0 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.666478642559736 20 -60.48391043951027 30 0.0 0 VERTEX 5 8E1 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.716044617418661 20 -60.42385576378727 30 0.0 0 VERTEX 5 8E2 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.753480760966533 20 -60.35495351764716 30 0.0 0 VERTEX 5 8E3 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.777145942756372 20 -60.27884483153694 30 0.0 0 VERTEX 5 8E4 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.785399032341203 20 -60.19717083590357 30 0.0 0 VERTEX 5 8E5 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.781062762314597 20 -60.13849857203104 30 0.0 0 VERTEX 5 8E6 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.768484757387987 20 -60.08264025138494 30 0.0 0 VERTEX 5 8E7 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.748311225291188 20 -60.03012071273061 30 0.0 0 VERTEX 5 8E8 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.721188373754011 20 -59.98146479483336 30 0.0 0 VERTEX 5 8E9 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.687762410506274 20 -59.93719733645854 30 0.0 0 VERTEX 5 8EA 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.648679543277788 20 -59.89784317637147 30 0.0 0 VERTEX 5 8EB 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.604585979798368 20 -59.8639271533378 30 0.0 0 VERTEX 5 8EC 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -59.8359741061219 30 0.0 0 VERTEX 5 8ED 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -58.90267351584009 30 0.0 0 VERTEX 5 8EE 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -57.96937292555828 30 0.0 0 VERTEX 5 8EF 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -57.03607233527647 30 0.0 0 VERTEX 5 8F0 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -56.10277174499466 30 0.0 0 VERTEX 5 8F1 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -55.16947115471284 30 0.0 0 VERTEX 5 8F2 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -54.23617056443103 30 0.0 0 VERTEX 5 8F3 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -53.30286997414922 30 0.0 0 VERTEX 5 8F4 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.556127927797827 20 -52.36956938386741 30 0.0 0 VERTEX 5 8F5 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.552547585399973 20 -52.333998100112 30 0.0 0 VERTEX 5 8F6 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.542277567354783 20 -52.30087740966854 30 0.0 0 VERTEX 5 8F7 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.526024387384821 20 -52.27091382625963 30 0.0 0 VERTEX 5 8F8 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.504494559212644 20 -52.2448138636078 30 0.0 0 VERTEX 5 8F9 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.478394596560817 20 -52.22328403543563 30 0.0 0 VERTEX 5 8FA 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.448431013151899 20 -52.20703085546566 30 0.0 0 VERTEX 5 8FB 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.415310322708452 20 -52.1967608374208 30 0.0 0 VERTEX 5 8FC 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.379739038953035 20 -52.19318049502262 30 0.0 0 VERTEX 5 8FD 330 8BB 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 7.379739038953035 20 -52.19318049502262 30 0.0 0 SEQEND 5 8FF 330 8BB 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 8FE 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 7.379739038953035 20 -52.19318049502262 11 7.344167755197619 21 -52.1967608374208 72 1 10 7.344167755197619 20 -52.1967608374208 11 7.31104706475417 21 -52.20703085546566 72 1 10 7.31104706475417 20 -52.20703085546566 11 7.281083481345252 21 -52.22328403543563 72 1 10 7.281083481345252 20 -52.22328403543563 11 7.254983518693425 21 -52.2448138636078 72 1 10 7.254983518693425 20 -52.2448138636078 11 7.23345369052125 21 -52.27091382625963 72 1 10 7.23345369052125 20 -52.27091382625963 11 7.217200510551287 21 -52.30087740966854 72 1 10 7.217200510551287 20 -52.30087740966854 11 7.206930492506098 21 -52.333998100112 72 1 10 7.206930492506098 20 -52.333998100112 11 7.203350150108244 21 -52.36956938386741 72 1 10 7.203350150108244 20 -52.36956938386741 11 7.203350150108244 21 -53.30286997414922 72 1 10 7.203350150108244 20 -53.30286997414922 11 7.203350150108244 21 -54.23617056443103 72 1 10 7.203350150108244 20 -54.23617056443103 11 7.203350150108244 21 -55.16947115471284 72 1 10 7.203350150108244 20 -55.16947115471284 11 7.203350150108244 21 -56.10277174499466 72 1 10 7.203350150108244 20 -56.10277174499466 11 7.203350150108244 21 -57.03607233527647 72 1 10 7.203350150108244 20 -57.03607233527647 11 7.203350150108244 21 -57.96937292555828 72 1 10 7.203350150108244 20 -57.96937292555828 11 7.203350150108244 21 -58.90267351584009 72 1 10 7.203350150108244 20 -58.90267351584009 11 7.203350150108244 21 -59.8359741061219 72 1 10 7.203350150108244 20 -59.8359741061219 11 7.154892098107703 21 -59.8639271533378 72 1 10 7.154892098107703 20 -59.8639271533378 11 7.110798534628282 21 -59.89784317637147 72 1 10 7.110798534628282 20 -59.89784317637147 11 7.071715667399796 21 -59.93719733645854 72 1 10 7.071715667399796 20 -59.93719733645854 11 7.038289704152058 21 -59.98146479483336 72 1 10 7.038289704152058 20 -59.98146479483336 11 7.011166852614883 21 -60.03012071273061 72 1 10 7.011166852614883 20 -60.03012071273061 11 6.990993320518083 21 -60.08264025138494 72 1 10 6.990993320518083 20 -60.08264025138494 11 6.978415315591473 21 -60.13849857203104 72 1 10 6.978415315591473 20 -60.13849857203104 11 6.974079045564866 21 -60.19717083590357 72 1 10 6.974079045564866 20 -60.19717083590357 11 6.982332135149697 21 -60.27884483153694 72 1 10 6.982332135149697 20 -60.27884483153694 11 7.005997316939537 21 -60.35495351764716 72 1 10 7.005997316939537 20 -60.35495351764716 11 7.043433460487408 21 -60.42385576378727 72 1 10 7.043433460487408 20 -60.42385576378727 11 7.092999435346335 21 -60.48391043951027 72 1 10 7.092999435346335 20 -60.48391043951027 11 7.153054111069338 21 -60.5334764143692 72 1 10 7.153054111069338 20 -60.5334764143692 11 7.22195635720944 21 -60.57091255791707 72 1 10 7.22195635720944 20 -60.57091255791707 11 7.298065043319665 21 -60.59457773970691 72 1 10 7.298065043319665 20 -60.59457773970691 11 7.379739038953035 21 -60.60283082929173 72 1 10 7.379739038953035 20 -60.60283082929173 11 7.461413034586405 21 -60.59457773970691 72 1 10 7.461413034586405 20 -60.59457773970691 11 7.537521720696629 21 -60.57091255791707 72 1 10 7.537521720696629 20 -60.57091255791707 11 7.606423966836733 21 -60.5334764143692 72 1 10 7.606423966836733 20 -60.5334764143692 11 7.666478642559736 21 -60.48391043951027 72 1 10 7.666478642559736 20 -60.48391043951027 11 7.716044617418661 21 -60.42385576378727 72 1 10 7.716044617418661 20 -60.42385576378727 11 7.753480760966533 21 -60.35495351764716 72 1 10 7.753480760966533 20 -60.35495351764716 11 7.777145942756372 21 -60.27884483153694 72 1 10 7.777145942756372 20 -60.27884483153694 11 7.785399032341203 21 -60.19717083590357 72 1 10 7.785399032341203 20 -60.19717083590357 11 7.781062762314597 21 -60.13849857203104 72 1 10 7.781062762314597 20 -60.13849857203104 11 7.768484757387987 21 -60.08264025138494 72 1 10 7.768484757387987 20 -60.08264025138494 11 7.748311225291188 21 -60.03012071273061 72 1 10 7.748311225291188 20 -60.03012071273061 11 7.721188373754011 21 -59.98146479483336 72 1 10 7.721188373754011 20 -59.98146479483336 11 7.687762410506274 21 -59.93719733645854 72 1 10 7.687762410506274 20 -59.93719733645854 11 7.648679543277788 21 -59.89784317637147 72 1 10 7.648679543277788 20 -59.89784317637147 11 7.604585979798368 21 -59.8639271533378 72 1 10 7.604585979798368 20 -59.8639271533378 11 7.556127927797827 21 -59.8359741061219 72 1 10 7.556127927797827 20 -59.8359741061219 11 7.556127927797827 21 -58.90267351584009 72 1 10 7.556127927797827 20 -58.90267351584009 11 7.556127927797827 21 -57.96937292555828 72 1 10 7.556127927797827 20 -57.96937292555828 11 7.556127927797827 21 -57.03607233527647 72 1 10 7.556127927797827 20 -57.03607233527647 11 7.556127927797827 21 -56.10277174499466 72 1 10 7.556127927797827 20 -56.10277174499466 11 7.556127927797827 21 -55.16947115471284 72 1 10 7.556127927797827 20 -55.16947115471284 11 7.556127927797827 21 -54.23617056443103 72 1 10 7.556127927797827 20 -54.23617056443103 11 7.556127927797827 21 -53.30286997414922 72 1 10 7.556127927797827 20 -53.30286997414922 11 7.556127927797827 21 -52.36956938386741 72 1 10 7.556127927797827 20 -52.36956938386741 11 7.552547585399973 21 -52.333998100112 72 1 10 7.552547585399973 20 -52.333998100112 11 7.542277567354783 21 -52.30087740966854 72 1 10 7.542277567354783 20 -52.30087740966854 11 7.526024387384821 21 -52.27091382625963 72 1 10 7.526024387384821 20 -52.27091382625963 11 7.504494559212644 21 -52.2448138636078 72 1 10 7.504494559212644 20 -52.2448138636078 11 7.478394596560817 21 -52.22328403543563 72 1 10 7.478394596560817 20 -52.22328403543563 11 7.448431013151899 21 -52.20703085546566 72 1 10 7.448431013151899 20 -52.20703085546566 11 7.415310322708452 21 -52.1967608374208 72 1 10 7.415310322708452 20 -52.1967608374208 11 7.379739038953035 21 -52.19318049502262 97 0 75 2 76 1 98 0 0 POLYLINE 5 900 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 901 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.44880913017124 20 -67.42945978808855 30 0.0 0 VERTEX 5 902 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.41488772417555 20 -67.45127760471145 30 0.0 0 VERTEX 5 903 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38362684699797 20 -67.47603855564147 30 0.0 0 VERTEX 5 904 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.355167801383 20 -67.50355289147885 30 0.0 0 VERTEX 5 905 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.32965189007516 20 -67.5336308628238 30 0.0 0 VERTEX 5 906 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.30722041581895 20 -67.56608272027655 30 0.0 0 VERTEX 5 907 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2880146813589 20 -67.60071871443733 30 0.0 0 VERTEX 5 908 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2721759894395 20 -67.63734909590639 30 0.0 0 VERTEX 5 909 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.25984564280528 20 -67.67578411528392 30 0.0 0 VERTEX 5 90A 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.25130557407505 20 -67.71517965688902 30 0.0 0 VERTEX 5 90B 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24672198219116 20 -67.7547871526109 30 0.0 0 VERTEX 5 90C 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24606256938344 20 -67.79436638778387 30 0.0 0 VERTEX 5 90D 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2492950378817 20 -67.83367714774226 30 0.0 0 VERTEX 5 90E 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.25638708991579 20 -67.87247921782043 30 0.0 0 VERTEX 5 90F 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.26730642771553 20 -67.91053238335267 30 0.0 0 VERTEX 5 910 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.28202075351073 20 -67.94759642967333 30 0.0 0 VERTEX 5 911 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.30049776953123 20 -67.98343114211673 30 0.0 0 VERTEX 5 912 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.32231558615413 20 -68.01735994968475 30 0.0 0 VERTEX 5 913 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.34707653708415 20 -68.04864034009847 30 0.0 0 VERTEX 5 914 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.37459087292152 20 -68.07712697339213 30 0.0 0 VERTEX 5 915 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.40466884426647 20 -68.10267450959994 30 0.0 0 VERTEX 5 916 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.43712070171923 20 -68.1251376087561 30 0.0 0 VERTEX 5 917 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.47175669588002 20 -68.14437093089485 30 0.0 0 VERTEX 5 918 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.50838707734907 20 -68.16022913605039 30 0.0 0 VERTEX 5 919 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.5468220967266 20 -68.17256688425694 30 0.0 0 VERTEX 5 91A 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.55990101147162 20 -68.17583703348708 30 0.0 0 VERTEX 5 91B 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.57303442870382 20 -68.17867116281987 30 0.0 0 VERTEX 5 91C 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.58621225537001 20 -68.1810692722553 30 0.0 0 VERTEX 5 91D 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.599424398417 20 -68.18303136179338 30 0.0 0 VERTEX 5 91E 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.61266076479163 20 -68.18455743143411 30 0.0 0 VERTEX 5 91F 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.62591126144071 20 -68.1856474811775 30 0.0 0 VERTEX 5 920 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.63916579531106 20 -68.18630151102353 30 0.0 0 VERTEX 5 921 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.6524142733495 20 -68.1865195209722 30 0.0 0 VERTEX 5 922 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.67871710637024 20 -68.18565690136046 30 0.0 0 VERTEX 5 923 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.70486854359328 20 -68.18307442548695 30 0.0 0 VERTEX 5 924 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.73079793364638 20 -68.1787801677942 30 0.0 0 VERTEX 5 925 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.75643462515727 20 -68.17278220272478 30 0.0 0 VERTEX 5 926 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.7817079667537 20 -68.16508860472119 30 0.0 0 VERTEX 5 927 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.80654730706341 20 -68.155707448226 30 0.0 0 VERTEX 5 928 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.83088199471415 20 -68.14464680768175 30 0.0 0 VERTEX 5 929 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.85464137833367 20 -68.13191475753099 30 0.0 0 VERTEX 5 92A 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.92118790586169 20 -68.08395526030313 30 0.0 0 VERTEX 5 92B 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.97521702883656 20 -68.02541824334321 30 0.0 0 VERTEX 5 92C 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.01612921989944 20 -67.95854840167834 30 0.0 0 VERTEX 5 92D 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.04332495169145 20 -67.88559043033563 30 0.0 0 VERTEX 5 92E 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05620469685373 20 -67.80878902434219 30 0.0 0 VERTEX 5 92F 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05416892802744 20 -67.73038887872512 30 0.0 0 VERTEX 5 930 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.03661811785371 20 -67.65263468851154 30 0.0 0 VERTEX 5 931 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.00295273897368 20 -67.57777114872856 30 0.0 0 VERTEX 5 932 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.95498617660859 20 -67.51125994688667 30 0.0 0 VERTEX 5 933 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.89643200145826 20 -67.45721972155329 30 0.0 0 VERTEX 5 934 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.82954096438171 20 -67.41626816758301 30 0.0 0 VERTEX 5 935 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.75656381623796 20 -67.38902297983043 30 0.0 0 VERTEX 5 936 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.67975130788603 20 -67.3761018531501 30 0.0 0 VERTEX 5 937 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.60135419018491 20 -67.37812248239663 30 0.0 0 VERTEX 5 938 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.52362321399364 20 -67.39570256242459 30 0.0 0 VERTEX 5 939 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.44880913017124 20 -67.42945978808855 30 0.0 0 VERTEX 5 93A 330 900 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.44880913017124 20 -67.42945978808855 30 0.0 0 SEQEND 5 93C 330 900 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 93B 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 56 72 1 10 24.44880913017124 20 -67.42945978808855 11 24.41488772417555 21 -67.45127760471145 72 1 10 24.41488772417555 20 -67.45127760471145 11 24.38362684699797 21 -67.47603855564147 72 1 10 24.38362684699797 20 -67.47603855564147 11 24.355167801383 21 -67.50355289147885 72 1 10 24.355167801383 20 -67.50355289147885 11 24.32965189007516 21 -67.5336308628238 72 1 10 24.32965189007516 20 -67.5336308628238 11 24.30722041581895 21 -67.56608272027655 72 1 10 24.30722041581895 20 -67.56608272027655 11 24.2880146813589 21 -67.60071871443733 72 1 10 24.2880146813589 20 -67.60071871443733 11 24.2721759894395 21 -67.63734909590639 72 1 10 24.2721759894395 20 -67.63734909590639 11 24.25984564280528 21 -67.67578411528392 72 1 10 24.25984564280528 20 -67.67578411528392 11 24.25130557407505 21 -67.71517965688902 72 1 10 24.25130557407505 20 -67.71517965688902 11 24.24672198219116 21 -67.7547871526109 72 1 10 24.24672198219116 20 -67.7547871526109 11 24.24606256938344 21 -67.79436638778387 72 1 10 24.24606256938344 20 -67.79436638778387 11 24.2492950378817 21 -67.83367714774226 72 1 10 24.2492950378817 20 -67.83367714774226 11 24.25638708991579 21 -67.87247921782043 72 1 10 24.25638708991579 20 -67.87247921782043 11 24.26730642771553 21 -67.91053238335267 72 1 10 24.26730642771553 20 -67.91053238335267 11 24.28202075351073 21 -67.94759642967333 72 1 10 24.28202075351073 20 -67.94759642967333 11 24.30049776953123 21 -67.98343114211673 72 1 10 24.30049776953123 20 -67.98343114211673 11 24.32231558615413 21 -68.01735994968475 72 1 10 24.32231558615413 20 -68.01735994968475 11 24.34707653708415 21 -68.04864034009847 72 1 10 24.34707653708415 20 -68.04864034009847 11 24.37459087292152 21 -68.07712697339213 72 1 10 24.37459087292152 20 -68.07712697339213 11 24.40466884426647 21 -68.10267450959994 72 1 10 24.40466884426647 20 -68.10267450959994 11 24.43712070171923 21 -68.1251376087561 72 1 10 24.43712070171923 20 -68.1251376087561 11 24.47175669588002 21 -68.14437093089485 72 1 10 24.47175669588002 20 -68.14437093089485 11 24.50838707734907 21 -68.16022913605039 72 1 10 24.50838707734907 20 -68.16022913605039 11 24.5468220967266 21 -68.17256688425694 72 1 10 24.5468220967266 20 -68.17256688425694 11 24.55990101147162 21 -68.17583703348708 72 1 10 24.55990101147162 20 -68.17583703348708 11 24.57303442870382 21 -68.17867116281987 72 1 10 24.57303442870382 20 -68.17867116281987 11 24.58621225537001 21 -68.1810692722553 72 1 10 24.58621225537001 20 -68.1810692722553 11 24.599424398417 21 -68.18303136179338 72 1 10 24.599424398417 20 -68.18303136179338 11 24.61266076479163 21 -68.18455743143411 72 1 10 24.61266076479163 20 -68.18455743143411 11 24.62591126144071 21 -68.1856474811775 72 1 10 24.62591126144071 20 -68.1856474811775 11 24.63916579531106 21 -68.18630151102353 72 1 10 24.63916579531106 20 -68.18630151102353 11 24.6524142733495 21 -68.1865195209722 72 1 10 24.6524142733495 20 -68.1865195209722 11 24.67871710637024 21 -68.18565690136046 72 1 10 24.67871710637024 20 -68.18565690136046 11 24.70486854359328 21 -68.18307442548695 72 1 10 24.70486854359328 20 -68.18307442548695 11 24.73079793364638 21 -68.1787801677942 72 1 10 24.73079793364638 20 -68.1787801677942 11 24.75643462515727 21 -68.17278220272478 72 1 10 24.75643462515727 20 -68.17278220272478 11 24.7817079667537 21 -68.16508860472119 72 1 10 24.7817079667537 20 -68.16508860472119 11 24.80654730706341 21 -68.155707448226 72 1 10 24.80654730706341 20 -68.155707448226 11 24.83088199471415 21 -68.14464680768175 72 1 10 24.83088199471415 20 -68.14464680768175 11 24.85464137833367 21 -68.13191475753099 72 1 10 24.85464137833367 20 -68.13191475753099 11 24.92118790586169 21 -68.08395526030313 72 1 10 24.92118790586169 20 -68.08395526030313 11 24.97521702883656 21 -68.02541824334321 72 1 10 24.97521702883656 20 -68.02541824334321 11 25.01612921989944 21 -67.95854840167834 72 1 10 25.01612921989944 20 -67.95854840167834 11 25.04332495169145 21 -67.88559043033563 72 1 10 25.04332495169145 20 -67.88559043033563 11 25.05620469685373 21 -67.80878902434219 72 1 10 25.05620469685373 20 -67.80878902434219 11 25.05416892802744 21 -67.73038887872512 72 1 10 25.05416892802744 20 -67.73038887872512 11 25.03661811785371 21 -67.65263468851154 72 1 10 25.03661811785371 20 -67.65263468851154 11 25.00295273897368 21 -67.57777114872856 72 1 10 25.00295273897368 20 -67.57777114872856 11 24.95498617660859 21 -67.51125994688667 72 1 10 24.95498617660859 20 -67.51125994688667 11 24.89643200145826 21 -67.45721972155329 72 1 10 24.89643200145826 20 -67.45721972155329 11 24.82954096438171 21 -67.41626816758301 72 1 10 24.82954096438171 20 -67.41626816758301 11 24.75656381623796 21 -67.38902297983043 72 1 10 24.75656381623796 20 -67.38902297983043 11 24.67975130788603 21 -67.3761018531501 72 1 10 24.67975130788603 20 -67.3761018531501 11 24.60135419018491 21 -67.37812248239663 72 1 10 24.60135419018491 20 -67.37812248239663 11 24.52362321399364 21 -67.39570256242459 72 1 10 24.52362321399364 20 -67.39570256242459 11 24.44880913017124 21 -67.42945978808855 97 0 75 2 76 1 98 0 0 POLYLINE 5 93D 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 93E 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.85464137833367 20 -60.39026843785182 30 0.0 0 VERTEX 5 93F 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.81861557075007 20 -60.37174903100797 30 0.0 0 VERTEX 5 940 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.7813765781743 20 -60.35702864938086 30 0.0 0 VERTEX 5 941 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.74318076415713 20 -60.34612747907685 30 0.0 0 VERTEX 5 942 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.7042844922493 20 -60.3390657062023 30 0.0 0 VERTEX 5 943 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.66494412600157 20 -60.33586351686356 30 0.0 0 VERTEX 5 944 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.6254160289647 20 -60.33654109716733 30 0.0 0 VERTEX 5 945 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.58595656468946 20 -60.341118633219 30 0.0 0 VERTEX 5 946 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.5468220967266 20 -60.34961631112587 30 0.0 0 VERTEX 5 947 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.50838707734907 20 -60.36195405933243 30 0.0 0 VERTEX 5 948 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.47175669588002 20 -60.37781226448796 30 0.0 0 VERTEX 5 949 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.43712070171923 20 -60.39704558662671 30 0.0 0 VERTEX 5 94A 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.40466884426647 20 -60.41950868578288 30 0.0 0 VERTEX 5 94B 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.37459087292152 20 -60.44505622199068 30 0.0 0 VERTEX 5 94C 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.34707653708415 20 -60.47354285528434 30 0.0 0 VERTEX 5 94D 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.32231558615413 20 -60.50482324569808 30 0.0 0 VERTEX 5 94E 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.30049776953123 20 -60.53875205326609 30 0.0 0 VERTEX 5 94F 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.2668323906512 20 -60.61361559304908 30 0.0 0 VERTEX 5 950 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24928158047747 20 -60.69136978326266 30 0.0 0 VERTEX 5 951 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.24724581165117 20 -60.76976992887972 30 0.0 0 VERTEX 5 952 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.26012555681346 20 -60.84657133487316 30 0.0 0 VERTEX 5 953 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.28732128860547 20 -60.91952930621587 30 0.0 0 VERTEX 5 954 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.32823347966834 20 -60.98639914788074 30 0.0 0 VERTEX 5 955 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.38226260264322 20 -61.04493616484066 30 0.0 0 VERTEX 5 956 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.44880913017124 20 -61.09289566206853 30 0.0 0 VERTEX 5 957 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.47256851379075 20 -61.10562771221929 30 0.0 0 VERTEX 5 958 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.49690320144149 20 -61.11668835276353 30 0.0 0 VERTEX 5 959 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.52174254175121 20 -61.12606950925872 30 0.0 0 VERTEX 5 95A 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.54701588334764 20 -61.1337631072623 30 0.0 0 VERTEX 5 95B 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.57265257485853 20 -61.13976107233174 30 0.0 0 VERTEX 5 95C 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.59858196491163 20 -61.14405533002449 30 0.0 0 VERTEX 5 95D 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.62473340213467 20 -61.146637805898 30 0.0 0 VERTEX 5 95E 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.6510362351554 20 -61.14750042550973 30 0.0 0 VERTEX 5 95F 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.66428471319385 20 -61.14728241556106 30 0.0 0 VERTEX 5 960 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.6775392470642 20 -61.14662838571503 30 0.0 0 VERTEX 5 961 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.69078974371327 20 -61.14553833597165 30 0.0 0 VERTEX 5 962 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.7040261100879 20 -61.14401226633092 30 0.0 0 VERTEX 5 963 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.7172382531349 20 -61.14205017679284 30 0.0 0 VERTEX 5 964 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.73041607980108 20 -61.1396520673574 30 0.0 0 VERTEX 5 965 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.74354949703328 20 -61.13681793802461 30 0.0 0 VERTEX 5 966 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.75662841177831 20 -61.13354778879447 30 0.0 0 VERTEX 5 967 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.79506343115584 20 -61.12121004058793 30 0.0 0 VERTEX 5 968 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.83169381262489 20 -61.10535183543238 30 0.0 0 VERTEX 5 969 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.86632980678568 20 -61.08611851329363 30 0.0 0 VERTEX 5 96A 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.89878166423843 20 -61.06365541413746 30 0.0 0 VERTEX 5 96B 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.92885963558338 20 -61.03810787792966 30 0.0 0 VERTEX 5 96C 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.95637397142076 20 -61.009621244636 30 0.0 0 VERTEX 5 96D 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.98113492235078 20 -60.97834085422227 30 0.0 0 VERTEX 5 96E 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.00295273897368 20 -60.94441204665426 30 0.0 0 VERTEX 5 96F 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.02142975499417 20 -60.90857699777575 30 0.0 0 VERTEX 5 970 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.03614408078938 20 -60.87151059640935 30 0.0 0 VERTEX 5 971 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.04706341858911 20 -60.8334510386101 30 0.0 0 VERTEX 5 972 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.0541554706232 20 -60.79463652043302 30 0.0 0 VERTEX 5 973 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05738793912147 20 -60.75530523793316 30 0.0 0 VERTEX 5 974 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05672852631374 20 -60.71569538716554 30 0.0 0 VERTEX 5 975 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.05214493442985 20 -60.6760451641852 30 0.0 0 VERTEX 5 976 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.04360486569962 20 -60.63659276504718 30 0.0 0 VERTEX 5 977 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.0312745190654 20 -60.59815774566965 30 0.0 0 VERTEX 5 978 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.01543582714601 20 -60.56152736420061 30 0.0 0 VERTEX 5 979 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.99623009268595 20 -60.52689137003982 30 0.0 0 VERTEX 5 97A 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.97379861842975 20 -60.49443951258706 30 0.0 0 VERTEX 5 97B 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.9482827071219 20 -60.46436154124179 30 0.0 0 VERTEX 5 97C 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.91982366150694 20 -60.43684720540474 30 0.0 0 VERTEX 5 97D 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.88856278432935 20 -60.41208625447472 30 0.0 0 VERTEX 5 97E 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.85464137833367 20 -60.39026843785182 30 0.0 0 VERTEX 5 97F 330 93D 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 24.85464137833367 20 -60.39026843785182 30 0.0 0 SEQEND 5 981 330 93D 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 980 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 24.85464137833367 20 -60.39026843785182 11 24.81861557075007 21 -60.37174903100797 72 1 10 24.81861557075007 20 -60.37174903100797 11 24.7813765781743 21 -60.35702864938086 72 1 10 24.7813765781743 20 -60.35702864938086 11 24.74318076415713 21 -60.34612747907685 72 1 10 24.74318076415713 20 -60.34612747907685 11 24.7042844922493 21 -60.3390657062023 72 1 10 24.7042844922493 20 -60.3390657062023 11 24.66494412600157 21 -60.33586351686356 72 1 10 24.66494412600157 20 -60.33586351686356 11 24.6254160289647 21 -60.33654109716733 72 1 10 24.6254160289647 20 -60.33654109716733 11 24.58595656468946 21 -60.341118633219 72 1 10 24.58595656468946 20 -60.341118633219 11 24.5468220967266 21 -60.34961631112587 72 1 10 24.5468220967266 20 -60.34961631112587 11 24.50838707734907 21 -60.36195405933243 72 1 10 24.50838707734907 20 -60.36195405933243 11 24.47175669588002 21 -60.37781226448796 72 1 10 24.47175669588002 20 -60.37781226448796 11 24.43712070171923 21 -60.39704558662671 72 1 10 24.43712070171923 20 -60.39704558662671 11 24.40466884426647 21 -60.41950868578288 72 1 10 24.40466884426647 20 -60.41950868578288 11 24.37459087292152 21 -60.44505622199068 72 1 10 24.37459087292152 20 -60.44505622199068 11 24.34707653708415 21 -60.47354285528434 72 1 10 24.34707653708415 20 -60.47354285528434 11 24.32231558615413 21 -60.50482324569808 72 1 10 24.32231558615413 20 -60.50482324569808 11 24.30049776953123 21 -60.53875205326609 72 1 10 24.30049776953123 20 -60.53875205326609 11 24.2668323906512 21 -60.61361559304908 72 1 10 24.2668323906512 20 -60.61361559304908 11 24.24928158047747 21 -60.69136978326266 72 1 10 24.24928158047747 20 -60.69136978326266 11 24.24724581165117 21 -60.76976992887972 72 1 10 24.24724581165117 20 -60.76976992887972 11 24.26012555681346 21 -60.84657133487316 72 1 10 24.26012555681346 20 -60.84657133487316 11 24.28732128860547 21 -60.91952930621587 72 1 10 24.28732128860547 20 -60.91952930621587 11 24.32823347966834 21 -60.98639914788074 72 1 10 24.32823347966834 20 -60.98639914788074 11 24.38226260264322 21 -61.04493616484066 72 1 10 24.38226260264322 20 -61.04493616484066 11 24.44880913017124 21 -61.09289566206853 72 1 10 24.44880913017124 20 -61.09289566206853 11 24.47256851379075 21 -61.10562771221929 72 1 10 24.47256851379075 20 -61.10562771221929 11 24.49690320144149 21 -61.11668835276353 72 1 10 24.49690320144149 20 -61.11668835276353 11 24.52174254175121 21 -61.12606950925872 72 1 10 24.52174254175121 20 -61.12606950925872 11 24.54701588334764 21 -61.1337631072623 72 1 10 24.54701588334764 20 -61.1337631072623 11 24.57265257485853 21 -61.13976107233174 72 1 10 24.57265257485853 20 -61.13976107233174 11 24.59858196491163 21 -61.14405533002449 72 1 10 24.59858196491163 20 -61.14405533002449 11 24.62473340213467 21 -61.146637805898 72 1 10 24.62473340213467 20 -61.146637805898 11 24.6510362351554 21 -61.14750042550973 72 1 10 24.6510362351554 20 -61.14750042550973 11 24.66428471319385 21 -61.14728241556106 72 1 10 24.66428471319385 20 -61.14728241556106 11 24.6775392470642 21 -61.14662838571503 72 1 10 24.6775392470642 20 -61.14662838571503 11 24.69078974371327 21 -61.14553833597165 72 1 10 24.69078974371327 20 -61.14553833597165 11 24.7040261100879 21 -61.14401226633092 72 1 10 24.7040261100879 20 -61.14401226633092 11 24.7172382531349 21 -61.14205017679284 72 1 10 24.7172382531349 20 -61.14205017679284 11 24.73041607980108 21 -61.1396520673574 72 1 10 24.73041607980108 20 -61.1396520673574 11 24.74354949703328 21 -61.13681793802461 72 1 10 24.74354949703328 20 -61.13681793802461 11 24.75662841177831 21 -61.13354778879447 72 1 10 24.75662841177831 20 -61.13354778879447 11 24.79506343115584 21 -61.12121004058793 72 1 10 24.79506343115584 20 -61.12121004058793 11 24.83169381262489 21 -61.10535183543238 72 1 10 24.83169381262489 20 -61.10535183543238 11 24.86632980678568 21 -61.08611851329363 72 1 10 24.86632980678568 20 -61.08611851329363 11 24.89878166423843 21 -61.06365541413746 72 1 10 24.89878166423843 20 -61.06365541413746 11 24.92885963558338 21 -61.03810787792966 72 1 10 24.92885963558338 20 -61.03810787792966 11 24.95637397142076 21 -61.009621244636 72 1 10 24.95637397142076 20 -61.009621244636 11 24.98113492235078 21 -60.97834085422227 72 1 10 24.98113492235078 20 -60.97834085422227 11 25.00295273897368 21 -60.94441204665426 72 1 10 25.00295273897368 20 -60.94441204665426 11 25.02142975499417 21 -60.90857699777575 72 1 10 25.02142975499417 20 -60.90857699777575 11 25.03614408078938 21 -60.87151059640935 72 1 10 25.03614408078938 20 -60.87151059640935 11 25.04706341858911 21 -60.8334510386101 72 1 10 25.04706341858911 20 -60.8334510386101 11 25.0541554706232 21 -60.79463652043302 72 1 10 25.0541554706232 20 -60.79463652043302 11 25.05738793912147 21 -60.75530523793316 72 1 10 25.05738793912147 20 -60.75530523793316 11 25.05672852631374 21 -60.71569538716554 72 1 10 25.05672852631374 20 -60.71569538716554 11 25.05214493442985 21 -60.6760451641852 72 1 10 25.05214493442985 20 -60.6760451641852 11 25.04360486569962 21 -60.63659276504718 72 1 10 25.04360486569962 20 -60.63659276504718 11 25.0312745190654 21 -60.59815774566965 72 1 10 25.0312745190654 20 -60.59815774566965 11 25.01543582714601 21 -60.56152736420061 72 1 10 25.01543582714601 20 -60.56152736420061 11 24.99623009268595 21 -60.52689137003982 72 1 10 24.99623009268595 20 -60.52689137003982 11 24.97379861842975 21 -60.49443951258706 72 1 10 24.97379861842975 20 -60.49443951258706 11 24.9482827071219 21 -60.46436154124179 72 1 10 24.9482827071219 20 -60.46436154124179 11 24.91982366150694 21 -60.43684720540474 72 1 10 24.91982366150694 20 -60.43684720540474 11 24.88856278432935 21 -60.41208625447472 72 1 10 24.88856278432935 20 -60.41208625447472 11 24.85464137833367 21 -60.39026843785182 97 0 75 2 76 1 98 0 0 POLYLINE 5 982 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 983 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.6198079370521 20 -60.60283082929173 30 0.0 0 VERTEX 5 984 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.70148193268547 20 -60.59457773970691 30 0.0 0 VERTEX 5 985 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.77759061879569 20 -60.57091255791707 30 0.0 0 VERTEX 5 986 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.8464928649358 20 -60.5334764143692 30 0.0 0 VERTEX 5 987 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9065475406588 20 -60.48391043951027 30 0.0 0 VERTEX 5 988 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.95611351551772 20 -60.42385576378727 30 0.0 0 VERTEX 5 989 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9935496590656 20 -60.35495351764716 30 0.0 0 VERTEX 5 98A 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.01721484085544 20 -60.27884483153694 30 0.0 0 VERTEX 5 98B 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.02546793044027 20 -60.19717083590357 30 0.0 0 VERTEX 5 98C 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 23.01721484085544 20 -60.1154968402702 30 0.0 0 VERTEX 5 98D 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9935496590656 20 -60.03938815415997 30 0.0 0 VERTEX 5 98E 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.95611351551772 20 -59.97048590801987 30 0.0 0 VERTEX 5 98F 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.9065475406588 20 -59.91043123229687 30 0.0 0 VERTEX 5 990 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.8464928649358 20 -59.86086525743794 30 0.0 0 VERTEX 5 991 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.77759061879569 20 -59.82342911389007 30 0.0 0 VERTEX 5 992 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.70148193268547 20 -59.79976393210023 30 0.0 0 VERTEX 5 993 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.6198079370521 20 -59.7915108425154 30 0.0 0 VERTEX 5 994 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.5381265398464 20 -59.79976393210023 30 0.0 0 VERTEX 5 995 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.46199834050002 20 -59.82342911389007 30 0.0 0 VERTEX 5 996 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.39306850668123 20 -59.86086525743794 30 0.0 0 VERTEX 5 997 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.33298220605827 20 -59.91043123229687 30 0.0 0 VERTEX 5 998 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.28338460629938 20 -59.97048590801987 30 0.0 0 VERTEX 5 999 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.24592087507282 20 -60.03938815415997 30 0.0 0 VERTEX 5 99A 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.22223618004683 20 -60.1154968402702 30 0.0 0 VERTEX 5 99B 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.21397568888967 20 -60.19717083590357 30 0.0 0 VERTEX 5 99C 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.22223618004683 20 -60.27884483153694 30 0.0 0 VERTEX 5 99D 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.24592087507282 20 -60.35495351764716 30 0.0 0 VERTEX 5 99E 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.28338460629938 20 -60.42385576378727 30 0.0 0 VERTEX 5 99F 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.33298220605827 20 -60.48391043951027 30 0.0 0 VERTEX 5 9A0 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.39306850668123 20 -60.5334764143692 30 0.0 0 VERTEX 5 9A1 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.46199834050002 20 -60.57091255791707 30 0.0 0 VERTEX 5 9A2 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.5381265398464 20 -60.59457773970691 30 0.0 0 VERTEX 5 9A3 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.6198079370521 20 -60.60283082929173 30 0.0 0 VERTEX 5 9A4 330 982 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 22.6198079370521 20 -60.60283082929173 30 0.0 0 SEQEND 5 9A6 330 982 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 9A5 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 32 72 1 10 22.6198079370521 20 -60.60283082929173 11 22.70148193268547 21 -60.59457773970691 72 1 10 22.70148193268547 20 -60.59457773970691 11 22.77759061879569 21 -60.57091255791707 72 1 10 22.77759061879569 20 -60.57091255791707 11 22.8464928649358 21 -60.5334764143692 72 1 10 22.8464928649358 20 -60.5334764143692 11 22.9065475406588 21 -60.48391043951027 72 1 10 22.9065475406588 20 -60.48391043951027 11 22.95611351551772 21 -60.42385576378727 72 1 10 22.95611351551772 20 -60.42385576378727 11 22.9935496590656 21 -60.35495351764716 72 1 10 22.9935496590656 20 -60.35495351764716 11 23.01721484085544 21 -60.27884483153694 72 1 10 23.01721484085544 20 -60.27884483153694 11 23.02546793044027 21 -60.19717083590357 72 1 10 23.02546793044027 20 -60.19717083590357 11 23.01721484085544 21 -60.1154968402702 72 1 10 23.01721484085544 20 -60.1154968402702 11 22.9935496590656 21 -60.03938815415997 72 1 10 22.9935496590656 20 -60.03938815415997 11 22.95611351551772 21 -59.97048590801987 72 1 10 22.95611351551772 20 -59.97048590801987 11 22.9065475406588 21 -59.91043123229687 72 1 10 22.9065475406588 20 -59.91043123229687 11 22.8464928649358 21 -59.86086525743794 72 1 10 22.8464928649358 20 -59.86086525743794 11 22.77759061879569 21 -59.82342911389007 72 1 10 22.77759061879569 20 -59.82342911389007 11 22.70148193268547 21 -59.79976393210023 72 1 10 22.70148193268547 20 -59.79976393210023 11 22.6198079370521 21 -59.7915108425154 72 1 10 22.6198079370521 20 -59.7915108425154 11 22.5381265398464 21 -59.79976393210023 72 1 10 22.5381265398464 20 -59.79976393210023 11 22.46199834050002 21 -59.82342911389007 72 1 10 22.46199834050002 20 -59.82342911389007 11 22.39306850668123 21 -59.86086525743794 72 1 10 22.39306850668123 20 -59.86086525743794 11 22.33298220605827 21 -59.91043123229687 72 1 10 22.33298220605827 20 -59.91043123229687 11 22.28338460629938 21 -59.97048590801987 72 1 10 22.28338460629938 20 -59.97048590801987 11 22.24592087507282 21 -60.03938815415997 72 1 10 22.24592087507282 20 -60.03938815415997 11 22.22223618004683 21 -60.1154968402702 72 1 10 22.22223618004683 20 -60.1154968402702 11 22.21397568888967 21 -60.19717083590357 72 1 10 22.21397568888967 20 -60.19717083590357 11 22.22223618004683 21 -60.27884483153694 72 1 10 22.22223618004683 20 -60.27884483153694 11 22.24592087507282 21 -60.35495351764716 72 1 10 22.24592087507282 20 -60.35495351764716 11 22.28338460629938 21 -60.42385576378727 72 1 10 22.28338460629938 20 -60.42385576378727 11 22.33298220605827 21 -60.48391043951027 72 1 10 22.33298220605827 20 -60.48391043951027 11 22.39306850668123 21 -60.5334764143692 72 1 10 22.39306850668123 20 -60.5334764143692 11 22.46199834050002 21 -60.57091255791707 72 1 10 22.46199834050002 20 -60.57091255791707 11 22.5381265398464 21 -60.59457773970691 72 1 10 22.5381265398464 20 -60.59457773970691 11 22.6198079370521 21 -60.60283082929173 97 0 75 2 76 1 98 0 0 POLYLINE 5 9A7 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 9A8 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.89993760578068 20 -62.63457589171783 30 0.0 0 VERTEX 5 9A9 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.92574587919562 20 -62.63375633579966 30 0.0 0 VERTEX 5 9AA 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.95156828288501 20 -62.63128151916038 30 0.0 0 VERTEX 5 9AB 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.97732205381278 20 -62.62712721847172 30 0.0 0 VERTEX 5 9AC 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.00292442894286 20 -62.62126921040605 30 0.0 0 VERTEX 5 9AD 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.02829264523918 20 -62.6136832716367 30 0.0 0 VERTEX 5 9AE 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.05334393966567 20 -62.60434517883476 30 0.0 0 VERTEX 5 9AF 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.07799554918624 20 -62.59323070867388 30 0.0 0 VERTEX 5 9B0 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.10216471076484 20 -62.58031563782514 30 0.0 0 VERTEX 5 9B1 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.13608611676053 20 -62.55849782120224 30 0.0 0 VERTEX 5 9B2 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.16734699393811 20 -62.53373687027255 30 0.0 0 VERTEX 5 9B3 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.19580603955308 20 -62.50622253443485 30 0.0 0 VERTEX 5 9B4 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.22132195086092 20 -62.4761445630899 30 0.0 0 VERTEX 5 9B5 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.24375342511713 20 -62.44369270563715 30 0.0 0 VERTEX 5 9B6 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.26295915957718 20 -62.40905671147635 30 0.0 0 VERTEX 5 9B7 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.27879785149658 20 -62.37242633000731 30 0.0 0 VERTEX 5 9B8 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.2911281981308 20 -62.33399131062978 30 0.0 0 VERTEX 5 9B9 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.29966826686103 20 -62.29459576902499 30 0.0 0 VERTEX 5 9BA 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.30425185874492 20 -62.25498827330279 30 0.0 0 VERTEX 5 9BB 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.30491127155264 20 -62.21540903812982 30 0.0 0 VERTEX 5 9BC 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.30167880305437 20 -62.17609827817142 30 0.0 0 VERTEX 5 9BD 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.29458675102028 20 -62.13729620809327 30 0.0 0 VERTEX 5 9BE 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.28366741322055 20 -62.09924304256103 30 0.0 0 VERTEX 5 9BF 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.26895308742535 20 -62.06217899624037 30 0.0 0 VERTEX 5 9C0 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.25047607140485 20 -62.02634428379697 30 0.0 0 VERTEX 5 9C1 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.22865825478195 20 -61.99241547622896 30 0.0 0 VERTEX 5 9C2 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.20389730385193 20 -61.96113508581522 30 0.0 0 VERTEX 5 9C3 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.17638296801456 20 -61.93264845252156 30 0.0 0 VERTEX 5 9C4 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.14630499666961 20 -61.90710091631376 30 0.0 0 VERTEX 5 9C5 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.11385313921685 20 -61.88463781715759 30 0.0 0 VERTEX 5 9C6 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.07921714505606 20 -61.86540449501884 30 0.0 0 VERTEX 5 9C7 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.04258676358702 20 -61.84954628986331 30 0.0 0 VERTEX 5 9C8 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.00415174420949 20 -61.83720854165675 30 0.0 0 VERTEX 5 9C9 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.96485477809043 20 -61.82876031971045 30 0.0 0 VERTEX 5 9CA 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.92529135536744 20 -61.82420599768079 30 0.0 0 VERTEX 5 9CB 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.88571178375936 20 -61.82353144529329 30 0.0 0 VERTEX 5 9CC 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.84636637098504 20 -61.82672253227352 30 0.0 0 VERTEX 5 9CD 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.80750542476334 20 -61.83376512834703 30 0.0 0 VERTEX 5 9CE 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.7693792528131 20 -61.84464510323937 30 0.0 0 VERTEX 5 9CF 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.73223816285317 20 -61.85934832667607 30 0.0 0 VERTEX 5 9D0 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.69633246260241 20 -61.8778606683827 30 0.0 0 VERTEX 5 9D1 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.62978593507439 20 -61.92582016561057 30 0.0 0 VERTEX 5 9D2 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.57575681209951 20 -61.98435718257048 30 0.0 0 VERTEX 5 9D3 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.53484462103664 20 -62.05122702423535 30 0.0 0 VERTEX 5 9D4 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.50764888924463 20 -62.12418499557806 30 0.0 0 VERTEX 5 9D5 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.49476914408235 20 -62.20098640157151 30 0.0 0 VERTEX 5 9D6 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.49680491290864 20 -62.27938654718857 30 0.0 0 VERTEX 5 9D7 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.51435572308237 20 -62.35714073740215 30 0.0 0 VERTEX 5 9D8 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.54802110196241 20 -62.43200427718514 30 0.0 0 VERTEX 5 9D9 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.57890483538618 20 -62.47799832052386 30 0.0 0 VERTEX 5 9DA 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.61490170955067 20 -62.51844925905643 30 0.0 0 VERTEX 5 9DB 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.65532741545029 20 -62.55317541782562 30 0.0 0 VERTEX 5 9DC 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.69949764407949 20 -62.5819951218742 30 0.0 0 VERTEX 5 9DD 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.74672808643269 20 -62.60472669624495 30 0.0 0 VERTEX 5 9DE 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.79633443350433 20 -62.62118846598062 30 0.0 0 VERTEX 5 9DF 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.84763237628885 20 -62.63119875612399 30 0.0 0 VERTEX 5 9E0 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.89993760578068 20 -62.63457589171783 30 0.0 0 VERTEX 5 9E1 330 9A7 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.89993760578068 20 -62.63457589171783 30 0.0 0 SEQEND 5 9E3 330 9A7 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 9E2 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 56 72 1 10 10.89993760578068 20 -62.63457589171783 11 10.92574587919562 21 -62.63375633579966 72 1 10 10.92574587919562 20 -62.63375633579966 11 10.95156828288501 21 -62.63128151916038 72 1 10 10.95156828288501 20 -62.63128151916038 11 10.97732205381278 21 -62.62712721847172 72 1 10 10.97732205381278 20 -62.62712721847172 11 11.00292442894286 21 -62.62126921040605 72 1 10 11.00292442894286 20 -62.62126921040605 11 11.02829264523918 21 -62.6136832716367 72 1 10 11.02829264523918 20 -62.6136832716367 11 11.05334393966567 21 -62.60434517883476 72 1 10 11.05334393966567 20 -62.60434517883476 11 11.07799554918624 21 -62.59323070867388 72 1 10 11.07799554918624 20 -62.59323070867388 11 11.10216471076484 21 -62.58031563782514 72 1 10 11.10216471076484 20 -62.58031563782514 11 11.13608611676053 21 -62.55849782120224 72 1 10 11.13608611676053 20 -62.55849782120224 11 11.16734699393811 21 -62.53373687027255 72 1 10 11.16734699393811 20 -62.53373687027255 11 11.19580603955308 21 -62.50622253443485 72 1 10 11.19580603955308 20 -62.50622253443485 11 11.22132195086092 21 -62.4761445630899 72 1 10 11.22132195086092 20 -62.4761445630899 11 11.24375342511713 21 -62.44369270563715 72 1 10 11.24375342511713 20 -62.44369270563715 11 11.26295915957718 21 -62.40905671147635 72 1 10 11.26295915957718 20 -62.40905671147635 11 11.27879785149658 21 -62.37242633000731 72 1 10 11.27879785149658 20 -62.37242633000731 11 11.2911281981308 21 -62.33399131062978 72 1 10 11.2911281981308 20 -62.33399131062978 11 11.29966826686103 21 -62.29459576902499 72 1 10 11.29966826686103 20 -62.29459576902499 11 11.30425185874492 21 -62.25498827330279 72 1 10 11.30425185874492 20 -62.25498827330279 11 11.30491127155264 21 -62.21540903812982 72 1 10 11.30491127155264 20 -62.21540903812982 11 11.30167880305437 21 -62.17609827817142 72 1 10 11.30167880305437 20 -62.17609827817142 11 11.29458675102028 21 -62.13729620809327 72 1 10 11.29458675102028 20 -62.13729620809327 11 11.28366741322055 21 -62.09924304256103 72 1 10 11.28366741322055 20 -62.09924304256103 11 11.26895308742535 21 -62.06217899624037 72 1 10 11.26895308742535 20 -62.06217899624037 11 11.25047607140485 21 -62.02634428379697 72 1 10 11.25047607140485 20 -62.02634428379697 11 11.22865825478195 21 -61.99241547622896 72 1 10 11.22865825478195 20 -61.99241547622896 11 11.20389730385193 21 -61.96113508581522 72 1 10 11.20389730385193 20 -61.96113508581522 11 11.17638296801456 21 -61.93264845252156 72 1 10 11.17638296801456 20 -61.93264845252156 11 11.14630499666961 21 -61.90710091631376 72 1 10 11.14630499666961 20 -61.90710091631376 11 11.11385313921685 21 -61.88463781715759 72 1 10 11.11385313921685 20 -61.88463781715759 11 11.07921714505606 21 -61.86540449501884 72 1 10 11.07921714505606 20 -61.86540449501884 11 11.04258676358702 21 -61.84954628986331 72 1 10 11.04258676358702 20 -61.84954628986331 11 11.00415174420949 21 -61.83720854165675 72 1 10 11.00415174420949 20 -61.83720854165675 11 10.96485477809043 21 -61.82876031971045 72 1 10 10.96485477809043 20 -61.82876031971045 11 10.92529135536744 21 -61.82420599768079 72 1 10 10.92529135536744 20 -61.82420599768079 11 10.88571178375936 21 -61.82353144529329 72 1 10 10.88571178375936 20 -61.82353144529329 11 10.84636637098504 21 -61.82672253227352 72 1 10 10.84636637098504 20 -61.82672253227352 11 10.80750542476334 21 -61.83376512834703 72 1 10 10.80750542476334 20 -61.83376512834703 11 10.7693792528131 21 -61.84464510323937 72 1 10 10.7693792528131 20 -61.84464510323937 11 10.73223816285317 21 -61.85934832667607 72 1 10 10.73223816285317 20 -61.85934832667607 11 10.69633246260241 21 -61.8778606683827 72 1 10 10.69633246260241 20 -61.8778606683827 11 10.62978593507439 21 -61.92582016561057 72 1 10 10.62978593507439 20 -61.92582016561057 11 10.57575681209951 21 -61.98435718257048 72 1 10 10.57575681209951 20 -61.98435718257048 11 10.53484462103664 21 -62.05122702423535 72 1 10 10.53484462103664 20 -62.05122702423535 11 10.50764888924463 21 -62.12418499557806 72 1 10 10.50764888924463 20 -62.12418499557806 11 10.49476914408235 21 -62.20098640157151 72 1 10 10.49476914408235 20 -62.20098640157151 11 10.49680491290864 21 -62.27938654718857 72 1 10 10.49680491290864 20 -62.27938654718857 11 10.51435572308237 21 -62.35714073740215 72 1 10 10.51435572308237 20 -62.35714073740215 11 10.54802110196241 21 -62.43200427718514 72 1 10 10.54802110196241 20 -62.43200427718514 11 10.57890483538618 21 -62.47799832052386 72 1 10 10.57890483538618 20 -62.47799832052386 11 10.61490170955067 21 -62.51844925905643 72 1 10 10.61490170955067 20 -62.51844925905643 11 10.65532741545029 21 -62.55317541782562 72 1 10 10.65532741545029 20 -62.55317541782562 11 10.69949764407949 21 -62.5819951218742 72 1 10 10.69949764407949 20 -62.5819951218742 11 10.74672808643269 21 -62.60472669624495 72 1 10 10.74672808643269 20 -62.60472669624495 11 10.79633443350433 21 -62.62118846598062 72 1 10 10.79633443350433 20 -62.62118846598062 11 10.84763237628885 21 -62.63119875612399 72 1 10 10.84763237628885 20 -62.63119875612399 11 10.89993760578068 21 -62.63457589171783 97 0 75 2 76 1 98 0 0 INSERT 5 9E5 330 1F 100 AcDbEntity 8 Graphics 100 AcDbBlockReference 2 block 4 10 0.0 20 0.0 30 0.0 0 POLYLINE 5 C35 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 C36 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.27798257806464 20 -64.26117772507854 30 0.0 0 VERTEX 5 C37 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.2862430692218 20 -64.3428517207116 30 0.0 0 VERTEX 5 C38 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.30992776424779 20 -64.41896040682214 30 0.0 0 VERTEX 5 C39 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.34739149547435 20 -64.48786265296256 30 0.0 0 VERTEX 5 C3A 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.39698909523324 20 -64.54791732868524 30 0.0 0 VERTEX 5 C3B 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.4570753958562 20 -64.59748330354417 30 0.0 0 VERTEX 5 C3C 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.526005229675 20 -64.63491944709203 30 0.0 0 VERTEX 5 C3D 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.60213342902137 20 -64.65858462888188 30 0.0 0 VERTEX 5 C3E 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.68381482622707 20 -64.66683771846671 30 0.0 0 VERTEX 5 C3F 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.76548882186044 20 -64.65858462888188 30 0.0 0 VERTEX 5 C40 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.84159750797066 20 -64.63491944709203 30 0.0 0 VERTEX 5 C41 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.91049975411077 20 -64.59748330354417 30 0.0 0 VERTEX 5 C42 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.97055442983377 20 -64.54791732868524 30 0.0 0 VERTEX 5 C43 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.0201204046927 20 -64.48786265296256 30 0.0 0 VERTEX 5 C44 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.05755654824057 20 -64.41896040682214 30 0.0 0 VERTEX 5 C45 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.08122173003041 20 -64.3428517207116 30 0.0 0 VERTEX 5 C46 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.08947481961524 20 -64.26117772507854 30 0.0 0 VERTEX 5 C47 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.08122173003041 20 -64.17949632787284 30 0.0 0 VERTEX 5 C48 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.05755654824057 20 -64.10336812852647 30 0.0 0 VERTEX 5 C49 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 27.0201204046927 20 -64.03443829470767 30 0.0 0 VERTEX 5 C4A 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.97055442983377 20 -63.97435199408503 30 0.0 0 VERTEX 5 C4B 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.91049975411077 20 -63.92475439432582 30 0.0 0 VERTEX 5 C4C 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.84159750797066 20 -63.88729066309926 30 0.0 0 VERTEX 5 C4D 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.76548882186044 20 -63.86360596807295 30 0.0 0 VERTEX 5 C4E 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.68381482622707 20 -63.85534547691611 30 0.0 0 VERTEX 5 C4F 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.60213342902137 20 -63.86360596807295 30 0.0 0 VERTEX 5 C50 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.526005229675 20 -63.88729066309926 30 0.0 0 VERTEX 5 C51 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.4570753958562 20 -63.92475439432582 30 0.0 0 VERTEX 5 C52 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.39698909523324 20 -63.97435199408503 30 0.0 0 VERTEX 5 C53 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.34739149547435 20 -64.03443829470767 30 0.0 0 VERTEX 5 C54 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.30992776424779 20 -64.10336812852647 30 0.0 0 VERTEX 5 C55 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.2862430692218 20 -64.17949632787284 30 0.0 0 VERTEX 5 C56 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.27798257806464 20 -64.26117772507854 30 0.0 0 VERTEX 5 C57 330 C35 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.27798257806464 20 -64.26117772507854 30 0.0 0 SEQEND 5 C59 330 C35 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 C58 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 32 72 1 10 26.27798257806464 20 -64.26117772507854 11 26.2862430692218 21 -64.3428517207116 72 1 10 26.2862430692218 20 -64.3428517207116 11 26.30992776424779 21 -64.41896040682214 72 1 10 26.30992776424779 20 -64.41896040682214 11 26.34739149547435 21 -64.48786265296256 72 1 10 26.34739149547435 20 -64.48786265296256 11 26.39698909523324 21 -64.54791732868524 72 1 10 26.39698909523324 20 -64.54791732868524 11 26.4570753958562 21 -64.59748330354417 72 1 10 26.4570753958562 20 -64.59748330354417 11 26.526005229675 21 -64.63491944709203 72 1 10 26.526005229675 20 -64.63491944709203 11 26.60213342902137 21 -64.65858462888188 72 1 10 26.60213342902137 20 -64.65858462888188 11 26.68381482622707 21 -64.66683771846671 72 1 10 26.68381482622707 20 -64.66683771846671 11 26.76548882186044 21 -64.65858462888188 72 1 10 26.76548882186044 20 -64.65858462888188 11 26.84159750797066 21 -64.63491944709203 72 1 10 26.84159750797066 20 -64.63491944709203 11 26.91049975411077 21 -64.59748330354417 72 1 10 26.91049975411077 20 -64.59748330354417 11 26.97055442983377 21 -64.54791732868524 72 1 10 26.97055442983377 20 -64.54791732868524 11 27.0201204046927 21 -64.48786265296256 72 1 10 27.0201204046927 20 -64.48786265296256 11 27.05755654824057 21 -64.41896040682214 72 1 10 27.05755654824057 20 -64.41896040682214 11 27.08122173003041 21 -64.3428517207116 72 1 10 27.08122173003041 20 -64.3428517207116 11 27.08947481961524 21 -64.26117772507854 72 1 10 27.08947481961524 20 -64.26117772507854 11 27.08122173003041 21 -64.17949632787284 72 1 10 27.08122173003041 20 -64.17949632787284 11 27.05755654824057 21 -64.10336812852647 72 1 10 27.05755654824057 20 -64.10336812852647 11 27.0201204046927 21 -64.03443829470767 72 1 10 27.0201204046927 20 -64.03443829470767 11 26.97055442983377 21 -63.97435199408503 72 1 10 26.97055442983377 20 -63.97435199408503 11 26.91049975411077 21 -63.92475439432582 72 1 10 26.91049975411077 20 -63.92475439432582 11 26.84159750797066 21 -63.88729066309926 72 1 10 26.84159750797066 20 -63.88729066309926 11 26.76548882186044 21 -63.86360596807295 72 1 10 26.76548882186044 20 -63.86360596807295 11 26.68381482622707 21 -63.85534547691611 72 1 10 26.68381482622707 20 -63.85534547691611 11 26.60213342902137 21 -63.86360596807295 72 1 10 26.60213342902137 20 -63.86360596807295 11 26.526005229675 21 -63.88729066309926 72 1 10 26.526005229675 20 -63.88729066309926 11 26.4570753958562 21 -63.92475439432582 72 1 10 26.4570753958562 20 -63.92475439432582 11 26.39698909523324 21 -63.97435199408503 72 1 10 26.39698909523324 20 -63.97435199408503 11 26.34739149547435 21 -64.03443829470767 72 1 10 26.34739149547435 20 -64.03443829470767 11 26.30992776424779 21 -64.10336812852647 72 1 10 26.30992776424779 20 -64.10336812852647 11 26.2862430692218 21 -64.17949632787284 72 1 10 26.2862430692218 20 -64.17949632787284 11 26.27798257806464 21 -64.26117772507854 97 0 75 2 76 1 98 0 0 INSERT 5 C5B 330 1F 100 AcDbEntity 8 Graphics 100 AcDbBlockReference 2 block 5 10 0.0 20 0.0 30 0.0 0 POLYLINE 5 DC5 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 DC6 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.20520154684672 20 -65.90121543083173 30 0.0 0 VERTEX 5 DC7 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.16579860366928 20 -65.89276720888543 30 0.0 0 VERTEX 5 DC8 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.12617159471126 20 -65.88821288685575 30 0.0 0 VERTEX 5 DC9 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.0865647718596 20 -65.88753833446826 30 0.0 0 VERTEX 5 DCA 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.04722238700123 20 -65.8907294214485 30 0.0 0 VERTEX 5 DCB 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.00838869202312 20 -65.897772017522 30 0.0 0 VERTEX 5 DCC 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.97030793881218 20 -65.90865199241433 30 0.0 0 VERTEX 5 DCD 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.93322437925538 20 -65.92335521585105 30 0.0 0 VERTEX 5 DCE 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.89738226523965 20 -65.94186755755767 30 0.0 0 VERTEX 5 DCF 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.86345345767164 20 -65.96368537418057 30 0.0 0 VERTEX 5 DD0 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.83217306725791 20 -65.98844632511059 30 0.0 0 VERTEX 5 DD1 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.80368643396424 20 -66.01596066094797 30 0.0 0 VERTEX 5 DD2 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.77813889775644 20 -66.04603863229292 30 0.0 0 VERTEX 5 DD3 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.75567579860027 20 -66.07849048974568 30 0.0 0 VERTEX 5 DD4 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.73644247646153 20 -66.11312648390646 30 0.0 0 VERTEX 5 DD5 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.72058427130598 20 -66.14975686537551 30 0.0 0 VERTEX 5 DD6 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.70824652309943 20 -66.18819188475304 30 0.0 0 VERTEX 5 DD7 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.6997064543692 20 -66.22758776279325 30 0.0 0 VERTEX 5 DD8 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.69512286248531 20 -66.26719761356087 30 0.0 0 VERTEX 5 DD9 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.69446344967758 20 -66.30678324100086 30 0.0 0 VERTEX 5 DDA 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.69769591817586 20 -66.34610644905817 30 0.0 0 VERTEX 5 DDB 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.70478797020995 20 -66.3849290416778 30 0.0 0 VERTEX 5 DDC 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.71570730800968 20 -66.42301282280468 30 0.0 0 VERTEX 5 DDD 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.73042163380488 20 -66.46011959638379 30 0.0 0 VERTEX 5 DDE 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.74889864982538 20 -66.4960111663601 30 0.0 0 VERTEX 5 DDF 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.77978238324916 20 -66.54201227483605 30 0.0 0 VERTEX 5 DE0 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.81577925741364 20 -66.58248037155903 30 0.0 0 VERTEX 5 DE1 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.85620496331326 20 -66.6172277257399 30 0.0 0 VERTEX 5 DE2 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.90037519194246 20 -66.64606660658953 30 0.0 0 VERTEX 5 DE3 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.94760563429566 20 -66.66880928331877 30 0.0 0 VERTEX 5 DE4 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.99721198136731 20 -66.68526802513848 30 0.0 0 VERTEX 5 DE5 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.04850992415183 20 -66.69525510125953 30 0.0 0 VERTEX 5 DE6 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.10081515364365 20 -66.69858278089279 30 0.0 0 VERTEX 5 DE7 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.12662342705859 20 -66.69776322497462 30 0.0 0 VERTEX 5 DE8 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.15244583074799 20 -66.69528840833503 30 0.0 0 VERTEX 5 DE9 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.17819960167576 20 -66.69113410764636 30 0.0 0 VERTEX 5 DEA 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.20380197680584 20 -66.68527609958102 30 0.0 0 VERTEX 5 DEB 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.22917019310216 20 -66.67769016081135 30 0.0 0 VERTEX 5 DEC 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.25422148752864 20 -66.66835206800972 30 0.0 0 VERTEX 5 DED 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.27887309704922 20 -66.65723759784854 30 0.0 0 VERTEX 5 DEE 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.30304225862782 20 -66.64432252700011 30 0.0 0 VERTEX 5 DEF 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.33697106619583 20 -66.62250504681232 30 0.0 0 VERTEX 5 DF0 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.36825145660956 20 -66.59774645092804 30 0.0 0 VERTEX 5 DF1 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.39673808990322 20 -66.57023850735769 30 0.0 0 VERTEX 5 DF2 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42228562611103 20 -66.54017298411165 30 0.0 0 VERTEX 5 DF3 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4447487252672 20 -66.50774164920037 30 0.0 0 VERTEX 5 DF4 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.46398204740594 20 -66.47313627063421 30 0.0 0 VERTEX 5 DF5 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.47984025256148 20 -66.43654861642364 30 0.0 0 VERTEX 5 DF6 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49217800076804 20 -66.39817045457902 30 0.0 0 VERTEX 5 DF7 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50071806949827 20 -66.35871805544099 30 0.0 0 VERTEX 5 DF8 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50530166138216 20 -66.31906783246066 30 0.0 0 VERTEX 5 DF9 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50596107418988 20 -66.27945798169304 30 0.0 0 VERTEX 5 DFA 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50272860569161 20 -66.24012669919317 30 0.0 0 VERTEX 5 DFB 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49563655365752 20 -66.20131218101609 30 0.0 0 VERTEX 5 DFC 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.48471721585779 20 -66.16325262321685 30 0.0 0 VERTEX 5 DFD 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.47000289006258 20 -66.12618622185045 30 0.0 0 VERTEX 5 DFE 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45152587404209 20 -66.09035117297194 30 0.0 0 VERTEX 5 DFF 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42970805741919 20 -66.05642236540392 30 0.0 0 VERTEX 5 E00 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.40494710648917 20 -66.02514197499019 30 0.0 0 VERTEX 5 E01 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.3774327706518 20 -65.99665534169654 30 0.0 0 VERTEX 5 E02 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.34735479930685 20 -65.97110780548873 30 0.0 0 VERTEX 5 E03 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.31490294185409 20 -65.94864470633256 30 0.0 0 VERTEX 5 E04 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.2802669476933 20 -65.92941138419381 30 0.0 0 VERTEX 5 E05 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.24363656622425 20 -65.91355317903827 30 0.0 0 VERTEX 5 E06 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.20520154684672 20 -65.90121543083173 30 0.0 0 VERTEX 5 E07 330 DC5 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.20520154684672 20 -65.90121543083173 30 0.0 0 SEQEND 5 E09 330 DC5 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 E08 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 19.20520154684672 20 -65.90121543083173 11 19.16579860366928 21 -65.89276720888543 72 1 10 19.16579860366928 20 -65.89276720888543 11 19.12617159471126 21 -65.88821288685575 72 1 10 19.12617159471126 20 -65.88821288685575 11 19.0865647718596 21 -65.88753833446826 72 1 10 19.0865647718596 20 -65.88753833446826 11 19.04722238700123 21 -65.8907294214485 72 1 10 19.04722238700123 20 -65.8907294214485 11 19.00838869202312 21 -65.897772017522 72 1 10 19.00838869202312 20 -65.897772017522 11 18.97030793881218 21 -65.90865199241433 72 1 10 18.97030793881218 20 -65.90865199241433 11 18.93322437925538 21 -65.92335521585105 72 1 10 18.93322437925538 20 -65.92335521585105 11 18.89738226523965 21 -65.94186755755767 72 1 10 18.89738226523965 20 -65.94186755755767 11 18.86345345767164 21 -65.96368537418057 72 1 10 18.86345345767164 20 -65.96368537418057 11 18.83217306725791 21 -65.98844632511059 72 1 10 18.83217306725791 20 -65.98844632511059 11 18.80368643396424 21 -66.01596066094797 72 1 10 18.80368643396424 20 -66.01596066094797 11 18.77813889775644 21 -66.04603863229292 72 1 10 18.77813889775644 20 -66.04603863229292 11 18.75567579860027 21 -66.07849048974568 72 1 10 18.75567579860027 20 -66.07849048974568 11 18.73644247646153 21 -66.11312648390646 72 1 10 18.73644247646153 20 -66.11312648390646 11 18.72058427130598 21 -66.14975686537551 72 1 10 18.72058427130598 20 -66.14975686537551 11 18.70824652309943 21 -66.18819188475304 72 1 10 18.70824652309943 20 -66.18819188475304 11 18.6997064543692 21 -66.22758776279325 72 1 10 18.6997064543692 20 -66.22758776279325 11 18.69512286248531 21 -66.26719761356087 72 1 10 18.69512286248531 20 -66.26719761356087 11 18.69446344967758 21 -66.30678324100086 72 1 10 18.69446344967758 20 -66.30678324100086 11 18.69769591817586 21 -66.34610644905817 72 1 10 18.69769591817586 20 -66.34610644905817 11 18.70478797020995 21 -66.3849290416778 72 1 10 18.70478797020995 20 -66.3849290416778 11 18.71570730800968 21 -66.42301282280468 72 1 10 18.71570730800968 20 -66.42301282280468 11 18.73042163380488 21 -66.46011959638379 72 1 10 18.73042163380488 20 -66.46011959638379 11 18.74889864982538 21 -66.4960111663601 72 1 10 18.74889864982538 20 -66.4960111663601 11 18.77978238324916 21 -66.54201227483605 72 1 10 18.77978238324916 20 -66.54201227483605 11 18.81577925741364 21 -66.58248037155903 72 1 10 18.81577925741364 20 -66.58248037155903 11 18.85620496331326 21 -66.6172277257399 72 1 10 18.85620496331326 20 -66.6172277257399 11 18.90037519194246 21 -66.64606660658953 72 1 10 18.90037519194246 20 -66.64606660658953 11 18.94760563429566 21 -66.66880928331877 72 1 10 18.94760563429566 20 -66.66880928331877 11 18.99721198136731 21 -66.68526802513848 72 1 10 18.99721198136731 20 -66.68526802513848 11 19.04850992415183 21 -66.69525510125953 72 1 10 19.04850992415183 20 -66.69525510125953 11 19.10081515364365 21 -66.69858278089279 72 1 10 19.10081515364365 20 -66.69858278089279 11 19.12662342705859 21 -66.69776322497462 72 1 10 19.12662342705859 20 -66.69776322497462 11 19.15244583074799 21 -66.69528840833503 72 1 10 19.15244583074799 20 -66.69528840833503 11 19.17819960167576 21 -66.69113410764636 72 1 10 19.17819960167576 20 -66.69113410764636 11 19.20380197680584 21 -66.68527609958102 72 1 10 19.20380197680584 20 -66.68527609958102 11 19.22917019310216 21 -66.67769016081135 72 1 10 19.22917019310216 20 -66.67769016081135 11 19.25422148752864 21 -66.66835206800972 72 1 10 19.25422148752864 20 -66.66835206800972 11 19.27887309704922 21 -66.65723759784854 72 1 10 19.27887309704922 20 -66.65723759784854 11 19.30304225862782 21 -66.64432252700011 72 1 10 19.30304225862782 20 -66.64432252700011 11 19.33697106619583 21 -66.62250504681232 72 1 10 19.33697106619583 20 -66.62250504681232 11 19.36825145660956 21 -66.59774645092804 72 1 10 19.36825145660956 20 -66.59774645092804 11 19.39673808990322 21 -66.57023850735769 72 1 10 19.39673808990322 20 -66.57023850735769 11 19.42228562611103 21 -66.54017298411165 72 1 10 19.42228562611103 20 -66.54017298411165 11 19.4447487252672 21 -66.50774164920037 72 1 10 19.4447487252672 20 -66.50774164920037 11 19.46398204740594 21 -66.47313627063421 72 1 10 19.46398204740594 20 -66.47313627063421 11 19.47984025256148 21 -66.43654861642364 72 1 10 19.47984025256148 20 -66.43654861642364 11 19.49217800076804 21 -66.39817045457902 72 1 10 19.49217800076804 20 -66.39817045457902 11 19.50071806949827 21 -66.35871805544099 72 1 10 19.50071806949827 20 -66.35871805544099 11 19.50530166138216 21 -66.31906783246066 72 1 10 19.50530166138216 20 -66.31906783246066 11 19.50596107418988 21 -66.27945798169304 72 1 10 19.50596107418988 20 -66.27945798169304 11 19.50272860569161 21 -66.24012669919317 72 1 10 19.50272860569161 20 -66.24012669919317 11 19.49563655365752 21 -66.20131218101609 72 1 10 19.49563655365752 20 -66.20131218101609 11 19.48471721585779 21 -66.16325262321685 72 1 10 19.48471721585779 20 -66.16325262321685 11 19.47000289006258 21 -66.12618622185045 72 1 10 19.47000289006258 20 -66.12618622185045 11 19.45152587404209 21 -66.09035117297194 72 1 10 19.45152587404209 20 -66.09035117297194 11 19.42970805741919 21 -66.05642236540392 72 1 10 19.42970805741919 20 -66.05642236540392 11 19.40494710648917 21 -66.02514197499019 72 1 10 19.40494710648917 20 -66.02514197499019 11 19.3774327706518 21 -65.99665534169654 72 1 10 19.3774327706518 20 -65.99665534169654 11 19.34735479930685 21 -65.97110780548873 72 1 10 19.34735479930685 20 -65.97110780548873 11 19.31490294185409 21 -65.94864470633256 72 1 10 19.31490294185409 20 -65.94864470633256 11 19.2802669476933 21 -65.92941138419381 72 1 10 19.2802669476933 20 -65.92941138419381 11 19.24363656622425 21 -65.91355317903827 72 1 10 19.24363656622425 20 -65.91355317903827 11 19.20520154684672 21 -65.90121543083173 97 0 75 2 76 1 98 0 0 POLYLINE 5 E0A 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 E0B 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49217800076804 20 -62.12418499557806 30 0.0 0 VERTEX 5 E0C 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.47984025256148 20 -62.08574997620053 30 0.0 0 VERTEX 5 E0D 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.46398204740594 20 -62.04911959473149 30 0.0 0 VERTEX 5 E0E 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.4447487252672 20 -62.0144836005707 30 0.0 0 VERTEX 5 E0F 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42228562611103 20 -61.98203174311794 30 0.0 0 VERTEX 5 E10 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.39673808990322 20 -61.95195377177267 30 0.0 0 VERTEX 5 E11 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.36825145660956 20 -61.92443943593562 30 0.0 0 VERTEX 5 E12 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.33697106619583 20 -61.89967848500559 30 0.0 0 VERTEX 5 E13 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.30304225862782 20 -61.8778606683827 30 0.0 0 VERTEX 5 E14 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.2670659070048 20 -61.85929180557827 30 0.0 0 VERTEX 5 E15 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.22985012845135 20 -61.84454820992885 30 0.0 0 VERTEX 5 E16 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.19165734235012 20 -61.83364401170888 30 0.0 0 VERTEX 5 E17 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.15274996808379 20 -61.82659334119283 30 0.0 0 VERTEX 5 E18 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.11339042503502 20 -61.82341032865514 30 0.0 0 VERTEX 5 E19 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.07384113258648 20 -61.82410910437026 30 0.0 0 VERTEX 5 E1A 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.03436451012084 20 -61.82870379861265 30 0.0 0 VERTEX 5 E1B 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.99522297702075 20 -61.83720854165675 30 0.0 0 VERTEX 5 E1C 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.95678795764321 20 -61.84954628986331 30 0.0 0 VERTEX 5 E1D 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.92015757617417 20 -61.86540449501884 30 0.0 0 VERTEX 5 E1E 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.88552158201338 20 -61.88463781715759 30 0.0 0 VERTEX 5 E1F 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.85306972456062 20 -61.90710091631376 30 0.0 0 VERTEX 5 E20 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.82299175321567 20 -61.93264845252156 30 0.0 0 VERTEX 5 E21 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.7954774173783 20 -61.96113508581522 30 0.0 0 VERTEX 5 E22 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.77071646644828 20 -61.99241547622896 30 0.0 0 VERTEX 5 E23 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.74889864982538 20 -62.02634428379697 30 0.0 0 VERTEX 5 E24 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.73042163380488 20 -62.06217933267548 30 0.0 0 VERTEX 5 E25 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.71570730800968 20 -62.09924573404187 30 0.0 0 VERTEX 5 E26 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.70478797020995 20 -62.13730529184113 30 0.0 0 VERTEX 5 E27 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.69769591817586 20 -62.17611981001821 30 0.0 0 VERTEX 5 E28 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.69446344967758 20 -62.21545109251807 30 0.0 0 VERTEX 5 E29 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.69512286248531 20 -62.25506094328569 30 0.0 0 VERTEX 5 E2A 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.6997064543692 20 -62.29471116626603 30 0.0 0 VERTEX 5 E2B 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.70824652309943 20 -62.33416356540404 30 0.0 0 VERTEX 5 E2C 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.72058427130598 20 -62.37254172724866 30 0.0 0 VERTEX 5 E2D 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.73644247646153 20 -62.40912938145924 30 0.0 0 VERTEX 5 E2E 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.75567579860027 20 -62.44373476002539 30 0.0 0 VERTEX 5 E2F 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.77813889775644 20 -62.47616609493701 30 0.0 0 VERTEX 5 E30 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.80368643396424 20 -62.50623161818272 30 0.0 0 VERTEX 5 E31 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.83217306725791 20 -62.53373956175275 30 0.0 0 VERTEX 5 E32 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.86345345767164 20 -62.55849815763735 30 0.0 0 VERTEX 5 E33 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.89738226523965 20 -62.58031563782514 30 0.0 0 VERTEX 5 E34 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.92113458372194 20 -62.5930476879759 30 0.0 0 VERTEX 5 E35 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.94545211318228 20 -62.60410832852015 30 0.0 0 VERTEX 5 E36 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.97027025808032 20 -62.61348948501534 30 0.0 0 VERTEX 5 E37 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.9955244228757 20 -62.62118308301892 30 0.0 0 VERTEX 5 E38 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.0211500120281 20 -62.62718104808835 30 0.0 0 VERTEX 5 E39 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.04708242999715 20 -62.6314753057811 30 0.0 0 VERTEX 5 E3A 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.0732570812425 20 -62.63405778165429 30 0.0 0 VERTEX 5 E3B 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.09960937022381 20 -62.63492040126635 30 0.0 0 VERTEX 5 E3C 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.11280132716445 20 -62.63470239131767 30 0.0 0 VERTEX 5 E3D 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.12601548882208 20 -62.63404836147165 30 0.0 0 VERTEX 5 E3E 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.13924176214353 20 -62.63295831172795 30 0.0 0 VERTEX 5 E3F 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.15247005407562 20 -62.63143224208753 30 0.0 0 VERTEX 5 E40 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.16569027156516 20 -62.62947015254945 30 0.0 0 VERTEX 5 E41 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.17889232155898 20 -62.62707204311402 30 0.0 0 VERTEX 5 E42 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.19206611100389 20 -62.62423791378123 30 0.0 0 VERTEX 5 E43 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.20520154684672 20 -62.62096776455109 30 0.0 0 VERTEX 5 E44 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.24363656622425 20 -62.60863741791687 30 0.0 0 VERTEX 5 E45 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.2802669476933 20 -62.59279872599748 30 0.0 0 VERTEX 5 E46 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.31490294185409 20 -62.57359299153742 30 0.0 0 VERTEX 5 E47 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.34735479930685 20 -62.55116151728122 30 0.0 0 VERTEX 5 E48 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.3774327706518 20 -62.52564560597337 30 0.0 0 VERTEX 5 E49 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.40494710648917 20 -62.4971865603584 30 0.0 0 VERTEX 5 E4A 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.42970805741919 20 -62.46592568318082 30 0.0 0 VERTEX 5 E4B 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.45152587404209 20 -62.43200427718514 30 0.0 0 VERTEX 5 E4C 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.47000289006258 20 -62.3961127072085 30 0.0 0 VERTEX 5 E4D 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.48471721585779 20 -62.35900593362971 30 0.0 0 VERTEX 5 E4E 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49563655365752 20 -62.32092215250282 30 0.0 0 VERTEX 5 E4F 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50272860569161 20 -62.28209955988321 30 0.0 0 VERTEX 5 E50 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50596107418988 20 -62.24277635182588 30 0.0 0 VERTEX 5 E51 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50530166138216 20 -62.2031907243859 30 0.0 0 VERTEX 5 E52 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.50071806949827 20 -62.16358087361828 30 0.0 0 VERTEX 5 E53 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49217800076804 20 -62.12418499557806 30 0.0 0 VERTEX 5 E54 330 E0A 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 19.49217800076804 20 -62.12418499557806 30 0.0 0 SEQEND 5 E56 330 E0A 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 E55 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 72 72 1 10 19.49217800076804 20 -62.12418499557806 11 19.47984025256148 21 -62.08574997620053 72 1 10 19.47984025256148 20 -62.08574997620053 11 19.46398204740594 21 -62.04911959473149 72 1 10 19.46398204740594 20 -62.04911959473149 11 19.4447487252672 21 -62.0144836005707 72 1 10 19.4447487252672 20 -62.0144836005707 11 19.42228562611103 21 -61.98203174311794 72 1 10 19.42228562611103 20 -61.98203174311794 11 19.39673808990322 21 -61.95195377177267 72 1 10 19.39673808990322 20 -61.95195377177267 11 19.36825145660956 21 -61.92443943593562 72 1 10 19.36825145660956 20 -61.92443943593562 11 19.33697106619583 21 -61.89967848500559 72 1 10 19.33697106619583 20 -61.89967848500559 11 19.30304225862782 21 -61.8778606683827 72 1 10 19.30304225862782 20 -61.8778606683827 11 19.2670659070048 21 -61.85929180557827 72 1 10 19.2670659070048 20 -61.85929180557827 11 19.22985012845135 21 -61.84454820992885 72 1 10 19.22985012845135 20 -61.84454820992885 11 19.19165734235012 21 -61.83364401170888 72 1 10 19.19165734235012 20 -61.83364401170888 11 19.15274996808379 21 -61.82659334119283 72 1 10 19.15274996808379 20 -61.82659334119283 11 19.11339042503502 21 -61.82341032865514 72 1 10 19.11339042503502 20 -61.82341032865514 11 19.07384113258648 21 -61.82410910437026 72 1 10 19.07384113258648 20 -61.82410910437026 11 19.03436451012084 21 -61.82870379861265 72 1 10 19.03436451012084 20 -61.82870379861265 11 18.99522297702075 21 -61.83720854165675 72 1 10 18.99522297702075 20 -61.83720854165675 11 18.95678795764321 21 -61.84954628986331 72 1 10 18.95678795764321 20 -61.84954628986331 11 18.92015757617417 21 -61.86540449501884 72 1 10 18.92015757617417 20 -61.86540449501884 11 18.88552158201338 21 -61.88463781715759 72 1 10 18.88552158201338 20 -61.88463781715759 11 18.85306972456062 21 -61.90710091631376 72 1 10 18.85306972456062 20 -61.90710091631376 11 18.82299175321567 21 -61.93264845252156 72 1 10 18.82299175321567 20 -61.93264845252156 11 18.7954774173783 21 -61.96113508581522 72 1 10 18.7954774173783 20 -61.96113508581522 11 18.77071646644828 21 -61.99241547622896 72 1 10 18.77071646644828 20 -61.99241547622896 11 18.74889864982538 21 -62.02634428379697 72 1 10 18.74889864982538 20 -62.02634428379697 11 18.73042163380488 21 -62.06217933267548 72 1 10 18.73042163380488 20 -62.06217933267548 11 18.71570730800968 21 -62.09924573404187 72 1 10 18.71570730800968 20 -62.09924573404187 11 18.70478797020995 21 -62.13730529184113 72 1 10 18.70478797020995 20 -62.13730529184113 11 18.69769591817586 21 -62.17611981001821 72 1 10 18.69769591817586 20 -62.17611981001821 11 18.69446344967758 21 -62.21545109251807 72 1 10 18.69446344967758 20 -62.21545109251807 11 18.69512286248531 21 -62.25506094328569 72 1 10 18.69512286248531 20 -62.25506094328569 11 18.6997064543692 21 -62.29471116626603 72 1 10 18.6997064543692 20 -62.29471116626603 11 18.70824652309943 21 -62.33416356540404 72 1 10 18.70824652309943 20 -62.33416356540404 11 18.72058427130598 21 -62.37254172724866 72 1 10 18.72058427130598 20 -62.37254172724866 11 18.73644247646153 21 -62.40912938145924 72 1 10 18.73644247646153 20 -62.40912938145924 11 18.75567579860027 21 -62.44373476002539 72 1 10 18.75567579860027 20 -62.44373476002539 11 18.77813889775644 21 -62.47616609493701 72 1 10 18.77813889775644 20 -62.47616609493701 11 18.80368643396424 21 -62.50623161818272 72 1 10 18.80368643396424 20 -62.50623161818272 11 18.83217306725791 21 -62.53373956175275 72 1 10 18.83217306725791 20 -62.53373956175275 11 18.86345345767164 21 -62.55849815763735 72 1 10 18.86345345767164 20 -62.55849815763735 11 18.89738226523965 21 -62.58031563782514 72 1 10 18.89738226523965 20 -62.58031563782514 11 18.92113458372194 21 -62.5930476879759 72 1 10 18.92113458372194 20 -62.5930476879759 11 18.94545211318228 21 -62.60410832852015 72 1 10 18.94545211318228 20 -62.60410832852015 11 18.97027025808032 21 -62.61348948501534 72 1 10 18.97027025808032 20 -62.61348948501534 11 18.9955244228757 21 -62.62118308301892 72 1 10 18.9955244228757 20 -62.62118308301892 11 19.0211500120281 21 -62.62718104808835 72 1 10 19.0211500120281 20 -62.62718104808835 11 19.04708242999715 21 -62.6314753057811 72 1 10 19.04708242999715 20 -62.6314753057811 11 19.0732570812425 21 -62.63405778165429 72 1 10 19.0732570812425 20 -62.63405778165429 11 19.09960937022381 21 -62.63492040126635 72 1 10 19.09960937022381 20 -62.63492040126635 11 19.11280132716445 21 -62.63470239131767 72 1 10 19.11280132716445 20 -62.63470239131767 11 19.12601548882208 21 -62.63404836147165 72 1 10 19.12601548882208 20 -62.63404836147165 11 19.13924176214353 21 -62.63295831172795 72 1 10 19.13924176214353 20 -62.63295831172795 11 19.15247005407562 21 -62.63143224208753 72 1 10 19.15247005407562 20 -62.63143224208753 11 19.16569027156516 21 -62.62947015254945 72 1 10 19.16569027156516 20 -62.62947015254945 11 19.17889232155898 21 -62.62707204311402 72 1 10 19.17889232155898 20 -62.62707204311402 11 19.19206611100389 21 -62.62423791378123 72 1 10 19.19206611100389 20 -62.62423791378123 11 19.20520154684672 21 -62.62096776455109 72 1 10 19.20520154684672 20 -62.62096776455109 11 19.24363656622425 21 -62.60863741791687 72 1 10 19.24363656622425 20 -62.60863741791687 11 19.2802669476933 21 -62.59279872599748 72 1 10 19.2802669476933 20 -62.59279872599748 11 19.31490294185409 21 -62.57359299153742 72 1 10 19.31490294185409 20 -62.57359299153742 11 19.34735479930685 21 -62.55116151728122 72 1 10 19.34735479930685 20 -62.55116151728122 11 19.3774327706518 21 -62.52564560597337 72 1 10 19.3774327706518 20 -62.52564560597337 11 19.40494710648917 21 -62.4971865603584 72 1 10 19.40494710648917 20 -62.4971865603584 11 19.42970805741919 21 -62.46592568318082 72 1 10 19.42970805741919 20 -62.46592568318082 11 19.45152587404209 21 -62.43200427718514 72 1 10 19.45152587404209 20 -62.43200427718514 11 19.47000289006258 21 -62.3961127072085 72 1 10 19.47000289006258 20 -62.3961127072085 11 19.48471721585779 21 -62.35900593362971 72 1 10 19.48471721585779 20 -62.35900593362971 11 19.49563655365752 21 -62.32092215250282 72 1 10 19.49563655365752 20 -62.32092215250282 11 19.50272860569161 21 -62.28209955988321 72 1 10 19.50272860569161 20 -62.28209955988321 11 19.50596107418988 21 -62.24277635182588 72 1 10 19.50596107418988 20 -62.24277635182588 11 19.50530166138216 21 -62.2031907243859 72 1 10 19.50530166138216 20 -62.2031907243859 11 19.50071806949827 21 -62.16358087361828 72 1 10 19.50071806949827 20 -62.16358087361828 11 19.49217800076804 21 -62.12418499557806 97 0 75 2 76 1 98 0 0 POLYLINE 5 E57 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 E58 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.10216471076484 20 -65.94186755755767 30 0.0 0 VERTEX 5 E59 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.06619542427905 20 -65.92334815071382 30 0.0 0 VERTEX 5 E5A 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.028996803916 20 -65.9086277690867 30 0.0 0 VERTEX 5 E5B 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.99082521322645 20 -65.8977265987827 30 0.0 0 VERTEX 5 E5C 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.95193701576117 20 -65.89066482590815 30 0.0 0 VERTEX 5 E5D 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.9125885750709 20 -65.88746263656941 30 0.0 0 VERTEX 5 E5E 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.8730362547064 20 -65.88814021687286 30 0.0 0 VERTEX 5 E5F 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.83353641821844 20 -65.89271775292484 30 0.0 0 VERTEX 5 E60 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.79434542915777 20 -65.90121543083173 30 0.0 0 VERTEX 5 E61 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.75591040978024 20 -65.91355317903827 30 0.0 0 VERTEX 5 E62 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.71928002831119 20 -65.92941138419381 30 0.0 0 VERTEX 5 E63 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.68464403415041 20 -65.94864470633256 30 0.0 0 VERTEX 5 E64 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.65219217669765 20 -65.97110780548873 30 0.0 0 VERTEX 5 E65 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.6221142053527 20 -65.99665534169654 30 0.0 0 VERTEX 5 E66 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.59459986951532 20 -66.02514197499019 30 0.0 0 VERTEX 5 E67 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.5698389185853 20 -66.05642236540392 30 0.0 0 VERTEX 5 E68 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.54802110196241 20 -66.09035117297194 30 0.0 0 VERTEX 5 E69 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.52954408594191 20 -66.12618588541534 30 0.0 0 VERTEX 5 E6A 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.5148297601467 20 -66.16324993173599 30 0.0 0 VERTEX 5 E6B 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.50391042234697 20 -66.20130309726824 30 0.0 0 VERTEX 5 E6C 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.49681837031288 20 -66.2401051673464 30 0.0 0 VERTEX 5 E6D 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.49358590181461 20 -66.2794159273048 30 0.0 0 VERTEX 5 E6E 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.49424531462233 20 -66.31899516247776 30 0.0 0 VERTEX 5 E6F 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.49882890650623 20 -66.35860265819964 30 0.0 0 VERTEX 5 E70 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.50736897523646 20 -66.39799819980475 30 0.0 0 VERTEX 5 E71 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.51969932187068 20 -66.43643321918228 30 0.0 0 VERTEX 5 E72 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.53553801379007 20 -66.47306360065133 30 0.0 0 VERTEX 5 E73 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.55474374825013 20 -66.50769959481211 30 0.0 0 VERTEX 5 E74 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.57717522250633 20 -66.54015145226487 30 0.0 0 VERTEX 5 E75 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.60269113381418 20 -66.57022942360982 30 0.0 0 VERTEX 5 E76 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.63115017942915 20 -66.5977437594472 30 0.0 0 VERTEX 5 E77 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.66241105660673 20 -66.62250471037721 30 0.0 0 VERTEX 5 E78 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.69633246260241 20 -66.64432252700011 30 0.0 0 VERTEX 5 E79 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.72049455904379 20 -66.65723759784854 30 0.0 0 VERTEX 5 E7A 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.74512901037396 20 -66.66835206800972 30 0.0 0 VERTEX 5 E7B 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.77015910938876 20 -66.67769016081135 30 0.0 0 VERTEX 5 E7C 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.79550814888404 20 -66.68527609958102 30 0.0 0 VERTEX 5 E7D 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.82109942165562 20 -66.69113410764636 30 0.0 0 VERTEX 5 E7E 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.84685622049935 20 -66.69528840833503 30 0.0 0 VERTEX 5 E7F 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.87270183821106 20 -66.69776322497462 30 0.0 0 VERTEX 5 E80 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.89855956758658 20 -66.69858278089279 30 0.0 0 VERTEX 5 E81 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 10.9508647970784 20 -66.69520564529896 30 0.0 0 VERTEX 5 E82 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.00216273986292 20 -66.68519535515559 30 0.0 0 VERTEX 5 E83 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.05176908693457 20 -66.66873358541991 30 0.0 0 VERTEX 5 E84 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.09899952928777 20 -66.64600201104918 30 0.0 0 VERTEX 5 E85 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.14316975791697 20 -66.61718230700059 30 0.0 0 VERTEX 5 E86 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.18359546381659 20 -66.5824561482314 30 0.0 0 VERTEX 5 E87 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.21959233798107 20 -66.54200520969883 30 0.0 0 VERTEX 5 E88 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.25047607140485 20 -66.4960111663601 30 0.0 0 VERTEX 5 E89 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.28414145028488 20 -66.42114762657712 30 0.0 0 VERTEX 5 E8A 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.30169226045861 20 -66.34339343636354 30 0.0 0 VERTEX 5 E8B 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.30372802928491 20 -66.26499329074647 30 0.0 0 VERTEX 5 E8C 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.29084828412262 20 -66.18819188475304 30 0.0 0 VERTEX 5 E8D 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.26365255233061 20 -66.11523391341032 30 0.0 0 VERTEX 5 E8E 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.22274036126774 20 -66.04836407174545 30 0.0 0 VERTEX 5 E8F 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.16871123829286 20 -65.98982705478554 30 0.0 0 VERTEX 5 E90 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.10216471076484 20 -65.94186755755767 30 0.0 0 VERTEX 5 E91 330 E57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.10216471076484 20 -65.94186755755767 30 0.0 0 SEQEND 5 E93 330 E57 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 E92 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 56 72 1 10 11.10216471076484 20 -65.94186755755767 11 11.06619542427905 21 -65.92334815071382 72 1 10 11.06619542427905 20 -65.92334815071382 11 11.028996803916 21 -65.9086277690867 72 1 10 11.028996803916 20 -65.9086277690867 11 10.99082521322645 21 -65.8977265987827 72 1 10 10.99082521322645 20 -65.8977265987827 11 10.95193701576117 21 -65.89066482590815 72 1 10 10.95193701576117 20 -65.89066482590815 11 10.9125885750709 21 -65.88746263656941 72 1 10 10.9125885750709 20 -65.88746263656941 11 10.8730362547064 21 -65.88814021687286 72 1 10 10.8730362547064 20 -65.88814021687286 11 10.83353641821844 21 -65.89271775292484 72 1 10 10.83353641821844 20 -65.89271775292484 11 10.79434542915777 21 -65.90121543083173 72 1 10 10.79434542915777 20 -65.90121543083173 11 10.75591040978024 21 -65.91355317903827 72 1 10 10.75591040978024 20 -65.91355317903827 11 10.71928002831119 21 -65.92941138419381 72 1 10 10.71928002831119 20 -65.92941138419381 11 10.68464403415041 21 -65.94864470633256 72 1 10 10.68464403415041 20 -65.94864470633256 11 10.65219217669765 21 -65.97110780548873 72 1 10 10.65219217669765 20 -65.97110780548873 11 10.6221142053527 21 -65.99665534169654 72 1 10 10.6221142053527 20 -65.99665534169654 11 10.59459986951532 21 -66.02514197499019 72 1 10 10.59459986951532 20 -66.02514197499019 11 10.5698389185853 21 -66.05642236540392 72 1 10 10.5698389185853 20 -66.05642236540392 11 10.54802110196241 21 -66.09035117297194 72 1 10 10.54802110196241 20 -66.09035117297194 11 10.52954408594191 21 -66.12618588541534 72 1 10 10.52954408594191 20 -66.12618588541534 11 10.5148297601467 21 -66.16324993173599 72 1 10 10.5148297601467 20 -66.16324993173599 11 10.50391042234697 21 -66.20130309726824 72 1 10 10.50391042234697 20 -66.20130309726824 11 10.49681837031288 21 -66.2401051673464 72 1 10 10.49681837031288 20 -66.2401051673464 11 10.49358590181461 21 -66.2794159273048 72 1 10 10.49358590181461 20 -66.2794159273048 11 10.49424531462233 21 -66.31899516247776 72 1 10 10.49424531462233 20 -66.31899516247776 11 10.49882890650623 21 -66.35860265819964 72 1 10 10.49882890650623 20 -66.35860265819964 11 10.50736897523646 21 -66.39799819980475 72 1 10 10.50736897523646 20 -66.39799819980475 11 10.51969932187068 21 -66.43643321918228 72 1 10 10.51969932187068 20 -66.43643321918228 11 10.53553801379007 21 -66.47306360065133 72 1 10 10.53553801379007 20 -66.47306360065133 11 10.55474374825013 21 -66.50769959481211 72 1 10 10.55474374825013 20 -66.50769959481211 11 10.57717522250633 21 -66.54015145226487 72 1 10 10.57717522250633 20 -66.54015145226487 11 10.60269113381418 21 -66.57022942360982 72 1 10 10.60269113381418 20 -66.57022942360982 11 10.63115017942915 21 -66.5977437594472 72 1 10 10.63115017942915 20 -66.5977437594472 11 10.66241105660673 21 -66.62250471037721 72 1 10 10.66241105660673 20 -66.62250471037721 11 10.69633246260241 21 -66.64432252700011 72 1 10 10.69633246260241 20 -66.64432252700011 11 10.72049455904379 21 -66.65723759784854 72 1 10 10.72049455904379 20 -66.65723759784854 11 10.74512901037396 21 -66.66835206800972 72 1 10 10.74512901037396 20 -66.66835206800972 11 10.77015910938876 21 -66.67769016081135 72 1 10 10.77015910938876 20 -66.67769016081135 11 10.79550814888404 21 -66.68527609958102 72 1 10 10.79550814888404 20 -66.68527609958102 11 10.82109942165562 21 -66.69113410764636 72 1 10 10.82109942165562 20 -66.69113410764636 11 10.84685622049935 21 -66.69528840833503 72 1 10 10.84685622049935 20 -66.69528840833503 11 10.87270183821106 21 -66.69776322497462 72 1 10 10.87270183821106 20 -66.69776322497462 11 10.89855956758658 21 -66.69858278089279 72 1 10 10.89855956758658 20 -66.69858278089279 11 10.9508647970784 21 -66.69520564529896 72 1 10 10.9508647970784 20 -66.69520564529896 11 11.00216273986292 21 -66.68519535515559 72 1 10 11.00216273986292 20 -66.68519535515559 11 11.05176908693457 21 -66.66873358541991 72 1 10 11.05176908693457 20 -66.66873358541991 11 11.09899952928777 21 -66.64600201104918 72 1 10 11.09899952928777 20 -66.64600201104918 11 11.14316975791697 21 -66.61718230700059 72 1 10 11.14316975791697 20 -66.61718230700059 11 11.18359546381659 21 -66.5824561482314 72 1 10 11.18359546381659 20 -66.5824561482314 11 11.21959233798107 21 -66.54200520969883 72 1 10 11.21959233798107 20 -66.54200520969883 11 11.25047607140485 21 -66.4960111663601 72 1 10 11.25047607140485 20 -66.4960111663601 11 11.28414145028488 21 -66.42114762657712 72 1 10 11.28414145028488 20 -66.42114762657712 11 11.30169226045861 21 -66.34339343636354 72 1 10 11.30169226045861 20 -66.34339343636354 11 11.30372802928491 21 -66.26499329074647 72 1 10 11.30372802928491 20 -66.26499329074647 11 11.29084828412262 21 -66.18819188475304 72 1 10 11.29084828412262 20 -66.18819188475304 11 11.26365255233061 21 -66.11523391341032 72 1 10 11.26365255233061 20 -66.11523391341032 11 11.22274036126774 21 -66.04836407174545 72 1 10 11.22274036126774 20 -66.04836407174545 11 11.16871123829286 21 -65.98982705478554 72 1 10 11.16871123829286 20 -65.98982705478554 11 11.10216471076484 21 -65.94186755755767 97 0 75 2 76 1 98 0 0 POLYLINE 5 E94 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 E95 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.44374592812736 20 -63.85534547691611 30 0.0 0 VERTEX 5 E96 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.36207193249399 20 -63.86360596807295 30 0.0 0 VERTEX 5 E97 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.28596324638377 20 -63.88729066309926 30 0.0 0 VERTEX 5 E98 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.21706100024367 20 -63.92475439432582 30 0.0 0 VERTEX 5 E99 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.15700632452066 20 -63.97435199408503 30 0.0 0 VERTEX 5 E9A 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.10744034966174 20 -64.03443829470767 30 0.0 0 VERTEX 5 E9B 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.07000420611387 20 -64.10336812852647 30 0.0 0 VERTEX 5 E9C 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.04633902432403 20 -64.17949632787284 30 0.0 0 VERTEX 5 E9D 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.0380859347392 20 -64.26117772507854 30 0.0 0 VERTEX 5 E9E 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.04633902432403 20 -64.3428517207116 30 0.0 0 VERTEX 5 E9F 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.07000420611387 20 -64.41896040682214 30 0.0 0 VERTEX 5 EA0 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.10744034966174 20 -64.48786265296256 30 0.0 0 VERTEX 5 EA1 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.15700632452066 20 -64.54791732868524 30 0.0 0 VERTEX 5 EA2 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.21706100024367 20 -64.59748330354417 30 0.0 0 VERTEX 5 EA3 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.28596324638377 20 -64.63491944709203 30 0.0 0 VERTEX 5 EA4 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.36207193249399 20 -64.65858462888188 30 0.0 0 VERTEX 5 EA5 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.44374592812736 20 -64.66683771846671 30 0.0 0 VERTEX 5 EA6 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.52541992376073 20 -64.65858462888188 30 0.0 0 VERTEX 5 EA7 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.60152860987096 20 -64.63491944709203 30 0.0 0 VERTEX 5 EA8 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.67043085601106 20 -64.59748330354417 30 0.0 0 VERTEX 5 EA9 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.73048553173406 20 -64.54791732868524 30 0.0 0 VERTEX 5 EAA 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.78005150659299 20 -64.48786265296256 30 0.0 0 VERTEX 5 EAB 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.81748765014086 20 -64.41896040682214 30 0.0 0 VERTEX 5 EAC 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.8411528319307 20 -64.3428517207116 30 0.0 0 VERTEX 5 EAD 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.84940592151553 20 -64.26117772507854 30 0.0 0 VERTEX 5 EAE 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.8411528319307 20 -64.17949632787284 30 0.0 0 VERTEX 5 EAF 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.81748765014086 20 -64.10336812852647 30 0.0 0 VERTEX 5 EB0 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.78005150659299 20 -64.03443829470767 30 0.0 0 VERTEX 5 EB1 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.73048553173406 20 -63.97435199408503 30 0.0 0 VERTEX 5 EB2 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.67043085601106 20 -63.92475439432582 30 0.0 0 VERTEX 5 EB3 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.60152860987096 20 -63.88729066309926 30 0.0 0 VERTEX 5 EB4 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.52541992376073 20 -63.86360596807295 30 0.0 0 VERTEX 5 EB5 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.44374592812736 20 -63.85534547691611 30 0.0 0 VERTEX 5 EB6 330 E94 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 11.44374592812736 20 -63.85534547691611 30 0.0 0 SEQEND 5 EB8 330 E94 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 EB7 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 32 72 1 10 11.44374592812736 20 -63.85534547691611 11 11.36207193249399 21 -63.86360596807295 72 1 10 11.36207193249399 20 -63.86360596807295 11 11.28596324638377 21 -63.88729066309926 72 1 10 11.28596324638377 20 -63.88729066309926 11 11.21706100024367 21 -63.92475439432582 72 1 10 11.21706100024367 20 -63.92475439432582 11 11.15700632452066 21 -63.97435199408503 72 1 10 11.15700632452066 20 -63.97435199408503 11 11.10744034966174 21 -64.03443829470767 72 1 10 11.10744034966174 20 -64.03443829470767 11 11.07000420611387 21 -64.10336812852647 72 1 10 11.07000420611387 20 -64.10336812852647 11 11.04633902432403 21 -64.17949632787284 72 1 10 11.04633902432403 20 -64.17949632787284 11 11.0380859347392 21 -64.26117772507854 72 1 10 11.0380859347392 20 -64.26117772507854 11 11.04633902432403 21 -64.3428517207116 72 1 10 11.04633902432403 20 -64.3428517207116 11 11.07000420611387 21 -64.41896040682214 72 1 10 11.07000420611387 20 -64.41896040682214 11 11.10744034966174 21 -64.48786265296256 72 1 10 11.10744034966174 20 -64.48786265296256 11 11.15700632452066 21 -64.54791732868524 72 1 10 11.15700632452066 20 -64.54791732868524 11 11.21706100024367 21 -64.59748330354417 72 1 10 11.21706100024367 20 -64.59748330354417 11 11.28596324638377 21 -64.63491944709203 72 1 10 11.28596324638377 20 -64.63491944709203 11 11.36207193249399 21 -64.65858462888188 72 1 10 11.36207193249399 20 -64.65858462888188 11 11.44374592812736 21 -64.66683771846671 72 1 10 11.44374592812736 20 -64.66683771846671 11 11.52541992376073 21 -64.65858462888188 72 1 10 11.52541992376073 20 -64.65858462888188 11 11.60152860987096 21 -64.63491944709203 72 1 10 11.60152860987096 20 -64.63491944709203 11 11.67043085601106 21 -64.59748330354417 72 1 10 11.67043085601106 20 -64.59748330354417 11 11.73048553173406 21 -64.54791732868524 72 1 10 11.73048553173406 20 -64.54791732868524 11 11.78005150659299 21 -64.48786265296256 72 1 10 11.78005150659299 20 -64.48786265296256 11 11.81748765014086 21 -64.41896040682214 72 1 10 11.81748765014086 20 -64.41896040682214 11 11.8411528319307 21 -64.3428517207116 72 1 10 11.8411528319307 20 -64.3428517207116 11 11.84940592151553 21 -64.26117772507854 72 1 10 11.84940592151553 20 -64.26117772507854 11 11.8411528319307 21 -64.17949632787284 72 1 10 11.8411528319307 20 -64.17949632787284 11 11.81748765014086 21 -64.10336812852647 72 1 10 11.81748765014086 20 -64.10336812852647 11 11.78005150659299 21 -64.03443829470767 72 1 10 11.78005150659299 20 -64.03443829470767 11 11.73048553173406 21 -63.97435199408503 72 1 10 11.73048553173406 20 -63.97435199408503 11 11.67043085601106 21 -63.92475439432582 72 1 10 11.67043085601106 20 -63.92475439432582 11 11.60152860987096 21 -63.88729066309926 72 1 10 11.60152860987096 20 -63.88729066309926 11 11.52541992376073 21 -63.86360596807295 72 1 10 11.52541992376073 20 -63.86360596807295 11 11.44374592812736 21 -63.85534547691611 97 0 75 2 76 1 98 0 0 POLYLINE 5 EB9 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 EBA 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.58743845106931 20 -68.27458477431391 30 0.0 0 VERTEX 5 EBB 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.65276586393642 20 -68.27022095866299 30 0.0 0 VERTEX 5 EBC 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7162147072805 20 -68.25741783659609 30 0.0 0 VERTEX 5 EBD 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.777034814924 20 -68.23660789544194 30 0.0 0 VERTEX 5 EBE 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.83447602068935 20 -68.20822362252927 30 0.0 0 VERTEX 5 EBF 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.88778815839899 20 -68.17269750518683 30 0.0 0 VERTEX 5 EC0 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.93622106187536 20 -68.13046203074336 30 0.0 0 VERTEX 5 EC1 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.97902456494089 20 -68.0819496865276 30 0.0 0 VERTEX 5 EC2 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.01544850141803 20 -68.02759295986827 30 0.0 0 VERTEX 5 EC3 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.03790424105626 20 -67.98391468347279 30 0.0 0 VERTEX 5 EC4 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.05578202409862 20 -67.93875727013388 30 0.0 0 VERTEX 5 EC5 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.06904374926936 20 -67.89240786721446 30 0.0 0 VERTEX 5 EC6 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.07765131529273 20 -67.8451536220775 30 0.0 0 VERTEX 5 EC7 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.08156662089297 20 -67.79728168208598 30 0.0 0 VERTEX 5 EC8 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.08075156479435 20 -67.74907919460281 30 0.0 0 VERTEX 5 EC9 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.07516804572109 20 -67.70083330699099 30 0.0 0 VERTEX 5 ECA 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.06477796239745 20 -67.65283116661344 30 0.0 0 VERTEX 5 ECB 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.04977787703411 20 -67.60606504676088 30 0.0 0 VERTEX 5 ECC 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.03049152431178 20 -67.56148937177458 30 0.0 0 VERTEX 5 ECD 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 21.00709578498744 20 -67.51933451559339 30 0.0 0 VERTEX 5 ECE 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.97976753981807 20 -67.47983085215608 30 0.0 0 VERTEX 5 ECF 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.94868366956062 20 -67.44320875540153 30 0.0 0 VERTEX 5 ED0 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.91402105497207 20 -67.40969859926852 30 0.0 0 VERTEX 5 ED1 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.87595657680939 20 -67.37953075769589 30 0.0 0 VERTEX 5 ED2 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.83466711582955 20 -67.35293560462244 30 0.0 0 VERTEX 5 ED3 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.80607143550716 20 -67.33765152597526 30 0.0 0 VERTEX 5 ED4 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.77661961194883 20 -67.32431036006511 30 0.0 0 VERTEX 5 ED5 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.74642039780256 20 -67.31294137674624 30 0.0 0 VERTEX 5 ED6 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.71558254571636 20 -67.30357384587285 30 0.0 0 VERTEX 5 ED7 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.68421480833824 20 -67.29623703729915 30 0.0 0 VERTEX 5 ED8 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.65242593831621 20 -67.29096022087938 30 0.0 0 VERTEX 5 ED9 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.62032468829827 20 -67.28777266646777 30 0.0 0 VERTEX 5 EDA 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.58801981093244 20 -67.28670364391851 30 0.0 0 VERTEX 5 EDB 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.52269239806533 20 -67.29107456676104 30 0.0 0 VERTEX 5 EDC 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.45924355472125 20 -67.30388302973525 30 0.0 0 VERTEX 5 EDD 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.39842344707775 20 -67.32469679783873 30 0.0 0 VERTEX 5 EDE 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.3409822413124 20 -67.35308363606907 30 0.0 0 VERTEX 5 EDF 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.28767010360276 20 -67.38861130942388 30 0.0 0 VERTEX 5 EE0 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.23923720012639 20 -67.43084758290073 30 0.0 0 VERTEX 5 EE1 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.19643369706085 20 -67.47936022149722 30 0.0 0 VERTEX 5 EE2 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.16000976058372 20 -67.53371699021092 30 0.0 0 VERTEX 5 EE3 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.13754779689603 20 -67.57738908461133 30 0.0 0 VERTEX 5 EE4 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.11966681772016 20 -67.62254359619746 30 0.0 0 VERTEX 5 EE5 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10640391502655 20 -67.66889262062737 30 0.0 0 VERTEX 5 EE6 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.09779618078563 20 -67.71614825355914 30 0.0 0 VERTEX 5 EE7 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.09388070696783 20 -67.76402259065081 30 0.0 0 VERTEX 5 EE8 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.09469458554359 20 -67.81222772756043 30 0.0 0 VERTEX 5 EE9 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.10027490848334 20 -67.86047575994606 30 0.0 0 VERTEX 5 EEA 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.11065876775751 20 -67.90847878346575 30 0.0 0 VERTEX 5 EEB 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.12566591825808 20 -67.95524490331832 30 0.0 0 VERTEX 5 EEC 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.144957317507 20 -67.99982057830461 30 0.0 0 VERTEX 5 EED 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.16835608474729 20 -68.0419754344858 30 0.0 0 VERTEX 5 EEE 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.19568533922198 20 -68.08147909792311 30 0.0 0 VERTEX 5 EEF 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.22676820017412 20 -68.11810119467766 30 0.0 0 VERTEX 5 EF0 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.26142778684671 20 -68.15161135081068 30 0.0 0 VERTEX 5 EF1 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.2994872184828 20 -68.18177919238332 30 0.0 0 VERTEX 5 EF2 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.34076961432542 20 -68.20837434545676 30 0.0 0 VERTEX 5 EF3 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.36937151869726 20 -68.2236574989074 30 0.0 0 VERTEX 5 EF4 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.3988265383891 20 -68.23699622566302 30 0.0 0 VERTEX 5 EF5 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.42902693005824 20 -68.24836176052206 30 0.0 0 VERTEX 5 EF6 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.459864950362 20 -68.25772533828297 30 0.0 0 VERTEX 5 EF7 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.49123285595767 20 -68.26505819374415 30 0.0 0 VERTEX 5 EF8 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.52302290350257 20 -68.27033156170408 30 0.0 0 VERTEX 5 EF9 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.55512734965401 20 -68.2735166769612 30 0.0 0 VERTEX 5 EFA 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.58743845106931 20 -68.27458477431391 30 0.0 0 VERTEX 5 EFB 330 EB9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.58743845106931 20 -68.27458477431391 30 0.0 0 SEQEND 5 EFC 330 EB9 100 AcDbEntity 8 Graphics 370 0 0 POLYLINE 5 EFD 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 EFE 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.31275668166098 20 -67.62191143463332 30 0.0 0 VERTEX 5 EFF 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.3369669303769 20 -67.58584104939818 30 0.0 0 VERTEX 5 F00 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.36514400131867 20 -67.55412379799934 30 0.0 0 VERTEX 5 F01 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.39676128943665 20 -67.52689997387597 30 0.0 0 VERTEX 5 F02 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.4312921896812 20 -67.5043098704673 30 0.0 0 VERTEX 5 F03 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.4682100970027 20 -67.4864937812125 30 0.0 0 VERTEX 5 F04 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.5069884063515 20 -67.47359199955078 30 0.0 0 VERTEX 5 F05 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54710051267796 20 -67.46574481892131 30 0.0 0 VERTEX 5 F06 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.58801981093244 20 -67.4630925327633 30 0.0 0 VERTEX 5 F07 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.6082450278724 20 -67.463739161037 30 0.0 0 VERTEX 5 F08 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.62847478668628 20 -67.46568981178147 30 0.0 0 VERTEX 5 F09 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.64864701509705 20 -67.46896063388184 30 0.0 0 VERTEX 5 F0A 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.66869964082764 20 -67.47356777622313 30 0.0 0 VERTEX 5 F0B 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.68857059160099 20 -67.4795273876905 30 0.0 0 VERTEX 5 F0C 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.70819779514007 20 -67.48685561716898 30 0.0 0 VERTEX 5 F0D 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.72751917916781 20 -67.4955686135437 30 0.0 0 VERTEX 5 F0E 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.74647267140715 20 -67.5056825256997 30 0.0 0 VERTEX 5 F0F 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.79866372323488 20 -67.54326304196243 30 0.0 0 VERTEX 5 F10 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.84102742150813 20 -67.58908377916718 30 0.0 0 VERTEX 5 F11 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.87309671019099 20 -67.64140091005088 30 0.0 0 VERTEX 5 F12 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89440453324761 20 -67.69847060735046 30 0.0 0 VERTEX 5 F13 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.9044838346421 20 -67.75854904380282 30 0.0 0 VERTEX 5 F14 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.90286755833857 20 -67.8198923921449 30 0.0 0 VERTEX 5 F15 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.88908864830116 20 -67.88075682511361 30 0.0 0 VERTEX 5 F16 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.86268004849398 20 -67.93939851544587 30 0.0 0 VERTEX 5 F17 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.83846984183246 20 -67.97546267663155 30 0.0 0 VERTEX 5 F18 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.81029306527141 20 -68.00717673189689 30 0.0 0 VERTEX 5 F19 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7786765761868 20 -68.03439937849738 30 0.0 0 VERTEX 5 F1A 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.74414723195461 20 -68.0569893136885 30 0.0 0 VERTEX 5 F1B 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.70723188995079 20 -68.07480523472576 30 0.0 0 VERTEX 5 F1C 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.66845740755133 20 -68.08770583886461 30 0.0 0 VERTEX 5 F1D 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.62835064213218 20 -68.09554982336057 30 0.0 0 VERTEX 5 F1E 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.58743845106931 20 -68.09819588546911 30 0.0 0 VERTEX 5 F1F 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.56721319207496 20 -68.09755014033756 30 0.0 0 VERTEX 5 F20 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54698313888036 20 -68.09560163436689 30 0.0 0 VERTEX 5 F21 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.52681011143622 20 -68.092333461693 30 0.0 0 VERTEX 5 F22 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.50675592969326 20 -68.08772871645182 30 0.0 0 VERTEX 5 F23 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.48688241360222 20 -68.08177049277927 30 0.0 0 VERTEX 5 F24 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.46725138311382 20 -68.07444188481129 30 0.0 0 VERTEX 5 F25 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44792465817877 20 -68.0657259866838 30 0.0 0 VERTEX 5 F26 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.42896405874781 20 -68.05560589253271 30 0.0 0 VERTEX 5 F27 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.37677918891515 20 -68.01803160031945 30 0.0 0 VERTEX 5 F28 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.3344183923947 20 -67.9722140592482 30 0.0 0 VERTEX 5 F29 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.30234948220133 20 -67.91989810588737 30 0.0 0 VERTEX 5 F2A 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.2810402713499 20 -67.86282857680536 30 0.0 0 VERTEX 5 F2B 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.27095857285528 20 -67.80275030857054 30 0.0 0 VERTEX 5 F2C 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.27257219973234 20 -67.74140813775134 30 0.0 0 VERTEX 5 F2D 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.28634896499596 20 -67.68054690091613 30 0.0 0 VERTEX 5 F2E 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.31275668166098 20 -67.62191143463332 30 0.0 0 VERTEX 5 F2F 330 EFD 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.31275668166098 20 -67.62191143463332 30 0.0 0 SEQEND 5 F30 330 EFD 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 F31 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 2 92 1 93 64 72 1 10 20.58743845106931 20 -68.27458477431391 11 20.65276586393642 21 -68.27022095866299 72 1 10 20.65276586393642 20 -68.27022095866299 11 20.7162147072805 21 -68.25741783659609 72 1 10 20.7162147072805 20 -68.25741783659609 11 20.777034814924 21 -68.23660789544194 72 1 10 20.777034814924 20 -68.23660789544194 11 20.83447602068935 21 -68.20822362252927 72 1 10 20.83447602068935 20 -68.20822362252927 11 20.88778815839899 21 -68.17269750518683 72 1 10 20.88778815839899 20 -68.17269750518683 11 20.93622106187536 21 -68.13046203074336 72 1 10 20.93622106187536 20 -68.13046203074336 11 20.97902456494089 21 -68.0819496865276 72 1 10 20.97902456494089 20 -68.0819496865276 11 21.01544850141803 21 -68.02759295986827 72 1 10 21.01544850141803 20 -68.02759295986827 11 21.03790424105626 21 -67.98391468347279 72 1 10 21.03790424105626 20 -67.98391468347279 11 21.05578202409862 21 -67.93875727013388 72 1 10 21.05578202409862 20 -67.93875727013388 11 21.06904374926936 21 -67.89240786721446 72 1 10 21.06904374926936 20 -67.89240786721446 11 21.07765131529273 21 -67.8451536220775 72 1 10 21.07765131529273 20 -67.8451536220775 11 21.08156662089297 21 -67.79728168208598 72 1 10 21.08156662089297 20 -67.79728168208598 11 21.08075156479435 21 -67.74907919460281 72 1 10 21.08075156479435 20 -67.74907919460281 11 21.07516804572109 21 -67.70083330699099 72 1 10 21.07516804572109 20 -67.70083330699099 11 21.06477796239745 21 -67.65283116661344 72 1 10 21.06477796239745 20 -67.65283116661344 11 21.04977787703411 21 -67.60606504676088 72 1 10 21.04977787703411 20 -67.60606504676088 11 21.03049152431178 21 -67.56148937177458 72 1 10 21.03049152431178 20 -67.56148937177458 11 21.00709578498744 21 -67.51933451559339 72 1 10 21.00709578498744 20 -67.51933451559339 11 20.97976753981807 21 -67.47983085215608 72 1 10 20.97976753981807 20 -67.47983085215608 11 20.94868366956062 21 -67.44320875540153 72 1 10 20.94868366956062 20 -67.44320875540153 11 20.91402105497207 21 -67.40969859926852 72 1 10 20.91402105497207 20 -67.40969859926852 11 20.87595657680939 21 -67.37953075769589 72 1 10 20.87595657680939 20 -67.37953075769589 11 20.83466711582955 21 -67.35293560462244 72 1 10 20.83466711582955 20 -67.35293560462244 11 20.80607143550716 21 -67.33765152597526 72 1 10 20.80607143550716 20 -67.33765152597526 11 20.77661961194883 21 -67.32431036006511 72 1 10 20.77661961194883 20 -67.32431036006511 11 20.74642039780256 21 -67.31294137674624 72 1 10 20.74642039780256 20 -67.31294137674624 11 20.71558254571636 21 -67.30357384587285 72 1 10 20.71558254571636 20 -67.30357384587285 11 20.68421480833824 21 -67.29623703729915 72 1 10 20.68421480833824 20 -67.29623703729915 11 20.65242593831621 21 -67.29096022087938 72 1 10 20.65242593831621 20 -67.29096022087938 11 20.62032468829827 21 -67.28777266646777 72 1 10 20.62032468829827 20 -67.28777266646777 11 20.58801981093244 21 -67.28670364391851 72 1 10 20.58801981093244 20 -67.28670364391851 11 20.52269239806533 21 -67.29107456676104 72 1 10 20.52269239806533 20 -67.29107456676104 11 20.45924355472125 21 -67.30388302973525 72 1 10 20.45924355472125 20 -67.30388302973525 11 20.39842344707775 21 -67.32469679783873 72 1 10 20.39842344707775 20 -67.32469679783873 11 20.3409822413124 21 -67.35308363606907 72 1 10 20.3409822413124 20 -67.35308363606907 11 20.28767010360276 21 -67.38861130942388 72 1 10 20.28767010360276 20 -67.38861130942388 11 20.23923720012639 21 -67.43084758290073 72 1 10 20.23923720012639 20 -67.43084758290073 11 20.19643369706085 21 -67.47936022149722 72 1 10 20.19643369706085 20 -67.47936022149722 11 20.16000976058372 21 -67.53371699021092 72 1 10 20.16000976058372 20 -67.53371699021092 11 20.13754779689603 21 -67.57738908461133 72 1 10 20.13754779689603 20 -67.57738908461133 11 20.11966681772016 21 -67.62254359619746 72 1 10 20.11966681772016 20 -67.62254359619746 11 20.10640391502655 21 -67.66889262062737 72 1 10 20.10640391502655 20 -67.66889262062737 11 20.09779618078563 21 -67.71614825355914 72 1 10 20.09779618078563 20 -67.71614825355914 11 20.09388070696783 21 -67.76402259065081 72 1 10 20.09388070696783 20 -67.76402259065081 11 20.09469458554359 21 -67.81222772756043 72 1 10 20.09469458554359 20 -67.81222772756043 11 20.10027490848334 21 -67.86047575994606 72 1 10 20.10027490848334 20 -67.86047575994606 11 20.11065876775751 21 -67.90847878346575 72 1 10 20.11065876775751 20 -67.90847878346575 11 20.12566591825808 21 -67.95524490331832 72 1 10 20.12566591825808 20 -67.95524490331832 11 20.144957317507 21 -67.99982057830461 72 1 10 20.144957317507 20 -67.99982057830461 11 20.16835608474729 21 -68.0419754344858 72 1 10 20.16835608474729 20 -68.0419754344858 11 20.19568533922198 21 -68.08147909792311 72 1 10 20.19568533922198 20 -68.08147909792311 11 20.22676820017412 21 -68.11810119467766 72 1 10 20.22676820017412 20 -68.11810119467766 11 20.26142778684671 21 -68.15161135081068 72 1 10 20.26142778684671 20 -68.15161135081068 11 20.2994872184828 21 -68.18177919238332 72 1 10 20.2994872184828 20 -68.18177919238332 11 20.34076961432542 21 -68.20837434545676 72 1 10 20.34076961432542 20 -68.20837434545676 11 20.36937151869726 21 -68.2236574989074 72 1 10 20.36937151869726 20 -68.2236574989074 11 20.3988265383891 21 -68.23699622566302 72 1 10 20.3988265383891 20 -68.23699622566302 11 20.42902693005824 21 -68.24836176052206 72 1 10 20.42902693005824 20 -68.24836176052206 11 20.459864950362 21 -68.25772533828297 72 1 10 20.459864950362 20 -68.25772533828297 11 20.49123285595767 21 -68.26505819374415 72 1 10 20.49123285595767 20 -68.26505819374415 11 20.52302290350257 21 -68.27033156170408 72 1 10 20.52302290350257 20 -68.27033156170408 11 20.55512734965401 21 -68.2735166769612 72 1 10 20.55512734965401 20 -68.2735166769612 11 20.58743845106931 21 -68.27458477431391 97 0 92 1 93 48 72 1 10 20.31275668166098 20 -67.62191143463332 11 20.3369669303769 21 -67.58584104939818 72 1 10 20.3369669303769 20 -67.58584104939818 11 20.36514400131867 21 -67.55412379799934 72 1 10 20.36514400131867 20 -67.55412379799934 11 20.39676128943665 21 -67.52689997387597 72 1 10 20.39676128943665 20 -67.52689997387597 11 20.4312921896812 21 -67.5043098704673 72 1 10 20.4312921896812 20 -67.5043098704673 11 20.4682100970027 21 -67.4864937812125 72 1 10 20.4682100970027 20 -67.4864937812125 11 20.5069884063515 21 -67.47359199955078 72 1 10 20.5069884063515 20 -67.47359199955078 11 20.54710051267796 21 -67.46574481892131 72 1 10 20.54710051267796 20 -67.46574481892131 11 20.58801981093244 21 -67.4630925327633 72 1 10 20.58801981093244 20 -67.4630925327633 11 20.6082450278724 21 -67.463739161037 72 1 10 20.6082450278724 20 -67.463739161037 11 20.62847478668628 21 -67.46568981178147 72 1 10 20.62847478668628 20 -67.46568981178147 11 20.64864701509705 21 -67.46896063388184 72 1 10 20.64864701509705 20 -67.46896063388184 11 20.66869964082764 21 -67.47356777622313 72 1 10 20.66869964082764 20 -67.47356777622313 11 20.68857059160099 21 -67.4795273876905 72 1 10 20.68857059160099 20 -67.4795273876905 11 20.70819779514007 21 -67.48685561716898 72 1 10 20.70819779514007 20 -67.48685561716898 11 20.72751917916781 21 -67.4955686135437 72 1 10 20.72751917916781 20 -67.4955686135437 11 20.74647267140715 21 -67.5056825256997 72 1 10 20.74647267140715 20 -67.5056825256997 11 20.79866372323488 21 -67.54326304196243 72 1 10 20.79866372323488 20 -67.54326304196243 11 20.84102742150813 21 -67.58908377916718 72 1 10 20.84102742150813 20 -67.58908377916718 11 20.87309671019099 21 -67.64140091005088 72 1 10 20.87309671019099 20 -67.64140091005088 11 20.89440453324761 21 -67.69847060735046 72 1 10 20.89440453324761 20 -67.69847060735046 11 20.9044838346421 21 -67.75854904380282 72 1 10 20.9044838346421 20 -67.75854904380282 11 20.90286755833857 21 -67.8198923921449 72 1 10 20.90286755833857 20 -67.8198923921449 11 20.88908864830116 21 -67.88075682511361 72 1 10 20.88908864830116 20 -67.88075682511361 11 20.86268004849398 21 -67.93939851544587 72 1 10 20.86268004849398 20 -67.93939851544587 11 20.83846984183246 21 -67.97546267663155 72 1 10 20.83846984183246 20 -67.97546267663155 11 20.81029306527141 21 -68.00717673189689 72 1 10 20.81029306527141 20 -68.00717673189689 11 20.7786765761868 21 -68.03439937849738 72 1 10 20.7786765761868 20 -68.03439937849738 11 20.74414723195461 21 -68.0569893136885 72 1 10 20.74414723195461 20 -68.0569893136885 11 20.70723188995079 21 -68.07480523472576 72 1 10 20.70723188995079 20 -68.07480523472576 11 20.66845740755133 21 -68.08770583886461 72 1 10 20.66845740755133 20 -68.08770583886461 11 20.62835064213218 21 -68.09554982336057 72 1 10 20.62835064213218 20 -68.09554982336057 11 20.58743845106931 21 -68.09819588546911 72 1 10 20.58743845106931 20 -68.09819588546911 11 20.56721319207496 21 -68.09755014033756 72 1 10 20.56721319207496 20 -68.09755014033756 11 20.54698313888036 21 -68.09560163436689 72 1 10 20.54698313888036 20 -68.09560163436689 11 20.52681011143622 21 -68.092333461693 72 1 10 20.52681011143622 20 -68.092333461693 11 20.50675592969326 21 -68.08772871645182 72 1 10 20.50675592969326 20 -68.08772871645182 11 20.48688241360222 21 -68.08177049277927 72 1 10 20.48688241360222 20 -68.08177049277927 11 20.46725138311382 21 -68.07444188481129 72 1 10 20.46725138311382 20 -68.07444188481129 11 20.44792465817877 21 -68.0657259866838 72 1 10 20.44792465817877 20 -68.0657259866838 11 20.42896405874781 21 -68.05560589253271 72 1 10 20.42896405874781 20 -68.05560589253271 11 20.37677918891515 21 -68.01803160031945 72 1 10 20.37677918891515 20 -68.01803160031945 11 20.3344183923947 21 -67.9722140592482 72 1 10 20.3344183923947 20 -67.9722140592482 11 20.30234948220133 21 -67.91989810588737 72 1 10 20.30234948220133 20 -67.91989810588737 11 20.2810402713499 21 -67.86282857680536 72 1 10 20.2810402713499 20 -67.86282857680536 11 20.27095857285528 21 -67.80275030857054 72 1 10 20.27095857285528 20 -67.80275030857054 11 20.27257219973234 21 -67.74140813775134 72 1 10 20.27257219973234 20 -67.74140813775134 11 20.28634896499596 21 -67.68054690091613 72 1 10 20.28634896499596 20 -67.68054690091613 11 20.31275668166098 21 -67.62191143463332 97 0 75 2 76 1 98 0 0 POLYLINE 5 F32 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 F33 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55580104787713 20 -64.66683771846671 30 0.0 0 VERTEX 5 F34 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.6374750435105 20 -64.65858462888188 30 0.0 0 VERTEX 5 F35 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.71358372962072 20 -64.63491944709203 30 0.0 0 VERTEX 5 F36 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.78248597576082 20 -64.59748330354417 30 0.0 0 VERTEX 5 F37 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.84254065148383 20 -64.54791732868524 30 0.0 0 VERTEX 5 F38 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.89210662634276 20 -64.48786265296256 30 0.0 0 VERTEX 5 F39 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.92954276989063 20 -64.41896040682214 30 0.0 0 VERTEX 5 F3A 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.95320795168047 20 -64.3428517207116 30 0.0 0 VERTEX 5 F3B 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.9614610412653 20 -64.26117772507854 30 0.0 0 VERTEX 5 F3C 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.95320795168047 20 -64.17949632787284 30 0.0 0 VERTEX 5 F3D 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.92954276989063 20 -64.10336812852647 30 0.0 0 VERTEX 5 F3E 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.89210662634276 20 -64.03443829470767 30 0.0 0 VERTEX 5 F3F 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.84254065148383 20 -63.97435199408503 30 0.0 0 VERTEX 5 F40 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.78248597576082 20 -63.92475439432582 30 0.0 0 VERTEX 5 F41 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.71358372962072 20 -63.88729066309926 30 0.0 0 VERTEX 5 F42 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.6374750435105 20 -63.86360596807295 30 0.0 0 VERTEX 5 F43 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55580104787713 20 -63.85534547691611 30 0.0 0 VERTEX 5 F44 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.47411965067143 20 -63.86360596807295 30 0.0 0 VERTEX 5 F45 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.39799145132505 20 -63.88729066309926 30 0.0 0 VERTEX 5 F46 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.32906161750626 20 -63.92475439432582 30 0.0 0 VERTEX 5 F47 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.2689753168833 20 -63.97435199408503 30 0.0 0 VERTEX 5 F48 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.21937771712441 20 -64.03443829470767 30 0.0 0 VERTEX 5 F49 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.18191398589785 20 -64.10336812852647 30 0.0 0 VERTEX 5 F4A 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.15822929087186 20 -64.17949632787284 30 0.0 0 VERTEX 5 F4B 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.1499687997147 20 -64.26117772507854 30 0.0 0 VERTEX 5 F4C 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.15822929087186 20 -64.3428517207116 30 0.0 0 VERTEX 5 F4D 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.18191398589785 20 -64.41896040682214 30 0.0 0 VERTEX 5 F4E 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.21937771712441 20 -64.48786265296256 30 0.0 0 VERTEX 5 F4F 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.2689753168833 20 -64.54791732868524 30 0.0 0 VERTEX 5 F50 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.32906161750626 20 -64.59748330354417 30 0.0 0 VERTEX 5 F51 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.39799145132505 20 -64.63491944709203 30 0.0 0 VERTEX 5 F52 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.47411965067143 20 -64.65858462888188 30 0.0 0 VERTEX 5 F53 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55580104787713 20 -64.66683771846671 30 0.0 0 VERTEX 5 F54 330 F32 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 18.55580104787713 20 -64.66683771846671 30 0.0 0 SEQEND 5 F56 330 F32 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 F55 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 32 72 1 10 18.55580104787713 20 -64.66683771846671 11 18.6374750435105 21 -64.65858462888188 72 1 10 18.6374750435105 20 -64.65858462888188 11 18.71358372962072 21 -64.63491944709203 72 1 10 18.71358372962072 20 -64.63491944709203 11 18.78248597576082 21 -64.59748330354417 72 1 10 18.78248597576082 20 -64.59748330354417 11 18.84254065148383 21 -64.54791732868524 72 1 10 18.84254065148383 20 -64.54791732868524 11 18.89210662634276 21 -64.48786265296256 72 1 10 18.89210662634276 20 -64.48786265296256 11 18.92954276989063 21 -64.41896040682214 72 1 10 18.92954276989063 20 -64.41896040682214 11 18.95320795168047 21 -64.3428517207116 72 1 10 18.95320795168047 20 -64.3428517207116 11 18.9614610412653 21 -64.26117772507854 72 1 10 18.9614610412653 20 -64.26117772507854 11 18.95320795168047 21 -64.17949632787284 72 1 10 18.95320795168047 20 -64.17949632787284 11 18.92954276989063 21 -64.10336812852647 72 1 10 18.92954276989063 20 -64.10336812852647 11 18.89210662634276 21 -64.03443829470767 72 1 10 18.89210662634276 20 -64.03443829470767 11 18.84254065148383 21 -63.97435199408503 72 1 10 18.84254065148383 20 -63.97435199408503 11 18.78248597576082 21 -63.92475439432582 72 1 10 18.78248597576082 20 -63.92475439432582 11 18.71358372962072 21 -63.88729066309926 72 1 10 18.71358372962072 20 -63.88729066309926 11 18.6374750435105 21 -63.86360596807295 72 1 10 18.6374750435105 20 -63.86360596807295 11 18.55580104787713 21 -63.85534547691611 72 1 10 18.55580104787713 20 -63.85534547691611 11 18.47411965067143 21 -63.86360596807295 72 1 10 18.47411965067143 20 -63.86360596807295 11 18.39799145132505 21 -63.88729066309926 72 1 10 18.39799145132505 20 -63.88729066309926 11 18.32906161750626 21 -63.92475439432582 72 1 10 18.32906161750626 20 -63.92475439432582 11 18.2689753168833 21 -63.97435199408503 72 1 10 18.2689753168833 20 -63.97435199408503 11 18.21937771712441 21 -64.03443829470767 72 1 10 18.21937771712441 20 -64.03443829470767 11 18.18191398589785 21 -64.10336812852647 72 1 10 18.18191398589785 20 -64.10336812852647 11 18.15822929087186 21 -64.17949632787284 72 1 10 18.15822929087186 20 -64.17949632787284 11 18.1499687997147 21 -64.26117772507854 72 1 10 18.1499687997147 20 -64.26117772507854 11 18.15822929087186 21 -64.3428517207116 72 1 10 18.15822929087186 20 -64.3428517207116 11 18.18191398589785 21 -64.41896040682214 72 1 10 18.18191398589785 20 -64.41896040682214 11 18.21937771712441 21 -64.48786265296256 72 1 10 18.21937771712441 20 -64.48786265296256 11 18.2689753168833 21 -64.54791732868524 72 1 10 18.2689753168833 20 -64.54791732868524 11 18.32906161750626 21 -64.59748330354417 72 1 10 18.32906161750626 20 -64.59748330354417 11 18.39799145132505 21 -64.63491944709203 72 1 10 18.39799145132505 20 -64.63491944709203 11 18.47411965067143 21 -64.65858462888188 72 1 10 18.47411965067143 20 -64.65858462888188 11 18.55580104787713 21 -64.66683771846671 97 0 75 2 76 1 98 0 0 POLYLINE 5 F57 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 F58 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.5311970962305 20 -62.33416356540404 30 0.0 0 VERTEX 5 F59 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.53973716496073 20 -62.29471116626603 30 0.0 0 VERTEX 5 F5A 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.54432075684463 20 -62.25506094328569 30 0.0 0 VERTEX 5 F5B 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.54498016965235 20 -62.21545109251807 30 0.0 0 VERTEX 5 F5C 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.54174770115408 20 -62.17611981001821 30 0.0 0 VERTEX 5 F5D 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.53465564911999 20 -62.13730529184113 30 0.0 0 VERTEX 5 F5E 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.52373631132026 20 -62.09924573404187 30 0.0 0 VERTEX 5 F5F 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.50902198552505 20 -62.06217933267548 30 0.0 0 VERTEX 5 F60 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.49054496950455 20 -62.02634428379697 30 0.0 0 VERTEX 5 F61 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.46872715288166 20 -61.99241547622896 30 0.0 0 VERTEX 5 F62 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.44396620195164 20 -61.96113508581522 30 0.0 0 VERTEX 5 F63 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.41645186611427 20 -61.93264845252156 30 0.0 0 VERTEX 5 F64 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.38637389476931 20 -61.90710091631376 30 0.0 0 VERTEX 5 F65 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.35392203731655 20 -61.88463781715759 30 0.0 0 VERTEX 5 F66 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.31928604315577 20 -61.86540449501884 30 0.0 0 VERTEX 5 F67 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.28265566168672 20 -61.84954628986331 30 0.0 0 VERTEX 5 F68 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.24422064230919 20 -61.83720854165675 30 0.0 0 VERTEX 5 F69 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.20502965324852 20 -61.82876031971045 30 0.0 0 VERTEX 5 F6A 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.16552981676056 20 -61.82420599768079 30 0.0 0 VERTEX 5 F6B 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.12597749639606 20 -61.82353144529329 30 0.0 0 VERTEX 5 F6C 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.08662905570579 20 -61.82672253227352 30 0.0 0 VERTEX 5 F6D 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.04774085824051 20 -61.83376512834703 30 0.0 0 VERTEX 5 F6E 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.00956926755096 20 -61.84464510323937 30 0.0 0 VERTEX 5 F6F 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.97237064718791 20 -61.85934832667607 30 0.0 0 VERTEX 5 F70 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.93640136070212 20 -61.8778606683827 30 0.0 0 VERTEX 5 F71 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.9024725531341 20 -61.89967848500559 30 0.0 0 VERTEX 5 F72 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.87119216272037 20 -61.92443943593562 30 0.0 0 VERTEX 5 F73 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.84270552942671 20 -61.95195377177267 30 0.0 0 VERTEX 5 F74 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.81715799321891 20 -61.98203174311794 30 0.0 0 VERTEX 5 F75 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.79469489406274 20 -62.0144836005707 30 0.0 0 VERTEX 5 F76 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.77546157192399 20 -62.04911959473149 30 0.0 0 VERTEX 5 F77 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.75960336676845 20 -62.08574997620053 30 0.0 0 VERTEX 5 F78 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.7472656185619 20 -62.12418499557806 30 0.0 0 VERTEX 5 F79 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73872554983167 20 -62.16358087361828 30 0.0 0 VERTEX 5 F7A 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73414195794778 20 -62.2031907243859 30 0.0 0 VERTEX 5 F7B 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73348254514005 20 -62.24277635182588 30 0.0 0 VERTEX 5 F7C 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73671501363832 20 -62.28209955988321 30 0.0 0 VERTEX 5 F7D 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.74380706567241 20 -62.32092215250282 30 0.0 0 VERTEX 5 F7E 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.75472640347214 20 -62.35900593362971 30 0.0 0 VERTEX 5 F7F 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.76944072926735 20 -62.3961127072085 30 0.0 0 VERTEX 5 F80 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.78791774528785 20 -62.43200427718514 30 0.0 0 VERTEX 5 F81 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.80973556191075 20 -62.46592568318082 30 0.0 0 VERTEX 5 F82 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.83449651284077 20 -62.4971865603584 30 0.0 0 VERTEX 5 F83 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.86201084867814 20 -62.52564560597337 30 0.0 0 VERTEX 5 F84 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.89208882002309 20 -62.55116151728122 30 0.0 0 VERTEX 5 F85 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.92454067747585 20 -62.57359299153742 30 0.0 0 VERTEX 5 F86 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.95917667163664 20 -62.59279872599748 30 0.0 0 VERTEX 5 F87 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.99580705310568 20 -62.60863741791687 30 0.0 0 VERTEX 5 F88 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.03424207248321 20 -62.62096776455109 30 0.0 0 VERTEX 5 F89 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.04737750832605 20 -62.62423791378123 30 0.0 0 VERTEX 5 F8A 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.06055129777096 20 -62.62707204311402 30 0.0 0 VERTEX 5 F8B 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.07375334776478 20 -62.62947015254945 30 0.0 0 VERTEX 5 F8C 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.08697356525432 20 -62.63143224208753 30 0.0 0 VERTEX 5 F8D 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.1002018571864 20 -62.63295831172795 30 0.0 0 VERTEX 5 F8E 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.11342813050785 20 -62.63404836147165 30 0.0 0 VERTEX 5 F8F 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.12664229216548 20 -62.63470239131767 30 0.0 0 VERTEX 5 F90 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.13983424910612 20 -62.63492040126635 30 0.0 0 VERTEX 5 F91 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.16618653808743 20 -62.63405778165429 30 0.0 0 VERTEX 5 F92 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.19236118933279 20 -62.6314753057811 30 0.0 0 VERTEX 5 F93 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.21829360730184 20 -62.62718104808835 30 0.0 0 VERTEX 5 F94 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.24391919645423 20 -62.62118308301892 30 0.0 0 VERTEX 5 F95 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.26917336124962 20 -62.61348948501534 30 0.0 0 VERTEX 5 F96 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.29399150614766 20 -62.60410832852015 30 0.0 0 VERTEX 5 F97 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.318309035608 20 -62.5930476879759 30 0.0 0 VERTEX 5 F98 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.34206135409029 20 -62.58031563782514 30 0.0 0 VERTEX 5 F99 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.3759901616583 20 -62.55849815763735 30 0.0 0 VERTEX 5 F9A 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.40727055207203 20 -62.53373956175275 30 0.0 0 VERTEX 5 F9B 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.43575718536569 20 -62.50623161818272 30 0.0 0 VERTEX 5 F9C 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.46130472157349 20 -62.47616609493701 30 0.0 0 VERTEX 5 F9D 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.48376782072966 20 -62.44373476002539 30 0.0 0 VERTEX 5 F9E 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.50300114286841 20 -62.40912938145924 30 0.0 0 VERTEX 5 F9F 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.51885934802395 20 -62.37254172724866 30 0.0 0 VERTEX 5 FA0 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.5311970962305 20 -62.33416356540404 30 0.0 0 VERTEX 5 FA1 330 F57 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.5311970962305 20 -62.33416356540404 30 0.0 0 SEQEND 5 FA3 330 F57 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 FA2 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 72 72 1 10 26.5311970962305 20 -62.33416356540404 11 26.53973716496073 21 -62.29471116626603 72 1 10 26.53973716496073 20 -62.29471116626603 11 26.54432075684463 21 -62.25506094328569 72 1 10 26.54432075684463 20 -62.25506094328569 11 26.54498016965235 21 -62.21545109251807 72 1 10 26.54498016965235 20 -62.21545109251807 11 26.54174770115408 21 -62.17611981001821 72 1 10 26.54174770115408 20 -62.17611981001821 11 26.53465564911999 21 -62.13730529184113 72 1 10 26.53465564911999 20 -62.13730529184113 11 26.52373631132026 21 -62.09924573404187 72 1 10 26.52373631132026 20 -62.09924573404187 11 26.50902198552505 21 -62.06217933267548 72 1 10 26.50902198552505 20 -62.06217933267548 11 26.49054496950455 21 -62.02634428379697 72 1 10 26.49054496950455 20 -62.02634428379697 11 26.46872715288166 21 -61.99241547622896 72 1 10 26.46872715288166 20 -61.99241547622896 11 26.44396620195164 21 -61.96113508581522 72 1 10 26.44396620195164 20 -61.96113508581522 11 26.41645186611427 21 -61.93264845252156 72 1 10 26.41645186611427 20 -61.93264845252156 11 26.38637389476931 21 -61.90710091631376 72 1 10 26.38637389476931 20 -61.90710091631376 11 26.35392203731655 21 -61.88463781715759 72 1 10 26.35392203731655 20 -61.88463781715759 11 26.31928604315577 21 -61.86540449501884 72 1 10 26.31928604315577 20 -61.86540449501884 11 26.28265566168672 21 -61.84954628986331 72 1 10 26.28265566168672 20 -61.84954628986331 11 26.24422064230919 21 -61.83720854165675 72 1 10 26.24422064230919 20 -61.83720854165675 11 26.20502965324852 21 -61.82876031971045 72 1 10 26.20502965324852 20 -61.82876031971045 11 26.16552981676056 21 -61.82420599768079 72 1 10 26.16552981676056 20 -61.82420599768079 11 26.12597749639606 21 -61.82353144529329 72 1 10 26.12597749639606 20 -61.82353144529329 11 26.08662905570579 21 -61.82672253227352 72 1 10 26.08662905570579 20 -61.82672253227352 11 26.04774085824051 21 -61.83376512834703 72 1 10 26.04774085824051 20 -61.83376512834703 11 26.00956926755096 21 -61.84464510323937 72 1 10 26.00956926755096 20 -61.84464510323937 11 25.97237064718791 21 -61.85934832667607 72 1 10 25.97237064718791 20 -61.85934832667607 11 25.93640136070212 21 -61.8778606683827 72 1 10 25.93640136070212 20 -61.8778606683827 11 25.9024725531341 21 -61.89967848500559 72 1 10 25.9024725531341 20 -61.89967848500559 11 25.87119216272037 21 -61.92443943593562 72 1 10 25.87119216272037 20 -61.92443943593562 11 25.84270552942671 21 -61.95195377177267 72 1 10 25.84270552942671 20 -61.95195377177267 11 25.81715799321891 21 -61.98203174311794 72 1 10 25.81715799321891 20 -61.98203174311794 11 25.79469489406274 21 -62.0144836005707 72 1 10 25.79469489406274 20 -62.0144836005707 11 25.77546157192399 21 -62.04911959473149 72 1 10 25.77546157192399 20 -62.04911959473149 11 25.75960336676845 21 -62.08574997620053 72 1 10 25.75960336676845 20 -62.08574997620053 11 25.7472656185619 21 -62.12418499557806 72 1 10 25.7472656185619 20 -62.12418499557806 11 25.73872554983167 21 -62.16358087361828 72 1 10 25.73872554983167 20 -62.16358087361828 11 25.73414195794778 21 -62.2031907243859 72 1 10 25.73414195794778 20 -62.2031907243859 11 25.73348254514005 21 -62.24277635182588 72 1 10 25.73348254514005 20 -62.24277635182588 11 25.73671501363832 21 -62.28209955988321 72 1 10 25.73671501363832 20 -62.28209955988321 11 25.74380706567241 21 -62.32092215250282 72 1 10 25.74380706567241 20 -62.32092215250282 11 25.75472640347214 21 -62.35900593362971 72 1 10 25.75472640347214 20 -62.35900593362971 11 25.76944072926735 21 -62.3961127072085 72 1 10 25.76944072926735 20 -62.3961127072085 11 25.78791774528785 21 -62.43200427718514 72 1 10 25.78791774528785 20 -62.43200427718514 11 25.80973556191075 21 -62.46592568318082 72 1 10 25.80973556191075 20 -62.46592568318082 11 25.83449651284077 21 -62.4971865603584 72 1 10 25.83449651284077 20 -62.4971865603584 11 25.86201084867814 21 -62.52564560597337 72 1 10 25.86201084867814 20 -62.52564560597337 11 25.89208882002309 21 -62.55116151728122 72 1 10 25.89208882002309 20 -62.55116151728122 11 25.92454067747585 21 -62.57359299153742 72 1 10 25.92454067747585 20 -62.57359299153742 11 25.95917667163664 21 -62.59279872599748 72 1 10 25.95917667163664 20 -62.59279872599748 11 25.99580705310568 21 -62.60863741791687 72 1 10 25.99580705310568 20 -62.60863741791687 11 26.03424207248321 21 -62.62096776455109 72 1 10 26.03424207248321 20 -62.62096776455109 11 26.04737750832605 21 -62.62423791378123 72 1 10 26.04737750832605 20 -62.62423791378123 11 26.06055129777096 21 -62.62707204311402 72 1 10 26.06055129777096 20 -62.62707204311402 11 26.07375334776478 21 -62.62947015254945 72 1 10 26.07375334776478 20 -62.62947015254945 11 26.08697356525432 21 -62.63143224208753 72 1 10 26.08697356525432 20 -62.63143224208753 11 26.1002018571864 21 -62.63295831172795 72 1 10 26.1002018571864 20 -62.63295831172795 11 26.11342813050785 21 -62.63404836147165 72 1 10 26.11342813050785 20 -62.63404836147165 11 26.12664229216548 21 -62.63470239131767 72 1 10 26.12664229216548 20 -62.63470239131767 11 26.13983424910612 21 -62.63492040126635 72 1 10 26.13983424910612 20 -62.63492040126635 11 26.16618653808743 21 -62.63405778165429 72 1 10 26.16618653808743 20 -62.63405778165429 11 26.19236118933279 21 -62.6314753057811 72 1 10 26.19236118933279 20 -62.6314753057811 11 26.21829360730184 21 -62.62718104808835 72 1 10 26.21829360730184 20 -62.62718104808835 11 26.24391919645423 21 -62.62118308301892 72 1 10 26.24391919645423 20 -62.62118308301892 11 26.26917336124962 21 -62.61348948501534 72 1 10 26.26917336124962 20 -62.61348948501534 11 26.29399150614766 21 -62.60410832852015 72 1 10 26.29399150614766 20 -62.60410832852015 11 26.318309035608 21 -62.5930476879759 72 1 10 26.318309035608 20 -62.5930476879759 11 26.34206135409029 21 -62.58031563782514 72 1 10 26.34206135409029 20 -62.58031563782514 11 26.3759901616583 21 -62.55849815763735 72 1 10 26.3759901616583 20 -62.55849815763735 11 26.40727055207203 21 -62.53373956175275 72 1 10 26.40727055207203 20 -62.53373956175275 11 26.43575718536569 21 -62.50623161818272 72 1 10 26.43575718536569 20 -62.50623161818272 11 26.46130472157349 21 -62.47616609493701 72 1 10 26.46130472157349 20 -62.47616609493701 11 26.48376782072966 21 -62.44373476002539 72 1 10 26.48376782072966 20 -62.44373476002539 11 26.50300114286841 21 -62.40912938145924 72 1 10 26.50300114286841 20 -62.40912938145924 11 26.51885934802395 21 -62.37254172724866 72 1 10 26.51885934802395 20 -62.37254172724866 11 26.5311970962305 21 -62.33416356540404 97 0 75 2 76 1 98 0 0 POLYLINE 5 FA4 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 FA5 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.78791774528785 20 -66.09035117297194 30 0.0 0 VERTEX 5 FA6 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.76944072926735 20 -66.12618622185045 30 0.0 0 VERTEX 5 FA7 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.75472640347214 20 -66.16325262321685 30 0.0 0 VERTEX 5 FA8 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.74380706567241 20 -66.20131218101609 30 0.0 0 VERTEX 5 FA9 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73671501363832 20 -66.24012669919317 30 0.0 0 VERTEX 5 FAA 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73348254514005 20 -66.27945798169304 30 0.0 0 VERTEX 5 FAB 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73414195794778 20 -66.31906783246066 30 0.0 0 VERTEX 5 FAC 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.73872554983167 20 -66.35871805544099 30 0.0 0 VERTEX 5 FAD 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.7472656185619 20 -66.39817045457902 30 0.0 0 VERTEX 5 FAE 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.75960336676845 20 -66.43654861642364 30 0.0 0 VERTEX 5 FAF 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.77546157192399 20 -66.47313627063421 30 0.0 0 VERTEX 5 FB0 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.79469489406274 20 -66.50774164920037 30 0.0 0 VERTEX 5 FB1 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.81715799321891 20 -66.54017298411165 30 0.0 0 VERTEX 5 FB2 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.84270552942671 20 -66.57023850735769 30 0.0 0 VERTEX 5 FB3 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.87119216272037 20 -66.59774645092804 30 0.0 0 VERTEX 5 FB4 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.9024725531341 20 -66.62250504681232 30 0.0 0 VERTEX 5 FB5 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.93640136070212 20 -66.64432252700011 30 0.0 0 VERTEX 5 FB6 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.96056345714349 20 -66.65723759784854 30 0.0 0 VERTEX 5 FB7 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.98519790847367 20 -66.66835206800972 30 0.0 0 VERTEX 5 FB8 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.01022800748847 20 -66.67769016081135 30 0.0 0 VERTEX 5 FB9 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.03557704698375 20 -66.68527609958102 30 0.0 0 VERTEX 5 FBA 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.06116831975533 20 -66.69113410764636 30 0.0 0 VERTEX 5 FBB 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.08692511859906 20 -66.69528840833503 30 0.0 0 VERTEX 5 FBC 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.11277073631076 20 -66.69776322497462 30 0.0 0 VERTEX 5 FBD 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.13862846568628 20 -66.69858278089279 30 0.0 0 VERTEX 5 FBE 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.19093369517811 20 -66.69520564529896 30 0.0 0 VERTEX 5 FBF 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.24223163796263 20 -66.68519535515559 30 0.0 0 VERTEX 5 FC0 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.29183798503427 20 -66.66873358541991 30 0.0 0 VERTEX 5 FC1 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.33906842738747 20 -66.64600201104918 30 0.0 0 VERTEX 5 FC2 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.38323865601667 20 -66.61718230700059 30 0.0 0 VERTEX 5 FC3 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.42366436191629 20 -66.5824561482314 30 0.0 0 VERTEX 5 FC4 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.45966123608078 20 -66.54200520969883 30 0.0 0 VERTEX 5 FC5 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.49054496950455 20 -66.4960111663601 30 0.0 0 VERTEX 5 FC6 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.50902198552505 20 -66.46011959638379 30 0.0 0 VERTEX 5 FC7 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.52373631132026 20 -66.42301282280468 30 0.0 0 VERTEX 5 FC8 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.53465564911999 20 -66.3849290416778 30 0.0 0 VERTEX 5 FC9 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.54174770115408 20 -66.34610644905817 30 0.0 0 VERTEX 5 FCA 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.54498016965235 20 -66.30678324100086 30 0.0 0 VERTEX 5 FCB 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.54432075684463 20 -66.26719761356087 30 0.0 0 VERTEX 5 FCC 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.53973716496073 20 -66.22758776279325 30 0.0 0 VERTEX 5 FCD 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.5311970962305 20 -66.18819188475304 30 0.0 0 VERTEX 5 FCE 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.51885934802395 20 -66.14975686537551 30 0.0 0 VERTEX 5 FCF 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.50300114286841 20 -66.11312648390646 30 0.0 0 VERTEX 5 FD0 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.48376782072966 20 -66.07849048974568 30 0.0 0 VERTEX 5 FD1 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.46130472157349 20 -66.04603863229292 30 0.0 0 VERTEX 5 FD2 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.43575718536569 20 -66.01596066094797 30 0.0 0 VERTEX 5 FD3 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.40727055207203 20 -65.98844632511059 30 0.0 0 VERTEX 5 FD4 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.3759901616583 20 -65.96368537418057 30 0.0 0 VERTEX 5 FD5 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.34206135409029 20 -65.94186755755767 30 0.0 0 VERTEX 5 FD6 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.30610619787894 20 -65.92334815071382 30 0.0 0 VERTEX 5 FD7 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.26894189389671 20 -65.9086277690867 30 0.0 0 VERTEX 5 FD8 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.23081269403051 20 -65.8977265987827 30 0.0 0 VERTEX 5 FD9 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.19196285016731 20 -65.89066482590815 30 0.0 0 VERTEX 5 FDA 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.15263661419403 20 -65.88746263656941 30 0.0 0 VERTEX 5 FDB 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.11307823799763 20 -65.88814021687286 30 0.0 0 VERTEX 5 FDC 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.07353197346504 20 -65.89271775292484 30 0.0 0 VERTEX 5 FDD 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 26.03424207248321 20 -65.90121543083173 30 0.0 0 VERTEX 5 FDE 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.99580705310568 20 -65.91355317903827 30 0.0 0 VERTEX 5 FDF 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.95917667163664 20 -65.92941138419381 30 0.0 0 VERTEX 5 FE0 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.92454067747585 20 -65.94864470633256 30 0.0 0 VERTEX 5 FE1 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.89208882002309 20 -65.97110780548873 30 0.0 0 VERTEX 5 FE2 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.86201084867814 20 -65.99665534169654 30 0.0 0 VERTEX 5 FE3 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.83449651284077 20 -66.02514197499019 30 0.0 0 VERTEX 5 FE4 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.80973556191075 20 -66.05642236540392 30 0.0 0 VERTEX 5 FE5 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.78791774528785 20 -66.09035117297194 30 0.0 0 VERTEX 5 FE6 330 FA4 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 25.78791774528785 20 -66.09035117297194 30 0.0 0 SEQEND 5 FE8 330 FA4 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 FE7 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 25.78791774528785 20 -66.09035117297194 11 25.76944072926735 21 -66.12618622185045 72 1 10 25.76944072926735 20 -66.12618622185045 11 25.75472640347214 21 -66.16325262321685 72 1 10 25.75472640347214 20 -66.16325262321685 11 25.74380706567241 21 -66.20131218101609 72 1 10 25.74380706567241 20 -66.20131218101609 11 25.73671501363832 21 -66.24012669919317 72 1 10 25.73671501363832 20 -66.24012669919317 11 25.73348254514005 21 -66.27945798169304 72 1 10 25.73348254514005 20 -66.27945798169304 11 25.73414195794778 21 -66.31906783246066 72 1 10 25.73414195794778 20 -66.31906783246066 11 25.73872554983167 21 -66.35871805544099 72 1 10 25.73872554983167 20 -66.35871805544099 11 25.7472656185619 21 -66.39817045457902 72 1 10 25.7472656185619 20 -66.39817045457902 11 25.75960336676845 21 -66.43654861642364 72 1 10 25.75960336676845 20 -66.43654861642364 11 25.77546157192399 21 -66.47313627063421 72 1 10 25.77546157192399 20 -66.47313627063421 11 25.79469489406274 21 -66.50774164920037 72 1 10 25.79469489406274 20 -66.50774164920037 11 25.81715799321891 21 -66.54017298411165 72 1 10 25.81715799321891 20 -66.54017298411165 11 25.84270552942671 21 -66.57023850735769 72 1 10 25.84270552942671 20 -66.57023850735769 11 25.87119216272037 21 -66.59774645092804 72 1 10 25.87119216272037 20 -66.59774645092804 11 25.9024725531341 21 -66.62250504681232 72 1 10 25.9024725531341 20 -66.62250504681232 11 25.93640136070212 21 -66.64432252700011 72 1 10 25.93640136070212 20 -66.64432252700011 11 25.96056345714349 21 -66.65723759784854 72 1 10 25.96056345714349 20 -66.65723759784854 11 25.98519790847367 21 -66.66835206800972 72 1 10 25.98519790847367 20 -66.66835206800972 11 26.01022800748847 21 -66.67769016081135 72 1 10 26.01022800748847 20 -66.67769016081135 11 26.03557704698375 21 -66.68527609958102 72 1 10 26.03557704698375 20 -66.68527609958102 11 26.06116831975533 21 -66.69113410764636 72 1 10 26.06116831975533 20 -66.69113410764636 11 26.08692511859906 21 -66.69528840833503 72 1 10 26.08692511859906 20 -66.69528840833503 11 26.11277073631076 21 -66.69776322497462 72 1 10 26.11277073631076 20 -66.69776322497462 11 26.13862846568628 21 -66.69858278089279 72 1 10 26.13862846568628 20 -66.69858278089279 11 26.19093369517811 21 -66.69520564529896 72 1 10 26.19093369517811 20 -66.69520564529896 11 26.24223163796263 21 -66.68519535515559 72 1 10 26.24223163796263 20 -66.68519535515559 11 26.29183798503427 21 -66.66873358541991 72 1 10 26.29183798503427 20 -66.66873358541991 11 26.33906842738747 21 -66.64600201104918 72 1 10 26.33906842738747 20 -66.64600201104918 11 26.38323865601667 21 -66.61718230700059 72 1 10 26.38323865601667 20 -66.61718230700059 11 26.42366436191629 21 -66.5824561482314 72 1 10 26.42366436191629 20 -66.5824561482314 11 26.45966123608078 21 -66.54200520969883 72 1 10 26.45966123608078 20 -66.54200520969883 11 26.49054496950455 21 -66.4960111663601 72 1 10 26.49054496950455 20 -66.4960111663601 11 26.50902198552505 21 -66.46011959638379 72 1 10 26.50902198552505 20 -66.46011959638379 11 26.52373631132026 21 -66.42301282280468 72 1 10 26.52373631132026 20 -66.42301282280468 11 26.53465564911999 21 -66.3849290416778 72 1 10 26.53465564911999 20 -66.3849290416778 11 26.54174770115408 21 -66.34610644905817 72 1 10 26.54174770115408 20 -66.34610644905817 11 26.54498016965235 21 -66.30678324100086 72 1 10 26.54498016965235 20 -66.30678324100086 11 26.54432075684463 21 -66.26719761356087 72 1 10 26.54432075684463 20 -66.26719761356087 11 26.53973716496073 21 -66.22758776279325 72 1 10 26.53973716496073 20 -66.22758776279325 11 26.5311970962305 21 -66.18819188475304 72 1 10 26.5311970962305 20 -66.18819188475304 11 26.51885934802395 21 -66.14975686537551 72 1 10 26.51885934802395 20 -66.14975686537551 11 26.50300114286841 21 -66.11312648390646 72 1 10 26.50300114286841 20 -66.11312648390646 11 26.48376782072966 21 -66.07849048974568 72 1 10 26.48376782072966 20 -66.07849048974568 11 26.46130472157349 21 -66.04603863229292 72 1 10 26.46130472157349 20 -66.04603863229292 11 26.43575718536569 21 -66.01596066094797 72 1 10 26.43575718536569 20 -66.01596066094797 11 26.40727055207203 21 -65.98844632511059 72 1 10 26.40727055207203 20 -65.98844632511059 11 26.3759901616583 21 -65.96368537418057 72 1 10 26.3759901616583 20 -65.96368537418057 11 26.34206135409029 21 -65.94186755755767 72 1 10 26.34206135409029 20 -65.94186755755767 11 26.30610619787894 21 -65.92334815071382 72 1 10 26.30610619787894 20 -65.92334815071382 11 26.26894189389671 21 -65.9086277690867 72 1 10 26.26894189389671 20 -65.9086277690867 11 26.23081269403051 21 -65.8977265987827 72 1 10 26.23081269403051 20 -65.8977265987827 11 26.19196285016731 21 -65.89066482590815 72 1 10 26.19196285016731 20 -65.89066482590815 11 26.15263661419403 21 -65.88746263656941 72 1 10 26.15263661419403 20 -65.88746263656941 11 26.11307823799763 21 -65.88814021687286 72 1 10 26.11307823799763 20 -65.88814021687286 11 26.07353197346504 21 -65.89271775292484 72 1 10 26.07353197346504 20 -65.89271775292484 11 26.03424207248321 21 -65.90121543083173 72 1 10 26.03424207248321 20 -65.90121543083173 11 25.99580705310568 21 -65.91355317903827 72 1 10 25.99580705310568 20 -65.91355317903827 11 25.95917667163664 21 -65.92941138419381 72 1 10 25.95917667163664 20 -65.92941138419381 11 25.92454067747585 21 -65.94864470633256 72 1 10 25.92454067747585 20 -65.94864470633256 11 25.89208882002309 21 -65.97110780548873 72 1 10 25.89208882002309 20 -65.97110780548873 11 25.86201084867814 21 -65.99665534169654 72 1 10 25.86201084867814 20 -65.99665534169654 11 25.83449651284077 21 -66.02514197499019 72 1 10 25.83449651284077 20 -66.02514197499019 11 25.80973556191075 21 -66.05642236540392 72 1 10 25.80973556191075 20 -66.05642236540392 11 25.78791774528785 21 -66.09035117297194 97 0 75 2 76 1 98 0 0 POLYLINE 5 FE9 330 1F 100 AcDbEntity 8 Graphics 370 0 100 AcDb2dPolyline 66 1 10 0.0 20 0.0 30 0.0 0 VERTEX 5 FEA 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.69262152260334 20 -60.34961631112587 30 0.0 0 VERTEX 5 FEB 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.65343053354267 20 -60.34118221945403 30 0.0 0 VERTEX 5 FEC 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.61393069705471 20 -60.33666221380516 30 0.0 0 VERTEX 5 FED 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.57437837669021 20 -60.33603005224103 30 0.0 0 VERTEX 5 FEE 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.53502993599994 20 -60.33925949282334 30 0.0 0 VERTEX 5 FEF 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.49614173853465 20 -60.34632429361385 30 0.0 0 VERTEX 5 FF0 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.45797014784511 20 -60.35719821267427 30 0.0 0 VERTEX 5 FF1 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.42077152748206 20 -60.37185500806635 30 0.0 0 VERTEX 5 FF2 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.38480224099627 20 -60.39026843785182 30 0.0 0 VERTEX 5 FF3 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.35088083500058 20 -60.41208625447472 30 0.0 0 VERTEX 5 FF4 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.319619957823 20 -60.43684720540474 30 0.0 0 VERTEX 5 FF5 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.29116091220803 20 -60.46436154124179 30 0.0 0 VERTEX 5 FF6 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.26564500090019 20 -60.49443951258706 30 0.0 0 VERTEX 5 FF7 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.24321352664398 20 -60.52689137003982 30 0.0 0 VERTEX 5 FF8 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.22400779218393 20 -60.56152736420061 30 0.0 0 VERTEX 5 FF9 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.20816910026453 20 -60.59815774566965 30 0.0 0 VERTEX 5 FFA 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.19583875363031 20 -60.63659276504718 30 0.0 0 VERTEX 5 FFB 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.18729868490008 20 -60.6760451641852 30 0.0 0 VERTEX 5 FFC 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.18271509301619 20 -60.71569538716554 30 0.0 0 VERTEX 5 FFD 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.18205568020847 20 -60.75530523793316 30 0.0 0 VERTEX 5 FFE 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.18528814870674 20 -60.79463652043302 30 0.0 0 VERTEX 5 FFF 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.19238020074082 20 -60.8334510386101 30 0.0 0 VERTEX 5 1000 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.20329953854056 20 -60.87151059640935 30 0.0 0 VERTEX 5 1001 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.21801386433576 20 -60.90857699777575 30 0.0 0 VERTEX 5 1002 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.23649088035626 20 -60.94441204665426 30 0.0 0 VERTEX 5 1003 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.25830869697916 20 -60.97834085422227 30 0.0 0 VERTEX 5 1004 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.28306964790918 20 -61.009621244636 30 0.0 0 VERTEX 5 1005 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.31058398374655 20 -61.03810787792966 30 0.0 0 VERTEX 5 1006 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.3406619550915 20 -61.06365541413746 30 0.0 0 VERTEX 5 1007 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.37311381254426 20 -61.08611851329363 30 0.0 0 VERTEX 5 1008 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.40774980670505 20 -61.10535183543238 30 0.0 0 VERTEX 5 1009 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.44438018817409 20 -61.12121004058793 30 0.0 0 VERTEX 5 100A 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.48281520755162 20 -61.13354778879447 30 0.0 0 VERTEX 5 100B 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.49589412229665 20 -61.13681793802461 30 0.0 0 VERTEX 5 100C 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.50902753952885 20 -61.1396520673574 30 0.0 0 VERTEX 5 100D 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.52220536619504 20 -61.14205017679284 30 0.0 0 VERTEX 5 100E 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.53541750924203 20 -61.14401226633092 30 0.0 0 VERTEX 5 100F 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.54865387561666 20 -61.14553833597165 30 0.0 0 VERTEX 5 1010 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.56190437226574 20 -61.14662838571503 30 0.0 0 VERTEX 5 1011 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.57515890613609 20 -61.14728241556106 30 0.0 0 VERTEX 5 1012 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.58840738417453 20 -61.14750042550973 30 0.0 0 VERTEX 5 1013 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.61471021719527 20 -61.146637805898 30 0.0 0 VERTEX 5 1014 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.64086165441831 20 -61.14405533002449 30 0.0 0 VERTEX 5 1015 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.6667910444714 20 -61.13976107233174 30 0.0 0 VERTEX 5 1016 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.6924277359823 20 -61.1337631072623 30 0.0 0 VERTEX 5 1017 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.71770107757873 20 -61.12606950925872 30 0.0 0 VERTEX 5 1018 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.74254041788844 20 -61.11668835276353 30 0.0 0 VERTEX 5 1019 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.76687510553918 20 -61.10562771221929 30 0.0 0 VERTEX 5 101A 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.7906344891587 20 -61.09289566206853 30 0.0 0 VERTEX 5 101B 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.85718101668672 20 -61.04493616484066 30 0.0 0 VERTEX 5 101C 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.91121013966159 20 -60.98639914788074 30 0.0 0 VERTEX 5 101D 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.95212233072447 20 -60.91952930621587 30 0.0 0 VERTEX 5 101E 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.97931806251648 20 -60.84657133487316 30 0.0 0 VERTEX 5 101F 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.99219780767876 20 -60.76976992887972 30 0.0 0 VERTEX 5 1020 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.99016203885247 20 -60.69136978326266 30 0.0 0 VERTEX 5 1021 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.97261122867873 20 -60.61361559304908 30 0.0 0 VERTEX 5 1022 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.9389458497987 20 -60.53875205326609 30 0.0 0 VERTEX 5 1023 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.91712803317581 20 -60.50482324569808 30 0.0 0 VERTEX 5 1024 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.89236708224579 20 -60.47354285528434 30 0.0 0 VERTEX 5 1025 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.86485274640841 20 -60.44505622199068 30 0.0 0 VERTEX 5 1026 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.83477477506346 20 -60.41950868578288 30 0.0 0 VERTEX 5 1027 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.80232291761071 20 -60.39704558662671 30 0.0 0 VERTEX 5 1028 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.76768692344992 20 -60.37781226448796 30 0.0 0 VERTEX 5 1029 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.73105654198087 20 -60.36195405933243 30 0.0 0 VERTEX 5 102A 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.69262152260334 20 -60.34961631112587 30 0.0 0 VERTEX 5 102B 330 FE9 100 AcDbEntity 8 Graphics 370 0 100 AcDbVertex 100 AcDb2dVertex 10 20.69262152260334 20 -60.34961631112587 30 0.0 0 SEQEND 5 102D 330 FE9 100 AcDbEntity 8 Graphics 370 0 0 HATCH 5 102C 330 1F 100 AcDbEntity 8 Graphics 62 2 100 AcDbHatch 10 0.0 20 0.0 30 0.0 210 0.0 220 0.0 230 1.0 2 SOLID 70 1 71 0 91 1 92 1 93 64 72 1 10 20.69262152260334 20 -60.34961631112587 11 20.65343053354267 21 -60.34118221945403 72 1 10 20.65343053354267 20 -60.34118221945403 11 20.61393069705471 21 -60.33666221380516 72 1 10 20.61393069705471 20 -60.33666221380516 11 20.57437837669021 21 -60.33603005224103 72 1 10 20.57437837669021 20 -60.33603005224103 11 20.53502993599994 21 -60.33925949282334 72 1 10 20.53502993599994 20 -60.33925949282334 11 20.49614173853465 21 -60.34632429361385 72 1 10 20.49614173853465 20 -60.34632429361385 11 20.45797014784511 21 -60.35719821267427 72 1 10 20.45797014784511 20 -60.35719821267427 11 20.42077152748206 21 -60.37185500806635 72 1 10 20.42077152748206 20 -60.37185500806635 11 20.38480224099627 21 -60.39026843785182 72 1 10 20.38480224099627 20 -60.39026843785182 11 20.35088083500058 21 -60.41208625447472 72 1 10 20.35088083500058 20 -60.41208625447472 11 20.319619957823 21 -60.43684720540474 72 1 10 20.319619957823 20 -60.43684720540474 11 20.29116091220803 21 -60.46436154124179 72 1 10 20.29116091220803 20 -60.46436154124179 11 20.26564500090019 21 -60.49443951258706 72 1 10 20.26564500090019 20 -60.49443951258706 11 20.24321352664398 21 -60.52689137003982 72 1 10 20.24321352664398 20 -60.52689137003982 11 20.22400779218393 21 -60.56152736420061 72 1 10 20.22400779218393 20 -60.56152736420061 11 20.20816910026453 21 -60.59815774566965 72 1 10 20.20816910026453 20 -60.59815774566965 11 20.19583875363031 21 -60.63659276504718 72 1 10 20.19583875363031 20 -60.63659276504718 11 20.18729868490008 21 -60.6760451641852 72 1 10 20.18729868490008 20 -60.6760451641852 11 20.18271509301619 21 -60.71569538716554 72 1 10 20.18271509301619 20 -60.71569538716554 11 20.18205568020847 21 -60.75530523793316 72 1 10 20.18205568020847 20 -60.75530523793316 11 20.18528814870674 21 -60.79463652043302 72 1 10 20.18528814870674 20 -60.79463652043302 11 20.19238020074082 21 -60.8334510386101 72 1 10 20.19238020074082 20 -60.8334510386101 11 20.20329953854056 21 -60.87151059640935 72 1 10 20.20329953854056 20 -60.87151059640935 11 20.21801386433576 21 -60.90857699777575 72 1 10 20.21801386433576 20 -60.90857699777575 11 20.23649088035626 21 -60.94441204665426 72 1 10 20.23649088035626 20 -60.94441204665426 11 20.25830869697916 21 -60.97834085422227 72 1 10 20.25830869697916 20 -60.97834085422227 11 20.28306964790918 21 -61.009621244636 72 1 10 20.28306964790918 20 -61.009621244636 11 20.31058398374655 21 -61.03810787792966 72 1 10 20.31058398374655 20 -61.03810787792966 11 20.3406619550915 21 -61.06365541413746 72 1 10 20.3406619550915 20 -61.06365541413746 11 20.37311381254426 21 -61.08611851329363 72 1 10 20.37311381254426 20 -61.08611851329363 11 20.40774980670505 21 -61.10535183543238 72 1 10 20.40774980670505 20 -61.10535183543238 11 20.44438018817409 21 -61.12121004058793 72 1 10 20.44438018817409 20 -61.12121004058793 11 20.48281520755162 21 -61.13354778879447 72 1 10 20.48281520755162 20 -61.13354778879447 11 20.49589412229665 21 -61.13681793802461 72 1 10 20.49589412229665 20 -61.13681793802461 11 20.50902753952885 21 -61.1396520673574 72 1 10 20.50902753952885 20 -61.1396520673574 11 20.52220536619504 21 -61.14205017679284 72 1 10 20.52220536619504 20 -61.14205017679284 11 20.53541750924203 21 -61.14401226633092 72 1 10 20.53541750924203 20 -61.14401226633092 11 20.54865387561666 21 -61.14553833597165 72 1 10 20.54865387561666 20 -61.14553833597165 11 20.56190437226574 21 -61.14662838571503 72 1 10 20.56190437226574 20 -61.14662838571503 11 20.57515890613609 21 -61.14728241556106 72 1 10 20.57515890613609 20 -61.14728241556106 11 20.58840738417453 21 -61.14750042550973 72 1 10 20.58840738417453 20 -61.14750042550973 11 20.61471021719527 21 -61.146637805898 72 1 10 20.61471021719527 20 -61.146637805898 11 20.64086165441831 21 -61.14405533002449 72 1 10 20.64086165441831 20 -61.14405533002449 11 20.6667910444714 21 -61.13976107233174 72 1 10 20.6667910444714 20 -61.13976107233174 11 20.6924277359823 21 -61.1337631072623 72 1 10 20.6924277359823 20 -61.1337631072623 11 20.71770107757873 21 -61.12606950925872 72 1 10 20.71770107757873 20 -61.12606950925872 11 20.74254041788844 21 -61.11668835276353 72 1 10 20.74254041788844 20 -61.11668835276353 11 20.76687510553918 21 -61.10562771221929 72 1 10 20.76687510553918 20 -61.10562771221929 11 20.7906344891587 21 -61.09289566206853 72 1 10 20.7906344891587 20 -61.09289566206853 11 20.85718101668672 21 -61.04493616484066 72 1 10 20.85718101668672 20 -61.04493616484066 11 20.91121013966159 21 -60.98639914788074 72 1 10 20.91121013966159 20 -60.98639914788074 11 20.95212233072447 21 -60.91952930621587 72 1 10 20.95212233072447 20 -60.91952930621587 11 20.97931806251648 21 -60.84657133487316 72 1 10 20.97931806251648 20 -60.84657133487316 11 20.99219780767876 21 -60.76976992887972 72 1 10 20.99219780767876 20 -60.76976992887972 11 20.99016203885247 21 -60.69136978326266 72 1 10 20.99016203885247 20 -60.69136978326266 11 20.97261122867873 21 -60.61361559304908 72 1 10 20.97261122867873 20 -60.61361559304908 11 20.9389458497987 21 -60.53875205326609 72 1 10 20.9389458497987 20 -60.53875205326609 11 20.91712803317581 21 -60.50482324569808 72 1 10 20.91712803317581 20 -60.50482324569808 11 20.89236708224579 21 -60.47354285528434 72 1 10 20.89236708224579 20 -60.47354285528434 11 20.86485274640841 21 -60.44505622199068 72 1 10 20.86485274640841 20 -60.44505622199068 11 20.83477477506346 21 -60.41950868578288 72 1 10 20.83477477506346 20 -60.41950868578288 11 20.80232291761071 21 -60.39704558662671 72 1 10 20.80232291761071 20 -60.39704558662671 11 20.76768692344992 21 -60.37781226448796 72 1 10 20.76768692344992 20 -60.37781226448796 11 20.73105654198087 21 -60.36195405933243 72 1 10 20.73105654198087 20 -60.36195405933243 11 20.69262152260334 21 -60.34961631112587 97 0 75 2 76 1 98 0 0 INSERT 5 102F 330 1F 100 AcDbEntity 8 Graphics 100 AcDbBlockReference 2 block 6 10 0.0 20 0.0 30 0.0 0 INSERT 5 1115 330 1F 100 AcDbEntity 8 Graphics 100 AcDbBlockReference 2 block 7 10 0.0 20 0.0 30 0.0 0 INSERT 5 11FB 330 1F 100 AcDbEntity 8 Graphics 100 AcDbBlockReference 2 block 8 10 0.0 20 0.0 30 0.0 0 ENDSEC 0 SECTION 2 OBJECTS 0 DICTIONARY 5 C 330 0 100 AcDbDictionary 281 1 3 ACAD_GROUP 350 D 3 ACAD_LAYOUT 350 1A 3 ACAD_MATERIAL 350 3B 3 ACAD_MLEADERSTYLE 350 1219 3 ACAD_MLINESTYLE 350 17 3 ACAD_PLOTSETTINGS 350 19 3 ACAD_PLOTSTYLENAME 350 E 3 ACAD_TABLESTYLE 350 1218 3 ACAD_VISUALSTYLE 350 2A 0 SUN 5 3F 330 29 100 AcDbSun 90 1 290 0 63 7 421 16777215 40 1.0 291 1 91 2455826 92 54000000 292 0 70 2 71 256 280 1 0 DICTIONARY 5 D 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 0 DICTIONARY 5 1A 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 3 Layout1 350 1E 3 Layout2 350 26 3 Model 350 22 0 DICTIONARY 5 3B 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 3 ByBlock 350 3D 3 ByLayer 350 3C 3 Global 350 3E 0 DICTIONARY 5 1219 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 0 DICTIONARY 5 17 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 3 Standard 350 18 0 DICTIONARY 5 19 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 0 ACDBDICTIONARYWDFLT 5 E 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 3 Normal 350 F 100 AcDbDictionaryWithDefault 340 F 0 DICTIONARY 5 1218 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 0 DICTIONARY 5 2A 102 {ACAD_REACTORS 330 C 102 } 330 C 100 AcDbDictionary 281 1 3 2dWireframe 350 2F 3 3D Hidden 350 31 3 3dWireframe 350 30 3 Basic 350 32 3 Brighten 350 36 3 ColorChange 350 3A 3 Conceptual 350 34 3 Dim 350 35 3 Facepattern 350 39 3 Flat 350 2B 3 FlatWithEdges 350 2C 3 Gouraud 350 2D 3 GouraudWithEdges 350 2E 3 Linepattern 350 38 3 Realistic 350 33 3 Thicken 350 37 0 LAYOUT 5 1E 102 {ACAD_REACTORS 330 1A 102 } 330 1A 100 AcDbPlotSettings 1 2 none_device 4 6 40 0.0 41 0.0 42 0.0 43 0.0 44 0.0 45 0.0 46 0.0 47 0.0 48 0.0 49 0.0 140 0.0 141 0.0 142 1.0 143 1.0 70 688 72 0 73 0 74 5 7 75 16 76 0 77 2 78 300 147 1.0 148 0.0 149 0.0 100 AcDbLayout 1 Layout1 70 1 71 1 10 0.0 20 0.0 11 12.0 21 9.0 12 0.0 22 0.0 32 0.0 14 1.000000000000000E+20 24 1.000000000000000E+20 34 1.000000000000000E+20 15 -1.000000000000000E+20 25 -1.000000000000000E+20 35 -1.000000000000000E+20 146 0.0 13 0.0 23 0.0 33 0.0 16 1.0 26 0.0 36 0.0 17 0.0 27 1.0 37 0.0 76 0 330 1B 0 LAYOUT 5 26 102 {ACAD_REACTORS 330 1A 102 } 330 1A 100 AcDbPlotSettings 1 2 none_device 4 6 40 0.0 41 0.0 42 0.0 43 0.0 44 0.0 45 0.0 46 0.0 47 0.0 48 0.0 49 0.0 140 0.0 141 0.0 142 1.0 143 1.0 70 688 72 0 73 0 74 5 7 75 16 76 0 77 2 78 300 147 1.0 148 0.0 149 0.0 100 AcDbLayout 1 Layout2 70 1 71 2 10 0.0 20 0.0 11 0.0 21 0.0 12 0.0 22 0.0 32 0.0 14 0.0 24 0.0 34 0.0 15 0.0 25 0.0 35 0.0 146 0.0 13 0.0 23 0.0 33 0.0 16 1.0 26 0.0 36 0.0 17 0.0 27 1.0 37 0.0 76 0 330 23 0 LAYOUT 5 22 102 {ACAD_REACTORS 330 1A 102 } 330 1A 100 AcDbPlotSettings 1 2 none_device 4 6 40 0.0 41 0.0 42 0.0 43 0.0 44 0.0 45 0.0 46 0.0 47 0.0 48 0.0 49 0.0 140 0.0 141 0.0 142 1.0 143 1.0 70 1712 72 0 73 0 74 0 7 75 0 76 0 77 2 78 300 147 1.0 148 0.0 149 0.0 100 AcDbLayout 1 Model 70 1 71 0 10 0.0 20 0.0 11 12.0 21 9.0 12 0.0 22 0.0 32 0.0 14 1.000000000000000E+20 24 1.000000000000000E+20 34 1.000000000000000E+20 15 -1.000000000000000E+20 25 -1.000000000000000E+20 35 -1.000000000000000E+20 146 0.0 13 0.0 23 0.0 33 0.0 16 1.0 26 0.0 36 0.0 17 0.0 27 1.0 37 0.0 76 0 330 1F 331 29 0 MATERIAL 5 3D 102 {ACAD_REACTORS 330 3B 102 } 330 3B 100 AcDbMaterial 1 ByBlock 72 1 94 127 0 MATERIAL 5 3C 102 {ACAD_REACTORS 330 3B 102 } 330 3B 100 AcDbMaterial 1 ByLayer 72 1 94 127 0 MATERIAL 5 3E 102 {ACAD_REACTORS 330 3B 102 } 330 3B 100 AcDbMaterial 1 Global 72 1 94 127 0 MLINESTYLE 5 18 102 {ACAD_REACTORS 330 17 102 } 330 17 100 AcDbMlineStyle 2 Standard 70 0 3 62 256 51 90.0 52 90.0 71 2 49 0.5 62 256 6 BYLAYER 49 -0.5 62 256 6 BYLAYER 0 ACDBPLACEHOLDER 5 F 102 {ACAD_REACTORS 330 E 102 } 330 E 0 VISUALSTYLE 5 2F 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 2dWireframe 70 4 177 2 291 0 71 0 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 0 176 1 66 257 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 31 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 3D Hidden 70 6 177 2 291 0 71 1 176 1 72 2 176 1 73 2 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 2 176 1 91 2 176 1 64 7 176 1 65 257 176 1 75 2 176 1 175 1 176 1 42 40.0 176 1 92 0 176 1 66 257 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 3 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 30 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 3dWireframe 70 5 177 2 291 0 71 0 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 0 176 1 66 257 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 32 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Basic 70 7 177 2 291 1 71 1 176 1 72 0 176 1 73 1 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 0 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 8 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 36 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Brighten 70 12 177 2 291 1 71 2 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 8 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 50.0 176 1 173 0 176 1 0 VISUALSTYLE 5 3A 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 ColorChange 70 16 177 2 291 1 71 2 176 1 72 2 176 1 73 3 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 8 421 8421504 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 8 176 1 66 8 424 8421504 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 34 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Conceptual 70 9 177 2 291 0 71 3 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 2 176 1 91 2 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 40.0 176 1 92 8 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 3 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 35 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Dim 70 11 177 2 291 1 71 2 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 8 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 -50.0 176 1 173 0 176 1 0 VISUALSTYLE 5 39 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Facepattern 70 15 177 2 291 1 71 2 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 8 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 2B 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Flat 70 0 177 2 291 1 71 2 176 1 72 1 176 1 73 1 176 1 90 2 176 1 40 -0.6 176 1 41 30.0 176 1 62 5 63 7 421 16777215 176 1 74 0 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 8 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 13 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 2C 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 FlatWithEdges 70 1 177 2 291 1 71 2 176 1 72 1 176 1 73 1 176 1 90 2 176 1 40 -0.6 176 1 41 30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 0 176 1 66 257 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 13 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 2D 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Gouraud 70 2 177 2 291 1 71 2 176 1 72 2 176 1 73 1 176 1 90 2 176 1 40 -0.6 176 1 41 30.0 176 1 62 5 63 7 421 16777215 176 1 74 0 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 0 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 13 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 2E 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 GouraudWithEdges 70 3 177 2 291 1 71 2 176 1 72 2 176 1 73 1 176 1 90 2 176 1 40 -0.6 176 1 41 30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 0 176 1 66 257 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 13 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 38 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Linepattern 70 14 177 2 291 1 71 2 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 7 176 1 175 7 176 1 42 1.0 176 1 92 8 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 33 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Realistic 70 8 177 2 291 0 71 2 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 0 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 8 176 1 66 8 424 7895160 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 13 176 1 44 0.0 176 1 173 0 176 1 0 VISUALSTYLE 5 37 102 {ACAD_REACTORS 330 2A 102 } 330 2A 100 AcDbVisualStyle 2 Thicken 70 13 177 2 291 1 71 2 176 1 72 2 176 1 73 0 176 1 90 0 176 1 40 -0.6 176 1 41 -30.0 176 1 62 5 63 7 421 16777215 176 1 74 1 176 1 91 4 176 1 64 7 176 1 65 257 176 1 75 1 176 1 175 1 176 1 42 1.0 176 1 92 12 176 1 66 7 176 1 43 1.0 176 1 76 1 176 1 77 6 176 1 78 2 176 1 67 7 176 1 79 5 176 1 170 0 176 1 171 0 176 1 290 0 176 1 93 1 176 1 44 0.0 176 1 173 0 176 1 0 ENDSEC 0 EOF ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/.cproject ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/.mxproject ================================================ [PreviousLibFiles] LibFiles=Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h; [PreviousUsedCubeIDEFiles] SourceFiles=Core/Src/main.c;Core/Src/gpio.c;Core/Src/adc.c;Core/Src/dac.c;Core/Src/dma.c;Core/Src/tim.c;Core/Src/stm32g4xx_it.c;Core/Src/stm32g4xx_hal_msp.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;;; HeaderPath=Drivers/STM32G4xx_HAL_Driver/Inc;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32G4xx/Include;Drivers/CMSIS/Include;Core/Inc; CDefines=USE_HAL_DRIVER;STM32G431xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=8 HeaderFiles#0=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/gpio.h HeaderFiles#1=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/adc.h HeaderFiles#2=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/dac.h HeaderFiles#3=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/dma.h HeaderFiles#4=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/tim.h HeaderFiles#5=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/stm32g4xx_it.h HeaderFiles#6=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/stm32g4xx_hal_conf.h HeaderFiles#7=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc/main.h HeaderFolderListSize=1 HeaderPath#0=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Inc HeaderFiles=; SourceFileListSize=8 SourceFiles#0=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/gpio.c SourceFiles#1=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/adc.c SourceFiles#2=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/dac.c SourceFiles#3=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/dma.c SourceFiles#4=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/tim.c SourceFiles#5=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/stm32g4xx_it.c SourceFiles#6=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/stm32g4xx_hal_msp.c SourceFiles#7=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src/main.c SourceFolderListSize=1 SourcePath#0=/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/Core/Src SourceFiles=; ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/.project ================================================ 2OPFM_G431 org.eclipse.cdt.managedbuilder.core.genmakebuilder clean,full,incremental, org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder full,incremental, com.st.stm32cube.ide.mcu.MCUProjectNature com.st.stm32cube.ide.mcu.MCUCubeProjectNature org.eclipse.cdt.core.cnature com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature com.st.stm32cube.ide.mcu.MCURootProjectNature org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/.settings/language.settings.xml ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/.settings/org.eclipse.cdt.core.prefs ================================================ doxygen/doxygen_new_line_after_brief=true doxygen/doxygen_use_brief_tag=false doxygen/doxygen_use_javadoc_tags=true doxygen/doxygen_use_pre_tag=false doxygen/doxygen_use_structural_commands=false eclipse.preferences.version=1 ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/.settings/stm32cubeide.project.prefs ================================================ 66BE74F758C12D739921AEA421D593D3=5 8DF89ED150041C4CBC7CB9A9CAA90856=06E11EC06D32D2F937CB0888ADAEEC49 DC22A860405A8BF2F2C095E5B6529F12=06E11EC06D32D2F937CB0888ADAEEC49 eclipse.preferences.version=1 ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/2OPFM_G431.ioc ================================================ #MicroXplorer Configuration settings - do not modify ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1 ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_2 ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_3 ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_4 ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_15 ADC1.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_VREFINT ADC1.DMAContinuousRequests=ENABLE ADC1.EOCSelection=ADC_EOC_SEQ_CONV ADC1.ExternalTrigConv=ADC_EXTERNALTRIG_T3_TRGO ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master,EOCSelection,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,OffsetNumber-3\#ChannelRegularConversion,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,OffsetNumber-4\#ChannelRegularConversion,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,OffsetNumber-5\#ChannelRegularConversion,NbrOfConversion,DMAContinuousRequests,ExternalTrigConv ADC1.NbrOfConversion=6 ADC1.NbrOfConversionFlag=1 ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-3\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-4\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-5\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.Rank-1\#ChannelRegularConversion=2 ADC1.Rank-2\#ChannelRegularConversion=3 ADC1.Rank-3\#ChannelRegularConversion=4 ADC1.Rank-4\#ChannelRegularConversion=5 ADC1.Rank-5\#ChannelRegularConversion=6 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5 ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5 ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_92CYCLES_5 ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5 ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5 ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_247CYCLES_5 ADC1.master=1 ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3 ADC2.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_4 ADC2.DMAContinuousRequests=ENABLE ADC2.EOCSelection=ADC_EOC_SEQ_CONV ADC2.ExternalTrigConv=ADC_EXTERNALTRIG_T2_TRGO ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,NbrOfConversion,ExternalTrigConv,DMAContinuousRequests,EOCSelection ADC2.NbrOfConversion=2 ADC2.NbrOfConversionFlag=1 ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE ADC2.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE ADC2.Rank-0\#ChannelRegularConversion=1 ADC2.Rank-1\#ChannelRegularConversion=2 ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_24CYCLES_5 ADC2.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_24CYCLES_5 DAC1.DAC_Channel-DAC_OUT2=DAC_CHANNEL_2 DAC1.DAC_SignedFormat-DAC_OUT1=DISABLE DAC1.DAC_SignedFormat-DAC_OUT2=DISABLE DAC1.IPParameters=DAC_Channel-DAC_OUT2,DAC_SignedFormat-DAC_OUT1,DAC_SignedFormat-DAC_OUT2 Dma.ADC1.1.Direction=DMA_PERIPH_TO_MEMORY Dma.ADC1.1.EventEnable=DISABLE Dma.ADC1.1.Instance=DMA1_Channel2 Dma.ADC1.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.ADC1.1.MemInc=DMA_MINC_ENABLE Dma.ADC1.1.Mode=DMA_CIRCULAR Dma.ADC1.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.ADC1.1.PeriphInc=DMA_PINC_DISABLE Dma.ADC1.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING Dma.ADC1.1.Priority=DMA_PRIORITY_MEDIUM Dma.ADC1.1.RequestNumber=1 Dma.ADC1.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber Dma.ADC1.1.SignalID=NONE Dma.ADC1.1.SyncEnable=DISABLE Dma.ADC1.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.ADC1.1.SyncRequestNumber=1 Dma.ADC1.1.SyncSignalID=NONE Dma.ADC2.0.Direction=DMA_PERIPH_TO_MEMORY Dma.ADC2.0.EventEnable=DISABLE Dma.ADC2.0.Instance=DMA1_Channel1 Dma.ADC2.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.ADC2.0.MemInc=DMA_MINC_ENABLE Dma.ADC2.0.Mode=DMA_CIRCULAR Dma.ADC2.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.ADC2.0.PeriphInc=DMA_PINC_DISABLE Dma.ADC2.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING Dma.ADC2.0.Priority=DMA_PRIORITY_VERY_HIGH Dma.ADC2.0.RequestNumber=1 Dma.ADC2.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber Dma.ADC2.0.SignalID=NONE Dma.ADC2.0.SyncEnable=DISABLE Dma.ADC2.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.ADC2.0.SyncRequestNumber=1 Dma.ADC2.0.SyncSignalID=NONE Dma.Request0=ADC2 Dma.Request1=ADC1 Dma.RequestsNb=2 File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.Family=STM32G4 Mcu.IP0=ADC1 Mcu.IP1=ADC2 Mcu.IP2=DAC1 Mcu.IP3=DMA Mcu.IP4=NVIC Mcu.IP5=RCC Mcu.IP6=SYS Mcu.IP7=TIM2 Mcu.IP8=TIM3 Mcu.IPNb=9 Mcu.Name=STM32G431K(6-8-B)Ux Mcu.Package=UFQFPN32 Mcu.Pin0=PA0 Mcu.Pin1=PA1 Mcu.Pin10=PB7 Mcu.Pin11=VP_ADC1_Vref_Input Mcu.Pin12=VP_SYS_VS_Systick Mcu.Pin13=VP_SYS_VS_DBSignals Mcu.Pin14=VP_TIM2_VS_ClockSourceINT Mcu.Pin15=VP_TIM3_VS_ClockSourceINT Mcu.Pin2=PA2 Mcu.Pin3=PA3 Mcu.Pin4=PA4 Mcu.Pin5=PA5 Mcu.Pin6=PA6 Mcu.Pin7=PA7 Mcu.Pin8=PB0 Mcu.Pin9=PB3 Mcu.PinsNb=16 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32G431KBUx MxCube.Version=6.4.0 MxDb.Version=DB.6.0.40 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.ForceEnableDMAVector=false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.TIM3_IRQn=true\:1\:0\:true\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA0.Locked=true PA0.Mode=IN1-Single-Ended PA0.Signal=ADC1_IN1 PA1.Locked=true PA1.Mode=IN2-Single-Ended PA1.Signal=ADC1_IN2 PA2.Locked=true PA2.Mode=IN3-Single-Ended PA2.Signal=ADC1_IN3 PA3.Locked=true PA3.Mode=IN4-Single-Ended PA3.Signal=ADC1_IN4 PA4.Locked=true PA4.Signal=COMP_DAC11_group PA5.Locked=true PA5.Signal=COMP_DAC12_group PA6.Locked=true PA6.Mode=IN3-Single-Ended PA6.Signal=ADC2_IN3 PA7.Locked=true PA7.Mode=IN4-Single-Ended PA7.Signal=ADC2_IN4 PB0.Locked=true PB0.Mode=IN15-Single-Ended PB0.Signal=ADC1_IN15 PB3.GPIOParameters=GPIO_PuPd,GPIO_Label PB3.GPIO_Label=TRIG PB3.GPIO_PuPd=GPIO_PULLUP PB3.Locked=true PB3.Signal=GPIO_Input PB7.GPIOParameters=GPIO_PuPd,GPIO_Label PB7.GPIO_Label=VOCT_JUMPER PB7.GPIO_PuPd=GPIO_PULLUP PB7.Locked=true PB7.Signal=GPIO_Input PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=true ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32G431KBUx ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.2 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x0 ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Core/Src ProjectManager.NoMain=false ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=2OPFM_G431.ioc ProjectManager.ProjectName=2OPFM_G431 ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_DAC1_Init-DAC1-false-HAL-true,7-MX_TIM2_Init-TIM2-false-HAL-true,8-MX_TIM3_Init-TIM3-false-HAL-true RCC.ADC12Freq_Value=64000000 RCC.AHBFreq_Value=64000000 RCC.APB1Freq_Value=64000000 RCC.APB1TimFreq_Value=64000000 RCC.APB2Freq_Value=64000000 RCC.APB2TimFreq_Value=64000000 RCC.CRSFreq_Value=48000000 RCC.CortexFreq_Value=64000000 RCC.EXTERNAL_CLOCK_VALUE=12288000 RCC.FCLKCortexFreq_Value=64000000 RCC.FDCANFreq_Value=64000000 RCC.FamilyName=M RCC.HCLKFreq_Value=64000000 RCC.HSE_VALUE=8000000 RCC.HSI48_VALUE=48000000 RCC.HSI_VALUE=16000000 RCC.I2C1Freq_Value=64000000 RCC.I2C2Freq_Value=64000000 RCC.I2C3Freq_Value=64000000 RCC.I2SFreq_Value=64000000 RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USART2Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value RCC.LPTIM1Freq_Value=64000000 RCC.LPUART1Freq_Value=64000000 RCC.LSCOPinFreq_Value=32000 RCC.LSE_VALUE=32768 RCC.LSI_VALUE=32000 RCC.MCO1PinFreq_Value=16000000 RCC.PLLPoutputFreq_Value=64000000 RCC.PLLQoutputFreq_Value=64000000 RCC.PLLRCLKFreq_Value=64000000 RCC.PWRFreq_Value=64000000 RCC.RNGFreq_Value=64000000 RCC.SAI1Freq_Value=64000000 RCC.SYSCLKFreq_VALUE=64000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.USART1Freq_Value=64000000 RCC.USART2Freq_Value=64000000 RCC.USBFreq_Value=64000000 RCC.VCOInputFreq_Value=16000000 RCC.VCOOutputFreq_Value=128000000 SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1 SH.COMP_DAC11_group.ConfNb=1 SH.COMP_DAC12_group.0=DAC1_OUT2,DAC_OUT2 SH.COMP_DAC12_group.ConfNb=1 TIM2.IPParameters=PeriodNoDither,TIM_MasterOutputTrigger TIM2.PeriodNoDither=1600 TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM3.IPParameters=PeriodNoDither,TIM_MasterOutputTrigger TIM3.PeriodNoDither=12800 TIM3.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE VP_ADC1_Vref_Input.Mode=IN-Vrefint VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT VP_TIM3_VS_ClockSourceINT.Mode=Internal VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT board=custom isbadioc=false ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/2OPFM_G431.launch ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Inc/2op_main.h ================================================ /* * 2op_main.h * * Created on: Jun 4, 2020 * Author: SUPER */ #ifndef INC_2OP_MAIN_H_ #define INC_2OP_MAIN_H_ #include "main.h" //***************************************************************************************** uint16_t expo_lut[1024]; typedef enum { ATTACK, DECAY, RELEASE, OFF, RETRIG } envelope_stage; typedef struct { volatile float output; volatile envelope_stage stage; volatile float rate; volatile float rate_offset; volatile float attack_offset; volatile float release_offset; volatile float cutoff; volatile float target; volatile float attack; volatile float decay; volatile float sustain; volatile float release; volatile char one_shot; volatile uint8_t gate; volatile uint8_t trig; } soft_adsr; void adsr_structinit(soft_adsr* adsr); void run_adsr(soft_adsr* adsr); void run_ar(soft_adsr* adsr); //************************************************************************************************ //#define ONLY_ONE_SHOTS #define SMOOTH_ATTACK #define SMOOTH_ATTACK_INCREMENT 0.1f #define ENV_INIT 1.0f #define KHZ_PRE_FILTER float noise_offset; typedef struct { //uint is cool! int32_t output; float amplitude; float frequency; uint32_t phase_increment; uint32_t phase_index; //uint is cool! int32_t modulation; soft_adsr ADSR; } Operator; float filtered_decay_jack; float decay_sum; float ENV_AMT; float ENV_OFFSET; int32_t output, voice1, voice2; float env_lowpass; uint32_t dummy; //int32_t freqSum; float freqSum; float khz_pot; float khz_in; float filtered_khz_in; uint8_t note; float fm_ratio; uint8_t trig, last_trig; float env_lp; Operator OP1, OP2; uint32_t operator_run(Operator *OP, float envelope); void operator_structinit(Operator *OP); void check_gate(); void check_trig(); void set_adsr_parameters(soft_adsr *adsr); void slow_2op_parameter_loop(); int16_t tanh_table[256]; void tanh_table_init(); void main_2OP_loop(); //todo needs to run in slow loop // run_ar(&OP1.ADSR); #endif /* INC_2OP_MAIN_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Inc/big_sine_wave.h ================================================ /* * big_sine_wave.h * * Created on: Mar 31, 2020 * Author: SUPER */ #ifndef BIG_SINE_WAVE_H_ #define BIG_SINE_WAVE_H_ #include "main.h" static const uint16_t big_sine_wave[1024] = { 32768, 32969, 33170, 33371, 33572, 33773, 33974, 34174, 34375, 34576, 34777, 34977, 35178, 35378, 35579, 35779, 35979, 36179, 36379, 36579, 36779, 36978, 37177, 37377, 37575, 37774, 37973, 38171, 38369, 38567, 38765, 38963, 39160, 39357, 39554, 39751, 39947, 40143, 40339, 40534, 40729, 40924, 41119, 41313, 41507, 41701, 41894, 42087, 42279, 42472, 42663, 42855, 43046, 43237, 43427, 43617, 43807, 43996, 44184, 44373, 44560, 44748, 44935, 45121, 45307, 45493, 45678, 45862, 46046, 46230, 46413, 46595, 46777, 46959, 47140, 47320, 47500, 47679, 47858, 48036, 48214, 48391, 48567, 48743, 48919, 49093, 49267, 49441, 49613, 49785, 49957, 50128, 50298, 50468, 50636, 50805, 50972, 51139, 51305, 51471, 51635, 51799, 51963, 52125, 52287, 52448, 52609, 52768, 52927, 53085, 53243, 53399, 53555, 53710, 53864, 54018, 54170, 54322, 54473, 54623, 54773, 54921, 55069, 55216, 55362, 55507, 55652, 55795, 55938, 56079, 56220, 56360, 56499, 56637, 56775, 56911, 57047, 57181, 57315, 57448, 57579, 57710, 57840, 57969, 58097, 58224, 58350, 58475, 58600, 58723, 58845, 58966, 59087, 59206, 59324, 59441, 59558, 59673, 59787, 59900, 60013, 60124, 60234, 60343, 60451, 60558, 60664, 60769, 60873, 60976, 61078, 61178, 61278, 61377, 61474, 61571, 61666, 61760, 61853, 61945, 62036, 62126, 62215, 62302, 62389, 62474, 62559, 62642, 62724, 62805, 62885, 62963, 63041, 63117, 63192, 63266, 63339, 63411, 63482, 63551, 63620, 63687, 63753, 63818, 63881, 63944, 64005, 64065, 64124, 64182, 64238, 64294, 64348, 64401, 64453, 64504, 64553, 64601, 64648, 64694, 64739, 64782, 64825, 64866, 64905, 64944, 64981, 65018, 65053, 65086, 65119, 65150, 65180, 65209, 65237, 65263, 65289, 65313, 65335, 65357, 65377, 65396, 65414, 65431, 65446, 65460, 65473, 65485, 65496, 65505, 65513, 65520, 65525, 65529, 65533, 65534, 65535, 65534, 65533, 65529, 65525, 65520, 65513, 65505, 65496, 65485, 65473, 65460, 65446, 65431, 65414, 65396, 65377, 65357, 65335, 65313, 65289, 65263, 65237, 65209, 65180, 65150, 65119, 65086, 65053, 65018, 64981, 64944, 64905, 64866, 64825, 64782, 64739, 64694, 64648, 64601, 64553, 64504, 64453, 64401, 64348, 64294, 64238, 64182, 64124, 64065, 64005, 63944, 63881, 63818, 63753, 63687, 63620, 63551, 63482, 63411, 63339, 63266, 63192, 63117, 63041, 62963, 62885, 62805, 62724, 62642, 62559, 62474, 62389, 62302, 62215, 62126, 62036, 61945, 61853, 61760, 61666, 61571, 61474, 61377, 61278, 61178, 61078, 60976, 60873, 60769, 60664, 60558, 60451, 60343, 60234, 60124, 60013, 59900, 59787, 59673, 59558, 59441, 59324, 59206, 59087, 58966, 58845, 58723, 58600, 58475, 58350, 58224, 58097, 57969, 57840, 57710, 57579, 57448, 57315, 57181, 57047, 56911, 56775, 56637, 56499, 56360, 56220, 56079, 55938, 55795, 55652, 55507, 55362, 55216, 55069, 54921, 54773, 54623, 54473, 54322, 54170, 54018, 53864, 53710, 53555, 53399, 53243, 53085, 52927, 52768, 52609, 52448, 52287, 52125, 51963, 51799, 51635, 51471, 51305, 51139, 50972, 50805, 50636, 50468, 50298, 50128, 49957, 49785, 49613, 49441, 49267, 49093, 48919, 48743, 48567, 48391, 48214, 48036, 47858, 47679, 47500, 47320, 47140, 46959, 46777, 46595, 46413, 46230, 46046, 45862, 45678, 45493, 45307, 45121, 44935, 44748, 44560, 44373, 44184, 43996, 43807, 43617, 43427, 43237, 43046, 42855, 42663, 42472, 42279, 42087, 41894, 41701, 41507, 41313, 41119, 40924, 40729, 40534, 40339, 40143, 39947, 39751, 39554, 39357, 39160, 38963, 38765, 38567, 38369, 38171, 37973, 37774, 37575, 37377, 37177, 36978, 36779, 36579, 36379, 36179, 35979, 35779, 35579, 35378, 35178, 34977, 34777, 34576, 34375, 34174, 33974, 33773, 33572, 33371, 33170, 32969, 32768, 32566, 32365, 32164, 31963, 31762, 31561, 31361, 31160, 30959, 30758, 30558, 30357, 30157, 29956, 29756, 29556, 29356, 29156, 28956, 28756, 28557, 28358, 28158, 27960, 27761, 27562, 27364, 27166, 26968, 26770, 26572, 26375, 26178, 25981, 25784, 25588, 25392, 25196, 25001, 24806, 24611, 24416, 24222, 24028, 23834, 23641, 23448, 23256, 23063, 22872, 22680, 22489, 22298, 22108, 21918, 21728, 21539, 21351, 21162, 20975, 20787, 20600, 20414, 20228, 20042, 19857, 19673, 19489, 19305, 19122, 18940, 18758, 18576, 18395, 18215, 18035, 17856, 17677, 17499, 17321, 17144, 16968, 16792, 16616, 16442, 16268, 16094, 15922, 15750, 15578, 15407, 15237, 15067, 14899, 14730, 14563, 14396, 14230, 14064, 13900, 13736, 13572, 13410, 13248, 13087, 12926, 12767, 12608, 12450, 12292, 12136, 11980, 11825, 11671, 11517, 11365, 11213, 11062, 10912, 10762, 10614, 10466, 10319, 10173, 10028, 9883, 9740, 9597, 9456, 9315, 9175, 9036, 8898, 8760, 8624, 8488, 8354, 8220, 8087, 7956, 7825, 7695, 7566, 7438, 7311, 7185, 7060, 6935, 6812, 6690, 6569, 6448, 6329, 6211, 6094, 5977, 5862, 5748, 5635, 5522, 5411, 5301, 5192, 5084, 4977, 4871, 4766, 4662, 4559, 4457, 4357, 4257, 4158, 4061, 3964, 3869, 3775, 3682, 3590, 3499, 3409, 3320, 3233, 3146, 3061, 2976, 2893, 2811, 2730, 2650, 2572, 2494, 2418, 2343, 2269, 2196, 2124, 2053, 1984, 1915, 1848, 1782, 1717, 1654, 1591, 1530, 1470, 1411, 1353, 1297, 1241, 1187, 1134, 1082, 1031, 982, 934, 887, 841, 796, 753, 710, 669, 630, 591, 554, 517, 482, 449, 416, 385, 355, 326, 298, 272, 246, 222, 200, 178, 158, 139, 121, 104, 89, 75, 62, 50, 39, 30, 22, 15, 10, 6, 2, 1, 0, 1, 2, 6, 10, 15, 22, 30, 39, 50, 62, 75, 89, 104, 121, 139, 158, 178, 200, 222, 246, 272, 298, 326, 355, 385, 416, 449, 482, 517, 554, 591, 630, 669, 710, 753, 796, 841, 887, 934, 982, 1031, 1082, 1134, 1187, 1241, 1297, 1353, 1411, 1470, 1530, 1591, 1654, 1717, 1782, 1848, 1915, 1984, 2053, 2124, 2196, 2269, 2343, 2418, 2494, 2572, 2650, 2730, 2811, 2893, 2976, 3061, 3146, 3233, 3320, 3409, 3499, 3590, 3682, 3775, 3869, 3964, 4061, 4158, 4257, 4357, 4457, 4559, 4662, 4766, 4871, 4977, 5084, 5192, 5301, 5411, 5522, 5635, 5748, 5862, 5977, 6094, 6211, 6329, 6448, 6569, 6690, 6812, 6935, 7060, 7185, 7311, 7438, 7566, 7695, 7825, 7956, 8087, 8220, 8354, 8488, 8624, 8760, 8898, 9036, 9175, 9315, 9456, 9597, 9740, 9883, 10028, 10173, 10319, 10466, 10614, 10762, 10912, 11062, 11213, 11365, 11517, 11671, 11825, 11980, 12136, 12292, 12450, 12608, 12767, 12926, 13087, 13248, 13410, 13572, 13736, 13900, 14064, 14230, 14396, 14563, 14730, 14899, 15067, 15237, 15407, 15578, 15750, 15922, 16094, 16268, 16442, 16616, 16792, 16968, 17144, 17321, 17499, 17677, 17856, 18035, 18215, 18395, 18576, 18758, 18940, 19122, 19305, 19489, 19673, 19857, 20042, 20228, 20414, 20600, 20787, 20975, 21162, 21351, 21539, 21728, 21918, 22108, 22298, 22489, 22680, 22872, 23063, 23256, 23448, 23641, 23834, 24028, 24222, 24416, 24611, 24806, 25001, 25196, 25392, 25588, 25784, 25981, 26178, 26375, 26572, 26770, 26968, 27166, 27364, 27562, 27761, 27960, 28158, 28358, 28557, 28756, 28956, 29156, 29356, 29556, 29756, 29956, 30157, 30357, 30558, 30758, 30959, 31160, 31361, 31561, 31762, 31963, 32164, 32365, 32566 }; #endif /* BIG_SINE_WAVE_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Inc/dynamic_smooth.h ================================================ /* * dynamic_smooth.h * * Created on: Sep 19, 2020 * Author: SUPER */ #ifndef INC_DYNAMIC_SMOOTH_H_ #define INC_DYNAMIC_SMOOTH_H_ #include "main.h" typedef struct { //init values float g0; float sense; //tick values float low1; float low2; float low1z; float low2z; float bandz; float out; }dynamic_smooth; dynamic_smooth dynamic_smooth_a; float dynamic_smooth_tick(dynamic_smooth* _smooth, float in); void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity); #endif /* INC_DYNAMIC_SMOOTH_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Inc/global_variables.h ================================================ /* * global_variables.h * * Created on: Apr 2, 2020 * Author: SUPER */ #ifndef INC_GLOBAL_VARIABLES_H_ #define INC_GLOBAL_VARIABLES_H_ #define NUM_ADC1_CHANNELS 6 #define NUM_ADC2_CHANNELS 2 //#define VOCT #define VOCT_SCALE 0.147299349f #define WIDE_SCALE 0.25f volatile uint16_t adc1_data[NUM_ADC1_CHANNELS]; volatile uint16_t adc1_data_10b[NUM_ADC1_CHANNELS-1]; volatile uint16_t adc2_data[NUM_ADC2_CHANNELS]; volatile uint16_t VREFINT_CAL; volatile uint16_t vdd_mv; volatile uint32_t vdd_cal; volatile float khz_correction; volatile uint16_t ramp; volatile uint16_t khz_in_mv; volatile float khz_in_scaling; #endif /* INC_GLOBAL_VARIABLES_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Inc/loop.h ================================================ /* * loop.h * * Created on: Apr 2, 2020 * Author: SUPER */ #ifndef INC_LOOP_H_ #define INC_LOOP_H_ void loop(void); #endif /* INC_LOOP_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Src/2op_main.c ================================================ /* * 2op_main.c * * Created on: Jun 4, 2020 * Author: SUPER */ #include "2op_main.h" uint16_t expo_lut[1024] = { 65535, 64771, 64017, 63271, 62534, 61805, 61085, 60374, 59670, 58975, 58288, 57609, 56938, 56274, 55619, 54971, 54330, 53697, 53072, 52454, 51842, 51238, 50642, 50052, 49468, 48892, 48322, 47760, 47203, 46653, 46110, 45572, 45042, 44517, 43998, 43486, 42979, 42478, 41983, 41494, 41011, 40533, 40061, 39594, 39133, 38677, 38226, 37781, 37341, 36906, 36476, 36051, 35631, 35216, 34805, 34400, 33999, 33603, 33212, 32825, 32442, 32064, 31691, 31321, 30957, 30596, 30239, 29887, 29539, 29195, 28855, 28519, 28186, 27858, 27533, 27213, 26896, 26582, 26272, 25966, 25664, 25365, 25069, 24777, 24489, 24203, 23921, 23643, 23367, 23095, 22826, 22560, 22297, 22037, 21781, 21527, 21276, 21028, 20783, 20541, 20302, 20065, 19832, 19600, 19372, 19146, 18923, 18703, 18485, 18270, 18057, 17846, 17639, 17433, 17230, 17029, 16831, 16635, 16441, 16249, 16060, 15873, 15688, 15505, 15325, 15146, 14970, 14795, 14623, 14452, 14284, 14118, 13953, 13791, 13630, 13471, 13314, 13159, 13006, 12854, 12705, 12557, 12410, 12266, 12123, 11982, 11842, 11704, 11568, 11433, 11300, 11168, 11038, 10909, 10782, 10657, 10532, 10410, 10288, 10169, 10050, 9933, 9817, 9703, 9590, 9478, 9368, 9259, 9151, 9044, 8939, 8835, 8732, 8630, 8529, 8430, 8332, 8235, 8139, 8044, 7950, 7858, 7766, 7676, 7586, 7498, 7410, 7324, 7239, 7154, 7071, 6989, 6907, 6827, 6747, 6669, 6591, 6514, 6438, 6363, 6289, 6216, 6144, 6072, 6001, 5931, 5862, 5794, 5726, 5660, 5594, 5529, 5464, 5400, 5338, 5275, 5214, 5153, 5093, 5034, 4975, 4917, 4860, 4803, 4747, 4692, 4637, 4583, 4530, 4477, 4425, 4373, 4323, 4272, 4222, 4173, 4125, 4077, 4029, 3982, 3936, 3890, 3845, 3800, 3755, 3712, 3668, 3626, 3583, 3542, 3500, 3460, 3419, 3380, 3340, 3301, 3263, 3225, 3187, 3150, 3113, 3077, 3041, 3006, 2971, 2936, 2902, 2868, 2835, 2802, 2769, 2737, 2705, 2673, 2642, 2612, 2581, 2551, 2521, 2492, 2463, 2434, 2406, 2378, 2350, 2323, 2296, 2269, 2242, 2216, 2191, 2165, 2140, 2115, 2090, 2066, 2042, 2018, 1995, 1971, 1948, 1926, 1903, 1881, 1859, 1837, 1816, 1795, 1774, 1753, 1733, 1713, 1693, 1673, 1654, 1634, 1615, 1596, 1578, 1559, 1541, 1523, 1506, 1488, 1471, 1454, 1437, 1420, 1403, 1387, 1371, 1355, 1339, 1323, 1308, 1293, 1278, 1263, 1248, 1234, 1219, 1205, 1191, 1177, 1163, 1150, 1136, 1123, 1110, 1097, 1084, 1072, 1059, 1047, 1035, 1023, 1011, 999, 987, 976, 964, 953, 942, 931, 920, 910, 899, 889, 878, 868, 858, 848, 838, 828, 819, 809, 800, 790, 781, 772, 763, 754, 745, 737, 728, 720, 711, 703, 695, 687, 679, 671, 663, 655, 648, 640, 633, 625, 618, 611, 604, 597, 590, 583, 576, 569, 563, 556, 550, 543, 537, 531, 524, 518, 512, 506, 500, 495, 489, 483, 477, 472, 466, 461, 456, 450, 445, 440, 435, 430, 425, 420, 415, 410, 405, 400, 396, 391, 387, 382, 378, 373, 369, 365, 360, 356, 352, 348, 344, 340, 336, 332, 328, 324, 321, 317, 313, 309, 306, 302, 299, 295, 292, 288, 285, 282, 278, 275, 272, 269, 266, 263, 260, 257, 254, 251, 248, 245, 242, 239, 236, 234, 231, 228, 226, 223, 220, 218, 215, 213, 210, 208, 205, 203, 201, 198, 196, 194, 191, 189, 187, 185, 183, 181, 178, 176, 174, 172, 170, 168, 166, 164, 162, 161, 159, 157, 155, 153, 151, 150, 148, 146, 144, 143, 141, 139, 138, 136, 135, 133, 132, 130, 129, 127, 126, 124, 123, 121, 120, 118, 117, 116, 114, 113, 112, 110, 109, 108, 107, 105, 104, 103, 102, 100, 99, 98, 97, 96, 95, 94, 93, 91, 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, 79, 79, 78, 77, 76, 75, 74, 73, 72, 72, 71, 70, 69, 68, 67, 67, 66, 65, 64, 64, 63, 62, 61, 61, 60, 59, 59, 58, 57, 57, 56, 55, 55, 54, 53, 53, 52, 52, 51, 50, 50, 49, 49, 48, 47, 47, 46, 46, 45, 45, 44, 44, 43, 43, 42, 42, 41, 41, 40, 40, 39, 39, 38, 38, 38, 37, 37, 36, 36, 35, 35, 35, 34, 34, 33, 33, 33, 32, 32, 31, 31, 31, 30, 30, 30, 29, 29, 29, 28, 28, 28, 27, 27, 27, 26, 26, 26, 26, 25, 25, 25, 24, 24, 24, 23, 23, 23, 23, 22, 22, 22, 22, 21, 21, 21, 21, 20, 20, 20, 20, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; void adsr_structinit(soft_adsr *adsr) { adsr->output = ENV_INIT; adsr->attack = 0.0f; adsr->decay = 0.0f; adsr->sustain = 0.0f; adsr->release = 0.0f; adsr->stage = OFF; adsr->rate = 0.0f; adsr->rate_offset = 0.0f; adsr->cutoff = 0.0f; adsr->target = ENV_INIT; adsr->one_shot = 0; } void run_adsr(soft_adsr *adsr) { if (adsr->output < 0.01f) { adsr->one_shot = 0; } if (adsr->stage == ATTACK) { adsr->target = 1.0f; adsr->rate = adsr->attack; //attack threshold if (adsr->output > 0.9f) { adsr->stage = DECAY; } } //sustain at decay if (adsr->stage == DECAY) { adsr->rate = adsr->decay; adsr->target = adsr->sustain; if (adsr->one_shot) { if (adsr->output < (adsr->sustain + 0.01f)) { adsr->stage = RELEASE; } } } //low at release if (adsr->stage == RELEASE) { adsr->rate = adsr->release; adsr->target = 0.0f; } adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; if (adsr->cutoff > 0.99) { adsr->cutoff = 0.99; } if (adsr->cutoff < 0.0) { adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } void run_ar(soft_adsr *adsr) { if (adsr->output < 0.01f) { adsr->one_shot = 0; } if (adsr->stage == ATTACK) { adsr->target = 1.0f; adsr->rate = adsr->attack + adsr->attack_offset; //attack threshold if (adsr->one_shot) { if (adsr->output > 0.9f) { adsr->stage = RELEASE; } } } //low at release if (adsr->stage == RELEASE) { adsr->rate = adsr->release + adsr->release_offset; adsr->target = 0.0f; } adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; //adsr->cutoff = adsr->rate; if (adsr->cutoff > 0.99) { adsr->cutoff = 0.99; } if (adsr->cutoff < 0.0) { adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } void run_linear_a_expo_r(soft_adsr *adsr) { //one shot style smooth attack if (adsr->output < 0.01f) { adsr->one_shot = 0; } if (adsr->stage == ATTACK) { adsr->output += SMOOTH_ATTACK_INCREMENT; adsr->rate = adsr->attack + adsr->attack_offset; //attack threshold if (adsr->output > 0.95f) { adsr->stage = RELEASE; } } else { //low at release if (adsr->stage == RELEASE) { adsr->rate = adsr->release + adsr->release_offset; adsr->target = 0.0f; } adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; //adsr->cutoff = adsr->rate; if (adsr->cutoff > 0.99) { adsr->cutoff = 0.99; } if (adsr->cutoff < 0.0) { adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } } //***************************************************************************************************** uint32_t operator_run(Operator *OP, float envelope) { OP->phase_index += OP->phase_increment; OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; return OP->phase_index; } void operator_structinit(Operator *OP) { OP->output = 0; OP->amplitude = 1.0f; OP->frequency = 440.0f; OP->phase_increment = ((4294967295) * (OP->frequency)) / 44100.0f; } void check_trig() { //read gate trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); //if low to high transition occurs if (trig) { if (!last_trig) { //set stage to attack #ifdef ONLY_ONE_SHOTS OP1.phase_index = 0; OP2.phase_index = 0; OP1.ADSR.output = 1.0f; OP1.ADSR.stage = RELEASE; OP1.ADSR.one_shot = 0; #else //OP1.phase_index = 0; //OP2.phase_index = 0; OP1.ADSR.stage = ATTACK; //OP1.ADSR.output = 1.0f; OP1.ADSR.one_shot = 0; #endif } } last_trig = trig; } void set_adsr_parameters(soft_adsr *adsr) { adsr->rate_offset = 0.0005f; adsr->attack = 7.0f; filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; int16_t jin_offset; jin_offset = adc1_data_10b[DECAY_SLIDER] - (adc1_data_10b[DECAY_JACK] - 495); if (jin_offset < 0) { jin_offset = 0; } if (jin_offset > 1023) { jin_offset = 1023; } decay_sum = expo_lut[jin_offset] + 100.0f; adsr->release = (decay_sum) / 100000.0f; } //fast interrupt for audio void main_2OP_loop() { check_trig(); ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; if (ENV_AMT < 0.0f) { ENV_AMT = 0.0f; } //khz pot, 1p filter khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; //khz input, 1p filter filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; //khz input, 2p adaptive filter khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; //filter the sum freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; //filtered fm ratio fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); if (adc1_data_10b[DECAY_SLIDER] > 1000) { OP1.ADSR.output = 1.0f; } operator_run(&OP1, OP1.ADSR.output); operator_run(&OP2, OP1.ADSR.output * OP1.ADSR.output); OP1.modulation = (OP2.output) >> 3; //original voice1 = (OP1.output) >> 5; output = voice1; //hard clipping if (output > 2047) { output = 2047; } if (output < -2047) { output = -2047; } //DAC output HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, output + 2048); } ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Src/dynamic_smooth.c ================================================ /* * dynamic_smooth.c * * Created on: Sep 19, 2020 * Author: SUPER */ #include "dynamic_smooth.h" float cm_min(float a, float b) { return ((a) < (b) ? a : b); } float cm_abs(float a) { if (a < 0.000f) { return a*-1.0; } else { return a; } } void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity) { float basefreq, sensitivity, wc, gc; //init values basefreq = _base; sensitivity = _sensitivity; wc = basefreq / 22050.0f; //gc = tan(3.14f * wc); gc = .00000712018209f; _smooth->g0 = 2*gc/(1+gc); _smooth->sense = sensitivity * 4.0f; //tick values _smooth->low1 = 0.0f; _smooth->low2 = 0.0f; _smooth->low1z = 0.0f; _smooth->low2z = 0.0f; _smooth->bandz = 0.0f; _smooth->out = 0.0f; } float dynamic_smooth_tick(dynamic_smooth* _smooth, float in) { float g; _smooth->low1z = _smooth->low1; _smooth->low2z = _smooth->low2; _smooth->bandz = _smooth->low2z - _smooth->low1z; g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); return _smooth->low2; } ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/App/Src/loop.c ================================================ /* * loop.c * * Created on: Apr 2, 2020 * Author: SUPER */ #include "loop.h" #include "main.h" void loop(void) { } ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/adc.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file adc.h * @brief This file contains all the function prototypes for * the adc.c file ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __ADC_H__ #define __ADC_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc2; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_ADC1_Init(void); void MX_ADC2_Init(void); /* USER CODE BEGIN Prototypes */ void ADC_Start(); /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __ADC_H__ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/dac.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dac.h * @brief This file contains all the function prototypes for * the dac.c file ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __DAC_H__ #define __DAC_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern DAC_HandleTypeDef hdac1; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_DAC1_Init(void); /* USER CODE BEGIN Prototypes */ void DAC_Start(); /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __DAC_H__ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/dma.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dma.h * @brief This file contains all the function prototypes for * the dma.c file ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __DMA_H__ #define __DMA_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* DMA memory to memory transfer handles -------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_DMA_Init(void); /* USER CODE BEGIN Prototypes */ /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __DMA_H__ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/gpio.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file gpio.h * @brief This file contains all the function prototypes for * the gpio.c file ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __GPIO_H__ #define __GPIO_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_GPIO_Init(void); /* USER CODE BEGIN Prototypes */ /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /*__ GPIO_H__ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/main.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.h * @brief : Header for main.c file. * This file contains the common defines of the application. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MAIN_H #define __MAIN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #include "loop.h" #include "global_variables.h" #include "big_sine_wave.h" #include "dac.h" #include "dynamic_smooth.h" #include "2op_main.h" /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ /* USER CODE BEGIN ET */ /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ /* USER CODE BEGIN EC */ /* USER CODE END EC */ /* Exported macro ------------------------------------------------------------*/ /* USER CODE BEGIN EM */ /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ #define TRIG_Pin GPIO_PIN_3 #define TRIG_GPIO_Port GPIOB #define VOCT_JUMPER_Pin GPIO_PIN_7 #define VOCT_JUMPER_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ #define DECAY_JACK 4 #define DECAY_SLIDER 2 #define FM_SLIDER 1 #define KHZ_POT 3 #define RATIO_POT 0 #define VREFINT_PIN 5 #define FM_JACK 1 #define KHZ_JACK 0 /* USER CODE END Private defines */ #ifdef __cplusplus } #endif #endif /* __MAIN_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/stm32g4xx_hal_conf.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_hal_conf.h * @author MCD Application Team * @brief HAL configuration file ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_CONF_H #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus extern "C" { #endif /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* ########################## Module Selection ############################## */ /** * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */ #define HAL_DAC_MODULE_ENABLED /*#define HAL_FDCAN_MODULE_ENABLED */ /*#define HAL_FMAC_MODULE_ENABLED */ /*#define HAL_HRTIM_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */ /*#define HAL_IWDG_MODULE_ENABLED */ /*#define HAL_I2C_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_RNG_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_SAI_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */ #define HAL_TIM_MODULE_ENABLED /*#define HAL_UART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED /* ########################## Register Callbacks selection ############################## */ /** * @brief This is the list of modules where register callback can be used */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U #define USE_HAL_COMP_REGISTER_CALLBACKS 0U #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U #define USE_HAL_DAC_REGISTER_CALLBACKS 0U #define USE_HAL_EXTI_REGISTER_CALLBACKS 0U #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U #define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U #define USE_HAL_I2C_REGISTER_CALLBACKS 0U #define USE_HAL_I2S_REGISTER_CALLBACKS 0U #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U #define USE_HAL_NAND_REGISTER_CALLBACKS 0U #define USE_HAL_NOR_REGISTER_CALLBACKS 0U #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U #define USE_HAL_PCD_REGISTER_CALLBACKS 0U #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U #define USE_HAL_RNG_REGISTER_CALLBACKS 0U #define USE_HAL_RTC_REGISTER_CALLBACKS 0U #define USE_HAL_SAI_REGISTER_CALLBACKS 0U #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U #define USE_HAL_SPI_REGISTER_CALLBACKS 0U #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U #define USE_HAL_TIM_REGISTER_CALLBACKS 0U #define USE_HAL_UART_REGISTER_CALLBACKS 0U #define USE_HAL_USART_REGISTER_CALLBACKS 0U #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. * This internal oscillator is mainly dedicated to provide a high precision clock to * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) #define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** * @brief External clock source for I2S and SAI peripherals * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section */ #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver * Activated: CRC code is present inside driver * Deactivated: CRC code cleaned from driver */ #define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32g4xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32g4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32g4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ #ifdef HAL_ADC_MODULE_ENABLED #include "stm32g4xx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ #ifdef HAL_COMP_MODULE_ENABLED #include "stm32g4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ #ifdef HAL_CORDIC_MODULE_ENABLED #include "stm32g4xx_hal_cordic.h" #endif /* HAL_CORDIC_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED #include "stm32g4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED #include "stm32g4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED #include "stm32g4xx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ #ifdef HAL_EXTI_MODULE_ENABLED #include "stm32g4xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ #ifdef HAL_FDCAN_MODULE_ENABLED #include "stm32g4xx_hal_fdcan.h" #endif /* HAL_FDCAN_MODULE_ENABLED */ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32g4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_FMAC_MODULE_ENABLED #include "stm32g4xx_hal_fmac.h" #endif /* HAL_FMAC_MODULE_ENABLED */ #ifdef HAL_HRTIM_MODULE_ENABLED #include "stm32g4xx_hal_hrtim.h" #endif /* HAL_HRTIM_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED #include "stm32g4xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED #include "stm32g4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED #include "stm32g4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_I2S_MODULE_ENABLED #include "stm32g4xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32g4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ #ifdef HAL_NAND_MODULE_ENABLED #include "stm32g4xx_hal_nand.h" #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_NOR_MODULE_ENABLED #include "stm32g4xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32g4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED #include "stm32g4xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED #include "stm32g4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_QSPI_MODULE_ENABLED #include "stm32g4xx_hal_qspi.h" #endif /* HAL_QSPI_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED #include "stm32g4xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED #include "stm32g4xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED #include "stm32g4xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED #include "stm32g4xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED #include "stm32g4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED #include "stm32g4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32g4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED #include "stm32g4xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED #include "stm32g4xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED #include "stm32g4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED #include "stm32g4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_CONF_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/stm32g4xx_it.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_it.h * @brief This file contains the headers of the interrupt handlers. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_IT_H #define __STM32G4xx_IT_H #ifdef __cplusplus extern "C" { #endif /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ /* USER CODE BEGIN ET */ /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ /* USER CODE BEGIN EC */ /* USER CODE END EC */ /* Exported macro ------------------------------------------------------------*/ /* USER CODE BEGIN EM */ /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ void NMI_Handler(void); void HardFault_Handler(void); void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void TIM2_IRQHandler(void); void TIM3_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_IT_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Inc/tim.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file tim.h * @brief This file contains all the function prototypes for * the tim.c file ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __TIM_H__ #define __TIM_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern TIM_HandleTypeDef htim2; extern TIM_HandleTypeDef htim3; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_TIM2_Init(void); void MX_TIM3_Init(void); /* USER CODE BEGIN Prototypes */ void TIM_Start(); /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __TIM_H__ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/adc.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file adc.c * @brief This file provides code for the configuration * of the ADC instances. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "adc.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; DMA_HandleTypeDef hdma_adc1; DMA_HandleTypeDef hdma_adc2; /* ADC1 init function */ void MX_ADC1_Init(void) { /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; ADC_ChannelConfTypeDef sConfig = {0}; /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; hadc1.Init.Resolution = ADC_RESOLUTION_12B; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.GainCompensation = 0; hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; hadc1.Init.LowPowerAutoWait = DISABLE; hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.NbrOfConversion = 6; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T3_TRGO; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; hadc1.Init.DMAContinuousRequests = ENABLE; hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; hadc1.Init.OversamplingMode = DISABLE; if (HAL_ADC_Init(&hadc1) != HAL_OK) { Error_Handler(); } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; sConfig.Rank = ADC_REGULAR_RANK_2; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; sConfig.Rank = ADC_REGULAR_RANK_3; sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; sConfig.Rank = ADC_REGULAR_RANK_4; sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; sConfig.Rank = ADC_REGULAR_RANK_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; sConfig.Rank = ADC_REGULAR_RANK_6; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } /* ADC2 init function */ void MX_ADC2_Init(void) { /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; /* USER CODE BEGIN ADC2_Init 1 */ /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; hadc2.Init.Resolution = ADC_RESOLUTION_12B; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.GainCompensation = 0; hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; hadc2.Init.LowPowerAutoWait = DISABLE; hadc2.Init.ContinuousConvMode = DISABLE; hadc2.Init.NbrOfConversion = 2; hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; hadc2.Init.DMAContinuousRequests = ENABLE; hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; hadc2.Init.OversamplingMode = DISABLE; if (HAL_ADC_Init(&hadc2) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_24CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; sConfig.Rank = ADC_REGULAR_RANK_2; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0; void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; if(adcHandle->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } /* ADC1 clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; if(HAL_RCC_ADC12_CLK_ENABLED==1){ __HAL_RCC_ADC12_CLK_ENABLE(); } __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /**ADC1 GPIO Configuration PA0 ------> ADC1_IN1 PA1 ------> ADC1_IN2 PA2 ------> ADC1_IN3 PA3 ------> ADC1_IN4 PB0 ------> ADC1_IN15 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel2; hdma_adc1.Init.Request = DMA_REQUEST_ADC1; hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_adc1.Init.Mode = DMA_CIRCULAR; hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) { Error_Handler(); } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } else if(adcHandle->Instance==ADC2) { /* USER CODE BEGIN ADC2_MspInit 0 */ /* USER CODE END ADC2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } /* ADC2 clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; if(HAL_RCC_ADC12_CLK_ENABLED==1){ __HAL_RCC_ADC12_CLK_ENABLE(); } __HAL_RCC_GPIOA_CLK_ENABLE(); /**ADC2 GPIO Configuration PA6 ------> ADC2_IN3 PA7 ------> ADC2_IN4 */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* ADC2 DMA Init */ /* ADC2 Init */ hdma_adc2.Instance = DMA1_Channel1; hdma_adc2.Init.Request = DMA_REQUEST_ADC2; hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_adc2.Init.Mode = DMA_CIRCULAR; hdma_adc2.Init.Priority = DMA_PRIORITY_VERY_HIGH; if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) { Error_Handler(); } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc2); /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) { if(adcHandle->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspDeInit 0 */ /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC12_CLK_ENABLED--; if(HAL_RCC_ADC12_CLK_ENABLED==0){ __HAL_RCC_ADC12_CLK_DISABLE(); } /**ADC1 GPIO Configuration PA0 ------> ADC1_IN1 PA1 ------> ADC1_IN2 PA2 ------> ADC1_IN3 PA3 ------> ADC1_IN4 PB0 ------> ADC1_IN15 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0); /* ADC1 DMA DeInit */ HAL_DMA_DeInit(adcHandle->DMA_Handle); /* USER CODE BEGIN ADC1_MspDeInit 1 */ /* USER CODE END ADC1_MspDeInit 1 */ } else if(adcHandle->Instance==ADC2) { /* USER CODE BEGIN ADC2_MspDeInit 0 */ /* USER CODE END ADC2_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC12_CLK_ENABLED--; if(HAL_RCC_ADC12_CLK_ENABLED==0){ __HAL_RCC_ADC12_CLK_DISABLE(); } /**ADC2 GPIO Configuration PA6 ------> ADC2_IN3 PA7 ------> ADC2_IN4 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6|GPIO_PIN_7); /* ADC2 DMA DeInit */ HAL_DMA_DeInit(adcHandle->DMA_Handle); /* USER CODE BEGIN ADC2_MspDeInit 1 */ /* USER CODE END ADC2_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void ADC_Start() { if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED) != HAL_OK) { // Calibration Error Error_Handler(); } if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED) != HAL_OK) { // Calibration Error Error_Handler(); } HAL_ADC_Start_DMA(&hadc1, (uint32_t*) adc1_data, NUM_ADC1_CHANNELS); HAL_ADC_Start_DMA(&hadc2, (uint32_t*) adc2_data, NUM_ADC2_CHANNELS); } /* USER CODE END 1 */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/dac.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dac.c * @brief This file provides code for the configuration * of the DAC instances. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "dac.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ DAC_HandleTypeDef hdac1; /* DAC1 init function */ void MX_DAC1_Init(void) { /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; if (HAL_DAC_Init(&hdac1) != HAL_OK) { Error_Handler(); } /** DAC channel OUT1 config */ sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; sConfig.DAC_DMADoubleDataMode = DISABLE; sConfig.DAC_SignedFormat = DISABLE; sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; sConfig.DAC_Trigger = DAC_TRIGGER_NONE; sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE; sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_EXTERNAL; sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) { Error_Handler(); } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(dacHandle->Instance==DAC1) { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* DAC1 clock enable */ __HAL_RCC_DAC1_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } void HAL_DAC_MspDeInit(DAC_HandleTypeDef* dacHandle) { if(dacHandle->Instance==DAC1) { /* USER CODE BEGIN DAC1_MspDeInit 0 */ /* USER CODE END DAC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DAC1_CLK_DISABLE(); /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5); /* USER CODE BEGIN DAC1_MspDeInit 1 */ /* USER CODE END DAC1_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void DAC_Start() { HAL_DAC_Start(&hdac1, DAC_CHANNEL_1); HAL_DAC_Start(&hdac1, DAC_CHANNEL_2); HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 2047); } /* USER CODE END 1 */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/dma.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dma.c * @brief This file provides code for the configuration * of all the requested memory to memory DMA transfers. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "dma.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /*----------------------------------------------------------------------------*/ /* Configure DMA */ /*----------------------------------------------------------------------------*/ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /** * Enable DMA controller clock */ void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); } /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/gpio.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file gpio.c * @brief This file provides code for the configuration * of all used GPIO pins. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "gpio.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /*----------------------------------------------------------------------------*/ /* Configure GPIO */ /*----------------------------------------------------------------------------*/ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /** Configure pins */ void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /*Configure GPIO pins : PBPin PBPin */ GPIO_InitStruct.Pin = TRIG_Pin|VOCT_JUMPER_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); } /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/main.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "adc.h" #include "dac.h" #include "dma.h" #include "tim.h" #include "gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN PTD */ /* USER CODE END PTD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ volatile float khz_in_scaling = 0.25f; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /** * @brief The application entry point. * @retval int */ int main(void) { /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_DMA_Init(); MX_ADC1_Init(); MX_ADC2_Init(); MX_DAC1_Init(); MX_TIM2_Init(); MX_TIM3_Init(); /* USER CODE BEGIN 2 */ ADC_Start(); TIM_Start(); DAC_Start(); dynamic_smooth_init(&dynamic_smooth_a, 0.05f, 0.5f); adsr_structinit(&OP1.ADSR); VREFINT_CAL = *VREFINT_CAL_ADDR; while (adc1_data[VREFINT_PIN] == 0) { //wait for values! } for(int i=0; i<100000; i++) { vdd_mv += ((3000.0f * VREFINT_CAL / (float)(adc1_data[VREFINT_PIN])) - vdd_mv) * 0.2f; } khz_correction = 3300.0f / vdd_mv; khz_in_mv = adc2_data[KHZ_JACK] * 3300 >> 12; /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { loop(); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; RCC_OscInitStruct.PLL.PLLN = 8; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { Error_Handler(); } } /* USER CODE BEGIN 4 */ /* USER CODE END 4 */ /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { } /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. * @param file: pointer to the source file name * @param line: assert_param error line source number * @retval None */ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/stm32g4xx_hal_msp.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_hal_msp.c * @brief This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN Macro */ /* USER CODE END Macro */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* External functions --------------------------------------------------------*/ /* USER CODE BEGIN ExternalFunctions */ /* USER CODE END ExternalFunctions */ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE(); /* System interrupt init*/ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_PWREx_DisableUCPDDeadBattery(); /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/stm32g4xx_it.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_it.c * @brief Interrupt Service Routines. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "stm32g4xx_it.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #include "global_variables.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ extern TIM_HandleTypeDef htim2; extern TIM_HandleTypeDef htim3; /* USER CODE BEGIN EV */ /* USER CODE END EV */ /******************************************************************************/ /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) { } /* USER CODE END NonMaskableInt_IRQn 1 */ } /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_HardFault_IRQn 0 */ /* USER CODE END W1_HardFault_IRQn 0 */ } } /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ /* USER CODE END W1_MemoryManagement_IRQn 0 */ } } /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_BusFault_IRQn 0 */ /* USER CODE END W1_BusFault_IRQn 0 */ } } /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ /* USER CODE END W1_UsageFault_IRQn 0 */ } } /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { /* USER CODE BEGIN SVCall_IRQn 0 */ /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { /* USER CODE BEGIN DebugMonitor_IRQn 0 */ /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { /* USER CODE BEGIN PendSV_IRQn 0 */ /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ /* STM32G4xx Peripheral Interrupt Handlers */ /* Add here the Interrupt Handlers for the used peripherals. */ /* For the available peripheral interrupt handler names, */ /* please refer to the startup file (startup_stm32g4xx.s). */ /******************************************************************************/ /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { /* USER CODE BEGIN TIM2_IRQn 0 */ #if 0 /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); /* USER CODE BEGIN TIM2_IRQn 1 */ #endif if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(&htim2, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); main_2OP_loop(); } } /* USER CODE END TIM2_IRQn 1 */ } /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { /* USER CODE BEGIN TIM3_IRQn 0 */ #if 0 /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); /* USER CODE BEGIN TIM3_IRQn 1 */ #endif /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ /* USER CODE BEGIN TIM3_IRQn 1 */ if (__HAL_TIM_GET_FLAG(&htim3, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(&htim3, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(&htim3, TIM_IT_UPDATE); for (uint8_t i = 0; i < (NUM_ADC1_CHANNELS - 1); i++) { adc1_data_10b[i] = adc1_data[i] >> 2; } run_linear_a_expo_r(&OP1.ADSR); set_adsr_parameters(&OP1.ADSR); #ifndef VOCT if(HAL_GPIO_ReadPin(VOCT_JUMPER_GPIO_Port, VOCT_JUMPER_Pin) == 0) { khz_in_scaling = VOCT_SCALE; } else { khz_in_scaling = WIDE_SCALE; } #else khz_in_scaling = VOCT_SCALE; #endif } } /* USER CODE END TIM3_IRQn 1 */ } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/syscalls.c ================================================ /** ****************************************************************************** * @file syscalls.c * @author Auto-generated by STM32CubeIDE * @brief STM32CubeIDE Minimal System calls file * * For more information about which c-functions * need which of these lowlevel functions * please consult the Newlib libc-manual ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes */ #include #include #include #include #include #include #include #include /* Variables */ extern int __io_putchar(int ch) __attribute__((weak)); extern int __io_getchar(void) __attribute__((weak)); char *__env[1] = { 0 }; char **environ = __env; /* Functions */ void initialise_monitor_handles() { } int _getpid(void) { return 1; } int _kill(int pid, int sig) { errno = EINVAL; return -1; } void _exit (int status) { _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) { *ptr++ = __io_getchar(); } return len; } __attribute__((weak)) int _write(int file, char *ptr, int len) { int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) { __io_putchar(*ptr++); } return len; } int _close(int file) { return -1; } int _fstat(int file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } int _isatty(int file) { return 1; } int _lseek(int file, int ptr, int dir) { return 0; } int _open(char *path, int flags, ...) { /* Pretend like we always fail */ return -1; } int _wait(int *status) { errno = ECHILD; return -1; } int _unlink(char *name) { errno = ENOENT; return -1; } int _times(struct tms *buf) { return -1; } int _stat(char *file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } int _link(char *old, char *new) { errno = EMLINK; return -1; } int _fork(void) { errno = EAGAIN; return -1; } int _execve(char *name, char **argv, char **env) { errno = ENOMEM; return -1; } ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/sysmem.c ================================================ /** ****************************************************************************** * @file sysmem.c * @author Generated by STM32CubeIDE * @brief STM32CubeIDE System Memory calls file * * For more information about which C functions * need which of these lowlevel functions * please consult the newlib libc manual ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes */ #include #include /** * Pointer to the current high watermark of the heap usage */ static uint8_t *__sbrk_heap_end = NULL; /** * @brief _sbrk() allocates memory to the newlib heap and is used by malloc * and others from the C library * * @verbatim * ############################################################################ * # .data # .bss # newlib heap # MSP stack # * # # # # Reserved by _Min_Stack_Size # * ############################################################################ * ^-- RAM start ^-- _end _estack, RAM end --^ * @endverbatim * * This implementation starts allocating at the '_end' linker symbol * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack * The implementation considers '_estack' linker symbol to be RAM end * NOTE: If the MSP stack, at any point during execution, grows larger than the * reserved size, please increase the '_Min_Stack_Size'. * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; const uint8_t *max_heap = (uint8_t *)stack_limit; uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) { __sbrk_heap_end = &_end; } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) { errno = ENOMEM; return (void *)-1; } prev_heap_end = __sbrk_heap_end; __sbrk_heap_end += incr; return (void *)prev_heap_end; } ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/system_stm32g4xx.c ================================================ /** ****************************************************************************** * @file system_stm32g4xx.c * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File * * This file provides two functions and one global variable to be called from * user application: * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32g4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * After each device reset the HSI (16 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to * configure the system clock before to branch to main program. * * This file configures the system clock as follows: *============================================================================= *----------------------------------------------------------------------------- * System Clock source | HSI *----------------------------------------------------------------------------- * SYSCLK(Hz) | 16000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 16000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 1 *----------------------------------------------------------------------------- * APB2 Prescaler | 1 *----------------------------------------------------------------------------- * PLL_M | 1 *----------------------------------------------------------------------------- * PLL_N | 16 *----------------------------------------------------------------------------- * PLL_P | 7 *----------------------------------------------------------------------------- * PLL_Q | 2 *----------------------------------------------------------------------------- * PLL_R | 2 *----------------------------------------------------------------------------- * Require 48MHz for RNG | Disabled *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32g4xx_system * @{ */ /** @addtogroup STM32G4xx_System_Private_Includes * @{ */ #include "stm32g4xx.h" #if !defined (HSE_VALUE) #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Defines * @{ */ /************************* Miscellaneous Configuration ************************/ /* Note: Following vector table addresses must be defined in line with linker configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ /* #define USER_VECT_TAB_ADDRESS */ #if defined(USER_VECT_TAB_ADDRESS) /*!< Uncomment the following line if you need to relocate your vector Table in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Variables * @{ */ /* The SystemCoreClock variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ uint32_t SystemCoreClock = HSI_VALUE; const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; /** * @} */ /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes * @{ */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ #endif /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value * 24 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp, pllvco, pllr, pllsource, pllm; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) { case 0x04: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; break; case 0x08: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; break; case 0x0C: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; if (pllsource == 0x02UL) /* HSI used as PLL clock source */ { pllvco = (HSI_VALUE / pllm); } else /* HSE used as PLL clock source */ { pllvco = (HSE_VALUE / pllm); } pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; SystemCoreClock = pllvco/pllr; break; default: break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } /** * @} */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Src/tim.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file tim.c * @brief This file provides code for the configuration * of the TIM instances. ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "tim.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; htim2.Init.Prescaler = 0; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 1600; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim2) != HAL_OK) { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } /* TIM3 init function */ void MX_TIM3_Init(void) { /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; htim3.Init.Prescaler = 0; htim3.Init.CounterMode = TIM_COUNTERMODE_UP; htim3.Init.Period = 12800; htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { if(tim_baseHandle->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); HAL_NVIC_EnableIRQ(TIM2_IRQn); /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } else if(tim_baseHandle->Instance==TIM3) { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 1, 0); HAL_NVIC_EnableIRQ(TIM3_IRQn); /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) { if(tim_baseHandle->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspDeInit 0 */ /* USER CODE END TIM2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM2_CLK_DISABLE(); /* TIM2 interrupt Deinit */ HAL_NVIC_DisableIRQ(TIM2_IRQn); /* USER CODE BEGIN TIM2_MspDeInit 1 */ /* USER CODE END TIM2_MspDeInit 1 */ } else if(tim_baseHandle->Instance==TIM3) { /* USER CODE BEGIN TIM3_MspDeInit 0 */ /* USER CODE END TIM3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM3_CLK_DISABLE(); /* TIM3 interrupt Deinit */ HAL_NVIC_DisableIRQ(TIM3_IRQn); /* USER CODE BEGIN TIM3_MspDeInit 1 */ /* USER CODE END TIM3_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void TIM_Start() { HAL_TIM_Base_Start_IT(&htim2); HAL_TIM_Base_Start_IT(&htim3); } /* USER CODE END 1 */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Core/Startup/startup_stm32g431kbux.s ================================================ /** ****************************************************************************** * @file startup_stm32g431xx.s * @author MCD Application Team * @brief STM32G431xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address, * - Configure the clock system * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ /* Call the clock system initialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata ldr r2, =_sidata movs r3, #0 b LoopCopyDataInit CopyDataInit: ldr r4, [r2, r3] str r4, [r0, r3] adds r3, r3, #4 LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss movs r3, #0 b LoopFillZerobss FillZerobss: str r3, [r2] adds r2, r2, #4 LoopFillZerobss: cmp r2, r4 bcc FillZerobss /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main LoopForever: b LoopForever .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex-M4. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler .word PVD_PVM_IRQHandler .word RTC_TAMP_LSECSS_IRQHandler .word RTC_WKUP_IRQHandler .word FLASH_IRQHandler .word RCC_IRQHandler .word EXTI0_IRQHandler .word EXTI1_IRQHandler .word EXTI2_IRQHandler .word EXTI3_IRQHandler .word EXTI4_IRQHandler .word DMA1_Channel1_IRQHandler .word DMA1_Channel2_IRQHandler .word DMA1_Channel3_IRQHandler .word DMA1_Channel4_IRQHandler .word DMA1_Channel5_IRQHandler .word DMA1_Channel6_IRQHandler .word 0 .word ADC1_2_IRQHandler .word USB_HP_IRQHandler .word USB_LP_IRQHandler .word FDCAN1_IT0_IRQHandler .word FDCAN1_IT1_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_TIM15_IRQHandler .word TIM1_UP_TIM16_IRQHandler .word TIM1_TRG_COM_TIM17_IRQHandler .word TIM1_CC_IRQHandler .word TIM2_IRQHandler .word TIM3_IRQHandler .word TIM4_IRQHandler .word I2C1_EV_IRQHandler .word I2C1_ER_IRQHandler .word I2C2_EV_IRQHandler .word I2C2_ER_IRQHandler .word SPI1_IRQHandler .word SPI2_IRQHandler .word USART1_IRQHandler .word USART2_IRQHandler .word USART3_IRQHandler .word EXTI15_10_IRQHandler .word RTC_Alarm_IRQHandler .word USBWakeUp_IRQHandler .word TIM8_BRK_IRQHandler .word TIM8_UP_IRQHandler .word TIM8_TRG_COM_IRQHandler .word TIM8_CC_IRQHandler .word 0 .word 0 .word LPTIM1_IRQHandler .word 0 .word SPI3_IRQHandler .word UART4_IRQHandler .word 0 .word TIM6_DAC_IRQHandler .word TIM7_IRQHandler .word DMA2_Channel1_IRQHandler .word DMA2_Channel2_IRQHandler .word DMA2_Channel3_IRQHandler .word DMA2_Channel4_IRQHandler .word DMA2_Channel5_IRQHandler .word 0 .word 0 .word UCPD1_IRQHandler .word COMP1_2_3_IRQHandler .word COMP4_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word CRS_IRQHandler .word SAI1_IRQHandler .word 0 .word 0 .word 0 .word 0 .word FPU_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word RNG_IRQHandler .word LPUART1_IRQHandler .word I2C3_EV_IRQHandler .word I2C3_ER_IRQHandler .word DMAMUX_OVR_IRQHandler .word 0 .word 0 .word DMA2_Channel6_IRQHandler .word 0 .word 0 .word CORDIC_IRQHandler .word FMAC_IRQHandler .size g_pfnVectors, .-g_pfnVectors /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_PVM_IRQHandler .thumb_set PVD_PVM_IRQHandler,Default_Handler .weak RTC_TAMP_LSECSS_IRQHandler .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler .weak USB_HP_IRQHandler .thumb_set USB_HP_IRQHandler,Default_Handler .weak USB_LP_IRQHandler .thumb_set USB_LP_IRQHandler,Default_Handler .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM15_IRQHandler .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler .weak TIM1_UP_TIM16_IRQHandler .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM17_IRQHandler .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler .weak TIM8_BRK_IRQHandler .thumb_set TIM8_BRK_IRQHandler,Default_Handler .weak TIM8_UP_IRQHandler .thumb_set TIM8_UP_IRQHandler,Default_Handler .weak TIM8_TRG_COM_IRQHandler .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Channel1_IRQHandler .thumb_set DMA2_Channel1_IRQHandler,Default_Handler .weak DMA2_Channel2_IRQHandler .thumb_set DMA2_Channel2_IRQHandler,Default_Handler .weak DMA2_Channel3_IRQHandler .thumb_set DMA2_Channel3_IRQHandler,Default_Handler .weak DMA2_Channel4_IRQHandler .thumb_set DMA2_Channel4_IRQHandler,Default_Handler .weak DMA2_Channel5_IRQHandler .thumb_set DMA2_Channel5_IRQHandler,Default_Handler .weak UCPD1_IRQHandler .thumb_set UCPD1_IRQHandler,Default_Handler .weak COMP1_2_3_IRQHandler .thumb_set COMP1_2_3_IRQHandler,Default_Handler .weak COMP4_IRQHandler .thumb_set COMP4_IRQHandler,Default_Handler .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler .weak LPUART1_IRQHandler .thumb_set LPUART1_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak DMAMUX_OVR_IRQHandler .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler .weak DMA2_Channel6_IRQHandler .thumb_set DMA2_Channel6_IRQHandler,Default_Handler .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/2OPFM_G431.list ================================================ 2OPFM_G431.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d8 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00003650 080001d8 080001d8 000101d8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000810 08003828 08003828 00013828 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08004038 08004038 00020810 2**0 CONTENTS 4 .ARM 00000000 08004038 08004038 00020810 2**0 CONTENTS 5 .preinit_array 00000000 08004038 08004038 00020810 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08004038 08004038 00014038 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 0800403c 0800403c 0001403c 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000810 20000000 08004040 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000598 20000810 08004850 00020810 2**2 ALLOC 10 ._user_heap_stack 00000400 20000da8 08004850 00020da8 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00020810 2**0 CONTENTS, READONLY 12 .debug_info 000282cf 00000000 00000000 00020840 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 000040f1 00000000 00000000 00048b0f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loc 00013303 00000000 00000000 0004cc00 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00000e50 00000000 00000000 0005ff08 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_ranges 00002658 00000000 00000000 00060d58 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 00020668 00000000 00000000 000633b0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 0001e14a 00000000 00000000 00083a18 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000d45c5 00000000 00000000 000a1b62 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000053 00000000 00000000 00176127 2**0 CONTENTS, READONLY 21 .debug_frame 00003074 00000000 00000000 0017617c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001d8 <__do_global_dtors_aux>: 80001d8: b510 push {r4, lr} 80001da: 4c05 ldr r4, [pc, #20] ; (80001f0 <__do_global_dtors_aux+0x18>) 80001dc: 7823 ldrb r3, [r4, #0] 80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16> 80001e0: 4b04 ldr r3, [pc, #16] ; (80001f4 <__do_global_dtors_aux+0x1c>) 80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12> 80001e4: 4804 ldr r0, [pc, #16] ; (80001f8 <__do_global_dtors_aux+0x20>) 80001e6: f3af 8000 nop.w 80001ea: 2301 movs r3, #1 80001ec: 7023 strb r3, [r4, #0] 80001ee: bd10 pop {r4, pc} 80001f0: 20000810 .word 0x20000810 80001f4: 00000000 .word 0x00000000 80001f8: 08003810 .word 0x08003810 080001fc : 80001fc: b508 push {r3, lr} 80001fe: 4b03 ldr r3, [pc, #12] ; (800020c ) 8000200: b11b cbz r3, 800020a 8000202: 4903 ldr r1, [pc, #12] ; (8000210 ) 8000204: 4803 ldr r0, [pc, #12] ; (8000214 ) 8000206: f3af 8000 nop.w 800020a: bd08 pop {r3, pc} 800020c: 00000000 .word 0x00000000 8000210: 20000814 .word 0x20000814 8000214: 08003810 .word 0x08003810 08000218 <__aeabi_drsub>: 8000218: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 800021c: e002 b.n 8000224 <__adddf3> 800021e: bf00 nop 08000220 <__aeabi_dsub>: 8000220: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 08000224 <__adddf3>: 8000224: b530 push {r4, r5, lr} 8000226: ea4f 0441 mov.w r4, r1, lsl #1 800022a: ea4f 0543 mov.w r5, r3, lsl #1 800022e: ea94 0f05 teq r4, r5 8000232: bf08 it eq 8000234: ea90 0f02 teqeq r0, r2 8000238: bf1f itttt ne 800023a: ea54 0c00 orrsne.w ip, r4, r0 800023e: ea55 0c02 orrsne.w ip, r5, r2 8000242: ea7f 5c64 mvnsne.w ip, r4, asr #21 8000246: ea7f 5c65 mvnsne.w ip, r5, asr #21 800024a: f000 80e2 beq.w 8000412 <__adddf3+0x1ee> 800024e: ea4f 5454 mov.w r4, r4, lsr #21 8000252: ebd4 5555 rsbs r5, r4, r5, lsr #21 8000256: bfb8 it lt 8000258: 426d neglt r5, r5 800025a: dd0c ble.n 8000276 <__adddf3+0x52> 800025c: 442c add r4, r5 800025e: ea80 0202 eor.w r2, r0, r2 8000262: ea81 0303 eor.w r3, r1, r3 8000266: ea82 0000 eor.w r0, r2, r0 800026a: ea83 0101 eor.w r1, r3, r1 800026e: ea80 0202 eor.w r2, r0, r2 8000272: ea81 0303 eor.w r3, r1, r3 8000276: 2d36 cmp r5, #54 ; 0x36 8000278: bf88 it hi 800027a: bd30 pophi {r4, r5, pc} 800027c: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000280: ea4f 3101 mov.w r1, r1, lsl #12 8000284: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000288: ea4c 3111 orr.w r1, ip, r1, lsr #12 800028c: d002 beq.n 8000294 <__adddf3+0x70> 800028e: 4240 negs r0, r0 8000290: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000294: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 8000298: ea4f 3303 mov.w r3, r3, lsl #12 800029c: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002a0: d002 beq.n 80002a8 <__adddf3+0x84> 80002a2: 4252 negs r2, r2 80002a4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002a8: ea94 0f05 teq r4, r5 80002ac: f000 80a7 beq.w 80003fe <__adddf3+0x1da> 80002b0: f1a4 0401 sub.w r4, r4, #1 80002b4: f1d5 0e20 rsbs lr, r5, #32 80002b8: db0d blt.n 80002d6 <__adddf3+0xb2> 80002ba: fa02 fc0e lsl.w ip, r2, lr 80002be: fa22 f205 lsr.w r2, r2, r5 80002c2: 1880 adds r0, r0, r2 80002c4: f141 0100 adc.w r1, r1, #0 80002c8: fa03 f20e lsl.w r2, r3, lr 80002cc: 1880 adds r0, r0, r2 80002ce: fa43 f305 asr.w r3, r3, r5 80002d2: 4159 adcs r1, r3 80002d4: e00e b.n 80002f4 <__adddf3+0xd0> 80002d6: f1a5 0520 sub.w r5, r5, #32 80002da: f10e 0e20 add.w lr, lr, #32 80002de: 2a01 cmp r2, #1 80002e0: fa03 fc0e lsl.w ip, r3, lr 80002e4: bf28 it cs 80002e6: f04c 0c02 orrcs.w ip, ip, #2 80002ea: fa43 f305 asr.w r3, r3, r5 80002ee: 18c0 adds r0, r0, r3 80002f0: eb51 71e3 adcs.w r1, r1, r3, asr #31 80002f4: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80002f8: d507 bpl.n 800030a <__adddf3+0xe6> 80002fa: f04f 0e00 mov.w lr, #0 80002fe: f1dc 0c00 rsbs ip, ip, #0 8000302: eb7e 0000 sbcs.w r0, lr, r0 8000306: eb6e 0101 sbc.w r1, lr, r1 800030a: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 800030e: d31b bcc.n 8000348 <__adddf3+0x124> 8000310: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 8000314: d30c bcc.n 8000330 <__adddf3+0x10c> 8000316: 0849 lsrs r1, r1, #1 8000318: ea5f 0030 movs.w r0, r0, rrx 800031c: ea4f 0c3c mov.w ip, ip, rrx 8000320: f104 0401 add.w r4, r4, #1 8000324: ea4f 5244 mov.w r2, r4, lsl #21 8000328: f512 0f80 cmn.w r2, #4194304 ; 0x400000 800032c: f080 809a bcs.w 8000464 <__adddf3+0x240> 8000330: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000334: bf08 it eq 8000336: ea5f 0c50 movseq.w ip, r0, lsr #1 800033a: f150 0000 adcs.w r0, r0, #0 800033e: eb41 5104 adc.w r1, r1, r4, lsl #20 8000342: ea41 0105 orr.w r1, r1, r5 8000346: bd30 pop {r4, r5, pc} 8000348: ea5f 0c4c movs.w ip, ip, lsl #1 800034c: 4140 adcs r0, r0 800034e: eb41 0101 adc.w r1, r1, r1 8000352: 3c01 subs r4, #1 8000354: bf28 it cs 8000356: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 800035a: d2e9 bcs.n 8000330 <__adddf3+0x10c> 800035c: f091 0f00 teq r1, #0 8000360: bf04 itt eq 8000362: 4601 moveq r1, r0 8000364: 2000 moveq r0, #0 8000366: fab1 f381 clz r3, r1 800036a: bf08 it eq 800036c: 3320 addeq r3, #32 800036e: f1a3 030b sub.w r3, r3, #11 8000372: f1b3 0220 subs.w r2, r3, #32 8000376: da0c bge.n 8000392 <__adddf3+0x16e> 8000378: 320c adds r2, #12 800037a: dd08 ble.n 800038e <__adddf3+0x16a> 800037c: f102 0c14 add.w ip, r2, #20 8000380: f1c2 020c rsb r2, r2, #12 8000384: fa01 f00c lsl.w r0, r1, ip 8000388: fa21 f102 lsr.w r1, r1, r2 800038c: e00c b.n 80003a8 <__adddf3+0x184> 800038e: f102 0214 add.w r2, r2, #20 8000392: bfd8 it le 8000394: f1c2 0c20 rsble ip, r2, #32 8000398: fa01 f102 lsl.w r1, r1, r2 800039c: fa20 fc0c lsr.w ip, r0, ip 80003a0: bfdc itt le 80003a2: ea41 010c orrle.w r1, r1, ip 80003a6: 4090 lslle r0, r2 80003a8: 1ae4 subs r4, r4, r3 80003aa: bfa2 ittt ge 80003ac: eb01 5104 addge.w r1, r1, r4, lsl #20 80003b0: 4329 orrge r1, r5 80003b2: bd30 popge {r4, r5, pc} 80003b4: ea6f 0404 mvn.w r4, r4 80003b8: 3c1f subs r4, #31 80003ba: da1c bge.n 80003f6 <__adddf3+0x1d2> 80003bc: 340c adds r4, #12 80003be: dc0e bgt.n 80003de <__adddf3+0x1ba> 80003c0: f104 0414 add.w r4, r4, #20 80003c4: f1c4 0220 rsb r2, r4, #32 80003c8: fa20 f004 lsr.w r0, r0, r4 80003cc: fa01 f302 lsl.w r3, r1, r2 80003d0: ea40 0003 orr.w r0, r0, r3 80003d4: fa21 f304 lsr.w r3, r1, r4 80003d8: ea45 0103 orr.w r1, r5, r3 80003dc: bd30 pop {r4, r5, pc} 80003de: f1c4 040c rsb r4, r4, #12 80003e2: f1c4 0220 rsb r2, r4, #32 80003e6: fa20 f002 lsr.w r0, r0, r2 80003ea: fa01 f304 lsl.w r3, r1, r4 80003ee: ea40 0003 orr.w r0, r0, r3 80003f2: 4629 mov r1, r5 80003f4: bd30 pop {r4, r5, pc} 80003f6: fa21 f004 lsr.w r0, r1, r4 80003fa: 4629 mov r1, r5 80003fc: bd30 pop {r4, r5, pc} 80003fe: f094 0f00 teq r4, #0 8000402: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 8000406: bf06 itte eq 8000408: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 800040c: 3401 addeq r4, #1 800040e: 3d01 subne r5, #1 8000410: e74e b.n 80002b0 <__adddf3+0x8c> 8000412: ea7f 5c64 mvns.w ip, r4, asr #21 8000416: bf18 it ne 8000418: ea7f 5c65 mvnsne.w ip, r5, asr #21 800041c: d029 beq.n 8000472 <__adddf3+0x24e> 800041e: ea94 0f05 teq r4, r5 8000422: bf08 it eq 8000424: ea90 0f02 teqeq r0, r2 8000428: d005 beq.n 8000436 <__adddf3+0x212> 800042a: ea54 0c00 orrs.w ip, r4, r0 800042e: bf04 itt eq 8000430: 4619 moveq r1, r3 8000432: 4610 moveq r0, r2 8000434: bd30 pop {r4, r5, pc} 8000436: ea91 0f03 teq r1, r3 800043a: bf1e ittt ne 800043c: 2100 movne r1, #0 800043e: 2000 movne r0, #0 8000440: bd30 popne {r4, r5, pc} 8000442: ea5f 5c54 movs.w ip, r4, lsr #21 8000446: d105 bne.n 8000454 <__adddf3+0x230> 8000448: 0040 lsls r0, r0, #1 800044a: 4149 adcs r1, r1 800044c: bf28 it cs 800044e: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 8000452: bd30 pop {r4, r5, pc} 8000454: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000458: bf3c itt cc 800045a: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 800045e: bd30 popcc {r4, r5, pc} 8000460: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000464: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000468: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 800046c: f04f 0000 mov.w r0, #0 8000470: bd30 pop {r4, r5, pc} 8000472: ea7f 5c64 mvns.w ip, r4, asr #21 8000476: bf1a itte ne 8000478: 4619 movne r1, r3 800047a: 4610 movne r0, r2 800047c: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000480: bf1c itt ne 8000482: 460b movne r3, r1 8000484: 4602 movne r2, r0 8000486: ea50 3401 orrs.w r4, r0, r1, lsl #12 800048a: bf06 itte eq 800048c: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000490: ea91 0f03 teqeq r1, r3 8000494: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 8000498: bd30 pop {r4, r5, pc} 800049a: bf00 nop 0800049c <__aeabi_ui2d>: 800049c: f090 0f00 teq r0, #0 80004a0: bf04 itt eq 80004a2: 2100 moveq r1, #0 80004a4: 4770 bxeq lr 80004a6: b530 push {r4, r5, lr} 80004a8: f44f 6480 mov.w r4, #1024 ; 0x400 80004ac: f104 0432 add.w r4, r4, #50 ; 0x32 80004b0: f04f 0500 mov.w r5, #0 80004b4: f04f 0100 mov.w r1, #0 80004b8: e750 b.n 800035c <__adddf3+0x138> 80004ba: bf00 nop 080004bc <__aeabi_i2d>: 80004bc: f090 0f00 teq r0, #0 80004c0: bf04 itt eq 80004c2: 2100 moveq r1, #0 80004c4: 4770 bxeq lr 80004c6: b530 push {r4, r5, lr} 80004c8: f44f 6480 mov.w r4, #1024 ; 0x400 80004cc: f104 0432 add.w r4, r4, #50 ; 0x32 80004d0: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 80004d4: bf48 it mi 80004d6: 4240 negmi r0, r0 80004d8: f04f 0100 mov.w r1, #0 80004dc: e73e b.n 800035c <__adddf3+0x138> 80004de: bf00 nop 080004e0 <__aeabi_f2d>: 80004e0: 0042 lsls r2, r0, #1 80004e2: ea4f 01e2 mov.w r1, r2, asr #3 80004e6: ea4f 0131 mov.w r1, r1, rrx 80004ea: ea4f 7002 mov.w r0, r2, lsl #28 80004ee: bf1f itttt ne 80004f0: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 80004f4: f093 4f7f teqne r3, #4278190080 ; 0xff000000 80004f8: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 80004fc: 4770 bxne lr 80004fe: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 8000502: bf08 it eq 8000504: 4770 bxeq lr 8000506: f093 4f7f teq r3, #4278190080 ; 0xff000000 800050a: bf04 itt eq 800050c: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000510: 4770 bxeq lr 8000512: b530 push {r4, r5, lr} 8000514: f44f 7460 mov.w r4, #896 ; 0x380 8000518: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800051c: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000520: e71c b.n 800035c <__adddf3+0x138> 8000522: bf00 nop 08000524 <__aeabi_ul2d>: 8000524: ea50 0201 orrs.w r2, r0, r1 8000528: bf08 it eq 800052a: 4770 bxeq lr 800052c: b530 push {r4, r5, lr} 800052e: f04f 0500 mov.w r5, #0 8000532: e00a b.n 800054a <__aeabi_l2d+0x16> 08000534 <__aeabi_l2d>: 8000534: ea50 0201 orrs.w r2, r0, r1 8000538: bf08 it eq 800053a: 4770 bxeq lr 800053c: b530 push {r4, r5, lr} 800053e: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 8000542: d502 bpl.n 800054a <__aeabi_l2d+0x16> 8000544: 4240 negs r0, r0 8000546: eb61 0141 sbc.w r1, r1, r1, lsl #1 800054a: f44f 6480 mov.w r4, #1024 ; 0x400 800054e: f104 0432 add.w r4, r4, #50 ; 0x32 8000552: ea5f 5c91 movs.w ip, r1, lsr #22 8000556: f43f aed8 beq.w 800030a <__adddf3+0xe6> 800055a: f04f 0203 mov.w r2, #3 800055e: ea5f 0cdc movs.w ip, ip, lsr #3 8000562: bf18 it ne 8000564: 3203 addne r2, #3 8000566: ea5f 0cdc movs.w ip, ip, lsr #3 800056a: bf18 it ne 800056c: 3203 addne r2, #3 800056e: eb02 02dc add.w r2, r2, ip, lsr #3 8000572: f1c2 0320 rsb r3, r2, #32 8000576: fa00 fc03 lsl.w ip, r0, r3 800057a: fa20 f002 lsr.w r0, r0, r2 800057e: fa01 fe03 lsl.w lr, r1, r3 8000582: ea40 000e orr.w r0, r0, lr 8000586: fa21 f102 lsr.w r1, r1, r2 800058a: 4414 add r4, r2 800058c: e6bd b.n 800030a <__adddf3+0xe6> 800058e: bf00 nop 08000590 <__gedf2>: 8000590: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 8000594: e006 b.n 80005a4 <__cmpdf2+0x4> 8000596: bf00 nop 08000598 <__ledf2>: 8000598: f04f 0c01 mov.w ip, #1 800059c: e002 b.n 80005a4 <__cmpdf2+0x4> 800059e: bf00 nop 080005a0 <__cmpdf2>: 80005a0: f04f 0c01 mov.w ip, #1 80005a4: f84d cd04 str.w ip, [sp, #-4]! 80005a8: ea4f 0c41 mov.w ip, r1, lsl #1 80005ac: ea7f 5c6c mvns.w ip, ip, asr #21 80005b0: ea4f 0c43 mov.w ip, r3, lsl #1 80005b4: bf18 it ne 80005b6: ea7f 5c6c mvnsne.w ip, ip, asr #21 80005ba: d01b beq.n 80005f4 <__cmpdf2+0x54> 80005bc: b001 add sp, #4 80005be: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80005c2: bf0c ite eq 80005c4: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 80005c8: ea91 0f03 teqne r1, r3 80005cc: bf02 ittt eq 80005ce: ea90 0f02 teqeq r0, r2 80005d2: 2000 moveq r0, #0 80005d4: 4770 bxeq lr 80005d6: f110 0f00 cmn.w r0, #0 80005da: ea91 0f03 teq r1, r3 80005de: bf58 it pl 80005e0: 4299 cmppl r1, r3 80005e2: bf08 it eq 80005e4: 4290 cmpeq r0, r2 80005e6: bf2c ite cs 80005e8: 17d8 asrcs r0, r3, #31 80005ea: ea6f 70e3 mvncc.w r0, r3, asr #31 80005ee: f040 0001 orr.w r0, r0, #1 80005f2: 4770 bx lr 80005f4: ea4f 0c41 mov.w ip, r1, lsl #1 80005f8: ea7f 5c6c mvns.w ip, ip, asr #21 80005fc: d102 bne.n 8000604 <__cmpdf2+0x64> 80005fe: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000602: d107 bne.n 8000614 <__cmpdf2+0x74> 8000604: ea4f 0c43 mov.w ip, r3, lsl #1 8000608: ea7f 5c6c mvns.w ip, ip, asr #21 800060c: d1d6 bne.n 80005bc <__cmpdf2+0x1c> 800060e: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000612: d0d3 beq.n 80005bc <__cmpdf2+0x1c> 8000614: f85d 0b04 ldr.w r0, [sp], #4 8000618: 4770 bx lr 800061a: bf00 nop 0800061c <__aeabi_cdrcmple>: 800061c: 4684 mov ip, r0 800061e: 4610 mov r0, r2 8000620: 4662 mov r2, ip 8000622: 468c mov ip, r1 8000624: 4619 mov r1, r3 8000626: 4663 mov r3, ip 8000628: e000 b.n 800062c <__aeabi_cdcmpeq> 800062a: bf00 nop 0800062c <__aeabi_cdcmpeq>: 800062c: b501 push {r0, lr} 800062e: f7ff ffb7 bl 80005a0 <__cmpdf2> 8000632: 2800 cmp r0, #0 8000634: bf48 it mi 8000636: f110 0f00 cmnmi.w r0, #0 800063a: bd01 pop {r0, pc} 0800063c <__aeabi_dcmpeq>: 800063c: f84d ed08 str.w lr, [sp, #-8]! 8000640: f7ff fff4 bl 800062c <__aeabi_cdcmpeq> 8000644: bf0c ite eq 8000646: 2001 moveq r0, #1 8000648: 2000 movne r0, #0 800064a: f85d fb08 ldr.w pc, [sp], #8 800064e: bf00 nop 08000650 <__aeabi_dcmplt>: 8000650: f84d ed08 str.w lr, [sp, #-8]! 8000654: f7ff ffea bl 800062c <__aeabi_cdcmpeq> 8000658: bf34 ite cc 800065a: 2001 movcc r0, #1 800065c: 2000 movcs r0, #0 800065e: f85d fb08 ldr.w pc, [sp], #8 8000662: bf00 nop 08000664 <__aeabi_dcmple>: 8000664: f84d ed08 str.w lr, [sp, #-8]! 8000668: f7ff ffe0 bl 800062c <__aeabi_cdcmpeq> 800066c: bf94 ite ls 800066e: 2001 movls r0, #1 8000670: 2000 movhi r0, #0 8000672: f85d fb08 ldr.w pc, [sp], #8 8000676: bf00 nop 08000678 <__aeabi_dcmpge>: 8000678: f84d ed08 str.w lr, [sp, #-8]! 800067c: f7ff ffce bl 800061c <__aeabi_cdrcmple> 8000680: bf94 ite ls 8000682: 2001 movls r0, #1 8000684: 2000 movhi r0, #0 8000686: f85d fb08 ldr.w pc, [sp], #8 800068a: bf00 nop 0800068c <__aeabi_dcmpgt>: 800068c: f84d ed08 str.w lr, [sp, #-8]! 8000690: f7ff ffc4 bl 800061c <__aeabi_cdrcmple> 8000694: bf34 ite cc 8000696: 2001 movcc r0, #1 8000698: 2000 movcs r0, #0 800069a: f85d fb08 ldr.w pc, [sp], #8 800069e: bf00 nop 080006a0 : 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; void adsr_structinit(soft_adsr *adsr) { adsr->output = ENV_INIT; adsr->attack = 0.0f; 80006a0: 2300 movs r3, #0 void adsr_structinit(soft_adsr *adsr) { 80006a2: b410 push {r4} adsr->output = ENV_INIT; 80006a4: f04f 527e mov.w r2, #1065353216 ; 0x3f800000 adsr->decay = 0.0f; adsr->sustain = 0.0f; adsr->release = 0.0f; adsr->stage = OFF; 80006a8: 2403 movs r4, #3 adsr->rate = 0.0f; adsr->rate_offset = 0.0f; adsr->cutoff = 0.0f; adsr->target = ENV_INIT; adsr->one_shot = 0; 80006aa: 2100 movs r1, #0 adsr->output = ENV_INIT; 80006ac: 6002 str r2, [r0, #0] adsr->attack = 0.0f; 80006ae: 6203 str r3, [r0, #32] adsr->decay = 0.0f; 80006b0: 6243 str r3, [r0, #36] ; 0x24 adsr->sustain = 0.0f; 80006b2: 6283 str r3, [r0, #40] ; 0x28 adsr->release = 0.0f; 80006b4: 62c3 str r3, [r0, #44] ; 0x2c adsr->stage = OFF; 80006b6: 7104 strb r4, [r0, #4] adsr->rate = 0.0f; 80006b8: 6083 str r3, [r0, #8] } 80006ba: f85d 4b04 ldr.w r4, [sp], #4 adsr->rate_offset = 0.0f; 80006be: 60c3 str r3, [r0, #12] adsr->cutoff = 0.0f; 80006c0: 6183 str r3, [r0, #24] adsr->target = ENV_INIT; 80006c2: 61c2 str r2, [r0, #28] adsr->one_shot = 0; 80006c4: f880 1030 strb.w r1, [r0, #48] ; 0x30 } 80006c8: 4770 bx lr 80006ca: bf00 nop 80006cc: 0000 movs r0, r0 ... 080006d0 : } void run_linear_a_expo_r(soft_adsr *adsr) { //one shot style smooth attack if (adsr->output < 0.01f) { 80006d0: ed90 7a00 vldr s14, [r0] 80006d4: eddf 7a36 vldr s15, [pc, #216] ; 80007b0 void run_linear_a_expo_r(soft_adsr *adsr) { 80006d8: b510 push {r4, lr} if (adsr->output < 0.01f) { 80006da: eeb4 7ae7 vcmpe.f32 s14, s15 80006de: eef1 fa10 vmrs APSR_nzcv, fpscr adsr->one_shot = 0; 80006e2: bf44 itt mi 80006e4: 2300 movmi r3, #0 80006e6: f880 3030 strbmi.w r3, [r0, #48] ; 0x30 } if (adsr->stage == ATTACK) { 80006ea: 7903 ldrb r3, [r0, #4] void run_linear_a_expo_r(soft_adsr *adsr) { 80006ec: 4604 mov r4, r0 if (adsr->stage == ATTACK) { 80006ee: b9db cbnz r3, 8000728 adsr->output += SMOOTH_ATTACK_INCREMENT; 80006f0: edd0 7a00 vldr s15, [r0] 80006f4: eddf 6a2f vldr s13, [pc, #188] ; 80007b4 adsr->rate = adsr->attack + adsr->attack_offset; //attack threshold if (adsr->output > 0.95f) { 80006f8: ed9f 7a2f vldr s14, [pc, #188] ; 80007b8 adsr->output += SMOOTH_ATTACK_INCREMENT; 80006fc: ee77 7aa6 vadd.f32 s15, s15, s13 8000700: edc0 7a00 vstr s15, [r0] adsr->rate = adsr->attack + adsr->attack_offset; 8000704: edd0 7a08 vldr s15, [r0, #32] 8000708: edd0 6a04 vldr s13, [r0, #16] 800070c: ee77 7aa6 vadd.f32 s15, s15, s13 8000710: edc0 7a02 vstr s15, [r0, #8] if (adsr->output > 0.95f) { 8000714: edd0 7a00 vldr s15, [r0] 8000718: eef4 7ac7 vcmpe.f32 s15, s14 800071c: eef1 fa10 vmrs APSR_nzcv, fpscr 8000720: dd01 ble.n 8000726 adsr->stage = RELEASE; 8000722: 2302 movs r3, #2 8000724: 7103 strb r3, [r0, #4] adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } } 8000726: bd10 pop {r4, pc} if (adsr->stage == RELEASE) { 8000728: 7903 ldrb r3, [r0, #4] 800072a: 2b02 cmp r3, #2 800072c: d02e beq.n 800078c adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; 800072e: edd4 7a02 vldr s15, [r4, #8] 8000732: edd4 6a03 vldr s13, [r4, #12] 8000736: ed9f 7a1f vldr s14, [pc, #124] ; 80007b4 800073a: ee77 7aa6 vadd.f32 s15, s15, s13 800073e: ee67 7a87 vmul.f32 s15, s15, s14 8000742: edc4 7a06 vstr s15, [r4, #24] if (adsr->cutoff > 0.99) { 8000746: 69a0 ldr r0, [r4, #24] 8000748: f7ff feca bl 80004e0 <__aeabi_f2d> 800074c: a316 add r3, pc, #88 ; (adr r3, 80007a8 ) 800074e: e9d3 2300 ldrd r2, r3, [r3] 8000752: f7ff ff9b bl 800068c <__aeabi_dcmpgt> 8000756: b108 cbz r0, 800075c adsr->cutoff = 0.99; 8000758: 4b18 ldr r3, [pc, #96] ; (80007bc ) 800075a: 61a3 str r3, [r4, #24] if (adsr->cutoff < 0.0) { 800075c: edd4 7a06 vldr s15, [r4, #24] 8000760: eef5 7ac0 vcmpe.f32 s15, #0.0 8000764: 2300 movs r3, #0 8000766: eef1 fa10 vmrs APSR_nzcv, fpscr adsr->cutoff = 0; 800076a: bf48 it mi 800076c: 61a3 strmi r3, [r4, #24] adsr->output += (adsr->target - adsr->output) * adsr->cutoff; 800076e: ed94 7a07 vldr s14, [r4, #28] 8000772: ed94 6a00 vldr s12, [r4] 8000776: edd4 6a06 vldr s13, [r4, #24] 800077a: edd4 7a00 vldr s15, [r4] 800077e: ee37 7a46 vsub.f32 s14, s14, s12 8000782: eee7 7a26 vfma.f32 s15, s14, s13 8000786: edc4 7a00 vstr s15, [r4] } 800078a: bd10 pop {r4, pc} adsr->rate = adsr->release + adsr->release_offset; 800078c: edd0 7a0b vldr s15, [r0, #44] ; 0x2c 8000790: ed90 7a05 vldr s14, [r0, #20] 8000794: ee77 7a87 vadd.f32 s15, s15, s14 adsr->target = 0.0f; 8000798: 2300 movs r3, #0 adsr->rate = adsr->release + adsr->release_offset; 800079a: edc0 7a02 vstr s15, [r0, #8] adsr->target = 0.0f; 800079e: 61c3 str r3, [r0, #28] 80007a0: e7c5 b.n 800072e 80007a2: bf00 nop 80007a4: f3af 8000 nop.w 80007a8: 7ae147ae .word 0x7ae147ae 80007ac: 3fefae14 .word 0x3fefae14 80007b0: 3c23d70a .word 0x3c23d70a 80007b4: 3dcccccd .word 0x3dcccccd 80007b8: 3f733333 .word 0x3f733333 80007bc: 3f7d70a4 .word 0x3f7d70a4 080007c0 : void set_adsr_parameters(soft_adsr *adsr) { adsr->rate_offset = 0.0005f; adsr->attack = 7.0f; filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007c0: 491b ldr r1, [pc, #108] ; (8000830 ) adsr->rate_offset = 0.0005f; 80007c2: 4a1c ldr r2, [pc, #112] ; (8000834 ) adsr->attack = 7.0f; 80007c4: 4b1c ldr r3, [pc, #112] ; (8000838 ) adsr->rate_offset = 0.0005f; 80007c6: 60c2 str r2, [r0, #12] adsr->attack = 7.0f; 80007c8: 6203 str r3, [r0, #32] filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007ca: 890a ldrh r2, [r1, #8] int16_t jin_offset; jin_offset = adc1_data_10b[DECAY_SLIDER] - (adc1_data_10b[DECAY_JACK] - 495); 80007cc: 888b ldrh r3, [r1, #4] 80007ce: 8909 ldrh r1, [r1, #8] jin_offset = 0; } if (jin_offset > 1023) { jin_offset = 1023; } decay_sum = expo_lut[jin_offset] + 100.0f; 80007d0: ed9f 5a1a vldr s10, [pc, #104] ; 800083c filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007d4: eddf 5a1a vldr s11, [pc, #104] ; 8000840 adsr->release = (decay_sum) / 100000.0f; 80007d8: ed9f 6a1a vldr s12, [pc, #104] ; 8000844 jin_offset = adc1_data_10b[DECAY_SLIDER] - (adc1_data_10b[DECAY_JACK] - 495); 80007dc: b29b uxth r3, r3 80007de: f203 13ef addw r3, r3, #495 ; 0x1ef void set_adsr_parameters(soft_adsr *adsr) { 80007e2: b430 push {r4, r5} filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007e4: b292 uxth r2, r2 80007e6: 4d18 ldr r5, [pc, #96] ; (8000848 ) 80007e8: 4c18 ldr r4, [pc, #96] ; (800084c ) 80007ea: f835 2012 ldrh.w r2, [r5, r2, lsl #1] 80007ee: edd4 6a00 vldr s13, [r4] jin_offset = adc1_data_10b[DECAY_SLIDER] - (adc1_data_10b[DECAY_JACK] - 495); 80007f2: 1a5b subs r3, r3, r1 80007f4: b21b sxth r3, r3 decay_sum = expo_lut[jin_offset] + 100.0f; 80007f6: f383 030a usat r3, #10, r3 filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007fa: ee07 2a10 vmov s14, r2 decay_sum = expo_lut[jin_offset] + 100.0f; 80007fe: f835 3013 ldrh.w r3, [r5, r3, lsl #1] filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 8000802: eeb8 7ac7 vcvt.f32.s32 s14, s14 decay_sum = expo_lut[jin_offset] + 100.0f; 8000806: ee07 3a90 vmov s15, r3 filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 800080a: ee37 7a66 vsub.f32 s14, s14, s13 decay_sum = expo_lut[jin_offset] + 100.0f; 800080e: eef8 7ae7 vcvt.f32.s32 s15, s15 filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 8000812: eee7 6a25 vfma.f32 s13, s14, s11 decay_sum = expo_lut[jin_offset] + 100.0f; 8000816: 4b0e ldr r3, [pc, #56] ; (8000850 ) 8000818: ee77 7a85 vadd.f32 s15, s15, s10 filtered_decay_jack += (expo_lut[adc1_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 800081c: edc4 6a00 vstr s13, [r4] adsr->release = (decay_sum) / 100000.0f; 8000820: ee27 7a86 vmul.f32 s14, s15, s12 } 8000824: bc30 pop {r4, r5} decay_sum = expo_lut[jin_offset] + 100.0f; 8000826: edc3 7a00 vstr s15, [r3] adsr->release = (decay_sum) / 100000.0f; 800082a: ed80 7a0b vstr s14, [r0, #44] ; 0x2c } 800082e: 4770 bx lr 8000830: 20000b54 .word 0x20000b54 8000834: 3a03126f .word 0x3a03126f 8000838: 40e00000 .word 0x40e00000 800083c: 42c80000 .word 0x42c80000 8000840: 3ca3d70a .word 0x3ca3d70a 8000844: 3727c5ac .word 0x3727c5ac 8000848: 20000000 .word 0x20000000 800084c: 20000894 .word 0x20000894 8000850: 200008b4 .word 0x200008b4 08000854 : //fast interrupt for audio void main_2OP_loop() { 8000854: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); 8000858: 2108 movs r1, #8 if (!last_trig) { 800085a: 4da1 ldr r5, [pc, #644] ; (8000ae0 ) trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); 800085c: 48a1 ldr r0, [pc, #644] ; (8000ae4 ) OP1.ADSR.stage = ATTACK; 800085e: 4ca2 ldr r4, [pc, #648] ; (8000ae8 ) check_trig(); ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 8000860: 4ea2 ldr r6, [pc, #648] ; (8000aec ) if (ENV_AMT < 0.0f) { ENV_AMT = 0.0f; } //khz pot, 1p filter khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 8000862: 4fa3 ldr r7, [pc, #652] ; (8000af0 ) trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); 8000864: f002 f850 bl 8002908 if (!last_trig) { 8000868: 7829 ldrb r1, [r5, #0] trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); 800086a: 4ba2 ldr r3, [pc, #648] ; (8000af4 ) ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 800086c: eddf 6aa2 vldr s13, [pc, #648] ; 8000af8 8000870: eddf 5aa2 vldr s11, [pc, #648] ; 8000afc ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 8000874: ed9f 6aa2 vldr s12, [pc, #648] ; 8000b00 trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); 8000878: fab0 f280 clz r2, r0 if (!last_trig) { 800087c: 4308 orrs r0, r1 800087e: f010 00ff ands.w r0, r0, #255 ; 0xff ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 8000882: 49a0 ldr r1, [pc, #640] ; (8000b04 ) OP1.ADSR.stage = ATTACK; 8000884: bf08 it eq 8000886: 7720 strbeq r0, [r4, #28] trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); 8000888: ea4f 1252 mov.w r2, r2, lsr #5 OP1.ADSR.one_shot = 0; 800088c: bf08 it eq 800088e: f884 0048 strbeq.w r0, [r4, #72] ; 0x48 trig = !HAL_GPIO_ReadPin(TRIG_GPIO_Port, TRIG_Pin); 8000892: 701a strb r2, [r3, #0] ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 8000894: 884b ldrh r3, [r1, #2] 8000896: 489c ldr r0, [pc, #624] ; (8000b08 ) last_trig = trig; 8000898: 702a strb r2, [r5, #0] ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 800089a: f3c3 038d ubfx r3, r3, #2, #14 800089e: f5c3 73e0 rsb r3, r3, #448 ; 0x1c0 80008a2: ee07 3a90 vmov s15, r3 80008a6: ed90 7a00 vldr s14, [r0] ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 80008aa: 8873 ldrh r3, [r6, #2] ENV_AMT = 0.0f; 80008ac: 4d97 ldr r5, [pc, #604] ; (8000b0c ) ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 80008ae: eef8 7ae7 vcvt.f32.s32 s15, s15 80008b2: eeb0 5a47 vmov.f32 s10, s14 80008b6: ee97 5aa6 vfnms.f32 s10, s15, s13 ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 80008ba: b29b uxth r3, r3 if (ENV_AMT < 0.0f) { 80008bc: 2200 movs r2, #0 ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 80008be: ee06 3a90 vmov s13, r3 ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 80008c2: eea5 7a25 vfma.f32 s14, s10, s11 khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008c6: 88f3 ldrh r3, [r6, #6] ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 80008c8: eef8 6ae6 vcvt.f32.s32 s13, s13 ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 80008cc: eef0 7a47 vmov.f32 s15, s14 ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 80008d0: eea6 7a86 vfma.f32 s14, s13, s12 khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008d4: b29b uxth r3, r3 80008d6: f5c3 737f rsb r3, r3, #1020 ; 0x3fc 80008da: 3303 adds r3, #3 if (ENV_AMT < 0.0f) { 80008dc: eeb5 7ac0 vcmpe.f32 s14, #0.0 80008e0: eef1 fa10 vmrs APSR_nzcv, fpscr ENV_AMT = 0.0f; 80008e4: bf48 it mi 80008e6: 602a strmi r2, [r5, #0] //khz input, 1p filter filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008e8: 880a ldrh r2, [r1, #0] ENV_AMT = (adc1_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 80008ea: bf58 it pl 80008ec: ed85 7a00 vstrpl s14, [r5] filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008f0: b292 uxth r2, r2 80008f2: f5a2 6200 sub.w r2, r2, #2048 ; 0x800 80008f6: 4986 ldr r1, [pc, #536] ; (8000b10 ) ENV_OFFSET += (((((960 - (adc2_data[FM_JACK] >> 2)) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 80008f8: edc0 7a00 vstr s15, [r0] filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008fc: ee07 2a10 vmov s14, r2 khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 8000900: ee07 3a90 vmov s15, r3 filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 8000904: ed91 0a00 vldr s0, [r1] khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 8000908: edd7 6a00 vldr s13, [r7] 800090c: ed9f 6a81 vldr s12, [pc, #516] ; 8000b14 //khz input, 2p adaptive filter khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; 8000910: 4881 ldr r0, [pc, #516] ; (8000b18 ) filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 8000912: eeb8 7ac7 vcvt.f32.s32 s14, s14 khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 8000916: eef8 7ae7 vcvt.f32.s32 s15, s15 filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 800091a: ee37 7a40 vsub.f32 s14, s14, s0 khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 800091e: ee77 7ae6 vsub.f32 s15, s15, s13 filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 8000922: eea7 0a06 vfma.f32 s0, s14, s12 khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 8000926: eee7 6a86 vfma.f32 s13, s15, s12 filtered_khz_in += ((adc2_data[0] - 2048) - filtered_khz_in) * 0.05f; 800092a: ed81 0a00 vstr s0, [r1] khz_pot += ((1023 - adc1_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 800092e: edc7 6a00 vstr s13, [r7] khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; 8000932: f000 f925 bl 8000b80 8000936: 4a79 ldr r2, [pc, #484] ; (8000b1c ) 8000938: 4b79 ldr r3, [pc, #484] ; (8000b20 ) 800093a: ed92 6a00 vldr s12, [r2] //filter the sum freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 800093e: f8df c218 ldr.w ip, [pc, #536] ; 8000b58 khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; 8000942: edd3 3a00 vldr s7, [r3] freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 8000946: eddc 6a00 vldr s13, [ip] 800094a: edd7 5a00 vldr s11, [r7] 800094e: ed9f 7a75 vldr s14, [pc, #468] ; 8000b24 //filtered fm ratio fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000952: 8833 ldrh r3, [r6, #0] 8000954: 4874 ldr r0, [pc, #464] ; (8000b28 ) 8000956: ed9f 4a75 vldr s8, [pc, #468] ; 8000b2c OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); if (adc1_data_10b[DECAY_SLIDER] > 1000) { 800095a: 88b2 ldrh r2, [r6, #4] fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 800095c: eddf 4a67 vldr s9, [pc, #412] ; 8000afc OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 8000960: 4e73 ldr r6, [pc, #460] ; (8000b30 ) OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 8000962: ed9f 5a74 vldr s10, [pc, #464] ; 8000b34 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 8000966: eddf 7a74 vldr s15, [pc, #464] ; 8000b38 OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 800096a: 4974 ldr r1, [pc, #464] ; (8000b3c ) khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; 800096c: ee26 6a23 vmul.f32 s12, s12, s7 freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 8000970: ee75 5ae6 vsub.f32 s11, s11, s13 khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; 8000974: ee26 0a00 vmul.f32 s0, s12, s0 fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000978: b29b uxth r3, r3 freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 800097a: ee75 5a80 vadd.f32 s11, s11, s0 fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 800097e: ee06 3a10 vmov s12, r3 freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 8000982: eee5 6a87 vfma.f32 s13, s11, s14 khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; 8000986: 4b6e ldr r3, [pc, #440] ; (8000b40 ) OP->phase_index += OP->phase_increment; 8000988: 690f ldr r7, [r1, #16] fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 800098a: ed90 7a00 vldr s14, [r0] freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 800098e: edcc 6a00 vstr s13, [ip] fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000992: eeb8 6ac6 vcvt.f32.s32 s12, s12 OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 8000996: eefc 6ae6 vcvt.u32.f32 s13, s13 fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 800099a: eef0 5a47 vmov.f32 s11, s14 800099e: eed6 5a04 vfnms.f32 s11, s12, s8 if (adc1_data_10b[DECAY_SLIDER] > 1000) { 80009a2: b292 uxth r2, r2 80009a4: f5b2 7f7a cmp.w r2, #1000 ; 0x3e8 khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * khz_in_scaling * khz_correction; 80009a8: ed83 0a00 vstr s0, [r3] OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 80009ac: ee16 3a90 vmov r3, s13 80009b0: f3c3 0309 ubfx r3, r3, #0, #10 fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 80009b4: eea5 7aa4 vfma.f32 s14, s11, s9 OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 80009b8: f836 3013 ldrh.w r3, [r6, r3, lsl #1] 80009bc: ee06 3a10 vmov s12, r3 fm_ratio += ((adc1_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 80009c0: ed80 7a00 vstr s14, [r0] OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 80009c4: eeb8 6a46 vcvt.f32.u32 s12, s12 OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 80009c8: ee27 7a05 vmul.f32 s14, s14, s10 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 80009cc: ee66 6a27 vmul.f32 s13, s12, s15 OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 80009d0: ee27 7a06 vmul.f32 s14, s14, s12 OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 80009d4: ed84 6a02 vstr s12, [r4, #8] OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); 80009d8: ee67 7a27 vmul.f32 s15, s14, s15 OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 80009dc: ed81 7a02 vstr s14, [r1, #8] OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); 80009e0: eefc 7ae7 vcvt.u32.f32 s15, s15 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009e4: ed95 6a00 vldr s12, [r5] OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); 80009e8: edc1 7a03 vstr s15, [r1, #12] 80009ec: ee17 0a90 vmov r0, s15 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009f0: edd4 7a05 vldr s15, [r4, #20] OP->phase_index += OP->phase_increment; 80009f4: 6925 ldr r5, [r4, #16] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009f6: eeb8 7ae7 vcvt.f32.s32 s14, s15 80009fa: edd1 7a05 vldr s15, [r1, #20] 80009fe: eef8 7ae7 vcvt.f32.s32 s15, s15 8000a02: ee27 7a06 vmul.f32 s14, s14, s12 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 8000a06: eefc 6ae6 vcvt.u32.f32 s13, s13 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a0a: ee67 7a86 vmul.f32 s15, s15, s12 8000a0e: eebd 7ac7 vcvt.s32.f32 s14, s14 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 8000a12: ee16 6a90 vmov r6, s13 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a16: eefd 7ae7 vcvt.s32.f32 s15, s15 OP1.ADSR.output = 1.0f; 8000a1a: bf88 it hi 8000a1c: f04f 537e movhi.w r3, #1065353216 ; 0x3f800000 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a20: ee17 2a10 vmov r2, s14 OP1.ADSR.output = 1.0f; 8000a24: bf88 it hi 8000a26: 61a3 strhi r3, [r4, #24] OP->phase_index += OP->phase_increment; 8000a28: 4435 add r5, r6 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a2a: ee17 3a90 vmov r3, s15 OP->phase_index += OP->phase_increment; 8000a2e: 4438 add r0, r7 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a30: eb02 5295 add.w r2, r2, r5, lsr #22 8000a34: 4e43 ldr r6, [pc, #268] ; (8000b44 ) } operator_run(&OP1, OP1.ADSR.output); 8000a36: edd4 5a06 vldr s11, [r4, #24] OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 8000a3a: edc4 6a03 vstr s13, [r4, #12] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a3e: eb03 5390 add.w r3, r3, r0, lsr #22 8000a42: f3c2 0209 ubfx r2, r2, #0, #10 8000a46: f3c3 0309 ubfx r3, r3, #0, #10 8000a4a: f836 2012 ldrh.w r2, [r6, r2, lsl #1] 8000a4e: f836 3013 ldrh.w r3, [r6, r3, lsl #1] operator_run(&OP2, OP1.ADSR.output * OP1.ADSR.output); 8000a52: edd4 6a06 vldr s13, [r4, #24] 8000a56: ed94 5a06 vldr s10, [r4, #24] OP1.modulation = (OP2.output) >> 3; //original voice1 = (OP1.output) >> 5; 8000a5a: 4e3b ldr r6, [pc, #236] ; (8000b48 ) OP->phase_index += OP->phase_increment; 8000a5c: 6108 str r0, [r1, #16] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a5e: f5a2 4200 sub.w r2, r2, #32768 ; 0x8000 8000a62: ee07 2a10 vmov s14, r2 8000a66: f5a3 4300 sub.w r3, r3, #32768 ; 0x8000 8000a6a: ee07 3a90 vmov s15, r3 8000a6e: eeb8 7ac7 vcvt.f32.s32 s14, s14 8000a72: eef8 7ae7 vcvt.f32.s32 s15, s15 operator_run(&OP2, OP1.ADSR.output * OP1.ADSR.output); 8000a76: ee66 6a85 vmul.f32 s13, s13, s10 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a7a: ee27 7a25 vmul.f32 s14, s14, s11 8000a7e: ee67 7aa6 vmul.f32 s15, s15, s13 8000a82: eebd 7ac7 vcvt.s32.f32 s14, s14 8000a86: eefd 7ae7 vcvt.s32.f32 s15, s15 8000a8a: ee17 2a10 vmov r2, s14 8000a8e: ee17 3a90 vmov r3, s15 voice1 = (OP1.output) >> 5; 8000a92: 1150 asrs r0, r2, #5 OP->phase_index += OP->phase_increment; 8000a94: 6125 str r5, [r4, #16] output = voice1; //hard clipping if (output > 2047) { 8000a96: f5b0 6f00 cmp.w r0, #2048 ; 0x800 OP1.modulation = (OP2.output) >> 3; 8000a9a: ea4f 05e3 mov.w r5, r3, asr #3 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a9e: ed84 7a00 vstr s14, [r4] voice1 = (OP1.output) >> 5; 8000aa2: 6030 str r0, [r6, #0] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000aa4: edc1 7a00 vstr s15, [r1] OP1.modulation = (OP2.output) >> 3; 8000aa8: 6165 str r5, [r4, #20] if (output > 2047) { 8000aaa: db0c blt.n 8000ac6 output = 2047; 8000aac: 4b27 ldr r3, [pc, #156] ; (8000b4c ) 8000aae: f240 72ff movw r2, #2047 ; 0x7ff 8000ab2: 601a str r2, [r3, #0] 8000ab4: f640 73ff movw r3, #4095 ; 0xfff output = -2047; } //DAC output HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, output + 2048); } 8000ab8: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, output + 2048); 8000abc: 4824 ldr r0, [pc, #144] ; (8000b50 ) 8000abe: 2200 movs r2, #0 8000ac0: 2110 movs r1, #16 8000ac2: f001 bc23 b.w 800230c if (output < -2047) { 8000ac6: 4a23 ldr r2, [pc, #140] ; (8000b54 ) 8000ac8: 4290 cmp r0, r2 8000aca: da03 bge.n 8000ad4 output = -2047; 8000acc: 491f ldr r1, [pc, #124] ; (8000b4c ) 8000ace: 2301 movs r3, #1 8000ad0: 600a str r2, [r1, #0] 8000ad2: e7f1 b.n 8000ab8 output = voice1; 8000ad4: 4a1d ldr r2, [pc, #116] ; (8000b4c ) 8000ad6: f500 6300 add.w r3, r0, #2048 ; 0x800 8000ada: 6010 str r0, [r2, #0] 8000adc: e7ec b.n 8000ab8 8000ade: bf00 nop 8000ae0: 200008a0 .word 0x200008a0 8000ae4: 48000400 .word 0x48000400 8000ae8: 20000840 .word 0x20000840 8000aec: 20000b54 .word 0x20000b54 8000af0: 20000898 .word 0x20000898 8000af4: 200008b2 .word 0x200008b2 8000af8: 3b000000 .word 0x3b000000 8000afc: 3c23d70a .word 0x3c23d70a 8000b00: 3a23d70a .word 0x3a23d70a 8000b04: 200008a4 .word 0x200008a4 8000b08: 20000838 .word 0x20000838 8000b0c: 2000083c .word 0x2000083c 8000b10: 20000afc .word 0x20000afc 8000b14: 3d4ccccd .word 0x3d4ccccd 8000b18: 20000ad4 .word 0x20000ad4 8000b1c: 20000800 .word 0x20000800 8000b20: 200008ac .word 0x200008ac 8000b24: 3da3d70a .word 0x3da3d70a 8000b28: 200008c8 .word 0x200008c8 8000b2c: 3a001002 .word 0x3a001002 8000b30: 20000000 .word 0x20000000 8000b34: 42000000 .word 0x42000000 8000b38: 4727c5ac .word 0x4727c5ac 8000b3c: 20000b04 .word 0x20000b04 8000b40: 20000830 .word 0x20000830 8000b44: 08003828 .word 0x08003828 8000b48: 20000af8 .word 0x20000af8 8000b4c: 2000089c .word 0x2000089c 8000b50: 20000cf8 .word 0x20000cf8 8000b54: fffff801 .word 0xfffff801 8000b58: 200008a8 .word 0x200008a8 08000b5c : sensitivity = _sensitivity; wc = basefreq / 22050.0f; //gc = tan(3.14f * wc); gc = .00000712018209f; _smooth->g0 = 2*gc/(1+gc); _smooth->sense = sensitivity * 4.0f; 8000b5c: eef1 7a00 vmov.f32 s15, #16 ; 0x40800000 4.0 8000b60: ee60 0aa7 vmul.f32 s1, s1, s15 //tick values _smooth->low1 = 0.0f; 8000b64: 2300 movs r3, #0 _smooth->g0 = 2*gc/(1+gc); 8000b66: 4a05 ldr r2, [pc, #20] ; (8000b7c ) 8000b68: 6002 str r2, [r0, #0] _smooth->sense = sensitivity * 4.0f; 8000b6a: edc0 0a01 vstr s1, [r0, #4] _smooth->low1 = 0.0f; 8000b6e: 6083 str r3, [r0, #8] _smooth->low2 = 0.0f; 8000b70: 60c3 str r3, [r0, #12] _smooth->low1z = 0.0f; 8000b72: 6103 str r3, [r0, #16] _smooth->low2z = 0.0f; 8000b74: 6143 str r3, [r0, #20] _smooth->bandz = 0.0f; 8000b76: 6183 str r3, [r0, #24] _smooth->out = 0.0f; 8000b78: 61c3 str r3, [r0, #28] } 8000b7a: 4770 bx lr 8000b7c: 376ee976 .word 0x376ee976 08000b80 : float dynamic_smooth_tick(dynamic_smooth* _smooth, float in) { float g; _smooth->low1z = _smooth->low1; 8000b80: ed90 7a02 vldr s14, [r0, #8] _smooth->low2z = _smooth->low2; 8000b84: edd0 7a03 vldr s15, [r0, #12] _smooth->bandz = _smooth->low2z - _smooth->low1z; g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); 8000b88: ed90 5a01 vldr s10, [r0, #4] 8000b8c: edd0 6a00 vldr s13, [r0] _smooth->low1z = _smooth->low1; 8000b90: ed80 7a04 vstr s14, [r0, #16] _smooth->bandz = _smooth->low2z - _smooth->low1z; 8000b94: ee37 6ac7 vsub.f32 s12, s15, s14 return ((a) < (b) ? a : b); 8000b98: eef7 5a00 vmov.f32 s11, #112 ; 0x3f800000 1.0 g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); 8000b9c: eef0 4ac6 vabs.f32 s9, s12 8000ba0: eee4 6a85 vfma.f32 s13, s9, s10 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8000ba4: ee30 0a47 vsub.f32 s0, s0, s14 return ((a) < (b) ? a : b); 8000ba8: eef4 6ae5 vcmpe.f32 s13, s11 8000bac: eef1 fa10 vmrs APSR_nzcv, fpscr 8000bb0: bf88 it hi 8000bb2: eef0 6a65 vmovhi.f32 s13, s11 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8000bb6: eea0 7a26 vfma.f32 s14, s0, s13 _smooth->low2z = _smooth->low2; 8000bba: edc0 7a05 vstr s15, [r0, #20] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 8000bbe: ee77 5a67 vsub.f32 s11, s14, s15 _smooth->bandz = _smooth->low2z - _smooth->low1z; 8000bc2: ed80 6a06 vstr s12, [r0, #24] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 8000bc6: eee5 7aa6 vfma.f32 s15, s11, s13 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8000bca: ed80 7a02 vstr s14, [r0, #8] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 8000bce: eeb0 0a67 vmov.f32 s0, s15 8000bd2: edc0 7a03 vstr s15, [r0, #12] return _smooth->low2; } 8000bd6: 4770 bx lr 08000bd8 : #include "loop.h" #include "main.h" void loop(void) { } 8000bd8: 4770 bx lr 8000bda: bf00 nop 08000bdc : DMA_HandleTypeDef hdma_adc1; DMA_HandleTypeDef hdma_adc2; /* ADC1 init function */ void MX_ADC1_Init(void) { 8000bdc: b530 push {r4, r5, lr} /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000bde: 2400 movs r4, #0 { 8000be0: b08d sub sp, #52 ; 0x34 ADC_ChannelConfTypeDef sConfig = {0}; 8000be2: 4621 mov r1, r4 8000be4: 2220 movs r2, #32 8000be6: a804 add r0, sp, #16 ADC_MultiModeTypeDef multimode = {0}; 8000be8: e9cd 4401 strd r4, r4, [sp, #4] 8000bec: 9403 str r4, [sp, #12] ADC_ChannelConfTypeDef sConfig = {0}; 8000bee: f002 fe07 bl 8003800 /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000bf2: 4845 ldr r0, [pc, #276] ; (8000d08 ) 8000bf4: f04f 41a0 mov.w r1, #1342177280 ; 0x50000000 hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 8000bf8: f44f 3200 mov.w r2, #131072 ; 0x20000 hadc1.Init.GainCompensation = 0; hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; hadc1.Init.LowPowerAutoWait = DISABLE; hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.NbrOfConversion = 6; 8000bfc: 2306 movs r3, #6 hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000bfe: 2508 movs r5, #8 hadc1.Instance = ADC1; 8000c00: 6001 str r1, [r0, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 8000c02: 6042 str r2, [r0, #4] hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T3_TRGO; 8000c04: f44f 6190 mov.w r1, #1152 ; 0x480 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000c08: f44f 6280 mov.w r2, #1024 ; 0x400 hadc1.Init.NbrOfConversion = 6; 8000c0c: 6203 str r3, [r0, #32] hadc1.Init.LowPowerAutoWait = DISABLE; 8000c0e: 8384 strh r4, [r0, #28] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000c10: 2301 movs r3, #1 hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8000c12: e9c0 4402 strd r4, r4, [r0, #8] hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000c16: e9c0 120b strd r1, r2, [r0, #44] ; 0x2c hadc1.Init.GainCompensation = 0; 8000c1a: 6104 str r4, [r0, #16] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000c1c: f880 4024 strb.w r4, [r0, #36] ; 0x24 hadc1.Init.DMAContinuousRequests = ENABLE; hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000c20: 63c4 str r4, [r0, #60] ; 0x3c hadc1.Init.OversamplingMode = DISABLE; 8000c22: f880 4040 strb.w r4, [r0, #64] ; 0x40 hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000c26: 6185 str r5, [r0, #24] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000c28: 6143 str r3, [r0, #20] hadc1.Init.DMAContinuousRequests = ENABLE; 8000c2a: f880 3038 strb.w r3, [r0, #56] ; 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000c2e: f000 fd0f bl 8001650 8000c32: 2800 cmp r0, #0 8000c34: d14f bne.n 8000cd6 { Error_Handler(); } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000c36: 2300 movs r3, #0 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000c38: 4833 ldr r0, [pc, #204] ; (8000d08 ) multimode.Mode = ADC_MODE_INDEPENDENT; 8000c3a: 9301 str r3, [sp, #4] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000c3c: a901 add r1, sp, #4 8000c3e: f001 fa2b bl 8002098 8000c42: 2800 cmp r0, #0 8000c44: d15d bne.n 8000d02 { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000c46: 2206 movs r2, #6 8000c48: 237f movs r3, #127 ; 0x7f 8000c4a: 4c30 ldr r4, [pc, #192] ; (8000d0c ) sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c4c: 482e ldr r0, [pc, #184] ; (8000d08 ) sConfig.Channel = ADC_CHANNEL_1; 8000c4e: e9cd 2306 strd r2, r3, [sp, #24] 8000c52: 2506 movs r5, #6 8000c54: 2204 movs r2, #4 8000c56: 2300 movs r3, #0 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c58: a904 add r1, sp, #16 sConfig.Channel = ADC_CHANNEL_1; 8000c5a: e9cd 4504 strd r4, r5, [sp, #16] 8000c5e: e9cd 2308 strd r2, r3, [sp, #32] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c62: f000 fe47 bl 80018f4 8000c66: 2800 cmp r0, #0 8000c68: d148 bne.n 8000cfc { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; 8000c6a: 4a29 ldr r2, [pc, #164] ; (8000d10 ) sConfig.Rank = ADC_REGULAR_RANK_2; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c6c: 4826 ldr r0, [pc, #152] ; (8000d08 ) sConfig.Channel = ADC_CHANNEL_2; 8000c6e: 230c movs r3, #12 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c70: a904 add r1, sp, #16 sConfig.Channel = ADC_CHANNEL_2; 8000c72: e9cd 2304 strd r2, r3, [sp, #16] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c76: f000 fe3d bl 80018f4 8000c7a: 2800 cmp r0, #0 8000c7c: d13b bne.n 8000cf6 { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000c7e: 4a25 ldr r2, [pc, #148] ; (8000d14 ) sConfig.Rank = ADC_REGULAR_RANK_3; sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c80: 4821 ldr r0, [pc, #132] ; (8000d08 ) sConfig.Channel = ADC_CHANNEL_3; 8000c82: 2312 movs r3, #18 sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5; 8000c84: 2405 movs r4, #5 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c86: a904 add r1, sp, #16 sConfig.Channel = ADC_CHANNEL_3; 8000c88: e9cd 2304 strd r2, r3, [sp, #16] sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5; 8000c8c: 9406 str r4, [sp, #24] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c8e: f000 fe31 bl 80018f4 8000c92: bb68 cbnz r0, 8000cf0 { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000c94: 4a20 ldr r2, [pc, #128] ; (8000d18 ) sConfig.Rank = ADC_REGULAR_RANK_4; sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c96: 481c ldr r0, [pc, #112] ; (8000d08 ) sConfig.Channel = ADC_CHANNEL_4; 8000c98: 2318 movs r3, #24 sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; 8000c9a: 2406 movs r4, #6 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c9c: a904 add r1, sp, #16 sConfig.Channel = ADC_CHANNEL_4; 8000c9e: e9cd 2304 strd r2, r3, [sp, #16] sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; 8000ca2: 9406 str r4, [sp, #24] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ca4: f000 fe26 bl 80018f4 8000ca8: b9f8 cbnz r0, 8000cea { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000caa: 4a1c ldr r2, [pc, #112] ; (8000d1c ) sConfig.Rank = ADC_REGULAR_RANK_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cac: 4816 ldr r0, [pc, #88] ; (8000d08 ) sConfig.Channel = ADC_CHANNEL_15; 8000cae: f44f 7380 mov.w r3, #256 ; 0x100 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cb2: a904 add r1, sp, #16 sConfig.Channel = ADC_CHANNEL_15; 8000cb4: e9cd 2304 strd r2, r3, [sp, #16] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cb8: f000 fe1c bl 80018f4 8000cbc: b990 cbnz r0, 8000ce4 { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000cbe: 4a18 ldr r2, [pc, #96] ; (8000d20 ) sConfig.Rank = ADC_REGULAR_RANK_6; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cc0: 4811 ldr r0, [pc, #68] ; (8000d08 ) sConfig.Channel = ADC_CHANNEL_VREFINT; 8000cc2: f44f 7383 mov.w r3, #262 ; 0x106 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cc6: a904 add r1, sp, #16 sConfig.Channel = ADC_CHANNEL_VREFINT; 8000cc8: e9cd 2304 strd r2, r3, [sp, #16] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ccc: f000 fe12 bl 80018f4 8000cd0: b920 cbnz r0, 8000cdc } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8000cd2: b00d add sp, #52 ; 0x34 8000cd4: bd30 pop {r4, r5, pc} Error_Handler(); 8000cd6: f000 faff bl 80012d8 8000cda: e7ac b.n 8000c36 Error_Handler(); 8000cdc: f000 fafc bl 80012d8 } 8000ce0: b00d add sp, #52 ; 0x34 8000ce2: bd30 pop {r4, r5, pc} Error_Handler(); 8000ce4: f000 faf8 bl 80012d8 8000ce8: e7e9 b.n 8000cbe Error_Handler(); 8000cea: f000 faf5 bl 80012d8 8000cee: e7dc b.n 8000caa Error_Handler(); 8000cf0: f000 faf2 bl 80012d8 8000cf4: e7ce b.n 8000c94 Error_Handler(); 8000cf6: f000 faef bl 80012d8 8000cfa: e7c0 b.n 8000c7e Error_Handler(); 8000cfc: f000 faec bl 80012d8 8000d00: e7b3 b.n 8000c6a Error_Handler(); 8000d02: f000 fae9 bl 80012d8 8000d06: e79e b.n 8000c46 8000d08: 20000bcc .word 0x20000bcc 8000d0c: 04300002 .word 0x04300002 8000d10: 08600004 .word 0x08600004 8000d14: 0c900008 .word 0x0c900008 8000d18: 10c00010 .word 0x10c00010 8000d1c: 3ef08000 .word 0x3ef08000 8000d20: cb840000 .word 0xcb840000 08000d24 : /* ADC2 init function */ void MX_ADC2_Init(void) { 8000d24: b530 push {r4, r5, lr} 8000d26: b089 sub sp, #36 ; 0x24 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000d28: 2220 movs r2, #32 8000d2a: 2100 movs r1, #0 8000d2c: 4668 mov r0, sp 8000d2e: f002 fd67 bl 8003800 /* USER CODE BEGIN ADC2_Init 1 */ /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000d32: 4823 ldr r0, [pc, #140] ; (8000dc0 ) 8000d34: 4b23 ldr r3, [pc, #140] ; (8000dc4 ) 8000d36: 6003 str r3, [r0, #0] hadc2.Init.GainCompensation = 0; hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; hadc2.Init.LowPowerAutoWait = DISABLE; hadc2.Init.ContinuousConvMode = DISABLE; hadc2.Init.NbrOfConversion = 2; 8000d38: 2302 movs r3, #2 hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 8000d3a: f44f 3100 mov.w r1, #131072 ; 0x20000 hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000d3e: f44f 62ac mov.w r2, #1376 ; 0x560 hadc2.Init.NbrOfConversion = 2; 8000d42: 6203 str r3, [r0, #32] hadc2.Init.Resolution = ADC_RESOLUTION_12B; 8000d44: 2300 movs r3, #0 hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000d46: 2408 movs r4, #8 hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 8000d48: 6041 str r1, [r0, #4] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000d4a: 62c2 str r2, [r0, #44] ; 0x2c hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000d4c: f44f 6180 mov.w r1, #1024 ; 0x400 hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000d50: 2201 movs r2, #1 hadc2.Init.LowPowerAutoWait = DISABLE; 8000d52: 8383 strh r3, [r0, #28] hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8000d54: e9c0 3302 strd r3, r3, [r0, #8] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000d58: 6184 str r4, [r0, #24] hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000d5a: 6301 str r1, [r0, #48] ; 0x30 hadc2.Init.GainCompensation = 0; 8000d5c: 6103 str r3, [r0, #16] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000d5e: f880 3024 strb.w r3, [r0, #36] ; 0x24 hadc2.Init.DMAContinuousRequests = ENABLE; hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000d62: 63c3 str r3, [r0, #60] ; 0x3c hadc2.Init.OversamplingMode = DISABLE; 8000d64: f880 3040 strb.w r3, [r0, #64] ; 0x40 hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000d68: 6142 str r2, [r0, #20] hadc2.Init.DMAContinuousRequests = ENABLE; 8000d6a: f880 2038 strb.w r2, [r0, #56] ; 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000d6e: f000 fc6f bl 8001650 8000d72: b9d8 cbnz r0, 8000dac { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000d74: 2203 movs r2, #3 8000d76: 237f movs r3, #127 ; 0x7f 8000d78: 4c13 ldr r4, [pc, #76] ; (8000dc8 ) sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_24CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d7a: 4811 ldr r0, [pc, #68] ; (8000dc0 ) sConfig.Channel = ADC_CHANNEL_3; 8000d7c: e9cd 2302 strd r2, r3, [sp, #8] 8000d80: 2506 movs r5, #6 8000d82: 2204 movs r2, #4 8000d84: 2300 movs r3, #0 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d86: 4669 mov r1, sp sConfig.Channel = ADC_CHANNEL_3; 8000d88: e9cd 4500 strd r4, r5, [sp] 8000d8c: e9cd 2304 strd r2, r3, [sp, #16] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d90: f000 fdb0 bl 80018f4 8000d94: b988 cbnz r0, 8000dba { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000d96: 4a0d ldr r2, [pc, #52] ; (8000dcc ) sConfig.Rank = ADC_REGULAR_RANK_2; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d98: 4809 ldr r0, [pc, #36] ; (8000dc0 ) sConfig.Channel = ADC_CHANNEL_4; 8000d9a: 230c movs r3, #12 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000d9c: 4669 mov r1, sp sConfig.Channel = ADC_CHANNEL_4; 8000d9e: e9cd 2300 strd r2, r3, [sp] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000da2: f000 fda7 bl 80018f4 8000da6: b920 cbnz r0, 8000db2 } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } 8000da8: b009 add sp, #36 ; 0x24 8000daa: bd30 pop {r4, r5, pc} Error_Handler(); 8000dac: f000 fa94 bl 80012d8 8000db0: e7e0 b.n 8000d74 Error_Handler(); 8000db2: f000 fa91 bl 80012d8 } 8000db6: b009 add sp, #36 ; 0x24 8000db8: bd30 pop {r4, r5, pc} Error_Handler(); 8000dba: f000 fa8d bl 80012d8 8000dbe: e7ea b.n 8000d96 8000dc0: 20000b60 .word 0x20000b60 8000dc4: 50000100 .word 0x50000100 8000dc8: 0c900008 .word 0x0c900008 8000dcc: 10c00010 .word 0x10c00010 08000dd0 : static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0; void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8000dd0: b570 push {r4, r5, r6, lr} 8000dd2: 4604 mov r4, r0 8000dd4: b09c sub sp, #112 ; 0x70 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000dd6: 2100 movs r1, #0 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000dd8: a80b add r0, sp, #44 ; 0x2c 8000dda: 2244 movs r2, #68 ; 0x44 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000ddc: e9cd 1106 strd r1, r1, [sp, #24] 8000de0: e9cd 1108 strd r1, r1, [sp, #32] 8000de4: 910a str r1, [sp, #40] ; 0x28 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000de6: f002 fd0b bl 8003800 if(adcHandle->Instance==ADC1) 8000dea: 6823 ldr r3, [r4, #0] 8000dec: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8000df0: d004 beq.n 8000dfc /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } else if(adcHandle->Instance==ADC2) 8000df2: 4a57 ldr r2, [pc, #348] ; (8000f50 ) 8000df4: 4293 cmp r3, r2 8000df6: d061 beq.n 8000ebc /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8000df8: b01c add sp, #112 ; 0x70 8000dfa: bd70 pop {r4, r5, r6, pc} PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8000dfc: f44f 4200 mov.w r2, #32768 ; 0x8000 PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8000e00: f04f 5300 mov.w r3, #536870912 ; 0x20000000 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000e04: a80b add r0, sp, #44 ; 0x2c PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8000e06: 920b str r2, [sp, #44] ; 0x2c PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8000e08: 931a str r3, [sp, #104] ; 0x68 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000e0a: f002 f9a5 bl 8003158 8000e0e: 2800 cmp r0, #0 8000e10: f040 8098 bne.w 8000f44 HAL_RCC_ADC12_CLK_ENABLED++; 8000e14: 4a4f ldr r2, [pc, #316] ; (8000f54 ) 8000e16: 6813 ldr r3, [r2, #0] 8000e18: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8000e1a: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 8000e1c: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8000e1e: d109 bne.n 8000e34 __HAL_RCC_ADC12_CLK_ENABLE(); 8000e20: 4b4d ldr r3, [pc, #308] ; (8000f58 ) 8000e22: 6cda ldr r2, [r3, #76] ; 0x4c 8000e24: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8000e28: 64da str r2, [r3, #76] ; 0x4c 8000e2a: 6cdb ldr r3, [r3, #76] ; 0x4c 8000e2c: f403 5300 and.w r3, r3, #8192 ; 0x2000 8000e30: 9301 str r3, [sp, #4] 8000e32: 9b01 ldr r3, [sp, #4] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000e34: 4b48 ldr r3, [pc, #288] ; (8000f58 ) hdma_adc1.Instance = DMA1_Channel2; 8000e36: 4d49 ldr r5, [pc, #292] ; (8000f5c ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8000e38: 6cda ldr r2, [r3, #76] ; 0x4c 8000e3a: f042 0201 orr.w r2, r2, #1 8000e3e: 64da str r2, [r3, #76] ; 0x4c 8000e40: 6cda ldr r2, [r3, #76] ; 0x4c 8000e42: f002 0201 and.w r2, r2, #1 8000e46: 9202 str r2, [sp, #8] 8000e48: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000e4a: 6cda ldr r2, [r3, #76] ; 0x4c 8000e4c: f042 0202 orr.w r2, r2, #2 8000e50: 64da str r2, [r3, #76] ; 0x4c 8000e52: 6cdb ldr r3, [r3, #76] ; 0x4c 8000e54: f003 0302 and.w r3, r3, #2 8000e58: 9303 str r3, [sp, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e5a: 2600 movs r6, #0 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 8000e5c: 220f movs r2, #15 8000e5e: 2303 movs r3, #3 __HAL_RCC_GPIOB_CLK_ENABLE(); 8000e60: 9903 ldr r1, [sp, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e62: 9608 str r6, [sp, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000e64: a906 add r1, sp, #24 8000e66: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 8000e6a: e9cd 2306 strd r2, r3, [sp, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000e6e: f001 fc4d bl 800270c GPIO_InitStruct.Pin = GPIO_PIN_0; 8000e72: 2201 movs r2, #1 8000e74: 2303 movs r3, #3 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000e76: 483a ldr r0, [pc, #232] ; (8000f60 ) GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e78: 9608 str r6, [sp, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000e7a: a906 add r1, sp, #24 GPIO_InitStruct.Pin = GPIO_PIN_0; 8000e7c: e9cd 2306 strd r2, r3, [sp, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000e80: f001 fc44 bl 800270c hdma_adc1.Instance = DMA1_Channel2; 8000e84: 4937 ldr r1, [pc, #220] ; (8000f64 ) 8000e86: 6029 str r1, [r5, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8000e88: 2205 movs r2, #5 hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8000e8a: 2380 movs r3, #128 ; 0x80 hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8000e8c: 606a str r2, [r5, #4] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8000e8e: 612b str r3, [r5, #16] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8000e90: 60ae str r6, [r5, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8000e92: 60ee str r6, [r5, #12] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8000e94: f44f 7080 mov.w r0, #256 ; 0x100 hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8000e98: f44f 6180 mov.w r1, #1024 ; 0x400 hdma_adc1.Init.Mode = DMA_CIRCULAR; 8000e9c: 2220 movs r2, #32 hdma_adc1.Init.Priority = DMA_PRIORITY_MEDIUM; 8000e9e: f44f 5380 mov.w r3, #4096 ; 0x1000 hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8000ea2: 6168 str r0, [r5, #20] hdma_adc2.Init.Mode = DMA_CIRCULAR; 8000ea4: e9c5 1206 strd r1, r2, [r5, #24] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8000ea8: 4628 mov r0, r5 hdma_adc2.Init.Priority = DMA_PRIORITY_VERY_HIGH; 8000eaa: 622b str r3, [r5, #32] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8000eac: f001 fb3a bl 8002524 8000eb0: 2800 cmp r0, #0 8000eb2: d144 bne.n 8000f3e __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc2); 8000eb4: 6565 str r5, [r4, #84] ; 0x54 8000eb6: 62ac str r4, [r5, #40] ; 0x28 } 8000eb8: b01c add sp, #112 ; 0x70 8000eba: bd70 pop {r4, r5, r6, pc} PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8000ebc: f44f 4200 mov.w r2, #32768 ; 0x8000 PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8000ec0: f04f 5300 mov.w r3, #536870912 ; 0x20000000 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000ec4: a80b add r0, sp, #44 ; 0x2c PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8000ec6: 920b str r2, [sp, #44] ; 0x2c PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8000ec8: 931a str r3, [sp, #104] ; 0x68 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000eca: f002 f945 bl 8003158 8000ece: 2800 cmp r0, #0 8000ed0: d13b bne.n 8000f4a HAL_RCC_ADC12_CLK_ENABLED++; 8000ed2: 4a20 ldr r2, [pc, #128] ; (8000f54 ) 8000ed4: 6813 ldr r3, [r2, #0] 8000ed6: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8000ed8: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 8000eda: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8000edc: d109 bne.n 8000ef2 __HAL_RCC_ADC12_CLK_ENABLE(); 8000ede: 4b1e ldr r3, [pc, #120] ; (8000f58 ) 8000ee0: 6cda ldr r2, [r3, #76] ; 0x4c 8000ee2: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8000ee6: 64da str r2, [r3, #76] ; 0x4c 8000ee8: 6cdb ldr r3, [r3, #76] ; 0x4c 8000eea: f403 5300 and.w r3, r3, #8192 ; 0x2000 8000eee: 9304 str r3, [sp, #16] 8000ef0: 9b04 ldr r3, [sp, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000ef2: 4b19 ldr r3, [pc, #100] ; (8000f58 ) hdma_adc2.Instance = DMA1_Channel1; 8000ef4: 4d1c ldr r5, [pc, #112] ; (8000f68 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8000ef6: 6cda ldr r2, [r3, #76] ; 0x4c 8000ef8: f042 0201 orr.w r2, r2, #1 8000efc: 64da str r2, [r3, #76] ; 0x4c 8000efe: 6cdb ldr r3, [r3, #76] ; 0x4c 8000f00: f003 0301 and.w r3, r3, #1 8000f04: 9305 str r3, [sp, #20] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8000f06: 22c0 movs r2, #192 ; 0xc0 8000f08: 2303 movs r3, #3 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f0a: 2600 movs r6, #0 __HAL_RCC_GPIOA_CLK_ENABLE(); 8000f0c: 9805 ldr r0, [sp, #20] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f0e: 9608 str r6, [sp, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f10: a906 add r1, sp, #24 8000f12: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8000f16: e9cd 2306 strd r2, r3, [sp, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f1a: f001 fbf7 bl 800270c hdma_adc2.Instance = DMA1_Channel1; 8000f1e: 4913 ldr r1, [pc, #76] ; (8000f6c ) 8000f20: 6029 str r1, [r5, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8000f22: 2224 movs r2, #36 ; 0x24 hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8000f24: 2380 movs r3, #128 ; 0x80 hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8000f26: 606a str r2, [r5, #4] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8000f28: 612b str r3, [r5, #16] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8000f2a: 60ae str r6, [r5, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8000f2c: 60ee str r6, [r5, #12] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8000f2e: f44f 7080 mov.w r0, #256 ; 0x100 hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8000f32: f44f 6180 mov.w r1, #1024 ; 0x400 hdma_adc2.Init.Mode = DMA_CIRCULAR; 8000f36: 2220 movs r2, #32 hdma_adc2.Init.Priority = DMA_PRIORITY_VERY_HIGH; 8000f38: f44f 5340 mov.w r3, #12288 ; 0x3000 8000f3c: e7b1 b.n 8000ea2 Error_Handler(); 8000f3e: f000 f9cb bl 80012d8 8000f42: e7b7 b.n 8000eb4 Error_Handler(); 8000f44: f000 f9c8 bl 80012d8 8000f48: e764 b.n 8000e14 Error_Handler(); 8000f4a: f000 f9c5 bl 80012d8 8000f4e: e7c0 b.n 8000ed2 8000f50: 50000100 .word 0x50000100 8000f54: 2000082c .word 0x2000082c 8000f58: 40021000 .word 0x40021000 8000f5c: 20000c38 .word 0x20000c38 8000f60: 48000400 .word 0x48000400 8000f64: 4002001c .word 0x4002001c 8000f68: 20000c98 .word 0x20000c98 8000f6c: 40020008 .word 0x40020008 08000f70 : /* USER CODE END ADC2_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void ADC_Start() { 8000f70: b508 push {r3, lr} if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED) != HAL_OK) { 8000f72: 4810 ldr r0, [pc, #64] ; (8000fb4 ) 8000f74: 217f movs r1, #127 ; 0x7f 8000f76: f001 f841 bl 8001ffc 8000f7a: b980 cbnz r0, 8000f9e // Calibration Error Error_Handler(); } if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED) != HAL_OK) { 8000f7c: 480e ldr r0, [pc, #56] ; (8000fb8 ) 8000f7e: 217f movs r1, #127 ; 0x7f 8000f80: f001 f83c bl 8001ffc 8000f84: b998 cbnz r0, 8000fae // Calibration Error Error_Handler(); } HAL_ADC_Start_DMA(&hadc1, (uint32_t*) adc1_data, NUM_ADC1_CHANNELS); 8000f86: 490d ldr r1, [pc, #52] ; (8000fbc ) 8000f88: 480a ldr r0, [pc, #40] ; (8000fb4 ) 8000f8a: 2206 movs r2, #6 8000f8c: f000 ff80 bl 8001e90 HAL_ADC_Start_DMA(&hadc2, (uint32_t*) adc2_data, NUM_ADC2_CHANNELS); } 8000f90: e8bd 4008 ldmia.w sp!, {r3, lr} HAL_ADC_Start_DMA(&hadc2, (uint32_t*) adc2_data, NUM_ADC2_CHANNELS); 8000f94: 490a ldr r1, [pc, #40] ; (8000fc0 ) 8000f96: 4808 ldr r0, [pc, #32] ; (8000fb8 ) 8000f98: 2202 movs r2, #2 8000f9a: f000 bf79 b.w 8001e90 Error_Handler(); 8000f9e: f000 f99b bl 80012d8 if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED) != HAL_OK) { 8000fa2: 4805 ldr r0, [pc, #20] ; (8000fb8 ) 8000fa4: 217f movs r1, #127 ; 0x7f 8000fa6: f001 f829 bl 8001ffc 8000faa: 2800 cmp r0, #0 8000fac: d0eb beq.n 8000f86 Error_Handler(); 8000fae: f000 f993 bl 80012d8 8000fb2: e7e8 b.n 8000f86 8000fb4: 20000bcc .word 0x20000bcc 8000fb8: 20000b60 .word 0x20000b60 8000fbc: 200008bc .word 0x200008bc 8000fc0: 200008a4 .word 0x200008a4 08000fc4 : DAC_HandleTypeDef hdac1; /* DAC1 init function */ void MX_DAC1_Init(void) { 8000fc4: b530 push {r4, r5, lr} 8000fc6: b08d sub sp, #52 ; 0x34 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000fc8: 4668 mov r0, sp 8000fca: 2230 movs r2, #48 ; 0x30 8000fcc: 2100 movs r1, #0 8000fce: f002 fc17 bl 8003800 /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000fd2: 4816 ldr r0, [pc, #88] ; (800102c ) 8000fd4: 4b16 ldr r3, [pc, #88] ; (8001030 ) 8000fd6: 6003 str r3, [r0, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8000fd8: f001 f938 bl 800224c 8000fdc: b9d8 cbnz r0, 8001016 /** DAC channel OUT1 config */ sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; sConfig.DAC_DMADoubleDataMode = DISABLE; sConfig.DAC_SignedFormat = DISABLE; sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000fde: 2400 movs r4, #0 8000fe0: 2500 movs r5, #0 8000fe2: e9cd 4502 strd r4, r5, [sp, #8] 8000fe6: e9cd 4504 strd r4, r5, [sp, #16] sConfig.DAC_DMADoubleDataMode = DISABLE; 8000fea: 2200 movs r2, #0 sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; 8000fec: 2302 movs r3, #2 sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000fee: 2401 movs r4, #1 8000ff0: 2500 movs r5, #0 sConfig.DAC_Trigger = DAC_TRIGGER_NONE; sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE; sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_EXTERNAL; sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000ff2: 480e ldr r0, [pc, #56] ; (800102c ) sConfig.DAC_DMADoubleDataMode = DISABLE; 8000ff4: f8ad 2004 strh.w r2, [sp, #4] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000ff8: 4669 mov r1, sp sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000ffa: e9cd 4506 strd r4, r5, [sp, #24] sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; 8000ffe: 9300 str r3, [sp, #0] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8001000: f001 f9a2 bl 8002348 8001004: b970 cbnz r0, 8001024 { Error_Handler(); } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8001006: 4809 ldr r0, [pc, #36] ; (800102c ) 8001008: 4669 mov r1, sp 800100a: 2210 movs r2, #16 800100c: f001 f99c bl 8002348 8001010: b920 cbnz r0, 800101c } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8001012: b00d add sp, #52 ; 0x34 8001014: bd30 pop {r4, r5, pc} Error_Handler(); 8001016: f000 f95f bl 80012d8 800101a: e7e0 b.n 8000fde Error_Handler(); 800101c: f000 f95c bl 80012d8 } 8001020: b00d add sp, #52 ; 0x34 8001022: bd30 pop {r4, r5, pc} Error_Handler(); 8001024: f000 f958 bl 80012d8 8001028: e7ed b.n 8001006 800102a: bf00 nop 800102c: 20000cf8 .word 0x20000cf8 8001030: 50000800 .word 0x50000800 08001034 : void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) { 8001034: b510 push {r4, lr} GPIO_InitTypeDef GPIO_InitStruct = {0}; if(dacHandle->Instance==DAC1) 8001036: 6801 ldr r1, [r0, #0] 8001038: 4a16 ldr r2, [pc, #88] ; (8001094 ) { 800103a: b088 sub sp, #32 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800103c: 2300 movs r3, #0 if(dacHandle->Instance==DAC1) 800103e: 4291 cmp r1, r2 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001040: e9cd 3302 strd r3, r3, [sp, #8] 8001044: e9cd 3304 strd r3, r3, [sp, #16] 8001048: 9306 str r3, [sp, #24] if(dacHandle->Instance==DAC1) 800104a: d001 beq.n 8001050 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 800104c: b008 add sp, #32 800104e: bd10 pop {r4, pc} __HAL_RCC_DAC1_CLK_ENABLE(); 8001050: f102 4270 add.w r2, r2, #4026531840 ; 0xf0000000 8001054: f502 3202 add.w r2, r2, #133120 ; 0x20800 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001058: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 __HAL_RCC_DAC1_CLK_ENABLE(); 800105c: 6cd1 ldr r1, [r2, #76] ; 0x4c 800105e: f441 3180 orr.w r1, r1, #65536 ; 0x10000 8001062: 64d1 str r1, [r2, #76] ; 0x4c 8001064: 6cd1 ldr r1, [r2, #76] ; 0x4c 8001066: f401 3180 and.w r1, r1, #65536 ; 0x10000 800106a: 9100 str r1, [sp, #0] 800106c: 9900 ldr r1, [sp, #0] __HAL_RCC_GPIOA_CLK_ENABLE(); 800106e: 6cd1 ldr r1, [r2, #76] ; 0x4c 8001070: f041 0101 orr.w r1, r1, #1 8001074: 64d1 str r1, [r2, #76] ; 0x4c 8001076: 6cd2 ldr r2, [r2, #76] ; 0x4c GPIO_InitStruct.Pull = GPIO_NOPULL; 8001078: 9304 str r3, [sp, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800107a: f002 0201 and.w r2, r2, #1 800107e: 9201 str r2, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8001080: 2303 movs r3, #3 8001082: 2230 movs r2, #48 ; 0x30 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001084: a902 add r1, sp, #8 GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8001086: e9cd 2302 strd r2, r3, [sp, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 800108a: 9c01 ldr r4, [sp, #4] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800108c: f001 fb3e bl 800270c } 8001090: b008 add sp, #32 8001092: bd10 pop {r4, pc} 8001094: 50000800 .word 0x50000800 08001098 : /* USER CODE END DAC1_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void DAC_Start() { 8001098: b510 push {r4, lr} HAL_DAC_Start(&hdac1, DAC_CHANNEL_1); 800109a: 4c09 ldr r4, [pc, #36] ; (80010c0 ) 800109c: 2100 movs r1, #0 800109e: 4620 mov r0, r4 80010a0: f001 f8ea bl 8002278 HAL_DAC_Start(&hdac1, DAC_CHANNEL_2); 80010a4: 4620 mov r0, r4 80010a6: 2110 movs r1, #16 80010a8: f001 f8e6 bl 8002278 HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 2047); 80010ac: 2200 movs r2, #0 80010ae: 4620 mov r0, r4 80010b0: 4611 mov r1, r2 } 80010b2: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 2047); 80010b6: f240 73ff movw r3, #2047 ; 0x7ff 80010ba: f001 b927 b.w 800230c 80010be: bf00 nop 80010c0: 20000cf8 .word 0x20000cf8 080010c4 : */ void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); 80010c4: 4b0a ldr r3, [pc, #40] ; (80010f0 ) 80010c6: 6c9a ldr r2, [r3, #72] ; 0x48 80010c8: f042 0204 orr.w r2, r2, #4 80010cc: 649a str r2, [r3, #72] ; 0x48 80010ce: 6c9a ldr r2, [r3, #72] ; 0x48 { 80010d0: b082 sub sp, #8 __HAL_RCC_DMAMUX1_CLK_ENABLE(); 80010d2: f002 0204 and.w r2, r2, #4 80010d6: 9200 str r2, [sp, #0] 80010d8: 9a00 ldr r2, [sp, #0] __HAL_RCC_DMA1_CLK_ENABLE(); 80010da: 6c9a ldr r2, [r3, #72] ; 0x48 80010dc: f042 0201 orr.w r2, r2, #1 80010e0: 649a str r2, [r3, #72] ; 0x48 80010e2: 6c9b ldr r3, [r3, #72] ; 0x48 80010e4: f003 0301 and.w r3, r3, #1 80010e8: 9301 str r3, [sp, #4] 80010ea: 9b01 ldr r3, [sp, #4] } 80010ec: b002 add sp, #8 80010ee: 4770 bx lr 80010f0: 40021000 .word 0x40021000 080010f4 : /* USER CODE END 1 */ /** Configure pins */ void MX_GPIO_Init(void) { 80010f4: b530 push {r4, r5, lr} GPIO_InitTypeDef GPIO_InitStruct = {0}; 80010f6: 2200 movs r2, #0 { 80010f8: b089 sub sp, #36 ; 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80010fa: e9cd 2205 strd r2, r2, [sp, #20] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80010fe: 4b0f ldr r3, [pc, #60] ; (800113c ) /*Configure GPIO pins : PBPin PBPin */ GPIO_InitStruct.Pin = TRIG_Pin|VOCT_JUMPER_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_PULLUP; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001100: 480f ldr r0, [pc, #60] ; (8001140 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8001102: 6cda ldr r2, [r3, #76] ; 0x4c 8001104: f042 0201 orr.w r2, r2, #1 8001108: 64da str r2, [r3, #76] ; 0x4c 800110a: 6cda ldr r2, [r3, #76] ; 0x4c 800110c: f002 0201 and.w r2, r2, #1 8001110: 9200 str r2, [sp, #0] 8001112: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001114: 6cda ldr r2, [r3, #76] ; 0x4c 8001116: f042 0202 orr.w r2, r2, #2 800111a: 64da str r2, [r3, #76] ; 0x4c 800111c: 6cdb ldr r3, [r3, #76] ; 0x4c 800111e: f003 0302 and.w r3, r3, #2 8001122: 9301 str r3, [sp, #4] GPIO_InitStruct.Pin = TRIG_Pin|VOCT_JUMPER_Pin; 8001124: 2288 movs r2, #136 ; 0x88 8001126: 2300 movs r3, #0 GPIO_InitStruct.Pull = GPIO_PULLUP; 8001128: 2401 movs r4, #1 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800112a: a902 add r1, sp, #8 GPIO_InitStruct.Pin = TRIG_Pin|VOCT_JUMPER_Pin; 800112c: e9cd 2302 strd r2, r3, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001130: 9d01 ldr r5, [sp, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8001132: 9404 str r4, [sp, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001134: f001 faea bl 800270c } 8001138: b009 add sp, #36 ; 0x24 800113a: bd30 pop {r4, r5, pc} 800113c: 40021000 .word 0x40021000 8001140: 48000400 .word 0x48000400 08001144 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8001144: b530 push {r4, r5, lr} 8001146: b095 sub sp, #84 ; 0x54 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001148: 2238 movs r2, #56 ; 0x38 800114a: 2100 movs r1, #0 800114c: a806 add r0, sp, #24 800114e: f002 fb57 bl 8003800 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001152: 2300 movs r3, #0 /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8001154: f44f 7000 mov.w r0, #512 ; 0x200 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001158: e9cd 3300 strd r3, r3, [sp] 800115c: e9cd 3302 strd r3, r3, [sp, #8] 8001160: 9304 str r3, [sp, #16] HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8001162: f001 fbd7 bl 8002914 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8001166: 2302 movs r3, #2 RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8001168: e9cd 330d strd r3, r3, [sp, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; RCC_OscInitStruct.PLL.PLLN = 8; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 800116c: e9cd 3311 strd r3, r3, [sp, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 8001170: 2401 movs r4, #1 RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001172: f44f 7180 mov.w r1, #256 ; 0x100 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8001176: 2240 movs r2, #64 ; 0x40 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8001178: 9306 str r3, [sp, #24] RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 800117a: 9313 str r3, [sp, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800117c: a806 add r0, sp, #24 RCC_OscInitStruct.PLL.PLLN = 8; 800117e: 2308 movs r3, #8 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8001180: e9cd 1209 strd r1, r2, [sp, #36] ; 0x24 RCC_OscInitStruct.PLL.PLLN = 8; 8001184: e9cd 430f strd r4, r3, [sp, #60] ; 0x3c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001188: f001 fc4a bl 8002a20 800118c: b108 cbz r0, 8001192 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 800118e: b672 cpsid i void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 8001190: e7fe b.n 8001190 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001192: 4603 mov r3, r0 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 8001194: 4621 mov r1, r4 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001196: 2503 movs r5, #3 8001198: 240f movs r4, #15 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800119a: 9304 str r3, [sp, #16] RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800119c: 2200 movs r2, #0 800119e: 2300 movs r3, #0 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80011a0: 4668 mov r0, sp RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80011a2: e9cd 4500 strd r4, r5, [sp] 80011a6: e9cd 2302 strd r2, r3, [sp, #8] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80011aa: f001 febd bl 8002f28 80011ae: b108 cbz r0, 80011b4 80011b0: b672 cpsid i while (1) { 80011b2: e7fe b.n 80011b2 } 80011b4: b015 add sp, #84 ; 0x54 80011b6: bd30 pop {r4, r5, pc} 080011b8

: { 80011b8: b5f8 push {r3, r4, r5, r6, r7, lr} HAL_Init(); 80011ba: f000 fa27 bl 800160c SystemClock_Config(); 80011be: f7ff ffc1 bl 8001144 MX_GPIO_Init(); 80011c2: f7ff ff97 bl 80010f4 MX_DMA_Init(); 80011c6: f7ff ff7d bl 80010c4 MX_ADC1_Init(); 80011ca: f7ff fd07 bl 8000bdc MX_ADC2_Init(); 80011ce: f7ff fda9 bl 8000d24 MX_DAC1_Init(); 80011d2: f7ff fef7 bl 8000fc4 MX_TIM2_Init(); 80011d6: f000 f90b bl 80013f0 MX_TIM3_Init(); 80011da: f000 f943 bl 8001464 ADC_Start(); 80011de: f7ff fec7 bl 8000f70 TIM_Start(); 80011e2: f000 f9b5 bl 8001550 DAC_Start(); 80011e6: f7ff ff57 bl 8001098 dynamic_smooth_init(&dynamic_smooth_a, 0.05f, 0.5f); 80011ea: ed9f 0a2d vldr s0, [pc, #180] ; 80012a0 80011ee: 482d ldr r0, [pc, #180] ; (80012a4 ) VREFINT_CAL = *VREFINT_CAL_ADDR; 80011f0: 4f2d ldr r7, [pc, #180] ; (80012a8 ) 80011f2: 4e2e ldr r6, [pc, #184] ; (80012ac ) dynamic_smooth_init(&dynamic_smooth_a, 0.05f, 0.5f); 80011f4: eef6 0a00 vmov.f32 s1, #96 ; 0x3f000000 0.5 80011f8: f7ff fcb0 bl 8000b5c adsr_structinit(&OP1.ADSR); 80011fc: 482c ldr r0, [pc, #176] ; (80012b0 ) 80011fe: f7ff fa4f bl 80006a0 VREFINT_CAL = *VREFINT_CAL_ADDR; 8001202: 4b2c ldr r3, [pc, #176] ; (80012b4 ) 8001204: 881b ldrh r3, [r3, #0] 8001206: 803b strh r3, [r7, #0] while (adc1_data[VREFINT_PIN] == 0) { 8001208: 8973 ldrh r3, [r6, #10] 800120a: b29b uxth r3, r3 800120c: 2b00 cmp r3, #0 800120e: d0fb beq.n 8001208 8001210: 4d29 ldr r5, [pc, #164] ; (80012b8 ) 8001212: 4c2a ldr r4, [pc, #168] ; (80012bc ) vdd_mv += ((3000.0f * VREFINT_CAL / (float)(adc1_data[VREFINT_PIN])) - vdd_mv) * 0.2f; 8001214: eddf 5a2a vldr s11, [pc, #168] ; 80012c0 8001218: ed9f 6a2a vldr s12, [pc, #168] ; 80012c4 800121c: 883a ldrh r2, [r7, #0] 800121e: 8970 ldrh r0, [r6, #10] 8001220: 8821 ldrh r1, [r4, #0] 8001222: 8823 ldrh r3, [r4, #0] 8001224: b292 uxth r2, r2 8001226: ee07 2a90 vmov s15, r2 800122a: b280 uxth r0, r0 800122c: eef8 7ae7 vcvt.f32.s32 s15, s15 8001230: ee07 0a10 vmov s14, r0 8001234: ee67 7aa5 vmul.f32 s15, s15, s11 8001238: eeb8 7a47 vcvt.f32.u32 s14, s14 800123c: b289 uxth r1, r1 800123e: eec7 6a87 vdiv.f32 s13, s15, s14 8001242: b29b uxth r3, r3 for(int i=0; i<100000; i++) { 8001244: 3d01 subs r5, #1 vdd_mv += ((3000.0f * VREFINT_CAL / (float)(adc1_data[VREFINT_PIN])) - vdd_mv) * 0.2f; 8001246: ee07 1a10 vmov s14, r1 800124a: ee07 3a90 vmov s15, r3 800124e: eeb8 7ac7 vcvt.f32.s32 s14, s14 8001252: eef8 7ae7 vcvt.f32.s32 s15, s15 8001256: ee36 7ac7 vsub.f32 s14, s13, s14 800125a: eee7 7a06 vfma.f32 s15, s14, s12 800125e: eefc 7ae7 vcvt.u32.f32 s15, s15 8001262: ee17 3a90 vmov r3, s15 8001266: b29b uxth r3, r3 8001268: 8023 strh r3, [r4, #0] for(int i=0; i<100000; i++) { 800126a: d1d7 bne.n 800121c khz_correction = 3300.0f / vdd_mv; 800126c: 8823 ldrh r3, [r4, #0] 800126e: eddf 6a16 vldr s13, [pc, #88] ; 80012c8 8001272: 4816 ldr r0, [pc, #88] ; (80012cc ) khz_in_mv = adc2_data[KHZ_JACK] * 3300 >> 12; 8001274: 4a16 ldr r2, [pc, #88] ; (80012d0 ) 8001276: 4917 ldr r1, [pc, #92] ; (80012d4 ) khz_correction = 3300.0f / vdd_mv; 8001278: b29b uxth r3, r3 800127a: ee07 3a90 vmov s15, r3 800127e: eef8 7ae7 vcvt.f32.s32 s15, s15 khz_in_mv = adc2_data[KHZ_JACK] * 3300 >> 12; 8001282: f640 43e4 movw r3, #3300 ; 0xce4 khz_correction = 3300.0f / vdd_mv; 8001286: ee86 7aa7 vdiv.f32 s14, s13, s15 800128a: ed80 7a00 vstr s14, [r0] khz_in_mv = adc2_data[KHZ_JACK] * 3300 >> 12; 800128e: 8812 ldrh r2, [r2, #0] 8001290: b292 uxth r2, r2 8001292: fb03 f302 mul.w r3, r3, r2 8001296: 0b1b lsrs r3, r3, #12 8001298: 800b strh r3, [r1, #0] loop(); 800129a: f7ff fc9d bl 8000bd8 while (1) { 800129e: e7fc b.n 800129a 80012a0: 3d4ccccd .word 0x3d4ccccd 80012a4: 20000ad4 .word 0x20000ad4 80012a8: 20000892 .word 0x20000892 80012ac: 200008bc .word 0x200008bc 80012b0: 20000858 .word 0x20000858 80012b4: 1fff75aa .word 0x1fff75aa 80012b8: 000186a0 .word 0x000186a0 80012bc: 20000890 .word 0x20000890 80012c0: 453b8000 .word 0x453b8000 80012c4: 3e4ccccd .word 0x3e4ccccd 80012c8: 454e4000 .word 0x454e4000 80012cc: 200008ac .word 0x200008ac 80012d0: 200008a4 .word 0x200008a4 80012d4: 20000834 .word 0x20000834 080012d8 : 80012d8: b672 cpsid i while (1) { 80012da: e7fe b.n 80012da 080012dc : { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80012dc: 4b0b ldr r3, [pc, #44] ; (800130c ) 80012de: 6e1a ldr r2, [r3, #96] ; 0x60 80012e0: f042 0201 orr.w r2, r2, #1 80012e4: 661a str r2, [r3, #96] ; 0x60 80012e6: 6e1a ldr r2, [r3, #96] ; 0x60 { 80012e8: b082 sub sp, #8 __HAL_RCC_SYSCFG_CLK_ENABLE(); 80012ea: f002 0201 and.w r2, r2, #1 80012ee: 9200 str r2, [sp, #0] 80012f0: 9a00 ldr r2, [sp, #0] __HAL_RCC_PWR_CLK_ENABLE(); 80012f2: 6d9a ldr r2, [r3, #88] ; 0x58 80012f4: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 80012f8: 659a str r2, [r3, #88] ; 0x58 80012fa: 6d9b ldr r3, [r3, #88] ; 0x58 80012fc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001300: 9301 str r3, [sp, #4] 8001302: 9b01 ldr r3, [sp, #4] HAL_PWREx_DisableUCPDDeadBattery(); /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001304: b002 add sp, #8 HAL_PWREx_DisableUCPDDeadBattery(); 8001306: f001 bb83 b.w 8002a10 800130a: bf00 nop 800130c: 40021000 .word 0x40021000 08001310 : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) { 8001310: e7fe b.n 8001310 8001312: bf00 nop 08001314 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001314: e7fe b.n 8001314 8001316: bf00 nop 08001318 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001318: e7fe b.n 8001318 800131a: bf00 nop 0800131c : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800131c: e7fe b.n 800131c 800131e: bf00 nop 08001320 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001320: e7fe b.n 8001320 8001322: bf00 nop 08001324 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001324: 4770 bx lr 8001326: bf00 nop 08001328 : 8001328: 4770 bx lr 800132a: bf00 nop 0800132c : 800132c: 4770 bx lr 800132e: bf00 nop 08001330 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001330: f000 b97c b.w 800162c 08001334 : #if 0 /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); /* USER CODE BEGIN TIM2_IRQn 1 */ #endif if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET) { 8001334: 4b06 ldr r3, [pc, #24] ; (8001350 ) 8001336: 681b ldr r3, [r3, #0] 8001338: 691a ldr r2, [r3, #16] 800133a: 07d1 lsls r1, r2, #31 800133c: d502 bpl.n 8001344 if (__HAL_TIM_GET_IT_SOURCE(&htim2, TIM_IT_UPDATE) != RESET) { 800133e: 68da ldr r2, [r3, #12] 8001340: 07d2 lsls r2, r2, #31 8001342: d400 bmi.n 8001346 __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); main_2OP_loop(); } } /* USER CODE END TIM2_IRQn 1 */ } 8001344: 4770 bx lr __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); 8001346: f06f 0201 mvn.w r2, #1 800134a: 611a str r2, [r3, #16] main_2OP_loop(); 800134c: f7ff ba82 b.w 8000854 8001350: 20000d58 .word 0x20000d58 08001354 : /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { 8001354: b508 push {r3, lr} #endif /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ /* USER CODE BEGIN TIM3_IRQn 1 */ if (__HAL_TIM_GET_FLAG(&htim3, TIM_FLAG_UPDATE) != RESET) { 8001356: 4b1a ldr r3, [pc, #104] ; (80013c0 ) 8001358: 681b ldr r3, [r3, #0] 800135a: 691a ldr r2, [r3, #16] 800135c: 07d1 lsls r1, r2, #31 800135e: d529 bpl.n 80013b4 if (__HAL_TIM_GET_IT_SOURCE(&htim3, TIM_IT_UPDATE) != RESET) { 8001360: 68da ldr r2, [r3, #12] 8001362: 07d2 lsls r2, r2, #31 8001364: d526 bpl.n 80013b4 __HAL_TIM_CLEAR_IT(&htim3, TIM_IT_UPDATE); for (uint8_t i = 0; i < (NUM_ADC1_CHANNELS - 1); i++) { adc1_data_10b[i] = adc1_data[i] >> 2; 8001366: 4a17 ldr r2, [pc, #92] ; (80013c4 ) } run_linear_a_expo_r(&OP1.ADSR); 8001368: 4817 ldr r0, [pc, #92] ; (80013c8 ) __HAL_TIM_CLEAR_IT(&htim3, TIM_IT_UPDATE); 800136a: f06f 0101 mvn.w r1, #1 800136e: 6119 str r1, [r3, #16] adc1_data_10b[i] = adc1_data[i] >> 2; 8001370: 8811 ldrh r1, [r2, #0] 8001372: 4b16 ldr r3, [pc, #88] ; (80013cc ) 8001374: f3c1 018d ubfx r1, r1, #2, #14 8001378: 8019 strh r1, [r3, #0] 800137a: 8851 ldrh r1, [r2, #2] 800137c: f3c1 018d ubfx r1, r1, #2, #14 8001380: 8059 strh r1, [r3, #2] 8001382: 8891 ldrh r1, [r2, #4] 8001384: f3c1 018d ubfx r1, r1, #2, #14 8001388: 8099 strh r1, [r3, #4] 800138a: 88d1 ldrh r1, [r2, #6] 800138c: f3c1 018d ubfx r1, r1, #2, #14 8001390: 80d9 strh r1, [r3, #6] 8001392: 8912 ldrh r2, [r2, #8] 8001394: f3c2 028d ubfx r2, r2, #2, #14 8001398: 811a strh r2, [r3, #8] run_linear_a_expo_r(&OP1.ADSR); 800139a: f7ff f999 bl 80006d0 set_adsr_parameters(&OP1.ADSR); 800139e: 480a ldr r0, [pc, #40] ; (80013c8 ) 80013a0: f7ff fa0e bl 80007c0 #ifndef VOCT if(HAL_GPIO_ReadPin(VOCT_JUMPER_GPIO_Port, VOCT_JUMPER_Pin) == 0) { 80013a4: 480a ldr r0, [pc, #40] ; (80013d0 ) 80013a6: 2180 movs r1, #128 ; 0x80 80013a8: f001 faae bl 8002908 khz_in_scaling = VOCT_SCALE; 80013ac: 4b09 ldr r3, [pc, #36] ; (80013d4 ) if(HAL_GPIO_ReadPin(VOCT_JUMPER_GPIO_Port, VOCT_JUMPER_Pin) == 0) { 80013ae: b910 cbnz r0, 80013b6 khz_in_scaling = VOCT_SCALE; 80013b0: 4a09 ldr r2, [pc, #36] ; (80013d8 ) 80013b2: 601a str r2, [r3, #0] khz_in_scaling = VOCT_SCALE; #endif } } /* USER CODE END TIM3_IRQn 1 */ } 80013b4: bd08 pop {r3, pc} khz_in_scaling = WIDE_SCALE; 80013b6: f04f 527a mov.w r2, #1048576000 ; 0x3e800000 80013ba: 601a str r2, [r3, #0] } 80013bc: bd08 pop {r3, pc} 80013be: bf00 nop 80013c0: 20000d0c .word 0x20000d0c 80013c4: 200008bc .word 0x200008bc 80013c8: 20000858 .word 0x20000858 80013cc: 20000b54 .word 0x20000b54 80013d0: 48000400 .word 0x48000400 80013d4: 20000800 .word 0x20000800 80013d8: 3e16d5a4 .word 0x3e16d5a4 080013dc : void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 80013dc: 4a03 ldr r2, [pc, #12] ; (80013ec ) 80013de: f8d2 3088 ldr.w r3, [r2, #136] ; 0x88 80013e2: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 80013e6: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 80013ea: 4770 bx lr 80013ec: e000ed00 .word 0xe000ed00 080013f0 : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM2 init function */ void MX_TIM2_Init(void) { 80013f0: b500 push {lr} TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80013f2: 481b ldr r0, [pc, #108] ; (8001460 ) { 80013f4: b089 sub sp, #36 ; 0x24 htim2.Instance = TIM2; 80013f6: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 htim2.Init.Prescaler = 0; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 1600; 80013fa: f44f 62c8 mov.w r2, #1600 ; 0x640 htim2.Instance = TIM2; 80013fe: 6003 str r3, [r0, #0] TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001400: 2300 movs r3, #0 8001402: e9cd 3305 strd r3, r3, [sp, #20] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001406: e9cd 3302 strd r3, r3, [sp, #8] htim2.Init.Period = 1600; 800140a: 60c2 str r2, [r0, #12] htim2.Init.Prescaler = 0; 800140c: 6043 str r3, [r0, #4] TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800140e: 9304 str r3, [sp, #16] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001410: 9301 str r3, [sp, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 8001412: 6083 str r3, [r0, #8] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001414: 6103 str r3, [r0, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001416: 6183 str r3, [r0, #24] TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001418: 9307 str r3, [sp, #28] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 800141a: f001 ffe9 bl 80033f0 800141e: b998 cbnz r0, 8001448 { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001420: f44f 5380 mov.w r3, #4096 ; 0x1000 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 8001424: 480e ldr r0, [pc, #56] ; (8001460 ) sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001426: 9304 str r3, [sp, #16] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 8001428: a904 add r1, sp, #16 800142a: f002 f8a9 bl 8003580 800142e: b998 cbnz r0, 8001458 { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001430: 2220 movs r2, #32 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8001432: 2300 movs r3, #0 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8001434: 480a ldr r0, [pc, #40] ; (8001460 ) sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001436: 9201 str r2, [sp, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8001438: a901 add r1, sp, #4 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800143a: 9303 str r3, [sp, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800143c: f002 f974 bl 8003728 8001440: b928 cbnz r0, 800144e } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 8001442: b009 add sp, #36 ; 0x24 8001444: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8001448: f7ff ff46 bl 80012d8 800144c: e7e8 b.n 8001420 Error_Handler(); 800144e: f7ff ff43 bl 80012d8 } 8001452: b009 add sp, #36 ; 0x24 8001454: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8001458: f7ff ff3e bl 80012d8 800145c: e7e8 b.n 8001430 800145e: bf00 nop 8001460: 20000d58 .word 0x20000d58 08001464 : /* TIM3 init function */ void MX_TIM3_Init(void) { 8001464: b500 push {lr} TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001466: 481a ldr r0, [pc, #104] ; (80014d0 ) 8001468: 4b1a ldr r3, [pc, #104] ; (80014d4 ) 800146a: 6003 str r3, [r0, #0] { 800146c: b089 sub sp, #36 ; 0x24 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800146e: 2300 movs r3, #0 htim3.Init.Prescaler = 0; htim3.Init.CounterMode = TIM_COUNTERMODE_UP; htim3.Init.Period = 12800; 8001470: f44f 5248 mov.w r2, #12800 ; 0x3200 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001474: e9cd 3305 strd r3, r3, [sp, #20] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001478: e9cd 3302 strd r3, r3, [sp, #8] htim3.Init.Period = 12800; 800147c: 60c2 str r2, [r0, #12] htim3.Init.Prescaler = 0; 800147e: 6043 str r3, [r0, #4] TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001480: 9304 str r3, [sp, #16] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001482: 9301 str r3, [sp, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001484: 6083 str r3, [r0, #8] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001486: 6103 str r3, [r0, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001488: 6183 str r3, [r0, #24] TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800148a: 9307 str r3, [sp, #28] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800148c: f001 ffb0 bl 80033f0 8001490: b998 cbnz r0, 80014ba { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001492: f44f 5380 mov.w r3, #4096 ; 0x1000 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8001496: 480e ldr r0, [pc, #56] ; (80014d0 ) sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001498: 9304 str r3, [sp, #16] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800149a: a904 add r1, sp, #16 800149c: f002 f870 bl 8003580 80014a0: b998 cbnz r0, 80014ca { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80014a2: 2220 movs r2, #32 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80014a4: 2300 movs r3, #0 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80014a6: 480a ldr r0, [pc, #40] ; (80014d0 ) sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80014a8: 9201 str r2, [sp, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80014aa: a901 add r1, sp, #4 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80014ac: 9303 str r3, [sp, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80014ae: f002 f93b bl 8003728 80014b2: b928 cbnz r0, 80014c0 } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 80014b4: b009 add sp, #36 ; 0x24 80014b6: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 80014ba: f7ff ff0d bl 80012d8 80014be: e7e8 b.n 8001492 Error_Handler(); 80014c0: f7ff ff0a bl 80012d8 } 80014c4: b009 add sp, #36 ; 0x24 80014c6: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 80014ca: f7ff ff05 bl 80012d8 80014ce: e7e8 b.n 80014a2 80014d0: 20000d0c .word 0x20000d0c 80014d4: 40000400 .word 0x40000400 080014d8 : void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { 80014d8: b500 push {lr} if(tim_baseHandle->Instance==TIM2) 80014da: 6803 ldr r3, [r0, #0] 80014dc: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 { 80014e0: b083 sub sp, #12 if(tim_baseHandle->Instance==TIM2) 80014e2: d005 beq.n 80014f0 HAL_NVIC_EnableIRQ(TIM2_IRQn); /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } else if(tim_baseHandle->Instance==TIM3) 80014e4: 4a18 ldr r2, [pc, #96] ; (8001548 ) 80014e6: 4293 cmp r3, r2 80014e8: d018 beq.n 800151c HAL_NVIC_EnableIRQ(TIM3_IRQn); /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80014ea: b003 add sp, #12 80014ec: f85d fb04 ldr.w pc, [sp], #4 __HAL_RCC_TIM2_CLK_ENABLE(); 80014f0: f503 3304 add.w r3, r3, #135168 ; 0x21000 HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 80014f4: 201c movs r0, #28 __HAL_RCC_TIM2_CLK_ENABLE(); 80014f6: 6d9a ldr r2, [r3, #88] ; 0x58 80014f8: f042 0201 orr.w r2, r2, #1 80014fc: 659a str r2, [r3, #88] ; 0x58 80014fe: 6d9b ldr r3, [r3, #88] ; 0x58 HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 8001500: 2200 movs r2, #0 __HAL_RCC_TIM2_CLK_ENABLE(); 8001502: f003 0301 and.w r3, r3, #1 8001506: 9300 str r3, [sp, #0] HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 8001508: 4611 mov r1, r2 __HAL_RCC_TIM2_CLK_ENABLE(); 800150a: 9b00 ldr r3, [sp, #0] HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 800150c: f000 fe3e bl 800218c HAL_NVIC_EnableIRQ(TIM2_IRQn); 8001510: 201c movs r0, #28 } 8001512: b003 add sp, #12 8001514: f85d eb04 ldr.w lr, [sp], #4 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8001518: f000 be70 b.w 80021fc __HAL_RCC_TIM3_CLK_ENABLE(); 800151c: 4b0b ldr r3, [pc, #44] ; (800154c ) 800151e: 6d9a ldr r2, [r3, #88] ; 0x58 8001520: f042 0202 orr.w r2, r2, #2 8001524: 659a str r2, [r3, #88] ; 0x58 8001526: 6d9b ldr r3, [r3, #88] ; 0x58 8001528: f003 0302 and.w r3, r3, #2 800152c: 9301 str r3, [sp, #4] HAL_NVIC_SetPriority(TIM3_IRQn, 1, 0); 800152e: 2200 movs r2, #0 8001530: 2101 movs r1, #1 8001532: 201d movs r0, #29 __HAL_RCC_TIM3_CLK_ENABLE(); 8001534: 9b01 ldr r3, [sp, #4] HAL_NVIC_SetPriority(TIM3_IRQn, 1, 0); 8001536: f000 fe29 bl 800218c HAL_NVIC_EnableIRQ(TIM3_IRQn); 800153a: 201d movs r0, #29 } 800153c: b003 add sp, #12 800153e: f85d eb04 ldr.w lr, [sp], #4 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8001542: f000 be5b b.w 80021fc 8001546: bf00 nop 8001548: 40000400 .word 0x40000400 800154c: 40021000 .word 0x40021000 08001550 : /* USER CODE END TIM3_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void TIM_Start() { 8001550: b508 push {r3, lr} HAL_TIM_Base_Start_IT(&htim2); 8001552: 4804 ldr r0, [pc, #16] ; (8001564 ) 8001554: f001 ffda bl 800350c HAL_TIM_Base_Start_IT(&htim3); } 8001558: e8bd 4008 ldmia.w sp!, {r3, lr} HAL_TIM_Base_Start_IT(&htim3); 800155c: 4802 ldr r0, [pc, #8] ; (8001568 ) 800155e: f001 bfd5 b.w 800350c 8001562: bf00 nop 8001564: 20000d58 .word 0x20000d58 8001568: 20000d0c .word 0x20000d0c 0800156c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 800156c: 480d ldr r0, [pc, #52] ; (80015a4 ) mov sp, r0 /* set stack pointer */ 800156e: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8001570: f7ff ff34 bl 80013dc /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001574: 480c ldr r0, [pc, #48] ; (80015a8 ) ldr r1, =_edata 8001576: 490d ldr r1, [pc, #52] ; (80015ac ) ldr r2, =_sidata 8001578: 4a0d ldr r2, [pc, #52] ; (80015b0 ) movs r3, #0 800157a: 2300 movs r3, #0 b LoopCopyDataInit 800157c: e002 b.n 8001584 0800157e : CopyDataInit: ldr r4, [r2, r3] 800157e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001580: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001582: 3304 adds r3, #4 08001584 : LoopCopyDataInit: adds r4, r0, r3 8001584: 18c4 adds r4, r0, r3 cmp r4, r1 8001586: 428c cmp r4, r1 bcc CopyDataInit 8001588: d3f9 bcc.n 800157e /* Zero fill the bss segment. */ ldr r2, =_sbss 800158a: 4a0a ldr r2, [pc, #40] ; (80015b4 ) ldr r4, =_ebss 800158c: 4c0a ldr r4, [pc, #40] ; (80015b8 ) movs r3, #0 800158e: 2300 movs r3, #0 b LoopFillZerobss 8001590: e001 b.n 8001596 08001592 : FillZerobss: str r3, [r2] 8001592: 6013 str r3, [r2, #0] adds r2, r2, #4 8001594: 3204 adds r2, #4 08001596 : LoopFillZerobss: cmp r2, r4 8001596: 42a2 cmp r2, r4 bcc FillZerobss 8001598: d3fb bcc.n 8001592 /* Call static constructors */ bl __libc_init_array 800159a: f002 f90d bl 80037b8 <__libc_init_array> /* Call the application's entry point.*/ bl main 800159e: f7ff fe0b bl 80011b8
080015a2 : LoopForever: b LoopForever 80015a2: e7fe b.n 80015a2 ldr r0, =_estack 80015a4: 20008000 .word 0x20008000 ldr r0, =_sdata 80015a8: 20000000 .word 0x20000000 ldr r1, =_edata 80015ac: 20000810 .word 0x20000810 ldr r2, =_sidata 80015b0: 08004040 .word 0x08004040 ldr r2, =_sbss 80015b4: 20000810 .word 0x20000810 ldr r4, =_ebss 80015b8: 20000da8 .word 0x20000da8 080015bc : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80015bc: e7fe b.n 80015bc ... 080015c0 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80015c0: b538 push {r3, r4, r5, lr} HAL_StatusTypeDef status = HAL_OK; if (uwTickFreq != 0U) 80015c2: 4b0f ldr r3, [pc, #60] ; (8001600 ) 80015c4: 681b ldr r3, [r3, #0] 80015c6: b90b cbnz r3, 80015cc status = HAL_ERROR; } } else { status = HAL_ERROR; 80015c8: 2001 movs r0, #1 } /* Return function status */ return status; } 80015ca: bd38 pop {r3, r4, r5, pc} if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) 80015cc: 490d ldr r1, [pc, #52] ; (8001604 ) 80015ce: f44f 727a mov.w r2, #1000 ; 0x3e8 80015d2: 4605 mov r5, r0 80015d4: fbb2 f3f3 udiv r3, r2, r3 80015d8: 6808 ldr r0, [r1, #0] 80015da: fbb0 f0f3 udiv r0, r0, r3 80015de: f000 fe1b bl 8002218 80015e2: 4604 mov r4, r0 80015e4: 2800 cmp r0, #0 80015e6: d1ef bne.n 80015c8 if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80015e8: 2d0f cmp r5, #15 80015ea: d8ed bhi.n 80015c8 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80015ec: 4602 mov r2, r0 80015ee: 4629 mov r1, r5 80015f0: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 80015f4: f000 fdca bl 800218c uwTickPrio = TickPriority; 80015f8: 4b03 ldr r3, [pc, #12] ; (8001608 ) 80015fa: 4620 mov r0, r4 80015fc: 601d str r5, [r3, #0] } 80015fe: bd38 pop {r3, r4, r5, pc} 8001600: 20000808 .word 0x20000808 8001604: 20000804 .word 0x20000804 8001608: 2000080c .word 0x2000080c 0800160c : { 800160c: b510 push {r4, lr} HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800160e: 2003 movs r0, #3 8001610: f000 fda8 bl 8002164 if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8001614: 200f movs r0, #15 8001616: f7ff ffd3 bl 80015c0 800161a: b110 cbz r0, 8001622 status = HAL_ERROR; 800161c: 2401 movs r4, #1 } 800161e: 4620 mov r0, r4 8001620: bd10 pop {r4, pc} 8001622: 4604 mov r4, r0 HAL_MspInit(); 8001624: f7ff fe5a bl 80012dc } 8001628: 4620 mov r0, r4 800162a: bd10 pop {r4, pc} 0800162c : * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; 800162c: 4a03 ldr r2, [pc, #12] ; (800163c ) 800162e: 4904 ldr r1, [pc, #16] ; (8001640 ) 8001630: 6813 ldr r3, [r2, #0] 8001632: 6809 ldr r1, [r1, #0] 8001634: 440b add r3, r1 8001636: 6013 str r3, [r2, #0] } 8001638: 4770 bx lr 800163a: bf00 nop 800163c: 20000da4 .word 0x20000da4 8001640: 20000808 .word 0x20000808 08001644 : * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; 8001644: 4b01 ldr r3, [pc, #4] ; (800164c ) 8001646: 6818 ldr r0, [r3, #0] } 8001648: 4770 bx lr 800164a: bf00 nop 800164c: 20000da4 .word 0x20000da4 08001650 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8001650: b570 push {r4, r5, r6, lr} 8001652: b082 sub sp, #8 HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_cfgr; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0UL; 8001654: 2300 movs r3, #0 8001656: 9301 str r3, [sp, #4] /* Check ADC handle */ if (hadc == NULL) 8001658: 2800 cmp r0, #0 800165a: f000 80d0 beq.w 80017fe /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800165e: 6dc5 ldr r5, [r0, #92] ; 0x5c 8001660: 4604 mov r4, r0 8001662: 2d00 cmp r5, #0 8001664: f000 80b8 beq.w 80017d8 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8001668: 6822 ldr r2, [r4, #0] * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 800166a: 6893 ldr r3, [r2, #8] 800166c: 0098 lsls r0, r3, #2 800166e: d505 bpl.n 800167c CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8001670: 6893 ldr r3, [r2, #8] 8001672: f023 4320 bic.w r3, r3, #2684354560 ; 0xa0000000 8001676: f023 033f bic.w r3, r3, #63 ; 0x3f 800167a: 6093 str r3, [r2, #8] * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 800167c: 6893 ldr r3, [r2, #8] 800167e: 00d9 lsls r1, r3, #3 8001680: d419 bmi.n 80016b6 LL_ADC_EnableInternalRegulator(hadc->Instance); /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8001682: 4b6f ldr r3, [pc, #444] ; (8001840 ) 8001684: 486f ldr r0, [pc, #444] ; (8001844 ) 8001686: 681b ldr r3, [r3, #0] MODIFY_REG(ADCx->CR, 8001688: 6891 ldr r1, [r2, #8] 800168a: 099b lsrs r3, r3, #6 800168c: fba0 0303 umull r0, r3, r0, r3 8001690: 099b lsrs r3, r3, #6 8001692: f021 4110 bic.w r1, r1, #2415919104 ; 0x90000000 8001696: 3301 adds r3, #1 8001698: f021 013f bic.w r1, r1, #63 ; 0x3f 800169c: 005b lsls r3, r3, #1 800169e: f041 5180 orr.w r1, r1, #268435456 ; 0x10000000 80016a2: 6091 str r1, [r2, #8] 80016a4: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 80016a6: 9b01 ldr r3, [sp, #4] 80016a8: b12b cbz r3, 80016b6 { wait_loop_index--; 80016aa: 9b01 ldr r3, [sp, #4] 80016ac: 3b01 subs r3, #1 80016ae: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 80016b0: 9b01 ldr r3, [sp, #4] 80016b2: 2b00 cmp r3, #0 80016b4: d1f9 bne.n 80016aa return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 80016b6: 6893 ldr r3, [r2, #8] 80016b8: 00db lsls r3, r3, #3 80016ba: d47f bmi.n 80017bc /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80016bc: 6de3 ldr r3, [r4, #92] ; 0x5c 80016be: f043 0310 orr.w r3, r3, #16 80016c2: 65e3 str r3, [r4, #92] ; 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80016c4: 6e23 ldr r3, [r4, #96] ; 0x60 80016c6: f043 0301 orr.w r3, r3, #1 80016ca: 6623 str r3, [r4, #96] ; 0x60 * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80016cc: 6893 ldr r3, [r2, #8] 80016ce: f013 0f04 tst.w r3, #4 tmp_hal_status = HAL_ERROR; 80016d2: f04f 0001 mov.w r0, #1 /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 80016d6: 6de3 ldr r3, [r4, #92] ; 0x5c 80016d8: d177 bne.n 80017ca 80016da: 06de lsls r6, r3, #27 80016dc: d475 bmi.n 80017ca && (tmp_adc_is_conversion_on_going_regular == 0UL) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80016de: 6de3 ldr r3, [r4, #92] ; 0x5c 80016e0: f423 7381 bic.w r3, r3, #258 ; 0x102 80016e4: f043 0302 orr.w r3, r3, #2 80016e8: 65e3 str r3, [r4, #92] ; 0x5c return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80016ea: 6893 ldr r3, [r2, #8] /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80016ec: 07dd lsls r5, r3, #31 80016ee: d40e bmi.n 800170e 80016f0: 4b55 ldr r3, [pc, #340] ; (8001848 ) 80016f2: f04f 41a0 mov.w r1, #1342177280 ; 0x50000000 80016f6: 6889 ldr r1, [r1, #8] 80016f8: 689b ldr r3, [r3, #8] { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80016fa: 430b orrs r3, r1 80016fc: 07d9 lsls r1, r3, #31 80016fe: d406 bmi.n 800170e MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8001700: 4952 ldr r1, [pc, #328] ; (800184c ) 8001702: 6865 ldr r5, [r4, #4] 8001704: 688b ldr r3, [r1, #8] 8001706: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 800170a: 432b orrs r3, r5 800170c: 608b str r3, [r1, #8] /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | hadc->Init.Overrun | hadc->Init.DataAlign | 800170e: e9d4 1502 ldrd r1, r5, [r4, #8] 8001712: 6be3 ldr r3, [r4, #60] ; 0x3c 8001714: 432b orrs r3, r5 8001716: 430b orrs r3, r1 tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001718: 7f65 ldrb r5, [r4, #29] hadc->Init.Resolution | ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 800171a: f894 1024 ldrb.w r1, [r4, #36] ; 0x24 hadc->Init.DataAlign | 800171e: ea43 3345 orr.w r3, r3, r5, lsl #13 if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001722: 2901 cmp r1, #1 tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001724: ea43 4301 orr.w r3, r3, r1, lsl #16 if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001728: d064 beq.n 80017f4 /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 800172a: 6ae1 ldr r1, [r4, #44] ; 0x2c 800172c: b121 cbz r1, 8001738 { tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) | hadc->Init.ExternalTrigConvEdge 800172e: 6b25 ldr r5, [r4, #48] ; 0x30 tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001730: f401 7178 and.w r1, r1, #992 ; 0x3e0 | hadc->Init.ExternalTrigConvEdge 8001734: 4329 orrs r1, r5 tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001736: 430b orrs r3, r1 ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); 8001738: 68d6 ldr r6, [r2, #12] 800173a: 4945 ldr r1, [pc, #276] ; (8001850 ) /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); 800173c: 6b65 ldr r5, [r4, #52] ; 0x34 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); 800173e: 4031 ands r1, r6 8001740: 430b orrs r3, r1 8001742: 60d3 str r3, [r2, #12] MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); 8001744: 6913 ldr r3, [r2, #16] 8001746: f023 6340 bic.w r3, r3, #201326592 ; 0xc000000 800174a: 432b orrs r3, r5 800174c: 6113 str r3, [r2, #16] * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 800174e: 6893 ldr r3, [r2, #8] 8001750: 071b lsls r3, r3, #28 8001752: d424 bmi.n 800179e { tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); 8001754: 68d1 ldr r1, [r2, #12] ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); 8001756: f894 3038 ldrb.w r3, [r4, #56] ; 0x38 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800175a: 7f26 ldrb r6, [r4, #28] if (hadc->Init.GainCompensation != 0UL) 800175c: 6925 ldr r5, [r4, #16] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); 800175e: f421 4180 bic.w r1, r1, #16384 ; 0x4000 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); 8001762: 005b lsls r3, r3, #1 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); 8001764: f021 0102 bic.w r1, r1, #2 tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | 8001768: ea43 3386 orr.w r3, r3, r6, lsl #14 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); 800176c: 430b orrs r3, r1 800176e: 60d3 str r3, [r2, #12] { SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8001770: 6913 ldr r3, [r2, #16] if (hadc->Init.GainCompensation != 0UL) 8001772: 2d00 cmp r5, #0 8001774: d046 beq.n 8001804 SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8001776: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800177a: 6113 str r3, [r2, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); 800177c: f8d2 30c0 ldr.w r3, [r2, #192] ; 0xc0 8001780: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 8001784: f023 033f bic.w r3, r3, #63 ; 0x3f 8001788: 432b orrs r3, r5 800178a: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0 { CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); } if (hadc->Init.OversamplingMode == ENABLE) 800178e: f894 3040 ldrb.w r3, [r4, #64] ; 0x40 8001792: 2b01 cmp r3, #1 8001794: d042 beq.n 800181c ); } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8001796: 6913 ldr r3, [r2, #16] 8001798: f023 0301 bic.w r3, r3, #1 800179c: 6113 str r3, [r2, #16] /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 800179e: 6963 ldr r3, [r4, #20] 80017a0: 2b01 cmp r3, #1 80017a2: d01f beq.n 80017e4 /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 80017a4: 6b13 ldr r3, [r2, #48] ; 0x30 80017a6: f023 030f bic.w r3, r3, #15 80017aa: 6313 str r3, [r2, #48] ; 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 80017ac: 6de3 ldr r3, [r4, #92] ; 0x5c 80017ae: f023 0303 bic.w r3, r3, #3 80017b2: f043 0301 orr.w r3, r3, #1 80017b6: 65e3 str r3, [r4, #92] ; 0x5c tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } 80017b8: b002 add sp, #8 80017ba: bd70 pop {r4, r5, r6, pc} return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80017bc: 6893 ldr r3, [r2, #8] 80017be: f013 0f04 tst.w r3, #4 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80017c2: f04f 0000 mov.w r0, #0 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 80017c6: 6de3 ldr r3, [r4, #92] ; 0x5c 80017c8: d087 beq.n 80016da SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80017ca: 6de3 ldr r3, [r4, #92] ; 0x5c tmp_hal_status = HAL_ERROR; 80017cc: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80017ce: f043 0310 orr.w r3, r3, #16 80017d2: 65e3 str r3, [r4, #92] ; 0x5c } 80017d4: b002 add sp, #8 80017d6: bd70 pop {r4, r5, r6, pc} HAL_ADC_MspInit(hadc); 80017d8: f7ff fafa bl 8000dd0 ADC_CLEAR_ERRORCODE(hadc); 80017dc: 6625 str r5, [r4, #96] ; 0x60 hadc->Lock = HAL_UNLOCKED; 80017de: f884 5058 strb.w r5, [r4, #88] ; 0x58 80017e2: e741 b.n 8001668 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 80017e4: 6b11 ldr r1, [r2, #48] ; 0x30 80017e6: 6a23 ldr r3, [r4, #32] 80017e8: f021 010f bic.w r1, r1, #15 80017ec: 3b01 subs r3, #1 80017ee: 430b orrs r3, r1 80017f0: 6313 str r3, [r2, #48] ; 0x30 80017f2: e7db b.n 80017ac tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 80017f4: 6aa1 ldr r1, [r4, #40] ; 0x28 80017f6: 3901 subs r1, #1 80017f8: ea43 4341 orr.w r3, r3, r1, lsl #17 80017fc: e795 b.n 800172a return HAL_ERROR; 80017fe: 2001 movs r0, #1 } 8001800: b002 add sp, #8 8001802: bd70 pop {r4, r5, r6, pc} CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8001804: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001808: 6113 str r3, [r2, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); 800180a: f8d2 30c0 ldr.w r3, [r2, #192] ; 0xc0 800180e: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 8001812: f023 033f bic.w r3, r3, #63 ; 0x3f 8001816: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0 800181a: e7b8 b.n 800178e MODIFY_REG(hadc->Instance->CFGR2, 800181c: e9d4 3611 ldrd r3, r6, [r4, #68] ; 0x44 8001820: 6911 ldr r1, [r2, #16] 8001822: 6ce5 ldr r5, [r4, #76] ; 0x4c 8001824: f421 61ff bic.w r1, r1, #2040 ; 0x7f8 8001828: f021 0104 bic.w r1, r1, #4 800182c: 4333 orrs r3, r6 800182e: 430b orrs r3, r1 8001830: 6d21 ldr r1, [r4, #80] ; 0x50 8001832: 432b orrs r3, r5 8001834: 430b orrs r3, r1 8001836: f043 0301 orr.w r3, r3, #1 800183a: 6113 str r3, [r2, #16] 800183c: e7af b.n 800179e 800183e: bf00 nop 8001840: 20000804 .word 0x20000804 8001844: 053e2d63 .word 0x053e2d63 8001848: 50000100 .word 0x50000100 800184c: 50000300 .word 0x50000300 8001850: fff04007 .word 0xfff04007 08001854 : 8001854: 4770 bx lr 8001856: bf00 nop 08001858 : 8001858: 4770 bx lr 800185a: bf00 nop 0800185c : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800185c: b508 push {r3, lr} /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 800185e: 6a80 ldr r0, [r0, #40] ; 0x28 8001860: f7ff fffa bl 8001858 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8001864: bd08 pop {r3, pc} 8001866: bf00 nop 08001868 : 8001868: 4770 bx lr 800186a: bf00 nop 0800186c : ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800186c: 6a83 ldr r3, [r0, #40] ; 0x28 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 800186e: 6dda ldr r2, [r3, #92] ; 0x5c 8001870: f012 0f50 tst.w r2, #80 ; 0x50 { 8001874: b510 push {r4, lr} SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8001876: 6dda ldr r2, [r3, #92] ; 0x5c if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8001878: d11d bne.n 80018b6 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 800187a: 6819 ldr r1, [r3, #0] SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800187c: f442 7200 orr.w r2, r2, #512 ; 0x200 8001880: 65da str r2, [r3, #92] ; 0x5c if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8001882: 680a ldr r2, [r1, #0] 8001884: f012 0f08 tst.w r2, #8 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8001888: 68ca ldr r2, [r1, #12] 800188a: d01b beq.n 80018c4 800188c: f412 6f40 tst.w r2, #3072 ; 0xc00 8001890: d10d bne.n 80018ae if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 8001892: 68ca ldr r2, [r1, #12] 8001894: 0494 lsls r4, r2, #18 8001896: d40a bmi.n 80018ae CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8001898: 6dda ldr r2, [r3, #92] ; 0x5c 800189a: f422 7280 bic.w r2, r2, #256 ; 0x100 800189e: 65da str r2, [r3, #92] ; 0x5c if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 80018a0: 6dda ldr r2, [r3, #92] ; 0x5c 80018a2: 04d1 lsls r1, r2, #19 80018a4: d403 bmi.n 80018ae SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80018a6: 6dda ldr r2, [r3, #92] ; 0x5c 80018a8: f042 0201 orr.w r2, r2, #1 80018ac: 65da str r2, [r3, #92] ; 0x5c HAL_ADC_ConvCpltCallback(hadc); 80018ae: 4618 mov r0, r3 80018b0: f7ff ffd0 bl 8001854 } 80018b4: bd10 pop {r4, pc} if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 80018b6: 06d2 lsls r2, r2, #27 80018b8: d40a bmi.n 80018d0 hadc->DMA_Handle->XferErrorCallback(hdma); 80018ba: 6d5b ldr r3, [r3, #84] ; 0x54 } 80018bc: e8bd 4010 ldmia.w sp!, {r4, lr} hadc->DMA_Handle->XferErrorCallback(hdma); 80018c0: 6b5b ldr r3, [r3, #52] ; 0x34 80018c2: 4718 bx r3 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) 80018c4: 0790 lsls r0, r2, #30 80018c6: d5e7 bpl.n 8001898 HAL_ADC_ConvCpltCallback(hadc); 80018c8: 4618 mov r0, r3 80018ca: f7ff ffc3 bl 8001854 80018ce: e7f1 b.n 80018b4 HAL_ADC_ErrorCallback(hadc); 80018d0: 4618 mov r0, r3 80018d2: f7ff ffc9 bl 8001868 } 80018d6: bd10 pop {r4, pc} 080018d8 : * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80018d8: 6a80 ldr r0, [r0, #40] ; 0x28 { 80018da: b508 push {r3, lr} /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 80018dc: 6dc3 ldr r3, [r0, #92] ; 0x5c 80018de: f043 0340 orr.w r3, r3, #64 ; 0x40 80018e2: 65c3 str r3, [r0, #92] ; 0x5c /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 80018e4: 6e03 ldr r3, [r0, #96] ; 0x60 80018e6: f043 0304 orr.w r3, r3, #4 80018ea: 6603 str r3, [r0, #96] ; 0x60 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 80018ec: f7ff ffbc bl 8001868 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 80018f0: bd08 pop {r3, pc} 80018f2: bf00 nop 080018f4 : { 80018f4: b5f0 push {r4, r5, r6, r7, lr} __HAL_LOCK(hadc); 80018f6: f890 2058 ldrb.w r2, [r0, #88] ; 0x58 { 80018fa: b083 sub sp, #12 80018fc: 4603 mov r3, r0 __HAL_LOCK(hadc); 80018fe: 2a01 cmp r2, #1 __IO uint32_t wait_loop_index = 0UL; 8001900: f04f 0000 mov.w r0, #0 8001904: 9001 str r0, [sp, #4] __HAL_LOCK(hadc); 8001906: f000 8143 beq.w 8001b90 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800190a: 681a ldr r2, [r3, #0] __HAL_LOCK(hadc); 800190c: 2001 movs r0, #1 800190e: f883 0058 strb.w r0, [r3, #88] ; 0x58 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001912: 6894 ldr r4, [r2, #8] 8001914: 0766 lsls r6, r4, #29 8001916: d43d bmi.n 8001994 MODIFY_REG(*preg, 8001918: e9d1 0400 ldrd r0, r4, [r1] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, 800191c: 09a6 lsrs r6, r4, #6 800191e: f102 0530 add.w r5, r2, #48 ; 0x30 8001922: f006 060c and.w r6, r6, #12 MODIFY_REG(*preg, 8001926: f004 041f and.w r4, r4, #31 800192a: 5977 ldr r7, [r6, r5] 800192c: f04f 0c1f mov.w ip, #31 8001930: fa0c fc04 lsl.w ip, ip, r4 8001934: f3c0 6084 ubfx r0, r0, #26, #5 8001938: ea27 070c bic.w r7, r7, ip 800193c: 40a0 lsls r0, r4 800193e: 4338 orrs r0, r7 8001940: 5170 str r0, [r6, r5] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001942: 6890 ldr r0, [r2, #8] 8001944: 0745 lsls r5, r0, #29 8001946: f140 809a bpl.w 8001a7e return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 800194a: 6890 ldr r0, [r2, #8] 800194c: 6808 ldr r0, [r1, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 800194e: 6894 ldr r4, [r2, #8] if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8001950: 07e4 lsls r4, r4, #31 8001952: d530 bpl.n 80019b6 8001954: 4604 mov r4, r0 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) 8001956: 49c2 ldr r1, [pc, #776] ; (8001c60 ) 8001958: 420c tst r4, r1 800195a: d02a beq.n 80019b2 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); 800195c: 49c1 ldr r1, [pc, #772] ; (8001c64 ) if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) 800195e: 4dc2 ldr r5, [pc, #776] ; (8001c68 ) 8001960: 6888 ldr r0, [r1, #8] 8001962: 42ac cmp r4, r5 8001964: f000 76e0 and.w r6, r0, #29360128 ; 0x1c00000 8001968: d01d beq.n 80019a6 800196a: 4dc0 ldr r5, [pc, #768] ; (8001c6c ) 800196c: 42ac cmp r4, r5 800196e: d01a beq.n 80019a6 else if ((pConfig->Channel == ADC_CHANNEL_VBAT) 8001970: 4dbf ldr r5, [pc, #764] ; (8001c70 ) 8001972: 42ac cmp r4, r5 8001974: f040 813e bne.w 8001bf4 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8001978: f010 7080 ands.w r0, r0, #16777216 ; 0x1000000 800197c: d119 bne.n 80019b2 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800197e: 4cbd ldr r4, [pc, #756] ; (8001c74 ) 8001980: 42a2 cmp r2, r4 8001982: d016 beq.n 80019b2 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); 8001984: 688a ldr r2, [r1, #8] 8001986: f022 72e0 bic.w r2, r2, #29360128 ; 0x1c00000 800198a: 4316 orrs r6, r2 800198c: f046 7680 orr.w r6, r6, #16777216 ; 0x1000000 8001990: 608e str r6, [r1, #8] } 8001992: e003 b.n 800199c SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001994: 6dda ldr r2, [r3, #92] ; 0x5c 8001996: f042 0220 orr.w r2, r2, #32 800199a: 65da str r2, [r3, #92] ; 0x5c __HAL_UNLOCK(hadc); 800199c: 2200 movs r2, #0 800199e: f883 2058 strb.w r2, [r3, #88] ; 0x58 } 80019a2: b003 add sp, #12 80019a4: bdf0 pop {r4, r5, r6, r7, pc} && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 80019a6: 0201 lsls r1, r0, #8 80019a8: d403 bmi.n 80019b2 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 80019aa: f1b2 4fa0 cmp.w r2, #1342177280 ; 0x50000000 80019ae: f000 8102 beq.w 8001bb6 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80019b2: 2000 movs r0, #0 80019b4: e7f2 b.n 800199c LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); 80019b6: 68ce ldr r6, [r1, #12] MODIFY_REG(ADCx->DIFSEL, 80019b8: 4caf ldr r4, [pc, #700] ; (8001c78 ) 80019ba: f8d2 50b0 ldr.w r5, [r2, #176] ; 0xb0 if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 80019be: f8df c2c8 ldr.w ip, [pc, #712] ; 8001c88 80019c2: f006 0718 and.w r7, r6, #24 80019c6: 40fc lsrs r4, r7 80019c8: f3c0 0712 ubfx r7, r0, #0, #19 80019cc: 4004 ands r4, r0 80019ce: ea25 0507 bic.w r5, r5, r7 80019d2: 432c orrs r4, r5 80019d4: 4566 cmp r6, ip 80019d6: f8c2 40b0 str.w r4, [r2, #176] ; 0xb0 LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); 80019da: 4604 mov r4, r0 if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 80019dc: d1bb bne.n 8001956 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 80019de: 2f00 cmp r7, #0 80019e0: f000 80d9 beq.w 8001b96 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80019e4: fa90 f4a0 rbit r4, r0 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 80019e8: 2c00 cmp r4, #0 80019ea: f000 8181 beq.w 8001cf0 { return 32U; } return __builtin_clz(value); 80019ee: fab4 f484 clz r4, r4 80019f2: 3401 adds r4, #1 80019f4: f004 041f and.w r4, r4, #31 LL_ADC_SetChannelSamplingTime(hadc->Instance, 80019f8: 2c09 cmp r4, #9 80019fa: f240 8179 bls.w 8001cf0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80019fe: fa90 f5a0 rbit r5, r0 if (value == 0U) 8001a02: 2d00 cmp r5, #0 8001a04: f000 81d7 beq.w 8001db6 return __builtin_clz(value); 8001a08: fab5 f585 clz r5, r5 8001a0c: 3501 adds r5, #1 8001a0e: 06ad lsls r5, r5, #26 8001a10: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001a14: fa90 f4a0 rbit r4, r0 if (value == 0U) 8001a18: 2c00 cmp r4, #0 8001a1a: f000 81d1 beq.w 8001dc0 return __builtin_clz(value); 8001a1e: fab4 f484 clz r4, r4 8001a22: 3401 adds r4, #1 8001a24: f004 041f and.w r4, r4, #31 8001a28: 2601 movs r6, #1 8001a2a: fa06 f404 lsl.w r4, r6, r4 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8001a2e: 4325 orrs r5, r4 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001a30: fa90 f0a0 rbit r0, r0 if (value == 0U) 8001a34: 2800 cmp r0, #0 8001a36: f000 81c1 beq.w 8001dbc return __builtin_clz(value); 8001a3a: fab0 f480 clz r4, r0 8001a3e: 3401 adds r4, #1 8001a40: f004 041f and.w r4, r4, #31 8001a44: eb04 0444 add.w r4, r4, r4, lsl #1 8001a48: f1a4 001e sub.w r0, r4, #30 8001a4c: 0500 lsls r0, r0, #20 8001a4e: f040 7000 orr.w r0, r0, #33554432 ; 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8001a52: 4328 orrs r0, r5 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, 8001a54: 0dc7 lsrs r7, r0, #23 8001a56: f007 0704 and.w r7, r7, #4 8001a5a: f102 0514 add.w r5, r2, #20 MODIFY_REG(*preg, 8001a5e: 688e ldr r6, [r1, #8] 8001a60: 597c ldr r4, [r7, r5] 8001a62: f3c0 5004 ubfx r0, r0, #20, #5 8001a66: f04f 0c07 mov.w ip, #7 8001a6a: fa0c fc00 lsl.w ip, ip, r0 8001a6e: ea24 040c bic.w r4, r4, ip 8001a72: fa06 f000 lsl.w r0, r6, r0 8001a76: 4320 orrs r0, r4 8001a78: 5178 str r0, [r7, r5] 8001a7a: 680c ldr r4, [r1, #0] } 8001a7c: e76b b.n 8001956 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8001a7e: 6890 ldr r0, [r2, #8] 8001a80: f010 0008 ands.w r0, r0, #8 8001a84: f040 8082 bne.w 8001b8c if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) 8001a88: 688c ldr r4, [r1, #8] LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); 8001a8a: 680e ldr r6, [r1, #0] if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) 8001a8c: f1b4 4f00 cmp.w r4, #2147483648 ; 0x80000000 8001a90: f000 80c4 beq.w 8001c1c __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, 8001a94: ea4f 5cd6 mov.w ip, r6, lsr #23 8001a98: f00c 0c04 and.w ip, ip, #4 8001a9c: f102 0714 add.w r7, r2, #20 MODIFY_REG(*preg, 8001aa0: f3c6 5604 ubfx r6, r6, #20, #5 8001aa4: f85c 5007 ldr.w r5, [ip, r7] 8001aa8: f04f 0e07 mov.w lr, #7 8001aac: fa0e fe06 lsl.w lr, lr, r6 8001ab0: 40b4 lsls r4, r6 8001ab2: ea25 050e bic.w r5, r5, lr 8001ab6: 432c orrs r4, r5 8001ab8: f84c 4007 str.w r4, [ip, r7] MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); 8001abc: 6954 ldr r4, [r2, #20] 8001abe: f024 4400 bic.w r4, r4, #2147483648 ; 0x80000000 8001ac2: 6154 str r4, [r2, #20] if (pConfig->OffsetNumber != ADC_OFFSET_NONE) 8001ac4: f8d1 c010 ldr.w ip, [r1, #16] tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); 8001ac8: 68d6 ldr r6, [r2, #12] if (pConfig->OffsetNumber != ADC_OFFSET_NONE) 8001aca: f1bc 0f04 cmp.w ip, #4 8001ace: d02e beq.n 8001b2e __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001ad0: f102 0460 add.w r4, r2, #96 ; 0x60 MODIFY_REG(*preg, 8001ad4: f8df e1b4 ldr.w lr, [pc, #436] ; 8001c8c 8001ad8: f854 502c ldr.w r5, [r4, ip, lsl #2] 8001adc: 680f ldr r7, [r1, #0] 8001ade: ea05 0e0e and.w lr, r5, lr tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); 8001ae2: f3c6 06c1 ubfx r6, r6, #3, #2 8001ae6: 694d ldr r5, [r1, #20] 8001ae8: 0076 lsls r6, r6, #1 8001aea: f007 47f8 and.w r7, r7, #2080374784 ; 0x7c000000 8001aee: 40b5 lsls r5, r6 8001af0: ea47 070e orr.w r7, r7, lr 8001af4: 433d orrs r5, r7 8001af6: f045 4500 orr.w r5, r5, #2147483648 ; 0x80000000 8001afa: f844 502c str.w r5, [r4, ip, lsl #2] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001afe: 690f ldr r7, [r1, #16] MODIFY_REG(*preg, 8001b00: 698e ldr r6, [r1, #24] 8001b02: f854 5027 ldr.w r5, [r4, r7, lsl #2] 8001b06: f025 7580 bic.w r5, r5, #16777216 ; 0x1000000 8001b0a: 4335 orrs r5, r6 8001b0c: f844 5027 str.w r5, [r4, r7, lsl #2] LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, 8001b10: 690e ldr r6, [r1, #16] 8001b12: 7f0f ldrb r7, [r1, #28] MODIFY_REG(*preg, 8001b14: f854 5026 ldr.w r5, [r4, r6, lsl #2] 8001b18: 2f01 cmp r7, #1 8001b1a: f025 7500 bic.w r5, r5, #33554432 ; 0x2000000 8001b1e: bf08 it eq 8001b20: f04f 7000 moveq.w r0, #33554432 ; 0x2000000 8001b24: 4328 orrs r0, r5 8001b26: f844 0026 str.w r0, [r4, r6, lsl #2] 8001b2a: 6808 ldr r0, [r1, #0] } 8001b2c: e70f b.n 800194e == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001b2e: 6808 ldr r0, [r1, #0] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001b30: 6e14 ldr r4, [r2, #96] ; 0x60 8001b32: 6e14 ldr r4, [r2, #96] ; 0x60 8001b34: f3c0 0512 ubfx r5, r0, #0, #19 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8001b38: f3c4 6484 ubfx r4, r4, #26, #5 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001b3c: 2d00 cmp r5, #0 8001b3e: f040 80a7 bne.w 8001c90 8001b42: f3c0 6584 ubfx r5, r0, #26, #5 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8001b46: 42ac cmp r4, r5 8001b48: f000 8119 beq.w 8001d7e 8001b4c: 6e54 ldr r4, [r2, #100] ; 0x64 8001b4e: 6e56 ldr r6, [r2, #100] ; 0x64 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001b50: f102 0460 add.w r4, r2, #96 ; 0x60 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8001b54: f3c6 6684 ubfx r6, r6, #26, #5 8001b58: f102 0764 add.w r7, r2, #100 ; 0x64 8001b5c: 42ae cmp r6, r5 8001b5e: f000 80fc beq.w 8001d5a return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001b62: 68a6 ldr r6, [r4, #8] 8001b64: 68a6 ldr r6, [r4, #8] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001b66: f104 0708 add.w r7, r4, #8 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 8001b6a: f3c6 6684 ubfx r6, r6, #26, #5 8001b6e: 42ae cmp r6, r5 8001b70: f000 80e2 beq.w 8001d38 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001b74: 68e6 ldr r6, [r4, #12] 8001b76: 68e6 ldr r6, [r4, #12] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001b78: 340c adds r4, #12 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 8001b7a: f3c6 6684 ubfx r6, r6, #26, #5 8001b7e: 42b5 cmp r5, r6 8001b80: f47f aee5 bne.w 800194e MODIFY_REG(*preg, 8001b84: 6820 ldr r0, [r4, #0] 8001b86: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001b8a: 6020 str r0, [r4, #0] 8001b8c: 6808 ldr r0, [r1, #0] } 8001b8e: e6de b.n 800194e __HAL_LOCK(hadc); 8001b90: 2002 movs r0, #2 } 8001b92: b003 add sp, #12 8001b94: bdf0 pop {r4, r5, r6, r7, pc} (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8001b96: 0e80 lsrs r0, r0, #26 8001b98: 1c44 adds r4, r0, #1 8001b9a: f004 061f and.w r6, r4, #31 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8001b9e: 2e09 cmp r6, #9 8001ba0: d850 bhi.n 8001c44 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8001ba2: 06a5 lsls r5, r4, #26 8001ba4: 2401 movs r4, #1 8001ba6: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 8001baa: 40b4 lsls r4, r6 8001bac: eb06 0046 add.w r0, r6, r6, lsl #1 8001bb0: 4325 orrs r5, r4 8001bb2: 0500 lsls r0, r0, #20 8001bb4: e74d b.n 8001a52 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); 8001bb6: 482b ldr r0, [pc, #172] ; (8001c64 ) wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8001bb8: 4a30 ldr r2, [pc, #192] ; (8001c7c ) 8001bba: 6881 ldr r1, [r0, #8] 8001bbc: 4c30 ldr r4, [pc, #192] ; (8001c80 ) 8001bbe: f021 71e0 bic.w r1, r1, #29360128 ; 0x1c00000 8001bc2: 430e orrs r6, r1 8001bc4: f446 0600 orr.w r6, r6, #8388608 ; 0x800000 8001bc8: 6086 str r6, [r0, #8] 8001bca: 6812 ldr r2, [r2, #0] 8001bcc: 0992 lsrs r2, r2, #6 8001bce: fba4 1202 umull r1, r2, r4, r2 8001bd2: 0992 lsrs r2, r2, #6 8001bd4: 3201 adds r2, #1 8001bd6: eb02 0242 add.w r2, r2, r2, lsl #1 8001bda: 0092 lsls r2, r2, #2 8001bdc: 9201 str r2, [sp, #4] while (wait_loop_index != 0UL) 8001bde: 9a01 ldr r2, [sp, #4] 8001be0: 2a00 cmp r2, #0 8001be2: f43f aee6 beq.w 80019b2 wait_loop_index--; 8001be6: 9a01 ldr r2, [sp, #4] 8001be8: 3a01 subs r2, #1 8001bea: 9201 str r2, [sp, #4] while (wait_loop_index != 0UL) 8001bec: 9a01 ldr r2, [sp, #4] 8001bee: 2a00 cmp r2, #0 8001bf0: d1f9 bne.n 8001be6 8001bf2: e6de b.n 80019b2 else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) 8001bf4: 4d23 ldr r5, [pc, #140] ; (8001c84 ) 8001bf6: 42ac cmp r4, r5 8001bf8: f47f aedb bne.w 80019b2 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8001bfc: f410 0080 ands.w r0, r0, #4194304 ; 0x400000 8001c00: f47f aed7 bne.w 80019b2 if (ADC_VREFINT_INSTANCE(hadc)) 8001c04: 4c1b ldr r4, [pc, #108] ; (8001c74 ) 8001c06: 42a2 cmp r2, r4 8001c08: f43f aed3 beq.w 80019b2 8001c0c: 688a ldr r2, [r1, #8] 8001c0e: f022 72e0 bic.w r2, r2, #29360128 ; 0x1c00000 8001c12: 4332 orrs r2, r6 8001c14: f442 0280 orr.w r2, r2, #4194304 ; 0x400000 8001c18: 608a str r2, [r1, #8] } 8001c1a: e6bf b.n 800199c __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, 8001c1c: 0df5 lsrs r5, r6, #23 8001c1e: f102 0414 add.w r4, r2, #20 8001c22: f005 0504 and.w r5, r5, #4 MODIFY_REG(*preg, 8001c26: f3c6 5604 ubfx r6, r6, #20, #5 8001c2a: 592f ldr r7, [r5, r4] 8001c2c: f04f 0c07 mov.w ip, #7 8001c30: fa0c f606 lsl.w r6, ip, r6 8001c34: ea27 0606 bic.w r6, r7, r6 8001c38: 512e str r6, [r5, r4] MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); 8001c3a: 6954 ldr r4, [r2, #20] 8001c3c: f044 4400 orr.w r4, r4, #2147483648 ; 0x80000000 8001c40: 6154 str r4, [r2, #20] } 8001c42: e73f b.n 8001ac4 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8001c44: eb06 0046 add.w r0, r6, r6, lsl #1 8001c48: 06a5 lsls r5, r4, #26 8001c4a: 381e subs r0, #30 8001c4c: 2401 movs r4, #1 8001c4e: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 8001c52: fa04 f606 lsl.w r6, r4, r6 8001c56: 0500 lsls r0, r0, #20 8001c58: 4335 orrs r5, r6 8001c5a: f040 7000 orr.w r0, r0, #33554432 ; 0x2000000 8001c5e: e6f8 b.n 8001a52 8001c60: 80080000 .word 0x80080000 8001c64: 50000300 .word 0x50000300 8001c68: c3210000 .word 0xc3210000 8001c6c: 90c00010 .word 0x90c00010 8001c70: c7520000 .word 0xc7520000 8001c74: 50000100 .word 0x50000100 8001c78: 0007ffff .word 0x0007ffff 8001c7c: 20000804 .word 0x20000804 8001c80: 053e2d63 .word 0x053e2d63 8001c84: cb840000 .word 0xcb840000 8001c88: 407f0000 .word 0x407f0000 8001c8c: 03fff000 .word 0x03fff000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001c90: fa90 f5a0 rbit r5, r0 if (value == 0U) 8001c94: b11d cbz r5, 8001c9e return __builtin_clz(value); 8001c96: fab5 f585 clz r5, r5 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8001c9a: 42ac cmp r4, r5 8001c9c: d06f beq.n 8001d7e return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001c9e: 6e54 ldr r4, [r2, #100] ; 0x64 8001ca0: 6e56 ldr r6, [r2, #100] ; 0x64 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001ca2: f102 0460 add.w r4, r2, #96 ; 0x60 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8001ca6: f3c6 6684 ubfx r6, r6, #26, #5 8001caa: f102 0764 add.w r7, r2, #100 ; 0x64 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001cae: fa90 f5a0 rbit r5, r0 if (value == 0U) 8001cb2: b11d cbz r5, 8001cbc return __builtin_clz(value); 8001cb4: fab5 f585 clz r5, r5 8001cb8: 42ae cmp r6, r5 8001cba: d04e beq.n 8001d5a return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001cbc: 68a5 ldr r5, [r4, #8] 8001cbe: 68a6 ldr r6, [r4, #8] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001cc0: f104 0708 add.w r7, r4, #8 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 8001cc4: f3c6 6684 ubfx r6, r6, #26, #5 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001cc8: fa90 f5a0 rbit r5, r0 if (value == 0U) 8001ccc: b11d cbz r5, 8001cd6 return __builtin_clz(value); 8001cce: fab5 f585 clz r5, r5 8001cd2: 42ae cmp r6, r5 8001cd4: d030 beq.n 8001d38 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001cd6: 68e5 ldr r5, [r4, #12] 8001cd8: 68e6 ldr r6, [r4, #12] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001cda: 340c adds r4, #12 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 8001cdc: f3c6 6684 ubfx r6, r6, #26, #5 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001ce0: fa90 f5a0 rbit r5, r0 if (value == 0U) 8001ce4: 2d00 cmp r5, #0 8001ce6: f43f ae32 beq.w 800194e return __builtin_clz(value); 8001cea: fab5 f585 clz r5, r5 8001cee: e746 b.n 8001b7e __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001cf0: fa90 f5a0 rbit r5, r0 if (value == 0U) 8001cf4: 2d00 cmp r5, #0 8001cf6: d058 beq.n 8001daa return __builtin_clz(value); 8001cf8: fab5 f585 clz r5, r5 8001cfc: 3501 adds r5, #1 8001cfe: 06ad lsls r5, r5, #26 8001d00: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001d04: fa90 f4a0 rbit r4, r0 if (value == 0U) 8001d08: 2c00 cmp r4, #0 8001d0a: d04c beq.n 8001da6 return __builtin_clz(value); 8001d0c: fab4 f484 clz r4, r4 8001d10: 3401 adds r4, #1 8001d12: f004 041f and.w r4, r4, #31 8001d16: 2601 movs r6, #1 8001d18: fa06 f404 lsl.w r4, r6, r4 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8001d1c: 4325 orrs r5, r4 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001d1e: fa90 f0a0 rbit r0, r0 if (value == 0U) 8001d22: 2800 cmp r0, #0 8001d24: d044 beq.n 8001db0 return __builtin_clz(value); 8001d26: fab0 f480 clz r4, r0 8001d2a: 3401 adds r4, #1 8001d2c: f004 041f and.w r4, r4, #31 8001d30: eb04 0444 add.w r4, r4, r4, lsl #1 8001d34: 0520 lsls r0, r4, #20 8001d36: e68c b.n 8001a52 MODIFY_REG(*preg, 8001d38: 6838 ldr r0, [r7, #0] 8001d3a: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001d3e: 6038 str r0, [r7, #0] == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001d40: 6808 ldr r0, [r1, #0] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001d42: 68e5 ldr r5, [r4, #12] 8001d44: 68e6 ldr r6, [r4, #12] 8001d46: f3c0 0512 ubfx r5, r0, #0, #19 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 8001d4a: f3c6 6684 ubfx r6, r6, #26, #5 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001d4e: 340c adds r4, #12 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001d50: 2d00 cmp r5, #0 8001d52: d1c5 bne.n 8001ce0 8001d54: f3c0 6584 ubfx r5, r0, #26, #5 8001d58: e711 b.n 8001b7e MODIFY_REG(*preg, 8001d5a: 6838 ldr r0, [r7, #0] 8001d5c: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001d60: 6038 str r0, [r7, #0] == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001d62: 6808 ldr r0, [r1, #0] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001d64: 68a5 ldr r5, [r4, #8] 8001d66: 68a6 ldr r6, [r4, #8] 8001d68: f3c0 0512 ubfx r5, r0, #0, #19 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 8001d6c: f3c6 6684 ubfx r6, r6, #26, #5 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001d70: f104 0708 add.w r7, r4, #8 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001d74: 2d00 cmp r5, #0 8001d76: d1a7 bne.n 8001cc8 8001d78: f3c0 6584 ubfx r5, r0, #26, #5 8001d7c: e6f7 b.n 8001b6e MODIFY_REG(*preg, 8001d7e: 6e10 ldr r0, [r2, #96] ; 0x60 8001d80: 4614 mov r4, r2 8001d82: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001d86: f844 0f60 str.w r0, [r4, #96]! == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001d8a: 6808 ldr r0, [r1, #0] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8001d8c: 6e55 ldr r5, [r2, #100] ; 0x64 8001d8e: 6e56 ldr r6, [r2, #100] ; 0x64 8001d90: f3c0 0512 ubfx r5, r0, #0, #19 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8001d94: f3c6 6684 ubfx r6, r6, #26, #5 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001d98: f102 0764 add.w r7, r2, #100 ; 0x64 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001d9c: 2d00 cmp r5, #0 8001d9e: d186 bne.n 8001cae 8001da0: f3c0 6584 ubfx r5, r0, #26, #5 8001da4: e6da b.n 8001b5c 8001da6: 2402 movs r4, #2 8001da8: e7b8 b.n 8001d1c 8001daa: f04f 6580 mov.w r5, #67108864 ; 0x4000000 8001dae: e7a9 b.n 8001d04 8001db0: f44f 1040 mov.w r0, #3145728 ; 0x300000 8001db4: e64d b.n 8001a52 8001db6: f04f 6580 mov.w r5, #67108864 ; 0x4000000 8001dba: e62b b.n 8001a14 8001dbc: 4801 ldr r0, [pc, #4] ; (8001dc4 ) 8001dbe: e648 b.n 8001a52 8001dc0: 2402 movs r4, #2 8001dc2: e634 b.n 8001a2e 8001dc4: fe500000 .word 0xfe500000 08001dc8 : { 8001dc8: b570 push {r4, r5, r6, lr} 8001dca: b082 sub sp, #8 __IO uint32_t wait_loop_index = 0UL; 8001dcc: 2200 movs r2, #0 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8001dce: 6803 ldr r3, [r0, #0] __IO uint32_t wait_loop_index = 0UL; 8001dd0: 9201 str r2, [sp, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001dd2: 689a ldr r2, [r3, #8] if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8001dd4: 07d2 lsls r2, r2, #31 8001dd6: d42c bmi.n 8001e32 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART 8001dd8: 6899 ldr r1, [r3, #8] 8001dda: 4a28 ldr r2, [pc, #160] ; (8001e7c ) 8001ddc: 4211 tst r1, r2 8001dde: 4604 mov r4, r0 8001de0: d12a bne.n 8001e38 MODIFY_REG(ADCx->CR, 8001de2: 689a ldr r2, [r3, #8] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); 8001de4: 4926 ldr r1, [pc, #152] ; (8001e80 ) MODIFY_REG(ADCx->CR, 8001de6: f022 4200 bic.w r2, r2, #2147483648 ; 0x80000000 8001dea: f022 023f bic.w r2, r2, #63 ; 0x3f 8001dee: f042 0201 orr.w r2, r2, #1 8001df2: 609a str r2, [r3, #8] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); 8001df4: 688b ldr r3, [r1, #8] if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) 8001df6: 021b lsls r3, r3, #8 8001df8: d429 bmi.n 8001e4e tickstart = HAL_GetTick(); 8001dfa: f7ff fc23 bl 8001644 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8001dfe: 6823 ldr r3, [r4, #0] 8001e00: 681a ldr r2, [r3, #0] 8001e02: 07d6 lsls r6, r2, #31 tickstart = HAL_GetTick(); 8001e04: 4605 mov r5, r0 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8001e06: d414 bmi.n 8001e32 MODIFY_REG(ADCx->CR, 8001e08: 4e1e ldr r6, [pc, #120] ; (8001e84 ) return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001e0a: 689a ldr r2, [r3, #8] if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8001e0c: 07d0 lsls r0, r2, #31 8001e0e: d404 bmi.n 8001e1a MODIFY_REG(ADCx->CR, 8001e10: 689a ldr r2, [r3, #8] 8001e12: 4032 ands r2, r6 8001e14: f042 0201 orr.w r2, r2, #1 8001e18: 609a str r2, [r3, #8] if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8001e1a: f7ff fc13 bl 8001644 8001e1e: 1b43 subs r3, r0, r5 8001e20: 2b02 cmp r3, #2 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8001e22: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8001e24: d902 bls.n 8001e2c if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8001e26: 681a ldr r2, [r3, #0] 8001e28: 07d1 lsls r1, r2, #31 8001e2a: d505 bpl.n 8001e38 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8001e2c: 681a ldr r2, [r3, #0] 8001e2e: 07d2 lsls r2, r2, #31 8001e30: d5eb bpl.n 8001e0a return HAL_OK; 8001e32: 2000 movs r0, #0 } 8001e34: b002 add sp, #8 8001e36: bd70 pop {r4, r5, r6, pc} SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001e38: 6de3 ldr r3, [r4, #92] ; 0x5c 8001e3a: f043 0310 orr.w r3, r3, #16 8001e3e: 65e3 str r3, [r4, #92] ; 0x5c SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001e40: 6e23 ldr r3, [r4, #96] ; 0x60 return HAL_ERROR; 8001e42: 2001 movs r0, #1 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001e44: f043 0301 orr.w r3, r3, #1 8001e48: 6623 str r3, [r4, #96] ; 0x60 } 8001e4a: b002 add sp, #8 8001e4c: bd70 pop {r4, r5, r6, pc} wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8001e4e: 4b0e ldr r3, [pc, #56] ; (8001e88 ) 8001e50: 4a0e ldr r2, [pc, #56] ; (8001e8c ) 8001e52: 681b ldr r3, [r3, #0] 8001e54: 099b lsrs r3, r3, #6 8001e56: fba2 2303 umull r2, r3, r2, r3 8001e5a: 099b lsrs r3, r3, #6 8001e5c: 3301 adds r3, #1 8001e5e: eb03 0343 add.w r3, r3, r3, lsl #1 8001e62: 009b lsls r3, r3, #2 8001e64: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 8001e66: 9b01 ldr r3, [sp, #4] 8001e68: 2b00 cmp r3, #0 8001e6a: d0c6 beq.n 8001dfa wait_loop_index--; 8001e6c: 9b01 ldr r3, [sp, #4] 8001e6e: 3b01 subs r3, #1 8001e70: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 8001e72: 9b01 ldr r3, [sp, #4] 8001e74: 2b00 cmp r3, #0 8001e76: d1f9 bne.n 8001e6c 8001e78: e7bf b.n 8001dfa 8001e7a: bf00 nop 8001e7c: 8000003f .word 0x8000003f 8001e80: 50000300 .word 0x50000300 8001e84: 7fffffc0 .word 0x7fffffc0 8001e88: 20000804 .word 0x20000804 8001e8c: 053e2d63 .word 0x053e2d63 08001e90 : { 8001e90: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8001e94: 6803 ldr r3, [r0, #0] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8001e96: 4d37 ldr r5, [pc, #220] ; (8001f74 ) 8001e98: f8d5 8008 ldr.w r8, [r5, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8001e9c: 689d ldr r5, [r3, #8] 8001e9e: 076b lsls r3, r5, #29 8001ea0: d412 bmi.n 8001ec8 __HAL_LOCK(hadc); 8001ea2: f890 3058 ldrb.w r3, [r0, #88] ; 0x58 8001ea6: 2b01 cmp r3, #1 8001ea8: 4604 mov r4, r0 8001eaa: d00d beq.n 8001ec8 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8001eac: f008 081f and.w r8, r8, #31 8001eb0: 2301 movs r3, #1 if ((ADC_IS_INDEPENDENT(hadc) != RESET) 8001eb2: f1b8 0f09 cmp.w r8, #9 __HAL_LOCK(hadc); 8001eb6: f880 3058 strb.w r3, [r0, #88] ; 0x58 if ((ADC_IS_INDEPENDENT(hadc) != RESET) 8001eba: d908 bls.n 8001ece __HAL_UNLOCK(hadc); 8001ebc: 2300 movs r3, #0 8001ebe: f884 3058 strb.w r3, [r4, #88] ; 0x58 tmp_hal_status = HAL_ERROR; 8001ec2: 2001 movs r0, #1 } 8001ec4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} tmp_hal_status = HAL_BUSY; 8001ec8: 2002 movs r0, #2 } 8001eca: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if ((ADC_IS_INDEPENDENT(hadc) != RESET) 8001ece: f240 2321 movw r3, #545 ; 0x221 8001ed2: fa23 f308 lsr.w r3, r3, r8 8001ed6: 43db mvns r3, r3 8001ed8: f013 0501 ands.w r5, r3, #1 8001edc: d1ee bne.n 8001ebc tmp_hal_status = ADC_Enable(hadc); 8001ede: 460f mov r7, r1 8001ee0: 4616 mov r6, r2 8001ee2: f7ff ff71 bl 8001dc8 if (tmp_hal_status == HAL_OK) 8001ee6: 2800 cmp r0, #0 8001ee8: d13b bne.n 8001f62 ADC_STATE_CLR_SET(hadc->State, 8001eea: 6de3 ldr r3, [r4, #92] ; 0x5c if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8001eec: 6821 ldr r1, [r4, #0] 8001eee: 4a22 ldr r2, [pc, #136] ; (8001f78 ) ADC_STATE_CLR_SET(hadc->State, 8001ef0: f423 6370 bic.w r3, r3, #3840 ; 0xf00 8001ef4: f023 0301 bic.w r3, r3, #1 8001ef8: f443 7380 orr.w r3, r3, #256 ; 0x100 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8001efc: 4291 cmp r1, r2 ADC_STATE_CLR_SET(hadc->State, 8001efe: 65e3 str r3, [r4, #92] ; 0x5c if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8001f00: d033 beq.n 8001f6a CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001f02: 6de3 ldr r3, [r4, #92] ; 0x5c 8001f04: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 8001f08: 65e3 str r3, [r4, #92] ; 0x5c if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 8001f0a: 6de3 ldr r3, [r4, #92] ; 0x5c hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8001f0c: 6d60 ldr r0, [r4, #84] ; 0x54 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8001f0e: 4a1b ldr r2, [pc, #108] ; (8001f7c ) if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 8001f10: f413 5380 ands.w r3, r3, #4096 ; 0x1000 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8001f14: bf1c itt ne 8001f16: 6e23 ldrne r3, [r4, #96] ; 0x60 8001f18: f023 0306 bicne.w r3, r3, #6 ADC_CLEAR_ERRORCODE(hadc); 8001f1c: 6623 str r3, [r4, #96] ; 0x60 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8001f1e: 4b18 ldr r3, [pc, #96] ; (8001f80 ) 8001f20: 62c3 str r3, [r0, #44] ; 0x2c hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8001f22: 4b18 ldr r3, [pc, #96] ; (8001f84 ) hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8001f24: 6302 str r2, [r0, #48] ; 0x30 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8001f26: 6343 str r3, [r0, #52] ; 0x34 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8001f28: 221c movs r2, #28 __HAL_UNLOCK(hadc); 8001f2a: 2300 movs r3, #0 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8001f2c: 600a str r2, [r1, #0] __HAL_UNLOCK(hadc); 8001f2e: f884 3058 strb.w r3, [r4, #88] ; 0x58 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8001f32: 684b ldr r3, [r1, #4] 8001f34: f043 0310 orr.w r3, r3, #16 8001f38: 604b str r3, [r1, #4] SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 8001f3a: 68cd ldr r5, [r1, #12] 8001f3c: f045 0501 orr.w r5, r5, #1 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8001f40: 4633 mov r3, r6 8001f42: 463a mov r2, r7 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 8001f44: 60cd str r5, [r1, #12] tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8001f46: 3140 adds r1, #64 ; 0x40 8001f48: f000 fb84 bl 8002654 LL_ADC_REG_StartConversion(hadc->Instance); 8001f4c: 6822 ldr r2, [r4, #0] MODIFY_REG(ADCx->CR, 8001f4e: 6893 ldr r3, [r2, #8] 8001f50: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 8001f54: f023 033f bic.w r3, r3, #63 ; 0x3f 8001f58: f043 0304 orr.w r3, r3, #4 8001f5c: 6093 str r3, [r2, #8] } 8001f5e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_UNLOCK(hadc); 8001f62: f884 5058 strb.w r5, [r4, #88] ; 0x58 } 8001f66: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8001f6a: f1b8 0f00 cmp.w r8, #0 8001f6e: d0c8 beq.n 8001f02 8001f70: e7cb b.n 8001f0a 8001f72: bf00 nop 8001f74: 50000300 .word 0x50000300 8001f78: 50000100 .word 0x50000100 8001f7c: 0800185d .word 0x0800185d 8001f80: 0800186d .word 0x0800186d 8001f84: 080018d9 .word 0x080018d9 08001f88 : { 8001f88: b538 push {r3, r4, r5, lr} const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8001f8a: 6803 ldr r3, [r0, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 8001f8c: 689a ldr r2, [r3, #8] 8001f8e: 0795 lsls r5, r2, #30 8001f90: d502 bpl.n 8001f98 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001f92: 689b ldr r3, [r3, #8] return HAL_OK; 8001f94: 2000 movs r0, #0 } 8001f96: bd38 pop {r3, r4, r5, pc} 8001f98: 689a ldr r2, [r3, #8] if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8001f9a: 07d4 lsls r4, r2, #31 8001f9c: d52c bpl.n 8001ff8 if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8001f9e: 689a ldr r2, [r3, #8] 8001fa0: f002 020d and.w r2, r2, #13 8001fa4: 2a01 cmp r2, #1 8001fa6: 4604 mov r4, r0 8001fa8: d009 beq.n 8001fbe SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001faa: 6de3 ldr r3, [r4, #92] ; 0x5c 8001fac: f043 0310 orr.w r3, r3, #16 8001fb0: 65e3 str r3, [r4, #92] ; 0x5c SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001fb2: 6e23 ldr r3, [r4, #96] ; 0x60 8001fb4: f043 0301 orr.w r3, r3, #1 8001fb8: 6623 str r3, [r4, #96] ; 0x60 return HAL_ERROR; 8001fba: 2001 movs r0, #1 } 8001fbc: bd38 pop {r3, r4, r5, pc} MODIFY_REG(ADCx->CR, 8001fbe: 689a ldr r2, [r3, #8] 8001fc0: f022 4200 bic.w r2, r2, #2147483648 ; 0x80000000 8001fc4: f022 023f bic.w r2, r2, #63 ; 0x3f __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8001fc8: 2103 movs r1, #3 8001fca: f042 0202 orr.w r2, r2, #2 8001fce: 609a str r2, [r3, #8] 8001fd0: 6019 str r1, [r3, #0] tickstart = HAL_GetTick(); 8001fd2: f7ff fb37 bl 8001644 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8001fd6: 6823 ldr r3, [r4, #0] 8001fd8: 689b ldr r3, [r3, #8] 8001fda: 07d9 lsls r1, r3, #31 tickstart = HAL_GetTick(); 8001fdc: 4605 mov r5, r0 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8001fde: d50b bpl.n 8001ff8 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8001fe0: f7ff fb30 bl 8001644 8001fe4: 1b40 subs r0, r0, r5 8001fe6: 2802 cmp r0, #2 if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8001fe8: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8001fea: d902 bls.n 8001ff2 if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8001fec: 689a ldr r2, [r3, #8] 8001fee: 07d2 lsls r2, r2, #31 8001ff0: d4db bmi.n 8001faa while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8001ff2: 689b ldr r3, [r3, #8] 8001ff4: 07db lsls r3, r3, #31 8001ff6: d4f3 bmi.n 8001fe0 return HAL_OK; 8001ff8: 2000 movs r0, #0 } 8001ffa: bd38 pop {r3, r4, r5, pc} 08001ffc : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { 8001ffc: b530 push {r4, r5, lr} /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8001ffe: f890 3058 ldrb.w r3, [r0, #88] ; 0x58 { 8002002: b083 sub sp, #12 __IO uint32_t wait_loop_index = 0UL; 8002004: 2200 movs r2, #0 __HAL_LOCK(hadc); 8002006: 2b01 cmp r3, #1 __IO uint32_t wait_loop_index = 0UL; 8002008: 9201 str r2, [sp, #4] __HAL_LOCK(hadc); 800200a: d03f beq.n 800208c 800200c: 2301 movs r3, #1 800200e: f880 3058 strb.w r3, [r0, #88] ; 0x58 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8002012: 4604 mov r4, r0 8002014: 460d mov r5, r1 8002016: f7ff ffb7 bl 8001f88 /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800201a: 6de3 ldr r3, [r4, #92] ; 0x5c if (tmp_hal_status == HAL_OK) 800201c: b9e8 cbnz r0, 800205a ADC_STATE_CLR_SET(hadc->State, 800201e: f423 5388 bic.w r3, r3, #4352 ; 0x1100 8002022: f023 0302 bic.w r3, r3, #2 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, SingleDiff); 8002026: 6822 ldr r2, [r4, #0] /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { wait_loop_index++; if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8002028: 491a ldr r1, [pc, #104] ; (8002094 ) ADC_STATE_CLR_SET(hadc->State, 800202a: f043 0302 orr.w r3, r3, #2 800202e: 65e3 str r3, [r4, #92] ; 0x5c MODIFY_REG(ADCx->CR, 8002030: 6893 ldr r3, [r2, #8] 8002032: f023 4340 bic.w r3, r3, #3221225472 ; 0xc0000000 8002036: f005 4580 and.w r5, r5, #1073741824 ; 0x40000000 800203a: f023 033f bic.w r3, r3, #63 ; 0x3f 800203e: 432b orrs r3, r5 8002040: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8002044: 6093 str r3, [r2, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8002046: 6893 ldr r3, [r2, #8] 8002048: 2b00 cmp r3, #0 800204a: db0e blt.n 800206a return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800204c: 6de3 ldr r3, [r4, #92] ; 0x5c 800204e: f023 0303 bic.w r3, r3, #3 8002052: f043 0301 orr.w r3, r3, #1 8002056: 65e3 str r3, [r4, #92] ; 0x5c 8002058: e002 b.n 8002060 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800205a: f043 0310 orr.w r3, r3, #16 800205e: 65e3 str r3, [r4, #92] ; 0x5c /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002060: 2300 movs r3, #0 8002062: f884 3058 strb.w r3, [r4, #88] ; 0x58 /* Return function status */ return tmp_hal_status; } 8002066: b003 add sp, #12 8002068: bd30 pop {r4, r5, pc} wait_loop_index++; 800206a: 9b01 ldr r3, [sp, #4] 800206c: 3301 adds r3, #1 800206e: 9301 str r3, [sp, #4] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8002070: 9b01 ldr r3, [sp, #4] 8002072: 428b cmp r3, r1 8002074: d9e7 bls.n 8002046 ADC_STATE_CLR_SET(hadc->State, 8002076: 6de3 ldr r3, [r4, #92] ; 0x5c 8002078: f023 0312 bic.w r3, r3, #18 800207c: f043 0310 orr.w r3, r3, #16 __HAL_UNLOCK(hadc); 8002080: 2200 movs r2, #0 ADC_STATE_CLR_SET(hadc->State, 8002082: 65e3 str r3, [r4, #92] ; 0x5c __HAL_UNLOCK(hadc); 8002084: f884 2058 strb.w r2, [r4, #88] ; 0x58 return HAL_ERROR; 8002088: 2001 movs r0, #1 800208a: e7ec b.n 8002066 __HAL_LOCK(hadc); 800208c: 2002 movs r0, #2 } 800208e: b003 add sp, #12 8002090: bd30 pop {r4, r5, pc} 8002092: bf00 nop 8002094: 0004de01 .word 0x0004de01 08002098 : * @param hadc Master ADC handle * @param pMultimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) { 8002098: b4f0 push {r4, r5, r6, r7} assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 800209a: f890 2058 ldrb.w r2, [r0, #88] ; 0x58 if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 800209e: 680d ldr r5, [r1, #0] __HAL_LOCK(hadc); 80020a0: 2a01 cmp r2, #1 { 80020a2: b09c sub sp, #112 ; 0x70 __HAL_LOCK(hadc); 80020a4: d04f beq.n 8002146 /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); 80020a6: 6804 ldr r4, [r0, #0] 80020a8: 4603 mov r3, r0 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); 80020aa: 2200 movs r2, #0 __HAL_LOCK(hadc); 80020ac: 2001 movs r0, #1 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); 80020ae: f1b4 4fa0 cmp.w r4, #1342177280 ; 0x50000000 __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); 80020b2: 9218 str r2, [sp, #96] ; 0x60 __HAL_LOCK(hadc); 80020b4: f883 0058 strb.w r0, [r3, #88] ; 0x58 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); 80020b8: 9219 str r2, [sp, #100] ; 0x64 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); 80020ba: d008 beq.n 80020ce if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80020bc: 6dd9 ldr r1, [r3, #92] ; 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); 80020be: f883 2058 strb.w r2, [r3, #88] ; 0x58 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80020c2: f041 0120 orr.w r1, r1, #32 80020c6: 65d9 str r1, [r3, #92] ; 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } 80020c8: b01c add sp, #112 ; 0x70 80020ca: bcf0 pop {r4, r5, r6, r7} 80020cc: 4770 bx lr return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80020ce: 4a23 ldr r2, [pc, #140] ; (800215c ) 80020d0: 6890 ldr r0, [r2, #8] 80020d2: 0740 lsls r0, r0, #29 80020d4: d50b bpl.n 80020ee 80020d6: 68a2 ldr r2, [r4, #8] SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80020d8: 6dda ldr r2, [r3, #92] ; 0x5c 80020da: f042 0220 orr.w r2, r2, #32 80020de: 65da str r2, [r3, #92] ; 0x5c tmp_hal_status = HAL_ERROR; 80020e0: 2001 movs r0, #1 __HAL_UNLOCK(hadc); 80020e2: 2200 movs r2, #0 80020e4: f883 2058 strb.w r2, [r3, #88] ; 0x58 } 80020e8: b01c add sp, #112 ; 0x70 80020ea: bcf0 pop {r4, r5, r6, r7} 80020ec: 4770 bx lr 80020ee: 68a0 ldr r0, [r4, #8] 80020f0: 0746 lsls r6, r0, #29 80020f2: d4f1 bmi.n 80020d8 if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 80020f4: b1d5 cbz r5, 800212c MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 80020f6: 4e1a ldr r6, [pc, #104] ; (8002160 ) 80020f8: 684f ldr r7, [r1, #4] 80020fa: 68b0 ldr r0, [r6, #8] 80020fc: f893 c038 ldrb.w ip, [r3, #56] ; 0x38 8002100: f420 4060 bic.w r0, r0, #57344 ; 0xe000 8002104: 4338 orrs r0, r7 8002106: ea40 304c orr.w r0, r0, ip, lsl #13 800210a: 60b0 str r0, [r6, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 800210c: 68a4 ldr r4, [r4, #8] 800210e: 6890 ldr r0, [r2, #8] if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8002110: 4320 orrs r0, r4 8002112: f010 0001 ands.w r0, r0, #1 8002116: d114 bne.n 8002142 MODIFY_REG(tmpADC_Common->CCR, 8002118: 68b4 ldr r4, [r6, #8] 800211a: 688a ldr r2, [r1, #8] 800211c: f424 6171 bic.w r1, r4, #3856 ; 0xf10 8002120: 4315 orrs r5, r2 8002122: f021 010f bic.w r1, r1, #15 8002126: 430d orrs r5, r1 8002128: 60b5 str r5, [r6, #8] 800212a: e7da b.n 80020e2 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); 800212c: 4d0c ldr r5, [pc, #48] ; (8002160 ) 800212e: 68a9 ldr r1, [r5, #8] 8002130: f421 4160 bic.w r1, r1, #57344 ; 0xe000 8002134: 60a9 str r1, [r5, #8] 8002136: 68a1 ldr r1, [r4, #8] 8002138: 6890 ldr r0, [r2, #8] if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 800213a: 4308 orrs r0, r1 800213c: f010 0001 ands.w r0, r0, #1 8002140: d005 beq.n 800214e HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002142: 2000 movs r0, #0 8002144: e7cd b.n 80020e2 __HAL_LOCK(hadc); 8002146: 2002 movs r0, #2 } 8002148: b01c add sp, #112 ; 0x70 800214a: bcf0 pop {r4, r5, r6, r7} 800214c: 4770 bx lr CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 800214e: 68aa ldr r2, [r5, #8] 8002150: f422 6271 bic.w r2, r2, #3856 ; 0xf10 8002154: f022 020f bic.w r2, r2, #15 8002158: 60aa str r2, [r5, #8] 800215a: e7c2 b.n 80020e2 800215c: 50000100 .word 0x50000100 8002160: 50000300 .word 0x50000300 08002164 : __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ 8002164: 4908 ldr r1, [pc, #32] ; (8002188 ) 8002166: 68ca ldr r2, [r1, #12] * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002168: b410 push {r4} reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800216a: 0200 lsls r0, r0, #8 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800216c: f64f 04ff movw r4, #63743 ; 0xf8ff 8002170: 4022 ands r2, r4 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002172: f400 63e0 and.w r3, r0, #1792 ; 0x700 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002176: 4313 orrs r3, r2 reg_value = (reg_value | 8002178: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800217c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } 8002180: f85d 4b04 ldr.w r4, [sp], #4 SCB->AIRCR = reg_value; 8002184: 60cb str r3, [r1, #12] 8002186: 4770 bx lr 8002188: e000ed00 .word 0xe000ed00 0800218c : \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800218c: 4b19 ldr r3, [pc, #100] ; (80021f4 ) 800218e: 68db ldr r3, [r3, #12] 8002190: f3c3 2302 ubfx r3, r3, #8, #3 * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002194: b430 push {r4, r5} { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002196: f1c3 0507 rsb r5, r3, #7 800219a: 2d04 cmp r5, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800219c: f103 0404 add.w r4, r3, #4 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80021a0: bf28 it cs 80021a2: 2504 movcs r5, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80021a4: 2c06 cmp r4, #6 80021a6: d919 bls.n 80021dc 80021a8: 3b03 subs r3, #3 80021aa: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff 80021ae: 409c lsls r4, r3 80021b0: ea22 0204 bic.w r2, r2, r4 return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80021b4: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff 80021b8: 40ac lsls r4, r5 80021ba: ea21 0104 bic.w r1, r1, r4 80021be: 4099 lsls r1, r3 if ((int32_t)(IRQn) >= 0) 80021c0: 2800 cmp r0, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80021c2: ea41 0102 orr.w r1, r1, r2 if ((int32_t)(IRQn) >= 0) 80021c6: db0c blt.n 80021e2 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80021c8: f100 4060 add.w r0, r0, #3758096384 ; 0xe0000000 80021cc: f500 4061 add.w r0, r0, #57600 ; 0xe100 80021d0: 0109 lsls r1, r1, #4 80021d2: b2c9 uxtb r1, r1 80021d4: f880 1300 strb.w r1, [r0, #768] ; 0x300 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } 80021d8: bc30 pop {r4, r5} 80021da: 4770 bx lr 80021dc: 2200 movs r2, #0 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80021de: 4613 mov r3, r2 80021e0: e7e8 b.n 80021b4 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80021e2: 4b05 ldr r3, [pc, #20] ; (80021f8 ) 80021e4: f000 000f and.w r0, r0, #15 80021e8: 0109 lsls r1, r1, #4 80021ea: 4403 add r3, r0 80021ec: b2c9 uxtb r1, r1 80021ee: 7619 strb r1, [r3, #24] 80021f0: bc30 pop {r4, r5} 80021f2: 4770 bx lr 80021f4: e000ed00 .word 0xe000ed00 80021f8: e000ecfc .word 0xe000ecfc 080021fc : if ((int32_t)(IRQn) >= 0) 80021fc: 2800 cmp r0, #0 80021fe: db07 blt.n 8002210 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002200: 4a04 ldr r2, [pc, #16] ; (8002214 ) 8002202: f000 011f and.w r1, r0, #31 8002206: 2301 movs r3, #1 8002208: 0940 lsrs r0, r0, #5 800220a: 408b lsls r3, r1 800220c: f842 3020 str.w r3, [r2, r0, lsl #2] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } 8002210: 4770 bx lr 8002212: bf00 nop 8002214: e000e100 .word 0xe000e100 08002218 : function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002218: 3801 subs r0, #1 800221a: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 800221e: d20e bcs.n 800223e { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002220: 4b08 ldr r3, [pc, #32] ; (8002244 ) * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8002222: b410 push {r4} SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002224: 4c08 ldr r4, [pc, #32] ; (8002248 ) SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002226: 6058 str r0, [r3, #4] SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002228: 20f0 movs r0, #240 ; 0xf0 800222a: f884 0023 strb.w r0, [r4, #35] ; 0x23 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 800222e: 2200 movs r2, #0 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002230: 2107 movs r1, #7 SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002232: 4610 mov r0, r2 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8002234: 609a str r2, [r3, #8] return SysTick_Config(TicksNumb); } 8002236: f85d 4b04 ldr.w r4, [sp], #4 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800223a: 6019 str r1, [r3, #0] 800223c: 4770 bx lr return (1UL); /* Reload value impossible */ 800223e: 2001 movs r0, #1 8002240: 4770 bx lr 8002242: bf00 nop 8002244: e000e010 .word 0xe000e010 8002248: e000ed00 .word 0xe000ed00 0800224c : * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { /* Check the DAC peripheral handle */ if (hdac == NULL) 800224c: b188 cbz r0, 8002272 { 800224e: b510 push {r4, lr} return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 8002250: 7903 ldrb r3, [r0, #4] 8002252: 4604 mov r4, r0 8002254: f003 02ff and.w r2, r3, #255 ; 0xff 8002258: b13b cbz r3, 800226a /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 800225a: 2300 movs r3, #0 hdac->State = HAL_DAC_STATE_BUSY; 800225c: 2102 movs r1, #2 /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 800225e: 2201 movs r2, #1 hdac->State = HAL_DAC_STATE_BUSY; 8002260: 7121 strb r1, [r4, #4] hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8002262: 6123 str r3, [r4, #16] hdac->State = HAL_DAC_STATE_READY; 8002264: 7122 strb r2, [r4, #4] /* Return function status */ return HAL_OK; 8002266: 4618 mov r0, r3 } 8002268: bd10 pop {r4, pc} hdac->Lock = HAL_UNLOCKED; 800226a: 7142 strb r2, [r0, #5] HAL_DAC_MspInit(hdac); 800226c: f7fe fee2 bl 8001034 8002270: e7f3 b.n 800225a return HAL_ERROR; 8002272: 2001 movs r0, #1 } 8002274: 4770 bx lr 8002276: bf00 nop 08002278 : HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { __IO uint32_t wait_loop_index; /* Check the DAC peripheral handle */ if (hdac == NULL) 8002278: 2800 cmp r0, #0 800227a: d03e beq.n 80022fa /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); 800227c: 7943 ldrb r3, [r0, #5] 800227e: 2b01 cmp r3, #1 8002280: d03d beq.n 80022fe __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */ /* bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8002282: 4b20 ldr r3, [pc, #128] ; (8002304 ) 8002284: 4a20 ldr r2, [pc, #128] ; (8002308 ) 8002286: 681b ldr r3, [r3, #0] { 8002288: b470 push {r4, r5, r6} __HAL_DAC_ENABLE(hdac, Channel); 800228a: 6804 ldr r4, [r0, #0] hdac->State = HAL_DAC_STATE_BUSY; 800228c: 2502 movs r5, #2 800228e: 7105 strb r5, [r0, #4] wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8002290: 099b lsrs r3, r3, #6 __HAL_DAC_ENABLE(hdac, Channel); 8002292: 6826 ldr r6, [r4, #0] wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8002294: fba2 2303 umull r2, r3, r2, r3 __HAL_DAC_ENABLE(hdac, Channel); 8002298: f001 0510 and.w r5, r1, #16 800229c: 2201 movs r2, #1 { 800229e: b083 sub sp, #12 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80022a0: 099b lsrs r3, r3, #6 __HAL_DAC_ENABLE(hdac, Channel); 80022a2: 40aa lsls r2, r5 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80022a4: 3301 adds r3, #1 __HAL_DAC_ENABLE(hdac, Channel); 80022a6: 4332 orrs r2, r6 80022a8: 6022 str r2, [r4, #0] wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80022aa: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 80022ac: 9b01 ldr r3, [sp, #4] 80022ae: b12b cbz r3, 80022bc { wait_loop_index--; 80022b0: 9b01 ldr r3, [sp, #4] 80022b2: 3b01 subs r3, #1 80022b4: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 80022b6: 9b01 ldr r3, [sp, #4] 80022b8: 2b00 cmp r3, #0 80022ba: d1f9 bne.n 80022b0 } if (Channel == DAC_CHANNEL_1) 80022bc: b981 cbnz r1, 80022e0 { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 80022be: 6823 ldr r3, [r4, #0] 80022c0: f003 033e and.w r3, r3, #62 ; 0x3e 80022c4: 2b02 cmp r3, #2 80022c6: d103 bne.n 80022d0 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 80022c8: 6863 ldr r3, [r4, #4] 80022ca: f043 0301 orr.w r3, r3, #1 80022ce: 6063 str r3, [r4, #4] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); 80022d0: 2300 movs r3, #0 hdac->State = HAL_DAC_STATE_READY; 80022d2: 2201 movs r2, #1 80022d4: 7102 strb r2, [r0, #4] __HAL_UNLOCK(hdac); 80022d6: 7143 strb r3, [r0, #5] /* Return function status */ return HAL_OK; 80022d8: 4618 mov r0, r3 } 80022da: b003 add sp, #12 80022dc: bc70 pop {r4, r5, r6} 80022de: 4770 bx lr if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 80022e0: 6822 ldr r2, [r4, #0] 80022e2: 2302 movs r3, #2 80022e4: f402 1278 and.w r2, r2, #4063232 ; 0x3e0000 80022e8: fa03 f505 lsl.w r5, r3, r5 80022ec: 42aa cmp r2, r5 80022ee: d1ef bne.n 80022d0 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 80022f0: 6863 ldr r3, [r4, #4] 80022f2: f043 0302 orr.w r3, r3, #2 80022f6: 6063 str r3, [r4, #4] 80022f8: e7ea b.n 80022d0 return HAL_ERROR; 80022fa: 2001 movs r0, #1 80022fc: 4770 bx lr __HAL_LOCK(hdac); 80022fe: 2002 movs r0, #2 } 8002300: 4770 bx lr 8002302: bf00 nop 8002304: 20000804 .word 0x20000804 8002308: 053e2d63 .word 0x053e2d63 0800230c : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 800230c: b410 push {r4} 800230e: b083 sub sp, #12 __IO uint32_t tmp = 0UL; 8002310: 2400 movs r4, #0 8002312: 9401 str r4, [sp, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 8002314: b198 cbz r0, 800233e /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */ if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL) 8002316: 6800 ldr r0, [r0, #0] 8002318: 6bc4 ldr r4, [r0, #60] ; 0x3c { assert_param(IS_DAC_DATA(Data)); } tmp = (uint32_t)hdac->Instance; 800231a: 9001 str r0, [sp, #4] if (Channel == DAC_CHANNEL_1) 800231c: b151 cbz r1, 8002334 tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 800231e: 9901 ldr r1, [sp, #4] 8002320: 3114 adds r1, #20 8002322: 440a add r2, r1 8002324: 9201 str r2, [sp, #4] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8002326: 9a01 ldr r2, [sp, #4] /* Return function status */ return HAL_OK; 8002328: 2000 movs r0, #0 *(__IO uint32_t *) tmp = Data; 800232a: 6013 str r3, [r2, #0] } 800232c: b003 add sp, #12 800232e: f85d 4b04 ldr.w r4, [sp], #4 8002332: 4770 bx lr tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 8002334: 9901 ldr r1, [sp, #4] 8002336: 3108 adds r1, #8 8002338: 440a add r2, r1 800233a: 9201 str r2, [sp, #4] 800233c: e7f3 b.n 8002326 return HAL_ERROR; 800233e: 2001 movs r0, #1 } 8002340: b003 add sp, #12 8002342: f85d 4b04 ldr.w r4, [sp], #4 8002346: 4770 bx lr 08002348 : uint32_t tickstart; uint32_t hclkfreq; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 8002348: 2800 cmp r0, #0 800234a: f000 80c8 beq.w 80024de { 800234e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8002352: 460d mov r5, r1 if ((hdac == NULL) || (sConfig == NULL)) 8002354: 2900 cmp r1, #0 8002356: f000 80c4 beq.w 80024e2 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); /* Process locked */ __HAL_LOCK(hdac); 800235a: 7943 ldrb r3, [r0, #5] if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) 800235c: 688f ldr r7, [r1, #8] __HAL_LOCK(hdac); 800235e: 2b01 cmp r3, #1 8002360: 4606 mov r6, r0 8002362: f000 80ca beq.w 80024fa 8002366: 4614 mov r4, r2 /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8002368: 2302 movs r3, #2 __HAL_LOCK(hdac); 800236a: 2201 movs r2, #1 /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 800236c: 2f04 cmp r7, #4 __HAL_LOCK(hdac); 800236e: 7142 strb r2, [r0, #5] hdac->State = HAL_DAC_STATE_BUSY; 8002370: 7103 strb r3, [r0, #4] if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 8002372: d077 beq.n 8002464 8002374: 6803 ldr r3, [r0, #0] 8002376: f004 0410 and.w r4, r4, #16 /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 800237a: 69ea ldr r2, [r5, #28] 800237c: 2a01 cmp r2, #1 800237e: d108 bne.n 8002392 /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 8002380: 6b99 ldr r1, [r3, #56] ; 0x38 /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8002382: 6a2a ldr r2, [r5, #32] tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 8002384: 201f movs r0, #31 8002386: 40a0 lsls r0, r4 8002388: ea21 0100 bic.w r1, r1, r0 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 800238c: 40a2 lsls r2, r4 800238e: 430a orrs r2, r1 /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 8002390: 639a str r2, [r3, #56] ; 0x38 /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 8002392: 69a9 ldr r1, [r5, #24] tmpreg1 = hdac->Instance->MCR; 8002394: 6bda ldr r2, [r3, #60] ; 0x3c tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 8002396: f8d5 c014 ldr.w ip, [r5, #20] 800239a: f04f 0807 mov.w r8, #7 if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 800239e: 2901 cmp r1, #1 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 80023a0: fa08 f004 lsl.w r0, r8, r4 if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 80023a4: f000 8099 beq.w 80024da { connectOnChip = 0x00000000UL; } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 80023a8: 2902 cmp r1, #2 { connectOnChip = DAC_MCR_MODE1_0; } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 80023aa: bf16 itet ne 80023ac: fabc f18c clzne r1, ip connectOnChip = DAC_MCR_MODE1_0; 80023b0: 2101 moveq r1, #1 if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 80023b2: 0949 lsrne r1, r1, #5 connectOnChip = 0x00000000UL; } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); /* Clear DAC_MCR_DMADOUBLEx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL)); 80023b4: f44f 7880 mov.w r8, #256 ; 0x100 80023b8: fa08 f804 lsl.w r8, r8, r4 80023bc: ea48 0800 orr.w r8, r8, r0 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 80023c0: ea41 010c orr.w r1, r1, ip tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL)); 80023c4: ea22 0808 bic.w r8, r2, r8 /* Configure for the selected DAC channel: DMA double data mode */ tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; 80023c8: f895 c004 ldrb.w ip, [r5, #4] /* Clear DAC_MCR_SINFORMATx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); 80023cc: f44f 7200 mov.w r2, #512 ; 0x200 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 80023d0: 430f orrs r7, r1 tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); 80023d2: 40a2 lsls r2, r4 /* Configure for the selected DAC channel: Signed format */ tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; 80023d4: 7969 ldrb r1, [r5, #5] tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; 80023d6: f1bc 0f01 cmp.w ip, #1 tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); 80023da: ea28 0802 bic.w r8, r8, r2 /* Clear DAC_MCR_HFSEL bits */ tmpreg1 &= ~(DAC_MCR_HFSEL); /* Configure for both DAC channels: high frequency mode */ if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) 80023de: 682a ldr r2, [r5, #0] 80023e0: bf08 it eq 80023e2: f447 7780 orreq.w r7, r7, #256 ; 0x100 tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; 80023e6: 2901 cmp r1, #1 80023e8: bf08 it eq 80023ea: f447 7700 orreq.w r7, r7, #512 ; 0x200 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) 80023ee: 2a02 cmp r2, #2 tmpreg1 &= ~(DAC_MCR_HFSEL); 80023f0: f428 4840 bic.w r8, r8, #49152 ; 0xc000 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) 80023f4: d078 beq.n 80024e8 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE; } } else { tmpreg1 |= sConfig->DAC_HighFrequency; 80023f6: ea48 0802 orr.w r8, r8, r2 } /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80023fa: 40a7 lsls r7, r4 80023fc: ea47 0708 orr.w r7, r7, r8 /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 8002400: 63df str r7, [r3, #60] ; 0x3c /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */ tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 8002402: e9d5 1203 ldrd r1, r2, [r5, #12] CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8002406: 6818 ldr r0, [r3, #0] 8002408: f44f 4580 mov.w r5, #16384 ; 0x4000 800240c: 40a5 lsls r5, r4 800240e: ea20 0005 bic.w r0, r0, r5 8002412: 6018 str r0, [r3, #0] tmpreg1 = hdac->Instance->CR; 8002414: 6818 ldr r0, [r3, #0] tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 8002416: f640 75fe movw r5, #4094 ; 0xffe 800241a: 40a5 lsls r5, r4 800241c: ea20 0505 bic.w r5, r0, r5 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8002420: fa01 f004 lsl.w r0, r1, r4 8002424: 4328 orrs r0, r5 hdac->Instance->CR = tmpreg1; 8002426: 6018 str r0, [r3, #0] CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8002428: 6818 ldr r0, [r3, #0] 800242a: 25c0 movs r5, #192 ; 0xc0 800242c: 40a5 lsls r5, r4 800242e: ea20 0005 bic.w r0, r0, r5 8002432: 6018 str r0, [r3, #0] tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 8002434: 0192 lsls r2, r2, #6 /* Modify STMODR register value depending on DAC_Channel */ MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) 8002436: 6e18 ldr r0, [r3, #96] ; 0x60 tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; 8002438: f3c1 0183 ubfx r1, r1, #2, #4 tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 800243c: f402 6270 and.w r2, r2, #3840 ; 0xf00 MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) 8002440: f640 750f movw r5, #3855 ; 0xf0f tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 8002444: 430a orrs r2, r1 MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) 8002446: fa05 f104 lsl.w r1, r5, r4 800244a: fa02 f404 lsl.w r4, r2, r4 800244e: ea20 0201 bic.w r2, r0, r1 8002452: 4314 orrs r4, r2 << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8002454: 2101 movs r1, #1 /* Process unlocked */ __HAL_UNLOCK(hdac); 8002456: 2200 movs r2, #0 MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) 8002458: 661c str r4, [r3, #96] ; 0x60 /* Return function status */ return status; 800245a: 4610 mov r0, r2 hdac->State = HAL_DAC_STATE_READY; 800245c: 7131 strb r1, [r6, #4] __HAL_UNLOCK(hdac); 800245e: 7172 strb r2, [r6, #5] } 8002460: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} tickstart = HAL_GetTick(); 8002464: f7ff f8ee bl 8001644 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8002468: 6833 ldr r3, [r6, #0] tickstart = HAL_GetTick(); 800246a: 4607 mov r7, r0 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800246c: 6b5a ldr r2, [r3, #52] ; 0x34 if (Channel == DAC_CHANNEL_1) 800246e: b154 cbz r4, 8002486 8002470: e018 b.n 80024a4 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8002472: f7ff f8e7 bl 8001644 8002476: 1bc3 subs r3, r0, r7 8002478: 2b01 cmp r3, #1 if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800247a: 6833 ldr r3, [r6, #0] if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 800247c: d902 bls.n 8002484 if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800247e: 6b5a ldr r2, [r3, #52] ; 0x34 8002480: 0411 lsls r1, r2, #16 8002482: d443 bmi.n 800250c while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8002484: 6b5a ldr r2, [r3, #52] ; 0x34 8002486: 0412 lsls r2, r2, #16 8002488: d4f3 bmi.n 8002472 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 800248a: 6a6a ldr r2, [r5, #36] ; 0x24 800248c: 641a str r2, [r3, #64] ; 0x40 800248e: e00d b.n 80024ac if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8002490: f7ff f8d8 bl 8001644 8002494: 1bc3 subs r3, r0, r7 8002496: 2b01 cmp r3, #1 if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8002498: 6833 ldr r3, [r6, #0] if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 800249a: d902 bls.n 80024a2 if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 800249c: 6b5a ldr r2, [r3, #52] ; 0x34 800249e: 2a00 cmp r2, #0 80024a0: db34 blt.n 800250c while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 80024a2: 6b5a ldr r2, [r3, #52] ; 0x34 80024a4: 2a00 cmp r2, #0 80024a6: dbf3 blt.n 8002490 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 80024a8: 6a6a ldr r2, [r5, #36] ; 0x24 80024aa: 645a str r2, [r3, #68] ; 0x44 MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 80024ac: 6c9a ldr r2, [r3, #72] ; 0x48 80024ae: 6aa9 ldr r1, [r5, #40] ; 0x28 80024b0: 68af ldr r7, [r5, #8] 80024b2: f004 0410 and.w r4, r4, #16 80024b6: f240 30ff movw r0, #1023 ; 0x3ff 80024ba: 40a0 lsls r0, r4 80024bc: ea22 0200 bic.w r2, r2, r0 80024c0: 40a1 lsls r1, r4 80024c2: 430a orrs r2, r1 80024c4: 649a str r2, [r3, #72] ; 0x48 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 80024c6: 6cda ldr r2, [r3, #76] ; 0x4c 80024c8: 6ae9 ldr r1, [r5, #44] ; 0x2c 80024ca: 20ff movs r0, #255 ; 0xff 80024cc: 40a0 lsls r0, r4 80024ce: ea22 0200 bic.w r2, r2, r0 80024d2: 40a1 lsls r1, r4 80024d4: 430a orrs r2, r1 80024d6: 64da str r2, [r3, #76] ; 0x4c 80024d8: e74f b.n 800237a connectOnChip = 0x00000000UL; 80024da: 2100 movs r1, #0 80024dc: e76a b.n 80023b4 return HAL_ERROR; 80024de: 2001 movs r0, #1 } 80024e0: 4770 bx lr return HAL_ERROR; 80024e2: 2001 movs r0, #1 } 80024e4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} hclkfreq = HAL_RCC_GetHCLKFreq(); 80024e8: f000 fe30 bl 800314c if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ) 80024ec: 4b0b ldr r3, [pc, #44] ; (800251c ) 80024ee: 4298 cmp r0, r3 80024f0: d905 bls.n 80024fe tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ; 80024f2: 6833 ldr r3, [r6, #0] 80024f4: f448 4800 orr.w r8, r8, #32768 ; 0x8000 80024f8: e77f b.n 80023fa __HAL_LOCK(hdac); 80024fa: 2002 movs r0, #2 80024fc: e7b0 b.n 8002460 else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) 80024fe: 4b08 ldr r3, [pc, #32] ; (8002520 ) 8002500: 4298 cmp r0, r3 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ; 8002502: bf88 it hi 8002504: f448 4880 orrhi.w r8, r8, #16384 ; 0x4000 8002508: 6833 ldr r3, [r6, #0] 800250a: e776 b.n 80023fa SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 800250c: 6933 ldr r3, [r6, #16] hdac->State = HAL_DAC_STATE_TIMEOUT; 800250e: 2203 movs r2, #3 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8002510: f043 0308 orr.w r3, r3, #8 8002514: 6133 str r3, [r6, #16] return HAL_TIMEOUT; 8002516: 4610 mov r0, r2 hdac->State = HAL_DAC_STATE_TIMEOUT; 8002518: 7132 strb r2, [r6, #4] return HAL_TIMEOUT; 800251a: e7a1 b.n 8002460 800251c: 09896800 .word 0x09896800 8002520: 04c4b400 .word 0x04c4b400 08002524 : HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) 8002524: 2800 cmp r0, #0 8002526: d07d beq.n 8002624 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 8002528: 4a3f ldr r2, [pc, #252] ; (8002628 ) 800252a: 4603 mov r3, r0 800252c: 6800 ldr r0, [r0, #0] 800252e: 4290 cmp r0, r2 { 8002530: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 8002534: d962 bls.n 80025fc hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 8002536: 493d ldr r1, [pc, #244] ; (800262c ) 8002538: 4a3d ldr r2, [pc, #244] ; (8002630 ) hdma->DmaBaseAddress = DMA2; 800253a: 4c3e ldr r4, [pc, #248] ; (8002634 ) hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 800253c: 4401 add r1, r0 800253e: fba2 2101 umull r2, r1, r2, r1 8002542: 0909 lsrs r1, r1, #4 8002544: 0089 lsls r1, r1, #2 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8002546: e9d3 7202 ldrd r7, r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 800254a: 691e ldr r6, [r3, #16] 800254c: 641c str r4, [r3, #64] ; 0x40 tmp |= hdma->Init.Direction | 800254e: 433a orrs r2, r7 hdma->Init.PeriphInc | hdma->Init.MemInc | 8002550: 695c ldr r4, [r3, #20] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002552: 699d ldr r5, [r3, #24] uint32_t dmamux_base_addr; uint32_t channel_number; DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; /* check if instance is not outside the DMA channel range */ if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8002554: f8df e0f4 ldr.w lr, [pc, #244] ; 800264c 8002558: f8df 80cc ldr.w r8, [pc, #204] ; 8002628 hdma->Init.PeriphInc | hdma->Init.MemInc | 800255c: 4332 orrs r2, r6 hdma->State = HAL_DMA_STATE_BUSY; 800255e: f04f 0c02 mov.w ip, #2 hdma->Init.PeriphInc | hdma->Init.MemInc | 8002562: 4322 orrs r2, r4 hdma->State = HAL_DMA_STATE_BUSY; 8002564: f883 c025 strb.w ip, [r3, #37] ; 0x25 #else DMAMUX1_ChannelBase = DMAMUX1_Channel7; #endif /* STM32G4x1xx) */ } dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8002568: 4c31 ldr r4, [pc, #196] ; (8002630 ) tmp = hdma->Instance->CCR; 800256a: f8d0 c000 ldr.w ip, [r0] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800256e: 69de ldr r6, [r3, #28] 8002570: 6459 str r1, [r3, #68] ; 0x44 8002572: 432a orrs r2, r5 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8002574: b2c5 uxtb r5, r0 8002576: 3d08 subs r5, #8 8002578: fba4 4505 umull r4, r5, r4, r5 hdma->Init.Mode | hdma->Init.Priority; 800257c: 6a1c ldr r4, [r3, #32] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800257e: 4332 orrs r2, r6 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 8002580: f42c 4cff bic.w ip, ip, #32640 ; 0x7f80 if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8002584: 4e2c ldr r6, [pc, #176] ; (8002638 ) hdma->Init.Mode | hdma->Init.Priority; 8002586: 4322 orrs r2, r4 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 8002588: f02c 0c70 bic.w ip, ip, #112 ; 0x70 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 800258c: f3c5 1404 ubfx r4, r5, #4, #5 if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8002590: 4540 cmp r0, r8 8002592: bf88 it hi 8002594: 4676 movhi r6, lr tmp |= hdma->Init.Direction | 8002596: ea42 020c orr.w r2, r2, ip hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 800259a: 2501 movs r5, #1 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800259c: f8df c0b0 ldr.w ip, [pc, #176] ; 8002650 hdma->Instance->CCR = tmp; 80025a0: 6002 str r2, [r0, #0] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 80025a2: eb01 0e06 add.w lr, r1, r6 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 80025a6: fa05 f404 lsl.w r4, r5, r4 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 80025aa: f5b7 4f80 cmp.w r7, #16384 ; 0x4000 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 80025ae: e9c3 ec12 strd lr, ip, [r3, #72] ; 0x48 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 80025b2: ea4f 0191 mov.w r1, r1, lsr #2 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 80025b6: 651c str r4, [r3, #80] ; 0x50 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 80025b8: d029 beq.n 800260e hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 80025ba: 6858 ldr r0, [r3, #4] 80025bc: b2c2 uxtb r2, r0 if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 80025be: 3801 subs r0, #1 80025c0: 2803 cmp r0, #3 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 80025c2: f846 2021 str.w r2, [r6, r1, lsl #2] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80025c6: f8cc 4004 str.w r4, [ip, #4] if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 80025ca: d826 bhi.n 800261a static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 80025cc: 491b ldr r1, [pc, #108] ; (800263c ) hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 80025ce: 481c ldr r0, [pc, #112] ; (8002640 ) 80025d0: 6598 str r0, [r3, #88] ; 0x58 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 80025d2: 4411 add r1, r2 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); 80025d4: 3a01 subs r2, #1 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 80025d6: 0089 lsls r1, r1, #2 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); 80025d8: f002 021f and.w r2, r2, #31 80025dc: fa05 f202 lsl.w r2, r5, r2 hdma->DMAmuxRequestGen->RGCR = 0U; 80025e0: 2400 movs r4, #0 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 80025e2: 6559 str r1, [r3, #84] ; 0x54 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); 80025e4: 65da str r2, [r3, #92] ; 0x5c hdma->DMAmuxRequestGen->RGCR = 0U; 80025e6: 600c str r4, [r1, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80025e8: 6042 str r2, [r0, #4] hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80025ea: 2000 movs r0, #0 hdma->State = HAL_DMA_STATE_READY; 80025ec: 2201 movs r2, #1 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 80025ee: 63d8 str r0, [r3, #60] ; 0x3c hdma->Lock = HAL_UNLOCKED; 80025f0: f883 0024 strb.w r0, [r3, #36] ; 0x24 hdma->State = HAL_DMA_STATE_READY; 80025f4: f883 2025 strb.w r2, [r3, #37] ; 0x25 } 80025f8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 80025fc: 4911 ldr r1, [pc, #68] ; (8002644 ) 80025fe: 4a0c ldr r2, [pc, #48] ; (8002630 ) hdma->DmaBaseAddress = DMA1; 8002600: 4c11 ldr r4, [pc, #68] ; (8002648 ) hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 8002602: 4401 add r1, r0 8002604: fba2 2101 umull r2, r1, r2, r1 8002608: 0909 lsrs r1, r1, #4 800260a: 0089 lsls r1, r1, #2 hdma->DmaBaseAddress = DMA1; 800260c: e79b b.n 8002546 hdma->Init.Request = DMA_REQUEST_MEM2MEM; 800260e: 2200 movs r2, #0 8002610: 605a str r2, [r3, #4] hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8002612: f846 2021 str.w r2, [r6, r1, lsl #2] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002616: f8cc 4004 str.w r4, [ip, #4] hdma->DMAmuxRequestGen = 0U; 800261a: 2200 movs r2, #0 hdma->DMAmuxRequestGenStatus = 0U; 800261c: e9c3 2215 strd r2, r2, [r3, #84] ; 0x54 hdma->DMAmuxRequestGenStatusMask = 0U; 8002620: 65da str r2, [r3, #92] ; 0x5c 8002622: e7e2 b.n 80025ea return HAL_ERROR; 8002624: 2001 movs r0, #1 } 8002626: 4770 bx lr 8002628: 40020407 .word 0x40020407 800262c: bffdfbf8 .word 0xbffdfbf8 8002630: cccccccd .word 0xcccccccd 8002634: 40020400 .word 0x40020400 8002638: 40020800 .word 0x40020800 800263c: 1000823f .word 0x1000823f 8002640: 40020940 .word 0x40020940 8002644: bffdfff8 .word 0xbffdfff8 8002648: 40020000 .word 0x40020000 800264c: 40020820 .word 0x40020820 8002650: 40020880 .word 0x40020880 08002654 : { 8002654: b4f0 push {r4, r5, r6, r7} __HAL_LOCK(hdma); 8002656: f890 4024 ldrb.w r4, [r0, #36] ; 0x24 800265a: 2c01 cmp r4, #1 800265c: d053 beq.n 8002706 if (HAL_DMA_STATE_READY == hdma->State) 800265e: f890 4025 ldrb.w r4, [r0, #37] ; 0x25 __HAL_LOCK(hdma); 8002662: 2501 movs r5, #1 if (HAL_DMA_STATE_READY == hdma->State) 8002664: 42ac cmp r4, r5 __HAL_LOCK(hdma); 8002666: f880 5024 strb.w r5, [r0, #36] ; 0x24 if (HAL_DMA_STATE_READY == hdma->State) 800266a: d005 beq.n 8002678 __HAL_UNLOCK(hdma); 800266c: 2300 movs r3, #0 800266e: f880 3024 strb.w r3, [r0, #36] ; 0x24 } 8002672: bcf0 pop {r4, r5, r6, r7} status = HAL_BUSY; 8002674: 2002 movs r0, #2 } 8002676: 4770 bx lr __HAL_DMA_DISABLE(hdma); 8002678: 6804 ldr r4, [r0, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800267a: 6cc7 ldr r7, [r0, #76] ; 0x4c hdma->State = HAL_DMA_STATE_BUSY; 800267c: 2602 movs r6, #2 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800267e: 2500 movs r5, #0 hdma->State = HAL_DMA_STATE_BUSY; 8002680: f880 6025 strb.w r6, [r0, #37] ; 0x25 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8002684: 63c5 str r5, [r0, #60] ; 0x3c __HAL_DMA_DISABLE(hdma); 8002686: 6826 ldr r6, [r4, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002688: e9d0 c514 ldrd ip, r5, [r0, #80] ; 0x50 __HAL_DMA_DISABLE(hdma); 800268c: f026 0601 bic.w r6, r6, #1 8002690: 6026 str r6, [r4, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002692: f8c7 c004 str.w ip, [r7, #4] if (hdma->DMAmuxRequestGen != 0U) 8002696: b115 cbz r5, 800269e hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002698: e9d0 6716 ldrd r6, r7, [r0, #88] ; 0x58 800269c: 6077 str r7, [r6, #4] hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 800269e: 6c46 ldr r6, [r0, #68] ; 0x44 if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80026a0: 6887 ldr r7, [r0, #8] hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 80026a2: f006 0c1f and.w ip, r6, #31 80026a6: 2601 movs r6, #1 80026a8: fa06 fc0c lsl.w ip, r6, ip 80026ac: 6c06 ldr r6, [r0, #64] ; 0x40 80026ae: f8c6 c004 str.w ip, [r6, #4] hdma->Instance->CNDTR = DataLength; 80026b2: 6063 str r3, [r4, #4] if (NULL != hdma->XferHalfCpltCallback) 80026b4: 6b03 ldr r3, [r0, #48] ; 0x30 if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80026b6: 2f10 cmp r7, #16 hdma->Instance->CPAR = DstAddress; 80026b8: bf0b itete eq 80026ba: 60a2 streq r2, [r4, #8] hdma->Instance->CPAR = SrcAddress; 80026bc: 60a1 strne r1, [r4, #8] hdma->Instance->CMAR = SrcAddress; 80026be: 60e1 streq r1, [r4, #12] hdma->Instance->CMAR = DstAddress; 80026c0: 60e2 strne r2, [r4, #12] if (NULL != hdma->XferHalfCpltCallback) 80026c2: b1bb cbz r3, 80026f4 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80026c4: 6823 ldr r3, [r4, #0] 80026c6: f043 030e orr.w r3, r3, #14 80026ca: 6023 str r3, [r4, #0] if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 80026cc: 6c83 ldr r3, [r0, #72] ; 0x48 80026ce: 681a ldr r2, [r3, #0] 80026d0: 03d2 lsls r2, r2, #15 80026d2: d503 bpl.n 80026dc hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 80026d4: 681a ldr r2, [r3, #0] 80026d6: f442 7280 orr.w r2, r2, #256 ; 0x100 80026da: 601a str r2, [r3, #0] if (hdma->DMAmuxRequestGen != 0U) 80026dc: b11d cbz r5, 80026e6 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 80026de: 682b ldr r3, [r5, #0] 80026e0: f443 7380 orr.w r3, r3, #256 ; 0x100 80026e4: 602b str r3, [r5, #0] __HAL_DMA_ENABLE(hdma); 80026e6: 6823 ldr r3, [r4, #0] 80026e8: f043 0301 orr.w r3, r3, #1 80026ec: 6023 str r3, [r4, #0] HAL_StatusTypeDef status = HAL_OK; 80026ee: 2000 movs r0, #0 } 80026f0: bcf0 pop {r4, r5, r6, r7} 80026f2: 4770 bx lr __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80026f4: 6823 ldr r3, [r4, #0] 80026f6: f023 0304 bic.w r3, r3, #4 80026fa: 6023 str r3, [r4, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 80026fc: 6823 ldr r3, [r4, #0] 80026fe: f043 030a orr.w r3, r3, #10 8002702: 6023 str r3, [r4, #0] 8002704: e7e2 b.n 80026cc __HAL_LOCK(hdma); 8002706: 2002 movs r0, #2 } 8002708: bcf0 pop {r4, r5, r6, r7} 800270a: 4770 bx lr 0800270c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800270c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) 8002710: 680c ldr r4, [r1, #0] { 8002712: b085 sub sp, #20 while (((GPIO_Init->Pin) >> position) != 0U) 8002714: 2c00 cmp r4, #0 8002716: f000 8084 beq.w 8002822 uint32_t position = 0x00U; 800271a: 2300 movs r3, #0 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800271c: f04f 0b01 mov.w fp, #1 8002720: fa0b fe03 lsl.w lr, fp, r3 if (iocurrent != 0x00u) 8002724: ea1e 0a04 ands.w sl, lr, r4 8002728: d076 beq.n 8002818 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 800272a: 684e ldr r6, [r1, #4] 800272c: f006 0203 and.w r2, r6, #3 8002730: 1e55 subs r5, r2, #1 8002732: 2d01 cmp r5, #1 8002734: ea4f 0c43 mov.w ip, r3, lsl #1 8002738: d976 bls.n 8002828 temp &= ~(GPIO_OTYPER_OT0 << position) ; temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800273a: 2a03 cmp r2, #3 800273c: f040 80ba bne.w 80028b4 8002740: fa02 f20c lsl.w r2, r2, ip 8002744: 43d5 mvns r5, r2 temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); GPIOx->AFR[position >> 3U] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002746: f8d0 c000 ldr.w ip, [r0] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800274a: ea0c 0505 and.w r5, ip, r5 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800274e: 432a orrs r2, r5 GPIOx->MODER = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8002750: f416 3f40 tst.w r6, #196608 ; 0x30000 GPIOx->MODER = temp; 8002754: 6002 str r2, [r0, #0] if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8002756: d05f beq.n 8002818 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002758: 4d64 ldr r5, [pc, #400] ; (80028ec ) 800275a: 6e2a ldr r2, [r5, #96] ; 0x60 800275c: f042 0201 orr.w r2, r2, #1 8002760: 662a str r2, [r5, #96] ; 0x60 8002762: 6e2a ldr r2, [r5, #96] ; 0x60 8002764: f023 0c03 bic.w ip, r3, #3 8002768: f10c 4c80 add.w ip, ip, #1073741824 ; 0x40000000 800276c: f002 0201 and.w r2, r2, #1 8002770: f50c 3c80 add.w ip, ip, #65536 ; 0x10000 8002774: 9203 str r2, [sp, #12] temp = SYSCFG->EXTICR[position >> 2U]; temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8002776: f003 0203 and.w r2, r3, #3 __HAL_RCC_SYSCFG_CLK_ENABLE(); 800277a: 9d03 ldr r5, [sp, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800277c: f8dc 5008 ldr.w r5, [ip, #8] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8002780: 0092 lsls r2, r2, #2 8002782: 270f movs r7, #15 8002784: fa07 fe02 lsl.w lr, r7, r2 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8002788: f1b0 4f90 cmp.w r0, #1207959552 ; 0x48000000 temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800278c: ea25 050e bic.w r5, r5, lr temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8002790: d019 beq.n 80027c6 8002792: 4f57 ldr r7, [pc, #348] ; (80028f0 ) 8002794: 42b8 cmp r0, r7 8002796: f000 8098 beq.w 80028ca 800279a: 4f56 ldr r7, [pc, #344] ; (80028f4 ) 800279c: 42b8 cmp r0, r7 800279e: f000 8098 beq.w 80028d2 80027a2: 4f55 ldr r7, [pc, #340] ; (80028f8 ) 80027a4: 42b8 cmp r0, r7 80027a6: f000 808a beq.w 80028be 80027aa: 4f54 ldr r7, [pc, #336] ; (80028fc ) 80027ac: 42b8 cmp r0, r7 80027ae: f000 8096 beq.w 80028de 80027b2: 4f53 ldr r7, [pc, #332] ; (8002900 ) 80027b4: 42b8 cmp r0, r7 80027b6: bf0c ite eq 80027b8: f04f 0e05 moveq.w lr, #5 80027bc: f04f 0e06 movne.w lr, #6 80027c0: fa0e f202 lsl.w r2, lr, r2 80027c4: 4315 orrs r5, r2 SYSCFG->EXTICR[position >> 2U] = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 80027c6: 4a4f ldr r2, [pc, #316] ; (8002904 ) SYSCFG->EXTICR[position >> 2U] = temp; 80027c8: f8cc 5008 str.w r5, [ip, #8] temp = EXTI->RTSR1; 80027cc: 6892 ldr r2, [r2, #8] temp &= ~(iocurrent); 80027ce: ea6f 0c0a mvn.w ip, sl if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 80027d2: 02f5 lsls r5, r6, #11 { temp |= iocurrent; } EXTI->RTSR1 = temp; 80027d4: 4d4b ldr r5, [pc, #300] ; (8002904 ) temp &= ~(iocurrent); 80027d6: bf54 ite pl 80027d8: ea0c 0202 andpl.w r2, ip, r2 temp |= iocurrent; 80027dc: ea4a 0202 orrmi.w r2, sl, r2 EXTI->RTSR1 = temp; 80027e0: 60aa str r2, [r5, #8] temp = EXTI->FTSR1; 80027e2: 68ed ldr r5, [r5, #12] temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 80027e4: 02b2 lsls r2, r6, #10 { temp |= iocurrent; } EXTI->FTSR1 = temp; 80027e6: 4a47 ldr r2, [pc, #284] ; (8002904 ) temp &= ~(iocurrent); 80027e8: bf54 ite pl 80027ea: ea0c 0505 andpl.w r5, ip, r5 temp |= iocurrent; 80027ee: ea4a 0505 orrmi.w r5, sl, r5 EXTI->FTSR1 = temp; 80027f2: 60d5 str r5, [r2, #12] temp = EXTI->EMR1; 80027f4: 6855 ldr r5, [r2, #4] temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } EXTI->EMR1 = temp; 80027f6: 4a43 ldr r2, [pc, #268] ; (8002904 ) if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 80027f8: 03b7 lsls r7, r6, #14 temp &= ~(iocurrent); 80027fa: bf54 ite pl 80027fc: ea0c 0505 andpl.w r5, ip, r5 temp |= iocurrent; 8002800: ea4a 0505 orrmi.w r5, sl, r5 EXTI->EMR1 = temp; 8002804: 6055 str r5, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 8002806: 6812 ldr r2, [r2, #0] temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8002808: 03f5 lsls r5, r6, #15 { temp |= iocurrent; } EXTI->IMR1 = temp; 800280a: 4d3e ldr r5, [pc, #248] ; (8002904 ) temp &= ~(iocurrent); 800280c: bf54 ite pl 800280e: ea0c 0202 andpl.w r2, ip, r2 temp |= iocurrent; 8002812: ea4a 0202 orrmi.w r2, sl, r2 EXTI->IMR1 = temp; 8002816: 602a str r2, [r5, #0] } } position++; 8002818: 3301 adds r3, #1 while (((GPIO_Init->Pin) >> position) != 0U) 800281a: fa34 f203 lsrs.w r2, r4, r3 800281e: f47f af7f bne.w 8002720 } } 8002822: b005 add sp, #20 8002824: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} temp = GPIOx->OSPEEDR; 8002828: f8d0 8008 ldr.w r8, [r0, #8] temp |= (GPIO_Init->Speed << (position * 2U)); 800282c: 68cf ldr r7, [r1, #12] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800282e: 2503 movs r5, #3 8002830: fa05 f50c lsl.w r5, r5, ip 8002834: ea28 0805 bic.w r8, r8, r5 temp |= (GPIO_Init->Speed << (position * 2U)); 8002838: fa07 f90c lsl.w r9, r7, ip 800283c: ea49 0808 orr.w r8, r9, r8 GPIOx->OSPEEDR = temp; 8002840: f8c0 8008 str.w r8, [r0, #8] temp = GPIOx->OTYPER; 8002844: f8d0 8004 ldr.w r8, [r0, #4] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002848: f3c6 1900 ubfx r9, r6, #4, #1 temp &= ~(GPIO_OTYPER_OT0 << position) ; 800284c: ea28 080e bic.w r8, r8, lr temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002850: fa09 fe03 lsl.w lr, r9, r3 8002854: ea4e 0e08 orr.w lr, lr, r8 temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8002858: 43ed mvns r5, r5 GPIOx->OTYPER = temp; 800285a: f8c0 e004 str.w lr, [r0, #4] temp = GPIOx->PUPDR; 800285e: f8d0 800c ldr.w r8, [r0, #12] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002862: 688f ldr r7, [r1, #8] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8002864: ea08 0805 and.w r8, r8, r5 temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002868: fa07 fe0c lsl.w lr, r7, ip 800286c: ea4e 0e08 orr.w lr, lr, r8 if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002870: 2a02 cmp r2, #2 GPIOx->PUPDR = temp; 8002872: f8c0 e00c str.w lr, [r0, #12] if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002876: d002 beq.n 800287e 8002878: fa02 f20c lsl.w r2, r2, ip 800287c: e763 b.n 8002746 temp = GPIOx->AFR[position >> 3U]; 800287e: ea4f 08d3 mov.w r8, r3, lsr #3 8002882: eb00 0888 add.w r8, r0, r8, lsl #2 temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8002886: f003 0e07 and.w lr, r3, #7 temp = GPIOx->AFR[position >> 3U]; 800288a: f8d8 7020 ldr.w r7, [r8, #32] 800288e: 9701 str r7, [sp, #4] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8002890: 690f ldr r7, [r1, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8002892: ea4f 0e8e mov.w lr, lr, lsl #2 temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8002896: fa07 f90e lsl.w r9, r7, lr temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800289a: 270f movs r7, #15 800289c: fa07 fe0e lsl.w lr, r7, lr 80028a0: 9f01 ldr r7, [sp, #4] 80028a2: ea27 0e0e bic.w lr, r7, lr temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80028a6: ea49 0e0e orr.w lr, r9, lr GPIOx->AFR[position >> 3U] = temp; 80028aa: fa02 f20c lsl.w r2, r2, ip 80028ae: f8c8 e020 str.w lr, [r8, #32] 80028b2: e748 b.n 8002746 80028b4: 2503 movs r5, #3 80028b6: fa05 f50c lsl.w r5, r5, ip 80028ba: 43ed mvns r5, r5 80028bc: e7cf b.n 800285e 80028be: f04f 0e03 mov.w lr, #3 80028c2: fa0e f202 lsl.w r2, lr, r2 80028c6: 4315 orrs r5, r2 80028c8: e77d b.n 80027c6 80028ca: fa0b f202 lsl.w r2, fp, r2 80028ce: 4315 orrs r5, r2 80028d0: e779 b.n 80027c6 80028d2: f04f 0e02 mov.w lr, #2 80028d6: fa0e f202 lsl.w r2, lr, r2 80028da: 4315 orrs r5, r2 80028dc: e773 b.n 80027c6 80028de: f04f 0e04 mov.w lr, #4 80028e2: fa0e f202 lsl.w r2, lr, r2 80028e6: 4315 orrs r5, r2 80028e8: e76d b.n 80027c6 80028ea: bf00 nop 80028ec: 40021000 .word 0x40021000 80028f0: 48000400 .word 0x48000400 80028f4: 48000800 .word 0x48000800 80028f8: 48000c00 .word 0x48000c00 80028fc: 48001000 .word 0x48001000 8002900: 48001400 .word 0x48001400 8002904: 40010400 .word 0x40010400 08002908 : GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 8002908: 6903 ldr r3, [r0, #16] 800290a: 4219 tst r1, r3 else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } 800290c: bf14 ite ne 800290e: 2001 movne r0, #1 8002910: 2000 moveq r0, #0 8002912: 4770 bx lr 08002914 : assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8002914: 4a3b ldr r2, [pc, #236] ; (8002a04 ) { 8002916: b410 push {r4} if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8002918: 6813 ldr r3, [r2, #0] if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) 800291a: b968 cbnz r0, 8002938 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 800291c: f403 63c0 and.w r3, r3, #1536 ; 0x600 8002920: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8002924: d014 beq.n 8002950 } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8002926: f8d2 3080 ldr.w r3, [r2, #128] ; 0x80 800292a: f423 7380 bic.w r3, r3, #256 ; 0x100 800292e: f8c2 3080 str.w r3, [r2, #128] ; 0x80 /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; } 8002932: f85d 4b04 ldr.w r4, [sp], #4 8002936: 4770 bx lr else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 8002938: f5b0 7f00 cmp.w r0, #512 ; 0x200 800293c: d02f beq.n 800299e MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 800293e: f423 63c0 bic.w r3, r3, #1536 ; 0x600 8002942: f443 6380 orr.w r3, r3, #1024 ; 0x400 8002946: 6013 str r3, [r2, #0] return HAL_OK; 8002948: 2000 movs r0, #0 } 800294a: f85d 4b04 ldr.w r4, [sp], #4 800294e: 4770 bx lr CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8002950: f8d2 1080 ldr.w r1, [r2, #128] ; 0x80 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8002954: 4b2c ldr r3, [pc, #176] ; (8002a08 ) 8002956: 482d ldr r0, [pc, #180] ; (8002a0c ) CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8002958: f421 7180 bic.w r1, r1, #256 ; 0x100 800295c: f8c2 1080 str.w r1, [r2, #128] ; 0x80 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8002960: 6811 ldr r1, [r2, #0] 8002962: f421 61c0 bic.w r1, r1, #1536 ; 0x600 8002966: f441 7100 orr.w r1, r1, #512 ; 0x200 800296a: 6011 str r1, [r2, #0] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 800296c: 681c ldr r4, [r3, #0] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 800296e: 6951 ldr r1, [r2, #20] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8002970: 2332 movs r3, #50 ; 0x32 8002972: fb03 f304 mul.w r3, r3, r4 8002976: fba0 0303 umull r0, r3, r0, r3 800297a: 0c9b lsrs r3, r3, #18 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 800297c: 0548 lsls r0, r1, #21 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 800297e: f103 0301 add.w r3, r3, #1 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8002982: d506 bpl.n 8002992 8002984: e000 b.n 8002988 8002986: b123 cbz r3, 8002992 8002988: 6951 ldr r1, [r2, #20] 800298a: 0549 lsls r1, r1, #21 wait_loop_index--; 800298c: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8002990: d4f9 bmi.n 8002986 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8002992: 4b1c ldr r3, [pc, #112] ; (8002a04 ) 8002994: 695b ldr r3, [r3, #20] 8002996: 055c lsls r4, r3, #21 8002998: d5d6 bpl.n 8002948 return HAL_TIMEOUT; 800299a: 2003 movs r0, #3 800299c: e7c9 b.n 8002932 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 800299e: f403 63c0 and.w r3, r3, #1536 ; 0x600 80029a2: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80029a6: d009 beq.n 80029bc SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 80029a8: f8d2 3080 ldr.w r3, [r2, #128] ; 0x80 } 80029ac: f85d 4b04 ldr.w r4, [sp], #4 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 80029b0: f443 7380 orr.w r3, r3, #256 ; 0x100 return HAL_OK; 80029b4: 2000 movs r0, #0 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 80029b6: f8c2 3080 str.w r3, [r2, #128] ; 0x80 } 80029ba: 4770 bx lr SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 80029bc: f8d2 1080 ldr.w r1, [r2, #128] ; 0x80 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 80029c0: 4b11 ldr r3, [pc, #68] ; (8002a08 ) 80029c2: 4812 ldr r0, [pc, #72] ; (8002a0c ) SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 80029c4: f441 7180 orr.w r1, r1, #256 ; 0x100 80029c8: f8c2 1080 str.w r1, [r2, #128] ; 0x80 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 80029cc: 6811 ldr r1, [r2, #0] 80029ce: f421 61c0 bic.w r1, r1, #1536 ; 0x600 80029d2: f441 7100 orr.w r1, r1, #512 ; 0x200 80029d6: 6011 str r1, [r2, #0] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 80029d8: 681c ldr r4, [r3, #0] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80029da: 6951 ldr r1, [r2, #20] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 80029dc: 2332 movs r3, #50 ; 0x32 80029de: fb03 f304 mul.w r3, r3, r4 80029e2: fba0 0303 umull r0, r3, r0, r3 80029e6: 0c9b lsrs r3, r3, #18 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80029e8: 0548 lsls r0, r1, #21 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 80029ea: f103 0301 add.w r3, r3, #1 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80029ee: d5d0 bpl.n 8002992 80029f0: e001 b.n 80029f6 80029f2: 2b00 cmp r3, #0 80029f4: d0cd beq.n 8002992 80029f6: 6951 ldr r1, [r2, #20] 80029f8: 0549 lsls r1, r1, #21 wait_loop_index--; 80029fa: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80029fe: d5c8 bpl.n 8002992 8002a00: e7f7 b.n 80029f2 8002a02: bf00 nop 8002a04: 40007000 .word 0x40007000 8002a08: 20000804 .word 0x20000804 8002a0c: 431bde83 .word 0x431bde83 08002a10 : * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); 8002a10: 4a02 ldr r2, [pc, #8] ; (8002a1c ) 8002a12: 6893 ldr r3, [r2, #8] 8002a14: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8002a18: 6093 str r3, [r2, #8] } 8002a1a: 4770 bx lr 8002a1c: 40007000 .word 0x40007000 08002a20 : uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8002a20: 2800 cmp r0, #0 8002a22: f000 8200 beq.w 8002e26 { 8002a26: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8002a2a: 6803 ldr r3, [r0, #0] 8002a2c: 07d9 lsls r1, r3, #31 { 8002a2e: b082 sub sp, #8 8002a30: 4604 mov r4, r0 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8002a32: d52d bpl.n 8002a90 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002a34: 49af ldr r1, [pc, #700] ; (8002cf4 ) 8002a36: 688a ldr r2, [r1, #8] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8002a38: 68c9 ldr r1, [r1, #12] temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002a3a: f002 020c and.w r2, r2, #12 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) 8002a3e: 2a0c cmp r2, #12 8002a40: f000 8107 beq.w 8002c52 8002a44: 2a08 cmp r2, #8 8002a46: f000 8109 beq.w 8002c5c } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8002a4a: 6863 ldr r3, [r4, #4] 8002a4c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8002a50: f000 8177 beq.w 8002d42 8002a54: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8002a58: f000 81d8 beq.w 8002e0c 8002a5c: 4da5 ldr r5, [pc, #660] ; (8002cf4 ) 8002a5e: 682a ldr r2, [r5, #0] 8002a60: f422 3280 bic.w r2, r2, #65536 ; 0x10000 8002a64: 602a str r2, [r5, #0] 8002a66: 682a ldr r2, [r5, #0] 8002a68: f422 2280 bic.w r2, r2, #262144 ; 0x40000 8002a6c: 602a str r2, [r5, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8002a6e: 2b00 cmp r3, #0 8002a70: f040 816c bne.w 8002d4c } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002a74: f7fe fde6 bl 8001644 8002a78: 4606 mov r6, r0 /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8002a7a: e005 b.n 8002a88 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002a7c: f7fe fde2 bl 8001644 8002a80: 1b80 subs r0, r0, r6 8002a82: 2864 cmp r0, #100 ; 0x64 8002a84: f200 817f bhi.w 8002d86 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8002a88: 682b ldr r3, [r5, #0] 8002a8a: 039f lsls r7, r3, #14 8002a8c: d4f6 bmi.n 8002a7c 8002a8e: 6823 ldr r3, [r4, #0] } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8002a90: 079e lsls r6, r3, #30 8002a92: d528 bpl.n 8002ae6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002a94: 4a97 ldr r2, [pc, #604] ; (8002cf4 ) 8002a96: 6893 ldr r3, [r2, #8] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8002a98: 68d2 ldr r2, [r2, #12] temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002a9a: f003 030c and.w r3, r3, #12 if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) 8002a9e: 2b0c cmp r3, #12 8002aa0: f000 8130 beq.w 8002d04 8002aa4: 2b04 cmp r3, #4 8002aa6: f000 8132 beq.w 8002d0e } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8002aaa: 68e3 ldr r3, [r4, #12] { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8002aac: 4d91 ldr r5, [pc, #580] ; (8002cf4 ) if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8002aae: 2b00 cmp r3, #0 8002ab0: f000 815a beq.w 8002d68 __HAL_RCC_HSI_ENABLE(); 8002ab4: 682b ldr r3, [r5, #0] 8002ab6: f443 7380 orr.w r3, r3, #256 ; 0x100 8002aba: 602b str r3, [r5, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002abc: f7fe fdc2 bl 8001644 8002ac0: 4606 mov r6, r0 /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002ac2: e005 b.n 8002ad0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8002ac4: f7fe fdbe bl 8001644 8002ac8: 1b80 subs r0, r0, r6 8002aca: 2802 cmp r0, #2 8002acc: f200 815b bhi.w 8002d86 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002ad0: 682b ldr r3, [r5, #0] 8002ad2: 0558 lsls r0, r3, #21 8002ad4: d5f6 bpl.n 8002ac4 return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002ad6: 686b ldr r3, [r5, #4] 8002ad8: 6922 ldr r2, [r4, #16] 8002ada: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 8002ade: ea43 6302 orr.w r3, r3, r2, lsl #24 8002ae2: 606b str r3, [r5, #4] 8002ae4: 6823 ldr r3, [r4, #0] } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8002ae6: 071a lsls r2, r3, #28 8002ae8: d519 bpl.n 8002b1e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8002aea: 6963 ldr r3, [r4, #20] { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8002aec: 4d81 ldr r5, [pc, #516] ; (8002cf4 ) if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8002aee: 2b00 cmp r3, #0 8002af0: f000 809a beq.w 8002c28 __HAL_RCC_LSI_ENABLE(); 8002af4: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8002af8: f043 0301 orr.w r3, r3, #1 8002afc: f8c5 3094 str.w r3, [r5, #148] ; 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002b00: f7fe fda0 bl 8001644 8002b04: 4606 mov r6, r0 /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002b06: e005 b.n 8002b14 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002b08: f7fe fd9c bl 8001644 8002b0c: 1b80 subs r0, r0, r6 8002b0e: 2802 cmp r0, #2 8002b10: f200 8139 bhi.w 8002d86 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002b14: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8002b18: 079b lsls r3, r3, #30 8002b1a: d5f5 bpl.n 8002b08 8002b1c: 6823 ldr r3, [r4, #0] } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8002b1e: 075e lsls r6, r3, #29 8002b20: d541 bpl.n 8002ba6 /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8002b22: 4b74 ldr r3, [pc, #464] ; (8002cf4 ) 8002b24: 6d9a ldr r2, [r3, #88] ; 0x58 8002b26: 00d5 lsls r5, r2, #3 8002b28: f100 8131 bmi.w 8002d8e { __HAL_RCC_PWR_CLK_ENABLE(); 8002b2c: 6d9a ldr r2, [r3, #88] ; 0x58 8002b2e: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 8002b32: 659a str r2, [r3, #88] ; 0x58 8002b34: 6d9b ldr r3, [r3, #88] ; 0x58 8002b36: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8002b3a: 9301 str r3, [sp, #4] 8002b3c: 9b01 ldr r3, [sp, #4] pwrclkchanged = SET; 8002b3e: 2501 movs r5, #1 } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8002b40: 4e6d ldr r6, [pc, #436] ; (8002cf8 ) 8002b42: 6833 ldr r3, [r6, #0] 8002b44: 05d8 lsls r0, r3, #23 8002b46: f140 8150 bpl.w 8002dea } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8002b4a: 68a3 ldr r3, [r4, #8] 8002b4c: 2b01 cmp r3, #1 8002b4e: f000 8120 beq.w 8002d92 8002b52: 2b05 cmp r3, #5 8002b54: f000 8169 beq.w 8002e2a 8002b58: 4e66 ldr r6, [pc, #408] ; (8002cf4 ) 8002b5a: f8d6 2090 ldr.w r2, [r6, #144] ; 0x90 8002b5e: f022 0201 bic.w r2, r2, #1 8002b62: f8c6 2090 str.w r2, [r6, #144] ; 0x90 8002b66: f8d6 2090 ldr.w r2, [r6, #144] ; 0x90 8002b6a: f022 0204 bic.w r2, r2, #4 8002b6e: f8c6 2090 str.w r2, [r6, #144] ; 0x90 /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8002b72: 2b00 cmp r3, #0 8002b74: f040 8114 bne.w 8002da0 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002b78: f7fe fd64 bl 8001644 /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002b7c: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 8002b80: 4607 mov r7, r0 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8002b82: e005 b.n 8002b90 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002b84: f7fe fd5e bl 8001644 8002b88: 1bc0 subs r0, r0, r7 8002b8a: 4540 cmp r0, r8 8002b8c: f200 80fb bhi.w 8002d86 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8002b90: f8d6 3090 ldr.w r3, [r6, #144] ; 0x90 8002b94: 079b lsls r3, r3, #30 8002b96: d4f5 bmi.n 8002b84 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8002b98: b125 cbz r5, 8002ba4 { __HAL_RCC_PWR_CLK_DISABLE(); 8002b9a: 4a56 ldr r2, [pc, #344] ; (8002cf4 ) 8002b9c: 6d93 ldr r3, [r2, #88] ; 0x58 8002b9e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8002ba2: 6593 str r3, [r2, #88] ; 0x58 8002ba4: 6823 ldr r3, [r4, #0] } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8002ba6: 069d lsls r5, r3, #26 8002ba8: d518 bpl.n 8002bdc { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8002baa: 69a3 ldr r3, [r4, #24] { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8002bac: 4d51 ldr r5, [pc, #324] ; (8002cf4 ) if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8002bae: 2b00 cmp r3, #0 8002bb0: f000 8107 beq.w 8002dc2 __HAL_RCC_HSI48_ENABLE(); 8002bb4: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 8002bb8: f043 0301 orr.w r3, r3, #1 8002bbc: f8c5 3098 str.w r3, [r5, #152] ; 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002bc0: f7fe fd40 bl 8001644 8002bc4: 4606 mov r6, r0 /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 8002bc6: e005 b.n 8002bd4 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8002bc8: f7fe fd3c bl 8001644 8002bcc: 1b80 subs r0, r0, r6 8002bce: 2802 cmp r0, #2 8002bd0: f200 80d9 bhi.w 8002d86 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 8002bd4: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 8002bd8: 0798 lsls r0, r3, #30 8002bda: d5f5 bpl.n 8002bc8 /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8002bdc: 69e0 ldr r0, [r4, #28] 8002bde: 2800 cmp r0, #0 8002be0: f000 8084 beq.w 8002cec { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8002be4: 4d43 ldr r5, [pc, #268] ; (8002cf4 ) 8002be6: 68ab ldr r3, [r5, #8] 8002be8: f003 030c and.w r3, r3, #12 8002bec: 2b0c cmp r3, #12 8002bee: f000 812a beq.w 8002e46 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8002bf2: 682b ldr r3, [r5, #0] if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8002bf4: 2802 cmp r0, #2 __HAL_RCC_PLL_DISABLE(); 8002bf6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8002bfa: 602b str r3, [r5, #0] if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8002bfc: d03b beq.n 8002c76 { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002bfe: f7fe fd21 bl 8001644 /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002c02: 462c mov r4, r5 tickstart = HAL_GetTick(); 8002c04: 4605 mov r5, r0 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002c06: e005 b.n 8002c14 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002c08: f7fe fd1c bl 8001644 8002c0c: 1b40 subs r0, r0, r5 8002c0e: 2802 cmp r0, #2 8002c10: f200 80b9 bhi.w 8002d86 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002c14: 6823 ldr r3, [r4, #0] 8002c16: f013 7300 ands.w r3, r3, #33554432 ; 0x2000000 8002c1a: d1f5 bne.n 8002c08 return HAL_TIMEOUT; } } /* Unselect PLL clock source and disable outputs to save power */ RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); 8002c1c: 68e1 ldr r1, [r4, #12] 8002c1e: 4a37 ldr r2, [pc, #220] ; (8002cfc ) 8002c20: 400a ands r2, r1 } } } } return HAL_OK; 8002c22: 4618 mov r0, r3 RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); 8002c24: 60e2 str r2, [r4, #12] 8002c26: e062 b.n 8002cee __HAL_RCC_LSI_DISABLE(); 8002c28: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8002c2c: f023 0301 bic.w r3, r3, #1 8002c30: f8c5 3094 str.w r3, [r5, #148] ; 0x94 tickstart = HAL_GetTick(); 8002c34: f7fe fd06 bl 8001644 8002c38: 4606 mov r6, r0 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8002c3a: e005 b.n 8002c48 if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002c3c: f7fe fd02 bl 8001644 8002c40: 1b80 subs r0, r0, r6 8002c42: 2802 cmp r0, #2 8002c44: f200 809f bhi.w 8002d86 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8002c48: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8002c4c: 079f lsls r7, r3, #30 8002c4e: d4f5 bmi.n 8002c3c 8002c50: e764 b.n 8002b1c temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8002c52: f001 0103 and.w r1, r1, #3 if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) 8002c56: 2903 cmp r1, #3 8002c58: f47f aef7 bne.w 8002a4a if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8002c5c: 4a25 ldr r2, [pc, #148] ; (8002cf4 ) 8002c5e: 6812 ldr r2, [r2, #0] 8002c60: 0392 lsls r2, r2, #14 8002c62: f57f af15 bpl.w 8002a90 8002c66: 6862 ldr r2, [r4, #4] 8002c68: 2a00 cmp r2, #0 8002c6a: f47f af11 bne.w 8002a90 return HAL_ERROR; 8002c6e: 2001 movs r0, #1 } 8002c70: b002 add sp, #8 8002c72: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} tickstart = HAL_GetTick(); 8002c76: f7fe fce5 bl 8001644 8002c7a: 4606 mov r6, r0 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002c7c: e004 b.n 8002c88 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002c7e: f7fe fce1 bl 8001644 8002c82: 1b80 subs r0, r0, r6 8002c84: 2802 cmp r0, #2 8002c86: d87e bhi.n 8002d86 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8002c88: 682b ldr r3, [r5, #0] 8002c8a: 019a lsls r2, r3, #6 8002c8c: d4f7 bmi.n 8002c7e __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8002c8e: 68e9 ldr r1, [r5, #12] 8002c90: 4b1b ldr r3, [pc, #108] ; (8002d00 ) 8002c92: 6a22 ldr r2, [r4, #32] 8002c94: 6aa7 ldr r7, [r4, #40] ; 0x28 8002c96: 6ae6 ldr r6, [r4, #44] ; 0x2c 8002c98: 6a60 ldr r0, [r4, #36] ; 0x24 8002c9a: 400b ands r3, r1 8002c9c: 4313 orrs r3, r2 8002c9e: e9d4 120c ldrd r1, r2, [r4, #48] ; 0x30 8002ca2: ea43 2307 orr.w r3, r3, r7, lsl #8 8002ca6: ea43 63c6 orr.w r3, r3, r6, lsl #27 8002caa: 3801 subs r0, #1 8002cac: 0849 lsrs r1, r1, #1 8002cae: ea43 1300 orr.w r3, r3, r0, lsl #4 8002cb2: 3901 subs r1, #1 8002cb4: 0852 lsrs r2, r2, #1 8002cb6: ea43 5341 orr.w r3, r3, r1, lsl #21 8002cba: 3a01 subs r2, #1 8002cbc: ea43 6342 orr.w r3, r3, r2, lsl #25 8002cc0: 60eb str r3, [r5, #12] __HAL_RCC_PLL_ENABLE(); 8002cc2: 682b ldr r3, [r5, #0] while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002cc4: 4e0b ldr r6, [pc, #44] ; (8002cf4 ) __HAL_RCC_PLL_ENABLE(); 8002cc6: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8002cca: 602b str r3, [r5, #0] __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 8002ccc: 68eb ldr r3, [r5, #12] 8002cce: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8002cd2: 60eb str r3, [r5, #12] tickstart = HAL_GetTick(); 8002cd4: f7fe fcb6 bl 8001644 8002cd8: 4604 mov r4, r0 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002cda: e004 b.n 8002ce6 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002cdc: f7fe fcb2 bl 8001644 8002ce0: 1b00 subs r0, r0, r4 8002ce2: 2802 cmp r0, #2 8002ce4: d84f bhi.n 8002d86 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002ce6: 6833 ldr r3, [r6, #0] 8002ce8: 019b lsls r3, r3, #6 8002cea: d5f7 bpl.n 8002cdc return HAL_OK; 8002cec: 2000 movs r0, #0 } 8002cee: b002 add sp, #8 8002cf0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8002cf4: 40021000 .word 0x40021000 8002cf8: 40007000 .word 0x40007000 8002cfc: feeefffc .word 0xfeeefffc 8002d00: 019f800c .word 0x019f800c temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8002d04: f002 0203 and.w r2, r2, #3 if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) 8002d08: 2a02 cmp r2, #2 8002d0a: f47f aece bne.w 8002aaa if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8002d0e: 4b68 ldr r3, [pc, #416] ; (8002eb0 ) 8002d10: 681b ldr r3, [r3, #0] 8002d12: 055d lsls r5, r3, #21 8002d14: d502 bpl.n 8002d1c 8002d16: 68e3 ldr r3, [r4, #12] 8002d18: 2b00 cmp r3, #0 8002d1a: d0a8 beq.n 8002c6e __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002d1c: 4a64 ldr r2, [pc, #400] ; (8002eb0 ) 8002d1e: 6920 ldr r0, [r4, #16] 8002d20: 6853 ldr r3, [r2, #4] if (HAL_InitTick(uwTickPrio) != HAL_OK) 8002d22: 4964 ldr r1, [pc, #400] ; (8002eb4 ) __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002d24: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 8002d28: ea43 6300 orr.w r3, r3, r0, lsl #24 8002d2c: 6053 str r3, [r2, #4] if (HAL_InitTick(uwTickPrio) != HAL_OK) 8002d2e: 6808 ldr r0, [r1, #0] 8002d30: f7fe fc46 bl 80015c0 8002d34: 2800 cmp r0, #0 8002d36: d19a bne.n 8002c6e 8002d38: 6823 ldr r3, [r4, #0] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8002d3a: 071a lsls r2, r3, #28 8002d3c: f57f aeef bpl.w 8002b1e 8002d40: e6d3 b.n 8002aea __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8002d42: 4a5b ldr r2, [pc, #364] ; (8002eb0 ) 8002d44: 6813 ldr r3, [r2, #0] 8002d46: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8002d4a: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 8002d4c: f7fe fc7a bl 8001644 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002d50: 4e57 ldr r6, [pc, #348] ; (8002eb0 ) tickstart = HAL_GetTick(); 8002d52: 4605 mov r5, r0 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002d54: e004 b.n 8002d60 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002d56: f7fe fc75 bl 8001644 8002d5a: 1b40 subs r0, r0, r5 8002d5c: 2864 cmp r0, #100 ; 0x64 8002d5e: d812 bhi.n 8002d86 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002d60: 6833 ldr r3, [r6, #0] 8002d62: 039b lsls r3, r3, #14 8002d64: d5f7 bpl.n 8002d56 8002d66: e692 b.n 8002a8e __HAL_RCC_HSI_DISABLE(); 8002d68: 682b ldr r3, [r5, #0] 8002d6a: f423 7380 bic.w r3, r3, #256 ; 0x100 8002d6e: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 8002d70: f7fe fc68 bl 8001644 8002d74: 4606 mov r6, r0 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8002d76: 682b ldr r3, [r5, #0] 8002d78: 0559 lsls r1, r3, #21 8002d7a: d5dd bpl.n 8002d38 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8002d7c: f7fe fc62 bl 8001644 8002d80: 1b80 subs r0, r0, r6 8002d82: 2802 cmp r0, #2 8002d84: d9f7 bls.n 8002d76 return HAL_TIMEOUT; 8002d86: 2003 movs r0, #3 } 8002d88: b002 add sp, #8 8002d8a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} FlagStatus pwrclkchanged = RESET; 8002d8e: 2500 movs r5, #0 8002d90: e6d6 b.n 8002b40 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8002d92: 4a47 ldr r2, [pc, #284] ; (8002eb0 ) 8002d94: f8d2 3090 ldr.w r3, [r2, #144] ; 0x90 8002d98: f043 0301 orr.w r3, r3, #1 8002d9c: f8c2 3090 str.w r3, [r2, #144] ; 0x90 tickstart = HAL_GetTick(); 8002da0: f7fe fc50 bl 8001644 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8002da4: 4f42 ldr r7, [pc, #264] ; (8002eb0 ) tickstart = HAL_GetTick(); 8002da6: 4606 mov r6, r0 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002da8: f241 3888 movw r8, #5000 ; 0x1388 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8002dac: e004 b.n 8002db8 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002dae: f7fe fc49 bl 8001644 8002db2: 1b80 subs r0, r0, r6 8002db4: 4540 cmp r0, r8 8002db6: d8e6 bhi.n 8002d86 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8002db8: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 8002dbc: 079a lsls r2, r3, #30 8002dbe: d5f6 bpl.n 8002dae 8002dc0: e6ea b.n 8002b98 __HAL_RCC_HSI48_DISABLE(); 8002dc2: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 8002dc6: f023 0301 bic.w r3, r3, #1 8002dca: f8c5 3098 str.w r3, [r5, #152] ; 0x98 tickstart = HAL_GetTick(); 8002dce: f7fe fc39 bl 8001644 8002dd2: 4606 mov r6, r0 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 8002dd4: e004 b.n 8002de0 if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8002dd6: f7fe fc35 bl 8001644 8002dda: 1b80 subs r0, r0, r6 8002ddc: 2802 cmp r0, #2 8002dde: d8d2 bhi.n 8002d86 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 8002de0: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 8002de4: 0799 lsls r1, r3, #30 8002de6: d4f6 bmi.n 8002dd6 8002de8: e6f8 b.n 8002bdc SET_BIT(PWR->CR1, PWR_CR1_DBP); 8002dea: 6833 ldr r3, [r6, #0] 8002dec: f443 7380 orr.w r3, r3, #256 ; 0x100 8002df0: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 8002df2: f7fe fc27 bl 8001644 8002df6: 4607 mov r7, r0 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8002df8: 6833 ldr r3, [r6, #0] 8002dfa: 05d9 lsls r1, r3, #23 8002dfc: f53f aea5 bmi.w 8002b4a if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8002e00: f7fe fc20 bl 8001644 8002e04: 1bc0 subs r0, r0, r7 8002e06: 2802 cmp r0, #2 8002e08: d9f6 bls.n 8002df8 8002e0a: e7bc b.n 8002d86 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8002e0c: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 8002e10: f5a3 333c sub.w r3, r3, #192512 ; 0x2f000 8002e14: 681a ldr r2, [r3, #0] 8002e16: f442 2280 orr.w r2, r2, #262144 ; 0x40000 8002e1a: 601a str r2, [r3, #0] 8002e1c: 681a ldr r2, [r3, #0] 8002e1e: f442 3280 orr.w r2, r2, #65536 ; 0x10000 8002e22: 601a str r2, [r3, #0] if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8002e24: e792 b.n 8002d4c return HAL_ERROR; 8002e26: 2001 movs r0, #1 } 8002e28: 4770 bx lr __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8002e2a: 4b21 ldr r3, [pc, #132] ; (8002eb0 ) 8002e2c: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 8002e30: f042 0204 orr.w r2, r2, #4 8002e34: f8c3 2090 str.w r2, [r3, #144] ; 0x90 8002e38: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 8002e3c: f042 0201 orr.w r2, r2, #1 8002e40: f8c3 2090 str.w r2, [r3, #144] ; 0x90 if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8002e44: e7ac b.n 8002da0 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8002e46: 2801 cmp r0, #1 8002e48: f43f af51 beq.w 8002cee temp_pllckcfg = RCC->PLLCFGR; 8002e4c: 68eb ldr r3, [r5, #12] if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002e4e: 6a22 ldr r2, [r4, #32] 8002e50: f003 0103 and.w r1, r3, #3 8002e54: 4291 cmp r1, r2 8002e56: f47f af0a bne.w 8002c6e (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 8002e5a: 6a61 ldr r1, [r4, #36] ; 0x24 8002e5c: f003 02f0 and.w r2, r3, #240 ; 0xf0 8002e60: 3901 subs r1, #1 if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8002e62: ebb2 1f01 cmp.w r2, r1, lsl #4 8002e66: f47f af02 bne.w 8002c6e (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 8002e6a: 6aa1 ldr r1, [r4, #40] ; 0x28 8002e6c: f403 42fe and.w r2, r3, #32512 ; 0x7f00 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 8002e70: ebb2 2f01 cmp.w r2, r1, lsl #8 8002e74: f47f aefb bne.w 8002c6e (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 8002e78: 6ae1 ldr r1, [r4, #44] ; 0x2c 8002e7a: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 8002e7e: ebb2 6fc1 cmp.w r2, r1, lsl #27 8002e82: f47f aef4 bne.w 8002c6e (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 8002e86: 6b22 ldr r2, [r4, #48] ; 0x30 8002e88: 0852 lsrs r2, r2, #1 8002e8a: 3a01 subs r2, #1 8002e8c: f403 01c0 and.w r1, r3, #6291456 ; 0x600000 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 8002e90: ebb1 5f42 cmp.w r1, r2, lsl #21 8002e94: f47f aeeb bne.w 8002c6e (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 8002e98: 6b62 ldr r2, [r4, #52] ; 0x34 8002e9a: 0852 lsrs r2, r2, #1 8002e9c: 3a01 subs r2, #1 8002e9e: f003 63c0 and.w r3, r3, #100663296 ; 0x6000000 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 8002ea2: ebb3 6f42 cmp.w r3, r2, lsl #25 return HAL_ERROR; 8002ea6: bf14 ite ne 8002ea8: 2001 movne r0, #1 8002eaa: 2000 moveq r0, #0 8002eac: e71f b.n 8002cee 8002eae: bf00 nop 8002eb0: 40021000 .word 0x40021000 8002eb4: 2000080c .word 0x2000080c 08002eb8 : uint32_t HAL_RCC_GetSysClockFreq(void) { uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8002eb8: 4b18 ldr r3, [pc, #96] ; (8002f1c ) 8002eba: 689a ldr r2, [r3, #8] 8002ebc: f002 020c and.w r2, r2, #12 8002ec0: 2a04 cmp r2, #4 8002ec2: d027 beq.n 8002f14 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8002ec4: 689a ldr r2, [r3, #8] 8002ec6: f002 020c and.w r2, r2, #12 8002eca: 2a08 cmp r2, #8 8002ecc: d024 beq.n 8002f18 { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) 8002ece: 689a ldr r2, [r3, #8] 8002ed0: f002 020c and.w r2, r2, #12 8002ed4: 2a0c cmp r2, #12 8002ed6: d001 beq.n 8002edc pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; } else { sysclockfreq = 0U; 8002ed8: 2000 movs r0, #0 } return sysclockfreq; } 8002eda: 4770 bx lr pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8002edc: 68d9 ldr r1, [r3, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8002ede: 68d8 ldr r0, [r3, #12] pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8002ee0: 68db ldr r3, [r3, #12] pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8002ee2: f001 0103 and.w r1, r1, #3 pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8002ee6: f3c0 1003 ubfx r0, r0, #4, #4 switch (pllsource) 8002eea: 2903 cmp r1, #3 pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8002eec: f3c3 2306 ubfx r3, r3, #8, #7 pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8002ef0: f100 0201 add.w r2, r0, #1 pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8002ef4: bf0c ite eq 8002ef6: 480a ldreq r0, [pc, #40] ; (8002f20 ) pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8002ef8: 480a ldrne r0, [pc, #40] ; (8002f24 ) 8002efa: fbb0 f0f2 udiv r0, r0, r2 8002efe: fb00 f003 mul.w r0, r0, r3 pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8002f02: 4b06 ldr r3, [pc, #24] ; (8002f1c ) 8002f04: 68db ldr r3, [r3, #12] 8002f06: f3c3 6341 ubfx r3, r3, #25, #2 8002f0a: 3301 adds r3, #1 8002f0c: 005b lsls r3, r3, #1 sysclockfreq = pllvco/pllr; 8002f0e: fbb0 f0f3 udiv r0, r0, r3 return sysclockfreq; 8002f12: 4770 bx lr sysclockfreq = HSI_VALUE; 8002f14: 4803 ldr r0, [pc, #12] ; (8002f24 ) 8002f16: 4770 bx lr sysclockfreq = HSE_VALUE; 8002f18: 4801 ldr r0, [pc, #4] ; (8002f20 ) 8002f1a: 4770 bx lr 8002f1c: 40021000 .word 0x40021000 8002f20: 007a1200 .word 0x007a1200 8002f24: 00f42400 .word 0x00f42400 08002f28 : if (RCC_ClkInitStruct == NULL) 8002f28: 2800 cmp r0, #0 8002f2a: f000 80ef beq.w 800310c if (FLatency > __HAL_FLASH_GET_LATENCY()) 8002f2e: 4a7f ldr r2, [pc, #508] ; (800312c ) { 8002f30: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} if (FLatency > __HAL_FLASH_GET_LATENCY()) 8002f34: 6813 ldr r3, [r2, #0] 8002f36: f003 030f and.w r3, r3, #15 8002f3a: 428b cmp r3, r1 8002f3c: 460d mov r5, r1 8002f3e: 4604 mov r4, r0 8002f40: d20c bcs.n 8002f5c __HAL_FLASH_SET_LATENCY(FLatency); 8002f42: 6813 ldr r3, [r2, #0] 8002f44: f023 030f bic.w r3, r3, #15 8002f48: 430b orrs r3, r1 8002f4a: 6013 str r3, [r2, #0] if (__HAL_FLASH_GET_LATENCY() != FLatency) 8002f4c: 6813 ldr r3, [r2, #0] 8002f4e: f003 030f and.w r3, r3, #15 8002f52: 428b cmp r3, r1 8002f54: d002 beq.n 8002f5c return HAL_ERROR; 8002f56: 2001 movs r0, #1 } 8002f58: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8002f5c: 6823 ldr r3, [r4, #0] 8002f5e: 07de lsls r6, r3, #31 8002f60: d563 bpl.n 800302a if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8002f62: 6862 ldr r2, [r4, #4] 8002f64: 2a03 cmp r2, #3 8002f66: f000 809a beq.w 800309e if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002f6a: 4b71 ldr r3, [pc, #452] ; (8003130 ) if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8002f6c: 2a02 cmp r2, #2 if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002f6e: 681b ldr r3, [r3, #0] if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8002f70: f000 8091 beq.w 8003096 if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002f74: 055b lsls r3, r3, #21 8002f76: d5ee bpl.n 8002f56 pllfreq = HAL_RCC_GetSysClockFreq(); 8002f78: f7ff ff9e bl 8002eb8 if(pllfreq > 80000000U) 8002f7c: 4b6d ldr r3, [pc, #436] ; (8003134 ) 8002f7e: 4298 cmp r0, r3 8002f80: f200 80c6 bhi.w 8003110 8002f84: 6862 ldr r2, [r4, #4] uint32_t hpre = RCC_SYSCLK_DIV1; 8002f86: f04f 0900 mov.w r9, #0 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8002f8a: 4e69 ldr r6, [pc, #420] ; (8003130 ) 8002f8c: 68b3 ldr r3, [r6, #8] 8002f8e: f023 0303 bic.w r3, r3, #3 8002f92: 431a orrs r2, r3 8002f94: 60b2 str r2, [r6, #8] tickstart = HAL_GetTick(); 8002f96: f7fe fb55 bl 8001644 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8002f9a: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 8002f9e: 4607 mov r7, r0 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002fa0: e004 b.n 8002fac if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8002fa2: f7fe fb4f bl 8001644 8002fa6: 1bc0 subs r0, r0, r7 8002fa8: 4540 cmp r0, r8 8002faa: d871 bhi.n 8003090 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002fac: 68b3 ldr r3, [r6, #8] 8002fae: 6862 ldr r2, [r4, #4] 8002fb0: f003 030c and.w r3, r3, #12 8002fb4: ebb3 0f82 cmp.w r3, r2, lsl #2 8002fb8: d1f3 bne.n 8002fa2 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8002fba: 6823 ldr r3, [r4, #0] 8002fbc: 079f lsls r7, r3, #30 8002fbe: d436 bmi.n 800302e if(hpre == RCC_SYSCLK_DIV2) 8002fc0: f1b9 0f80 cmp.w r9, #128 ; 0x80 8002fc4: d103 bne.n 8002fce MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); 8002fc6: 68b3 ldr r3, [r6, #8] 8002fc8: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8002fcc: 60b3 str r3, [r6, #8] if (FLatency < __HAL_FLASH_GET_LATENCY()) 8002fce: 4e57 ldr r6, [pc, #348] ; (800312c ) 8002fd0: 6833 ldr r3, [r6, #0] 8002fd2: f003 030f and.w r3, r3, #15 8002fd6: 42ab cmp r3, r5 8002fd8: d846 bhi.n 8003068 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8002fda: 6823 ldr r3, [r4, #0] 8002fdc: 075a lsls r2, r3, #29 8002fde: d506 bpl.n 8002fee MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8002fe0: 4953 ldr r1, [pc, #332] ; (8003130 ) 8002fe2: 68e0 ldr r0, [r4, #12] 8002fe4: 688a ldr r2, [r1, #8] 8002fe6: f422 62e0 bic.w r2, r2, #1792 ; 0x700 8002fea: 4302 orrs r2, r0 8002fec: 608a str r2, [r1, #8] if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8002fee: 071b lsls r3, r3, #28 8002ff0: d507 bpl.n 8003002 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8002ff2: 4a4f ldr r2, [pc, #316] ; (8003130 ) 8002ff4: 6921 ldr r1, [r4, #16] 8002ff6: 6893 ldr r3, [r2, #8] 8002ff8: f423 5360 bic.w r3, r3, #14336 ; 0x3800 8002ffc: ea43 03c1 orr.w r3, r3, r1, lsl #3 8003000: 6093 str r3, [r2, #8] SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 8003002: f7ff ff59 bl 8002eb8 8003006: 4a4a ldr r2, [pc, #296] ; (8003130 ) 8003008: 4c4b ldr r4, [pc, #300] ; (8003138 ) 800300a: 6892 ldr r2, [r2, #8] 800300c: 494b ldr r1, [pc, #300] ; (800313c ) 800300e: f3c2 1203 ubfx r2, r2, #4, #4 8003012: 4603 mov r3, r0 8003014: 5ca2 ldrb r2, [r4, r2] return HAL_InitTick(uwTickPrio); 8003016: 484a ldr r0, [pc, #296] ; (8003140 ) SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 8003018: f002 021f and.w r2, r2, #31 800301c: 40d3 lsrs r3, r2 800301e: 600b str r3, [r1, #0] return HAL_InitTick(uwTickPrio); 8003020: 6800 ldr r0, [r0, #0] } 8003022: e8bd 43f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, lr} return HAL_InitTick(uwTickPrio); 8003026: f7fe bacb b.w 80015c0 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800302a: 0798 lsls r0, r3, #30 800302c: d5cf bpl.n 8002fce if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800302e: 0758 lsls r0, r3, #29 8003030: d504 bpl.n 800303c MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003032: 493f ldr r1, [pc, #252] ; (8003130 ) 8003034: 688a ldr r2, [r1, #8] 8003036: f442 62e0 orr.w r2, r2, #1792 ; 0x700 800303a: 608a str r2, [r1, #8] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800303c: 0719 lsls r1, r3, #28 800303e: d506 bpl.n 800304e MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); 8003040: 4a3b ldr r2, [pc, #236] ; (8003130 ) 8003042: 6893 ldr r3, [r2, #8] 8003044: f423 537c bic.w r3, r3, #16128 ; 0x3f00 8003048: f443 63e0 orr.w r3, r3, #1792 ; 0x700 800304c: 6093 str r3, [r2, #8] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800304e: 4a38 ldr r2, [pc, #224] ; (8003130 ) 8003050: 68a1 ldr r1, [r4, #8] 8003052: 6893 ldr r3, [r2, #8] if (FLatency < __HAL_FLASH_GET_LATENCY()) 8003054: 4e35 ldr r6, [pc, #212] ; (800312c ) MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003056: f023 03f0 bic.w r3, r3, #240 ; 0xf0 800305a: 430b orrs r3, r1 800305c: 6093 str r3, [r2, #8] if (FLatency < __HAL_FLASH_GET_LATENCY()) 800305e: 6833 ldr r3, [r6, #0] 8003060: f003 030f and.w r3, r3, #15 8003064: 42ab cmp r3, r5 8003066: d9b8 bls.n 8002fda __HAL_FLASH_SET_LATENCY(FLatency); 8003068: 6833 ldr r3, [r6, #0] 800306a: f023 030f bic.w r3, r3, #15 800306e: 432b orrs r3, r5 8003070: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 8003072: f7fe fae7 bl 8001644 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003076: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 800307a: 4607 mov r7, r0 while (__HAL_FLASH_GET_LATENCY() != FLatency) 800307c: 6833 ldr r3, [r6, #0] 800307e: f003 030f and.w r3, r3, #15 8003082: 42ab cmp r3, r5 8003084: d0a9 beq.n 8002fda if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003086: f7fe fadd bl 8001644 800308a: 1bc0 subs r0, r0, r7 800308c: 4540 cmp r0, r8 800308e: d9f5 bls.n 800307c return HAL_TIMEOUT; 8003090: 2003 movs r0, #3 } 8003092: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003096: 039a lsls r2, r3, #14 8003098: f53f af6e bmi.w 8002f78 800309c: e75b b.n 8002f56 if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800309e: 4824 ldr r0, [pc, #144] ; (8003130 ) 80030a0: 6801 ldr r1, [r0, #0] 80030a2: 0189 lsls r1, r1, #6 80030a4: f57f af57 bpl.w 8002f56 uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 80030a8: 68c7 ldr r7, [r0, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80030aa: 68c1 ldr r1, [r0, #12] pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80030ac: 68c0 ldr r0, [r0, #12] pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 80030ae: f007 0703 and.w r7, r7, #3 pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80030b2: f3c1 1103 ubfx r1, r1, #4, #4 switch (pllsource) 80030b6: 2f03 cmp r7, #3 pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80030b8: f101 0601 add.w r6, r1, #1 pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80030bc: bf0c ite eq 80030be: 4921 ldreq r1, [pc, #132] ; (8003144 ) pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80030c0: 4921 ldrne r1, [pc, #132] ; (8003148 ) 80030c2: fbb1 f1f6 udiv r1, r1, r6 break; } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 80030c6: 4e1a ldr r6, [pc, #104] ; (8003130 ) if(pllfreq > 80000000U) 80030c8: 4f1a ldr r7, [pc, #104] ; (8003134 ) pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80030ca: f3c0 2006 ubfx r0, r0, #8, #7 80030ce: fb01 f100 mul.w r1, r1, r0 pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 80030d2: 68f0 ldr r0, [r6, #12] 80030d4: f3c0 6041 ubfx r0, r0, #25, #2 80030d8: 3001 adds r0, #1 80030da: 0040 lsls r0, r0, #1 sysclockfreq = pllvco/pllr; 80030dc: fbb1 f1f0 udiv r1, r1, r0 if(pllfreq > 80000000U) 80030e0: 42b9 cmp r1, r7 80030e2: d920 bls.n 8003126 if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 80030e4: 68b1 ldr r1, [r6, #8] 80030e6: f011 0ff0 tst.w r1, #240 ; 0xf0 80030ea: d005 beq.n 80030f8 80030ec: f013 0902 ands.w r9, r3, #2 80030f0: f43f af4b beq.w 8002f8a (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 80030f4: 68a3 ldr r3, [r4, #8] 80030f6: b9b3 cbnz r3, 8003126 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 80030f8: 490d ldr r1, [pc, #52] ; (8003130 ) 80030fa: 688b ldr r3, [r1, #8] 80030fc: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8003100: f043 0380 orr.w r3, r3, #128 ; 0x80 8003104: 608b str r3, [r1, #8] hpre = RCC_SYSCLK_DIV2; 8003106: f04f 0980 mov.w r9, #128 ; 0x80 800310a: e73e b.n 8002f8a return HAL_ERROR; 800310c: 2001 movs r0, #1 } 800310e: 4770 bx lr MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 8003110: 4a07 ldr r2, [pc, #28] ; (8003130 ) 8003112: 6893 ldr r3, [r2, #8] 8003114: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8003118: f043 0380 orr.w r3, r3, #128 ; 0x80 800311c: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 800311e: 6862 ldr r2, [r4, #4] 8003120: f04f 0980 mov.w r9, #128 ; 0x80 8003124: e731 b.n 8002f8a uint32_t hpre = RCC_SYSCLK_DIV1; 8003126: f04f 0900 mov.w r9, #0 800312a: e72e b.n 8002f8a 800312c: 40022000 .word 0x40022000 8003130: 40021000 .word 0x40021000 8003134: 04c4b400 .word 0x04c4b400 8003138: 08004028 .word 0x08004028 800313c: 20000804 .word 0x20000804 8003140: 2000080c .word 0x2000080c 8003144: 007a1200 .word 0x007a1200 8003148: 00f42400 .word 0x00f42400 0800314c : return SystemCoreClock; 800314c: 4b01 ldr r3, [pc, #4] ; (8003154 ) } 800314e: 6818 ldr r0, [r3, #0] 8003150: 4770 bx lr 8003152: bf00 nop 8003154: 20000804 .word 0x20000804 08003158 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003158: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800315c: 6803 ldr r3, [r0, #0] { 800315e: 4604 mov r4, r0 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8003160: f413 2000 ands.w r0, r3, #524288 ; 0x80000 { 8003164: b082 sub sp, #8 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8003166: d056 beq.n 8003216 /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003168: 4b9f ldr r3, [pc, #636] ; (80033e8 ) 800316a: 6d9a ldr r2, [r3, #88] ; 0x58 800316c: 00d5 lsls r5, r2, #3 800316e: f140 810c bpl.w 800338a FlagStatus pwrclkchanged = RESET; 8003172: 2700 movs r7, #0 __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003174: 4d9d ldr r5, [pc, #628] ; (80033ec ) 8003176: 682b ldr r3, [r5, #0] 8003178: f443 7380 orr.w r3, r3, #256 ; 0x100 800317c: 602b str r3, [r5, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800317e: f7fe fa61 bl 8001644 8003182: 4606 mov r6, r0 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003184: e005 b.n 8003192 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003186: f7fe fa5d bl 8001644 800318a: 1b83 subs r3, r0, r6 800318c: 2b02 cmp r3, #2 800318e: f200 8107 bhi.w 80033a0 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003192: 682b ldr r3, [r5, #0] 8003194: 05d8 lsls r0, r3, #23 8003196: d5f6 bpl.n 8003186 } if(ret == HAL_OK) { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 8003198: 4d93 ldr r5, [pc, #588] ; (80033e8 ) 800319a: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 800319e: f413 7340 ands.w r3, r3, #768 ; 0x300 80031a2: d027 beq.n 80031f4 80031a4: 6c22 ldr r2, [r4, #64] ; 0x40 80031a6: 429a cmp r2, r3 80031a8: d025 beq.n 80031f6 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 80031aa: f8d5 1090 ldr.w r1, [r5, #144] ; 0x90 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80031ae: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 80031b2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80031b6: f8c5 3090 str.w r3, [r5, #144] ; 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); 80031ba: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 80031be: f421 7040 bic.w r0, r1, #768 ; 0x300 __HAL_RCC_BACKUPRESET_RELEASE(); 80031c2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80031c6: 07c9 lsls r1, r1, #31 __HAL_RCC_BACKUPRESET_RELEASE(); 80031c8: f8c5 3090 str.w r3, [r5, #144] ; 0x90 RCC->BDCR = tmpregister; 80031cc: f8c5 0090 str.w r0, [r5, #144] ; 0x90 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80031d0: f140 8108 bpl.w 80033e4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80031d4: f7fe fa36 bl 8001644 /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80031d8: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 80031dc: 4606 mov r6, r0 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80031de: e005 b.n 80031ec if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80031e0: f7fe fa30 bl 8001644 80031e4: 1b80 subs r0, r0, r6 80031e6: 4540 cmp r0, r8 80031e8: f200 80da bhi.w 80033a0 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80031ec: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 80031f0: 079b lsls r3, r3, #30 80031f2: d5f5 bpl.n 80031e0 80031f4: 6c23 ldr r3, [r4, #64] ; 0x40 } if(ret == HAL_OK) { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80031f6: 497c ldr r1, [pc, #496] ; (80033e8 ) 80031f8: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90 80031fc: f422 7240 bic.w r2, r2, #768 ; 0x300 8003200: 4313 orrs r3, r2 8003202: f8c1 3090 str.w r3, [r1, #144] ; 0x90 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003206: 2000 movs r0, #0 /* set overall return value */ status = ret; } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 8003208: b127 cbz r7, 8003214 { __HAL_RCC_PWR_CLK_DISABLE(); 800320a: 4a77 ldr r2, [pc, #476] ; (80033e8 ) 800320c: 6d93 ldr r3, [r2, #88] ; 0x58 800320e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003212: 6593 str r3, [r2, #88] ; 0x58 8003214: 6823 ldr r3, [r4, #0] } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8003216: 07de lsls r6, r3, #31 8003218: d508 bpl.n 800322c { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 800321a: 4973 ldr r1, [pc, #460] ; (80033e8 ) 800321c: 6865 ldr r5, [r4, #4] 800321e: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8003222: f022 0203 bic.w r2, r2, #3 8003226: 432a orrs r2, r5 8003228: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 800322c: 079d lsls r5, r3, #30 800322e: d508 bpl.n 8003242 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8003230: 496d ldr r1, [pc, #436] ; (80033e8 ) 8003232: 68a5 ldr r5, [r4, #8] 8003234: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8003238: f022 020c bic.w r2, r2, #12 800323c: 432a orrs r2, r5 800323e: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 8003242: 0759 lsls r1, r3, #29 8003244: d508 bpl.n 8003258 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 8003246: 4968 ldr r1, [pc, #416] ; (80033e8 ) 8003248: 68e5 ldr r5, [r4, #12] 800324a: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 800324e: f022 0230 bic.w r2, r2, #48 ; 0x30 8003252: 432a orrs r2, r5 8003254: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 8003258: 071a lsls r2, r3, #28 800325a: d508 bpl.n 800326e { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 800325c: 4962 ldr r1, [pc, #392] ; (80033e8 ) 800325e: 6925 ldr r5, [r4, #16] 8003260: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8003264: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8003268: 432a orrs r2, r5 800326a: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800326e: 069f lsls r7, r3, #26 8003270: d508 bpl.n 8003284 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8003272: 495d ldr r1, [pc, #372] ; (80033e8 ) 8003274: 6965 ldr r5, [r4, #20] 8003276: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 800327a: f422 6240 bic.w r2, r2, #3072 ; 0xc00 800327e: 432a orrs r2, r5 8003280: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8003284: 065e lsls r6, r3, #25 8003286: d508 bpl.n 800329a { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8003288: 4957 ldr r1, [pc, #348] ; (80033e8 ) 800328a: 69a5 ldr r5, [r4, #24] 800328c: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8003290: f422 5240 bic.w r2, r2, #12288 ; 0x3000 8003294: 432a orrs r2, r5 8003296: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 800329a: 061d lsls r5, r3, #24 800329c: d508 bpl.n 80032b0 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 800329e: 4952 ldr r1, [pc, #328] ; (80033e8 ) 80032a0: 69e5 ldr r5, [r4, #28] 80032a2: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80032a6: f422 4240 bic.w r2, r2, #49152 ; 0xc000 80032aa: 432a orrs r2, r5 80032ac: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 80032b0: 05d9 lsls r1, r3, #23 80032b2: d508 bpl.n 80032c6 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 80032b4: 494c ldr r1, [pc, #304] ; (80033e8 ) 80032b6: 6a25 ldr r5, [r4, #32] 80032b8: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80032bc: f422 3240 bic.w r2, r2, #196608 ; 0x30000 80032c0: 432a orrs r2, r5 80032c2: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 80032c6: 059a lsls r2, r3, #22 80032c8: d508 bpl.n 80032dc { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 80032ca: 4947 ldr r1, [pc, #284] ; (80033e8 ) 80032cc: 6a65 ldr r5, [r4, #36] ; 0x24 80032ce: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80032d2: f422 2240 bic.w r2, r2, #786432 ; 0xc0000 80032d6: 432a orrs r2, r5 80032d8: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80032dc: 055f lsls r7, r3, #21 80032de: d50b bpl.n 80032f8 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80032e0: 4941 ldr r1, [pc, #260] ; (80033e8 ) 80032e2: 6aa5 ldr r5, [r4, #40] ; 0x28 80032e4: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80032e8: f422 1240 bic.w r2, r2, #3145728 ; 0x300000 80032ec: 432a orrs r2, r5 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) 80032ee: f5b5 1f80 cmp.w r5, #1048576 ; 0x100000 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80032f2: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) 80032f6: d055 beq.n 80033a4 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) 80032f8: 051e lsls r6, r3, #20 80032fa: d50b bpl.n 8003314 { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 80032fc: 493a ldr r1, [pc, #232] ; (80033e8 ) 80032fe: 6ae5 ldr r5, [r4, #44] ; 0x2c 8003300: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8003304: f422 0240 bic.w r2, r2, #12582912 ; 0xc00000 8003308: 432a orrs r2, r5 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) 800330a: f5b5 0f80 cmp.w r5, #4194304 ; 0x400000 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 800330e: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) 8003312: d04c beq.n 80033ae } } #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8003314: 04dd lsls r5, r3, #19 8003316: d50b bpl.n 8003330 { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8003318: 4933 ldr r1, [pc, #204] ; (80033e8 ) 800331a: 6b25 ldr r5, [r4, #48] ; 0x30 800331c: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8003320: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000 8003324: 432a orrs r2, r5 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) 8003326: f1b5 7f80 cmp.w r5, #16777216 ; 0x1000000 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800332a: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) 800332e: d043 beq.n 80033b8 #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 8003330: 0499 lsls r1, r3, #18 8003332: d50b bpl.n 800334c { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8003334: 492c ldr r1, [pc, #176] ; (80033e8 ) 8003336: 6b65 ldr r5, [r4, #52] ; 0x34 8003338: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 800333c: f022 6240 bic.w r2, r2, #201326592 ; 0xc000000 8003340: 432a orrs r2, r5 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 8003342: f1b5 6f00 cmp.w r5, #134217728 ; 0x8000000 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8003346: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 800334a: d03a beq.n 80033c2 } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 800334c: 045a lsls r2, r3, #17 800334e: d50b bpl.n 8003368 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8003350: 4925 ldr r1, [pc, #148] ; (80033e8 ) 8003352: 6ba5 ldr r5, [r4, #56] ; 0x38 8003354: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8003358: f022 6240 bic.w r2, r2, #201326592 ; 0xc000000 800335c: 432a orrs r2, r5 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 800335e: f1b5 6f00 cmp.w r5, #134217728 ; 0x8000000 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8003362: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 8003366: d031 beq.n 80033cc __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) 8003368: 041b lsls r3, r3, #16 800336a: d50b bpl.n 8003384 { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 800336c: 4a1e ldr r2, [pc, #120] ; (80033e8 ) 800336e: 6be1 ldr r1, [r4, #60] ; 0x3c 8003370: f8d2 3088 ldr.w r3, [r2, #136] ; 0x88 8003374: f023 5340 bic.w r3, r3, #805306368 ; 0x30000000 8003378: 430b orrs r3, r1 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) 800337a: f1b1 5f80 cmp.w r1, #268435456 ; 0x10000000 __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 800337e: f8c2 3088 str.w r3, [r2, #136] ; 0x88 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) 8003382: d028 beq.n 80033d6 } #endif /* QUADSPI */ return status; } 8003384: b002 add sp, #8 8003386: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_RCC_PWR_CLK_ENABLE(); 800338a: 6d9a ldr r2, [r3, #88] ; 0x58 800338c: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 8003390: 659a str r2, [r3, #88] ; 0x58 8003392: 6d9b ldr r3, [r3, #88] ; 0x58 8003394: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003398: 9301 str r3, [sp, #4] 800339a: 9b01 ldr r3, [sp, #4] pwrclkchanged = SET; 800339c: 2701 movs r7, #1 800339e: e6e9 b.n 8003174 ret = HAL_TIMEOUT; 80033a0: 2003 movs r0, #3 80033a2: e731 b.n 8003208 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80033a4: 68ca ldr r2, [r1, #12] 80033a6: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80033aa: 60ca str r2, [r1, #12] 80033ac: e7a4 b.n 80032f8 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80033ae: 68ca ldr r2, [r1, #12] 80033b0: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80033b4: 60ca str r2, [r1, #12] 80033b6: e7ad b.n 8003314 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80033b8: 68ca ldr r2, [r1, #12] 80033ba: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80033be: 60ca str r2, [r1, #12] 80033c0: e7b6 b.n 8003330 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80033c2: 68ca ldr r2, [r1, #12] 80033c4: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80033c8: 60ca str r2, [r1, #12] 80033ca: e7bf b.n 800334c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80033cc: 68ca ldr r2, [r1, #12] 80033ce: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80033d2: 60ca str r2, [r1, #12] 80033d4: e7c8 b.n 8003368 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 80033d6: 68d3 ldr r3, [r2, #12] 80033d8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80033dc: 60d3 str r3, [r2, #12] } 80033de: b002 add sp, #8 80033e0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80033e4: 4613 mov r3, r2 80033e6: e706 b.n 80031f6 80033e8: 40021000 .word 0x40021000 80033ec: 40007000 .word 0x40007000 080033f0 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) 80033f0: 2800 cmp r0, #0 80033f2: f000 8086 beq.w 8003502 { 80033f6: b538 push {r3, r4, r5, lr} assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80033f8: f890 303d ldrb.w r3, [r0, #61] ; 0x3d 80033fc: 4604 mov r4, r0 80033fe: f003 02ff and.w r2, r3, #255 ; 0xff 8003402: 2b00 cmp r3, #0 8003404: d075 beq.n 80034f2 /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8003406: 6823 ldr r3, [r4, #0] { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8003408: 493f ldr r1, [pc, #252] ; (8003508 ) htim->State = HAL_TIM_STATE_BUSY; 800340a: 2202 movs r2, #2 800340c: f884 203d strb.w r2, [r4, #61] ; 0x3d if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8003410: 428b cmp r3, r1 tmpcr1 = TIMx->CR1; 8003412: 681a ldr r2, [r3, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8003414: d059 beq.n 80034ca 8003416: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800341a: d021 beq.n 8003460 800341c: f5a1 3194 sub.w r1, r1, #75776 ; 0x12800 8003420: 428b cmp r3, r1 8003422: d01d beq.n 8003460 8003424: f501 6180 add.w r1, r1, #1024 ; 0x400 8003428: 428b cmp r3, r1 800342a: d019 beq.n 8003460 800342c: f501 3196 add.w r1, r1, #76800 ; 0x12c00 8003430: 428b cmp r3, r1 8003432: d04a beq.n 80034ca /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8003434: f501 6140 add.w r1, r1, #3072 ; 0xc00 8003438: 428b cmp r3, r1 800343a: d05f beq.n 80034fc 800343c: f501 6180 add.w r1, r1, #1024 ; 0x400 8003440: 428b cmp r3, r1 8003442: d05b beq.n 80034fc 8003444: f501 6180 add.w r1, r1, #1024 ; 0x400 8003448: 428b cmp r3, r1 800344a: d057 beq.n 80034fc tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800344c: 69a5 ldr r5, [r4, #24] TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800344e: 68e0 ldr r0, [r4, #12] /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8003450: 6861 ldr r1, [r4, #4] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8003452: f022 0280 bic.w r2, r2, #128 ; 0x80 8003456: 432a orrs r2, r5 TIMx->CR1 = tmpcr1; 8003458: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 800345a: 62d8 str r0, [r3, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 800345c: 6299 str r1, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800345e: e010 b.n 8003482 tmpcr1 |= Structure->CounterMode; 8003460: 68a1 ldr r1, [r4, #8] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8003462: 6925 ldr r5, [r4, #16] TIMx->ARR = (uint32_t)Structure->Period ; 8003464: 68e0 ldr r0, [r4, #12] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8003466: f022 0270 bic.w r2, r2, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 800346a: 430a orrs r2, r1 tmpcr1 &= ~TIM_CR1_CKD; 800346c: f422 7240 bic.w r2, r2, #768 ; 0x300 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8003470: 69a1 ldr r1, [r4, #24] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8003472: 432a orrs r2, r5 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8003474: f022 0280 bic.w r2, r2, #128 ; 0x80 8003478: 430a orrs r2, r1 TIMx->PSC = Structure->Prescaler; 800347a: 6861 ldr r1, [r4, #4] TIMx->CR1 = tmpcr1; 800347c: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 800347e: 62d8 str r0, [r3, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 8003480: 6299 str r1, [r3, #40] ; 0x28 TIMx->RCR = Structure->RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8003482: 2201 movs r2, #1 8003484: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8003486: 691a ldr r2, [r3, #16] 8003488: 07d2 lsls r2, r2, #31 800348a: d503 bpl.n 8003494 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 800348c: 691a ldr r2, [r3, #16] 800348e: f022 0201 bic.w r2, r2, #1 8003492: 611a str r2, [r3, #16] htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8003494: 2301 movs r3, #1 8003496: f884 3048 strb.w r3, [r4, #72] ; 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800349a: f884 303e strb.w r3, [r4, #62] ; 0x3e 800349e: f884 303f strb.w r3, [r4, #63] ; 0x3f 80034a2: f884 3040 strb.w r3, [r4, #64] ; 0x40 80034a6: f884 3041 strb.w r3, [r4, #65] ; 0x41 80034aa: f884 3042 strb.w r3, [r4, #66] ; 0x42 80034ae: f884 3043 strb.w r3, [r4, #67] ; 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80034b2: f884 3044 strb.w r3, [r4, #68] ; 0x44 80034b6: f884 3045 strb.w r3, [r4, #69] ; 0x45 80034ba: f884 3046 strb.w r3, [r4, #70] ; 0x46 80034be: f884 3047 strb.w r3, [r4, #71] ; 0x47 htim->State = HAL_TIM_STATE_READY; 80034c2: f884 303d strb.w r3, [r4, #61] ; 0x3d return HAL_OK; 80034c6: 2000 movs r0, #0 } 80034c8: bd38 pop {r3, r4, r5, pc} tmpcr1 |= Structure->CounterMode; 80034ca: 68a5 ldr r5, [r4, #8] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80034cc: 6920 ldr r0, [r4, #16] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80034ce: 69a1 ldr r1, [r4, #24] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80034d0: f022 0270 bic.w r2, r2, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 80034d4: 432a orrs r2, r5 tmpcr1 &= ~TIM_CR1_CKD; 80034d6: f422 7240 bic.w r2, r2, #768 ; 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 80034da: 4302 orrs r2, r0 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80034dc: f022 0280 bic.w r2, r2, #128 ; 0x80 80034e0: 430a orrs r2, r1 TIMx->CR1 = tmpcr1; 80034e2: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 80034e4: 68e2 ldr r2, [r4, #12] 80034e6: 62da str r2, [r3, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 80034e8: 6862 ldr r2, [r4, #4] 80034ea: 629a str r2, [r3, #40] ; 0x28 TIMx->RCR = Structure->RepetitionCounter; 80034ec: 6962 ldr r2, [r4, #20] 80034ee: 631a str r2, [r3, #48] ; 0x30 80034f0: e7c7 b.n 8003482 htim->Lock = HAL_UNLOCKED; 80034f2: f880 203c strb.w r2, [r0, #60] ; 0x3c HAL_TIM_Base_MspInit(htim); 80034f6: f7fd ffef bl 80014d8 80034fa: e784 b.n 8003406 tmpcr1 |= (uint32_t)Structure->ClockDivision; 80034fc: 6920 ldr r0, [r4, #16] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80034fe: 69a1 ldr r1, [r4, #24] 8003500: e7e9 b.n 80034d6 return HAL_ERROR; 8003502: 2001 movs r0, #1 } 8003504: 4770 bx lr 8003506: bf00 nop 8003508: 40012c00 .word 0x40012c00 0800350c : if (htim->State != HAL_TIM_STATE_READY) 800350c: f890 303d ldrb.w r3, [r0, #61] ; 0x3d 8003510: 2b01 cmp r3, #1 8003512: d122 bne.n 800355a __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8003514: 6803 ldr r3, [r0, #0] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8003516: 4917 ldr r1, [pc, #92] ; (8003574 ) htim->State = HAL_TIM_STATE_BUSY; 8003518: 2202 movs r2, #2 800351a: f880 203d strb.w r2, [r0, #61] ; 0x3d __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800351e: 68da ldr r2, [r3, #12] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8003520: 428b cmp r3, r1 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8003522: f042 0201 orr.w r2, r2, #1 8003526: 60da str r2, [r3, #12] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8003528: d019 beq.n 800355e 800352a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 800352e: d016 beq.n 800355e 8003530: 4a11 ldr r2, [pc, #68] ; (8003578 ) 8003532: 4293 cmp r3, r2 8003534: d013 beq.n 800355e 8003536: f502 6280 add.w r2, r2, #1024 ; 0x400 800353a: 4293 cmp r3, r2 800353c: d00f beq.n 800355e 800353e: f502 3296 add.w r2, r2, #76800 ; 0x12c00 8003542: 4293 cmp r3, r2 8003544: d00b beq.n 800355e 8003546: f502 6240 add.w r2, r2, #3072 ; 0xc00 800354a: 4293 cmp r3, r2 800354c: d007 beq.n 800355e __HAL_TIM_ENABLE(htim); 800354e: 681a ldr r2, [r3, #0] 8003550: f042 0201 orr.w r2, r2, #1 8003554: 601a str r2, [r3, #0] return HAL_OK; 8003556: 2000 movs r0, #0 8003558: 4770 bx lr return HAL_ERROR; 800355a: 2001 movs r0, #1 800355c: 4770 bx lr tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800355e: 6899 ldr r1, [r3, #8] 8003560: 4a06 ldr r2, [pc, #24] ; (800357c ) 8003562: 400a ands r2, r1 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8003564: 2a06 cmp r2, #6 8003566: d002 beq.n 800356e 8003568: f5b2 3f80 cmp.w r2, #65536 ; 0x10000 800356c: d1ef bne.n 800354e return HAL_OK; 800356e: 2000 movs r0, #0 } 8003570: 4770 bx lr 8003572: bf00 nop 8003574: 40012c00 .word 0x40012c00 8003578: 40000400 .word 0x40000400 800357c: 00010007 .word 0x00010007 08003580 : __HAL_LOCK(htim); 8003580: f890 303c ldrb.w r3, [r0, #60] ; 0x3c 8003584: 2b01 cmp r3, #1 8003586: f000 8089 beq.w 800369c 800358a: 4602 mov r2, r0 { 800358c: b4f0 push {r4, r5, r6, r7} htim->State = HAL_TIM_STATE_BUSY; 800358e: 2302 movs r3, #2 tmpsmcr = htim->Instance->SMCR; 8003590: 6814 ldr r4, [r2, #0] htim->State = HAL_TIM_STATE_BUSY; 8003592: f882 303d strb.w r3, [r2, #61] ; 0x3d __HAL_LOCK(htim); 8003596: 2001 movs r0, #1 8003598: f882 003c strb.w r0, [r2, #60] ; 0x3c tmpsmcr = htim->Instance->SMCR; 800359c: 68a6 ldr r6, [r4, #8] switch (sClockSourceConfig->ClockSource) 800359e: 680b ldr r3, [r1, #0] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80035a0: 4d5e ldr r5, [pc, #376] ; (800371c ) switch (sClockSourceConfig->ClockSource) 80035a2: 2b70 cmp r3, #112 ; 0x70 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80035a4: ea05 0506 and.w r5, r5, r6 htim->Instance->SMCR = tmpsmcr; 80035a8: 60a5 str r5, [r4, #8] switch (sClockSourceConfig->ClockSource) 80035aa: f000 80a5 beq.w 80036f8 80035ae: d827 bhi.n 8003600 80035b0: 2b50 cmp r3, #80 ; 0x50 80035b2: d075 beq.n 80036a0 80035b4: d93d bls.n 8003632 80035b6: 2b60 cmp r3, #96 ; 0x60 80035b8: d11a bne.n 80035f0 { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80035ba: 6a23 ldr r3, [r4, #32] TIMx->CCER &= ~TIM_CCER_CC2E; 80035bc: 6a20 ldr r0, [r4, #32] TIM_TI2_ConfigInputStage(htim->Instance, 80035be: 684e ldr r6, [r1, #4] 80035c0: 68cd ldr r5, [r1, #12] TIMx->CCER &= ~TIM_CCER_CC2E; 80035c2: f020 0010 bic.w r0, r0, #16 80035c6: 6220 str r0, [r4, #32] tmpccmr1 = TIMx->CCMR1; 80035c8: 69a1 ldr r1, [r4, #24] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 80035ca: f023 03a0 bic.w r3, r3, #160 ; 0xa0 tmpccmr1 &= ~TIM_CCMR1_IC2F; 80035ce: f421 4170 bic.w r1, r1, #61440 ; 0xf000 tmpccer |= (TIM_ICPolarity << 4U); 80035d2: ea43 1306 orr.w r3, r3, r6, lsl #4 tmpccmr1 |= (TIM_ICFilter << 12U); 80035d6: ea41 3105 orr.w r1, r1, r5, lsl #12 /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80035da: 61a1 str r1, [r4, #24] TIMx->CCER = tmpccer; 80035dc: 6223 str r3, [r4, #32] static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80035de: 68a3 ldr r3, [r4, #8] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80035e0: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 80035e4: f023 0370 bic.w r3, r3, #112 ; 0x70 /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80035e8: f043 0367 orr.w r3, r3, #103 ; 0x67 /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80035ec: 60a3 str r3, [r4, #8] HAL_StatusTypeDef status = HAL_OK; 80035ee: 2000 movs r0, #0 htim->State = HAL_TIM_STATE_READY; 80035f0: 2101 movs r1, #1 __HAL_UNLOCK(htim); 80035f2: 2300 movs r3, #0 htim->State = HAL_TIM_STATE_READY; 80035f4: f882 103d strb.w r1, [r2, #61] ; 0x3d __HAL_UNLOCK(htim); 80035f8: f882 303c strb.w r3, [r2, #60] ; 0x3c } 80035fc: bcf0 pop {r4, r5, r6, r7} 80035fe: 4770 bx lr switch (sClockSourceConfig->ClockSource) 8003600: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8003604: d067 beq.n 80036d6 8003606: d938 bls.n 800367a 8003608: 4945 ldr r1, [pc, #276] ; (8003720 ) 800360a: 428b cmp r3, r1 800360c: d006 beq.n 800361c 800360e: d92d bls.n 800366c 8003610: 4944 ldr r1, [pc, #272] ; (8003724 ) 8003612: 428b cmp r3, r1 8003614: d002 beq.n 800361c 8003616: 3130 adds r1, #48 ; 0x30 8003618: 428b cmp r3, r1 800361a: d1e9 bne.n 80035f0 tmpsmcr = TIMx->SMCR; 800361c: 68a0 ldr r0, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 800361e: f420 1040 bic.w r0, r0, #3145728 ; 0x300000 8003622: f020 0070 bic.w r0, r0, #112 ; 0x70 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8003626: 4303 orrs r3, r0 8003628: f043 0307 orr.w r3, r3, #7 TIMx->SMCR = tmpsmcr; 800362c: 60a3 str r3, [r4, #8] HAL_StatusTypeDef status = HAL_OK; 800362e: 2000 movs r0, #0 } 8003630: e7de b.n 80035f0 switch (sClockSourceConfig->ClockSource) 8003632: 2b40 cmp r3, #64 ; 0x40 8003634: d126 bne.n 8003684 tmpccer = TIMx->CCER; 8003636: 6a25 ldr r5, [r4, #32] TIMx->CCER &= ~TIM_CCER_CC1E; 8003638: 6a26 ldr r6, [r4, #32] TIM_TI1_ConfigInputStage(htim->Instance, 800363a: 6848 ldr r0, [r1, #4] 800363c: 68cf ldr r7, [r1, #12] TIMx->CCER &= ~TIM_CCER_CC1E; 800363e: f026 0601 bic.w r6, r6, #1 8003642: 6226 str r6, [r4, #32] tmpccmr1 = TIMx->CCMR1; 8003644: 69a3 ldr r3, [r4, #24] tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8003646: f025 010a bic.w r1, r5, #10 tmpccmr1 &= ~TIM_CCMR1_IC1F; 800364a: f023 03f0 bic.w r3, r3, #240 ; 0xf0 tmpccer |= TIM_ICPolarity; 800364e: 4301 orrs r1, r0 tmpccmr1 |= (TIM_ICFilter << 4U); 8003650: ea43 1307 orr.w r3, r3, r7, lsl #4 TIMx->CCMR1 = tmpccmr1; 8003654: 61a3 str r3, [r4, #24] TIMx->CCER = tmpccer; 8003656: 6221 str r1, [r4, #32] tmpsmcr = TIMx->SMCR; 8003658: 68a3 ldr r3, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 800365a: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 800365e: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8003662: f043 0347 orr.w r3, r3, #71 ; 0x47 TIMx->SMCR = tmpsmcr; 8003666: 60a3 str r3, [r4, #8] HAL_StatusTypeDef status = HAL_OK; 8003668: 2000 movs r0, #0 } 800366a: e7c1 b.n 80035f0 switch (sClockSourceConfig->ClockSource) 800366c: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 8003670: d0d4 beq.n 800361c 8003672: 3910 subs r1, #16 8003674: 428b cmp r3, r1 8003676: d0d1 beq.n 800361c 8003678: e7ba b.n 80035f0 HAL_StatusTypeDef status = HAL_OK; 800367a: f5b3 5080 subs.w r0, r3, #4096 ; 0x1000 800367e: bf18 it ne 8003680: 2001 movne r0, #1 8003682: e7b5 b.n 80035f0 switch (sClockSourceConfig->ClockSource) 8003684: d8b4 bhi.n 80035f0 8003686: 2b20 cmp r3, #32 8003688: d0c8 beq.n 800361c 800368a: d903 bls.n 8003694 800368c: 2b30 cmp r3, #48 ; 0x30 800368e: d0c5 beq.n 800361c 8003690: 2001 movs r0, #1 8003692: e7ad b.n 80035f0 8003694: f033 0110 bics.w r1, r3, #16 8003698: d1aa bne.n 80035f0 800369a: e7bf b.n 800361c __HAL_LOCK(htim); 800369c: 2002 movs r0, #2 } 800369e: 4770 bx lr tmpccer = TIMx->CCER; 80036a0: 6a25 ldr r5, [r4, #32] TIMx->CCER &= ~TIM_CCER_CC1E; 80036a2: 6a26 ldr r6, [r4, #32] TIM_TI1_ConfigInputStage(htim->Instance, 80036a4: 6848 ldr r0, [r1, #4] 80036a6: 68cf ldr r7, [r1, #12] TIMx->CCER &= ~TIM_CCER_CC1E; 80036a8: f026 0601 bic.w r6, r6, #1 80036ac: 6226 str r6, [r4, #32] tmpccmr1 = TIMx->CCMR1; 80036ae: 69a3 ldr r3, [r4, #24] tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 80036b0: f025 010a bic.w r1, r5, #10 tmpccmr1 &= ~TIM_CCMR1_IC1F; 80036b4: f023 03f0 bic.w r3, r3, #240 ; 0xf0 tmpccer |= TIM_ICPolarity; 80036b8: 4301 orrs r1, r0 tmpccmr1 |= (TIM_ICFilter << 4U); 80036ba: ea43 1307 orr.w r3, r3, r7, lsl #4 TIMx->CCMR1 = tmpccmr1; 80036be: 61a3 str r3, [r4, #24] TIMx->CCER = tmpccer; 80036c0: 6221 str r1, [r4, #32] tmpsmcr = TIMx->SMCR; 80036c2: 68a3 ldr r3, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 80036c4: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 80036c8: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80036cc: f043 0357 orr.w r3, r3, #87 ; 0x57 TIMx->SMCR = tmpsmcr; 80036d0: 60a3 str r3, [r4, #8] HAL_StatusTypeDef status = HAL_OK; 80036d2: 2000 movs r0, #0 } 80036d4: e78c b.n 80035f0 /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80036d6: e9d1 5301 ldrd r5, r3, [r1, #4] 80036da: 68c8 ldr r0, [r1, #12] tmpsmcr = TIMx->SMCR; 80036dc: 68a1 ldr r1, [r4, #8] tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80036de: 432b orrs r3, r5 80036e0: ea43 2300 orr.w r3, r3, r0, lsl #8 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80036e4: f421 417f bic.w r1, r1, #65280 ; 0xff00 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80036e8: 430b orrs r3, r1 /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80036ea: 60a3 str r3, [r4, #8] htim->Instance->SMCR |= TIM_SMCR_ECE; 80036ec: 68a3 ldr r3, [r4, #8] 80036ee: f443 4380 orr.w r3, r3, #16384 ; 0x4000 80036f2: 60a3 str r3, [r4, #8] HAL_StatusTypeDef status = HAL_OK; 80036f4: 2000 movs r0, #0 break; 80036f6: e77b b.n 80035f0 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80036f8: e9d1 5301 ldrd r5, r3, [r1, #4] 80036fc: 68c8 ldr r0, [r1, #12] tmpsmcr = TIMx->SMCR; 80036fe: 68a1 ldr r1, [r4, #8] tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8003700: 432b orrs r3, r5 8003702: ea43 2300 orr.w r3, r3, r0, lsl #8 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8003706: f421 417f bic.w r1, r1, #65280 ; 0xff00 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800370a: 430b orrs r3, r1 TIMx->SMCR = tmpsmcr; 800370c: 60a3 str r3, [r4, #8] tmpsmcr = htim->Instance->SMCR; 800370e: 68a3 ldr r3, [r4, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8003710: f043 0377 orr.w r3, r3, #119 ; 0x77 htim->Instance->SMCR = tmpsmcr; 8003714: 60a3 str r3, [r4, #8] HAL_StatusTypeDef status = HAL_OK; 8003716: 2000 movs r0, #0 break; 8003718: e76a b.n 80035f0 800371a: bf00 nop 800371c: ffce0088 .word 0xffce0088 8003720: 00100030 .word 0x00100030 8003724: 00100040 .word 0x00100040 08003728 : assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8003728: f890 303c ldrb.w r3, [r0, #60] ; 0x3c 800372c: 2b01 cmp r3, #1 800372e: d03c beq.n 80037aa { 8003730: b470 push {r4, r5, r6} /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8003732: 6802 ldr r2, [r0, #0] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8003734: 4c1e ldr r4, [pc, #120] ; (80037b0 ) htim->State = HAL_TIM_STATE_BUSY; 8003736: 2302 movs r3, #2 8003738: f880 303d strb.w r3, [r0, #61] ; 0x3d if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800373c: 42a2 cmp r2, r4 tmpcr2 = htim->Instance->CR2; 800373e: 6853 ldr r3, [r2, #4] tmpsmcr = htim->Instance->SMCR; 8003740: 6895 ldr r5, [r2, #8] if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8003742: d026 beq.n 8003792 8003744: f504 6400 add.w r4, r4, #2048 ; 0x800 8003748: 42a2 cmp r2, r4 800374a: d022 beq.n 8003792 } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800374c: 680c ldr r4, [r1, #0] tmpcr2 &= ~TIM_CR2_MMS; 800374e: f023 7300 bic.w r3, r3, #33554432 ; 0x2000000 8003752: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8003756: 4323 orrs r3, r4 /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8003758: f1b2 4f80 cmp.w r2, #1073741824 ; 0x40000000 htim->Instance->CR2 = tmpcr2; 800375c: 6053 str r3, [r2, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800375e: d00a beq.n 8003776 8003760: 4b14 ldr r3, [pc, #80] ; (80037b4 ) 8003762: 429a cmp r2, r3 8003764: d007 beq.n 8003776 8003766: f503 6380 add.w r3, r3, #1024 ; 0x400 800376a: 429a cmp r2, r3 800376c: d003 beq.n 8003776 800376e: f503 339c add.w r3, r3, #79872 ; 0x13800 8003772: 429a cmp r2, r3 8003774: d104 bne.n 8003780 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8003776: 688b ldr r3, [r1, #8] tmpsmcr &= ~TIM_SMCR_MSM; 8003778: f025 0580 bic.w r5, r5, #128 ; 0x80 tmpsmcr |= sMasterConfig->MasterSlaveMode; 800377c: 431d orrs r5, r3 /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800377e: 6095 str r5, [r2, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); 8003780: 2300 movs r3, #0 htim->State = HAL_TIM_STATE_READY; 8003782: 2201 movs r2, #1 8003784: f880 203d strb.w r2, [r0, #61] ; 0x3d __HAL_UNLOCK(htim); 8003788: f880 303c strb.w r3, [r0, #60] ; 0x3c return HAL_OK; } 800378c: bc70 pop {r4, r5, r6} return HAL_OK; 800378e: 4618 mov r0, r3 } 8003790: 4770 bx lr tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8003792: e9d1 4600 ldrd r4, r6, [r1] tmpcr2 &= ~TIM_CR2_MMS2; 8003796: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800379a: 4333 orrs r3, r6 tmpcr2 &= ~TIM_CR2_MMS; 800379c: f023 7300 bic.w r3, r3, #33554432 ; 0x2000000 80037a0: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80037a4: 4323 orrs r3, r4 htim->Instance->CR2 = tmpcr2; 80037a6: 6053 str r3, [r2, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80037a8: e7e5 b.n 8003776 __HAL_LOCK(htim); 80037aa: 2002 movs r0, #2 } 80037ac: 4770 bx lr 80037ae: bf00 nop 80037b0: 40012c00 .word 0x40012c00 80037b4: 40000400 .word 0x40000400 080037b8 <__libc_init_array>: 80037b8: b570 push {r4, r5, r6, lr} 80037ba: 4d0d ldr r5, [pc, #52] ; (80037f0 <__libc_init_array+0x38>) 80037bc: 4c0d ldr r4, [pc, #52] ; (80037f4 <__libc_init_array+0x3c>) 80037be: 1b64 subs r4, r4, r5 80037c0: 10a4 asrs r4, r4, #2 80037c2: 2600 movs r6, #0 80037c4: 42a6 cmp r6, r4 80037c6: d109 bne.n 80037dc <__libc_init_array+0x24> 80037c8: 4d0b ldr r5, [pc, #44] ; (80037f8 <__libc_init_array+0x40>) 80037ca: 4c0c ldr r4, [pc, #48] ; (80037fc <__libc_init_array+0x44>) 80037cc: f000 f820 bl 8003810 <_init> 80037d0: 1b64 subs r4, r4, r5 80037d2: 10a4 asrs r4, r4, #2 80037d4: 2600 movs r6, #0 80037d6: 42a6 cmp r6, r4 80037d8: d105 bne.n 80037e6 <__libc_init_array+0x2e> 80037da: bd70 pop {r4, r5, r6, pc} 80037dc: f855 3b04 ldr.w r3, [r5], #4 80037e0: 4798 blx r3 80037e2: 3601 adds r6, #1 80037e4: e7ee b.n 80037c4 <__libc_init_array+0xc> 80037e6: f855 3b04 ldr.w r3, [r5], #4 80037ea: 4798 blx r3 80037ec: 3601 adds r6, #1 80037ee: e7f2 b.n 80037d6 <__libc_init_array+0x1e> 80037f0: 08004038 .word 0x08004038 80037f4: 08004038 .word 0x08004038 80037f8: 08004038 .word 0x08004038 80037fc: 0800403c .word 0x0800403c 08003800 : 8003800: 4402 add r2, r0 8003802: 4603 mov r3, r0 8003804: 4293 cmp r3, r2 8003806: d100 bne.n 800380a 8003808: 4770 bx lr 800380a: f803 1b01 strb.w r1, [r3], #1 800380e: e7f9 b.n 8003804 08003810 <_init>: 8003810: b5f8 push {r3, r4, r5, r6, r7, lr} 8003812: bf00 nop 8003814: bcf8 pop {r3, r4, r5, r6, r7} 8003816: bc08 pop {r3} 8003818: 469e mov lr, r3 800381a: 4770 bx lr 0800381c <_fini>: 800381c: b5f8 push {r3, r4, r5, r6, r7, lr} 800381e: bf00 nop 8003820: bcf8 pop {r3, r4, r5, r6, r7} 8003822: bc08 pop {r3} 8003824: 469e mov lr, r3 8003826: 4770 bx lr ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/2op_main.d ================================================ App/Src/2op_main.o: ../App/Src/2op_main.c ../App/Inc/2op_main.h \ ../Core/Inc/main.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/dac.h ../Core/Inc/main.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/main.h: ../App/Inc/dynamic_smooth.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/2op_main.su ================================================ 2op_main.c:47:6:adsr_structinit 4 static 2op_main.c:61:6:run_adsr 8 static 2op_main.c:105:6:run_ar 8 static 2op_main.c:142:6:run_linear_a_expo_r 8 static 2op_main.c:181:10:operator_run 0 static 2op_main.c:187:6:operator_structinit 0 static 2op_main.c:194:6:check_trig 8 static 2op_main.c:223:6:set_adsr_parameters 8 static 2op_main.c:243:6:main_2OP_loop 24 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/dynamic_smooth.d ================================================ App/Src/dynamic_smooth.o: ../App/Src/dynamic_smooth.c \ ../App/Inc/dynamic_smooth.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/dac.h ../Core/Inc/main.h \ ../App/Inc/2op_main.h ../App/Inc/dynamic_smooth.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/main.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/dynamic_smooth.su ================================================ dynamic_smooth.c:11:7:cm_min 0 static dynamic_smooth.c:15:7:cm_abs 0 static dynamic_smooth.c:23:6:dynamic_smooth_init 0 static dynamic_smooth.c:44:7:dynamic_smooth_tick 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/float_expo_table.su ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/loop.d ================================================ App/Src/loop.o: ../App/Src/loop.c ../App/Inc/loop.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/global_variables.h ../App/Inc/big_sine_wave.h \ ../Core/Inc/dac.h ../Core/Inc/main.h ../App/Inc/dynamic_smooth.h \ ../App/Inc/2op_main.h ../App/Inc/loop.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/main.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/loop.su ================================================ loop.c:11:6:loop 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/App/Src/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../App/Src/2op_main.c \ ../App/Src/dynamic_smooth.c \ ../App/Src/loop.c OBJS += \ ./App/Src/2op_main.o \ ./App/Src/dynamic_smooth.o \ ./App/Src/loop.o C_DEPS += \ ./App/Src/2op_main.d \ ./App/Src/dynamic_smooth.d \ ./App/Src/loop.d # Each subdirectory must supply rules for building sources it contributes App/Src/%.o: ../App/Src/%.c App/Src/subdir.mk arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../App/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -Ofast -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-App-2f-Src clean-App-2f-Src: -$(RM) ./App/Src/2op_main.d ./App/Src/2op_main.o ./App/Src/dynamic_smooth.d ./App/Src/dynamic_smooth.o ./App/Src/loop.d ./App/Src/loop.o .PHONY: clean-App-2f-Src ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/adc.d ================================================ Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/adc.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/main.h ../Core/Inc/dac.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h ../Core/Inc/adc.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/main.h: ../Core/Inc/dac.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/adc.su ================================================ adc.c:33:6:MX_ADC1_Init 64 static adc.c:135:6:MX_ADC2_Init 48 static adc.c:197:6:HAL_ADC_MspInit 128 static adc.c:318:6:HAL_ADC_MspDeInit 8 static adc.c:375:6:ADC_Start 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/dac.d ================================================ Core/Src/dac.o: ../Core/Src/dac.c ../Core/Inc/dac.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/main.h ../Core/Inc/dac.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h ../Core/Inc/dac.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/main.h: ../Core/Inc/dac.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/dac.su ================================================ dac.c:30:6:MX_DAC1_Init 64 static dac.c:76:6:HAL_DAC_MspInit 40 static dac.c:104:6:HAL_DAC_MspDeInit 0 static dac.c:128:6:DAC_Start 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/dma.d ================================================ Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/main.h ../Core/Inc/dac.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h ../Core/Inc/dma.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/main.h: ../Core/Inc/dac.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/dma.su ================================================ dma.c:39:6:MX_DMA_Init 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/gpio.d ================================================ Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/main.h ../Core/Inc/dac.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h ../Core/Inc/gpio.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/main.h: ../Core/Inc/dac.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/gpio.su ================================================ gpio.c:37:6:MX_GPIO_Init 48 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/main.d ================================================ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/dac.h ../Core/Inc/main.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h ../Core/Inc/adc.h \ ../Core/Inc/dac.h ../Core/Inc/dma.h ../Core/Inc/tim.h ../Core/Inc/gpio.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/main.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ../Core/Inc/adc.h: ../Core/Inc/dac.h: ../Core/Inc/dma.h: ../Core/Inc/tim.h: ../Core/Inc/gpio.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/main.su ================================================ main.c:138:6:SystemClock_Config 96 static,ignoring_inline_asm main.c:68:5:main 24 static main.c:186:6:Error_Handler 0 static,ignoring_inline_asm ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/stm32g4xx_hal_msp.d ================================================ Core/Src/stm32g4xx_hal_msp.o: ../Core/Src/stm32g4xx_hal_msp.c \ ../Core/Inc/main.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/dac.h ../Core/Inc/main.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/main.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/stm32g4xx_hal_msp.su ================================================ stm32g4xx_hal_msp.c:63:6:HAL_MspInit 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/stm32g4xx_it.d ================================================ Core/Src/stm32g4xx_it.o: ../Core/Src/stm32g4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/dac.h ../Core/Inc/main.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h \ ../Core/Inc/stm32g4xx_it.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/main.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ../Core/Inc/stm32g4xx_it.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/stm32g4xx_it.su ================================================ stm32g4xx_it.c:71:6:NMI_Handler 0 static stm32g4xx_it.c:85:6:HardFault_Handler 0 static stm32g4xx_it.c:100:6:MemManage_Handler 0 static stm32g4xx_it.c:115:6:BusFault_Handler 0 static stm32g4xx_it.c:130:6:UsageFault_Handler 0 static stm32g4xx_it.c:145:6:SVC_Handler 0 static stm32g4xx_it.c:158:6:DebugMon_Handler 0 static stm32g4xx_it.c:171:6:PendSV_Handler 0 static stm32g4xx_it.c:184:6:SysTick_Handler 0 static stm32g4xx_it.c:205:6:TIM2_IRQHandler 0 static stm32g4xx_it.c:225:6:TIM3_IRQHandler 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../Core/Src/adc.c \ ../Core/Src/dac.c \ ../Core/Src/dma.c \ ../Core/Src/gpio.c \ ../Core/Src/main.c \ ../Core/Src/stm32g4xx_hal_msp.c \ ../Core/Src/stm32g4xx_it.c \ ../Core/Src/syscalls.c \ ../Core/Src/sysmem.c \ ../Core/Src/system_stm32g4xx.c \ ../Core/Src/tim.c OBJS += \ ./Core/Src/adc.o \ ./Core/Src/dac.o \ ./Core/Src/dma.o \ ./Core/Src/gpio.o \ ./Core/Src/main.o \ ./Core/Src/stm32g4xx_hal_msp.o \ ./Core/Src/stm32g4xx_it.o \ ./Core/Src/syscalls.o \ ./Core/Src/sysmem.o \ ./Core/Src/system_stm32g4xx.o \ ./Core/Src/tim.o C_DEPS += \ ./Core/Src/adc.d \ ./Core/Src/dac.d \ ./Core/Src/dma.d \ ./Core/Src/gpio.d \ ./Core/Src/main.d \ ./Core/Src/stm32g4xx_hal_msp.d \ ./Core/Src/stm32g4xx_it.d \ ./Core/Src/syscalls.d \ ./Core/Src/sysmem.d \ ./Core/Src/system_stm32g4xx.d \ ./Core/Src/tim.d # Each subdirectory must supply rules for building sources it contributes Core/Src/%.o: ../Core/Src/%.c Core/Src/subdir.mk arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../App/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -Ofast -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Core-2f-Src clean-Core-2f-Src: -$(RM) ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/dac.d ./Core/Src/dac.o ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/stm32g4xx_hal_msp.d ./Core/Src/stm32g4xx_hal_msp.o ./Core/Src/stm32g4xx_it.d ./Core/Src/stm32g4xx_it.o ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/system_stm32g4xx.d ./Core/Src/system_stm32g4xx.o ./Core/Src/tim.d ./Core/Src/tim.o .PHONY: clean-Core-2f-Src ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/syscalls.d ================================================ Core/Src/syscalls.o: ../Core/Src/syscalls.c ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/syscalls.su ================================================ syscalls.c:44:6:initialise_monitor_handles 0 static syscalls.c:48:5:_getpid 0 static syscalls.c:53:5:_kill 8 static syscalls.c:59:6:_exit 8 static syscalls.c:65:27:_read 16 static syscalls.c:77:27:_write 16 static syscalls.c:88:5:_close 0 static syscalls.c:94:5:_fstat 0 static syscalls.c:100:5:_isatty 0 static syscalls.c:105:5:_lseek 0 static syscalls.c:110:5:_open 0 static syscalls.c:116:5:_wait 8 static syscalls.c:122:5:_unlink 8 static syscalls.c:128:5:_times 0 static syscalls.c:133:5:_stat 0 static syscalls.c:139:5:_link 8 static syscalls.c:145:5:_fork 8 static syscalls.c:151:5:_execve 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/sysmem.d ================================================ Core/Src/sysmem.o: ../Core/Src/sysmem.c ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/sysmem.su ================================================ sysmem.c:53:7:_sbrk 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/system_stm32g4xx.d ================================================ Core/Src/system_stm32g4xx.o: ../Core/Src/system_stm32g4xx.c \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/system_stm32g4xx.su ================================================ system_stm32g4xx.c:179:6:SystemInit 0 static system_stm32g4xx.c:228:6:SystemCoreClockUpdate 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/tim.d ================================================ Core/Src/tim.o: ../Core/Src/tim.c ../Core/Inc/tim.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../App/Inc/loop.h ../App/Inc/global_variables.h \ ../App/Inc/big_sine_wave.h ../Core/Inc/main.h ../Core/Inc/dac.h \ ../App/Inc/dynamic_smooth.h ../App/Inc/2op_main.h ../Core/Inc/tim.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../App/Inc/loop.h: ../App/Inc/global_variables.h: ../App/Inc/big_sine_wave.h: ../Core/Inc/main.h: ../Core/Inc/dac.h: ../App/Inc/dynamic_smooth.h: ../App/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Src/tim.su ================================================ tim.c:31:6:MX_TIM2_Init 40 static tim.c:71:6:MX_TIM3_Init 40 static tim.c:111:6:HAL_TIM_Base_MspInit 16 static tim.c:146:6:HAL_TIM_Base_MspDeInit 0 static tim.c:180:6:TIM_Start 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Startup/startup_stm32g431kbux.d ================================================ Core/Startup/startup_stm32g431kbux.o: \ ../Core/Startup/startup_stm32g431kbux.s ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Core/Startup/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables S_SRCS += \ ../Core/Startup/startup_stm32g431kbux.s OBJS += \ ./Core/Startup/startup_stm32g431kbux.o S_DEPS += \ ./Core/Startup/startup_stm32g431kbux.d # Each subdirectory must supply rules for building sources it contributes Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" clean: clean-Core-2f-Startup clean-Core-2f-Startup: -$(RM) ./Core/Startup/startup_stm32g431kbux.d ./Core/Startup/startup_stm32g431kbux.o .PHONY: clean-Core-2f-Startup ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.su ================================================ stm32g4xx_hal.c:221:13:HAL_MspInit 0 static stm32g4xx_hal.c:232:13:HAL_MspDeInit 0 static stm32g4xx_hal.c:192:19:HAL_DeInit 8 static stm32g4xx_hal.c:255:26:HAL_InitTick 16 static stm32g4xx_hal.c:148:19:HAL_Init 8 static stm32g4xx_hal.c:322:13:HAL_IncTick 0 static stm32g4xx_hal.c:333:17:HAL_GetTick 0 static stm32g4xx_hal.c:342:10:HAL_GetTickPrio 0 static stm32g4xx_hal.c:351:19:HAL_SetTickFreq 16 static stm32g4xx_hal.c:384:10:HAL_GetTickFreq 0 static stm32g4xx_hal.c:400:13:HAL_Delay 16 static stm32g4xx_hal.c:426:13:HAL_SuspendTick 0 static stm32g4xx_hal.c:442:13:HAL_ResumeTick 0 static stm32g4xx_hal.c:452:10:HAL_GetHalVersion 0 static stm32g4xx_hal.c:461:10:HAL_GetREVID 0 static stm32g4xx_hal.c:470:10:HAL_GetDEVID 0 static stm32g4xx_hal.c:479:10:HAL_GetUIDw0 0 static stm32g4xx_hal.c:488:10:HAL_GetUIDw1 0 static stm32g4xx_hal.c:497:10:HAL_GetUIDw2 0 static stm32g4xx_hal.c:526:6:HAL_DBGMCU_EnableDBGSleepMode 0 static stm32g4xx_hal.c:535:6:HAL_DBGMCU_DisableDBGSleepMode 0 static stm32g4xx_hal.c:544:6:HAL_DBGMCU_EnableDBGStopMode 0 static stm32g4xx_hal.c:553:6:HAL_DBGMCU_DisableDBGStopMode 0 static stm32g4xx_hal.c:562:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static stm32g4xx_hal.c:571:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static stm32g4xx_hal.c:604:6:HAL_SYSCFG_CCMSRAMErase 0 static stm32g4xx_hal.c:623:6:HAL_SYSCFG_EnableMemorySwappingBank 0 static stm32g4xx_hal.c:638:6:HAL_SYSCFG_DisableMemorySwappingBank 0 static stm32g4xx_hal.c:656:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 0 static stm32g4xx_hal.c:672:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 0 static stm32g4xx_hal.c:686:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 0 static stm32g4xx_hal.c:698:19:HAL_SYSCFG_EnableVREFBUF 16 static stm32g4xx_hal.c:724:6:HAL_SYSCFG_DisableVREFBUF 0 static stm32g4xx_hal.c:735:6:HAL_SYSCFG_EnableIOSwitchBooster 0 static stm32g4xx_hal.c:745:6:HAL_SYSCFG_DisableIOSwitchBooster 0 static stm32g4xx_hal.c:755:6:HAL_SYSCFG_EnableIOSwitchVDD 0 static stm32g4xx_hal.c:765:6:HAL_SYSCFG_DisableIOSwitchVDD 0 static stm32g4xx_hal.c:776:6:HAL_SYSCFG_CCMSRAM_WriteProtectionEnable 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.su ================================================ stm32g4xx_hal_adc.c:912:13:HAL_ADC_MspInit 0 static stm32g4xx_hal_adc.c:396:19:HAL_ADC_Init 24 static stm32g4xx_hal_adc.c:929:13:HAL_ADC_MspDeInit 0 static stm32g4xx_hal_adc.c:1408:19:HAL_ADC_PollForConversion 24 static stm32g4xx_hal_adc.c:1594:19:HAL_ADC_PollForEvent 24 static stm32g4xx_hal_adc.c:2230:10:HAL_ADC_GetValue 0 static stm32g4xx_hal_adc.c:2251:19:HAL_ADC_StartSampling 0 static stm32g4xx_hal_adc.c:2273:19:HAL_ADC_StopSampling 0 static stm32g4xx_hal_adc.c:2662:13:HAL_ADC_ConvCpltCallback 0 static stm32g4xx_hal_adc.c:2677:13:HAL_ADC_ConvHalfCpltCallback 0 static stm32g4xx_hal_adc.c:3668:6:ADC_DMAHalfConvCplt 8 static stm32g4xx_hal_adc.c:2692:13:HAL_ADC_LevelOutOfWindowCallback 0 static stm32g4xx_hal_adc.c:2714:13:HAL_ADC_ErrorCallback 0 static stm32g4xx_hal_adc.c:2290:6:HAL_ADC_IRQHandler 24 static stm32g4xx_hal_adc.c:3590:6:ADC_DMAConvCplt 8 static stm32g4xx_hal_adc.c:3686:6:ADC_DMAError 8 static stm32g4xx_hal_adc.c:2760:19:HAL_ADC_ConfigChannel 32 static,ignoring_inline_asm stm32g4xx_hal_adc.c:2998:19:HAL_ADC_AnalogWDGConfig 16 static,ignoring_inline_asm stm32g4xx_hal_adc.c:3259:10:HAL_ADC_GetState 0 static stm32g4xx_hal_adc.c:3273:10:HAL_ADC_GetError 0 static stm32g4xx_hal_adc.c:3303:19:ADC_ConversionStop 16 static stm32g4xx_hal_adc.c:3435:19:ADC_Enable 24 static stm32g4xx_hal_adc.c:1219:19:HAL_ADC_Start 16 static stm32g4xx_hal_adc.c:1743:19:HAL_ADC_Start_IT 16 static stm32g4xx_hal_adc.c:2003:19:HAL_ADC_Start_DMA 24 static stm32g4xx_hal_adc.c:3528:19:ADC_Disable 16 static stm32g4xx_hal_adc.c:713:19:HAL_ADC_DeInit 24 static stm32g4xx_hal_adc.c:1354:19:HAL_ADC_Stop 8 static stm32g4xx_hal_adc.c:1950:19:HAL_ADC_Stop_IT 8 static stm32g4xx_hal_adc.c:2145:19:HAL_ADC_Stop_DMA 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.su ================================================ stm32g4xx_hal_adc_ex.c:126:19:HAL_ADCEx_Calibration_Start 24 static stm32g4xx_hal_adc_ex.c:200:10:HAL_ADCEx_Calibration_GetValue 0 static stm32g4xx_hal_adc_ex.c:220:19:HAL_ADCEx_Calibration_SetValue 12 static stm32g4xx_hal_adc_ex.c:277:19:HAL_ADCEx_InjectedStart 16 static stm32g4xx_hal_adc_ex.c:426:19:HAL_ADCEx_InjectedStop 8 static stm32g4xx_hal_adc_ex.c:481:19:HAL_ADCEx_InjectedPollForConversion 24 static stm32g4xx_hal_adc_ex.c:622:19:HAL_ADCEx_InjectedStart_IT 16 static stm32g4xx_hal_adc_ex.c:795:19:HAL_ADCEx_InjectedStop_IT 8 static stm32g4xx_hal_adc_ex.c:862:19:HAL_ADCEx_MultiModeStart_DMA 136 static stm32g4xx_hal_adc_ex.c:981:19:HAL_ADCEx_MultiModeStop_DMA 128 static stm32g4xx_hal_adc_ex.c:1104:10:HAL_ADCEx_MultiModeGetValue 0 static stm32g4xx_hal_adc_ex.c:1151:10:HAL_ADCEx_InjectedGetValue 0 static stm32g4xx_hal_adc_ex.c:1186:13:HAL_ADCEx_InjectedConvCpltCallback 0 static stm32g4xx_hal_adc_ex.c:1205:13:HAL_ADCEx_InjectedQueueOverflowCallback 0 static stm32g4xx_hal_adc_ex.c:1220:13:HAL_ADCEx_LevelOutOfWindow2Callback 0 static stm32g4xx_hal_adc_ex.c:1235:13:HAL_ADCEx_LevelOutOfWindow3Callback 0 static stm32g4xx_hal_adc_ex.c:1251:13:HAL_ADCEx_EndOfSamplingCallback 0 static stm32g4xx_hal_adc_ex.c:1268:19:HAL_ADCEx_RegularStop 8 static stm32g4xx_hal_adc_ex.c:1326:19:HAL_ADCEx_RegularStop_IT 8 static stm32g4xx_hal_adc_ex.c:1386:19:HAL_ADCEx_RegularStop_DMA 16 static stm32g4xx_hal_adc_ex.c:1474:19:HAL_ADCEx_RegularMultiModeStop_DMA 128 static stm32g4xx_hal_adc_ex.c:1659:19:HAL_ADCEx_InjectedConfigChannel 32 static,ignoring_inline_asm stm32g4xx_hal_adc_ex.c:2116:19:HAL_ADCEx_MultiModeConfigChannel 128 static stm32g4xx_hal_adc_ex.c:2233:19:HAL_ADCEx_EnableInjectedQueue 0 static stm32g4xx_hal_adc_ex.c:2274:19:HAL_ADCEx_DisableInjectedQueue 0 static stm32g4xx_hal_adc_ex.c:2311:19:HAL_ADCEx_DisableVoltageRegulator 0 static stm32g4xx_hal_adc_ex.c:2348:19:HAL_ADCEx_EnterADCDeepPowerDownMode 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.su ================================================ stm32g4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriorityGrouping 4 static stm32g4xx_hal_cortex.c:185:6:HAL_NVIC_SetPriority 8 static stm32g4xx_hal_cortex.c:207:6:HAL_NVIC_EnableIRQ 0 static,ignoring_inline_asm stm32g4xx_hal_cortex.c:223:6:HAL_NVIC_DisableIRQ 0 static,ignoring_inline_asm stm32g4xx_hal_cortex.c:236:6:HAL_NVIC_SystemReset 0 static,ignoring_inline_asm stm32g4xx_hal_cortex.c:249:10:HAL_SYSTICK_Config 4 static stm32g4xx_hal_cortex.c:277:10:HAL_NVIC_GetPriorityGrouping 0 static stm32g4xx_hal_cortex.c:304:6:HAL_NVIC_GetPriority 8 static stm32g4xx_hal_cortex.c:319:6:HAL_NVIC_SetPendingIRQ 0 static stm32g4xx_hal_cortex.c:337:10:HAL_NVIC_GetPendingIRQ 0 static stm32g4xx_hal_cortex.c:353:6:HAL_NVIC_ClearPendingIRQ 0 static stm32g4xx_hal_cortex.c:370:10:HAL_NVIC_GetActive 0 static stm32g4xx_hal_cortex.c:384:6:HAL_SYSTICK_CLKSourceConfig 0 static stm32g4xx_hal_cortex.c:411:13:HAL_SYSTICK_Callback 0 static stm32g4xx_hal_cortex.c:402:6:HAL_SYSTICK_IRQHandler 8 static stm32g4xx_hal_cortex.c:430:6:HAL_MPU_Enable 0 static,ignoring_inline_asm stm32g4xx_hal_cortex.c:445:6:HAL_MPU_Disable 0 static,ignoring_inline_asm stm32g4xx_hal_cortex.c:461:6:HAL_MPU_ConfigRegion 12 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.su ================================================ stm32g4xx_hal_dac.c:511:13:HAL_DAC_MspInit 0 static stm32g4xx_hal_dac.c:405:19:HAL_DAC_Init 8 static stm32g4xx_hal_dac.c:527:13:HAL_DAC_MspDeInit 0 static stm32g4xx_hal_dac.c:466:19:HAL_DAC_DeInit 8 static stm32g4xx_hal_dac.c:572:19:HAL_DAC_Start 24 static stm32g4xx_hal_dac.c:647:19:HAL_DAC_Stop 4 static stm32g4xx_hal_dac.c:688:19:HAL_DAC_Start_DMA 32 static stm32g4xx_hal_dac.c:834:19:HAL_DAC_Stop_DMA 24 static stm32g4xx_hal_dac.c:967:19:HAL_DAC_SetValue 16 static stm32g4xx_hal_dac.c:1011:13:HAL_DAC_ConvCpltCallbackCh1 0 static stm32g4xx_hal_dac.c:1675:6:DAC_DMAConvCpltCh1 8 static stm32g4xx_hal_dac.c:1027:13:HAL_DAC_ConvHalfCpltCallbackCh1 0 static stm32g4xx_hal_dac.c:1694:6:DAC_DMAHalfConvCpltCh1 8 static stm32g4xx_hal_dac.c:1043:13:HAL_DAC_ErrorCallbackCh1 0 static stm32g4xx_hal_dac.c:1711:6:DAC_DMAErrorCh1 8 static stm32g4xx_hal_dac.c:1059:13:HAL_DAC_DMAUnderrunCallbackCh1 0 static stm32g4xx_hal_dac.c:888:6:HAL_DAC_IRQHandler 16 static stm32g4xx_hal_dac.c:1101:10:HAL_DAC_GetValue 0 static stm32g4xx_hal_dac.c:1144:19:HAL_DAC_ConfigChannel 24 static stm32g4xx_hal_dac.c:1390:22:HAL_DAC_GetState 0 static stm32g4xx_hal_dac.c:1403:10:HAL_DAC_GetError 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.su ================================================ stm32g4xx_hal_dac_ex.c:131:19:HAL_DACEx_DualStart 16 static stm32g4xx_hal_dac_ex.c:193:19:HAL_DACEx_DualStop 4 static stm32g4xx_hal_dac_ex.c:232:19:HAL_DACEx_DualStart_DMA 32 static stm32g4xx_hal_dac_ex.c:360:19:HAL_DACEx_DualStop_DMA 8 static stm32g4xx_hal_dac_ex.c:444:19:HAL_DACEx_TriangleWaveGenerate 8 static stm32g4xx_hal_dac_ex.c:503:19:HAL_DACEx_NoiseWaveGenerate 8 static stm32g4xx_hal_dac_ex.c:559:19:HAL_DACEx_SawtoothWaveGenerate 8 static stm32g4xx_hal_dac_ex.c:629:19:HAL_DACEx_SawtoothWaveDataReset 8 static stm32g4xx_hal_dac_ex.c:691:19:HAL_DACEx_SawtoothWaveDataStep 8 static stm32g4xx_hal_dac_ex.c:754:19:HAL_DACEx_DualSetValue 0 static stm32g4xx_hal_dac_ex.c:796:13:HAL_DACEx_ConvCpltCallbackCh2 0 static stm32g4xx_hal_dac_ex.c:1114:6:DAC_DMAConvCpltCh2 8 static stm32g4xx_hal_dac_ex.c:812:13:HAL_DACEx_ConvHalfCpltCallbackCh2 0 static stm32g4xx_hal_dac_ex.c:1133:6:DAC_DMAHalfConvCpltCh2 8 static stm32g4xx_hal_dac_ex.c:828:13:HAL_DACEx_ErrorCallbackCh2 0 static stm32g4xx_hal_dac_ex.c:1150:6:DAC_DMAErrorCh2 8 static stm32g4xx_hal_dac_ex.c:844:13:HAL_DACEx_DMAUnderrunCallbackCh2 0 static stm32g4xx_hal_dac_ex.c:871:19:HAL_DACEx_SelfCalibrate 48 static stm32g4xx_hal_dac_ex.c:1002:19:HAL_DACEx_SetUserTrimming 16 static stm32g4xx_hal_dac_ex.c:1047:10:HAL_DACEx_GetTrimOffset 0 static stm32g4xx_hal_dac_ex.c:1081:10:HAL_DACEx_DualGetValue 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.su ================================================ stm32g4xx_hal_dma.c:152:19:HAL_DMA_Init 24 static stm32g4xx_hal_dma.c:263:19:HAL_DMA_DeInit 16 static stm32g4xx_hal_dma.c:378:19:HAL_DMA_Start 16 static stm32g4xx_hal_dma.c:421:19:HAL_DMA_Start_IT 16 static stm32g4xx_hal_dma.c:491:19:HAL_DMA_Abort 12 static stm32g4xx_hal_dma.c:544:19:HAL_DMA_Abort_IT 16 static stm32g4xx_hal_dma.c:611:19:HAL_DMA_PollForTransfer 32 static stm32g4xx_hal_dma.c:741:6:HAL_DMA_IRQHandler 12 static stm32g4xx_hal_dma.c:835:19:HAL_DMA_RegisterCallback 4 static stm32g4xx_hal_dma.c:886:19:HAL_DMA_UnRegisterCallback 4 static stm32g4xx_hal_dma.c:964:22:HAL_DMA_GetState 0 static stm32g4xx_hal_dma.c:976:10:HAL_DMA_GetError 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.su ================================================ stm32g4xx_hal_dma_ex.c:95:19:HAL_DMAEx_ConfigMuxSync 12 static stm32g4xx_hal_dma_ex.c:141:19:HAL_DMAEx_ConfigMuxRequestGenerator 8 static,ignoring_inline_asm stm32g4xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator 0 static stm32g4xx_hal_dma_ex.c:209:19:HAL_DMAEx_DisableMuxRequestGenerator 0 static stm32g4xx_hal_dma_ex.c:237:6:HAL_DMAEx_MUX_IRQHandler 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.su ================================================ stm32g4xx_hal_exti.c:144:19:HAL_EXTI_SetConfigLine 16 static stm32g4xx_hal_exti.c:268:19:HAL_EXTI_GetConfigLine 12 static stm32g4xx_hal_exti.c:364:19:HAL_EXTI_ClearConfigLine 16 static stm32g4xx_hal_exti.c:432:19:HAL_EXTI_RegisterCallback 0 static stm32g4xx_hal_exti.c:463:19:HAL_EXTI_GetHandle 0 static stm32g4xx_hal_exti.c:504:6:HAL_EXTI_IRQHandler 8 static stm32g4xx_hal_exti.c:539:10:HAL_EXTI_GetPending 0 static stm32g4xx_hal_exti.c:574:6:HAL_EXTI_ClearPending 0 static stm32g4xx_hal_exti.c:603:6:HAL_EXTI_GenerateSWI 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.su ================================================ stm32g4xx_hal_flash.c:173:19:HAL_FLASH_Program 40 static,ignoring_inline_asm stm32g4xx_hal_flash.c:255:19:HAL_FLASH_Program_IT 40 static,ignoring_inline_asm stm32g4xx_hal_flash.c:467:13:HAL_FLASH_EndOfOperationCallback 0 static stm32g4xx_hal_flash.c:485:13:HAL_FLASH_OperationErrorCallback 0 static stm32g4xx_hal_flash.c:327:6:HAL_FLASH_IRQHandler 8 static stm32g4xx_hal_flash.c:518:19:HAL_FLASH_Unlock 0 static stm32g4xx_hal_flash.c:542:19:HAL_FLASH_Lock 0 static stm32g4xx_hal_flash.c:562:19:HAL_FLASH_OB_Unlock 0 static stm32g4xx_hal_flash.c:586:19:HAL_FLASH_OB_Lock 0 static stm32g4xx_hal_flash.c:606:19:HAL_FLASH_OB_Launch 16 static stm32g4xx_hal_flash.c:654:10:HAL_FLASH_GetError 0 static stm32g4xx_hal_flash.c:678:19:FLASH_WaitForLastOperation 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.su ================================================ stm32g4xx_hal_flash_ex.c:138:19:HAL_FLASHEx_Erase 32 static stm32g4xx_hal_flash_ex.c:237:19:HAL_FLASHEx_Erase_IT 4 static stm32g4xx_hal_flash_ex.c:310:19:HAL_FLASHEx_OBProgram 32 static stm32g4xx_hal_flash_ex.c:399:6:HAL_FLASHEx_OBGetConfig 4 static stm32g4xx_hal_flash_ex.c:459:19:HAL_FLASHEx_EnableSecMemProtection 0 static stm32g4xx_hal_flash_ex.c:497:6:HAL_FLASHEx_EnableDebugger 0 static stm32g4xx_hal_flash_ex.c:509:6:HAL_FLASHEx_DisableDebugger 0 static stm32g4xx_hal_flash_ex.c:582:6:FLASH_PageErase 0 static stm32g4xx_hal_flash_ex.c:620:6:FLASH_FlushCaches 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.su ================================================ stm32g4xx_hal_flash_ramfunc.c:92:30:HAL_FLASHEx_EnableRunPowerDown 0 static stm32g4xx_hal_flash_ramfunc.c:106:30:HAL_FLASHEx_DisableRunPowerDown 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.su ================================================ stm32g4xx_hal_gpio.c:162:6:HAL_GPIO_Init 56 static stm32g4xx_hal_gpio.c:292:6:HAL_GPIO_DeInit 48 static stm32g4xx_hal_gpio.c:373:15:HAL_GPIO_ReadPin 0 static stm32g4xx_hal_gpio.c:407:6:HAL_GPIO_WritePin 0 static stm32g4xx_hal_gpio.c:430:6:HAL_GPIO_TogglePin 0 static stm32g4xx_hal_gpio.c:455:19:HAL_GPIO_LockPin 8 static stm32g4xx_hal_gpio.c:505:13:HAL_GPIO_EXTI_Callback 0 static stm32g4xx_hal_gpio.c:490:6:HAL_GPIO_EXTI_IRQHandler 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.su ================================================ stm32g4xx_hal_pwr.c:86:6:HAL_PWR_DeInit 0 static stm32g4xx_hal_pwr.c:104:6:HAL_PWR_EnableBkUpAccess 0 static stm32g4xx_hal_pwr.c:114:6:HAL_PWR_DisableBkUpAccess 0 static stm32g4xx_hal_pwr.c:308:19:HAL_PWR_ConfigPVD 4 static stm32g4xx_hal_pwr.c:354:6:HAL_PWR_EnablePVD 0 static stm32g4xx_hal_pwr.c:363:6:HAL_PWR_DisablePVD 0 static stm32g4xx_hal_pwr.c:388:6:HAL_PWR_EnableWakeUpPin 0 static stm32g4xx_hal_pwr.c:409:6:HAL_PWR_DisableWakeUpPin 0 static stm32g4xx_hal_pwr.c:441:6:HAL_PWR_EnterSLEEPMode 8 static,ignoring_inline_asm stm32g4xx_hal_pwr.c:516:6:HAL_PWR_EnterSTOPMode 0 static stm32g4xx_hal_pwr.c:549:6:HAL_PWR_EnterSTANDBYMode 0 static,ignoring_inline_asm stm32g4xx_hal_pwr.c:575:6:HAL_PWR_EnableSleepOnExit 0 static stm32g4xx_hal_pwr.c:588:6:HAL_PWR_DisableSleepOnExit 0 static stm32g4xx_hal_pwr.c:602:6:HAL_PWR_EnableSEVOnPend 0 static stm32g4xx_hal_pwr.c:615:6:HAL_PWR_DisableSEVOnPend 0 static stm32g4xx_hal_pwr.c:629:13:HAL_PWR_PVDCallback 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.su ================================================ stm32g4xx_hal_pwr_ex.c:109:10:HAL_PWREx_GetVoltageRange 0 static stm32g4xx_hal_pwr_ex.c:153:19:HAL_PWREx_ControlVoltageScaling 4 static stm32g4xx_hal_pwr_ex.c:238:6:HAL_PWREx_EnableBatteryCharging 0 static stm32g4xx_hal_pwr_ex.c:254:6:HAL_PWREx_DisableBatteryCharging 0 static stm32g4xx_hal_pwr_ex.c:264:6:HAL_PWREx_EnableInternalWakeUpLine 0 static stm32g4xx_hal_pwr_ex.c:274:6:HAL_PWREx_DisableInternalWakeUpLine 0 static stm32g4xx_hal_pwr_ex.c:302:19:HAL_PWREx_EnableGPIOPullUp 0 static stm32g4xx_hal_pwr_ex.c:363:19:HAL_PWREx_DisableGPIOPullUp 0 static stm32g4xx_hal_pwr_ex.c:424:19:HAL_PWREx_EnableGPIOPullDown 0 static stm32g4xx_hal_pwr_ex.c:485:19:HAL_PWREx_DisableGPIOPullDown 0 static stm32g4xx_hal_pwr_ex.c:535:6:HAL_PWREx_EnablePullUpPullDownConfig 0 static stm32g4xx_hal_pwr_ex.c:547:6:HAL_PWREx_DisablePullUpPullDownConfig 0 static stm32g4xx_hal_pwr_ex.c:560:6:HAL_PWREx_EnableSRAM2ContentRetention 0 static stm32g4xx_hal_pwr_ex.c:572:6:HAL_PWREx_DisableSRAM2ContentRetention 0 static stm32g4xx_hal_pwr_ex.c:585:6:HAL_PWREx_EnablePVM1 0 static stm32g4xx_hal_pwr_ex.c:594:6:HAL_PWREx_DisablePVM1 0 static stm32g4xx_hal_pwr_ex.c:606:6:HAL_PWREx_EnablePVM2 0 static stm32g4xx_hal_pwr_ex.c:615:6:HAL_PWREx_DisablePVM2 0 static stm32g4xx_hal_pwr_ex.c:626:6:HAL_PWREx_EnablePVM3 0 static stm32g4xx_hal_pwr_ex.c:635:6:HAL_PWREx_DisablePVM3 0 static stm32g4xx_hal_pwr_ex.c:645:6:HAL_PWREx_EnablePVM4 0 static stm32g4xx_hal_pwr_ex.c:654:6:HAL_PWREx_DisablePVM4 0 static stm32g4xx_hal_pwr_ex.c:674:19:HAL_PWREx_ConfigPVM 0 static stm32g4xx_hal_pwr_ex.c:835:6:HAL_PWREx_EnableLowPowerRunMode 0 static stm32g4xx_hal_pwr_ex.c:850:19:HAL_PWREx_DisableLowPowerRunMode 0 static stm32g4xx_hal_pwr_ex.c:894:6:HAL_PWREx_EnterSTOP0Mode 0 static,ignoring_inline_asm stm32g4xx_hal_pwr_ex.c:945:6:HAL_PWREx_EnterSTOP1Mode 0 static,ignoring_inline_asm stm32g4xx_hal_pwr_ex.c:986:6:HAL_PWREx_EnterSHUTDOWNMode 0 static,ignoring_inline_asm stm32g4xx_hal_pwr_ex.c:1067:13:HAL_PWREx_PVM1Callback 0 static stm32g4xx_hal_pwr_ex.c:1080:13:HAL_PWREx_PVM2Callback 0 static stm32g4xx_hal_pwr_ex.c:1092:13:HAL_PWREx_PVM3Callback 0 static stm32g4xx_hal_pwr_ex.c:1103:13:HAL_PWREx_PVM4Callback 0 static stm32g4xx_hal_pwr_ex.c:1011:6:HAL_PWREx_PVD_PVM_IRQHandler 8 static stm32g4xx_hal_pwr_ex.c:1115:6:HAL_PWREx_EnableUCPDStandbyMode 0 static stm32g4xx_hal_pwr_ex.c:1127:6:HAL_PWREx_DisableUCPDStandbyMode 0 static stm32g4xx_hal_pwr_ex.c:1141:6:HAL_PWREx_EnableUCPDDeadBattery 0 static stm32g4xx_hal_pwr_ex.c:1157:6:HAL_PWREx_DisableUCPDDeadBattery 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.su ================================================ stm32g4xx_hal_rcc.c:219:19:HAL_RCC_DeInit 16 static stm32g4xx_hal_rcc.c:312:19:HAL_RCC_OscConfig 32 static stm32g4xx_hal_rcc.c:994:6:HAL_RCC_MCOConfig 48 static stm32g4xx_hal_rcc.c:1063:10:HAL_RCC_GetSysClockFreq 0 static stm32g4xx_hal_rcc.c:766:19:HAL_RCC_ClockConfig 32 static stm32g4xx_hal_rcc.c:1118:10:HAL_RCC_GetHCLKFreq 0 static stm32g4xx_hal_rcc.c:1129:10:HAL_RCC_GetPCLK1Freq 0 static stm32g4xx_hal_rcc.c:1141:10:HAL_RCC_GetPCLK2Freq 0 static stm32g4xx_hal_rcc.c:1154:6:HAL_RCC_GetOscConfig 0 static stm32g4xx_hal_rcc.c:1248:6:HAL_RCC_GetClockConfig 4 static stm32g4xx_hal_rcc.c:1283:6:HAL_RCC_EnableCSS 0 static stm32g4xx_hal_rcc.c:1297:6:HAL_RCC_EnableLSECSS 0 static stm32g4xx_hal_rcc.c:1308:6:HAL_RCC_DisableLSECSS 0 static stm32g4xx_hal_rcc.c:1335:13:HAL_RCC_CSSCallback 0 static stm32g4xx_hal_rcc.c:1318:6:HAL_RCC_NMI_IRQHandler 8 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.su ================================================ stm32g4xx_hal_rcc_ex.c:123:19:HAL_RCCEx_PeriphCLKConfig 32 static stm32g4xx_hal_rcc_ex.c:485:6:HAL_RCCEx_GetPeriphCLKConfig 0 static stm32g4xx_hal_rcc_ex.c:648:10:HAL_RCCEx_GetPeriphCLKFreq 0 static stm32g4xx_hal_rcc_ex.c:1286:6:HAL_RCCEx_EnableLSECSS 0 static stm32g4xx_hal_rcc_ex.c:1296:6:HAL_RCCEx_DisableLSECSS 0 static stm32g4xx_hal_rcc_ex.c:1309:6:HAL_RCCEx_EnableLSECSS_IT 0 static stm32g4xx_hal_rcc_ex.c:1343:13:HAL_RCCEx_LSECSS_Callback 0 static stm32g4xx_hal_rcc_ex.c:1326:6:HAL_RCCEx_LSECSS_IRQHandler 8 static stm32g4xx_hal_rcc_ex.c:1358:6:HAL_RCCEx_EnableLSCO 48 static stm32g4xx_hal_rcc_ex.c:1405:6:HAL_RCCEx_DisableLSCO 16 static stm32g4xx_hal_rcc_ex.c:1513:6:HAL_RCCEx_CRSConfig 8 static stm32g4xx_hal_rcc_ex.c:1555:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 0 static stm32g4xx_hal_rcc_ex.c:1565:6:HAL_RCCEx_CRSGetSynchronizationInfo 0 static stm32g4xx_hal_rcc_ex.c:1598:10:HAL_RCCEx_CRSWaitSynchronization 24 static stm32g4xx_hal_rcc_ex.c:1746:13:HAL_RCCEx_CRS_SyncOkCallback 0 static stm32g4xx_hal_rcc_ex.c:1757:13:HAL_RCCEx_CRS_SyncWarnCallback 0 static stm32g4xx_hal_rcc_ex.c:1768:13:HAL_RCCEx_CRS_ExpectedSyncCallback 0 static stm32g4xx_hal_rcc_ex.c:1784:13:HAL_RCCEx_CRS_ErrorCallback 0 static stm32g4xx_hal_rcc_ex.c:1681:6:HAL_RCCEx_CRS_IRQHandler 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.su ================================================ stm32g4xx_hal_tim.c:7163:13:TIM_OC1_SetConfig 16 static stm32g4xx_hal_tim.c:7315:13:TIM_OC3_SetConfig 16 static stm32g4xx_hal_tim.c:7390:13:TIM_OC4_SetConfig 16 static stm32g4xx_hal_tim.c:384:13:HAL_TIM_Base_MspInit 0 static stm32g4xx_hal_tim.c:281:19:HAL_TIM_Base_Init 16 static stm32g4xx_hal_tim.c:399:13:HAL_TIM_Base_MspDeInit 0 static stm32g4xx_hal_tim.c:341:19:HAL_TIM_Base_DeInit 8 static stm32g4xx_hal_tim.c:415:19:HAL_TIM_Base_Start 0 static stm32g4xx_hal_tim.c:454:19:HAL_TIM_Base_Stop 0 static stm32g4xx_hal_tim.c:474:19:HAL_TIM_Base_Start_IT 0 static stm32g4xx_hal_tim.c:516:19:HAL_TIM_Base_Stop_IT 0 static stm32g4xx_hal_tim.c:541:19:HAL_TIM_Base_Start_DMA 24 static stm32g4xx_hal_tim.c:610:19:HAL_TIM_Base_Stop_DMA 8 static stm32g4xx_hal_tim.c:768:13:HAL_TIM_OC_MspInit 0 static stm32g4xx_hal_tim.c:665:19:HAL_TIM_OC_Init 16 static stm32g4xx_hal_tim.c:783:13:HAL_TIM_OC_MspDeInit 0 static stm32g4xx_hal_tim.c:725:19:HAL_TIM_OC_DeInit 8 static stm32g4xx_hal_tim.c:806:19:HAL_TIM_OC_Start 4 static stm32g4xx_hal_tim.c:862:19:HAL_TIM_OC_Stop 12 static stm32g4xx_hal_tim.c:897:19:HAL_TIM_OC_Start_IT 4 static stm32g4xx_hal_tim.c:990:19:HAL_TIM_OC_Stop_IT 8 static stm32g4xx_hal_tim.c:1067:19:HAL_TIM_OC_Start_DMA 16 static stm32g4xx_hal_tim.c:1231:19:HAL_TIM_OC_Stop_DMA 16 static stm32g4xx_hal_tim.c:1437:13:HAL_TIM_PWM_MspInit 0 static stm32g4xx_hal_tim.c:1334:19:HAL_TIM_PWM_Init 16 static stm32g4xx_hal_tim.c:1452:13:HAL_TIM_PWM_MspDeInit 0 static stm32g4xx_hal_tim.c:1394:19:HAL_TIM_PWM_DeInit 8 static stm32g4xx_hal_tim.c:1475:19:HAL_TIM_PWM_Start 4 static stm32g4xx_hal_tim.c:1531:19:HAL_TIM_PWM_Stop 12 static stm32g4xx_hal_tim.c:1566:19:HAL_TIM_PWM_Start_IT 4 static stm32g4xx_hal_tim.c:1659:19:HAL_TIM_PWM_Stop_IT 8 static stm32g4xx_hal_tim.c:1736:19:HAL_TIM_PWM_Start_DMA 16 static stm32g4xx_hal_tim.c:1899:19:HAL_TIM_PWM_Stop_DMA 16 static stm32g4xx_hal_tim.c:2105:13:HAL_TIM_IC_MspInit 0 static stm32g4xx_hal_tim.c:2002:19:HAL_TIM_IC_Init 16 static stm32g4xx_hal_tim.c:2120:13:HAL_TIM_IC_MspDeInit 0 static stm32g4xx_hal_tim.c:2062:19:HAL_TIM_IC_DeInit 8 static stm32g4xx_hal_tim.c:2141:19:HAL_TIM_IC_Start 4 static stm32g4xx_hal_tim.c:2193:19:HAL_TIM_IC_Stop 8 static stm32g4xx_hal_tim.c:2223:19:HAL_TIM_IC_Start_IT 4 static stm32g4xx_hal_tim.c:2315:19:HAL_TIM_IC_Stop_IT 4 static stm32g4xx_hal_tim.c:2387:19:HAL_TIM_IC_Start_DMA 24 static stm32g4xx_hal_tim.c:2546:19:HAL_TIM_IC_Stop_DMA 16 static stm32g4xx_hal_tim.c:2765:13:HAL_TIM_OnePulse_MspInit 0 static stm32g4xx_hal_tim.c:2651:19:HAL_TIM_OnePulse_Init 16 static stm32g4xx_hal_tim.c:2780:13:HAL_TIM_OnePulse_MspDeInit 0 static stm32g4xx_hal_tim.c:2720:19:HAL_TIM_OnePulse_DeInit 8 static stm32g4xx_hal_tim.c:2800:19:HAL_TIM_OnePulse_Start 8 static stm32g4xx_hal_tim.c:2857:19:HAL_TIM_OnePulse_Stop 0 static stm32g4xx_hal_tim.c:2900:19:HAL_TIM_OnePulse_Start_IT 8 static stm32g4xx_hal_tim.c:2963:19:HAL_TIM_OnePulse_Stop_IT 0 static stm32g4xx_hal_tim.c:3202:13:HAL_TIM_Encoder_MspInit 0 static stm32g4xx_hal_tim.c:3042:19:HAL_TIM_Encoder_Init 24 static stm32g4xx_hal_tim.c:3217:13:HAL_TIM_Encoder_MspDeInit 0 static stm32g4xx_hal_tim.c:3157:19:HAL_TIM_Encoder_DeInit 8 static stm32g4xx_hal_tim.c:3237:19:HAL_TIM_Encoder_Start 8 static stm32g4xx_hal_tim.c:3331:19:HAL_TIM_Encoder_Stop 4 static stm32g4xx_hal_tim.c:3391:19:HAL_TIM_Encoder_Start_IT 8 static stm32g4xx_hal_tim.c:3491:19:HAL_TIM_Encoder_Stop_IT 4 static stm32g4xx_hal_tim.c:3556:19:HAL_TIM_Encoder_Start_DMA 32 static stm32g4xx_hal_tim.c:3769:19:HAL_TIM_Encoder_Stop_DMA 16 static stm32g4xx_hal_tim.c:4231:19:HAL_TIM_IC_ConfigChannel 16 static stm32g4xx_hal_tim.c:4637:19:HAL_TIM_DMABurst_WriteStart 24 static stm32g4xx_hal_tim.c:4699:19:HAL_TIM_DMABurst_MultiWriteStart 24 static stm32g4xx_hal_tim.c:4883:19:HAL_TIM_DMABurst_WriteStop 16 static stm32g4xx_hal_tim.c:4993:19:HAL_TIM_DMABurst_ReadStart 24 static stm32g4xx_hal_tim.c:5053:19:HAL_TIM_DMABurst_MultiReadStart 24 static stm32g4xx_hal_tim.c:5237:19:HAL_TIM_DMABurst_ReadStop 16 static stm32g4xx_hal_tim.c:5321:19:HAL_TIM_GenerateEvent 8 static stm32g4xx_hal_tim.c:5360:19:HAL_TIM_ConfigOCrefClear 16 static stm32g4xx_hal_tim.c:5562:19:HAL_TIM_ConfigClockSource 16 static stm32g4xx_hal_tim.c:5730:19:HAL_TIM_ConfigTI1Input 0 static stm32g4xx_hal_tim.c:5762:19:HAL_TIM_SlaveConfigSynchro 16 static stm32g4xx_hal_tim.c:5802:19:HAL_TIM_SlaveConfigSynchro_IT 16 static stm32g4xx_hal_tim.c:5845:10:HAL_TIM_ReadCapturedValue 0 static stm32g4xx_hal_tim.c:5933:13:HAL_TIM_PeriodElapsedCallback 0 static stm32g4xx_hal_tim.c:7033:13:TIM_DMAPeriodElapsedCplt 8 static stm32g4xx_hal_tim.c:5948:13:HAL_TIM_PeriodElapsedHalfCpltCallback 0 static stm32g4xx_hal_tim.c:7054:13:TIM_DMAPeriodElapsedHalfCplt 8 static stm32g4xx_hal_tim.c:5963:13:HAL_TIM_OC_DelayElapsedCallback 0 static stm32g4xx_hal_tim.c:5978:13:HAL_TIM_IC_CaptureCallback 0 static stm32g4xx_hal_tim.c:6931:6:TIM_DMACaptureCplt 8 static stm32g4xx_hal_tim.c:5993:13:HAL_TIM_IC_CaptureHalfCpltCallback 0 static stm32g4xx_hal_tim.c:6994:6:TIM_DMACaptureHalfCplt 8 static stm32g4xx_hal_tim.c:6008:13:HAL_TIM_PWM_PulseFinishedCallback 0 static stm32g4xx_hal_tim.c:6833:13:TIM_DMADelayPulseCplt 8 static stm32g4xx_hal_tim.c:6023:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 0 static stm32g4xx_hal_tim.c:6892:6:TIM_DMADelayPulseHalfCplt 8 static stm32g4xx_hal_tim.c:6038:13:HAL_TIM_TriggerCallback 0 static stm32g4xx_hal_tim.c:3846:6:HAL_TIM_IRQHandler 16 static stm32g4xx_hal_tim.c:7070:13:TIM_DMATriggerCplt 8 static stm32g4xx_hal_tim.c:6053:13:HAL_TIM_TriggerHalfCpltCallback 0 static stm32g4xx_hal_tim.c:7091:13:TIM_DMATriggerHalfCplt 8 static stm32g4xx_hal_tim.c:6068:13:HAL_TIM_ErrorCallback 0 static stm32g4xx_hal_tim.c:6790:6:TIM_DMAError 8 static stm32g4xx_hal_tim.c:6670:22:HAL_TIM_Base_GetState 0 static stm32g4xx_hal_tim.c:6680:22:HAL_TIM_OC_GetState 0 static stm32g4xx_hal_tim.c:6690:22:HAL_TIM_PWM_GetState 0 static stm32g4xx_hal_tim.c:6700:22:HAL_TIM_IC_GetState 0 static stm32g4xx_hal_tim.c:6710:22:HAL_TIM_OnePulse_GetState 0 static stm32g4xx_hal_tim.c:6720:22:HAL_TIM_Encoder_GetState 0 static stm32g4xx_hal_tim.c:6730:23:HAL_TIM_GetActiveChannel 0 static stm32g4xx_hal_tim.c:6748:29:HAL_TIM_GetChannelState 0 static stm32g4xx_hal_tim.c:6765:30:HAL_TIM_DMABurstState 0 static stm32g4xx_hal_tim.c:7108:6:TIM_Base_SetConfig 12 static stm32g4xx_hal_tim.c:7239:6:TIM_OC2_SetConfig 16 static stm32g4xx_hal_tim.c:4132:19:HAL_TIM_OC_ConfigChannel 24 static stm32g4xx_hal_tim.c:4332:19:HAL_TIM_PWM_ConfigChannel 24 static stm32g4xx_hal_tim.c:4480:19:HAL_TIM_OnePulse_ConfigChannel 56 static stm32g4xx_hal_tim.c:7726:6:TIM_TI1_SetConfig 12 static stm32g4xx_hal_tim.c:8031:6:TIM_ETR_SetConfig 4 static stm32g4xx_hal_tim.c:8063:6:TIM_CCxChannelCmd 4 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.su ================================================ stm32g4xx_hal_tim_ex.c:3608:13:TIM_DMAErrorCCxN 8 static stm32g4xx_hal_tim_ex.c:3549:13:TIM_DMADelayPulseNCplt 8 static stm32g4xx_hal_tim_ex.c:304:13:HAL_TIMEx_HallSensor_MspInit 0 static stm32g4xx_hal_tim_ex.c:157:19:HAL_TIMEx_HallSensor_Init 48 static stm32g4xx_hal_tim_ex.c:319:13:HAL_TIMEx_HallSensor_MspDeInit 0 static stm32g4xx_hal_tim_ex.c:259:19:HAL_TIMEx_HallSensor_DeInit 8 static stm32g4xx_hal_tim_ex.c:334:19:HAL_TIMEx_HallSensor_Start 16 static stm32g4xx_hal_tim_ex.c:388:19:HAL_TIMEx_HallSensor_Stop 8 static stm32g4xx_hal_tim_ex.c:416:19:HAL_TIMEx_HallSensor_Start_IT 16 static stm32g4xx_hal_tim_ex.c:473:19:HAL_TIMEx_HallSensor_Stop_IT 8 static stm32g4xx_hal_tim_ex.c:506:19:HAL_TIMEx_HallSensor_Start_DMA 24 static stm32g4xx_hal_tim_ex.c:582:19:HAL_TIMEx_HallSensor_Stop_DMA 8 static stm32g4xx_hal_tim_ex.c:645:19:HAL_TIMEx_OCN_Start 4 static stm32g4xx_hal_tim_ex.c:697:19:HAL_TIMEx_OCN_Stop 8 static stm32g4xx_hal_tim_ex.c:730:19:HAL_TIMEx_OCN_Start_IT 4 static stm32g4xx_hal_tim_ex.c:825:19:HAL_TIMEx_OCN_Stop_IT 8 static stm32g4xx_hal_tim_ex.c:908:19:HAL_TIMEx_OCN_Start_DMA 24 static stm32g4xx_hal_tim_ex.c:1068:19:HAL_TIMEx_OCN_Stop_DMA 16 static stm32g4xx_hal_tim_ex.c:1167:19:HAL_TIMEx_PWMN_Start 4 static stm32g4xx_hal_tim_ex.c:1218:19:HAL_TIMEx_PWMN_Stop 8 static stm32g4xx_hal_tim_ex.c:1251:19:HAL_TIMEx_PWMN_Start_IT 4 static stm32g4xx_hal_tim_ex.c:1345:19:HAL_TIMEx_PWMN_Stop_IT 8 static stm32g4xx_hal_tim_ex.c:1428:19:HAL_TIMEx_PWMN_Start_DMA 24 static stm32g4xx_hal_tim_ex.c:1588:19:HAL_TIMEx_PWMN_Stop_DMA 16 static stm32g4xx_hal_tim_ex.c:1687:19:HAL_TIMEx_OnePulseN_Start 24 static stm32g4xx_hal_tim_ex.c:1736:19:HAL_TIMEx_OnePulseN_Stop 8 static stm32g4xx_hal_tim_ex.c:1775:19:HAL_TIMEx_OnePulseN_Start_IT 24 static stm32g4xx_hal_tim_ex.c:1830:19:HAL_TIMEx_OnePulseN_Stop_IT 8 static stm32g4xx_hal_tim_ex.c:1924:19:HAL_TIMEx_ConfigCommutEvent 4 static stm32g4xx_hal_tim_ex.c:2015:19:HAL_TIMEx_ConfigCommutEvent_IT 4 static stm32g4xx_hal_tim_ex.c:2107:19:HAL_TIMEx_ConfigCommutEvent_DMA 12 static stm32g4xx_hal_tim_ex.c:2180:19:HAL_TIMEx_MasterConfigSynchronization 12 static stm32g4xx_hal_tim_ex.c:2253:19:HAL_TIMEx_ConfigBreakDeadTime 8 static stm32g4xx_hal_tim_ex.c:2321:19:HAL_TIMEx_ConfigBreakInput 16 static stm32g4xx_hal_tim_ex.c:2584:19:HAL_TIMEx_RemapConfig 0 static stm32g4xx_hal_tim_ex.c:2758:20:HAL_TIMEx_TISelection 4 static stm32g4xx_hal_tim_ex.c:2813:19:HAL_TIMEx_GroupChannel5 8 static stm32g4xx_hal_tim_ex.c:2851:19:HAL_TIMEx_DisarmBreakInput 0 static stm32g4xx_hal_tim_ex.c:2905:19:HAL_TIMEx_ReArmBreakInput 16 static stm32g4xx_hal_tim_ex.c:2988:19:HAL_TIMEx_DitheringEnable 0 static stm32g4xx_hal_tim_ex.c:3012:19:HAL_TIMEx_DitheringDisable 0 static stm32g4xx_hal_tim_ex.c:3030:19:HAL_TIMEx_OC_ConfigPulseOnCompare 8 static stm32g4xx_hal_tim_ex.c:3075:19:HAL_TIMEx_ConfigSlaveModePreload 0 static stm32g4xx_hal_tim_ex.c:3090:19:HAL_TIMEx_EnableSlaveModePreload 0 static stm32g4xx_hal_tim_ex.c:3104:19:HAL_TIMEx_DisableSlaveModePreload 0 static stm32g4xx_hal_tim_ex.c:3118:19:HAL_TIMEx_EnableDeadTimePreload 0 static stm32g4xx_hal_tim_ex.c:3132:19:HAL_TIMEx_DisableDeadTimePreload 0 static stm32g4xx_hal_tim_ex.c:3148:19:HAL_TIMEx_ConfigDeadTime 0 static stm32g4xx_hal_tim_ex.c:3165:19:HAL_TIMEx_ConfigAsymmetricalDeadTime 0 static stm32g4xx_hal_tim_ex.c:3180:19:HAL_TIMEx_EnableAsymmetricalDeadTime 0 static stm32g4xx_hal_tim_ex.c:3194:19:HAL_TIMEx_DisableAsymmetricalDeadTime 0 static stm32g4xx_hal_tim_ex.c:3212:19:HAL_TIMEx_ConfigEncoderIndex 16 static stm32g4xx_hal_tim_ex.c:3251:19:HAL_TIMEx_EnableEncoderIndex 0 static stm32g4xx_hal_tim_ex.c:3265:19:HAL_TIMEx_DisableEncoderIndex 0 static stm32g4xx_hal_tim_ex.c:3279:19:HAL_TIMEx_EnableEncoderFirstIndex 0 static stm32g4xx_hal_tim_ex.c:3293:19:HAL_TIMEx_DisableEncoderFirstIndex 0 static stm32g4xx_hal_tim_ex.c:3327:13:HAL_TIMEx_CommutCallback 0 static stm32g4xx_hal_tim_ex.c:3510:6:TIMEx_DMACommutationCplt 8 static stm32g4xx_hal_tim_ex.c:3341:13:HAL_TIMEx_CommutHalfCpltCallback 0 static stm32g4xx_hal_tim_ex.c:3529:6:TIMEx_DMACommutationHalfCplt 8 static stm32g4xx_hal_tim_ex.c:3356:13:HAL_TIMEx_BreakCallback 0 static stm32g4xx_hal_tim_ex.c:3371:13:HAL_TIMEx_Break2Callback 0 static stm32g4xx_hal_tim_ex.c:3386:13:HAL_TIMEx_EncoderIndexCallback 0 static stm32g4xx_hal_tim_ex.c:3401:13:HAL_TIMEx_DirectionChangeCallback 0 static stm32g4xx_hal_tim_ex.c:3416:13:HAL_TIMEx_IndexErrorCallback 0 static stm32g4xx_hal_tim_ex.c:3431:13:HAL_TIMEx_TransitionErrorCallback 0 static stm32g4xx_hal_tim_ex.c:3465:22:HAL_TIMEx_HallSensor_GetState 0 static stm32g4xx_hal_tim_ex.c:3481:29:HAL_TIMEx_GetChannelNState 0 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.su ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dac.su ================================================ stm32g4xx_ll_dac.h:2091:26:LL_DAC_IsEnabled 16 static stm32g4xx_ll_bus.h:581:22:LL_AHB2_GRP1_ForceReset 16 static stm32g4xx_ll_bus.h:623:22:LL_AHB2_GRP1_ReleaseReset 16 static stm32g4xx_ll_dac.c:216:13:LL_DAC_DeInit 16 static stm32g4xx_ll_dac.c:293:13:LL_DAC_Init 32 static stm32g4xx_ll_dac.c:398:6:LL_DAC_StructInit 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.su ================================================ stm32g4xx_ll_dma.h:599:22:LL_DMA_ConfigTransfer 32 static stm32g4xx_ll_dma.h:997:22:LL_DMA_SetDataLength 32 static stm32g4xx_ll_dma.h:1092:22:LL_DMA_SetMemoryAddress 32 static stm32g4xx_ll_dma.h:1117:22:LL_DMA_SetPeriphAddress 32 static stm32g4xx_ll_dma.h:1406:22:LL_DMA_SetPeriphRequest 32 static stm32g4xx_ll_dma.h:1943:22:LL_DMA_ClearFlag_GI1 16 static stm32g4xx_ll_dma.h:1958:22:LL_DMA_ClearFlag_GI2 16 static stm32g4xx_ll_dma.h:1973:22:LL_DMA_ClearFlag_GI3 16 static stm32g4xx_ll_dma.h:1988:22:LL_DMA_ClearFlag_GI4 16 static stm32g4xx_ll_dma.h:2003:22:LL_DMA_ClearFlag_GI5 16 static stm32g4xx_ll_dma.h:2018:22:LL_DMA_ClearFlag_GI6 16 static stm32g4xx_ll_bus.h:320:22:LL_AHB1_GRP1_ForceReset 16 static stm32g4xx_ll_bus.h:345:22:LL_AHB1_GRP1_ReleaseReset 16 static stm32g4xx_ll_dma.c:145:10:LL_DMA_DeInit 24 static stm32g4xx_ll_dma.c:273:10:LL_DMA_Init 24 static stm32g4xx_ll_dma.c:341:6:LL_DMA_StructInit 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_exti.su ================================================ stm32g4xx_ll_exti.h:312:22:LL_EXTI_EnableIT_0_31 16 static stm32g4xx_ll_exti.h:338:22:LL_EXTI_EnableIT_32_63 16 static stm32g4xx_ll_exti.h:387:22:LL_EXTI_DisableIT_0_31 16 static stm32g4xx_ll_exti.h:414:22:LL_EXTI_DisableIT_32_63 16 static stm32g4xx_ll_exti.h:544:22:LL_EXTI_EnableEvent_0_31 16 static stm32g4xx_ll_exti.h:569:22:LL_EXTI_EnableEvent_32_63 16 static stm32g4xx_ll_exti.h:615:22:LL_EXTI_DisableEvent_0_31 16 static stm32g4xx_ll_exti.h:639:22:LL_EXTI_DisableEvent_32_63 16 static stm32g4xx_ll_exti.h:763:22:LL_EXTI_EnableRisingTrig_0_31 16 static stm32g4xx_ll_exti.h:788:22:LL_EXTI_EnableRisingTrig_32_63 16 static stm32g4xx_ll_exti.h:833:22:LL_EXTI_DisableRisingTrig_0_31 16 static stm32g4xx_ll_exti.h:859:22:LL_EXTI_DisableRisingTrig_32_63 16 static stm32g4xx_ll_exti.h:968:22:LL_EXTI_EnableFallingTrig_0_31 16 static stm32g4xx_ll_exti.h:993:22:LL_EXTI_EnableFallingTrig_32_63 16 static stm32g4xx_ll_exti.h:1037:22:LL_EXTI_DisableFallingTrig_0_31 16 static stm32g4xx_ll_exti.h:1061:22:LL_EXTI_DisableFallingTrig_32_63 16 static stm32g4xx_ll_exti.c:79:10:LL_EXTI_DeInit 4 static stm32g4xx_ll_exti.c:121:10:LL_EXTI_Init 24 static stm32g4xx_ll_exti.c:268:6:LL_EXTI_StructInit 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_gpio.su ================================================ stm32g4xx_ll_gpio.h:285:22:LL_GPIO_SetPinMode 48 static,ignoring_inline_asm stm32g4xx_ll_gpio.h:354:22:LL_GPIO_SetPinOutputType 24 static stm32g4xx_ll_gpio.h:425:22:LL_GPIO_SetPinSpeed 48 static,ignoring_inline_asm stm32g4xx_ll_gpio.h:496:22:LL_GPIO_SetPinPull 48 static,ignoring_inline_asm stm32g4xx_ll_gpio.h:568:22:LL_GPIO_SetAFPin_0_7 48 static,ignoring_inline_asm stm32g4xx_ll_gpio.h:645:22:LL_GPIO_SetAFPin_8_15 48 static,ignoring_inline_asm stm32g4xx_ll_bus.h:581:22:LL_AHB2_GRP1_ForceReset 16 static stm32g4xx_ll_bus.h:623:22:LL_AHB2_GRP1_ReleaseReset 16 static stm32g4xx_ll_gpio.c:108:13:LL_GPIO_DeInit 24 static stm32g4xx_ll_gpio.c:168:13:LL_GPIO_Init 40 static,ignoring_inline_asm stm32g4xx_ll_gpio.c:240:6:LL_GPIO_StructInit 16 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h: ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.su ================================================ stm32g4xx_ll_utils.h:282:22:LL_InitTick 16 static stm32g4xx_ll_rcc.h:924:22:LL_RCC_HSE_EnableBypass 4 static stm32g4xx_ll_rcc.h:934:22:LL_RCC_HSE_DisableBypass 4 static stm32g4xx_ll_rcc.h:944:22:LL_RCC_HSE_Enable 4 static stm32g4xx_ll_rcc.h:964:26:LL_RCC_HSE_IsReady 4 static stm32g4xx_ll_rcc.h:1003:22:LL_RCC_HSI_Enable 4 static stm32g4xx_ll_rcc.h:1023:26:LL_RCC_HSI_IsReady 4 static stm32g4xx_ll_rcc.h:1340:22:LL_RCC_SetSysClkSource 16 static stm32g4xx_ll_rcc.h:1353:26:LL_RCC_GetSysClkSource 4 static stm32g4xx_ll_rcc.h:1373:22:LL_RCC_SetAHBPrescaler 16 static stm32g4xx_ll_rcc.h:1389:22:LL_RCC_SetAPB1Prescaler 16 static stm32g4xx_ll_rcc.h:1405:22:LL_RCC_SetAPB2Prescaler 16 static stm32g4xx_ll_rcc.h:2053:22:LL_RCC_PLL_Enable 4 static stm32g4xx_ll_rcc.h:2074:26:LL_RCC_PLL_IsReady 4 static stm32g4xx_ll_rcc.h:2117:22:LL_RCC_PLL_ConfigDomain_SYS 24 static stm32g4xx_ll_rcc.h:2446:22:LL_RCC_PLL_EnableDomain_SYS 4 static stm32g4xx_ll_system.h:1289:22:LL_FLASH_SetLatency 16 static stm32g4xx_ll_system.h:1317:26:LL_FLASH_GetLatency 4 static stm32g4xx_ll_pwr.h:330:26:LL_PWR_GetRegulVoltageScaling 4 static stm32g4xx_ll_pwr.h:361:26:LL_PWR_IsEnabledRange1BoostMode 16 static stm32g4xx_ll_utils.c:170:6:LL_Init1msTick 16 static stm32g4xx_ll_utils.c:186:6:LL_mDelay 24 static stm32g4xx_ll_utils.c:257:6:LL_SetSystemCoreClock 16 static stm32g4xx_ll_utils.c:271:13:LL_SetFlashLatency 40 static stm32g4xx_ll_utils.c:406:13:LL_PLL_ConfigSystemClock_HSI 32 static stm32g4xx_ll_utils.c:488:13:LL_PLL_ConfigSystemClock_HSE 40 static stm32g4xx_ll_utils.c:584:17:UTILS_GetPLLOutputFrequency 24 static stm32g4xx_ll_utils.c:615:20:UTILS_PLL_IsBusy 16 static stm32g4xx_ll_utils.c:638:20:UTILS_EnablePLLAndSwitchSystem 24 static ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c OBJS += \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o C_DEPS += \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d # Each subdirectory must supply rules for building sources it contributes Drivers/STM32G4xx_HAL_Driver/Src/%.o: ../Drivers/STM32G4xx_HAL_Driver/Src/%.c Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../App/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -Ofast -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src: -$(RM) ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o .PHONY: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/makefile ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ -include ../makefile.init RM := rm -rf # All of the sources participating in the build are defined here -include sources.mk -include Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk -include Core/Startup/subdir.mk -include Core/Src/subdir.mk -include App/Src/subdir.mk -include objects.mk ifneq ($(MAKECMDGOALS),clean) ifneq ($(strip $(S_DEPS)),) -include $(S_DEPS) endif ifneq ($(strip $(S_UPPER_DEPS)),) -include $(S_UPPER_DEPS) endif ifneq ($(strip $(C_DEPS)),) -include $(C_DEPS) endif endif -include ../makefile.defs OPTIONAL_TOOL_DEPS := \ $(wildcard ../makefile.defs) \ $(wildcard ../makefile.init) \ $(wildcard ../makefile.targets) \ BUILD_ARTIFACT_NAME := 2OPFM_G431 BUILD_ARTIFACT_EXTENSION := elf BUILD_ARTIFACT_PREFIX := BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) # Add inputs and outputs from these tool invocations to the build variables EXECUTABLES += \ 2OPFM_G431.elf \ SIZE_OUTPUT += \ default.size.stdout \ OBJDUMP_LIST += \ 2OPFM_G431.list \ OBJCOPY_BIN += \ 2OPFM_G431.bin \ # All Target all: main-build # Main-build Target main-build: 2OPFM_G431.elf secondary-outputs # Tool invocations 2OPFM_G431.elf: $(OBJS) $(USER_OBJS) /Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/STM32G431KBUX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-gcc -o "2OPFM_G431.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_G431/STM32G431KBUX_FLASH.ld" --specs=nosys.specs -Wl,-Map="2OPFM_G431.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group @echo 'Finished building target: $@' @echo ' ' default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-size $(EXECUTABLES) @echo 'Finished building: $@' @echo ' ' 2OPFM_G431.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-objdump -h -S $(EXECUTABLES) > "2OPFM_G431.list" @echo 'Finished building: $@' @echo ' ' 2OPFM_G431.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-objcopy -O binary $(EXECUTABLES) "2OPFM_G431.bin" @echo 'Finished building: $@' @echo ' ' # Other Targets clean: -$(RM) 2OPFM_G431.bin 2OPFM_G431.elf 2OPFM_G431.list default.size.stdout -@echo ' ' secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) fail-specified-linker-script-missing: @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' @exit 2 warn-no-linker-script-specified: @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' .PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified -include ../makefile.targets ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/objects.list ================================================ "./App/Src/2op_main.o" "./App/Src/dynamic_smooth.o" "./App/Src/loop.o" "./Core/Src/adc.o" "./Core/Src/dac.o" "./Core/Src/dma.o" "./Core/Src/gpio.o" "./Core/Src/main.o" "./Core/Src/stm32g4xx_hal_msp.o" "./Core/Src/stm32g4xx_it.o" "./Core/Src/syscalls.o" "./Core/Src/sysmem.o" "./Core/Src/system_stm32g4xx.o" "./Core/Src/tim.o" "./Core/Startup/startup_stm32g431kbux.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o" ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/objects.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ USER_OBJS := LIBS := ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Debug/sources.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ ELF_SRCS := OBJ_SRCS := S_SRCS := C_SRCS := S_UPPER_SRCS := O_SRCS := SIZE_OUTPUT := OBJDUMP_LIST := EXECUTABLES := OBJS := S_DEPS := S_UPPER_DEPS := C_DEPS := OBJCOPY_BIN := # Every subdirectory with source files must be described here SUBDIRS := \ App/Src \ Core/Src \ Core/Startup \ Drivers/STM32G4xx_HAL_Driver/Src \ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h ================================================ /** ****************************************************************************** * @file stm32g431xx.h * @author MCD Application Team * @brief CMSIS STM32G431xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32g431xx * @{ */ #ifndef __STM32G431xx_H #define __STM32G431xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /*!< FPU present */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32G4XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers ***************************************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_IRQn = 19, /*!< USB HP Interrupt */ USB_LP_IRQn = 20, /*!< USB LP Interrupt */ FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupts */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ COMP4_IRQn = 65, /*!< COMP4 */ CRS_IRQn = 75, /*!< CRS global interrupt */ SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ RNG_IRQn = 90, /*!< RNG global interrupt */ LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ FMAC_IRQn = 101 /*!< FMAC global Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32g4xx.h" #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved, 0x1C */ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x2C */ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ uint32_t RESERVED3; /*!< Reserved, 0x44 */ uint32_t RESERVED4; /*!< Reserved, 0x48 */ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ uint32_t RESERVED9; /*!< Reserved, 0x0AC */ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ } ADC_Common_TypeDef; /** * @brief FD Controller Area Network */ typedef struct { __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ uint32_t RESERVED1; /*!< Reserved, 0x008 */ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ uint32_t RESERVED3; /*!< Reserved, 0x04C */ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ uint32_t RESERVED5; /*!< Reserved, 0x08C */ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ } FDCAN_GlobalTypeDef; /** * @brief FD Controller Area Network Configuration */ typedef struct { __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ } FDCAN_Config_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ } COMP_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED0; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ } CRS_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ __IO uint32_t RESERVED[2]; __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** * @brief DMA Multiplexer */ typedef struct { __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ }DMAMUX_Channel_TypeDef; typedef struct { __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ }DMAMUX_ChannelStatus_TypeDef; typedef struct { __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ }DMAMUX_RequestGen_TypeDef; typedef struct { __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ }DMAMUX_RequestGenStatus_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ } FLASH_TypeDef; /** * @brief FMAC */ typedef struct { __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ } FMAC_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ } IWDG_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ } LPTIM_TypeDef; /** * @brief Operational Amplifier (OPAMP) */ typedef struct { __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ } OPAMP_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ } RCC_TypeDef; /** * @brief Real-Time Clock */ /* * @brief Specific device feature definitions */ #define RTC_TAMP_INT_6_SUPPORT #define RTC_TAMP_INT_NB 4u #define RTC_TAMP_NB 3u #define RTC_BACKUP_NB 16u typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ } RTC_TypeDef; /** * @brief Tamper and backup registers */ typedef struct { __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ } TAMP_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ } SYSCFG_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ } USART_TypeDef; /** * @brief Universal Serial Bus Full Speed Device */ typedef struct { __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ __IO uint16_t RESERVED2; /*!< Reserved */ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ __IO uint16_t RESERVEDC; /*!< Reserved */ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ __IO uint16_t RESERVEDD; /*!< Reserved */ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ __IO uint16_t RESERVEDE; /*!< Reserved */ } USB_TypeDef; /** * @brief VREFBUF */ typedef struct { __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ } VREFBUF_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @brief CORDIC */ typedef struct { __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ } CORDIC_TypeDef; /** * @brief UCPD */ typedef struct { __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ } UCPD_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */ #define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */ #define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */ #define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */ #define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */ #define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */ #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE #define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */ #define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */ #define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) #define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) #define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ #define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ #define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) #define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) #define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) #define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) #define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) /*!< APB2 peripherals */ #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) #define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) #define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) #define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) #define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) #define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) #define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) #define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) #define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL) #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL) #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL) #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL) #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL) #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL) #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) /*!< AHB2 peripherals */ #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) #define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) #define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) #define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) #define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) #define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) #define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ #define DBGMCU_BASE (0xE0042000UL) #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) #define TAMP ((TAMP_TypeDef *) TAMP_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) #define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) #define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) #define COMP1 ((COMP_TypeDef *) COMP1_BASE) #define COMP2 ((COMP_TypeDef *) COMP2_BASE) #define COMP3 ((COMP_TypeDef *) COMP3_BASE) #define COMP4 ((COMP_TypeDef *) COMP4_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FMAC ((FMAC_TypeDef *) FMAC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define DAC1 ((DAC_TypeDef *) DAC1_BASE) #define DAC3 ((DAC_TypeDef *) DAC3_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Hardware_Constant_Definition * @{ */ #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ /** * @} */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_EXTSEL_Pos (5U) #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ #define ADC_CFGR2_GCOMP_Pos (16U) #define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ #define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ #define ADC_CFGR2_SWTRIG_Pos (25U) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ #define ADC_CFGR2_BULB_Pos (26U) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ #define ADC_CFGR2_SMPTRIG_Pos (27U) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ #define ADC_SMPR1_SMPPLUS_Pos (31U) #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_AWDFILT_Pos (12U) #define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ #define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ #define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ #define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ #define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ #define ADC_TR1_HT1_Pos (16U) #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_HT2_Pos (16U) #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_HT3_Pos (16U) #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSETPOS_Pos (24U) #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR1_SATEN_Pos (25U) #define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSETPOS_Pos (24U) #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ #define ADC_OFR2_SATEN_Pos (25U) #define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSETPOS_Pos (24U) #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ #define ADC_OFR3_SATEN_Pos (25U) #define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSETPOS_Pos (24U) #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ #define ADC_OFR4_SATEN_Pos (25U) #define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ /******************** Bit definition for ADC_GCOMP register *****************/ #define ADC_GCOMP_GCOMPCOEFF_Pos (0U) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_VSENSESEL_Pos (23U) #define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ #define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATSEL_Pos (24U) #define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_SLV_Pos (16U) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ /* */ /******************************************************************************/ /********************** Bit definition for COMP_CSR register ****************/ #define COMP_CSR_EN_Pos (0U) #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ #define COMP_CSR_INMSEL_Pos (4U) #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ #define COMP_CSR_INPSEL_Pos (8U) #define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ #define COMP_CSR_POLARITY_Pos (15U) #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ #define COMP_CSR_HYST_Pos (16U) #define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ #define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ #define COMP_CSR_BLANKING_Pos (19U) #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ #define COMP_CSR_BRGEN_Pos (22U) #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ #define COMP_CSR_SCALEN_Pos (23U) #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ #define COMP_CSR_VALUE_Pos (30U) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ #define COMP_CSR_LOCK_Pos (31U) #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ /******************************************************************************/ /* */ /* CORDIC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CORDIC_CSR register *****************/ #define CORDIC_CSR_FUNC_Pos (0U) #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ #define CORDIC_CSR_PRECISION_Pos (4U) #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ #define CORDIC_CSR_SCALE_Pos (8U) #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ #define CORDIC_CSR_IEN_Pos (16U) #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ #define CORDIC_CSR_DMAREN_Pos (17U) #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ #define CORDIC_CSR_DMAWEN_Pos (18U) #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ #define CORDIC_CSR_NRES_Pos (19U) #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ #define CORDIC_CSR_NARGS_Pos (20U) #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ #define CORDIC_CSR_RESSIZE_Pos (21U) #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ #define CORDIC_CSR_ARGSIZE_Pos (22U) #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ #define CORDIC_CSR_RRDY_Pos (31U) #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ /******************* Bit definition for CORDIC_WDATA register ***************/ #define CORDIC_WDATA_ARG_Pos (0U) #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ /******************* Bit definition for CORDIC_RDATA register ***************/ #define CORDIC_RDATA_RES_Pos (0U) #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ #define CRC_CR_POLYSIZE_Pos (3U) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ #define CRC_CR_REV_IN_Pos (5U) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ #define CRC_CR_REV_OUT_Pos (7U) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT_Pos (0U) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL_Pos (0U) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ #define CRS_CR_SYNCOKIE_Pos (0U) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ #define CRS_CR_SYNCWARNIE_Pos (1U) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ #define CRS_CR_ERRIE_Pos (2U) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ #define CRS_CR_ESYNCIE_Pos (3U) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ #define CRS_CR_CEN_Pos (5U) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ #define CRS_CR_AUTOTRIMEN_Pos (6U) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ #define CRS_CR_SWSYNC_Pos (7U) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ #define CRS_CFGR_RELOAD_Pos (0U) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ #define CRS_CFGR_FELIM_Pos (16U) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ #define CRS_CFGR_SYNCDIV_Pos (24U) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ #define CRS_CFGR_SYNCSRC_Pos (28U) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ #define CRS_CFGR_SYNCPOL_Pos (31U) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ #define CRS_ISR_SYNCOKF_Pos (0U) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ #define CRS_ISR_SYNCWARNF_Pos (1U) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ #define CRS_ISR_ERRF_Pos (2U) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ #define CRS_ISR_ESYNCF_Pos (3U) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ #define CRS_ISR_SYNCERR_Pos (8U) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ #define CRS_ISR_SYNCMISS_Pos (9U) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ #define CRS_ISR_TRIMOVF_Pos (10U) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ #define CRS_ISR_FEDIR_Pos (15U) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ #define CRS_ISR_FECAP_Pos (16U) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ #define CRS_ICR_SYNCOKC_Pos (0U) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ #define CRS_ICR_SYNCWARNC_Pos (1U) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ #define CRS_ICR_ERRC_Pos (2U) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ #define CRS_ICR_ESYNCC_Pos (3U) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) #define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return result; } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/cmsis_armclang.h ================================================ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V5.2.0 * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) #define __SADD8 __builtin_arm_sadd8 #define __QADD8 __builtin_arm_qadd8 #define __SHADD8 __builtin_arm_shadd8 #define __UADD8 __builtin_arm_uadd8 #define __UQADD8 __builtin_arm_uqadd8 #define __UHADD8 __builtin_arm_uhadd8 #define __SSUB8 __builtin_arm_ssub8 #define __QSUB8 __builtin_arm_qsub8 #define __SHSUB8 __builtin_arm_shsub8 #define __USUB8 __builtin_arm_usub8 #define __UQSUB8 __builtin_arm_uqsub8 #define __UHSUB8 __builtin_arm_uhsub8 #define __SADD16 __builtin_arm_sadd16 #define __QADD16 __builtin_arm_qadd16 #define __SHADD16 __builtin_arm_shadd16 #define __UADD16 __builtin_arm_uadd16 #define __UQADD16 __builtin_arm_uqadd16 #define __UHADD16 __builtin_arm_uhadd16 #define __SSUB16 __builtin_arm_ssub16 #define __QSUB16 __builtin_arm_qsub16 #define __SHSUB16 __builtin_arm_shsub16 #define __USUB16 __builtin_arm_usub16 #define __UQSUB16 __builtin_arm_uqsub16 #define __UHSUB16 __builtin_arm_uhsub16 #define __SASX __builtin_arm_sasx #define __QASX __builtin_arm_qasx #define __SHASX __builtin_arm_shasx #define __UASX __builtin_arm_uasx #define __UQASX __builtin_arm_uqasx #define __UHASX __builtin_arm_uhasx #define __SSAX __builtin_arm_ssax #define __QSAX __builtin_arm_qsax #define __SHSAX __builtin_arm_shsax #define __USAX __builtin_arm_usax #define __UQSAX __builtin_arm_uqsax #define __UHSAX __builtin_arm_uhsax #define __USAD8 __builtin_arm_usad8 #define __USADA8 __builtin_arm_usada8 #define __SSAT16 __builtin_arm_ssat16 #define __USAT16 __builtin_arm_usat16 #define __UXTB16 __builtin_arm_uxtb16 #define __UXTAB16 __builtin_arm_uxtab16 #define __SXTB16 __builtin_arm_sxtb16 #define __SXTAB16 __builtin_arm_sxtab16 #define __SMUAD __builtin_arm_smuad #define __SMUADX __builtin_arm_smuadx #define __SMLAD __builtin_arm_smlad #define __SMLADX __builtin_arm_smladx #define __SMLALD __builtin_arm_smlald #define __SMLALDX __builtin_arm_smlaldx #define __SMUSD __builtin_arm_smusd #define __SMUSDX __builtin_arm_smusdx #define __SMLSD __builtin_arm_smlsd #define __SMLSDX __builtin_arm_smlsdx #define __SMLSLD __builtin_arm_smlsld #define __SMLSLDX __builtin_arm_smlsldx #define __SEL __builtin_arm_sel #define __QADD __builtin_arm_qadd #define __QSUB __builtin_arm_qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/cmsis_armclang_ltm.h ================================================ /**************************************************************************//** * @file cmsis_armclang_ltm.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V1.2.0 * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2018-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/cmsis_compiler.h ================================================ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file * @version V5.1.0 * @date 09. October 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* * Arm Compiler 6.6 LTM (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) #include "cmsis_armclang_ltm.h" /* * Arm Compiler above 6.10.1 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) #include /* * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) #include #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) #include #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif #else #error Unknown compiler. #endif #endif /* __CMSIS_COMPILER_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/cmsis_gcc.h ================================================ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V5.2.0 * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START /** \brief Initializes data and bss sections \details This default implementations initialized all data and additional bss sections relying on .copy.table and .zero.table specified properly in the used linker script. */ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) { extern void _start(void) __NO_RETURN; typedef struct { uint32_t const* src; uint32_t* dest; uint32_t wlen; } __copy_table_t; typedef struct { uint32_t* dest; uint32_t wlen; } __zero_table_t; extern const __copy_table_t __copy_table_start__; extern const __copy_table_t __copy_table_end__; extern const __zero_table_t __zero_table_start__; extern const __zero_table_t __zero_table_end__; for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = pTable->src[i]; } } for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = 0u; } } _start(); } #define __PROGRAM_START __cmsis_start #endif #ifndef __INITIAL_SP #define __INITIAL_SP __StackTop #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT __StackLimit #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #endif #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_set_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #endif #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI() __ASM volatile ("wfi") /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE() __ASM volatile ("wfe") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV() __ASM volatile ("sev") /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); #else int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/cmsis_iccarm.h ================================================ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.1.0 * @date 08. May 2019 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2019 IAR Systems // Copyright (c) 2017-2019 Arm Limited. All rights reserved. // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // //------------------------------------------------------------------------------ #ifndef __CMSIS_ICCARM_H__ #define __CMSIS_ICCARM_H__ #ifndef __ICCARM__ #error This file should only be compiled by ICCARM #endif #pragma system_include #define __IAR_FT _Pragma("inline=forced") __intrinsic #if (__VER__ >= 8000000) #define __ICCARM_V8 1 #else #define __ICCARM_V8 0 #endif #ifndef __ALIGNED #if __ICCARM_V8 #define __ALIGNED(x) __attribute__((aligned(x))) #elif (__VER__ >= 7080000) /* Needs IAR language extensions */ #define __ALIGNED(x) __attribute__((aligned(x))) #else #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. #define __ALIGNED(x) #endif #endif /* Define compiler macros for CPU architecture, used in CMSIS 5. */ #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ /* Macros already defined */ #else #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' #if __ARM_ARCH == 6 #define __ARM_ARCH_6M__ 1 #elif __ARM_ARCH == 7 #if __ARM_FEATURE_DSP #define __ARM_ARCH_7EM__ 1 #else #define __ARM_ARCH_7M__ 1 #endif #endif /* __ARM_ARCH */ #endif /* __ARM_ARCH_PROFILE == 'M' */ #endif /* Alternativ core deduction for older ICCARM's */ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) #define __ARM_ARCH_6M__ 1 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) #define __ARM_ARCH_7M__ 1 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) #define __ARM_ARCH_7EM__ 1 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #else #error "Unknown target." #endif #endif #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 #define __IAR_M0_FAMILY 1 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 #define __IAR_M0_FAMILY 1 #else #define __IAR_M0_FAMILY 0 #endif #ifndef __ASM #define __ASM __asm #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __NO_RETURN #if __ICCARM_V8 #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif #endif #ifndef __PACKED #if __ICCARM_V8 #define __PACKED __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED __packed #endif #endif #ifndef __PACKED_STRUCT #if __ICCARM_V8 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_STRUCT __packed struct #endif #endif #ifndef __PACKED_UNION #if __ICCARM_V8 #define __PACKED_UNION union __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_UNION __packed union #endif #endif #ifndef __RESTRICT #if __ICCARM_V8 #define __RESTRICT __restrict #else /* Needs IAR language extensions */ #define __RESTRICT restrict #endif #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma language=save #pragma language=extended __packed struct __iar_u32 { uint32_t v; }; #pragma language=restore #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) #endif #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) #else #define __USED _Pragma("__root") #endif #endif #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) #else #define __WEAK _Pragma("__weak") #endif #endif #ifndef __PROGRAM_START #define __PROGRAM_START __iar_program_start #endif #ifndef __INITIAL_SP #define __INITIAL_SP CSTACK$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT CSTACK$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __vector_table #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE @".intvec" #endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif #if __ICCARM_INTRINSICS_VERSION__ == 2 #if defined(__CLZ) #undef __CLZ #endif #if defined(__REVSH) #undef __REVSH #endif #if defined(__RBIT) #undef __RBIT #endif #if defined(__SSAT) #undef __SSAT #endif #if defined(__USAT) #undef __USAT #endif #include "iccarm_builtin.h" #define __disable_fault_irq __iar_builtin_disable_fiq #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt #define __arm_rsr __iar_builtin_rsr #define __arm_wsr __iar_builtin_wsr #define __get_APSR() (__arm_rsr("APSR")) #define __get_BASEPRI() (__arm_rsr("BASEPRI")) #define __get_CONTROL() (__arm_rsr("CONTROL")) #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR() (__arm_rsr("FPSCR")) #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) #else #define __get_FPSCR() ( 0 ) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #define __get_IPSR() (__arm_rsr("IPSR")) #define __get_MSP() (__arm_rsr("MSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __get_MSPLIM() (0U) #else #define __get_MSPLIM() (__arm_rsr("MSPLIM")) #endif #define __get_PRIMASK() (__arm_rsr("PRIMASK")) #define __get_PSP() (__arm_rsr("PSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __get_PSPLIM() (0U) #else #define __get_PSPLIM() (__arm_rsr("PSPLIM")) #endif #define __get_xPSR() (__arm_rsr("xPSR")) #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __set_MSPLIM(VALUE) ((void)(VALUE)) #else #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) #endif #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __set_PSPLIM(VALUE) ((void)(VALUE)) #else #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __TZ_get_PSPLIM_NS() (0U) #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) #else #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) #endif #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) #define __NOP __iar_builtin_no_operation #define __CLZ __iar_builtin_CLZ #define __CLREX __iar_builtin_CLREX #define __DMB __iar_builtin_DMB #define __DSB __iar_builtin_DSB #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH #define __LDREXW __iar_builtin_LDREX #define __RBIT __iar_builtin_RBIT #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 __IAR_FT int16_t __REVSH(int16_t val) { return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR #define __RRX __iar_builtin_RRX #define __SEV __iar_builtin_SEV #if !__IAR_M0_FAMILY #define __SSAT __iar_builtin_SSAT #endif #define __STREXB __iar_builtin_STREXB #define __STREXH __iar_builtin_STREXH #define __STREXW __iar_builtin_STREX #if !__IAR_M0_FAMILY #define __USAT __iar_builtin_USAT #endif #define __WFE __iar_builtin_WFE #define __WFI __iar_builtin_WFI #if __ARM_MEDIA__ #define __SADD8 __iar_builtin_SADD8 #define __QADD8 __iar_builtin_QADD8 #define __SHADD8 __iar_builtin_SHADD8 #define __UADD8 __iar_builtin_UADD8 #define __UQADD8 __iar_builtin_UQADD8 #define __UHADD8 __iar_builtin_UHADD8 #define __SSUB8 __iar_builtin_SSUB8 #define __QSUB8 __iar_builtin_QSUB8 #define __SHSUB8 __iar_builtin_SHSUB8 #define __USUB8 __iar_builtin_USUB8 #define __UQSUB8 __iar_builtin_UQSUB8 #define __UHSUB8 __iar_builtin_UHSUB8 #define __SADD16 __iar_builtin_SADD16 #define __QADD16 __iar_builtin_QADD16 #define __SHADD16 __iar_builtin_SHADD16 #define __UADD16 __iar_builtin_UADD16 #define __UQADD16 __iar_builtin_UQADD16 #define __UHADD16 __iar_builtin_UHADD16 #define __SSUB16 __iar_builtin_SSUB16 #define __QSUB16 __iar_builtin_QSUB16 #define __SHSUB16 __iar_builtin_SHSUB16 #define __USUB16 __iar_builtin_USUB16 #define __UQSUB16 __iar_builtin_UQSUB16 #define __UHSUB16 __iar_builtin_UHSUB16 #define __SASX __iar_builtin_SASX #define __QASX __iar_builtin_QASX #define __SHASX __iar_builtin_SHASX #define __UASX __iar_builtin_UASX #define __UQASX __iar_builtin_UQASX #define __UHASX __iar_builtin_UHASX #define __SSAX __iar_builtin_SSAX #define __QSAX __iar_builtin_QSAX #define __SHSAX __iar_builtin_SHSAX #define __USAX __iar_builtin_USAX #define __UQSAX __iar_builtin_UQSAX #define __UHSAX __iar_builtin_UHSAX #define __USAD8 __iar_builtin_USAD8 #define __USADA8 __iar_builtin_USADA8 #define __SSAT16 __iar_builtin_SSAT16 #define __USAT16 __iar_builtin_USAT16 #define __UXTB16 __iar_builtin_UXTB16 #define __UXTAB16 __iar_builtin_UXTAB16 #define __SXTB16 __iar_builtin_SXTB16 #define __SXTAB16 __iar_builtin_SXTAB16 #define __SMUAD __iar_builtin_SMUAD #define __SMUADX __iar_builtin_SMUADX #define __SMMLA __iar_builtin_SMMLA #define __SMLAD __iar_builtin_SMLAD #define __SMLADX __iar_builtin_SMLADX #define __SMLALD __iar_builtin_SMLALD #define __SMLALDX __iar_builtin_SMLALDX #define __SMUSD __iar_builtin_SMUSD #define __SMUSDX __iar_builtin_SMUSDX #define __SMLSD __iar_builtin_SMLSD #define __SMLSDX __iar_builtin_SMLSDX #define __SMLSLD __iar_builtin_SMLSLD #define __SMLSLDX __iar_builtin_SMLSLDX #define __SEL __iar_builtin_SEL #define __QADD __iar_builtin_QADD #define __QSUB __iar_builtin_QSUB #define __PKHBT __iar_builtin_PKHBT #define __PKHTB __iar_builtin_PKHTB #endif #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #define __CLZ __cmsis_iar_clz_not_active #define __SSAT __cmsis_iar_ssat_not_active #define __USAT __cmsis_iar_usat_not_active #define __RBIT __cmsis_iar_rbit_not_active #define __get_APSR __cmsis_iar_get_APSR_not_active #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #define __set_FPSCR __cmsis_iar_set_FPSR_not_active #endif #ifdef __INTRINSICS_INCLUDED #error intrinsics.h is already included previously! #endif #include #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #undef __CLZ #undef __SSAT #undef __USAT #undef __RBIT #undef __get_APSR __STATIC_INLINE uint8_t __CLZ(uint32_t data) { if (data == 0U) { return 32U; } uint32_t count = 0U; uint32_t mask = 0x80000000U; while ((data & mask) == 0U) { count += 1U; mask = mask >> 1U; } return count; } __STATIC_INLINE uint32_t __RBIT(uint32_t v) { uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) { r <<= 1U; r |= v & 1U; sc--; } return (r << sc); } __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t res; __asm("MRS %0,APSR" : "=r" (res)); return res; } #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #undef __get_FPSCR #undef __set_FPSCR #define __get_FPSCR() (0) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #pragma diag_suppress=Pe940 #pragma diag_suppress=Pe177 #define __enable_irq __enable_interrupt #define __disable_irq __disable_interrupt #define __NOP __no_operation #define __get_xPSR __get_PSR #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); } __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); } #endif /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); } #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #endif /* (__CORTEX_M >= 0x03) */ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint32_t __get_MSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,MSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_MSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR MSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __get_PSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_PSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR PSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_MSP_NS(void) { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR MSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_SP_NS(void) { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR SP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); #endif return res; } __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t res; __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t res; __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { uint32_t res; __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #undef __IAR_FT #undef __IAR_M0_FAMILY #undef __ICCARM_V8 #pragma diag_default=Pe940 #pragma diag_default=Pe177 #endif /* __CMSIS_ICCARM_H__ */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/cmsis_version.h ================================================ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions * @version V5.0.3 * @date 24. June 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_VERSION_H #define __CMSIS_VERSION_H /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_armv81mml.h ================================================ /**************************************************************************//** * @file core_armv81mml.h * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File * @version V1.0.0 * @date 15. March 2019 ******************************************************************************/ /* * Copyright (c) 2018-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV81MML_H_GENERIC #define __CORE_ARMV81MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMV81MML @{ */ #include "cmsis_version.h" #define __ARM_ARCH_8M_MAIN__ 1 // patching for now /* CMSIS ARMV81MML definitions */ #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV81MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV81MML_H_DEPENDANT #define __CORE_ARMV81MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv81MML_REV #define __ARMv81MML_REV 0x0000U #warning "__ARMv81MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv81MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ #define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV81MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_armv8mbl.h ================================================ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File * @version V5.0.8 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MBL_H_GENERIC #define __CORE_ARMV8MBL_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MBL @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MBL_H_DEPENDANT #define __CORE_ARMV8MBL_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MBL_REV #define __ARMv8MBL_REV 0x0000U #warning "__ARMv8MBL_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MBL */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_armv8mml.h ================================================ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File * @version V5.1.0 * @date 12. September 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MML_H_GENERIC #define __CORE_ARMV8MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MML @{ */ #include "cmsis_version.h" /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MML_H_DEPENDANT #define __CORE_ARMV8MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MML_REV #define __ARMv8MML_REV 0x0000U #warning "__ARMv8MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm0.h ================================================ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V5.0.6 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ #include "cmsis_version.h" /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = 0x0U; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = 0x0U; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm0plus.h ================================================ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V5.0.7 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ #include "cmsis_version.h" /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000U #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t vectors = SCB->VTOR; #else uint32_t vectors = 0x0U; #endif (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t vectors = SCB->VTOR; #else uint32_t vectors = 0x0U; #endif return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm1.h ================================================ /**************************************************************************//** * @file core_cm1.h * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File * @version V1.0.1 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM1_H_GENERIC #define __CORE_CM1_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M1 @{ */ #include "cmsis_version.h" /* CMSIS CM1 definitions */ #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (1U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM1_H_DEPENDANT #define __CORE_CM1_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM1_REV #define __CM1_REV 0x0100U #warning "__CM1_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M1 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M1 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)0x0U; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm23.h ================================================ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM23_H_GENERIC #define __CORE_CM23_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M23 @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (23U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM23_H_DEPENDANT #define __CORE_CM23_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM23_REV #define __CM23_REV 0x0000U #warning "__CM23_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M23 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm3.h ================================================ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ #include "cmsis_version.h" /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ #endif /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm33.h ================================================ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM33_H_GENERIC #define __CORE_CM33_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M33 @{ */ #include "cmsis_version.h" /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM33_H_DEPENDANT #define __CORE_CM33_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM33_REV #define __CM33_REV 0x0000U #warning "__CM33_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M33 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm35p.h ================================================ /**************************************************************************//** * @file core_cm35p.h * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File * @version V1.0.0 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM35P_H_GENERIC #define __CORE_CM35P_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M35P @{ */ #include "cmsis_version.h" /* CMSIS CM35P definitions */ #define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (35U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM35P_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM35P_H_DEPENDANT #define __CORE_CM35P_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM35P_REV #define __CM35P_REV 0x0000U #warning "__CM35P_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M35P */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM35P_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm4.h ================================================ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ #include "cmsis_version.h" /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000U #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_cm7.h ================================================ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V5.1.1 * @date 28. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M7 @{ */ #include "cmsis_version.h" /* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (7U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM7_H_DEPENDANT #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM7_REV #define __CM7_REV 0x0000U #warning "__CM7_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M7 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED3[93U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ #define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ #define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ #define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ #define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ #define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ #define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ #define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ #define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ #define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED3[981U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = SCB->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_FORCEINLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief I-Cache Invalidate by address \details Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] isize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if ( isize > 0 ) { int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_ICACHE_LINE_SIZE; op_size -= __SCB_ICACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_FORCEINLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_FORCEINLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_FORCEINLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address. D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /*@} end of CMSIS_Core_CacheFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_sc000.h ================================================ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.6 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ #include "cmsis_version.h" /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/core_sc300.h ================================================ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 31. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ #include "cmsis_version.h" /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/mpu_armv7.h ================================================ /****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU * @version V5.1.0 * @date 08. March 2019 ******************************************************************************/ /* * Copyright (c) 2017-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access /** MPU Region Base Address Register Value * * \param Region The region to be configured, number 0 to 15. * \param BaseAddress The base address for the region. */ #define ARM_MPU_RBAR(Region, BaseAddress) \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \ (MPU_RBAR_VALID_Msk)) /** * MPU Memory Access Attributes * * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. */ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ (((MPU_RASR_ENABLE_Msk)))) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) /** * MPU Memory Access Attribute for strongly ordered memory. * - TEX: 000b * - Shareable * - Non-cacheable * - Non-bufferable */ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** * MPU Memory Access Attribute for device memory. * - TEX: 000b (if shareable) or 010b (if non-shareable) * - Shareable or non-shareable * - Non-cacheable * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** * MPU Memory Access Attribute for normal memory. * - TEX: 1BBb (reflecting outer cacheability rules) * - Shareable or non-shareable * - Cacheable or non-cacheable (reflecting inner cacheability rules) * - Bufferable or non-bufferable (reflecting inner cacheability rules) * * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) /** * MPU Memory Access Attribute non-cacheable policy. */ #define ARM_MPU_CACHEP_NOCACHE 0U /** * MPU Memory Access Attribute write-back, write and read allocate policy. */ #define ARM_MPU_CACHEP_WB_WRA 1U /** * MPU Memory Access Attribute write-through, no write allocate policy. */ #define ARM_MPU_CACHEP_WT_NWA 2U /** * MPU Memory Access Attribute write-back, no write allocate policy. */ #define ARM_MPU_CACHEP_WB_NWA 3U /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { MPU->RNR = rnr; MPU->RASR = 0U; } /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; MPU->RASR = rasr; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; MPU->RBAR = rbar; MPU->RASR = rasr; } /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); table += MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES; } ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/mpu_armv8.h ================================================ /****************************************************************************** * @file mpu_armv8.h * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU * @version V5.1.0 * @date 08. March 2019 ******************************************************************************/ /* * Copyright (c) 2017-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H /** \brief Attribute for device memory (outer only) */ #define ARM_MPU_ATTR_DEVICE ( 0U ) /** \brief Attribute for non-cacheable, normal memory */ #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) /** \brief Attribute for normal memory (outer and inner) * \param NT Non-Transient: Set to 1 for non-transient data. * \param WB Write-Back: Set to 1 to use write-back update policy. * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. */ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGRE (2U) /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_GRE (3U) /** \brief Memory Attribute * \param O Outer memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes */ #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) /** \brief Normal memory non-shareable */ #define ARM_MPU_SH_NON (0U) /** \brief Normal memory outer shareable */ #define ARM_MPU_SH_OUTER (2U) /** \brief Normal memory inner shareable */ #define ARM_MPU_SH_INNER (3U) /** \brief Memory access permissions * \param RO Read-Only: Set to 1 for read-only memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory. */ #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) /** \brief Region Base Address Register value * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. * \param SH Defines the Shareability domain for this memory region. * \param RO Read-Only: Set to 1 for a read-only memory region. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ ((BASE & MPU_RBAR_BASE_Msk) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) /** \brief Region Limit Address Register value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR(LIMIT, IDX) \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) #if defined(MPU_RLAR_PXN_Pos) /** \brief Region Limit Address Register with PXN value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) #endif /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #ifdef MPU_NS /** Enable the Non-secure MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the Non-secure MPU. */ __STATIC_INLINE void ARM_MPU_Disable_NS(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #endif /** Set the memory attribute encoding to the given MPU. * \param mpu Pointer to the MPU to be configured. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) { const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } /** Set the memory attribute encoding. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU, idx, attr); } #ifdef MPU_NS /** Set the memory attribute encoding to the Non-secure MPU. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); } #endif /** Clear and disable the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) { mpu->RNR = rnr; mpu->RLAR = 0U; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU, rnr); } #ifdef MPU_NS /** Clear and disable the given Non-secure MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif /** Configure the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; mpu->RBAR = rbar; mpu->RLAR = rlar; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); } #ifdef MPU_NS /** Configure the given Non-secure MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table to the given MPU. * \param mpu Pointer to the MPU registers to be used. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); table += c; cnt -= c; rnrOffset = 0U; rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } /** Load the given number of MPU regions from a table. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } #ifdef MPU_NS /** Load the given number of MPU regions from a table to the Non-secure MPU. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } #endif #endif ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/Include/tz_context.h ================================================ /****************************************************************************** * @file tz_context.h * @brief Context Management for Armv8-M TrustZone * @version V1.0.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H #include #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); #endif // TZ_CONTEXT_H ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/CMSIS/LICENSE.txt ================================================ Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. 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See the License for the specific language governing permissions and limitations under the License. ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h ================================================ /** ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32_HAL_LEGACY #define STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose * @{ */ #define AES_FLAG_RDERR CRYP_FLAG_RDERR #define AES_FLAG_WRERR CRYP_FLAG_WRERR #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR #if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP #endif /* STM32H7 || STM32MP1 */ /** * @} */ /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ #define ADC_RESOLUTION12b ADC_RESOLUTION_12B #define ADC_RESOLUTION10b ADC_RESOLUTION_10B #define ADC_RESOLUTION8b ADC_RESOLUTION_8B #define ADC_RESOLUTION6b ADC_RESOLUTION_6B #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV #define REGULAR_GROUP ADC_REGULAR_GROUP #define INJECTED_GROUP ADC_INJECTED_GROUP #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP #define AWD_EVENT ADC_AWD_EVENT #define AWD1_EVENT ADC_AWD1_EVENT #define AWD2_EVENT ADC_AWD2_EVENT #define AWD3_EVENT ADC_AWD3_EVENT #define OVR_EVENT ADC_OVR_EVENT #define JQOVF_EVENT ADC_JQOVF_EVENT #define ALL_CHANNELS ADC_ALL_CHANNELS #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} */ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32L0) || defined(STM32L4) #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 #if defined(STM32L0) /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ /* to the second dedicated IO (only for COMP2). */ #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 #else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 #endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ #if defined(COMP_CSR_LOCK) #define COMP_FLAG_LOCK COMP_CSR_LOCK #elif defined(COMP_CSR_COMP1LOCK) #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK #elif defined(COMP_CSR_COMPxLOCK) #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK #endif #if defined(STM32L4) #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE #endif #if defined(STM32L0) #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER #else #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER #endif #endif /** * @} */ /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig /** * @} */ /** @defgroup CRC_Aliases CRC API aliases * @{ */ #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ /** * @} */ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE /** * @} */ /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose * @{ */ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 #define DAC_WAVE_NONE 0x00000000U #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #if defined(STM32G4) || defined(STM32H7) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif /** * @} */ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 #define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE #if defined(STM32L4) #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif #endif /* STM32L4 */ #if defined(STM32G0) #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM #endif #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE #define OBEX_PCROP OPTIONBYTE_PCROP #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD #define PAGESIZE FLASH_PAGE_SIZE #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS #define OB_WDG_SW OB_IWDG_SW #define OB_WDG_HW OB_IWDG_HW #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 #if defined(STM32G0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 #if defined(STM32G4) #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ /** * @} */ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 #endif /** * @} */ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** * @} */ /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose * @{ */ #define GET_GPIO_SOURCE GPIO_GET_INDEX #define GET_GPIO_INDEX GPIO_GET_INDEX #if defined(STM32F4) #define GPIO_AF12_SDMMC GPIO_AF12_SDIO #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO #endif #if defined(STM32F7) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32L4) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32H7) #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB */ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 /** * @} */ /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose * @{ */ /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ #if defined(STM32F3) /** @brief Constants defining available sources associated to external events. */ #define HRTIM_EVENTSRC_1 (0x00000000U) #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) #endif /* STM32F3 */ /** * @} */ /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose * @{ */ #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose * @{ */ #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose * @{ */ #define KR_KEY_RELOAD IWDG_KEY_RELOAD #define KR_KEY_ENABLE IWDG_KEY_ENABLE #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue /** * @} */ /** * @} */ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE /** * @} */ /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ #define NOR_StatusTypedef HAL_NOR_StatusTypeDef #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS #define NOR_ONGOING HAL_NOR_STATUS_ONGOING #define NOR_ERROR HAL_NOR_STATUS_ERROR #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT #define __NOR_WRITE NOR_WRITE #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose * @{ */ #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif #if defined(STM32L4) || defined(STM32L5) #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER #elif defined(STM32G4) #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED #endif /** * @} */ /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) #define I2S_IT_TXE I2S_IT_TXP #define I2S_IT_RXNE I2S_IT_RXP #define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} */ /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose * @{ */ /* Compact Flash-ATA registers description */ #define CF_DATA ATA_DATA #define CF_SECTOR_COUNT ATA_SECTOR_COUNT #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER #define CF_CYLINDER_LOW ATA_CYLINDER_LOW #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH #define CF_CARD_HEAD ATA_CARD_HEAD #define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT /** * @} */ /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK #endif /* STM32F7 */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ #if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP #endif /* STM32F7 || STM32H7 || STM32L0 */ /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN /** * @} */ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE #if defined(STM32H7) #define SPI_FLAG_TXE SPI_FLAG_TXP #define SPI_FLAG_RXNE SPI_FLAG_RXP #define SPI_IT_TXE SPI_IT_TXP #define SPI_IT_RXNE SPI_IT_RXP #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR #define TIM_DMABase_DIER TIM_DMABASE_DIER #define TIM_DMABase_SR TIM_DMABASE_SR #define TIM_DMABase_EGR TIM_DMABASE_EGR #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 #define TIM_DMABase_CCER TIM_DMABASE_CCER #define TIM_DMABase_CNT TIM_DMABASE_CNT #define TIM_DMABase_PSC TIM_DMABASE_PSC #define TIM_DMABase_ARR TIM_DMABASE_ARR #define TIM_DMABase_RCR TIM_DMABASE_RCR #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR #define TIM_DMABase_DCR TIM_DMABASE_DCR #define TIM_DMABase_DMAR TIM_DMABASE_DMAR #define TIM_DMABase_OR1 TIM_DMABASE_OR1 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 #define TIM_DMABase_OR TIM_DMABASE_OR #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS #if defined(STM32L0) #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO #endif #if defined(STM32F3) #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #endif #if defined(STM32H7) #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif /** * @} */ /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose * @{ */ #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING /** * @} */ /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose * @{ */ #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 #define __DIV_LPUART UART_DIV_LPUART #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK /** * @} */ /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE #define USARTNACK_ENABLED USART_NACK_ENABLE #define USARTNACK_DISABLED USART_NACK_DISABLE /** * @} */ /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose * @{ */ #define CFR_BASE WWDG_CFR_BASE /** * @} */ /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose * @{ */ #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) #define CAN_TXSTATUS_OK ((uint8_t)0x01U) #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) /** * @} */ /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ #define VLAN_TAG ETH_VLAN_TAG #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK #define ETH_MMCCR 0x00000100U #define ETH_MMCRIR 0x00000104U #define ETH_MMCTIR 0x00000108U #define ETH_MMCRIMR 0x0000010CU #define ETH_MMCTIMR 0x00000110U #define ETH_MMCTGFSCCR 0x0000014CU #define ETH_MMCTGFMSCCR 0x00000150U #define ETH_MMCTGFCR 0x00000168U #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ #define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ /** * @} */ /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR #define DCMI_IT_OVF DCMI_IT_OVR #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop /** * @} */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ || defined(STM32H7) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 #define CM_RGB888 DMA2D_INPUT_RGB888 #define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 #define CM_L8 DMA2D_INPUT_L8 #define CM_AL44 DMA2D_INPUT_AL44 #define CM_AL88 DMA2D_INPUT_AL88 #define CM_L4 DMA2D_INPUT_L4 #define CM_A8 DMA2D_INPUT_A8 #define CM_A4 DMA2D_INPUT_A4 /** * @} */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ /** * @} */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} */ /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose * @{ */ /** * @} */ #if !defined(STM32F2) /** @defgroup HASH_alias HASH API alias * @{ */ #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ /** * * @} */ #endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish /*HASH Algorithm Selection*/ #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) #else #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ /** * @} */ /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose * @{ */ #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program /** * @} */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ #if defined(STM32G0) #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB #define PMODE_BIT_NUMBER VOS_BIT_NUMBER #define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER #define PMODE_BitNumber PMODE_BIT_NUMBER #define EWUP_BitNumber EWUP_BIT_NUMBER #define FPDS_BitNumber FPDS_BIT_NUMBER #define ODEN_BitNumber ODEN_BIT_NUMBER #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL /** * @} */ /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ */ #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} */ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ /** * @} */ /* Exported macros ------------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose * @{ */ #define AES_IT_CC CRYP_IT_CC #define AES_IT_ERR CRYP_IT_ERR #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} */ /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER /** * @} */ /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ #define __ADC_ENABLE __HAL_ADC_ENABLE #define __ADC_DISABLE __HAL_ADC_DISABLE #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE #define __ADC_IS_ENABLED ADC_IS_ENABLE #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR_RK ADC_JSQR_RK #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER #define __HAL_ADC_SQR1 ADC_SQR1 #define __HAL_ADC_SMPR1 ADC_SMPR1 #define __HAL_ADC_SMPR2 ADC_SMPR2 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK #define __HAL_ADC_SQR2_RK ADC_SQR2_RK #define __HAL_ADC_SQR1_RK ADC_SQR1_RK #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ /** * @} */ /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE /** * @} */ /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 /** * @} */ /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32F3) #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP7_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP7_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ __HAL_COMP_COMP7_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) # endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) #endif #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE #if defined(STM32L0) || defined(STM32L4) /* Note: On these STM32 families, the only argument of this macro */ /* is COMP_FLAG_LOCK. */ /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ /* argument. */ #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) #endif /** * @} */ #if defined(STM32L0) || defined(STM32L4) /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ /** * @} */ #endif /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} */ /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose * @{ */ #define IS_WRPAREA IS_OB_WRPAREA #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM #define IS_TYPEERASE IS_FLASH_TYPEERASE #define IS_NBSECTORS IS_FLASH_NBSECTORS #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE /** * @} */ /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE #else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE #endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST #define __HAL_I2C_SPEED I2C_SPEED #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB #define __HAL_I2C_FREQRANGE I2C_FREQRANGE /** * @} */ /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET /** * @} */ /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ } while(0) #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET #if defined(STM32WB) #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED #define QSPI_IRQHandler QUADSPI_IRQHandler #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET #if defined(STM32H7) #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE /* alias define maintained for legacy */ #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED #if defined(STM32L1) #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #endif /* STM32L1 */ #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED #define Sdmmc1ClockSelection SdioClockSelection #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE #endif #if defined(STM32F7) || defined(STM32L4) #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif #if defined(STM32H7) #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() #endif #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK #define IS_RCC_HCLK_DIV IS_RCC_PCLK #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK #define RCC_IT_HSI14 RCC_IT_HSI14RDY #define RCC_IT_CSSLSE RCC_IT_LSECSS #define RCC_IT_CSSHSE RCC_IT_CSS #define RCC_PLLMUL_3 RCC_PLL_MUL3 #define RCC_PLLMUL_4 RCC_PLL_MUL4 #define RCC_PLLMUL_6 RCC_PLL_MUL6 #define RCC_PLLMUL_8 RCC_PLL_MUL8 #define RCC_PLLMUL_12 RCC_PLL_MUL12 #define RCC_PLLMUL_16 RCC_PLL_MUL16 #define RCC_PLLMUL_24 RCC_PLL_MUL24 #define RCC_PLLMUL_32 RCC_PLL_MUL32 #define RCC_PLLMUL_48 RCC_PLL_MUL48 #define RCC_PLLDIV_2 RCC_PLL_DIV2 #define RCC_PLLDIV_3 RCC_PLL_DIV3 #define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG #define RCC_MCO_NODIV RCC_MCODIV_1 #define RCC_MCO_DIV1 RCC_MCODIV_1 #define RCC_MCO_DIV2 RCC_MCODIV_2 #define RCC_MCO_DIV4 RCC_MCODIV_4 #define RCC_MCO_DIV8 RCC_MCODIV_8 #define RCC_MCO_DIV16 RCC_MCODIV_16 #define RCC_MCO_DIV32 RCC_MCODIV_32 #define RCC_MCO_DIV64 RCC_MCODIV_64 #define RCC_MCO_DIV128 RCC_MCODIV_128 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 #define HSION_BitNumber RCC_HSION_BIT_NUMBER #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER #define LSION_BitNumber RCC_LSION_BIT_NUMBER #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE #define CR_HSION_BB RCC_CR_HSION_BB #define CR_CSSON_BB RCC_CR_CSSON_BB #define CR_PLLON_BB RCC_CR_PLLON_BB #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB #define CR_MSION_BB RCC_CR_MSION_BB #define CSR_LSION_BB RCC_CSR_LSION_BB #define CSR_LSEON_BB RCC_CSR_LSEON_BB #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB #define CR_HSEON_BB RCC_CR_HSEON_BB #define CSR_RMVF_BB RCC_CSR_RMVF_BB #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 /** * @} */ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT #if defined (STM32F1) #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ defined (STM32H7) || \ defined (STM32L0) || defined (STM32L1) || \ defined (STM32WB) #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG #endif #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE /** * @} */ /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV #endif #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn #define SDMMC1_IRQHandler SDIO_IRQHandler #endif #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif #if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback #endif /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose * @{ */ #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED /** * @} */ /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SPI_1LINE_TX SPI_1LINE_TX #define __HAL_SPI_1LINE_RX SPI_1LINE_RX #define __HAL_SPI_RESET_CRC SPI_RESET_CRC /** * @} */ /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose * @{ */ #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT #define __USART_ENABLE __HAL_USART_ENABLE #define __USART_DISABLE __HAL_USART_DISABLE #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) #define USART_OVERSAMPLING_16 0x00000000U #define USART_OVERSAMPLING_8 USART_CR1_OVER8 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ ((__SAMPLING__) == USART_OVERSAMPLING_8)) #endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose * @{ */ #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo /** * @} */ /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 #define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** * @} */ /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose * @{ */ #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE #define SAI_STREOMODE SAI_STEREOMODE #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA #endif /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose * @{ */ #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} */ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE #endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32F7) #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE #endif /* STM32F7 */ /** * @} */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32_HAL_LEGACY */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal.h * @author MCD Application Team * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_H #define STM32G4xx_HAL_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_conf.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup HAL HAL * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ #define HAL_TICK_FREQ_10HZ 100U #define HAL_TICK_FREQ_100HZ 10U #define HAL_TICK_FREQ_1KHZ 1U #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ /** * @} */ /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants * @{ */ /** @defgroup SYSCFG_BootMode Boot Mode * @{ */ #define SYSCFG_BOOT_MAINFLASH 0x00000000U #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0 #if defined (FMC_BANK1) #define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1 #endif /* FMC_BANK1 */ #define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0) #if defined (QUADSPI) #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1) #endif /* QUADSPI */ /** * @} */ /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts * @{ */ #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ /** * @} */ /** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection * @{ */ #define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */ #define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */ #define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */ #define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */ #define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */ #define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */ #define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */ #define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */ #define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */ #define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */ #define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */ #define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */ #define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */ #define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */ #define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */ #define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */ #define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */ #define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */ #define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */ #define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */ #define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */ #define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */ #define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */ #define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */ #define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */ #define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */ #define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */ #define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */ #define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */ #define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */ #define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */ #define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */ /** * @} */ #if defined(VREFBUF) /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale * @{ */ #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */ #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */ #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */ /** * @} */ /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance * @{ */ #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ /** * @} */ #endif /* VREFBUF */ /** @defgroup SYSCFG_flags_definition Flags * @{ */ #define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */ #define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */ /** * @} */ /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO * @{ */ /** @brief Fast-mode Plus driving capability on a specific GPIO */ #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ /** * @} */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros * @{ */ /** @brief Freeze/Unfreeze Peripherals in Debug mode */ #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) #endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) #endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) #endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */ #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP) #define __HAL_DBGMCU_FREEZE_TIM20() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM20() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */ #if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP) #define __HAL_DBGMCU_FREEZE_HRTIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_HRTIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) #endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */ /** * @} */ /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros * @{ */ /** @brief Main Flash memory mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) /** @brief System Flash memory mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) /** @brief Embedded SRAM mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) #if defined (FMC_BANK1) /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) #endif /* FMC_BANK1 */ #if defined (QUADSPI) /** @brief QUADSPI mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) #endif /* QUADSPI */ /** * @brief Return the boot mode as configured by user. * @retval The boot mode as configured by user. The returned value can be one * of the following values: * @arg @ref SYSCFG_BOOT_MAINFLASH * @arg @ref SYSCFG_BOOT_SYSTEMFLASH * @arg @ref SYSCFG_BOOT_FMC (*) * @arg @ref SYSCFG_BOOT_QUADSPI (*) * @arg @ref SYSCFG_BOOT_SRAM * @note (*) availability depends on devices */ #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) /** @brief CCMSRAM page write protection enable macro * @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP * @note write protection can only be disabled by a system reset * @retval None */ /* Legacy define */ #define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE #define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\ SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\ }while(0) /** @brief CCMSRAM page write protection unlock prior to erase * @note Writing a wrong key reactivates the write protection */ #define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ SYSCFG->SKR = 0x53;\ }while(0) /** @brief CCMSRAM erase * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase */ #define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER) /** @brief Floating Point Unit interrupt enable/disable macros * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts */ #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ }while(0) #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ }while(0) /** @brief SYSCFG Break ECC lock. * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. * @note The selected configuration is locked and can be unlocked only by system reset. */ #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) /** @brief SYSCFG Break Cortex-M4 Lockup lock. * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. * @note The selected configuration is locked and can be unlocked only by system reset. */ #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) /** @brief SYSCFG Break PVD lock. * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. * @note The selected configuration is locked and can be unlocked only by system reset. */ #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) /** @brief SYSCFG Break SRAM parity lock. * Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input. * @note The selected configuration is locked and can be unlocked by system reset. */ #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) /** @brief Check SYSCFG flag is set or not. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag * @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ & (__FLAG__))!= 0U) ? 1U : 0U) /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. */ #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) /** @brief Fast-mode Plus driving capability enable/disable macros * @param __FASTMODEPLUS__: This parameter can be a value of : * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 */ #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0) #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros * @{ */ #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) #if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL) #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U) #elif (CCMSRAM_SIZE == 0x00002800UL) #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU)) #endif /* CCMSRAM_SIZE */ #if defined(VREFBUF) #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2)) #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) #endif /* VREFBUF */ #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) #elif defined(SYSCFG_FASTMODEPLUS_PB8) #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) #elif defined(SYSCFG_FASTMODEPLUS_PB9) #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) #else #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) #endif /* SYSCFG_FASTMODEPLUS_PB */ /** * @} */ /** @defgroup HAL_Private_Macros HAL Private Macros * @{ */ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ ((FREQ) == HAL_TICK_FREQ_100HZ) || \ ((FREQ) == HAL_TICK_FREQ_1KHZ)) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions * @{ */ /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ /* Initialization and Configuration functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); /** * @} */ /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions * @{ */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); uint32_t HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); uint32_t HAL_GetUIDw0(void); uint32_t HAL_GetUIDw1(void); uint32_t HAL_GetUIDw2(void); /** * @} */ /** @addtogroup HAL_Exported_Functions_Group3 * @{ */ /* DBGMCU Peripheral Control functions *****************************************/ void HAL_DBGMCU_EnableDBGSleepMode(void); void HAL_DBGMCU_DisableDBGSleepMode(void); void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} */ /* Exported variables ---------------------------------------------------------*/ /** @addtogroup HAL_Exported_Variables * @{ */ extern __IO uint32_t uwTick; extern uint32_t uwTickPrio; extern uint32_t uwTickFreq; /** * @} */ /** @addtogroup HAL_Exported_Functions_Group4 * @{ */ /* SYSCFG Control functions ****************************************************/ void HAL_SYSCFG_CCMSRAMErase(void); void HAL_SYSCFG_EnableMemorySwappingBank(void); void HAL_SYSCFG_DisableMemorySwappingBank(void); #if defined(VREFBUF) void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); void HAL_SYSCFG_DisableVREFBUF(void); #endif /* VREFBUF */ void HAL_SYSCFG_EnableIOSwitchBooster(void); void HAL_SYSCFG_DisableIOSwitchBooster(void); void HAL_SYSCFG_EnableIOSwitchVDD(void); void HAL_SYSCFG_DisableIOSwitchVDD(void); void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc.h * @author MCD Application Team * @brief Header file of ADC HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_ADC_H #define STM32G4xx_HAL_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /* Include low level driver */ #include "stm32g4xx_ll_adc.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ /** * @brief ADC group regular oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ } ADC_OversamplingTypeDef; /** * @brief Structure definition of ADC instance and ADC group regular. * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait. * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, * SamplingMode. * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled * without conversion on going on group regular. * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going * on groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock configuration is common to all ADC instances. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled. */ uint32_t Resolution; /*!< Configure the ADC resolution. This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). Refer to reference manual for alignments formats versus resolutions. This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula: DATA = DATA(raw) * (gain compensation coef) / 4096 "2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa Gain step is 1/4096 = 0.000244 Gain range is 0.0000 to 3.999756 This parameter value can be 0 Gain compensation will be disabled and coefficient set to 0 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value Note: Gain compensation when enabled is applied to all channels. */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). Scan direction is upward: from rank 1 to rank 'n'. This parameter can be a value of @ref ADC_Scan_mode */ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of @ref ADC_EOCSelection. */ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. This parameter is dependent on ScanConvMode: - sequencer configured to fully configurable: Number of ranks in the scan sequence is configurable using this parameter. Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). - sequencer configured to not fully configurable: Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_regular_external_trigger_source. Caution: external trigger source is common to all ADC instances. */ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. This parameter can be a value of @ref ADC_regular_sampling_mode */ FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in continuous mode (DMA transfer unlimited, whatever number of conversions). This parameter can be set to ENABLE or DISABLE. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear) Note: Error reporting with respect to the conversion mode: - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ } ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion * on going on regular group. * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on * regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t Rank; /*!< Specify the rank in the regular group sequencer. This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values. */ uint32_t SingleDiff; /*!< Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t OffsetNumber; /*!< Select the offset number This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).*/ FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ } ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC analog watchdog * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. * ADC state can be either: * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups. */ typedef struct { uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).*/ uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. Before setting flag or raising interrupt, analog watchdog can wait to have several consecutive out-of-window samples. This parameter allows to configure this number. This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ } ADC_AnalogWDGConfTypeDef; /** * @brief ADC group injected contexts queue configuration * @note Structure intended to be used only through structure "ADC_HandleTypeDef" */ typedef struct { uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ } ADC_InjectionConfigTypeDef; /** @defgroup ADC_States ADC States * @{ */ /** * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ /* States of ADC global scope */ #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration, ...) */ #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ /* States of ADC group regular */ #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ /** * @} */ /** * @brief ADC handle Structure definition */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) typedef struct __ADC_HandleTypeDef #else typedef struct #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ HAL_LockTypeDef Lock; /*!< ADC locking object */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief HAL ADC Callback ID enumeration definition */ typedef enum { HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ } HAL_ADC_CallbackIDTypeDef; /** * @brief HAL ADC Callback pointer definition */ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants ADC Exported Constants * @{ */ /** @defgroup ADC_Error_Code ADC Error Code * @{ */ #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...) */ #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock without prescaler */ #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock with prescaler division by 2 */ #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock with prescaler division by 4 */ #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ /** * @} */ /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution * @{ */ #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ /** * @} */ /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ /** @defgroup ADC_Scan_mode ADC sequencer scan mode * @{ */ #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ /** * @} */ /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source * @{ */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger software start */ #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. */ #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. */ #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare). */ #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare). */ #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. */ #define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare). */ #define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare). */ #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. */ #define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. */ #define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. */ #define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. */ #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. */ #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. */ #define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. */ #define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. */ #define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. */ #define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare). */ #define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare). */ #define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. */ #define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. */ #define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. */ #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. */ #define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. */ /** * @} */ /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger disabled (SW start)*/ #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ /** * @} */ /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode * @{ */ #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: Trigger rising edge = start sampling Trigger falling edge = stop sampling and start conversion */ /** * @} */ /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions * @{ */ #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ /** * @} */ /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} */ /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ /** * @} */ /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ /** * @} */ /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number * @{ */ /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ /* all ADC instances (refer to Reference Manual). */ #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ #define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< Internal channel Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ #define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< Internal channel Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda. On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availability */ #define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< Internal channel OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ #define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< Internal channel OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< Internal channel OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< Internal channel OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ #define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< Internal channel OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ #define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< Internal channel OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ #define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< Internal channel OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ /** * @} */ /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number * @{ */ #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ /** * @} */ /** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration * @{ */ #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one out-of-window sample to raise flag or interrupt */ #define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives out-of-window samples to raise flag or interrupt */ #define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives out-of-window samples to raise flag or interrupt */ #define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives out-of-window samples to raise flag or interrupt */ #define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives out-of-window samples to raise flag or interrupt */ #define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives out-of-window samples to raise flag or interrupt */ #define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives out-of-window samples to raise flag or interrupt */ #define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives out-of-window samples to raise flag or interrupt */ /** * @} */ /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode * @{ */ #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an injected group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\ | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular and injected groups single channel */ #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular group all channels */ #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected group all channels */ #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular and injected groups all channels */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio * @{ */ /** * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed * to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ /** * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling * conversion data) */ #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of OVS ratio are done from 1 trigger) */ #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of OVS ratio needs a trigger) */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular * @{ */ #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ /** * @} */ /** @defgroup ADC_Event_type ADC Event type * @{ */ /** * @note Analog watchdog 1 is available on all stm32 series * Analog watchdog 2 and 3 are not available on all series */ #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ /** * @} */ #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ /** * @} */ /** @defgroup ADC_flags_definition ADC flags definition * @{ */ #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ /** * @} */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief Return resolution bits in CFGR register RES[1:0] field. * @param __HANDLE__ ADC handle * @retval Value of bitfield RES in CFGR register. */ #define ADC_GET_RESOLUTION(__HANDLE__) \ (LL_ADC_GetResolution((__HANDLE__)->Instance)) /** * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Simultaneously clear and set specific bits of the handle State. * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Verify that a given value is aligned with the ADC resolution range. * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) /** * @brief Verify the length of the scheduled regular conversions group. * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) * or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. * @param NUMBER number of scheduled regular conversions in discontinuous mode. * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) * or RESET (NUMBER is null or too large) */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) /** * @brief Verify the ADC clock setting. * @param __ADC_CLOCK__ programmed ADC clock. * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) */ #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) /** * @brief Verify the ADC resolution setting. * @param __RESOLUTION__ programmed ADC resolution. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) /** * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) /** * @brief Verify the ADC converted data alignment. * @param __ALIGN__ programmed ADC converted data alignment. * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) */ #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) /** * @brief Verify the ADC gain compensation. * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient. * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid) */ #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL) /** * @brief Verify the ADC scan mode. * @param __SCAN_MODE__ programmed ADC scan mode. * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) */ #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) /** * @brief Verify the ADC edge trigger setting for regular group. * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) */ #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) /** * @brief Verify the ADC regular conversions external trigger. * @param __HANDLE__ ADC handle * @param __REGTRIG__ programmed ADC regular conversions external trigger. * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || \ ((__HANDLE__)->Instance == ADC4) || \ ((__HANDLE__)->Instance == ADC5)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || \ ((__HANDLE__)->Instance == ADC4) || \ ((__HANDLE__)->Instance == ADC5)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G471xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ (((__HANDLE__)->Instance == ADC3) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #endif /* STM32G4xx */ /** * @brief Verify the ADC regular conversions external trigger. * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) */ #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) /** * @brief Verify the ADC regular conversions check for converted data availability. * @param __EOC_SELECTION__ converted data availability check. * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) */ #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) /** * @brief Verify the ADC regular conversions overrun handling. * @param __OVR__ ADC regular conversions overrun handling. * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) */ #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) /** * @brief Verify the ADC conversions sampling time. * @param __TIME__ ADC conversions sampling time. * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) */ #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) /** * @brief Verify the ADC regular channel setting. * @param __CHANNEL__ programmed ADC regular channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup ADC_Private_Constants ADC Private Constants * @{ */ /* Fixed timeout values for ADC conversion (including sampling time) */ /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ /* Maximum conversion time is 12.5 + Maximum sampling time */ /* or 12.5 + 640.5 = 653 ADC clock cycles */ /* Minimum ADC Clock frequency is 0.14 MHz */ /* Maximum conversion time is */ /* 653 / 0.14 MHz = 4.66 ms */ #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros * @{ */ /* Macro for internal HAL driver usage, and possibly can be used into code of */ /* final user. */ /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. * @{ */ /** @brief Reset ADC handle state. * @param __HANDLE__ ADC handle * @retval None */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ do{ \ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @brief Enable ADC interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be one of the following values: * @arg @ref ADC_IT_RDY ADC Ready interrupt source * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable ADC interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be one of the following values: * @arg @ref ADC_IT_RDY ADC Ready interrupt source * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC interrupt source to check * This parameter can be one of the following values: * @arg @ref ADC_IT_RDY ADC Ready interrupt source * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Check whether the specified ADC flag is set or not. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: * @arg @ref ADC_FLAG_RDY ADC Ready flag * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_OVR ADC overrun flag * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) /** * @brief Clear the specified ADC flag. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: * @arg @ref ADC_FLAG_RDY ADC Ready flag * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_OVR ADC overrun flag * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ (((__HANDLE__)->Instance->ISR) = (__FLAG__)) /** * @} */ /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro * @{ */ /** * @brief Helper macro to get ADC channel number in decimal format * from literals ADC_CHANNEL_x. * @note Example: * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) * will return decimal number "4". * @note The input can be a value from functions where a channel * number is returned, either defined with number * or with bitfield (only one bit must be set). * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 */ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) /** * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x * from number in decimal format. * @note Example: * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "ADC_CHANNEL_4". * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) * to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) /** * @brief Helper macro to determine whether the selected channel * corresponds to literal definitions of driver. * @note The different literal definitions of ADC channels are: * - ADC internal channel: * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... * - ADC external channel (channel connected to a GPIO pin): * ADC_CHANNEL_1, ADC_CHANNEL_2, ... * @note The channel parameter must be a value defined from literal * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, * ADC_CHANNEL_TEMPSENSOR, ...), * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), * must not be a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel * connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) /** * @brief Helper macro to convert a channel defined from parameter * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, * ADC_CHANNEL_TEMPSENSOR, ...), * to its equivalent parameter definition of a ADC external channel * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). * @note The channel parameter can be, additionally to a value * defined from parameter definition of a ADC internal channel * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), * a value defined from parameter definition of * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) * or a value from functions where a channel number is returned * from ADC registers. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 * @arg @ref ADC_CHANNEL_2 * @arg @ref ADC_CHANNEL_3 * @arg @ref ADC_CHANNEL_4 * @arg @ref ADC_CHANNEL_5 * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 */ #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) /** * @brief Helper macro to determine whether the internal channel * selected is available on the ADC instance selected. * @note The channel parameter must be a value defined from parameter * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, * ADC_CHANNEL_TEMPSENSOR, ...), * must not be a value defined from parameter definition of * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) * or a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __ADC_INSTANCE__ ADC instance * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Helper macro to get the ADC multimode conversion data of ADC master * or ADC slave from raw value with both ADC conversion data concatenated. * @note This macro is intended to be used when multimode transfer by DMA * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). * In this case the transferred data need to processed with this macro * to separate the conversion data of ADC master and ADC slave. * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_MASTER * @arg @ref LL_ADC_MULTI_SLAVE * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance * to which is belonging the selected ADC instance. * @note ADC common register instance can be used for: * - Set parameters common to several ADC instances * - Multimode (for devices with several ADC instances) * Refer to functions having argument "ADCxy_COMMON" as parameter. * @param __ADCx__ ADC instance * @retval ADC common register instance */ #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ __LL_ADC_COMMON_INSTANCE((__ADCx__)) /** * @brief Helper macro to check if all ADC instances sharing the same * ADC common instance are disabled. * @note This check is required by functions with setting conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * Refer to functions having argument "ADCxy_COMMON" as parameter. * @note On devices with only 1 ADC common instance, parameter of this macro * is useless and can be ignored (parameter kept for compatibility * with devices featuring several ADC common instances). * @param __ADCXY_COMMON__ ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Value "0" if all ADC instances sharing the same ADC common instance * are disabled. * Value "1" if at least one ADC instance sharing the same ADC common instance * is enabled. */ #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) /** * @brief Helper macro to define the ADC conversion data full-scale digital * value corresponding to the selected ADC resolution. * @note ADC conversion data full-scale corresponds to voltage range * determined by analog voltage references Vref+ and Vref- * (refer to reference manual). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval ADC conversion data full-scale digital value */ #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval ADC conversion data to the requested resolution */ #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ (__ADC_RESOLUTION_CURRENT__),\ (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ (__ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value) * in differential ended mode. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ (__ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage * reference VrefInt. * @note Computation is using VrefInt calibration value * stored in system memory for each device during production. * @note This voltage depends on user board environment: voltage level * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval Analog reference voltage (unit: mV) */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor calibration values * stored in system memory for each device during production. * @note Calculation formula: * Temperature = ((TS_ADC_DATA - TS_CAL1) * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * Avg_Slope = (TS_CAL2 - TS_CAL1) * / (TS_CAL2_TEMP - TS_CAL1_TEMP) * TS_CAL1 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL1 (calibrated in factory) * TS_CAL2 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL2 (calibrated in factory) * Caution: Calculation relevancy under reserve that calibration * parameters are correct (address and data). * To calculate temperature using temperature sensor * datasheet typical values (generic values less, therefore * less accurate than calibrated values), * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal * temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature * sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) */ #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ (__TEMPSENSOR_ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor typical values * (refer to device datasheet). * @note Calculation formula: * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) * / Avg_Slope + CALx_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * (unit: digital value) * Avg_Slope = temperature sensor slope * (unit: uV/Degree Celsius) * TS_TYP_CALx_VOLT = temperature sensor digital value at * temperature CALx_TEMP (unit: mV) * Caution: Calculation relevancy under reserve the temperature sensor * of the current device has characteristics in line with * datasheet typical values. * If temperature sensor calibration values are available on * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), * temperature calculation will be more accurate using * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). * On STM32G4, refer to device datasheet parameter "Avg_Slope". * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) */ #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ __TEMPSENSOR_TYP_CALX_V__,\ __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ (__TEMPSENSOR_TYP_CALX_V__),\ (__TEMPSENSOR_CALX_TEMP__),\ (__VREFANALOG_VOLTAGE__),\ (__TEMPSENSOR_ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @} */ /** * @} */ /* Include ADC HAL Extended module */ #include "stm32g4xx_hal_adc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_Exported_Functions * @{ */ /** @addtogroup ADC_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @{ */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup ADC_Exported_Functions_Group2 * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); /* Non-blocking mode: DMA */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC sampling control */ HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); /** * @} */ /* Peripheral State functions *************************************************/ /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @addtogroup ADC_Private_Functions ADC Private Functions * @{ */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_ADC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc_ex.h * @author MCD Application Team * @brief Header file of ADC HAL extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_ADC_EX_H #define STM32G4xx_HAL_ADC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup ADCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types * @{ */ /** * @brief ADC Injected Conversion Oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ } ADC_InjOversamplingTypeDef; /** * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, * InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, * InjectedDiscontinuousConvMode, * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, * InjecOversamplingMode, InjecOversampling. * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter * 'InjectedSingleDiff') * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled * without conversion on going on injected group. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', * 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and * injected groups. * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', * 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going * on ADC groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt, ...), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values. */ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_injected_external_trigger_source. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADC_injected_external_trigger_edge. If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared).*/ } ADC_InjectionConfTypeDef; #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state * (both Master and Slave ADCs). * Both Master and Slave ADCs must be disabled. */ typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ } ADC_MultiModeTypeDef; #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants * @{ */ /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source * @{ */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< ADC group injected conversion trigger software start */ #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. */ #define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. */ #define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. */ #define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. */ #define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. */ #define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. */ #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. */ #define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. */ /** * @} */ /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions trigger disabled (SW start)*/ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger polarity set to rising edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger polarity set to falling edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger polarity set to both rising and falling edges */ /** * @} */ /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended */ #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential */ /** * @} */ /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number * @{ */ #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ /** * @} */ /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign * @{ */ #define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ #define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ /** * @} */ /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ /** * @} */ #if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode * @{ */ #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution * @{ */ #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** * @} */ /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ /** * @} */ /** * @} */ #endif /* ADC_MULTIMODE_SUPPORT */ /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups * @{ */ #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices) */ #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ /** * @} */ /** @defgroup ADC_CFGR_fields ADCx CFGR fields * @{ */ #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) /** * @} */ /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields * @{ */ #if defined(ADC_SMPR1_SMPPLUS) #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) #else #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ ADC_SMPR1_SMP0) #endif /* ADC_SMPR1_SMPPLUS */ /** * @} */ /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields * @{ */ /* ADC_CFGR fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */ #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ #if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros * @{ */ /** @brief Force ADC instance in multimode mode independent (multimode disable). * @note This macro must be used only in case of transition from multimode * to mode independent and in case of unknown previous state, * to ensure ADC configuration is in mode independent. * @note Standard way of multimode configuration change is done from * HAL ADC handle of ADC master using function * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". * Usage of this macro is not the Standard way of multimode * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases * mentioned above. * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) /** * @} */ #endif /* ADC_MULTIMODE_SUPPORT */ /* Private macros ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief Test if conversion trigger of injected group is software start * or external trigger. * @param __HANDLE__ ADC handle. * @retval SET (software start) or RESET (external trigger). */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) /** * @brief Check whether or not ADC is independent. * @param __HANDLE__ ADC handle. * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC5) \ )? \ SET \ : \ RESET \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC3) \ )? \ SET \ : \ RESET \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Set the selected injected Channel rank. * @param __CHANNELNB__ Channel number. * @param __RANKNB__ Rank number. * @retval None */ #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \ ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \ << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. * @retval None */ #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \ ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) /** * @brief Configure ADC discontinuous conversion mode for injected group * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. * @retval None */ #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \ ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) /** * @brief Configure ADC discontinuous conversion mode for regular group * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. * @retval None */ #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \ ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) /** * @brief Configure the number of discontinuous conversions for regular group. * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. * @retval None */ #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \ (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) /** * @brief Configure the ADC auto delay mode. * @param __AUTOWAIT__ Auto delay bit enable or disable. * @retval None */ #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) /** * @brief Configure ADC continuous conversion mode. * @param __CONTINUOUS_MODE__ Continuous mode. * @retval None */ #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) /** * @brief Configure the ADC DMA continuous request. * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None */ #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Configure the ADC DMA continuous request for ADC multimode. * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None */ #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Shift the offset with respect to the selected ADC resolution. * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). * @param __HANDLE__ ADC handle * @param __OFFSET__ Value to be shifted * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). * @param __HANDLE__ ADC handle * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. * @note Thresholds have to be left-aligned on bit 7. * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). * If resolution 8 bits, no shift. * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). * @param __HANDLE__ ADC handle * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ ((__THRESHOLD__) << 2UL) \ ) /** * @brief Clear Common Control Register. * @param __HANDLE__ ADC handle. * @retval None */ #if defined(ADC_MULTIMODE_SUPPORT) #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATSEL | \ ADC_CCR_VSENSESEL | \ ADC_CCR_VREFEN | \ ADC_CCR_MDMA | \ ADC_CCR_DMACFG | \ ADC_CCR_DELAY | \ ADC_CCR_DUAL) #endif /* ADC_MULTIMODE_SUPPORT */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. * @param __HANDLE_SLAVE__ ADC slave handle. * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is * set to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ ((__HANDLE_SLAVE__)->Instance = ADC2) \ : \ ((__HANDLE_MASTER__)->Instance == ADC3) ? \ ((__HANDLE_SLAVE__)->Instance = ADC4) \ : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. * @param __HANDLE_SLAVE__ ADC slave handle. * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set * to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ ((__HANDLE_SLAVE__)->Instance = ADC2) \ : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) #endif /* STM32G4xx */ /** * @brief Verify the ADC instance connected to the temperature sensor. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \ ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC instance connected to the battery voltage VBAT. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \ ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /* STM32G4xx */ /** * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) /** * @brief Verify the length of scheduled injected conversions group. * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) * or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) /** * @brief Calibration factor size verification (7 bits maximum). * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) */ #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) /** * @brief Verify the ADC channel setting. * @param __HANDLE__ ADC handle. * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC4) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC5) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #elif defined(STM32G471xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC channel setting in differential mode. * @param __HANDLE__ ADC handle. * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_14)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) || \ ((((__HANDLE__)->Instance) == ADC4) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) || \ ((((__HANDLE__)->Instance) == ADC5) && \ (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) #elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_14)) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_14)) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13))) ) #endif /* STM32G4xx */ /** * @brief Verify the ADC single-ended input or differential mode setting. * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) */ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) /** * @brief Verify the ADC offset management setting. * @param __OFFSET_NUMBER__ ADC offset management. * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) */ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) /** * @brief Verify the ADC offset sign setting. * @param __OFFSET_SIGN__ ADC offset sign. * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) */ #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) /** * @brief Verify the ADC injected channel setting. * @param __CHANNEL__ programmed ADC injected channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) /** * @brief Verify the ADC injected conversions external trigger. * @param __HANDLE__ ADC handle. * @param __INJTRIG__ programmed ADC injected conversions external trigger. * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || \ ((__HANDLE__)->Instance == ADC4) || \ ((__HANDLE__)->Instance == ADC5)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || \ ((__HANDLE__)->Instance == ADC4) || \ ((__HANDLE__)->Instance == ADC5)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G471xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || \ ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ (((__HANDLE__)->Instance == ADC3) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32G4xx */ /** * @brief Verify the ADC edge trigger setting for injected group. * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) */ #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Verify the ADC multimode setting. * @param __MODE__ programmed ADC multimode setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ ((__MODE__) == ADC_DUALMODE_INTERL) || \ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) /** * @brief Verify the ADC multimode DMA access setting. * @param __MODE__ programmed ADC multimode DMA access setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) /** * @brief Verify the ADC multimode delay setting. * @param __DELAY__ programmed ADC multimode delay setting. * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) */ #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Verify the ADC analog watchdog setting. * @param __WATCHDOG__ programmed ADC analog watchdog setting. * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) /** * @brief Verify the ADC analog watchdog mode setting. * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) /** * @brief Verify the ADC analog watchdog filtering setting. * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \ (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) /** * @brief Verify the ADC conversion (regular or injected or both). * @param __CONVERSION__ ADC conversion group. * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) */ #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) /** * @brief Verify the ADC event type. * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ ((__EVENT__) == ADC_AWD_EVENT) || \ ((__EVENT__) == ADC_AWD2_EVENT) || \ ((__EVENT__) == ADC_AWD3_EVENT) || \ ((__EVENT__) == ADC_OVR_EVENT) || \ ((__EVENT__) == ADC_JQOVF_EVENT) ) /** * @brief Verify the ADC oversampling ratio. * @param __RATIO__ programmed ADC oversampling ratio. * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) */ #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) /** * @brief Verify the ADC oversampling shift. * @param __SHIFT__ programmed ADC oversampling shift. * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) */ #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) /** * @brief Verify the ADC oversampling triggered mode. * @param __MODE__ programmed ADC oversampling triggered mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) /** * @brief Verify the ADC oversampling regular conversion resumed or continued mode. * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) /** * @brief Verify the DFSDM mode configuration. * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) */ #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) /** * @brief Return the DFSDM configuration mode. * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * For this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval DFSDM configuration mode */ #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ */ /** @addtogroup ADCEx_Exported_Functions_Group1 * @{ */ /* IO operation functions *****************************************************/ /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); /* ADC group regular conversions stop */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @addtogroup ADCEx_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *pConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode); #endif /* ADC_MULTIMODE_SUPPORT */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_ADC_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_cortex.h * @author MCD Application Team * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_CORTEX_H #define __STM32G4xx_HAL_CORTEX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup CORTEX CORTEX * @brief CORTEX HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types CORTEX Exported Types * @{ */ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @brief MPU Region initialization structure * @{ */ typedef struct { uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority, 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority, 3 bits for subpriority */ #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority, 2 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority, 1 bit for subpriority */ #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority, 0 bit for subpriority */ /** * @} */ /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U #define SYSTICK_CLKSOURCE_HCLK 0x00000004U /** * @} */ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /** * @} */ /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ #define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_DISABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) /** * @} */ /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels * @{ */ #define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL2 ((uint8_t)0x02) #define MPU_TEX_LEVEL4 ((uint8_t)0x04) /** * @} */ /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) /** * @} */ /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} */ /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ #define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions * @{ */ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @{ */ /* Initialization and Configuration functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** * @} */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions * @brief Cortex control functions * @{ */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ ((GROUP) == NVIC_PRIORITYGROUP_1) || \ ((GROUP) == NVIC_PRIORITYGROUP_2) || \ ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) #if (__MPU_PRESENT == 1) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ ((TYPE) == MPU_TEX_LEVEL1) || \ ((TYPE) == MPU_TEX_LEVEL2) || \ ((TYPE) == MPU_TEX_LEVEL4)) #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ ((TYPE) == MPU_REGION_FULL_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RO) || \ ((TYPE) == MPU_REGION_PRIV_RO_URO)) #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ ((NUMBER) == MPU_REGION_NUMBER1) || \ ((NUMBER) == MPU_REGION_NUMBER2) || \ ((NUMBER) == MPU_REGION_NUMBER3) || \ ((NUMBER) == MPU_REGION_NUMBER4) || \ ((NUMBER) == MPU_REGION_NUMBER5) || \ ((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER7)) #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ ((SIZE) == MPU_REGION_SIZE_64B) || \ ((SIZE) == MPU_REGION_SIZE_128B) || \ ((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \ ((SIZE) == MPU_REGION_SIZE_1KB) || \ ((SIZE) == MPU_REGION_SIZE_2KB) || \ ((SIZE) == MPU_REGION_SIZE_4KB) || \ ((SIZE) == MPU_REGION_SIZE_8KB) || \ ((SIZE) == MPU_REGION_SIZE_16KB) || \ ((SIZE) == MPU_REGION_SIZE_32KB) || \ ((SIZE) == MPU_REGION_SIZE_64KB) || \ ((SIZE) == MPU_REGION_SIZE_128KB) || \ ((SIZE) == MPU_REGION_SIZE_256KB) || \ ((SIZE) == MPU_REGION_SIZE_512KB) || \ ((SIZE) == MPU_REGION_SIZE_1MB) || \ ((SIZE) == MPU_REGION_SIZE_2MB) || \ ((SIZE) == MPU_REGION_SIZE_4MB) || \ ((SIZE) == MPU_REGION_SIZE_8MB) || \ ((SIZE) == MPU_REGION_SIZE_16MB) || \ ((SIZE) == MPU_REGION_SIZE_32MB) || \ ((SIZE) == MPU_REGION_SIZE_64MB) || \ ((SIZE) == MPU_REGION_SIZE_128MB) || \ ((SIZE) == MPU_REGION_SIZE_256MB) || \ ((SIZE) == MPU_REGION_SIZE_512MB) || \ ((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #endif /* __MPU_PRESENT */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_HAL_CORTEX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac.h * @author MCD Application Team * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_DAC_H #define STM32G4xx_HAL_DAC_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @addtogroup DAC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Types DAC Exported Types * @{ */ /** * @brief HAL State structures definition */ typedef enum { HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ } HAL_DAC_StateTypeDef; /** * @brief DAC handle Structure definition */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) typedef struct __DAC_HandleTypeDef #else typedef struct #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ { DAC_TypeDef *Instance; /*!< Register base address */ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ HAL_LockTypeDef Lock; /*!< DAC locking object */ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; /** * @brief DAC Configuration sample and hold Channel structure definition */ typedef struct { uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ } DAC_SampleAndHoldConfTypeDef; /** * @brief DAC Configuration regular Channel structure definition */ typedef struct { uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode This parameter can be a value of @ref DAC_HighFrequency */ FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel. This parameter can be ENABLE or DISABLE */ FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel. This parameter can be ENABLE or DISABLE */ uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. This parameter can be a value of @ref DAC_SampleAndHold */ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection. Note: In case of sawtooth wave generation, this trigger corresponds to the reset trigger. */ uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection. Note: In case of sawtooth wave generation, this trigger corresponds to the step trigger.*/ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral. This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode This parameter must be a value of @ref DAC_UserTrimming DAC_UserTrimming is either factory or user trimming */ uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ } DAC_ChannelConfTypeDef; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief HAL DAC Callback ID enumeration definition */ typedef enum { HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ } HAL_DAC_CallbackIDTypeDef; /** * @brief HAL DAC Callback pointer definition */ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DAC_Exported_Constants DAC Exported Constants * @{ */ /** @defgroup DAC_Error_Code DAC Error Code * @{ */ #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup DAC_trigger_selection DAC trigger selection * @{ */ #define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */ #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */ #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */ #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */ #define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */ #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */ #define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ /** * @} */ /** @defgroup DAC_output_buffer DAC output buffer * @{ */ #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) /** * @} */ /** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ #define DAC_CHANNEL_1 0x00000000U #define DAC_CHANNEL_2 0x00000010U /** * @} */ /** @defgroup DAC_data_alignment DAC data alignment * @{ */ #define DAC_ALIGN_12B_R 0x00000000U #define DAC_ALIGN_12B_L 0x00000004U #define DAC_ALIGN_8B_R 0x00000008U /** * @} */ /** @defgroup DAC_flags_definition DAC flags definition * @{ */ #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) #define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) #define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /** * @} */ /** @defgroup DAC_IT_definition DAC IT definition * @{ */ #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) /** * @} */ /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ #define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) #define DAC_CHIPCONNECT_INTERNAL (1UL << 1) #define DAC_CHIPCONNECT_BOTH (1UL << 2) /** * @} */ /** @defgroup DAC_UserTrimming DAC User Trimming * @{ */ #define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */ #define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */ /** * @} */ /** @defgroup DAC_SampleAndHold DAC power mode * @{ */ #define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL) #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) /** * @} */ /** @defgroup DAC_HighFrequency DAC high frequency interface mode * @{ */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */ /** * @} */ /** * @} */ /* Delay for DAC channel voltage settling time from DAC channel startup */ /* (transition from disable to enable). */ /* Note: DAC channel startup time depends on board application environment: */ /* impedance connected to DAC channel output. */ /* The delay below is specified under conditions: */ /* - voltage maximum transition (lowest to highest value) */ /* - until voltage reaches final value +-1LSB */ /* - DAC channel output buffer enabled */ /* - load impedance of 5kOhm (min), 50pF (max) */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ #define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Macros DAC Exported Macros * @{ */ /** @brief Reset DAC handle state. * @param __HANDLE__ specifies the DAC handle. * @retval None */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** @brief Enable the DAC channel. * @param __HANDLE__ specifies the DAC handle. * @param __DAC_Channel__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Disable the DAC channel. * @param __HANDLE__ specifies the DAC handle * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Set DHR12R1 alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) /** @brief Enable the DAC interrupt. * @param __HANDLE__ specifies the DAC handle * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt. * @param __HANDLE__ specifies the DAC handle * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified DAC interrupt source is enabled or not. * @param __HANDLE__ DAC handle * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of interruption (SET or RESET) */ #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. * @param __HANDLE__ specifies the DAC handle. * @param __FLAG__ specifies the DAC flag to get. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) * @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag * @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. * @param __HANDLE__ specifies the DAC handle. * @param __FLAG__ specifies the DAC flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup DAC_Private_Macros DAC Private Macros * @{ */ #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((DACX) == DAC2) ? \ ((CHANNEL) == DAC_CHANNEL_1) \ : \ (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2))) #else #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) #endif /* STM32G474xx || STM32G484xx || STM32G473xx */ #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL) /** * @} */ /* Include DAC HAL Extended module */ #include "stm32g4xx_hal_dac_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DAC_Exported_Functions * @{ */ /** @addtogroup DAC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /** * @} */ /** @addtogroup DAC_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* DAC callback registering/unregistering */ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup DAC_Exported_Functions_Group3 * @{ */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ /** @addtogroup DAC_Exported_Functions_Group4 * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); /** * @} */ /** * @} */ /** @defgroup DAC_Private_Functions DAC Private Functions * @{ */ void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_DAC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac_ex.h * @author MCD Application Team * @brief Header file of DAC HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_DAC_EX_H #define STM32G4xx_HAL_DAC_EX_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @addtogroup DACEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief HAL State structures definition */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ */ /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude * @{ */ #define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ #define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */ #define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ #define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ #define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ #define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ #define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ #define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ #define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ #define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ #define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ #define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ #define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ /** * @} */ /** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode * @{ */ #define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */ #define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup DACEx_Private_Macros DACEx Private Macros * @{ */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_DAC_TRIGGER(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG1) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG2) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG3) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG4) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG5) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG6) || \ (((DACX) == DAC1) && \ (((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \ ) || \ (((DACX) == DAC2) && \ (((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG02)) \ ) || \ (((DACX) == DAC3) && \ (((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG03)) \ ) || \ (((DACX) == DAC4) && \ (((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \ ) \ ) #else #define IS_DAC_TRIGGER(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ (((DACX) == DAC3) ? \ ((TRIGGER) == DAC_TRIGGER_T1_TRGO) \ : ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) #endif /* STM32G474xx || STM32G484xx */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_DAC_TRIGGER2(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG1) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG2) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG3) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG4) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG5) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG6) || \ (((DACX) == DAC1) && \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) || \ (((DACX) == DAC2) && \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) || \ (((DACX) == DAC3) && \ ((TRIGGER) == DAC_TRIGGER_T1_TRGO) \ ) || \ (((DACX) == DAC4) && \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) #else #define IS_DAC_TRIGGER2(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ (((DACX) == DAC3) ? \ ((TRIGGER) == DAC_TRIGGER_T1_TRGO) \ :((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) #endif /* STM32G474xx || STM32G484xx */ #define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC)) #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU) #define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU) #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \ ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \ ((CONNECT) == DAC_CHIPCONNECT_BOTH)) #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \ ((TRIMMING) == DAC_TRIMMING_USER)) #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) #define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \ ((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT)) #define IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL) #define IS_DAC_STEP_DATA(DATA) ((DATA) <= 0x0000FFFFUL) /** * @} */ /* Exported functions --------------------------------------------------------*/ /* Extended features functions ***********************************************/ /** @addtogroup DACEx_Exported_Functions * @{ */ /** @addtogroup DACEx_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData); HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); /** * @} */ /** @addtogroup DACEx_Exported_Functions_Group3 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel); /** * @} */ /** * @} */ /** @addtogroup DACEx_Private_Functions * @{ */ /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */ /* are called by HAL_DAC_Start_DMA */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_DAC_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_def.h * @author MCD Application Team * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_DEF #define __STM32G4xx_HAL_DEF #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx.h" #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ #include /* Exported types ------------------------------------------------------------*/ /** * @brief HAL Status structures definition */ typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** * @brief HAL Lock structures definition */ typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macros -----------------------------------------------------------*/ #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ do{ \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while(0) #if !defined(UNUSED) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ #endif /* UNUSED */ /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * In this later function, when the Handle's "State" field is set to 0, it will execute the function * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) #if (USE_RTOS == 1U) /* Reserved for future use */ #error " USE_RTOS should be 0 in the current HAL release " #else #define __HAL_LOCK(__HANDLE__) \ do{ \ if((__HANDLE__)->Lock == HAL_LOCKED) \ { \ return HAL_BUSY; \ } \ else \ { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ }while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do{ \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ }while (0U) #endif /* USE_RTOS */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #ifndef __weak #define __weak __attribute__((weak)) #endif #ifndef __packed #define __packed __attribute__((packed)) #endif #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ #ifndef __packed #define __packed __attribute__((__packed__)) #endif /* __packed */ #endif /* __GNUC__ */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4U))) #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4U) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ /** * @brief __RAM_FUNC definition */ #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler V4/V5 and V6 -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' dialog. */ #define __RAM_FUNC #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc #elif defined ( __GNUC__ ) /* GNU Compiler ------------ RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC __attribute__((section(".RamFunc"))) #endif /* __CC_ARM */ /** * @brief __NOINLINE definition */ #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM V4/V5 and V6 & GNU Compiler ------------------------------- */ #define __NOINLINE __attribute__ ( (noinline) ) #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- */ #define __NOINLINE _Pragma("optimize = no_inline") #endif /* __CC_ARM || __GNUC__ */ #ifdef __cplusplus } #endif #endif /* ___STM32G4xx_HAL_DEF */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma.h * @author MCD Application Team * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_DMA_H #define __STM32G4xx_HAL_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ /** * @brief DMA Configuration Structure definition */ typedef struct { uint32_t Request; /*!< Specifies the request selected for the specified channel. This parameter can be a value of @ref DMA_request */ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; /** * @brief HAL DMA State structures definition */ typedef enum { HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ } HAL_DMA_StateTypeDef; /** * @brief HAL DMA Error Code structure definition */ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ } HAL_DMA_LevelCompleteTypeDef; /** * @brief HAL DMA Callback ID structure definition */ typedef enum { HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ } HAL_DMA_CallbackIDTypeDef; /** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_InitTypeDef Init; /*!< DMA communication parameters */ HAL_LockTypeDef Lock; /*!< DMA locking object */ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ void *Parent; /*!< Parent object state */ void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ uint32_t ChannelIndex; /*!< DMA Channel Index */ DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ } DMA_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ /** @defgroup DMA_Error_Code DMA Error Code * @{ */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ /** * @} */ /** @defgroup DMA_request DMA request * @{ */ #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ #define DMA_REQUEST_GENERATOR0 1U #define DMA_REQUEST_GENERATOR1 2U #define DMA_REQUEST_GENERATOR2 3U #define DMA_REQUEST_GENERATOR3 4U #define DMA_REQUEST_ADC1 5U #define DMA_REQUEST_DAC1_CHANNEL1 6U #define DMA_REQUEST_DAC1_CHANNEL2 7U #define DMA_REQUEST_TIM6_UP 8U #define DMA_REQUEST_TIM7_UP 9U #define DMA_REQUEST_SPI1_RX 10U #define DMA_REQUEST_SPI1_TX 11U #define DMA_REQUEST_SPI2_RX 12U #define DMA_REQUEST_SPI2_TX 13U #define DMA_REQUEST_SPI3_RX 14U #define DMA_REQUEST_SPI3_TX 15U #define DMA_REQUEST_I2C1_RX 16U #define DMA_REQUEST_I2C1_TX 17U #define DMA_REQUEST_I2C2_RX 18U #define DMA_REQUEST_I2C2_TX 19U #define DMA_REQUEST_I2C3_RX 20U #define DMA_REQUEST_I2C3_TX 21U #if defined (I2C4) #define DMA_REQUEST_I2C4_RX 22U #define DMA_REQUEST_I2C4_TX 23U #endif /* I2C4 */ #define DMA_REQUEST_USART1_RX 24U #define DMA_REQUEST_USART1_TX 25U #define DMA_REQUEST_USART2_RX 26U #define DMA_REQUEST_USART2_TX 27U #define DMA_REQUEST_USART3_RX 28U #define DMA_REQUEST_USART3_TX 29U #define DMA_REQUEST_UART4_RX 30U #define DMA_REQUEST_UART4_TX 31U #if defined (UART5) #define DMA_REQUEST_UART5_RX 32U #define DMA_REQUEST_UART5_TX 33U #endif /* UART5 */ #define DMA_REQUEST_LPUART1_RX 34U #define DMA_REQUEST_LPUART1_TX 35U #define DMA_REQUEST_ADC2 36U #if defined (ADC3) #define DMA_REQUEST_ADC3 37U #endif /* ADC3 */ #if defined (ADC4) #define DMA_REQUEST_ADC4 38U #endif /* ADC4 */ #if defined (ADC5) #define DMA_REQUEST_ADC5 39U #endif /* ADC5 */ #if defined (QUADSPI) #define DMA_REQUEST_QUADSPI 40U #endif /* QUADSPI */ #if defined (DAC2) #define DMA_REQUEST_DAC2_CHANNEL1 41U #endif /* DAC2 */ #define DMA_REQUEST_TIM1_CH1 42U #define DMA_REQUEST_TIM1_CH2 43U #define DMA_REQUEST_TIM1_CH3 44U #define DMA_REQUEST_TIM1_CH4 45U #define DMA_REQUEST_TIM1_UP 46U #define DMA_REQUEST_TIM1_TRIG 47U #define DMA_REQUEST_TIM1_COM 48U #define DMA_REQUEST_TIM8_CH1 49U #define DMA_REQUEST_TIM8_CH2 50U #define DMA_REQUEST_TIM8_CH3 51U #define DMA_REQUEST_TIM8_CH4 52U #define DMA_REQUEST_TIM8_UP 53U #define DMA_REQUEST_TIM8_TRIG 54U #define DMA_REQUEST_TIM8_COM 55U #define DMA_REQUEST_TIM2_CH1 56U #define DMA_REQUEST_TIM2_CH2 57U #define DMA_REQUEST_TIM2_CH3 58U #define DMA_REQUEST_TIM2_CH4 59U #define DMA_REQUEST_TIM2_UP 60U #define DMA_REQUEST_TIM3_CH1 61U #define DMA_REQUEST_TIM3_CH2 62U #define DMA_REQUEST_TIM3_CH3 63U #define DMA_REQUEST_TIM3_CH4 64U #define DMA_REQUEST_TIM3_UP 65U #define DMA_REQUEST_TIM3_TRIG 66U #define DMA_REQUEST_TIM4_CH1 67U #define DMA_REQUEST_TIM4_CH2 68U #define DMA_REQUEST_TIM4_CH3 69U #define DMA_REQUEST_TIM4_CH4 70U #define DMA_REQUEST_TIM4_UP 71U #if defined (TIM5) #define DMA_REQUEST_TIM5_CH1 72U #define DMA_REQUEST_TIM5_CH2 73U #define DMA_REQUEST_TIM5_CH3 74U #define DMA_REQUEST_TIM5_CH4 75U #define DMA_REQUEST_TIM5_UP 76U #define DMA_REQUEST_TIM5_TRIG 77U #endif /* TIM5 */ #define DMA_REQUEST_TIM15_CH1 78U #define DMA_REQUEST_TIM15_UP 79U #define DMA_REQUEST_TIM15_TRIG 80U #define DMA_REQUEST_TIM15_COM 81U #define DMA_REQUEST_TIM16_CH1 82U #define DMA_REQUEST_TIM16_UP 83U #define DMA_REQUEST_TIM17_CH1 84U #define DMA_REQUEST_TIM17_UP 85U #if defined (TIM20) #define DMA_REQUEST_TIM20_CH1 86U #define DMA_REQUEST_TIM20_CH2 87U #define DMA_REQUEST_TIM20_CH3 88U #define DMA_REQUEST_TIM20_CH4 89U #define DMA_REQUEST_TIM20_UP 90U #endif /* TIM20 */ #define DMA_REQUEST_AES_IN 91U #define DMA_REQUEST_AES_OUT 92U #if defined (TIM20) #define DMA_REQUEST_TIM20_TRIG 93U #define DMA_REQUEST_TIM20_COM 94U #endif /* TIM20 */ #if defined (HRTIM1) #define DMA_REQUEST_HRTIM1_M 95U #define DMA_REQUEST_HRTIM1_A 96U #define DMA_REQUEST_HRTIM1_B 97U #define DMA_REQUEST_HRTIM1_C 98U #define DMA_REQUEST_HRTIM1_D 99U #define DMA_REQUEST_HRTIM1_E 100U #define DMA_REQUEST_HRTIM1_F 101U #endif /* HRTIM1 */ #define DMA_REQUEST_DAC3_CHANNEL1 102U #define DMA_REQUEST_DAC3_CHANNEL2 103U #if defined (DAC4) #define DMA_REQUEST_DAC4_CHANNEL1 104U #define DMA_REQUEST_DAC4_CHANNEL2 105U #endif /* DAC4 */ #if defined (SPI4) #define DMA_REQUEST_SPI4_RX 106U #define DMA_REQUEST_SPI4_TX 107U #endif /* SPI4 */ #define DMA_REQUEST_SAI1_A 108U #define DMA_REQUEST_SAI1_B 109U #define DMA_REQUEST_FMAC_READ 110U #define DMA_REQUEST_FMAC_WRITE 111U #define DMA_REQUEST_CORDIC_READ 112U #define DMA_REQUEST_CORDIC_WRITE 113U #define DMA_REQUEST_UCPD1_RX 114U #define DMA_REQUEST_UCPD1_TX 115U /** * @} */ /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** * @} */ /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** * @} */ /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** * @} */ /** @defgroup DMA_mode DMA mode * @{ */ #define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ /** * @} */ /** @defgroup DMA_Priority_level DMA Priority level * @{ */ #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ /** * @} */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ #define DMA_IT_TC DMA_CCR_TCIE #define DMA_IT_HT DMA_CCR_HTIE #define DMA_IT_TE DMA_CCR_TEIE /** * @} */ /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ #define DMA_FLAG_GL1 0x00000001U #define DMA_FLAG_TC1 0x00000002U #define DMA_FLAG_HT1 0x00000004U #define DMA_FLAG_TE1 0x00000008U #define DMA_FLAG_GL2 0x00000010U #define DMA_FLAG_TC2 0x00000020U #define DMA_FLAG_HT2 0x00000040U #define DMA_FLAG_TE2 0x00000080U #define DMA_FLAG_GL3 0x00000100U #define DMA_FLAG_TC3 0x00000200U #define DMA_FLAG_HT3 0x00000400U #define DMA_FLAG_TE3 0x00000800U #define DMA_FLAG_GL4 0x00001000U #define DMA_FLAG_TC4 0x00002000U #define DMA_FLAG_HT4 0x00004000U #define DMA_FLAG_TE4 0x00008000U #define DMA_FLAG_GL5 0x00010000U #define DMA_FLAG_TC5 0x00020000U #define DMA_FLAG_HT5 0x00040000U #define DMA_FLAG_TE5 0x00080000U #define DMA_FLAG_GL6 0x00100000U #define DMA_FLAG_TC6 0x00200000U #define DMA_FLAG_HT6 0x00400000U #define DMA_FLAG_TE6 0x00800000U #if defined (DMA1_Channel7) #define DMA_FLAG_GL7 0x01000000U #define DMA_FLAG_TC7 0x02000000U #define DMA_FLAG_HT7 0x04000000U #define DMA_FLAG_TE7 0x08000000U #endif /* DMA1_Channel7 */ #if defined (DMA1_Channel8) #define DMA_FLAG_GL8 0x10000000U #define DMA_FLAG_TC8 0x20000000U #define DMA_FLAG_HT8 0x40000000U #define DMA_FLAG_TE8 0x80000000U #endif /* DMA1_Channel8 */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ /** @brief Reset DMA handle state. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) /* Interrupt & Flag management */ /** * @brief Return the current DMA Channel transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\ DMA_FLAG_TC8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ DMA_FLAG_TC6) #endif /* DMA1_Channel8 */ /** * @brief Return the current DMA Channel half transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\ DMA_FLAG_HT8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ DMA_FLAG_HT6) #endif /* DMA1_Channel8 */ /** * @brief Return the current DMA Channel transfer error flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\ DMA_FLAG_TE8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ DMA_FLAG_TE6) #endif /* DMA1_Channel8 */ /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\ DMA_ISR_GIF8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ DMA_ISR_GIF6) #endif /* DMA1_Channel8 */ /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx Transfer complete flag * @arg DMA_FLAG_HTx Half transfer complete flag * @arg DMA_FLAG_TEx Transfer error flag * @arg DMA_FLAG_GLx Global interrupt flag * Where x can be from 1 to 8 to select the DMA Channel x flag. * @retval The state of FLAG (SET or RESET). */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) #endif /* DMA1_Channel8 */ /** * @brief Clear the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx Transfer complete flag * @arg DMA_FLAG_HTx Half transfer complete flag * @arg DMA_FLAG_TEx Transfer error flag * @arg DMA_FLAG_GLx Global interrupt flag * Where x can be from 1 to 8 to select the DMA Channel x flag. * @retval None */ #if defined (DMA1_Channel8) #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) #else #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) #endif /* DMA1_Channel8 */ /** * @brief Enable the specified DMA Channel interrupts. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC Transfer complete interrupt mask * @arg DMA_IT_HT Half transfer complete interrupt mask * @arg DMA_IT_TE Transfer error interrupt mask * @retval None */ #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) /** * @brief Disable the specified DMA Channel interrupts. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC Transfer complete interrupt mask * @arg DMA_IT_HT Half transfer complete interrupt mask * @arg DMA_IT_TE Transfer error interrupt mask * @retval None */ #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) /** * @brief Check whether the specified DMA Channel interrupt is enabled or not. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC Transfer complete interrupt mask * @arg DMA_IT_HT Half transfer complete interrupt mask * @arg DMA_IT_TE Transfer error interrupt mask * @retval The state of DMA_IT (SET or RESET). */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) /** * @brief Return the number of remaining data units in the current DMA Channel transfer. * @param __HANDLE__ DMA handle * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) /** * @} */ /* Include DMA HAL Extension module */ #include "stm32g4xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions * @{ */ /** @addtogroup DMA_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros * @{ */ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ ((STATE) == DMA_MINC_DISABLE)) #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_PDATAALIGN_WORD)) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_MDATAALIGN_WORD )) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_HAL_DMA_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma_ex.h * @author MCD Application Team * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_DMA_EX_H #define __STM32G4xx_HAL_DMA_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup DMAEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Types DMAEx Exported Types * @{ */ /** * @brief HAL DMA Synchro definition */ /** * @brief HAL DMAMUX Synchronization configuration structure definition */ typedef struct { uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABLE or DISABLE*/ FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. This parameter can take the value ENABLE or DISABLE */ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ } HAL_DMA_MuxSyncConfigTypeDef; /** * @brief HAL DMAMUX request generator parameters structure definition */ typedef struct { uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ } HAL_DMA_MuxRequestGeneratorConfigTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants * @{ */ /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection * @{ */ #define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ #define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ #define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ #define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ #define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ #define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ #define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ #define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ #define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ #define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ #define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ #define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ #define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ #define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ #define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ #define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ #define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ /** * @} */ /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection * @{ */ #define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ #define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ #define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ #define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ /** * @} */ /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection * @{ */ #define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ /** * @} */ /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection * @{ */ #define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */ #define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ #define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ #define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMAEx_Exported_Functions * @{ */ /* IO operation functions *****************************************************/ /** @addtogroup DMAEx_Exported_Functions_Group1 * @{ */ /* ------------------------- REQUEST -----------------------------------------*/ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); /* -------------------------------------------------------------------------- */ /* ------------------------- SYNCHRO -----------------------------------------*/ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); /* -------------------------------------------------------------------------- */ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMAEx_Private_Macros DMAEx Private Macros * @brief DMAEx private macros * @{ */ #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT) #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ ((EVENT) == ENABLE)) #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT) #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_HAL_DMA_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_exti.h * @author MCD Application Team * @brief Header file of EXTI HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_EXTI_H #define STM32G4xx_HAL_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup EXTI EXTI * @brief EXTI HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Types EXTI Exported Types * @{ */ typedef enum { HAL_EXTI_COMMON_CB_ID = 0x00UL } EXTI_CallbackIDTypeDef; /** * @brief EXTI Handle structure definition */ typedef struct { uint32_t Line; /*!< Exti line number */ void (* PendingCallback)(void); /*!< Exti pending callback */ } EXTI_HandleTypeDef; /** * @brief EXTI Configuration structure definition */ typedef struct { uint32_t Line; /*!< The Exti line to be configured. This parameter can be a value of @ref EXTI_Line */ uint32_t Mode; /*!< The Exit Mode to be configured for a core. This parameter can be a combination of @ref EXTI_Mode */ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter can be a value of @ref EXTI_Trigger */ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of @ref EXTI_GPIOSel */ } EXTI_ConfigTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Constants EXTI Exported Constants * @{ */ /** @defgroup EXTI_Line EXTI Line * @{ */ #define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) #define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) #define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) #define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) #define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) #define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) #define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) #define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) #define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) #define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) #define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) #define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) #define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) #define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) #define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) #define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) #define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) #define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) #define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u) #define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u) #define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) #define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u) #define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u) #define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) #define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) #define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) #define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) #define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du) #define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu) #define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) #define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u) #define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) #define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u) #define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) #define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) #define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u) #define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u) #define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u) #define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u) #define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) /** * @} */ /** @defgroup EXTI_Mode EXTI Mode * @{ */ #define EXTI_MODE_NONE 0x00000000U #define EXTI_MODE_INTERRUPT 0x00000001U #define EXTI_MODE_EVENT 0x00000002U /** * @} */ /** @defgroup EXTI_Trigger EXTI Trigger * @{ */ #define EXTI_TRIGGER_NONE 0x00000000U #define EXTI_TRIGGER_RISING 0x00000001U #define EXTI_TRIGGER_FALLING 0x00000002U #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @} */ /** @defgroup EXTI_GPIOSel EXTI GPIOSel * @brief * @{ */ #define EXTI_GPIOA 0x00000000U #define EXTI_GPIOB 0x00000001U #define EXTI_GPIOC 0x00000002U #define EXTI_GPIOD 0x00000003U #define EXTI_GPIOE 0x00000004U #define EXTI_GPIOF 0x00000005U #define EXTI_GPIOG 0x00000006U /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Macros EXTI Exported Macros * @{ */ /** * @} */ /* Private constants --------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ /** * @brief EXTI Line property definition */ #define EXTI_PROPERTY_SHIFT 24U #define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) #define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) #define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI Register and bit usage */ #define EXTI_REG_SHIFT 16U #define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) #define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) #define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) #define EXTI_PIN_MASK 0x0000001FU /** * @brief EXTI Mask for interrupt & event mode */ #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) /** * @brief EXTI Mask for trigger possibilities */ #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @brief EXTI Line number */ #define EXTI_LINE_NB 44UL /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ #define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) #define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOF) || \ ((__PORT__) == EXTI_GPIOG)) #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) #define IS_EXTI_PENDING_EDGE(__EDGE__) (((__EDGE__) == EXTI_TRIGGER_RISING) || \ ((__EDGE__) == EXTI_TRIGGER_FALLING)|| \ ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING)) #define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Functions EXTI Exported Functions * @brief EXTI Exported Functions * @{ */ /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions * @brief Configuration functions * @{ */ /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); /** * @} */ /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_EXTI_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash.h * @author MCD Application Team * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_FLASH_H #define STM32G4xx_HAL_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup FLASH * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ /** * @brief FLASH Erase structure definition */ typedef struct { uint32_t TypeErase; /*!< Mass erase or page erase. This parameter can be a value of @ref FLASH_Type_Erase */ uint32_t Banks; /*!< Select bank to erase. This parameter must be a value of @ref FLASH_Banks (FLASH_BANK_BOTH should be used only for mass erase) */ uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled. This parameter must be a value between 0 and (max number of pages in the bank - 1) (eg : 127 for 512KB dual bank) */ uint32_t NbPages; /*!< Number of pages to be erased. This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ } FLASH_EraseInitTypeDef; /** * @brief FLASH Option Bytes Program structure definition */ typedef struct { uint32_t OptionType; /*!< Option byte to be configured. This parameter can be a combination of the values of @ref FLASH_OB_Type */ uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). Only one WRP area could be programmed at the same time. This parameter can be value of @ref FLASH_OB_WRP_Area */ uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). This parameter must be a value between 0 and (max number of pages in the bank - 1) */ uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). This parameter can be a value of @ref FLASH_OB_Read_Protection */ uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_Type */ uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST @note (*) availability depends on devices */ uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) and @ref FLASH_OB_PCROP_RDP */ uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). This parameter must be a value between begin and end of bank => Be careful of the bank swapping for the address */ uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of bank */ uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK). This parameter can be a value of @ref FLASH_OB_Boot_Lock */ uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC). Only one securable memory area could be programmed at the same time. This parameter can be one of the following values: FLASH_BANK_1: Securable memory area to be programmed in bank 1 FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*) @note (*) availability depends on devices */ uint32_t SecSize; /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC), in number of pages. Securable memory area is starting from first page of the bank. Only one securable memory could be programmed at the same time. This parameter must be a value between 0 and (max number of pages in the bank - 1) */ } FLASH_OBProgramInitTypeDef; /** * @brief FLASH Procedure structure definition */ typedef enum { FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, FLASH_PROC_MASS_ERASE, FLASH_PROC_PROGRAM, FLASH_PROC_PROGRAM_LAST } FLASH_ProcedureTypeDef; /** * @brief FLASH Cache structure definition */ typedef enum { FLASH_CACHE_DISABLED = 0, FLASH_CACHE_ICACHE_ENABLED, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_ICACHE_DCACHE_ENABLED } FLASH_CacheTypeDef; /** * @brief FLASH handle Structure definition */ typedef struct { HAL_LockTypeDef Lock; /* FLASH locking object */ __IO uint32_t ErrorCode; /* FLASH error code */ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ } FLASH_ProcessTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ */ /** @defgroup FLASH_Error FLASH Error * @{ */ #define HAL_FLASH_ERROR_NONE 0x00000000U #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD #if defined (FLASH_OPTR_DBANK) #define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2 #define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2 #endif /** * @} */ /** @defgroup FLASH_Type_Erase FLASH Erase Type * @{ */ #define FLASH_TYPEERASE_PAGES 0x00U /*!> 24U) /*!< ECC Correction Interrupt source */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @brief macros to control FLASH features * @{ */ /** * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency. * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states * @arg FLASH_LATENCY_5: FLASH Five wait states * @arg FLASH_LATENCY_6: FLASH Six wait states * @arg FLASH_LATENCY_7: FLASH Seven wait states * @arg FLASH_LATENCY_8: FLASH Eight wait states * @arg FLASH_LATENCY_9: FLASH Nine wait states * @arg FLASH_LATENCY_10: FLASH Ten wait state * @arg FLASH_LATENCY_11: FLASH Eleven wait state * @arg FLASH_LATENCY_12: FLASH Twelve wait states * @arg FLASH_LATENCY_13: FLASH Thirteen wait states * @arg FLASH_LATENCY_14: FLASH Fourteen wait states * @arg FLASH_LATENCY_15: FLASH Fifteen wait states * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) /** * @brief Get the FLASH Latency. * @retval FLASH_Latency. * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states * @arg FLASH_LATENCY_5: FLASH Five wait states * @arg FLASH_LATENCY_6: FLASH Six wait states * @arg FLASH_LATENCY_7: FLASH Seven wait states * @arg FLASH_LATENCY_8: FLASH Eight wait states * @arg FLASH_LATENCY_9: FLASH Nine wait states * @arg FLASH_LATENCY_10: FLASH Ten wait state * @arg FLASH_LATENCY_11: FLASH Eleven wait state * @arg FLASH_LATENCY_12: FLASH Twelve wait states * @arg FLASH_LATENCY_13: FLASH Thirteen wait states * @arg FLASH_LATENCY_14: FLASH Fourteen wait states * @arg FLASH_LATENCY_15: FLASH Fifteen wait states */ #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) /** * @brief Enable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) /** * @brief Disable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) /** * @brief Enable the FLASH instruction cache. * @retval none */ #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Disable the FLASH instruction cache. * @retval none */ #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Enable the FLASH data cache. * @retval none */ #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Disable the FLASH data cache. * @retval none */ #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Reset the FLASH instruction Cache. * @note This function must be used only when the Instruction Cache is disabled. * @retval None */ #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ } while (0) /** * @brief Reset the FLASH data Cache. * @note This function must be used only when the data Cache is disabled. * @retval None */ #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ } while (0) /** * @brief Enable the FLASH power down during Low-power run mode. * @note Writing this bit to 1, automatically the keys are * lost and a new unlock sequence is necessary to re-write it to 0. */ #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ } while (0) /** * @brief Disable the FLASH power down during Low-power run mode. * @note Writing this bit to 0, automatically the keys are * lost and a new unlock sequence is necessary to re-write it to 1. */ #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ } while (0) /** * @brief Enable the FLASH power down during Low-Power sleep mode * @retval none */ #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @brief Disable the FLASH power down during Low-Power sleep mode * @retval none */ #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @} */ /** @defgroup FLASH_Interrupt FLASH Interrupts Macros * @brief macros to handle FLASH interrupts * @{ */ /** * @brief Enable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while (0) /** * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while (0) /** * @brief Check whether the specified FLASH flag is set or not. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) * @note (*) availability depends on devices * @retval The new state of FLASH_FLAG (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) /** * @brief Clear the FLASH's pending flags. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) * @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags * @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags * @note (*) availability depends on devices * @retval None */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ } while (0) /** * @} */ /* Include FLASH HAL Extended module */ #include "stm32g4xx_hal_flash_ex.h" #include "stm32g4xx_hal_flash_ramfunc.h" /* Exported variables --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Variables FLASH Exported Variables * @{ */ extern FLASH_ProcessTypeDef pFlash; /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ /* Program operation functions ***********************************************/ /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler method */ void HAL_FLASH_IRQHandler(void); /* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** * @} */ /* Peripheral Control functions **********************************************/ /** @addtogroup FLASH_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); /* Option bytes control */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); /** * @} */ /* Peripheral State functions ************************************************/ /** @addtogroup FLASH_Exported_Functions_Group3 * @{ */ uint32_t HAL_FLASH_GetError(void); /** * @} */ /** * @} */ /** @addtogroup FLASH_Private_Functions * @{ */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} */ /* Private constants --------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ #define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE #if defined (FLASH_OPTR_DBANK) #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) #define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 128U : \ ((FLASH_SIZE == 0x00040000U) ? 64U : 32U)) #define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */ #else #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) #define FLASH_BANK_SIZE (FLASH_SIZE) #define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \ ((FLASH_SIZE == 0x00040000U) ? 128U : 64U)) #endif #define FLASH_PAGE_SIZE 0x800U /* 2 KB */ #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #if defined (FLASH_OPTR_DBANK) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ ((BANK) == FLASH_BANK_2) || \ ((BANK) == FLASH_BANK_BOTH)) #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ ((BANK) == FLASH_BANK_2)) #else #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) #endif #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) #define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC))) #if defined (FLASH_OPTR_DBANK) #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) #else #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) #endif #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ ((LEVEL) == OB_RDP_LEVEL_1) ||\ ((LEVEL) == OB_RDP_LEVEL_2)) #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U)) #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ ((LEVEL) == OB_BOR_LEVEL_4)) #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) #if defined (FLASH_OPTR_DBANK) #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) #endif #if defined (FLASH_OPTR_PB4_PUPEN) #define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE)) #endif #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE)) #define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE)) #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) #define IS_OB_USER_NRST_MODE(VALUE) (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \ ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT)) #define IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE)) #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) #define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB) #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_FLASH_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ex.h * @author MCD Application Team * @brief Header file of FLASH HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_FLASH_EX_H #define STM32G4xx_HAL_FLASH_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup FLASHEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ */ /* Extended Program operation functions *************************************/ /** @addtogroup FLASHEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank); void HAL_FLASHEx_EnableDebugger(void); void HAL_FLASHEx_DisableDebugger(void); /** * @} */ /** * @} */ /** @addtogroup FLASHEx_Private_Functions * @{ */ void FLASH_PageErase(uint32_t Page, uint32_t Banks); void FLASH_FlushCaches(void); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_FLASH_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ramfunc.h * @author MCD Application Team * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_FLASH_RAMFUNC_H #define STM32G4xx_FLASH_RAMFUNC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup FLASH_RAMFUNC * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_RAMFUNC_Exported_Functions * @{ */ /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 * @{ */ /* Peripheral Control functions ************************************************/ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void); __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void); #if defined (FLASH_OPTR_DBANK) __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); #endif /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_FLASH_RAMFUNC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_gpio.h * @author MCD Application Team * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_GPIO_H #define STM32G4xx_HAL_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup GPIO GPIO * @brief GPIO HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ */ /** * @brief GPIO Init structure definition */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode */ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull */ uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed */ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ } GPIO_InitTypeDef; /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ */ /** @defgroup GPIO_pins GPIO pins * @{ */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ /** * @} */ /** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode * Elements values convention: 0x00WX00YZ * - W : EXTI trigger detection on 3 bits * - X : EXTI mode (IT or Event) on 2 bits * - Y : Output type (Push Pull or Open Drain) on 1 bit * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ */ #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ #define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ #define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup GPIO_speed GPIO speed * @brief GPIO Output Maximum frequency * @{ */ #define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */ /** * @} */ /** @defgroup GPIO_pull GPIO pull * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ #define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ #define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ /** * @brief Check whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) /** * @brief Clear the EXTI's line pending flags. * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) /** * @brief Check whether the specified EXTI line is asserted or not. * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) /** * @brief Clear the EXTI's line pending bits. * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) /** * @brief Generate a Software interrupt on selected EXTI line. * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ #define GPIO_MODE_Pos 0U #define GPIO_MODE (0x3UL << GPIO_MODE_Pos) #define MODE_INPUT (0x0UL << GPIO_MODE_Pos) #define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) #define MODE_AF (0x2UL << GPIO_MODE_Pos) #define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) #define OUTPUT_TYPE_Pos 4U #define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) #define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) #define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) #define EXTI_MODE_Pos 16U #define EXTI_MODE (0x3UL << EXTI_MODE_Pos) #define EXTI_IT (0x1UL << EXTI_MODE_Pos) #define EXTI_EVT (0x2UL << EXTI_MODE_Pos) #define TRIGGER_MODE_Pos 20U #define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) #define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) #define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) /** * @} */ /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ ((__MODE__) == GPIO_MODE_AF_PP) ||\ ((__MODE__) == GPIO_MODE_AF_OD) ||\ ((__MODE__) == GPIO_MODE_IT_RISING) ||\ ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ ((__MODE__) == GPIO_MODE_ANALOG)) #define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) #define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ ((__PULL__) == GPIO_PULLUP) || \ ((__PULL__) == GPIO_PULLDOWN)) /** * @} */ /* Include GPIO HAL Extended module */ #include "stm32g4xx_hal_gpio_ex.h" /* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Functions GPIO Exported Functions * @brief GPIO Exported Functions * @{ */ /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} */ /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_GPIO_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_gpio_ex.h * @author MCD Application Team * @brief Header file of GPIO HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_GPIO_EX_H #define STM32G4xx_HAL_GPIO_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup GPIOEx GPIOEx * @brief GPIO Extended HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection * @{ */ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ #if defined(TIM5) #define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ #define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #if defined(TIM5) #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ #define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */ #define GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF2_TIM20_COMP1 ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */ #define GPIO_AF2_TIM20_COMP2 ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */ #define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */ #if defined(I2C4) #define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ #endif /* I2C4 */ #if defined(HRTIM1) #define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */ #endif /* HRTIM1 */ #if defined(QUADSPI) #define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */ #endif /* QUADSPI */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ #define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ #if defined(I2C4) #define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ #endif /* I2C4 */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ #if defined(SPI4) #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #endif /* SPI4 */ #define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */ #define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */ #define GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */ #if defined(UART5) #define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */ #endif /* UART5 */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */ #if defined(TIM5) #define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ #define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */ #define GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #if defined(COMP5) #define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */ #endif /* COMP5 */ #if defined(COMP6) #define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */ #endif /* COMP6 */ #if defined(COMP7) #define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */ #endif /* COMP7 */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */ #if defined(COMP5) #define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */ #endif /* COMP5 */ #if defined(COMP6) #define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */ #endif /* COMP6 */ #if defined(COMP7) #define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */ #endif /* COMP7 */ #define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */ #if defined(I2C4) #define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */ #endif /* I2C4 */ #define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #if defined(UART5) #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #endif /* UART5 */ /** * @brief AF 9 selection */ #define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */ #define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ #if defined(FDCAN2) #define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ #endif /* FDCAN2 */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */ #define GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */ #define GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */ #if defined(QUADSPI) #define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */ #endif /* QUADSPI */ /** * @brief AF 11 selection */ #define GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */ #if defined(FDCAN3) #define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */ #endif /* FDCAN3 */ #define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ #define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ #define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */ #define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ #if defined(HRTIM1) #define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */ #endif /* HRTIM1 */ #if defined(FMC_BANK1) #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #endif /* FMC_BANK1 */ #define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */ /** * @brief AF 13 selection */ #if defined(HRTIM1) #define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */ #endif /* HRTIM1 */ #define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ #define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ #define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */ #define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */ #define GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */ #if defined(UART5) #define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ #endif /* UART5 */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros * @{ */ /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ ((__GPIOx__) == (GPIOB))? 1UL :\ ((__GPIOx__) == (GPIOC))? 2UL :\ ((__GPIOx__) == (GPIOD))? 3UL :\ ((__GPIOx__) == (GPIOE))? 4UL :\ ((__GPIOx__) == (GPIOF))? 5UL : 6UL) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_GPIO_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr.h * @author MCD Application Team * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_PWR_H #define STM32G4xx_HAL_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ */ /** * @brief PWR PVD configuration structure definition */ typedef struct { uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This parameter can be a value of @ref PWR_PVD_detection_level. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWR_PVD_Mode. */ }PWR_PVDTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels * @{ */ #define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ #define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ #define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ #define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ #define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ #define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ #define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ #define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ /** * @} */ /** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode * @{ */ #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode * @{ */ #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ /** * @} */ /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ /** * @} */ /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ /** * @} */ /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line * @{ */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** * @} */ /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line * @{ */ #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup PWR_Exported_Macros PWR Exported Macros * @{ */ /** @brief Check whether or not a specific PWR flag is set. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event * was received from the WKUP pin 1. * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event * was received from the WKUP pin 2. * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event * was received from the WKUP pin 3. * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event * was received from the WKUP pin 4. * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event * was received from the WKUP pin 5. * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system * entered StandBy mode. * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on * the internal wakeup line. * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the * low-power regulator is ready. * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the * regulator is ready in main mode or is in low-power mode. * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready * in the selected voltage range or is still changing to the required voltage level. * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is * below or above the selected PVD threshold. @if PWR_CR2_PVME1 * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is * is below or above PVM1 threshold (applicable when USB feature is supported). @endif @if PWR_CR2_PVME2 * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). @endif * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is * is below or above PVM3 threshold. * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is * is below or above PVM4 threshold. * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) /** @brief Clear a specific PWR flag. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event * was received from the WKUP pin 1. * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event * was received from the WKUP pin 2. * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event * was received from the WKUP pin 3. * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event * was received from the WKUP pin 4. * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event * was received from the WKUP pin 5. * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system * entered Standby mode. * @retval None */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ (PWR->SCR = (__FLAG__)) :\ (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) /** * @brief Enable the PVD Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) /** * @brief Enable the PVD Event Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) /** * @brief Disable the PVD Event Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) /** * @brief Enable the PVD Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) /** * @brief Enable the PVD Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) /** * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) /** * @brief Check whether or not the PVD EXTI interrupt flag is set. * @retval EXTI PVD Line Status. */ #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) /** * @brief Clear the PVD EXTI interrupt flag. * @retval None */ #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) /** * @} */ /* Private macros --------------------------------------------------------*/ /** @addtogroup PWR_Private_Macros PWR Private Macros * @{ */ #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) /** * @} */ /* Include PWR HAL Extended module */ #include "stm32g4xx_hal_pwr_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *******************************/ void HAL_PWR_DeInit(void); void HAL_PWR_EnableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void); /** * @} */ /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); /* WakeUp pins configuration functions ****************************************/ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); /* Low Power modes configuration functions ************************************/ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSTANDBYMode(void); void HAL_PWR_EnableSleepOnExit(void); void HAL_PWR_DisableSleepOnExit(void); void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_PVDCallback(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_PWR_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr_ex.h * @author MCD Application Team * @brief Header file of PWR HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_PWR_EX_H #define STM32G4xx_HAL_PWR_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup PWREx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWREx_Exported_Types PWR Extended Exported Types * @{ */ /** * @brief PWR PVM configuration structure definition */ typedef struct { uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. This parameter can be a value of @ref PWREx_PVM_Type. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWREx_PVM_Mode. */ }PWR_PVMTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants * @{ */ /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants * @{ */ #define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */ /** * @} */ /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins * @{ */ #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<IMR2, PWR_EXTI_LINE_PVM1) /** * @brief Disable the PVM1 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) /** * @brief Enable the PVM1 Event Line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) /** * @brief Disable the PVM1 Event Line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) /** * @brief Enable the PVM1 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) /** * @brief Disable the PVM1 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) /** * @brief Enable the PVM1 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) /** * @brief Disable the PVM1 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) /** * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) /** * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. * @retval EXTI PVM1 Line Status. */ #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) /** * @brief Clear the PVM1 EXTI flag. * @retval None */ #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) /** * @brief Enable the PVM2 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) /** * @brief Disable the PVM2 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) /** * @brief Enable the PVM2 Event Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) /** * @brief Disable the PVM2 Event Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) /** * @brief Enable the PVM2 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) /** * @brief Disable the PVM2 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) /** * @brief Enable the PVM2 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) /** * @brief Disable the PVM2 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) /** * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) /** * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. * @retval EXTI PVM2 Line Status. */ #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) /** * @brief Clear the PVM2 EXTI flag. * @retval None */ #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) #endif /* PWR_CR2_PVME2 */ /** * @brief Enable the PVM3 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) /** * @brief Disable the PVM3 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) /** * @brief Enable the PVM3 Event Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) /** * @brief Disable the PVM3 Event Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) /** * @brief Enable the PVM3 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) /** * @brief Disable the PVM3 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) /** * @brief Enable the PVM3 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) /** * @brief Disable the PVM3 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) /** * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) /** * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. * @retval EXTI PVM3 Line Status. */ #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) /** * @brief Clear the PVM3 EXTI flag. * @retval None */ #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) /** * @brief Enable the PVM4 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) /** * @brief Disable the PVM4 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) /** * @brief Enable the PVM4 Event Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) /** * @brief Disable the PVM4 Event Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) /** * @brief Enable the PVM4 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) /** * @brief Disable the PVM4 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) /** * @brief Enable the PVM4 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) /** * @brief Disable the PVM4 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) /** * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) /** * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. * @retval EXTI PVM4 Line Status. */ #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) /** * @brief Clear the PVM4 EXTI flag. * @retval None */ #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) /** * @brief Configure the main internal regulator output voltage. * @param __REGULATOR__: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage output range 1 mode, * typical output voltage at 1.28 V, * system frequency up to 170 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, * typical output voltage at 1.2 V, * system frequency up to 150 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, * typical output voltage at 1.0 V, * system frequency up to 26 MHz. * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check * whether or not VOSF flag is cleared when moving from range 2 to range 1. User * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. * @retval None */ #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ __IO uint32_t tmpreg; \ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ UNUSED(tmpreg); \ } while(0) /** * @} */ /* Private macros --------------------------------------------------------*/ /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros * @{ */ #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ ((PIN) == PWR_WAKEUP_PIN2) || \ ((PIN) == PWR_WAKEUP_PIN3) || \ ((PIN) == PWR_WAKEUP_PIN4) || \ ((PIN) == PWR_WAKEUP_PIN5) || \ ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ ((PIN) == PWR_WAKEUP_PIN5_LOW)) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ ((TYPE) == PWR_PVM_2) ||\ ((TYPE) == PWR_PVM_3) ||\ ((TYPE) == PWR_PVM_4)) #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) #if defined(PWR_CR5_R1MODE) #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) #else #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) #endif #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U) #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ ((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_C) ||\ ((GPIO) == PWR_GPIO_D) ||\ ((GPIO) == PWR_GPIO_E) ||\ ((GPIO) == PWR_GPIO_F) ||\ ((GPIO) == PWR_GPIO_G)) /** * @} */ /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @{ */ /* Peripheral Control functions **********************************************/ uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); void HAL_PWREx_DisableBatteryCharging(void); void HAL_PWREx_EnableInternalWakeUpLine(void); void HAL_PWREx_DisableInternalWakeUpLine(void); HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); void HAL_PWREx_EnablePullUpPullDownConfig(void); void HAL_PWREx_DisablePullUpPullDownConfig(void); void HAL_PWREx_EnableSRAM2ContentRetention(void); void HAL_PWREx_DisableSRAM2ContentRetention(void); #if defined(PWR_CR2_PVME1) void HAL_PWREx_EnablePVM1(void); void HAL_PWREx_DisablePVM1(void); #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) void HAL_PWREx_EnablePVM2(void); void HAL_PWREx_DisablePVM2(void); #endif /* PWR_CR2_PVME2 */ void HAL_PWREx_EnablePVM3(void); void HAL_PWREx_DisablePVM3(void); void HAL_PWREx_EnablePVM4(void); void HAL_PWREx_DisablePVM4(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); /* Low Power modes configuration functions ************************************/ void HAL_PWREx_EnableLowPowerRunMode(void); HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSHUTDOWNMode(void); void HAL_PWREx_PVD_PVM_IRQHandler(void); #if defined(PWR_CR2_PVME1) void HAL_PWREx_PVM1Callback(void); #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) void HAL_PWREx_PVM2Callback(void); #endif /* PWR_CR2_PVME2 */ void HAL_PWREx_PVM3Callback(void); void HAL_PWREx_PVM4Callback(void); #if defined(PWR_CR3_UCPD_STDBY) void HAL_PWREx_EnableUCPDStandbyMode(void); void HAL_PWREx_DisableUCPDStandbyMode(void); #endif /* PWR_CR3_UCPD_STDBY */ #if defined(PWR_CR3_UCPD_DBDIS) void HAL_PWREx_EnableUCPDDeadBattery(void); void HAL_PWREx_DisableUCPDDeadBattery(void); #endif /* PWR_CR3_UCPD_DBDIS */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_PWR_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc.h * @author MCD Application Team * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_RCC_H #define STM32G4xx_HAL_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ /** * @brief RCC PLL configuration structure definition */ typedef struct { uint32_t PLLState; /*!< The new state of the PLL. This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 127 */ uint32_t PLLP; /*!< PLLP: Division factor for ADC clock. This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks. This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ uint32_t PLLR; /*!< PLLR: Division for the main system clock. User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ. This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ }RCC_PLLInitTypeDef; /** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { uint32_t OscillatorType; /*!< The oscillators to be configured. This parameter can be a value of @ref RCC_Oscillator_Type */ uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ uint32_t HSI48State; /*!< The new state of the HSI48. This parameter can be a value of @ref RCC_HSI48_Config */ RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ }RCC_OscInitTypeDef; /** * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { uint32_t ClockType; /*!< The clock to be configured. This parameter can be a value of @ref RCC_System_Clock_Type */ uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). This parameter can be a value of @ref RCC_System_Clock_Source */ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of @ref RCC_AHB_Clock_Source */ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ }RCC_ClkInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants RCC Exported Constants * @{ */ /** @defgroup RCC_Timeout_Value Timeout Values * @{ */ #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /** * @} */ /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ /** * @} */ /** @defgroup RCC_HSE_Config HSE Config * @{ */ #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ /** * @} */ /** @defgroup RCC_LSE_Config LSE Config * @{ */ #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ /** * @} */ /** @defgroup RCC_HSI_Config HSI Config * @{ */ #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ /** * @} */ /** @defgroup RCC_LSI_Config LSI Config * @{ */ #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ /** * @} */ /** @defgroup RCC_PLL_Config PLL Config * @{ */ #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} */ /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider * @{ */ #define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */ #define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */ #define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */ #define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */ #define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */ #define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */ #define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */ #define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */ #define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */ #define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */ #define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */ #define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */ #define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */ #define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */ #define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */ #define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */ /** * @} */ /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider * @{ */ #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ /** * @} */ /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider * @{ */ #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ /** * @} */ /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider * @{ */ #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ /** * @} */ /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ /** * @} */ /** @defgroup RCC_PLL_Clock_Output PLL Clock Output * @{ */ #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ /** * @} */ /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} */ /** @defgroup RCC_System_Clock_Source System Clock Source * @{ */ #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ /** * @} */ /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status * @{ */ #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ /** * @} */ /** @defgroup RCC_AHB_Clock_Source AHB Clock Source * @{ */ #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} */ /** @defgroup RCC_MCO_Index MCO Index * @{ */ /* 32 28 20 16 0 -------------------------------- | MCO | GPIO | GPIO | GPIO | | Index | AF | Port | Pin | -------------------------------*/ #define RCC_MCO_GPIOPORT_POS 16U #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) #define RCC_MCO_GPIOAF_POS 20U #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) #define RCC_MCO_INDEX_POS 28U #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ #define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) #define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) /* Legacy Defines*/ #define RCC_MCO1 RCC_MCO_PA8 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source * @{ */ #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ /** * @} */ /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler * @{ */ #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ /** * @} */ /** @defgroup RCC_Interrupt Interrupts * @{ */ #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ /** * @} */ /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register * - XXX : Register index * - 001: CR register * - 010: BDCR register * - 011: CSR register * - 100: CRRCR register * @{ */ /* Flags in the CR register */ #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ /* Flags in the CSR register */ #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ /* Flags in the CRRCR register */ #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ /** * @} */ /** @defgroup RCC_LSEDrive_Config LSE Drive Config * @{ */ #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup RCC_Exported_Macros RCC Exported Macros * @{ */ /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) /** * @} */ /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable * @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ UNUSED(tmpreg); \ } while(0) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ UNUSED(tmpreg); \ } while(0) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ UNUSED(tmpreg); \ } while(0) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ UNUSED(tmpreg); \ } while(0) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ UNUSED(tmpreg); \ } while(0) #endif /* AES */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); #endif /* AES */ #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) /** * @} */ /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable * @brief Enable or disable the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ UNUSED(tmpreg); \ } while(0) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ UNUSED(tmpreg); \ } while(0) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable * @brief Enable or disable the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ UNUSED(tmpreg); \ } while(0) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ UNUSED(tmpreg); \ } while(0) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CRS_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ UNUSED(tmpreg); \ } while(0) #if defined(UART4) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ UNUSED(tmpreg); \ } while(0) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ UNUSED(tmpreg); \ } while(0) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ UNUSED(tmpreg); \ } while(0) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) #if defined(UART4) #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable * @brief Enable or disable the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ UNUSED(tmpreg); \ } while(0) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ UNUSED(tmpreg); \ } while(0) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ UNUSED(tmpreg); \ } while(0) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status * @brief Check whether the AHB1 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) /** * @} */ /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status * @brief Check whether the AHB2 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) #define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) /** * @} */ /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status * @brief Check whether the AHB3 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status * @brief Check whether the APB1 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) #if defined(USB) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U) #endif /* USB */ #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status * @brief Check whether the APB2 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset * @brief Force or release AHB1 peripheral reset. * @{ */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) /** * @} */ /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset * @brief Force or release AHB2 peripheral reset. * @{ */ #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) #if defined(DAC2) #define __HAL_RCC_DAC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) #endif /* DAC2 */ #define __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) #if defined(DAC4) #define __HAL_RCC_DAC4_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #endif /* AES */ #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) #if defined(DAC2) #define __HAL_RCC_DAC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) #endif /* DAC2 */ #define __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) #if defined(DAC4) #define __HAL_RCC_DAC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #endif /* AES */ #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) /** * @} */ /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset * @brief Force or release AHB3 peripheral reset. * @{ */ #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) #if defined(FMC_BANK1) #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) #if defined(FMC_BANK1) #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) #if defined(TIM5) #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) #endif /* TIM5 */ #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) #if defined(UART4) #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) #endif /* UART5 */ #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) #if defined(I2C4) #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) #if defined(TIM5) #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) #endif /* TIM5 */ #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) #if defined(UART4) #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) #endif /* UART5 */ #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) #if defined(I2C4) #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) /** * @} */ /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #if defined(SPI4) #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) #endif /* SPI4 */ #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #if defined(TIM20) #define __HAL_RCC_TIM20_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) #endif /* TIM20 */ #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) #endif /* HRTIM1 */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #if defined(SPI4) #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) #endif /* SPI4 */ #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #if defined(TIM20) #define __HAL_RCC_TIM20_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) #endif /* TIM20 */ #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) /** * @} */ /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) #define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) #endif /* AES */ #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) #define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) #endif /* AES */ #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) /** * @} */ /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) #if defined(UART4) #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) #if defined(USB) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) #endif /* USB */ #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) #if defined(UART4) #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) #if defined(USB) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) #endif /* USB */ #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) /** * @} */ /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U) #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U) #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U) #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U) #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) /** * @} */ /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) #define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U) #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) #define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U) #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) /** * @} */ /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U) #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U) /** * @} */ /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset * @{ */ /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. * @note The BKPSRAM is not affected by this reset. * @retval None */ #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) /** * @} */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration * @{ */ /** @brief Macros to enable or disable the RTC clock. * @note As the RTC is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the RTC * (to be done once after reset). * @note These macros must be used after the RTC clock source was selected. * @retval None */ #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) /** * @} */ /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. * @retval None */ #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x7F. * @retval None */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) /** * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication * speed because of the HSI startup time. * @note The enable of this function has not effect on the HSION bit. * This parameter can be: ENABLE or DISABLE. * @retval None */ #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. * @retval None */ #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) /** * @brief Macro to configure the External High Speed oscillator (HSE). * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. * @retval None */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ do { \ if((__STATE__) == RCC_HSE_ON) \ { \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } \ else if((__STATE__) == RCC_HSE_BYPASS) \ { \ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } \ else \ { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ } while(0) /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not * supported by this macro. User should request a transition to LSE Off * first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. * @retval None */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ if((__STATE__) == RCC_LSE_ON) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ else if((__STATE__) == RCC_LSE_BYPASS) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ else \ { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0) /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. * @note After enabling the HSI48, the application software should wait on HSI48RDY * flag to be set indicating that HSI48 clock is stable. * This parameter can be: ENABLE or DISABLE. * @retval None */ #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) /** @brief Macros to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it cannot be changed unless the * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected * * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). * @retval None */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) /** @brief Macro to get the RTC clock source. * @retval The returned value can be one of the following: * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected */ #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macros to enable or disable the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. * @retval None */ #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @retval None * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL source division factor M. * @note This function must be used only when the main PLL is disabled. * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency * of 8 MHz to limit PLL jitter. * @retval None * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) /** * @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This macro must be used only when the main PLL is disabled. * @note This macro preserves the PLL's output clocks enable state. * * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * * @param __PLLM__ specifies the division factor for PLL VCO input clock. * This parameter must be a value of @ref RCC_PLLM_Clock_Divider * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency * of 8 MHz to limit PLL jitter. * * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. * This parameter must be a number between 8 and 127. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 64 and 344 MHz. * * @param __PLLP__ specifies the division factor for SAI clock. * This parameter must be a number in the range (2 to 31). * * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. * This parameter must be in the range (2, 4, 6 or 8). * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work * correctly. * @param __PLLR__ specifies the division factor for the main system clock. * @note You have to set the PLLR parameter correctly to not exceed 170MHZ. * This parameter must be in the range (2, 4, 6 or 8). * @retval None */ #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ MODIFY_REG(RCC->PLLCFGR, \ (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ ((__PLLSOURCE__) | \ (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) /** @brief Macro to get the oscillator used as PLL clock source. * @retval The oscillator used as PLL clock source. The returned value can be one * of the following: * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. */ #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) /** * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK) * @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot * be stopped if used as System Clock. * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. * This parameter can be one or a combination of the following values: * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), * FDCAN (<=48 MHz) and QSPI (<=48 MHz). * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) * @retval None */ #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) /** * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. * This parameter can be one of the following values: * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), * FDCAN (<=48 MHz) and QSPI (<=48 MHz). * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) * @retval SET / RESET */ #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) /** * @brief Macro to configure the system clock source. * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. * @retval None */ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) /** @brief Macro to get the clock source used as system clock. * @retval The clock source used as system clock. The returned value can be one * of the following: * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. */ #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) /** * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. * @retval None */ #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 */ #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable * the selected interrupts). * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval None */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable * the selected interrupts). * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval None */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval None */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) /** @brief Check whether the RCC interrupt has occurred or not. * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. * @retval None */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) /** @brief Check whether the selected RCC flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready * @arg @ref RCC_FLAG_BORRST BOR reset * @arg @ref RCC_FLAG_OBLRST OBLRST reset * @arg @ref RCC_FLAG_PINRST Pin reset * @arg @ref RCC_FLAG_SFTRST Software reset * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset * @arg @ref RCC_FLAG_LPWRRST Low Power reset * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ ? 1U : 0U) /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup RCC_Private_Constants * @{ */ /* Defines used for Flags */ #define CR_REG_INDEX 1U #define BDCR_REG_INDEX 2U #define CSR_REG_INDEX 3U #define CRRCR_REG_INDEX 4U #define RCC_FLAG_MASK 0x1FU /* Define used for IS_RCC_CLOCKTYPE() */ #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCC_Private_Macros * @{ */ #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ ((__HSE__) == RCC_HSE_BYPASS)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ ((__PLL__) == RCC_PLL_ON)) #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ ((__HCLK__) == RCC_SYSCLK_DIV512)) #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \ ((__MCOX__) == RCC_MCO_PG10)) #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ ((__DIV__) == RCC_MCODIV_16)) #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) /** * @} */ /* Include RCC HAL Extended module */ #include "stm32g4xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_Exported_Functions * @{ */ /** @addtogroup RCC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} */ /** @addtogroup RCC_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ************************************************/ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); void HAL_RCC_EnableCSS(void); void HAL_RCC_EnableLSECSS(void); void HAL_RCC_DisableLSECSS(void); uint32_t HAL_RCC_GetSysClockFreq(void); uint32_t HAL_RCC_GetHCLKFreq(void); uint32_t HAL_RCC_GetPCLK1Freq(void); uint32_t HAL_RCC_GetPCLK2Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_RCC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc_ex.h * @author MCD Application Team * @brief Header file of RCC HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_RCC_EX_H #define STM32G4xx_HAL_RCC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup RCCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ /** * @brief RCC extended clocks structure definition */ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ #if defined(UART4) uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ #endif /* UART4 */ #if defined(UART5) uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ #endif /* UART5 */ uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ #if defined(I2C4) uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ #endif /* I2C4 */ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ uint32_t I2sClockSelection; /*!< Specifies I2S clock source. This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ #if defined(FDCAN1) uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source. This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ #endif /* FDCAN1 */ #if defined(USB) uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). This parameter can be a value of @ref RCCEx_USB_Clock_Source */ #endif /* USB */ uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source. This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ #if defined(ADC345_COMMON) uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source. This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */ #endif /* ADC345_COMMON */ #if defined(QUADSPI) uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source. This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ #endif uint32_t RTCClockSelection; /*!< Specifies RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ }RCC_PeriphCLKInitTypeDef; /** * @brief RCC_CRS Init structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ uint32_t Source; /*!< Specifies the SYNC signal source. This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ }RCC_CRSInitTypeDef; /** * @brief RCC_CRS Synchronization structure definition */ typedef struct { uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. This parameter must be a number between 0 and 0xFFFF */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x7F */ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF */ uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ }RCC_CRSSynchroInfoTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants * @{ */ /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source * @{ */ #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ /** * @} */ /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ #define RCC_PERIPHCLK_USART1 0x00000001U #define RCC_PERIPHCLK_USART2 0x00000002U #define RCC_PERIPHCLK_USART3 0x00000004U #if defined(UART4) #define RCC_PERIPHCLK_UART4 0x00000008U #endif /* UART4 */ #if defined(UART5) #define RCC_PERIPHCLK_UART5 0x00000010U #endif /* UART5 */ #define RCC_PERIPHCLK_LPUART1 0x00000020U #define RCC_PERIPHCLK_I2C1 0x00000040U #define RCC_PERIPHCLK_I2C2 0x00000080U #define RCC_PERIPHCLK_I2C3 0x00000100U #define RCC_PERIPHCLK_LPTIM1 0x00000200U #define RCC_PERIPHCLK_SAI1 0x00000400U #define RCC_PERIPHCLK_I2S 0x00000800U #if defined(FDCAN1) #define RCC_PERIPHCLK_FDCAN 0x00001000U #endif /* FDCAN1 */ #define RCC_PERIPHCLK_USB 0x00002000U #define RCC_PERIPHCLK_RNG 0x00004000U #define RCC_PERIPHCLK_ADC12 0x00008000U #if defined(ADC345_COMMON) #define RCC_PERIPHCLK_ADC345 0x00010000U #endif /* ADC345_COMMON */ #if defined(I2C4) #define RCC_PERIPHCLK_I2C4 0x00020000U #endif /* I2C4 */ #if defined(QUADSPI) #define RCC_PERIPHCLK_QSPI 0x00040000U #endif /* QUADSPI */ #define RCC_PERIPHCLK_RTC 0x00080000U /** * @} */ /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source * @{ */ #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /** * @} */ /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source * @{ */ #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) /** * @} */ /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source * @{ */ #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) /** * @} */ #if defined(UART4) /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source * @{ */ #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) /** * @} */ #endif /* UART4 */ #if defined(UART5) /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source * @{ */ #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) /** * @} */ #endif /* UART5 */ /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source * @{ */ #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) /** * @} */ /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source * @{ */ #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /** * @} */ /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source * @{ */ #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /** * @} */ /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source * @{ */ #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 /** * @} */ /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ */ #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /** * @} */ /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ #define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1 #define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0) /** * @} */ /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source * @{ */ #define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U #define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 #define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1 #define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0) /** * @} */ #if defined(FDCAN1) /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source * @{ */ #define RCC_FDCANCLKSOURCE_HSE 0x00000000U #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 #define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 /** * @} */ #endif /* FDCAN1 */ /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source * @{ */ #define RCC_RNGCLKSOURCE_HSI48 0x00000000U #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /** * @} */ /** @defgroup RCCEx_USB_Clock_Source USB Clock Source * @{ */ #define RCC_USBCLKSOURCE_HSI48 0x00000000U #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /** * @} */ /** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source * @{ */ #define RCC_ADC12CLKSOURCE_NONE 0x00000000U #define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0 #define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1 /** * @} */ #if defined(ADC345_COMMON) /** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source * @{ */ #define RCC_ADC345CLKSOURCE_NONE 0x00000000U #define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0 #define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1 /** * @} */ #endif /* ADC345_COMMON */ #if defined(I2C4) /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source * @{ */ #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 /** * @} */ #endif /* I2C4 */ #if defined(QUADSPI) /** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source * @{ */ #define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U #define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 #define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 /** * @} */ #endif /* QUADSPI */ /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ */ #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ /** * @} */ /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ #define RCC_CRS_NONE 0x00000000U #define RCC_CRS_TIMEOUT 0x00000001U #define RCC_CRS_SYNCOK 0x00000002U #define RCC_CRS_SYNCWARN 0x00000004U #define RCC_CRS_SYNCERR 0x00000008U #define RCC_CRS_SYNCMISS 0x00000010U #define RCC_CRS_TRIMOVF 0x00000020U /** * @} */ /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ */ #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** * @} */ /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider * @{ */ #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ /** * @} */ /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity * @{ */ #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} */ /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault * @{ */ #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} */ /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault * @{ */ #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ /** * @} */ /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ /** * @} */ /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection * @{ */ #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ /** * @} */ /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources * @{ */ #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ /** * @} */ /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags * @{ */ #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros * @{ */ /** @brief Macro to configure the USART1 clock (USART1CLK). * * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock * @retval None */ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) /** @brief Macro to configure the USART2 clock (USART2CLK). * * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock * @retval None */ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) /** @brief Macro to configure the USART3 clock (USART3CLK). * * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock * @retval None */ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) #if defined(UART4) /** @brief Macro to configure the UART4 clock (UART4CLK). * * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. * This parameter can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock * @retval None */ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) /** @brief Macro to get the UART4 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock */ #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) #endif /* UART4 */ #if defined(UART5) /** @brief Macro to configure the UART5 clock (UART5CLK). * * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. * This parameter can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock * @retval None */ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) /** @brief Macro to get the UART5 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock */ #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) #endif /* UART5 */ /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). * * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock * @retval None */ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) /** @brief Macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) /** @brief Macro to configure the I2C1 clock (I2C1CLK). * * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock * @retval None */ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) /** @brief Macro to configure the I2C2 clock (I2C2CLK). * * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock * @retval None */ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) /** @brief Macro to configure the I2C3 clock (I2C3CLK). * * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock * @retval None */ #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) #if defined(I2C4) /** @brief Macro to configure the I2C4 clock (I2C4CLK). * * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock * @retval None */ #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) /** @brief Macro to get the I2C4 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock */ #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) #endif /* I2C4 */ /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock * @retval None */ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) /** @brief Macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock */ #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) /** * @brief Macro to configure the SAI1 clock source. * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived * from the HSI, system PLL, System Clock or external clock. * This parameter can be one of the following values: * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI * * @retval None */ #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI * */ #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) /** * @brief Macro to configure the I2S clock source. * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived * from the HSI, system PLL, System Clock or external clock. * This parameter can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI * * @retval None */ #define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__)) /** @brief Macro to get the I2S clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI * */ #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL))) #if defined(FDCAN1) /** * @brief Macro to configure the FDCAN clock source. * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived * from the HSE, system PLL or PCLK1. * This parameter can be one of the following values: * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 * * @retval None */ #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) /** @brief Macro to get the FDCAN clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 * */ #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL))) #endif /* FDCAN1 */ /** @brief Macro to configure the RNG clock. * * @note USB and RNG peripherals share the same 48MHz clock source. * * @param __RNG_CLKSOURCE__ specifies the RNG clock source. * This parameter can be one of the following values: * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock * @retval None */ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) /** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock */ #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #if defined(USB) /** @brief Macro to configure the USB clock (USBCLK). * * @note USB, RNG peripherals share the same 48MHz clock source. * * @param __USB_CLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock * @retval None */ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #endif /* USB */ /** @brief Macro to configure the ADC12 interface clock. * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock * @retval None */ #define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__)) /** @brief Macro to get the ADC12 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock */ #define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL)) #if defined(ADC345_COMMON) /** @brief Macro to configure the ADC345 interface clock. * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock * @retval None */ #define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__) /** @brief Macro to get the ADC345 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock */ #define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL)) #endif /* ADC345_COMMON */ #if defined(QUADSPI) /** @brief Macro to configure the QuadSPI clock. * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source. * This parameter can be one of the following values: * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock * @retval None */ #define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__) /** @brief Macro to get the QuadSPI clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock */ #define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL)) #endif /* QUADSPI */ /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ /** * @brief Enable the RCC LSE CSS Extended Interrupt Line. * @retval None */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Extended Interrupt Line. * @retval None */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Event Line. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Event Line. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. * @retval EXTI RCC LSE CSS Line Status. */ #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) /** * @brief Clear the RCC LSE CSS EXTI flag. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) /** * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval None */ #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) /** * @brief Disable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval None */ #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) /** @brief Check whether the CRS interrupt has occurred or not. * @param __INTERRUPT__ specifies the CRS interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) /** @brief Clear the CRS interrupt pending bits * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt */ /* CRS IT Error Mask */ #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ } \ else \ { \ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ } \ } while(0) /** * @brief Check whether the specified CRS flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning * @arg @ref RCC_CRS_FLAG_ERR Error * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed * @retval The new state of _FLAG_ (TRUE or FALSE). */ #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) /** * @brief Clear the CRS specified FLAG. * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning * @arg @ref RCC_CRS_FLAG_ERR Error * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR * @retval None */ /* CRS Flag Error Mask */ #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ } \ else \ { \ WRITE_REG(CRS->ICR, (__FLAG__)); \ } \ } while(0) /** * @} */ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features * @{ */ /** * @brief Enable the oscillator clock for frequency error counter. * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) /** * @brief Disable the oscillator clock for frequency error counter. * @retval None */ #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) /** * @brief Enable the automatic hardware adjustment of TRIM bits. * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** * @brief Enable or disable the automatic hardware adjustment of TRIM bits. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency * of the synchronization source after prescaling. It is then decreased by one in order to * reach the expected synchronization on the zero value. The formula is the following: * RELOAD = (fTARGET / fSYNC) -1 * @param __FTARGET__ Target frequency (value in Hz) * @param __FSYNC__ Synchronization signal frequency (value in Hz) * @retval None */ #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCCEx_Exported_Functions * @{ */ /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** * @} */ /** @addtogroup RCCEx_Exported_Functions_Group2 * @{ */ void HAL_RCCEx_EnableLSECSS(void); void HAL_RCCEx_DisableLSECSS(void); void HAL_RCCEx_EnableLSECSS_IT(void); void HAL_RCCEx_LSECSS_IRQHandler(void); void HAL_RCCEx_LSECSS_Callback(void); void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); void HAL_RCCEx_DisableLSCO(void); /** * @} */ /** @addtogroup RCCEx_Exported_Functions_Group3 * @{ */ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); void HAL_RCCEx_CRS_IRQHandler(void); void HAL_RCCEx_CRS_SyncOkCallback(void); void HAL_RCCEx_CRS_SyncWarnCallback(void); void HAL_RCCEx_CRS_ExpectedSyncCallback(void); void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCCEx_Private_Macros * @{ */ #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G471xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G431xx) || defined(STM32G441xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32GBK1CB) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #endif /* STM32G474xx || STM32G484xx */ #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) #if defined(UART4) #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) #endif /* UART4 */ #if defined(UART5) #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) #endif /* UART5 */ #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) #if defined(I2C4) #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) #endif /* I2C4 */ #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) #define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \ ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI)) #if defined(FDCAN1) #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) #endif /* FDCAN1 */ #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) #if defined(USB) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) #endif /* USB */ #define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK)) #if defined(ADC345_COMMON) #define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK)) #endif /* ADC345_COMMON */ #if defined(QUADSPI) #define IS_RCC_QSPICLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)) #endif /* QUADSPI */ #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_RCC_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim.h * @author MCD Application Team * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_TIM_H #define STM32G4xx_HAL_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIM_Exported_Types TIM Exported Types * @{ */ /** * @brief TIM Time base Configuration Structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** * @brief TIM Output Compare Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate Pulse value */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ } TIM_OC_InitTypeDef; /** * @brief TIM One Pulse Mode Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate Pulse value */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; /** * @brief TIM Input Capture Configuration Structure definition */ typedef struct { uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_IC_InitTypeDef; /** * @brief TIM Encoder Configuration Structure definition */ typedef struct { uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; /** * @brief Clock Configuration Handle Structure definition */ typedef struct { uint32_t ClockSource; /*!< TIM clock sources This parameter can be a value of @ref TIM_Clock_Source */ uint32_t ClockPolarity; /*!< TIM clock polarity This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ uint32_t ClockFilter; /*!< TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClockConfigTypeDef; /** * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { uint32_t ClearInputState; /*!< TIM clear Input state This parameter can be ENABLE or DISABLE */ uint32_t ClearInputSource; /*!< TIM clear Input sources This parameter can be a value of @ref TIM_ClearInput_Source */ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; /** * @brief TIM Master configuration Structure definition * @note Advanced timers provide TRGO2 internal line which is redirected * to the ADC */ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode @note When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode. */ } TIM_MasterConfigTypeDef; /** * @brief TIM Slave configuration Structure definition */ typedef struct { uint32_t SlaveMode; /*!< Slave mode selection This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_SlaveConfigTypeDef; /** * @brief TIM Break input(s) and Dead time configuration Structure definition * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable * filter and polarity. */ typedef struct { uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** * @brief HAL State structures definition */ typedef enum { HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; /** * @brief TIM Channel States definition */ typedef enum { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ } HAL_TIM_ChannelStateTypeDef; /** * @brief DMA Burst States definition */ typedef enum { HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ } HAL_TIM_DMABurstStateTypeDef; /** * @brief HAL Active channel structures definition */ typedef enum { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; /** * @brief TIM Time Base Handle Structure definition */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) typedef struct __TIM_HandleTypeDef #else typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { TIM_TypeDef *Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } TIM_HandleTypeDef; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief HAL TIM Callback ID enumeration definition */ typedef enum { HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** * @brief HAL TIM Callback pointer definition */ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_Constants TIM Exported Constants * @{ */ /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ #define TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */ #define TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */ #if defined (COMP5) #define TIM_CLEARINPUTSOURCE_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_CLEARINPUTSOURCE_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_CLEARINPUTSOURCE_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */ #endif /* COMP7 */ /** * @} */ /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ #define TIM_DMABASE_CR1 0x00000000U #define TIM_DMABASE_CR2 0x00000001U #define TIM_DMABASE_SMCR 0x00000002U #define TIM_DMABASE_DIER 0x00000003U #define TIM_DMABASE_SR 0x00000004U #define TIM_DMABASE_EGR 0x00000005U #define TIM_DMABASE_CCMR1 0x00000006U #define TIM_DMABASE_CCMR2 0x00000007U #define TIM_DMABASE_CCER 0x00000008U #define TIM_DMABASE_CNT 0x00000009U #define TIM_DMABASE_PSC 0x0000000AU #define TIM_DMABASE_ARR 0x0000000BU #define TIM_DMABASE_RCR 0x0000000CU #define TIM_DMABASE_CCR1 0x0000000DU #define TIM_DMABASE_CCR2 0x0000000EU #define TIM_DMABASE_CCR3 0x0000000FU #define TIM_DMABASE_CCR4 0x00000010U #define TIM_DMABASE_BDTR 0x00000011U #define TIM_DMABASE_CCR5 0x00000012U #define TIM_DMABASE_CCR6 0x00000013U #define TIM_DMABASE_CCMR3 0x00000014U #define TIM_DMABASE_DTR2 0x00000015U #define TIM_DMABASE_ECR 0x00000016U #define TIM_DMABASE_TISEL 0x00000017U #define TIM_DMABASE_AF1 0x00000018U #define TIM_DMABASE_AF2 0x00000019U #define TIM_DMABASE_OR 0x0000001AU /** * @} */ /** @defgroup TIM_Event_Source TIM Event Source * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ /** * @} */ /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** * @} */ /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ /** * @} */ /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ /** * @} */ /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap * @{ */ #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ /** * @} */ /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ /** * @} */ /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ /** * @} */ /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ /** * @} */ /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ /** * @} */ /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ /** * @} */ /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ /** * @} */ /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity * @{ */ #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ /** * @} */ /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ /** * @} */ /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ #define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ #define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ /** * @} */ /** @defgroup TIM_Interrupt_definition TIM interrupt Definition * @{ */ #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ #define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ #define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ #define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ #define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ /** * @} */ /** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** * @} */ /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ /** * @} */ /** @defgroup TIM_CC_DMA_Request CCx DMA request selection * @{ */ #define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ #define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ /** * @} */ /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ #define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ #define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ #define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ #define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ /** * @} */ /** @defgroup TIM_Channel TIM Channel * @{ */ #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} */ /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ #if defined (TIM5) #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ #endif /* TIM5 */ #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ #if defined (TIM20) #define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ #endif /* TIM20 */ #define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ /** * @} */ /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** * @} */ /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ */ #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state * @{ */ #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state * @{ */ #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_Lock_level TIM Lock level * @{ */ #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ /** * @} */ /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable * @{ */ #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ /** * @} */ /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ /** * @} */ /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode * @{ */ #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ /** * @} */ /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ /** * @} */ /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity * @{ */ #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ /** * @} */ /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode * @{ */ #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ /** * @} */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ /** * @} */ /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ /** * @} */ /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ /** * @} */ /** @defgroup TIM_Slave_Mode TIM Slave mode * @{ */ #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ #define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ /** * @} */ /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes * @{ */ #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ #define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ #define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ /** * @} */ /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ #if defined (TIM5) #define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */ #endif /* TIM5 */ #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ #if defined (TIM20) #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ #endif /* TIM20 */ #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ /** * @} */ /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ /** * @} */ /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ /** @defgroup DMA_Handle_index TIM DMA Handle Index * @{ */ #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ /** @defgroup Channel_CC_State TIM Capture/Compare Channel State * @{ */ #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ /** * @} */ /** @defgroup TIM_Break_System TIM Break System * @{ */ #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */ #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */ #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */ #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /** @defgroup TIM_Exported_Macros TIM Exported Macros * @{ */ /** @brief Reset TIM handle state. * @param __HANDLE__ TIM handle. * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ (__HANDLE__)->Base_MspInitCallback = NULL; \ (__HANDLE__)->Base_MspDeInitCallback = NULL; \ (__HANDLE__)->IC_MspInitCallback = NULL; \ (__HANDLE__)->IC_MspDeInitCallback = NULL; \ (__HANDLE__)->OC_MspInitCallback = NULL; \ (__HANDLE__)->OC_MspDeInitCallback = NULL; \ (__HANDLE__)->PWM_MspInitCallback = NULL; \ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ (__HANDLE__)->Encoder_MspInitCallback = NULL; \ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ } while(0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ } while(0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval None */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) /** @brief Disable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval None */ #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @arg TIM_FLAG_IDX: Index interrupt flag * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @arg TIM_FLAG_IDX: Index interrupt flag * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** * @brief Check whether the specified TIM interrupt source is enabled or not. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval The state of TIM_IT (SET or RESET). */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read * in an atomic way. * @param __HANDLE__ TIM handle. * @retval None mode. */ #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) /** * @brief Disable update interrupt flag (UIF) remapping. * @param __HANDLE__ TIM handle. * @retval None mode. */ #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) /** * @brief Get update interrupt flag (UIF) copy status. * @param __COUNTER__ Counter value. * @retval The state of UIFCPY (TRUE or FALSE). mode. */ #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) /** * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in * case of 32 bits counter TIM instance. * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while(0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do{ \ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while(0) /** * @brief Get the TIM Clock Division value on runtime. * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do{ \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ } while(0) /** * @brief Get the TIM Input Capture prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval The input capture prescaler can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) /** * @brief Get the TIM Capture Compare Register value on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @arg TIM_CHANNEL_5: get capture/compare 5 register value * @arg TIM_CHANNEL_6: get capture/compare 6 register value * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) /** * @brief Set the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval None */ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) /** * @brief Reset the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) /** * @brief Enable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @note When fast mode is enabled an active edge on the trigger input acts * like a compare match on CCx output. Delay to sample the trigger * input and to activate CCx output is reduced to 3 clock cycles. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. * @retval None */ #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) /** * @brief Disable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @note When fast mode is disabled CCx output behaves normally depending * on counter and CCRx values even when the trigger is ON. The minimum * delay to activate CCx output when an active edge occurs on the * trigger input is 5 clock cycles. * @retval None */ #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit * _ Update generation through the slave mode controller * @retval None */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ do{ \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) /** @brief Select the Capture/compare DMA request source. * @param __HANDLE__ specifies the TIM Handle. * @param __CCDMA__ specifies Capture/compare DMA request source * This parameter can be one of the following values: * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event * @retval None */ #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) /** * @} */ /* End of exported macros ----------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_Private_Constants TIM Private Constants * @{ */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) /** * @} */ /* End of private constants --------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ #if defined(COMP5) && defined(COMP6) && defined(COMP7) #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) #else /* COMP5 && COMP6 && COMP7 */ #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) #endif /* COMP5 && COMP6 && COMP7 */ #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ ((__BASE__) == TIM_DMABASE_SMCR) || \ ((__BASE__) == TIM_DMABASE_DIER) || \ ((__BASE__) == TIM_DMABASE_SR) || \ ((__BASE__) == TIM_DMABASE_EGR) || \ ((__BASE__) == TIM_DMABASE_CCMR1) || \ ((__BASE__) == TIM_DMABASE_CCMR2) || \ ((__BASE__) == TIM_DMABASE_CCER) || \ ((__BASE__) == TIM_DMABASE_CNT) || \ ((__BASE__) == TIM_DMABASE_PSC) || \ ((__BASE__) == TIM_DMABASE_ARR) || \ ((__BASE__) == TIM_DMABASE_RCR) || \ ((__BASE__) == TIM_DMABASE_CCR1) || \ ((__BASE__) == TIM_DMABASE_CCR2) || \ ((__BASE__) == TIM_DMABASE_CCR3) || \ ((__BASE__) == TIM_DMABASE_CCR4) || \ ((__BASE__) == TIM_DMABASE_BDTR) || \ ((__BASE__) == TIM_DMABASE_CCMR3) || \ ((__BASE__) == TIM_DMABASE_CCR5) || \ ((__BASE__) == TIM_DMABASE_CCR6) || \ ((__BASE__) == TIM_DMABASE_AF1) || \ ((__BASE__) == TIM_DMABASE_AF2) || \ ((__BASE__) == TIM_DMABASE_TISEL) || \ ((__BASE__) == TIM_DMABASE_DTR2) || \ ((__BASE__) == TIM_DMABASE_ECR) || \ ((__BASE__) == TIM_DMABASE_OR)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ ((__MODE__) == TIM_UIFREMAP_ENABLE)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ ((__STATE__) == TIM_OCFAST_ENABLE)) #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ ((__POLARITY__) == TIM_OCPOLARITY_LOW)) #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ ((__STATE__) == TIM_OCIDLESTATE_RESET)) #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ ((__SELECTION__) == TIM_ICSELECTION_TRC)) #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ ((__CHANNEL__) != (TIM_CHANNEL_6))) #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12) || \ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4) || \ ((__CHANNEL__) == TIM_CHANNEL_5) || \ ((__CHANNEL__) == TIM_CHANNEL_6) || \ ((__CHANNEL__) == TIM_CHANNEL_ALL)) #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4)) #if defined(TIM5) && defined(TIM20) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #elif defined(TIM5) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #elif defined(TIM20) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #else #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #endif /* TIM5 && TIM20 */ #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ ((__STATE__) == TIM_OSSR_DISABLE)) #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ ((__STATE__) == TIM_OSSI_DISABLE)) #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ ((__LEVEL__) == TIM_LOCKLEVEL_3)) #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ ((__STATE__) == TIM_BREAK2_DISABLE)) #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ ((__SOURCE__) == TIM_TRGO_ENABLE) || \ ((__SOURCE__) == TIM_TRGO_UPDATE) || \ ((__SOURCE__) == TIM_TRGO_OC1) || \ ((__SOURCE__) == TIM_TRGO_OC1REF) || \ ((__SOURCE__) == TIM_TRGO_OC2REF) || \ ((__SOURCE__) == TIM_TRGO_OC3REF) || \ ((__SOURCE__) == TIM_TRGO_OC4REF) || \ ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ ((__SOURCE__) == TIM_TRGO2_OC1) || \ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ ((__MODE__) == TIM_SLAVEMODE_RESET) || \ ((__MODE__) == TIM_SLAVEMODE_GATED) || \ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_INACTIVE) || \ ((__MODE__) == TIM_OCMODE_TOGGLE) || \ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ (__HANDLE__)->ChannelState[5]) #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ (__HANDLE__)->ChannelState[0] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[1] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[2] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[3] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[4] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[5] = \ (__CHANNEL_STATE__); \ } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ (__HANDLE__)->ChannelNState[3]) #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ (__HANDLE__)->ChannelNState[0] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[1] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[2] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[3] = \ (__CHANNEL_STATE__); \ } while(0) /** * @} */ /* End of private macros -----------------------------------------------------*/ /* Include TIM HAL Extended module */ #include "stm32g4xx_hal_tim_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @{ */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @{ */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @{ */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @{ */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @{ */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @{ */ /* Timer Encoder functions ****************************************************/ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief IRQ handler management * @{ */ /* Interrupt Handler functions ***********************************************/ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief Peripheral State functions * @{ */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_TIM_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim_ex.h * @author MCD Application Team * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_TIM_EX_H #define STM32G4xx_HAL_TIM_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup TIMEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types * @{ */ /** * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; /** * @brief TIM Break/Break2 input configuration */ typedef struct { uint32_t Source; /*!< Specifies the source of the timer break input. This parameter can be a value of @ref TIMEx_Break_Input_Source */ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ } TIMEx_BreakInputConfigTypeDef; /** * @brief TIM Encoder index configuration */ typedef struct { uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */ uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */ uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */ uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ } TIMEx_EncoderIndexConfigTypeDef; /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants * @{ */ /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ #define TIM_TIM1_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ #define TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM1_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM1_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM1_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */ #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */ #if defined (ADC4) #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */ #define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */ #define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */ #endif /* ADC4 */ #define TIM_TIM2_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ #define TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM2_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM2_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM2_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ #if defined (TIM5) #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ #define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */ #define TIM_TIM3_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ #define TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM3_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM3_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM3_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ #define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */ #define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */ #define TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */ #define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */ #define TIM_TIM4_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ #define TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM4_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM4_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM4_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */ #if defined (TIM5) #define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ #if defined (TIM5) #define TIM_TIM5_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define TIM_TIM5_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ #define TIM_TIM5_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM5_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM5_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM5_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */ #define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */ #endif /* TIM5 */ #define TIM_TIM8_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ #define TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM8_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM8_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM8_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */ #define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */ #define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */ #if defined (ADC3) #define TIM_TIM8_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */ #define TIM_TIM8_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */ #endif /* ADC3 */ #if defined (TIM20) #define TIM_TIM20_ETR_GPIO 0x00000000U /*!< ETR input is connected to GPIO */ #define TIM_TIM20_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */ #define TIM_TIM20_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */ #define TIM_TIM20_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */ #define TIM_TIM20_ETR_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM20_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM20_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM20_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM20_ETR_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */ #if defined (ADC5) #define TIM_TIM20_ETR_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */ #endif /* ADC5 */ #endif /* TIM20 */ /** * @} */ /** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ #define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ #define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ /** * @} */ /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /*!< The COMP3 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP4 0x00000010U /*!< The COMP4 output is connected to the break input */ #if defined(COMP5) #define TIM_BREAKINPUTSOURCE_COMP5 0x00000020U /*!< The COMP5 output is connected to the break input */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_BREAKINPUTSOURCE_COMP6 0x00000040U /*!< The COMP6 output is connected to the break input */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_BREAKINPUTSOURCE_COMP7 0x00000080U /*!< The COMP7 output is connected to the break input */ #endif /* COMP7 */ /** * @} */ /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ /** * @} */ /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ /** * @} */ /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection * @{ */ #define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */ #define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */ #define TIM_TIM1_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */ #define TIM_TIM1_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */ #define TIM_TIM2_TI1_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */ #define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */ #define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */ #define TIM_TIM2_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */ #define TIM_TIM2_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM2_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #define TIM_TIM2_TI2_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */ #define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */ #define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */ #define TIM_TIM2_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */ #define TIM_TIM2_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */ #if defined (COMP6) #define TIM_TIM2_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #define TIM_TIM2_TI3_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */ #define TIM_TIM2_TI3_COMP4 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */ #define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */ #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */ #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */ #define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */ #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */ #define TIM_TIM3_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */ #define TIM_TIM3_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM3_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM3_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM3_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM3_TI2_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */ #define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */ #define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */ #define TIM_TIM3_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */ #define TIM_TIM3_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM3_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM3_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM3_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM3_TI3_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */ #define TIM_TIM3_TI3_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */ #define TIM_TIM4_TI1_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */ #define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */ #define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */ #define TIM_TIM4_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */ #define TIM_TIM4_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM4_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM4_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM4_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM4_TI2_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */ #define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */ #define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */ #define TIM_TIM4_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */ #define TIM_TIM4_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM4_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM4_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM4_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM4_TI3_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */ #if defined (COMP5) #define TIM_TIM4_TI3_COMP5 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */ #endif /* COMP5 */ #define TIM_TIM4_TI4_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */ #if defined (COMP6) #define TIM_TIM4_TI4_COMP6 TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(TIM5) #define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */ #define TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */ #define TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */ #define TIM_TIM5_TI1_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */ #define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */ #define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */ #define TIM_TIM5_TI1_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */ #define TIM_TIM5_TI1_COMP4 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM5_TI1_COMP5 TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM5_TI1_COMP6 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM5_TI1_COMP7 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM5_TI2_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */ #define TIM_TIM5_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */ #define TIM_TIM5_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */ #define TIM_TIM5_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */ #define TIM_TIM5_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM5_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM5_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM5_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #endif /* TIM5 */ #define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */ #define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */ #define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */ #define TIM_TIM8_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */ #define TIM_TIM8_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */ #define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */ #define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */ #define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */ #define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */ #if defined (COMP5) #define TIM_TIM15_TI1_COMP5 TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP7) #define TIM_TIM15_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */ #define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */ #define TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */ #if defined (COMP6) #define TIM_TIM15_TI2_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM15_TI2_COMP7 TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */ #if defined (COMP6) #define TIM_TIM16_TI1_COMP6 TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */ #define TIM_TIM16_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */ #define TIM_TIM16_TI1_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */ #define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */ #define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */ #define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */ #if defined (COMP5) #define TIM_TIM17_TI1_COMP5 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */ #define TIM_TIM17_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */ #define TIM_TIM17_TI1_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */ #define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */ #define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */ #if defined (TIM20) #define TIM_TIM20_TI1_GPIO 0x00000000U /*!< TIM20 input 1 is connected to GPIO */ #define TIM_TIM20_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */ #define TIM_TIM20_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */ #define TIM_TIM20_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */ #define TIM_TIM20_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */ #endif /* TIM20 */ /** * @} */ /** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling * @{ */ #define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */ #define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position * @{ */ #define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */ #define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */ #define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */ #define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */ #define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */ #define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction * @{ */ #define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */ #define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */ #define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity * @{ */ #define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler * @{ */ #define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros * @{ */ /** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __CNTCLK__ counter clock frequency (in Hz) * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __FREQ__ output signal frequency (in Hz) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U /** * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required * output signal frequency. * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __FREQ__ output signal frequency (in Hz) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) */ #define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U /** * @brief HELPER macro calculating the compare value required to achieve the required timer output compare * active/inactive delay. * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @retval Compare value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer * output compare active/inactive delay. * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @retval Compare value (between Min_Data=0 and Max_Data=65519) */ #define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration * (when the timer operates in one pulse mode). * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @param __PULSE__ pulse duration (in us) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \ + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required * pulse duration (when the timer operates in one pulse mode). * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @param __PULSE__ pulse duration (in us) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) */ #define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @} */ /* End of exported macro -----------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros * @{ */ #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) #if defined (COMP5) && defined (COMP6) && defined (COMP7) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP5) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP6) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP7)) #else #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4)) #endif /* COMP5 && COMP6 && COMP7 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) #define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) #define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) #if defined(TIM5) && defined(TIM20) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM20) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR10)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE)))) #elif defined(TIM5) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) #elif defined(TIM20) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM20) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) #else #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) #endif /* TIM5 && TIM20 */ #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ (IS_TIM_OC_MODE(__MODE__) \ && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1))) #define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4)) #define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE) #define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU) #define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U) #define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \ || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX)) #define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \ ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED)) #define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8)) #define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL) #define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1)) #define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN)) /** * @} */ /* End of private macro ------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ /* Timer Hall Sensor functions **********************************************/ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @{ */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @{ */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @{ */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Extended Control functions ************************************************/ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth); HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source); HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime); HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime); HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig); HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ /* Extended Callback **********************************************************/ void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_TIM_EX_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_ll_adc.h * @author MCD Application Team * @brief Header file of ADC LL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_LL_ADC_H #define STM32G4xx_LL_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx.h" /** @addtogroup STM32G4xx_LL_Driver * @{ */ #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) /** @defgroup ADC_LL ADC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Constants ADC Private Constants * @{ */ /* Internal mask for ADC group regular sequencer: */ /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ /* - sequencer register offset */ /* - sequencer rank bits position into the selected register */ /* Internal register offset for ADC group regular sequencer configuration */ /* (offset placed into a spare area of literal definition) */ #define ADC_SQR1_REGOFFSET (0x00000000UL) #define ADC_SQR2_REGOFFSET (0x00000100UL) #define ADC_SQR3_REGOFFSET (0x00000200UL) #define ADC_SQR4_REGOFFSET (0x00000300UL) #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos) #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos) #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos) #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos) #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos) #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos) #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos) #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos) #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos) #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos) #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos) #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos) #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos) #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos) #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos) #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos) /* Internal mask for ADC group injected sequencer: */ /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ /* - data register offset */ /* - sequencer rank bits position into the selected register */ /* Internal register offset for ADC group injected data register */ /* (offset placed into a spare area of literal definition) */ #define ADC_JDR1_REGOFFSET (0x00000000UL) #define ADC_JDR2_REGOFFSET (0x00000100UL) #define ADC_JDR3_REGOFFSET (0x00000200UL) #define ADC_JDR4_REGOFFSET (0x00000300UL) #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/ /* Definition of ADC group injected sequencer bits information to be inserted */ /* into ADC group injected sequencer ranks literals definition. */ #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos) #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos) #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos) #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos) /* Internal mask for ADC group regular trigger: */ /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ /* - regular trigger edge */ #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos) #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos) /* Internal mask for ADC group injected trigger: */ /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ /* - injected trigger source */ /* - injected trigger edge */ #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group injected trigger bits information. */ #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos) #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos) /* Internal mask for ADC channel: */ /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ /* - channel identifier defined by number */ /* - channel identifier defined by bitfield */ /* - channel differentiation between external channels (connected to */ /* GPIO pins) and internal channels (connected to internal paths) */ /* - channel sampling time defined by SMPRx register offset */ /* and SMPx bits positions into SMPRx register */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos) #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ /* Channel differentiation between external and internal channels */ #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /* Internal register offset for ADC channel sampling time configuration */ /* (offset placed into a spare area of literal definition) */ #define ADC_SMPR1_REGOFFSET (0x00000000UL) #define ADC_SMPR2_REGOFFSET (0x02000000UL) #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_NUMBER (0x00000000UL) #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2) #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3) #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2) #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \ ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4) #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1) /* Definition of channels ID bitfield information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0) #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1) #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2) #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3) #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4) #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5) #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6) #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7) #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8) #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9) #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10) #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11) #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12) #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13) #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14) #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15) #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16) #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17) #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18) /* Definition of channels sampling time information to be inserted into */ /* channels literals definition. */ /* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position */ /* in register. */ #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Internal mask for ADC mode single or differential ended: */ /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */ /* the relevant bits for: */ /* (concatenation of multiple bits used in different registers) */ /* - ADC calibration: calibration start, calibration factor get or set */ /* - ADC channels: set each ADC channel ending mode */ #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */ #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */ #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */ /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ /* (concatenation of multiple bits used in different analog watchdogs, */ /* (feature of several watchdogs not available on all STM32 series)). */ /* - analog watchdog 1: monitored channel defined by number, */ /* selection of ADC group (ADC groups regular and-or injected). */ /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ /* selection on groups. */ /* Internal register offset for ADC analog watchdog channel configuration */ #define ADC_AWD_CR1_REGOFFSET (0x00000000UL) #define ADC_AWD_CR2_REGOFFSET (0x00100000UL) #define ADC_AWD_CR3_REGOFFSET (0x00200000UL) /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ /* Internal mask for ADC offset: */ /* Internal register offset for ADC offset instance configuration */ #define ADC_OFR1_REGOFFSET (0x00000000UL) #define ADC_OFR2_REGOFFSET (0x00000001UL) #define ADC_OFR3_REGOFFSET (0x00000002UL) #define ADC_OFR4_REGOFFSET (0x00000003UL) #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \ | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) /* ADC registers bits positions */ #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos) #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos) #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos) #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos) #define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos) /* ADC registers bits groups */ #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ | ADC_CR_JADSTART | ADC_CR_JADSTP \ | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL2_TEMP (110L) /* Temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance +-10 mV) (unit: mV). */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Macros ADC Private Macros * @{ */ /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure * @{ */ /** * @brief Structure definition of some features of ADC common parameters * and multimode * (all ADC instances belonging to the same ADC common instance). * @note The setting of these parameters by function @ref LL_ADC_CommonInit() * is conditioned to ADC instances state (all ADC instances * sharing the same ADC common instance): * All ADC instances sharing the same ADC common instance must be * disabled. */ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE @note On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ #if defined(ADC_MULTIMODE_SUPPORT) uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ #endif /* ADC_MULTIMODE_SUPPORT */ } LL_ADC_CommonInitTypeDef; /** * @brief Structure definition of some features of ADC instance. * @note These parameters have an impact on ADC scope: ADC instance. * Affects both group regular and group injected (availability * of ADC group injected depends on STM32 series). * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Instance . * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. */ typedef struct { uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ uint32_t DataAlignment; /*!< Set ADC conversion data alignment. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ uint32_t LowPowerMode; /*!< Set ADC low power mode. This parameter can be a value of @ref ADC_LL_EC_LP_MODE This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ } LL_ADC_InitTypeDef; /** * @brief Structure definition of some features of ADC group regular. * @note These parameters have an impact on ADC scope: ADC group regular. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "REG"). * @note The setting of these parameters by function @ref LL_ADC_REG_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. */ typedef struct { uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge(default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE @note This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more). This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ } LL_ADC_REG_InitTypeDef; /** * @brief Structure definition of some features of ADC group injected. * @note These parameters have an impact on ADC scope: ADC group injected. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "INJ"). * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. */ typedef struct { uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE @note This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more). This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ } LL_ADC_INJ_InitTypeDef; /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants * @{ */ /** @defgroup ADC_LL_EC_FLAG ADC flags * @brief Flags defines which can be used with LL_ADC_ReadReg function * @{ */ #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */ #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */ #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */ #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */ #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */ #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */ #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */ #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */ #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */ #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */ #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */ #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */ #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */ #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */ #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */ #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */ #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */ #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */ #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */ #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions * @{ */ #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */ #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */ #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */ #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ /** * @} */ /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose * @{ */ /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 4 */ #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with prescaler division by 8 */ #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */ #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 12 */ #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */ #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */ #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */ #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */ #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */ /** * @} */ /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels * @{ */ /* Note: Other measurement paths to internal channels may be available */ /* (connections to other peripherals). */ /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */ /** * @} */ /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ /** * @} */ /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset instance * @{ */ #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */ #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */ #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */ #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or injected) */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state * @{ */ #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (setting offset instance wise) */ #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (setting offset instance wise) */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign * @{ */ #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative */ #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode * @{ */ #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset instance 1, 2, 3 or 4) */ #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset instance 1, 2, 3 or 4) */ /** * @} */ /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ /** * @} */ /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number * @{ */ #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP \ | ADC_CHANNEL_0_BITFIELD) /*!< ADC channel ADCx_IN0 */ #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP \ | ADC_CHANNEL_1_BITFIELD) /*!< ADC channel ADCx_IN1 */ #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP \ | ADC_CHANNEL_2_BITFIELD) /*!< ADC channel ADCx_IN2 */ #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP \ | ADC_CHANNEL_3_BITFIELD) /*!< ADC channel ADCx_IN3 */ #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP \ | ADC_CHANNEL_4_BITFIELD) /*!< ADC channel ADCx_IN4 */ #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP \ | ADC_CHANNEL_5_BITFIELD) /*!< ADC channel ADCx_IN5 */ #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP \ | ADC_CHANNEL_6_BITFIELD) /*!< ADC channel ADCx_IN6 */ #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP \ | ADC_CHANNEL_7_BITFIELD) /*!< ADC channel ADCx_IN7 */ #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP \ | ADC_CHANNEL_8_BITFIELD) /*!< ADC channel ADCx_IN8 */ #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP \ | ADC_CHANNEL_9_BITFIELD) /*!< ADC channel ADCx_IN9 */ #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \ | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \ | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \ | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \ | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \ | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \ | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \ ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \ ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \ ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to internal temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to internal temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availability */ #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ #define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ #define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ #define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \ ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ /** * @} */ /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \ ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \ ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \ ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \ ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** * @} */ /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge * @{ */ #define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1) /*!< ADC group regular conversion trigger polarity set to falling edge */ #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode * @{ */ #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */ #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */ #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: trigger rising edge for start sampling, trigger falling edge for stop sampling and start conversion */ /** * @} */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} */ /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ #define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ #if defined(ADC_SMPR1_SMPPLUS) /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration * @{ */ #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */ #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */ /** * @} */ #endif /* ADC_SMPR1_SMPPLUS */ /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_SQR1_L_1) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_SQR1_L_2) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (ADC_SQR1_L_2 | ADC_SQR1_L_1 \ | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \ | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ | ADC_SQR1_L_1) /*!< ADC group regular sequencerenable with 15 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \ | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_REG_SEQ_DISCONT_2RANKS (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ #define LL_ADC_REG_SEQ_DISCONT_3RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ #define LL_ADC_REG_SEQ_DISCONT_4RANKS (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \ | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \ | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \ | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \ | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source * @{ */ #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */ #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \ ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices.Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \ ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availability */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \ ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */ #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \ ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge * @{ */ #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode * @{ */ #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode * @{ */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length * @{ */ #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode * @{ */ #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */ #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \ | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */ #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \ | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */ #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \ | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */ #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \ | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */ /** * @} */ /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_6CYCLES_5 (ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_24CYCLES_5 (ADC_SMPR2_SMP10_1 \ | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 \ | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 \ | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 \ | ADC_SMPR2_SMP10_1 \ | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ /** * @} */ /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number * @{ */ #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK \ | ADC_CFGR_JAWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN0, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN0, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN0, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN1, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN1, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN1, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN2, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN2, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN2, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN3, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN3, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN3, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN4, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN4, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN4, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN5, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN5, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN5, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN6, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN6, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN6, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN7, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN7, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN7, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN8, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN8, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN8, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN9, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN9, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN9, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN10, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN10, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN10, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN11, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN11, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN11, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN12, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN12, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN12, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN13, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN13, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN13, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN14, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN14, converted by group only */ #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN14, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring monitoring of ADC channel ADCx_IN15, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN15, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN15, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN16, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN16, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN16, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN17, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN17, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN17, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN18, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN18, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC channel ADCx_IN18, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to internal temperature sensor, converted by group regular only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog of ADC1 internal channel connected to internal temperature sensor, converted by group injected only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to internal temperature sensor, converted by either group regular or injected */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to internal temperature sensor, converted by group regular only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog of ADC5 internal channel connected to internal temperature sensor, converted by group injected only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to internal temperature sensor, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda, converted by group regular only */ #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda, converted by group injected only */ #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have channel voltage always below Vdda */ #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring channel specific to ADC2, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) \ | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \ | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds * @{ */ #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1) /*!< ADC analog watchdog threshold high */ #define LL_ADC_AWD_THRESHOLD_LOW (ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 \ | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config * @{ */ #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_2SAMPLES (ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 2 out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_3SAMPLES (ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_4SAMPLES (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ #define LL_ADC_OVS_GRP_INJECTED (ADC_CFGR2_JOVSE) /*!< ADC oversampling on conversions of ADC group injected. */ #define LL_ADC_OVS_GRP_INJ_REG_RESUMED (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (sum of conversions data computed to result as oversampling conversion data (before potential shift) */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift * @{ */ #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 (sum of the ADC conversions data (after OVS ratio) is divided by 2 to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 (sum of the ADC conversions data (after OVS ratio) is divided by 4 to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 (sum of the ADC conversions data (after OVS ratio) is divided by 8 to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 (sum of the ADC conversions data (after OVS ratio) is divided by 16 to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 (sum of the ADC conversions data (after OVS ratio) is divided by 32 to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 (sum of the ADC conversions data (after OVS ratio) is divided by 64 to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 (sum of the ADC conversions data (after OVS ratio) is divided by 128 to result as oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 (sum of the ADC conversions data (after OVS ratio) is divided by 256 to result as oversampling conversion data) */ /** * @} */ #if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode * @{ */ #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ #define LL_ADC_MULTI_DUAL_REG_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular simultaneous */ #define LL_ADC_MULTI_DUAL_REG_INTERL (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \ | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define LL_ADC_MULTI_DUAL_INJ_SIMULT (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not SW start) */ #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM (ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT (ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ /** * @} */ /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer * @{ */ #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC(DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC(DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC(DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \ | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */ /** * @} */ /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES (ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES (ADC_CCR_DELAY_1) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (ADC_CCR_DELAY_2) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \ | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \ | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ /** * @} */ /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave * @{ */ #define LL_ADC_MULTI_MASTER (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC instances: ADC slave */ #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \ | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ /** * @} */ #endif /* ADC_MULTIMODE_SUPPORT */ /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro * @{ */ #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */ /** * @} */ /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. * @{ */ /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values. */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Indications for estimation of ADC timeout delays, for this */ /* STM32 series: */ /* - ADC calibration time: maximum delay is 112/fADC. */ /* (refer to device datasheet, parameter "tCAL") */ /* - ADC enable time: maximum delay is 1 conversion cycle. */ /* (refer to device datasheet, parameter "tSTAB") */ /* - ADC disable time: maximum delay should be a few ADC clock cycles */ /* - ADC stop conversion time: maximum delay should be a few ADC clock */ /* cycles */ /* - ADC conversion time: duration depending on ADC clock and ADC */ /* configuration. */ /* (refer to device reference manual, section "Timing") */ /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 series, a minimum number of ADC clock cycles */ /* are required between ADC end of calibration and ADC enable. */ /* Wait time can be computed in user application by waiting for the */ /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros * @{ */ /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros * @{ */ /** * @brief Write a value in ADC register * @param __INSTANCE__ ADC Instance * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) /** * @brief Read a value in ADC register * @param __INSTANCE__ ADC Instance * @param __REG__ Register to be read * @retval Register value */ #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) /** * @} */ /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro * @{ */ /** * @brief Helper macro to get ADC channel number in decimal format * from literals LL_ADC_CHANNEL_x. * @note Example: * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) * will return decimal number "4". * @note The input can be a value from functions where a channel * number is returned, either defined with number * or with bitfield (only one bit must be set). * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ ) \ : \ ( \ (uint32_t)POSITION_VAL((__CHANNEL__)) \ ) \ ) /** * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x * from number in decimal format. * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) <= 9UL) ? \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ : \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ ) /** * @brief Helper macro to determine whether the selected channel * corresponds to literal definitions of driver. * @note The different literal definitions of ADC channels are: * - ADC internal channel: * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... * - ADC external channel (channel connected to a GPIO pin): * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... * @note The channel parameter must be a value defined from literal * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, * LL_ADC_CHANNEL_TEMPSENSOR, ...), * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), * must not be a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) /** * @brief Helper macro to convert a channel defined from parameter * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, * LL_ADC_CHANNEL_TEMPSENSOR, ...), * to its equivalent parameter definition of a ADC external channel * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). * @note The channel parameter can be, additionally to a value * defined from parameter definition of a ADC internal channel * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), * a value defined from parameter definition of * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) * or a value from functions where a channel number is returned * from ADC registers. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 * @arg @ref LL_ADC_CHANNEL_4 * @arg @ref LL_ADC_CHANNEL_5 * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 */ #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) /** * @brief Helper macro to determine whether the internal channel * selected is available on the ADC instance selected. * @note The channel parameter must be a value defined from parameter * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, * LL_ADC_CHANNEL_TEMPSENSOR, ...), * must not be a value defined from parameter definition of * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) * or a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __ADC_INSTANCE__ ADC instance * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC3) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC4) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC5) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ ) #elif defined(STM32G471xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC3) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC3) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ ) #endif /* STM32G4xx */ /** * @brief Helper macro to define ADC analog watchdog parameter: * define a single channel to monitor with analog watchdog * from sequencer channel and groups definition. * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). * Example: * LL_ADC_SetAnalogWDMonitChannels( * ADC1, LL_ADC_AWD1, * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). * @param __GROUP__ This parameter can be one of the following values: * @arg @ref LL_ADC_GROUP_REGULAR * @arg @ref LL_ADC_GROUP_INJECTED * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4) * * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ : \ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ : \ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ ) /** * @brief Helper macro to set the value of ADC analog watchdog threshold high * or low in function of ADC resolution, when ADC resolution is * different of 12 bits. * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() * or @ref LL_ADC_SetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to set the value of * analog watchdog threshold high (on 8 bits): * LL_ADC_SetAnalogWDThresholds * (< ADCx param >, * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) * ); * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) /** * @brief Helper macro to get the value of ADC analog watchdog threshold high * or low in function of ADC resolution, when ADC resolution is * different of 12 bits. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to get the value of * analog watchdog threshold high (on 8 bits): * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION * (LL_ADC_RESOLUTION_8B, * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) * ); * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) /** * @brief Helper macro to get the ADC analog watchdog threshold high * or low from raw value containing both thresholds concatenated. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, to get analog watchdog threshold high from the register raw value: * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \ & LL_ADC_AWD_THRESHOLD_LOW) /** * @brief Helper macro to set the ADC calibration value with both single ended * and differential modes calibration factors concatenated. * @note To be used with function @ref LL_ADC_SetCalibrationFactor(). * Example, to set calibration factors single ended to 0x55 * and differential ended to 0x2A: * LL_ADC_SetCalibrationFactor( * ADC1, * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A)) * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Helper macro to get the ADC multimode conversion data of ADC master * or ADC slave from raw value with both ADC conversion data concatenated. * @note This macro is intended to be used when multimode transfer by DMA * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). * In this case the transferred data need to processed with this macro * to separate the conversion data of ADC master and ADC slave. * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_MASTER * @arg @ref LL_ADC_MULTI_SLAVE * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) #endif /* ADC_MULTIMODE_SUPPORT */ #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Helper macro to select, from a ADC instance, to which ADC instance * it has a dependence in multimode (ADC master of the corresponding * ADC common instance). * @note In case of device with multimode available and a mix of * ADC instances compliant and not compliant with multimode feature, * ADC instances not compliant with multimode feature are * considered as master instances (do not depend to * any other ADC instance). * @param __ADCx__ ADC instance * @retval __ADCx__ ADC instance master of the corresponding ADC common instance */ #if defined(ADC5) #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ ( ( ((__ADCx__) == ADC2) \ )? \ (ADC1) \ : \ ( ( ((__ADCx__) == ADC4) \ )? \ (ADC3) \ : \ (__ADCx__) \ ) \ ) #else #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ ( ( ((__ADCx__) == ADC2) \ )? \ (ADC1) \ : \ (__ADCx__) \ ) #endif /* ADC5 */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance * to which is belonging the selected ADC instance. * @note ADC common register instance can be used for: * - Set parameters common to several ADC instances * - Multimode (for devices with several ADC instances) * Refer to functions having argument "ADCxy_COMMON" as parameter. * @param __ADCx__ ADC instance * @retval ADC common register instance */ #if defined(ADC345_COMMON) #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ ? ( \ (ADC12_COMMON) \ ) \ : \ ( \ (ADC345_COMMON) \ ) \ ) #else #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON) #endif /* ADC345_COMMON */ /** * @brief Helper macro to check if all ADC instances sharing the same * ADC common instance are disabled. * @note This check is required by functions with setting conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * Refer to functions having argument "ADCxy_COMMON" as parameter. * @note On devices with only 1 ADC common instance, parameter of this macro * is useless and can be ignored (parameter kept for compatibility * with devices featuring several ADC common instances). * @param __ADCXY_COMMON__ ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Value "0" if all ADC instances sharing the same ADC common instance * are disabled. * Value "1" if at least one ADC instance sharing the same ADC common instance * is enabled. */ #if defined(ADC345_COMMON) #if defined(ADC4) && defined(ADC5) #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (((__ADCXY_COMMON__) == ADC12_COMMON) \ ? ( \ (LL_ADC_IsEnabled(ADC1) | \ LL_ADC_IsEnabled(ADC2) ) \ ) \ : \ ( \ (LL_ADC_IsEnabled(ADC3) | \ LL_ADC_IsEnabled(ADC4) | \ LL_ADC_IsEnabled(ADC5) ) \ ) \ ) #else #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (((__ADCXY_COMMON__) == ADC12_COMMON) \ ? ( \ (LL_ADC_IsEnabled(ADC1) | \ LL_ADC_IsEnabled(ADC2) ) \ ) \ : \ (LL_ADC_IsEnabled(ADC3)) \ ) #endif /* ADC4 && ADC5 */ #else #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) #endif /* ADC345_COMMON */ /** * @brief Helper macro to define the ADC conversion data full-scale digital * value corresponding to the selected ADC resolution. * @note ADC conversion data full-scale corresponds to voltage range * determined by analog voltage references Vref+ and Vref- * (refer to reference manual). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) */ #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data to the requested resolution */ #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ (((__DATA__) \ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ ) /** * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ ) /** * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value) in * differential ended mode. * @note ADC data from ADC data register is unsigned and centered around * middle code in. Converted voltage can be positive or negative * depending on differential input voltages. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__)\ ((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\ / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\ - (int32_t)(__VREFANALOG_VOLTAGE__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage * reference VrefInt. * @note Computation is using VrefInt calibration value * stored in system memory for each device during production. * @note This voltage depends on user board environment: voltage level * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval Analog reference voltage (unit: mV) */ #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ (__ADC_RESOLUTION__), \ LL_ADC_RESOLUTION_12B) \ ) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor calibration values * stored in system memory for each device during production. * @note Calculation formula: * Temperature = ((TS_ADC_DATA - TS_CAL1) * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * Avg_Slope = (TS_CAL2 - TS_CAL1) * / (TS_CAL2_TEMP - TS_CAL1_TEMP) * TS_CAL1 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL1 (calibrated in factory) * TS_CAL2 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL2 (calibrated in factory) * Caution: Calculation relevancy under reserve that calibration * parameters are correct (address and data). * To calculate temperature using temperature sensor * datasheet typical values (generic values less, therefore * less accurate than calibrated values), * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal * temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature * sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value) */ #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__)\ ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ (__ADC_RESOLUTION__), \ LL_ADC_RESOLUTION_12B) \ * (__VREFANALOG_VOLTAGE__)) \ / TEMPSENSOR_CAL_VREFANALOG) \ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ ) + TEMPSENSOR_CAL1_TEMP \ ) \ : \ ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ ) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor typical values * (refer to device datasheet). * @note Calculation formula: * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) * / Avg_Slope + CALx_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * (unit: digital value) * Avg_Slope = temperature sensor slope * (unit: uV/Degree Celsius) * TS_TYP_CALx_VOLT = temperature sensor digital value at * temperature CALx_TEMP (unit: mV) * Caution: Calculation relevancy under reserve the temperature sensor * of the current device has characteristics in line with * datasheet typical values. * If temperature sensor calibration values are available on * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), * temperature calculation will be more accurate using * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note ADC measurement data must correspond to a resolution of 12 bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value * (unit: uV/DegCelsius). * On STM32G4, refer to device datasheet parameter "Avg_Slope". * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value * (at temperature and Vref+ defined in parameters below) (unit: mV). * On STM32G4, refer to datasheet parameter "V30" (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage * (see parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) */ #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ __TEMPSENSOR_TYP_CALX_V__,\ __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ * 1000UL) \ - \ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ * 1000UL) \ ) \ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ ) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management * @{ */ /* Note: LL ADC functions to set DMA transfer are located into sections of */ /* configuration of ADC instance, groups and multimode (if available): */ /* @ref LL_ADC_REG_SetDMATransfer(), ... */ /** * @brief Function to help to configure DMA transfer from ADC: retrieve the * ADC register address from ADC instance and a list of ADC registers * intended to be used (most commonly) with DMA transfer. * @note These ADC registers are data registers: * when ADC conversion data is available in ADC data registers, * ADC generates a DMA transfer request. * @note This macro is intended to be used with LL DMA driver, refer to * function "LL_DMA_ConfigAddresses()". * Example: * LL_DMA_ConfigAddresses(DMA1, * LL_DMA_CHANNEL_1, * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), * (uint32_t)&< array or variable >, * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); * @note For devices with several ADC: in multimode, some devices * use a different data register outside of ADC instance scope * (common data register). This macro manages this register difference, * only ADC instance has to be set as parameter. * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr * @param ADCx ADC instance * @param Register This parameter can be one of the following values: * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) * * (1) Available on devices with several ADC instances. * @retval ADC register address */ #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { /* Retrieve address of register DR */ data_reg_addr = (uint32_t) &(ADCx->DR); } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ { /* Retrieve address of register CDR */ data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); } return data_reg_addr; } #else __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { /* Prevent unused argument(s) compilation warning */ (void)(Register); /* Retrieve address of register DR */ return (uint32_t) &(ADCx->DR); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several * ADC instances * @{ */ /** * @brief Set parameter common to several ADC: Clock source and prescaler. * @note On this STM32 series, if ADC group injected is used, some * clock ratio constraints between ADC clock and AHB clock * must be respected. * Refer to reference manual. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n * CCR PRESC LL_ADC_SetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param CommonClock This parameter can be one of the following values: * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); } /** * @brief Get parameter common to several ADC: Clock source and prescaler. * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n * CCR PRESC LL_ADC_GetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); } /** * @brief Set parameter common to several ADC: measurement path to * internal channels (VrefInt, temperature sensor, ...). * Configure all paths (overwrite current configuration). * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * The values not selected are removed from configuration. * @note Stabilization time of measurement path to internal channel: * After enabling internal paths, before starting ADC conversion, * a delay is required for internal voltage reference and * temperature sensor stabilization time. * Refer to device datasheet. * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. * @note ADC internal channel sampling time constraint: * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n * CCR VBATSEL LL_ADC_SetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param PathInternal This parameter can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); } /** * @brief Set parameter common to several ADC: measurement path to * internal channels (VrefInt, temperature sensor, ...). * Add paths to the current configuration. * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * @note Stabilization time of measurement path to internal channel: * After enabling internal paths, before starting ADC conversion, * a delay is required for internal voltage reference and * temperature sensor stabilization time. * Refer to device datasheet. * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. * @note ADC internal channel sampling time constraint: * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param PathInternal This parameter can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { SET_BIT(ADCxy_COMMON->CCR, PathInternal); } /** * @brief Set parameter common to several ADC: measurement path to * internal channels (VrefInt, temperature sensor, ...). * Remove paths to the current configuration. * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param PathInternal This parameter can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); } /** * @brief Get parameter common to several ADC: measurement path to internal * channels (VrefInt, temperature sensor, ...). * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n * CCR VBATSEL LL_ADC_GetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance * @{ */ /** * @brief Set ADC calibration factor in the mode single-ended * or differential (for devices with differential mode available). * @note This function is intended to set calibration parameters * without having to perform a new calibration using * @ref LL_ADC_StartCalibration(). * @note For devices with differential mode available: * Calibration of offset is specific to each of * single-ended and differential modes * (calibration factor must be specified for each of these * differential modes, if used afterwards and if the application * requires their calibration). * @note In case of setting calibration factors of both modes single ended * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): * both calibration factors must be concatenated. * To perform this processing, use helper macro * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F * @retval None */ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) { MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); } /** * @brief Get ADC calibration factor in the mode single-ended * or differential (for devices with differential mode available). * @note Calibration factors are set by hardware after performing * a calibration run using function @ref LL_ADC_StartCalibration(). * @note For devices with differential mode available: * Calibration of offset is specific to each of * single-ended and differential modes * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Retrieve bits with position in register depending on parameter */ /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); } /** * @brief Set ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR RES LL_ADC_SetResolution * @param ADCx ADC instance * @param Resolution This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval None */ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); } /** * @brief Get ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @rmtoll CFGR RES LL_ADC_GetResolution * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B */ __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); } /** * @brief Set ADC conversion data alignment. * @note Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment * @param ADCx ADC instance * @param DataAlignment This parameter can be one of the following values: * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT * @retval None */ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); } /** * @brief Get ADC conversion data alignment. * @note Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT */ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); } /** * @brief Set ADC low power mode. * @note Description of ADC low power modes: * - ADC low power mode "auto wait": Dynamic low power mode, * ADC conversions occurrences are limited to the minimum necessary * in order to reduce power consumption. * New ADC conversion starts only when the previous * unitary conversion data (for ADC group regular) * or previous sequence conversions data (for ADC group injected) * has been retrieved by user software. * In the meantime, ADC remains idle: does not performs any * other conversion. * This mode allows to automatically adapt the ADC conversions * triggers to the speed of the software that reads the data. * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: * - It is not recommended to use with interruption or DMA * since these modes have to clear immediately the EOC flag * (by CPU to free the IRQ pending event or by DMA). * Auto wait will work but fort a very short time, discarding * its intended benefit (except specific case of high load of CPU * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and * retrieve ADC conversion data. This will trig another * ADC conversion start. * @note With ADC low power mode "auto wait", the ADC conversion data read * is corresponding to previous ADC conversion start, independently * of delay during which ADC was idle. * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode * @param ADCx ADC instance * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT * @retval None */ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); } /** * @brief Get ADC low power mode: * @note Description of ADC low power modes: * - ADC low power mode "auto wait": Dynamic low power mode, * ADC conversions occurrences are limited to the minimum necessary * in order to reduce power consumption. * New ADC conversion starts only when the previous * unitary conversion data (for ADC group regular) * or previous sequence conversions data (for ADC group injected) * has been retrieved by user software. * In the meantime, ADC remains idle: does not performs any * other conversion. * This mode allows to automatically adapt the ADC conversions * triggers to the speed of the software that reads the data. * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: * - It is not recommended to use with interruption or DMA * since these modes have to clear immediately the EOC flag * (by CPU to free the IRQ pending event or by DMA). * Auto wait will work but fort a very short time, discarding * its intended benefit (except specific case of high load of CPU * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and * retrieve ADC conversion data. This will trig another * ADC conversion start. * @note With ADC low power mode "auto wait", the ADC conversion data read * is corresponding to previous ADC conversion start, independently * of delay during which ADC was idle. * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); } /** * @brief Set ADC selected offset instance 1, 2, 3 or 4. * @note This function set the 2 items of offset configuration: * - ADC channel to which the offset programmed will be applied * (independently of channel mapped on ADC group regular * or group injected) * - Offset level (offset to be subtracted from the raw * converted data). * @note Caution: Offset format is dependent to ADC resolution: * offset has to be left-aligned on bit 11, the LSB (right bits) * are set to 0. * @note This function enables the offset, by default. It can be forced * to disable state using function LL_ADC_SetOffsetState(). * @note If a channel is mapped on several offsets numbers, only the offset * with the lowest value is considered for the subtraction. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n * OFR1 OFFSET1 LL_ADC_SetOffset\n * OFR1 OFFSET1_EN LL_ADC_SetOffset\n * OFR2 OFFSET2_CH LL_ADC_SetOffset\n * OFR2 OFFSET2 LL_ADC_SetOffset\n * OFR2 OFFSET2_EN LL_ADC_SetOffset\n * OFR3 OFFSET3_CH LL_ADC_SetOffset\n * OFR3 OFFSET3 LL_ADC_SetOffset\n * OFR3 OFFSET3_EN LL_ADC_SetOffset\n * OFR4 OFFSET4_CH LL_ADC_SetOffset\n * OFR4 OFFSET4 LL_ADC_SetOffset\n * OFR4 OFFSET4_EN LL_ADC_SetOffset * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } /** * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * Channel to which the offset programmed will be applied * (independently of channel mapped on ADC group regular * or group injected) * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } /** * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * Offset level (offset to be subtracted from the raw * converted data). * @note Caution: Offset format is dependent to ADC resolution: * offset has to be left-aligned on bit 11, the LSB (right bits) * are set to 0. * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n * OFR4 OFFSET4 LL_ADC_GetOffsetLevel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } /** * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: * force offset state disable or enable * without modifying offset channel or offset value. * @note This function should be needed only in case of offset to be * enabled-disabled dynamically, and should not be needed in other cases: * function LL_ADC_SetOffset() automatically enables the offset. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n * OFR4 OFFSET4_EN LL_ADC_SetOffsetState * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param OffsetState This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, OffsetState); } /** * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * offset state disabled or enabled. * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n * OFR4 OFFSET4_EN LL_ADC_GetOffsetState * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } /** * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: * choose offset sign. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_SetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param OffsetSign This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign); } /** * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * offset sign if positive or negative. * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_GetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS); } /** * @brief Set for the ADC selected offset instance 1, 2, 3 or 4: * choose offset saturation mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n * OFR2 SATEN LL_ADC_SetOffsetSaturation\n * OFR3 SATEN LL_ADC_SetOffsetSaturation\n * OFR4 SATEN LL_ADC_SetOffsetSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param OffsetSaturation This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_SATEN, OffsetSaturation); } /** * @brief Get for the ADC selected offset instance 1, 2, 3 or 4: * offset saturation if enabled or disabled. * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n * OFR2 SATEN LL_ADC_GetOffsetSaturation\n * OFR3 SATEN LL_ADC_GetOffsetSaturation\n * OFR4 SATEN LL_ADC_GetOffsetSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN); } /** * @brief Set ADC gain compensation. * @note This function set the gain compensation coefficient * that is applied to raw converted data using the formula: * DATA = DATA(raw) * (gain compensation coef) / 4096 * @note This function enables the gain compensation if given * coefficient is above 0, otherwise it disables it. * @note Gain compensation when enabled is applied to all channels. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n * CFGR2 GCOMP LL_ADC_SetGainCompensation * @param ADCx ADC instance * @param GainCompensation This parameter can be: * 0 Gain compensation will be disabled and value set to 0 * 1 -> 16393 Gain compensation will be enabled with specified value * @retval None */ __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation) { MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation); MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos); } /** * @brief Get the ADC gain compensation value * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n * CFGR2 GCOMP LL_ADC_GetGainCompensation * @param ADCx ADC instance * @retval Returned value can be: * 0 Gain compensation is disabled * 1 -> 16393 Gain compensation is enabled with returned value */ __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL); } #if defined(ADC_SMPR1_SMPPLUS) /** * @brief Set ADC sampling time common configuration impacting * settings of sampling time channel wise. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig * @param ADCx ADC instance * @param SamplingTimeCommonConfig This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) { MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); } /** * @brief Get ADC sampling time common configuration impacting * settings of sampling time channel wise. * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 */ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS)); } #endif /* ADC_SMPR1_SMPPLUS */ /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular * @{ */ /** * @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 series having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n * CFGR EXTEN LL_ADC_REG_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_SOFTWARE * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); } /** * @brief Get ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note To determine whether group regular trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, * (equivalent to * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n * CFGR EXTEN LL_ADC_REG_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_SOFTWARE * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ return ((trigger_source & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL) | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN) ); } /** * @brief Get ADC group regular conversion trigger source internal (SW start) * or external. * @note In case of group regular trigger source set to external trigger, * to determine which peripheral is selected as external trigger, * use function @ref LL_ADC_REG_GetTriggerSource(). * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } /** * @brief Set ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge * @param ADCx ADC instance * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_EXT_RISING * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); } /** * @brief Get ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_EXT_RISING * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } /** * @brief Set ADC sampling mode. * @note This function set the ADC conversion sampling mode * @note This mode applies to regular group only. * @note Set sampling mode is applied to all conversion of regular group. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode * @param ADCx ADC instance * @param SamplingMode This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode) { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode); } /** * @brief Get the ADC sampling mode * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); } /** * @brief Set ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: * - For devices with sequencer fully configurable * (function "LL_ADC_REG_SetSequencerRanks()" available): * sequencer length and each rank affectation to a channel * are configurable. * This function performs configuration of: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerRanks()". * - For devices with sequencer not fully configurable * (function "LL_ADC_REG_SetSequencerChannels()" available): * sequencer length and each rank affectation to a channel * are defined by channel number. * This function performs configuration of: * - Sequence length: Number of ranks in the scan sequence is * defined by number of channels set in the sequence, * rank of each channel is fixed by channel HW number. * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from lowest channel number to * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength * @param ADCx ADC instance * @param SequencerNbRanks This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) { MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); } /** * @brief Get ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: * - For devices with sequencer fully configurable * (function "LL_ADC_REG_SetSequencerRanks()" available): * sequencer length and each rank affectation to a channel * are configurable. * This function retrieves: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerRanks()". * - For devices with sequencer not fully configurable * (function "LL_ADC_REG_SetSequencerChannels()" available): * sequencer length and each rank affectation to a channel * are defined by channel number. * This function retrieves: * - Sequence length: Number of ranks in the scan sequence is * defined by number of channels set in the sequence, * rank of each channel is fixed by channel HW number. * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from lowest channel number to * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); } /** * @brief Set ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont * @param ADCx ADC instance * @param SeqDiscont This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont); } /** * @brief Get ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); } /** * @brief Set ADC group regular sequence: channel on the selected * scan sequence rank. * @note This function performs configuration of: * - Channels ordering into each rank of scan sequence: * whatever channel can be placed into whatever rank. * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_REG_RANK_1 * @arg @ref LL_ADC_REG_RANK_2 * @arg @ref LL_ADC_REG_RANK_3 * @arg @ref LL_ADC_REG_RANK_4 * @arg @ref LL_ADC_REG_RANK_5 * @arg @ref LL_ADC_REG_RANK_6 * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 * @arg @ref LL_ADC_REG_RANK_9 * @arg @ref LL_ADC_REG_RANK_10 * @arg @ref LL_ADC_REG_RANK_11 * @arg @ref LL_ADC_REG_RANK_12 * @arg @ref LL_ADC_REG_RANK_13 * @arg @ref LL_ADC_REG_RANK_14 * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** * @brief Get ADC group regular sequence: channel on the selected * scan sequence rank. * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_REG_RANK_1 * @arg @ref LL_ADC_REG_RANK_2 * @arg @ref LL_ADC_REG_RANK_3 * @arg @ref LL_ADC_REG_RANK_4 * @arg @ref LL_ADC_REG_RANK_5 * @arg @ref LL_ADC_REG_RANK_6 * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 * @arg @ref LL_ADC_REG_RANK_9 * @arg @ref LL_ADC_REG_RANK_10 * @arg @ref LL_ADC_REG_RANK_11 * @arg @ref LL_ADC_REG_RANK_12 * @arg @ref LL_ADC_REG_RANK_13 * @arg @ref LL_ADC_REG_RANK_14 * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } /** * @brief Set ADC continuous conversion mode on ADC group regular. * @note Description of ADC continuous conversion mode: * - single mode: one conversion per trigger * - continuous mode: after the first trigger, following * conversions launched successively automatically. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode * @param ADCx ADC instance * @param Continuous This parameter can be one of the following values: * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous); } /** * @brief Get ADC continuous conversion mode on ADC group regular. * @note Description of ADC continuous conversion mode: * - single mode: one conversion per trigger * - continuous mode: after the first trigger, following * conversions launched successively automatically. * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); } /** * @brief Set ADC group regular conversion data transfer: no transfer or * transfer by DMA, and DMA requests mode. * @note If transfer by DMA selected, specifies the DMA requests * mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note For devices with several ADC instances: ADC multimode DMA * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n * CFGR DMACFG LL_ADC_REG_SetDMATransfer * @param ADCx ADC instance * @param DMATransfer This parameter can be one of the following values: * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer); } /** * @brief Get ADC group regular conversion data transfer: no transfer or * transfer by DMA, and DMA requests mode. * @note If transfer by DMA selected, specifies the DMA requests * mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note For devices with several ADC instances: ADC multimode DMA * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n * CFGR DMACFG LL_ADC_REG_GetDMATransfer * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED */ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); } /** * @brief Set ADC group regular behavior in case of overrun: * data preserved or overwritten. * @note Compatibility with devices without feature overrun: * other devices without this feature have a behavior * equivalent to data overwritten. * The default setting of overrun is data preserved. * Therefore, for compatibility with all devices, parameter * overrun should be set to data overwritten. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun * @param ADCx ADC instance * @param Overrun This parameter can be one of the following values: * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun); } /** * @brief Get ADC group regular behavior in case of overrun: * data preserved or overwritten. * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected * @{ */ /** * @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 series having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_INJ_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource); } /** * @brief Get ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note To determine whether group injected trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, * (equivalent to * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ return ((trigger_source & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL) | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN) ); } /** * @brief Get ADC group injected conversion trigger source internal (SW start) or external * @note In case of group injected trigger source set to external trigger, * to determine which peripheral is selected as external trigger, * use function @ref LL_ADC_INJ_GetTriggerSource. * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } /** * @brief Set ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge * @param ADCx ADC instance * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) { MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge); } /** * @brief Get ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } /** * @brief Set ADC group injected sequencer length and scan direction. * @note This function performs configuration of: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength * @param ADCx ADC instance * @param SequencerNbRanks This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) { MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); } /** * @brief Get ADC group injected sequencer length and scan direction. * @note This function retrieves: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } /** * @brief Set ADC group injected sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont * @param ADCx ADC instance * @param SeqDiscont This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont); } /** * @brief Get ADC group injected sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); } /** * @brief Set ADC group injected sequence: channel on the selected * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { /* Set bits with content of parameter "Channel" with bits position */ /* in register depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); } /** * @brief Get ADC group injected sequence: channel on the selected * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } /** * @brief Set ADC group injected conversion trigger: * independent or from ADC group regular. * @note This mode can be used to extend number of data registers * updated after one ADC conversion trigger and with data * permanently kept (not erased by successive conversions of scan of * ADC sequencer ranks), up to 5 data registers: * 1 data register on ADC group regular, 4 data registers * on ADC group injected. * @note If ADC group injected injected trigger source is set to an * external trigger, this feature must be must be set to * independent trigger. * ADC group injected automatic trigger is compliant only with * group injected trigger source set to SW start, without any * further action on ADC group injected conversion start or stop: * in this case, ADC group injected is controlled only * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto * @param ADCx ADC instance * @param TrigAuto This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto); } /** * @brief Get ADC group injected conversion trigger: * independent or from ADC group regular. * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); } /** * @brief Set ADC group injected contexts queue mode. * @note A context is a setting of group injected sequencer: * - group injected trigger * - sequencer length * - sequencer ranks * If contexts queue is disabled: * - only 1 sequence can be configured * and is active perpetually. * If contexts queue is enabled: * - up to 2 contexts can be queued * and are checked in and out as a FIFO stack (first-in, first-out). * - If a new context is set when queues is full, error is triggered * by interruption "Injected Queue Overflow". * - Two behaviors are possible when all contexts have been processed: * the contexts queue can maintain the last context active perpetually * or can be empty and injected group triggers are disabled. * - Triggers can be only external (not internal SW start) * - Caution: The sequence must be fully configured in one time * (one write of register JSQR makes a check-in of a new context * into the queue). * Therefore functions to set separately injected trigger and * sequencer channels cannot be used, register JSQR must be set * using function @ref LL_ADC_INJ_ConfigQueueContext(). * @note This parameter can be modified only when no conversion is on going * on either groups regular or injected. * @note A modification of the context mode (bit JQDIS) causes the contexts * queue to be flushed and the register JSQR is cleared. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n * CFGR JQDIS LL_ADC_INJ_SetQueueMode * @param ADCx ADC instance * @param QueueMode This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_QUEUE_DISABLE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode); } /** * @brief Get ADC group injected context queue mode. * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n * CFGR JQDIS LL_ADC_INJ_GetQueueMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_QUEUE_DISABLE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); } /** * @brief Set one context on ADC group injected that will be checked in * contexts queue. * @note A context is a setting of group injected sequencer: * - group injected trigger * - sequencer length * - sequencer ranks * This function is intended to be used when contexts queue is enabled, * because the sequence must be fully configured in one time * (functions to set separately injected trigger and sequencer channels * cannot be used): * Refer to function @ref LL_ADC_INJ_SetQueueMode(). * @note In the contexts queue, only the active context can be read. * The parameters of this function can be read using functions: * @arg @ref LL_ADC_INJ_GetTriggerSource() * @arg @ref LL_ADC_INJ_GetTriggerEdge() * @arg @ref LL_ADC_INJ_GetSequencerRanks() * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n * JSQR JL LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for * more details. * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING * * Note: This parameter is discarded in case of SW start: * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE". * @param SequencerNbRanks This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS * @param Rank1_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @param Rank2_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @param Rank3_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @param Rank4_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel) { /* Set bits with content of parameter "Rankx_Channel" with bits position */ /* in register depending on literal "LL_ADC_INJ_RANK_x". */ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | ADC_JSQR_JL, (TriggerSource & ADC_JSQR_JEXTSEL) | (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | SequencerNbRanks ); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels * @{ */ /** * @brief Set sampling time of the selected ADC channel * Unit: ADC clock cycles. * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note In case of internal channel (VrefInt, TempSensor, ...) to be * converted: * sampling time constraints must be respected (sampling time can be * adjusted in function of ADC clock frequency and sampling time * setting). * Refer to device datasheet for timings values (parameters TS_vrefint, * TS_temp, ...). * @note Conversion time is the addition of sampling time and processing time. * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits * - 6.5 ADC clock cycles at ADC resolution 6 bits * @note In case of ADC conversion of internal channel (VrefInt, * temperature sensor, ...), a sampling time minimum value * is required. * Refer to device datasheet. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @param SamplingTime This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 * * (1) On some devices, ADC sampling time 2.5 ADC clock cycles * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } /** * @brief Get sampling time of the selected ADC channel * Unit: ADC clock cycles. * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note Conversion time is the addition of sampling time and processing time. * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits * - 6.5 ADC clock cycles at ADC resolution 6 bits * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to * convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 * * (1) On some devices, ADC sampling time 2.5 ADC clock cycles * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) ); } /** * @brief Set mode single-ended or differential input of the selected * ADC channel. * @note Channel ending is on channel scope: independently of channel mapped * on ADC group regular or injected. * In differential mode: Differential measurement is carried out * between the selected channel 'i' (positive input) and * channel 'i+1' (negative input). Only channel 'i' has to be * configured, channel 'i+1' is configured automatically. * @note Refer to Reference Manual to ensure the selected channel is * available in differential mode. * For example, internal channels (VrefInt, TempSensor, ...) are * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. * @note On STM32G4, some channels are internally fixed to single-ended inputs * configuration: * - ADC1: Channels 12, 15, 16, 17 and 18 * - ADC2: Channels 15, 17 and 18 * - ADC3: Channels 12, 16, 17 and 18 (1) * - ADC4: Channels 16, 17 and 18 (1) * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) * (1) ADC3/4/5 are not available on all devices, refer to device datasheet * for more details. * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. * (Vref+ is the analog voltage reference) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 * @arg @ref LL_ADC_CHANNEL_4 * @arg @ref LL_ADC_CHANNEL_5 * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @param SingleDiff This parameter can be a combination of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } /** * @brief Get mode single-ended or differential input of the selected * ADC channel. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. * Therefore, to ensure a channel is configured in single-ended mode, * the configuration of channel itself and the channel 'i-1' must be * read back (to ensure that the selected channel channel has not been * configured in differential mode by the previous channel). * @note Refer to Reference Manual to ensure the selected channel is * available in differential mode. * For example, internal channels (VrefInt, TempSensor, ...) are * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. * @note On STM32G4, some channels are internally fixed to single-ended inputs * configuration: * - ADC1: Channels 12, 15, 16, 17 and 18 * - ADC2: Channels 15, 17 and 18 * - ADC3: Channels 12, 16, 17 and 18 (1) * - ADC4: Channels 16, 17 and 18 (1) * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) * (1) ADC3/4/5 are not available on all devices, refer to device datasheet * for more details. * @note One or several values can be selected. In this case, the value * returned is null if all channels are in single ended-mode. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 * @arg @ref LL_ADC_CHANNEL_4 * @arg @ref LL_ADC_CHANNEL_5 * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @retval 0: channel in single-ended mode, else: channel in differential mode */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) { return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog * @{ */ /** * @brief Set ADC analog watchdog monitored channels: * a single channel, multiple channels or all channels, * on ADC groups regular and-or injected. * @note Once monitored channels are selected, analog watchdog * is enabled. * @note In case of need to define a single channel to monitor * with analog watchdog from sequencer channel definition, * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDChannelGroup This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4) * * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet * for more details. * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) { /* Set bits with content of parameter "AWDChannelGroup" with bits position */ /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); } /** * @brief Get ADC analog watchdog monitored channel. * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Applicable only when the analog watchdog is set to monitor * one channel. * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 (1) * @arg @ref LL_ADC_AWD3 (1) * * (1) On this AWD number, monitored channel can be retrieved * if only 1 channel is programmed (or none or all channels). * This function cannot retrieve monitored channel if * multiple channels are programmed simultaneously * by bitfield. * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ * * (0) On STM32G4, parameter available only on analog watchdog number: AWD1. */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ if (analog_wd_monit_channels != 0UL) { if (AWDy == LL_ADC_AWD1) { if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ analog_wd_monit_channels = ((analog_wd_monit_channels | (ADC_AWD_CR23_CHANNEL_MASK) ) & (~(ADC_CFGR_AWD1CH)) ); } else { /* AWD monitoring a single channel */ analog_wd_monit_channels = (analog_wd_monit_channels | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos)) ); } } else { if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) ); } else { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ analog_wd_monit_channels = (analog_wd_monit_channels | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos) ); } } } return analog_wd_monit_channels; } /** * @brief Set ADC analog watchdog thresholds value of both thresholds * high and low. * @note If value of only one threshold high or low must be set, * use function @ref LL_ADC_SetAnalogWDThresholds(). * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). * Examples: * - Oversampling ratio and shift selected to have ADC conversion data * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): * ADC analog watchdog thresholds must be divided by 16. * - Oversampling ratio and shift selected to have ADC conversion data * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): * ADC analog watchdog thresholds must be divided by 4. * - Oversampling ratio and shift selected to have ADC conversion data * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): * ADC analog watchdog thresholds match directly to ADC data register. * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) { /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ /* position in register and register position depending on parameter */ /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); } /** * @brief Set ADC analog watchdog threshold value of threshold * high or low. * @note If values of both thresholds high or low must be set, * use function @ref LL_ADC_ConfigAnalogWDThresholds(). * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). * Examples: * - Oversampling ratio and shift selected to have ADC conversion data * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): * ADC analog watchdog thresholds must be divided by 16. * - Oversampling ratio and shift selected to have ADC conversion data * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): * ADC analog watchdog thresholds must be divided by 4. * - Oversampling ratio and shift selected to have ADC conversion data * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): * ADC analog watchdog thresholds match directly to ADC data register. * @note On this STM32 series, setting of this feature is not conditioned to * ADC state: * ADC can be disabled, enabled with or without conversion on going * on either ADC groups regular or injected. * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n * TR3 LT3 LL_ADC_SetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); } /** * @brief Get ADC analog watchdog threshold value of threshold high, * threshold low or raw data with ADC thresholds high and low * concatenated. * @note If raw data with ADC thresholds high and low is retrieved, * the data of each threshold high or low can be isolated * using helper macro: * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n * TR3 LT3 LL_ADC_GetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); } /** * @brief Set ADC analog watchdog filtering configuration * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @param FilteringConfig This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_FILTERING_NONE * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES * @retval None */ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig) { /* Prevent unused argument(s) compilation warning */ (void)(AWDy); MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig); } /** * @brief Get ADC analog watchdog filtering configuration * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @retval Returned value can be: * @arg @ref LL_ADC_AWD_FILTERING_NONE * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) { /* Prevent unused argument(s) compilation warning */ (void)(AWDy); return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling * @{ */ /** * @brief Set ADC oversampling scope: ADC groups regular and-or injected * (availability of ADC group injected depends on STM32 series). * @note If both groups regular and injected are selected, * specify behavior of ADC group injected interrupting * group regular: when ADC group injected is triggered, * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_SetOverSamplingScope * @param ADCx ADC instance * @param OvsScope This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED * @retval None */ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); } /** * @brief Get ADC oversampling scope: ADC groups regular and-or injected * (availability of ADC group injected depends on STM32 series). * @note If both groups regular and injected are selected, * specify behavior of ADC group injected interrupting * group regular: when ADC group injected is triggered, * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_GetOverSamplingScope * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } /** * @brief Set ADC oversampling discontinuous mode (triggered mode) * on the selected ADC group. * @note Number of oversampled conversions are done either in: * - continuous mode (all conversions of oversampling ratio * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @note On this STM32 series, oversampling discontinuous mode * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont * @param ADCx ADC instance * @param OverSamplingDiscont This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT * @retval None */ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); } /** * @brief Get ADC oversampling discontinuous mode (triggered mode) * on the selected ADC group. * @note Number of oversampled conversions are done either in: * - continuous mode (all conversions of oversampling ratio * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } /** * @brief Set ADC oversampling * (impacting both ADC groups regular and injected) * @note This function set the 2 items of oversampling configuration: * - ratio * - shift * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift * @param ADCx ADC instance * @param Ratio This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_RATIO_2 * @arg @ref LL_ADC_OVS_RATIO_4 * @arg @ref LL_ADC_OVS_RATIO_8 * @arg @ref LL_ADC_OVS_RATIO_16 * @arg @ref LL_ADC_OVS_RATIO_32 * @arg @ref LL_ADC_OVS_RATIO_64 * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 * @param Shift This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_SHIFT_NONE * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 * @retval None */ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) { MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); } /** * @brief Get ADC oversampling ratio * (impacting both ADC groups regular and injected) * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio * @param ADCx ADC instance * @retval Ratio This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_RATIO_2 * @arg @ref LL_ADC_OVS_RATIO_4 * @arg @ref LL_ADC_OVS_RATIO_8 * @arg @ref LL_ADC_OVS_RATIO_16 * @arg @ref LL_ADC_OVS_RATIO_32 * @arg @ref LL_ADC_OVS_RATIO_64 * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); } /** * @brief Get ADC oversampling shift * (impacting both ADC groups regular and injected) * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift * @param ADCx ADC instance * @retval Shift This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_SHIFT_NONE * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode * @{ */ #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Set ADC multimode configuration to operate in independent mode * or multimode (for devices with several ADC instances). * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR DUAL LL_ADC_SetMultimode * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param Multimode This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_INDEPENDENT * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM * @retval None */ __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); } /** * @brief Get ADC multimode configuration to operate in independent mode * or multimode (for devices with several ADC instances). * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. * @rmtoll CCR DUAL LL_ADC_GetMultimode * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_MULTI_INDEPENDENT * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); } /** * @brief Set ADC multimode conversion data transfer: no transfer * or transfer by DMA. * @note If ADC multimode transfer by DMA is not selected: * each ADC uses its own DMA channel, with its individual * DMA transfer settings. * If ADC multimode transfer by DMA is selected: * One DMA channel is used for both ADC (DMA of ADC master) * Specifies the DMA requests mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note How to retrieve multimode conversion data: * Whatever multimode transfer by DMA setting: using function * @ref LL_ADC_REG_ReadMultiConversionData32(). * If ADC multimode transfer by DMA is selected: conversion data * is a raw data with ADC master and slave concatenated. * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled * or enabled without conversion on going on group regular. * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n * CCR DMACFG LL_ADC_SetMultiDMATransfer * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param MultiDMATransfer This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B * @retval None */ __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer); } /** * @brief Get ADC multimode conversion data transfer: no transfer * or transfer by DMA. * @note If ADC multimode transfer by DMA is not selected: * each ADC uses its own DMA channel, with its individual * DMA transfer settings. * If ADC multimode transfer by DMA is selected: * One DMA channel is used for both ADC (DMA of ADC master) * Specifies the DMA requests mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note How to retrieve multimode conversion data: * Whatever multimode transfer by DMA setting: using function * @ref LL_ADC_REG_ReadMultiConversionData32(). * If ADC multimode transfer by DMA is selected: conversion data * is a raw data with ADC master and slave concatenated. * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n * CCR DMACFG LL_ADC_GetMultiDMATransfer * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B */ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); } /** * @brief Set ADC multimode delay between 2 sampling phases. * @note The sampling delay range depends on ADC resolution: * - ADC resolution 12 bits can have maximum delay of 12 cycles. * - ADC resolution 10 bits can have maximum delay of 10 cycles. * - ADC resolution 8 bits can have maximum delay of 8 cycles. * - ADC resolution 6 bits can have maximum delay of 6 cycles. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param MultiTwoSamplingDelay This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) * * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n * (3) Parameter available only if ADC resolution is 12 bits. * @retval None */ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); } /** * @brief Get ADC multimode delay between 2 sampling phases. * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) * * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n * (3) Parameter available only if ADC resolution is 12 bits. */ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance * @{ */ /** * @brief Put ADC instance in deep power down state. * @note In case of ADC calibration necessary: When ADC is in deep-power-down * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD); } /** * @brief Disable ADC deep power down mode. * @note In case of ADC calibration necessary: When ADC is in deep-power-down * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); } /** * @brief Get the selected ADC instance deep power down state. * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } /** * @brief Enable ADC instance internal voltage regulator. * @note On this STM32 series, after ADC internal voltage regulator enable, * a delay for ADC internal voltage regulator stabilization * is required before performing a ADC calibration or ADC enable. * Refer to device datasheet, parameter tADCVREG_STUP. * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } /** * @brief Disable ADC internal voltage regulator. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); } /** * @brief Get the selected ADC instance internal voltage regulator state. * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } /** * @brief Enable the selected ADC instance. * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled and ADC internal voltage regulator enabled. * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } /** * @brief Disable the selected ADC instance. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be not disabled. Must be enabled without conversion on going * on either groups regular or injected. * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } /** * @brief Get the selected ADC instance enable state. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } /** * @brief Get the selected ADC instance disable state. * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } /** * @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). * @note On this STM32 series, a minimum number of ADC clock cycles * are required between ADC end of calibration and ADC enable. * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. * @note For devices with differential mode available: * Calibration of offset is specific to each of * single-ended and differential modes * (calibration run must be performed for each of these * differential modes, if used afterwards and if the application * requires their calibration). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADCAL LL_ADC_StartCalibration\n * CR ADCALDIF LL_ADC_StartCalibration * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK)); } /** * @brief Get ADC calibration state. * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } /** * @} */ /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular * @{ */ /** * @brief Start ADC group regular conversion. * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, * without ADC disable command on going. * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } /** * @brief Stop ADC group regular conversion. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group regular, * without ADC disable command on going. * @rmtoll CR ADSTP LL_ADC_REG_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTP); } /** * @brief Get ADC group regular conversion state. * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } /** * @brief Get ADC group regular command of conversion stop state * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } /** * @brief Start ADC sampling phase for sampling time trigger mode * @note This function is relevant only when * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set * using @ref LL_ADC_REG_SetSamplingMode * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, * without ADC disable command on going. * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) { SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); } /** * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion * @note This function is relevant only when * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set * using @ref LL_ADC_REG_SetSamplingMode * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source * - @ref LL_ADC_REG_StartSamplingPhase has been called to start * the sampling phase * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, * without ADC disable command on going. * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); } /** * @brief Get ADC group regular conversion data, range fit for * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 12 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 10 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 8 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 6 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Get ADC multimode conversion data of ADC master, ADC slave * or raw data with ADC master and slave concatenated. * @note If raw data with ADC master and slave concatenated is retrieved, * a macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). * (however this macro is mainly intended for multimode * transfer by DMA, because this function can do the same * by getting multimode conversion data of ADC master or ADC slave * separately). * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param ConversionData This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_MASTER * @arg @ref LL_ADC_MULTI_SLAVE * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >> (POSITION_VAL(ConversionData) & 0x1FUL) ); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected * @{ */ /** * @brief Start ADC group injected conversion. * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group injected, * without conversion stop command on going on group injected, * without ADC disable command on going. * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART); } /** * @brief Stop ADC group injected conversion. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group injected, * without ADC disable command on going. * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP); } /** * @brief Get ADC group injected conversion state. * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } /** * @brief Get ADC group injected command of conversion stop state * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } /** * @brief Get ADC group injected conversion data, range fit for * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 12 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 10 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 8 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 6 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @} */ /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management * @{ */ /** * @brief Get flag ADC ready. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular end of sequence conversions. * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular overrun. * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular end of sampling phase. * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } /** * @brief Get flag ADC group injected end of unitary conversion. * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } /** * @brief Get flag ADC group injected end of sequence conversions. * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } /** * @brief Get flag ADC group injected contexts queue overflow. * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } /** * @brief Get flag ADC analog watchdog 1 flag * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } /** * @brief Get flag ADC analog watchdog 2. * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } /** * @brief Get flag ADC analog watchdog 3. * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } /** * @brief Clear flag ADC ready. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); } /** * @brief Clear flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); } /** * @brief Clear flag ADC group regular end of sequence conversions. * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); } /** * @brief Clear flag ADC group regular overrun. * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); } /** * @brief Clear flag ADC group regular end of sampling phase. * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); } /** * @brief Clear flag ADC group injected end of unitary conversion. * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC); } /** * @brief Clear flag ADC group injected end of sequence conversions. * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS); } /** * @brief Clear flag ADC group injected contexts queue overflow. * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); } /** * @brief Clear flag ADC analog watchdog 1. * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); } /** * @brief Clear flag ADC analog watchdog 2. * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); } /** * @brief Clear flag ADC analog watchdog 3. * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Get flag multimode ADC ready of the ADC master. * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC ready of the ADC slave. * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master. * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave. * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular overrun of the ADC master. * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular overrun of the ADC slave. * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sampling of the ADC master. * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sampling of the ADC slave. * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master. * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave. * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected context queue overflow of the ADC master. * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave. * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode analog watchdog 1 of the ADC slave. * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 2 of the ADC master. * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave. * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 3 of the ADC master. * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave. * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_IT_Management ADC IT management * @{ */ /** * @brief Enable ADC ready. * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); } /** * @brief Enable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_EOC); } /** * @brief Enable interruption ADC group regular end of sequence conversions. * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_EOS); } /** * @brief Enable ADC group regular interruption overrun. * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_OVR); } /** * @brief Enable interruption ADC group regular end of sampling. * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); } /** * @brief Enable interruption ADC group injected end of unitary conversion. * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_JEOC); } /** * @brief Enable interruption ADC group injected end of sequence conversions. * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_JEOS); } /** * @brief Enable interruption ADC group injected context queue overflow. * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); } /** * @brief Enable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); } /** * @brief Enable interruption ADC analog watchdog 2. * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); } /** * @brief Enable interruption ADC analog watchdog 3. * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); } /** * @brief Disable interruption ADC ready. * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); } /** * @brief Disable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); } /** * @brief Disable interruption ADC group regular end of sequence conversions. * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); } /** * @brief Disable interruption ADC group regular overrun. * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); } /** * @brief Disable interruption ADC group regular end of sampling. * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); } /** * @brief Disable interruption ADC group regular end of unitary conversion. * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC); } /** * @brief Disable interruption ADC group injected end of sequence conversions. * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS); } /** * @brief Disable interruption ADC group injected context queue overflow. * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); } /** * @brief Disable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); } /** * @brief Disable interruption ADC analog watchdog 2. * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); } /** * @brief Disable interruption ADC analog watchdog 3. * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); } /** * @brief Get state of interruption ADC ready * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular end of unitary conversion * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular end of sequence conversions * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular overrun * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular end of sampling * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group injected end of unitary conversion * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group injected end of sequence conversions * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group injected context queue overflow interrupt state * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC analog watchdog 1 * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } /** * @brief Get state of interruption Get ADC analog watchdog 2 * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } /** * @brief Get state of interruption Get ADC analog watchdog 3 * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions * @{ */ /* Initialization of some features of ADC common parameters and multimode */ ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); /* De-initialization of ADC instance, ADC group regular and ADC group injected */ /* (availability of ADC group injected depends on STM32 series) */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct); void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); /* Initialization of some features of ADC instance and ADC group injected */ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct); void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_LL_ADC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt ================================================ This software component is provided to you as part of a software package and applicable license terms are in the Package_license file. If you received this software component outside of a package or without applicable license terms, the terms of the BSD-3-Clause license shall apply. You may obtain a copy of the BSD-3-Clause at: https://opensource.org/licenses/BSD-3-Clause ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal.c * @author MCD Application Team * @brief HAL module driver. * This is the common part of the HAL initialization ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be used by the PPP peripheral drivers and the user to start using the HAL. [..] The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup HAL HAL * @brief HAL module driver * @{ */ #ifdef HAL_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** * @brief STM32G4xx HAL Driver version number V1.2.3 */ #define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32G4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\ |(__STM32G4xx_HAL_VERSION_RC)) #if defined(VREFBUF) #define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ #endif /* VREFBUF */ /* ------------ SYSCFG registers bit address in the alias region ------------ */ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) /* --- MEMRMP Register ---*/ /* Alias word address of FB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET #define FB_MODE_BitNumber ((uint8_t)0x8) #define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4)) /* --- GPC Register ---*/ /* Alias word address of CCMER bit */ #define SCSR_OFFSET (SYSCFG_OFFSET + 0x18) #define CCMER_BitNumber ((uint8_t)0x0) #define SCSR_CCMER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4)) /* Private macro -------------------------------------------------------------*/ /* Exported variables ---------------------------------------------------------*/ /** @defgroup HAL_Exported_Variables HAL Exported Variables * @{ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions * @{ */ /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief HAL Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize the Flash interface the NVIC allocation and initial time base clock configuration. (+) De-Initialize common part of the HAL. (+) Configure the time base source to have 1ms time base with a dedicated Tick interrupt priority. (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. (++) Time base configuration function (HAL_InitTick ()) is called automatically at the beginning of the program after reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). (++) Source of time base is configured to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. (++) functions affecting time base configurations are declared as __weak to make override possible in case of other implementations in user file. @endverbatim * @{ */ /** * @brief This function is used to configure the Flash prefetch, the Instruction and Data caches, * the time base source, NVIC and any required global low level hardware * by calling the HAL_MspInit() callback function to be optionally defined in user file * stm32g4xx_hal_msp.c. * * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. * * @note In the default implementation the System Timer (Systick) is used as source of time base. * The Systick configuration is based on HSI clock, as HSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { HAL_StatusTypeDef status = HAL_OK; /* Configure Flash prefetch, Instruction cache, Data cache */ /* Default configuration at reset is: */ /* - Prefetch disabled */ /* - Instruction cache enabled */ /* - Data cache enabled */ #if (INSTRUCTION_CACHE_ENABLE == 0U) __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE == 0U) __HAL_FLASH_DATA_CACHE_DISABLE(); #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { status = HAL_ERROR; } else { /* Init the low level hardware */ HAL_MspInit(); } /* Return function status */ return status; } /** * @brief This function de-initializes common part of the HAL and stops the source of time base. * @note This function is optional. * @retval HAL status */ HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ __HAL_RCC_APB1_FORCE_RESET(); __HAL_RCC_APB1_RELEASE_RESET(); __HAL_RCC_APB2_FORCE_RESET(); __HAL_RCC_APB2_RELEASE_RESET(); __HAL_RCC_AHB1_FORCE_RESET(); __HAL_RCC_AHB1_RELEASE_RESET(); __HAL_RCC_AHB2_FORCE_RESET(); __HAL_RCC_AHB2_RELEASE_RESET(); __HAL_RCC_AHB3_FORCE_RESET(); __HAL_RCC_AHB3_RELEASE_RESET(); /* De-Init the low level hardware */ HAL_MspDeInit(); /* Return function status */ return HAL_OK; } /** * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } /** * @brief DeInitializes the MSP. * @retval None */ __weak void HAL_MspDeInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } /** * @brief This function configures the source of the time base: * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { HAL_StatusTypeDef status = HAL_OK; if (uwTickFreq != 0U) { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); uwTickPrio = TickPriority; } else { status = HAL_ERROR; } } else { status = HAL_ERROR; } } else { status = HAL_ERROR; } /* Return function status */ return status; } /** * @} */ /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim =============================================================================== ##### HAL Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Provide a tick value in millisecond (+) Provide a blocking delay in millisecond (+) Suspend the time base source interrupt (+) Resume the time base source interrupt (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier @endverbatim * @{ */ /** * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; } /** * @brief Provides a tick value in millisecond. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; } /** * @brief This function returns a tick priority. * @retval tick priority */ uint32_t HAL_GetTickPrio(void) { return uwTickPrio; } /** * @brief Set new tick Freq. * @retval status */ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) { HAL_StatusTypeDef status = HAL_OK; uint32_t prevTickFreq; assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { /* Back up uwTickFreq frequency */ prevTickFreq = uwTickFreq; /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); if (status != HAL_OK) { /* Restore previous tick frequency */ uwTickFreq = prevTickFreq; } } return status; } /** * @brief Returns tick frequency. * @retval Tick frequency. * Value of @ref HAL_TickFreqTypeDef. */ uint32_t HAL_GetTickFreq(void) { return uwTickFreq; } /** * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { wait += (uint32_t)(uwTickFreq); } while ((HAL_GetTick() - tickstart) < wait) { } } /** * @brief Suspends Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_SuspendTick(void) { /* Disable SysTick Interrupt */ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_ResumeTick(void) { /* Enable SysTick Interrupt */ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Returns the HAL revision. * @retval version : 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) { return __STM32G4xx_HAL_VERSION; } /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U); } /** * @brief Returns the device identifier. * @retval Device identifier */ uint32_t HAL_GetDEVID(void) { return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } /** * @brief Return the first word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw0(void) { return (READ_REG(*((uint32_t *)UID_BASE))); } /** * @brief Return the second word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw1(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); } /** * @brief Return the third word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw2(void) { return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** * @} */ /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions * @brief HAL Debug functions * @verbatim =============================================================================== ##### HAL Debug functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Enable/Disable Debug module during SLEEP mode (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes (+) Enable/Disable Debug module during STANDBY mode @endverbatim * @{ */ /** * @brief Enable the Debug Module during SLEEP mode. * @retval None */ void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Disable the Debug Module during SLEEP mode. * @retval None */ void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. * @retval None */ void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. * @retval None */ void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Enable the Debug Module during STANDBY mode. * @retval None */ void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Disable the Debug Module during STANDBY mode. * @retval None */ void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @} */ /** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions * @brief HAL SYSCFG configuration functions * @verbatim =============================================================================== ##### HAL SYSCFG configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start a hardware CCMSRAM erase operation (+) Enable/Disable the Internal FLASH Bank Swapping (+) Configure the Voltage reference buffer (+) Enable/Disable the Voltage reference buffer (+) Enable/Disable the I/O analog switch voltage booster @endverbatim * @{ */ /** * @brief Start a hardware CCMSRAM erase operation. * @note As long as CCMSRAM is not erased the CCMER bit will be set. * This bit is automatically reset at the end of the CCMSRAM erase operation. * @retval None */ void HAL_SYSCFG_CCMSRAMErase(void) { /* unlock the write protection of the CCMER bit */ SYSCFG->SKR = 0xCA; SYSCFG->SKR = 0x53; /* Starts a hardware CCMSRAM erase operation*/ SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER); } /** * @brief Enable the Internal FLASH Bank Swapping. * * @note This function can be used only for STM32G4xx devices. * * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) * and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000) * * @retval None */ void HAL_SYSCFG_EnableMemorySwappingBank(void) { SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE); } /** * @brief Disable the Internal FLASH Bank Swapping. * * @note This function can be used only for STM32G4xx devices. * * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) * and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000) * * @retval None */ void HAL_SYSCFG_DisableMemorySwappingBank(void) { CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE); } #if defined(VREFBUF) /** * @brief Configure the internal voltage reference buffer voltage scale. * @param VoltageScaling: specifies the output voltage to achieve * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V. * This requires VDDA equal to or higher than 2.4 V. * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V. * This requires VDDA equal to or higher than 3.15 V. * @retval None */ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); } /** * @brief Configure the internal voltage reference buffer high impedance mode. * @param Mode: specifies the high impedance mode * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); } /** * @brief Tune the Internal Voltage Reference buffer (VREFBUF). * @param TrimmingValue specifies trimming code for VREFBUF calibration * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F * @retval None */ void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); } /** * @brief Enable the Internal Voltage Reference buffer (VREFBUF). * @retval HAL_OK/HAL_TIMEOUT */ HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) { uint32_t tickstart; SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait for VRR bit */ while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) { if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } return HAL_OK; } /** * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); } #endif /* VREFBUF */ /** * @brief Enable the I/O analog switch voltage booster * * @retval None */ void HAL_SYSCFG_EnableIOSwitchBooster(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } /** * @brief Disable the I/O analog switch voltage booster * * @retval None */ void HAL_SYSCFG_DisableIOSwitchBooster(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } /** * @brief Enable the I/O analog switch voltage by VDD * * @retval None */ void HAL_SYSCFG_EnableIOSwitchVDD(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } /** * @brief Disable the I/O analog switch voltage by VDD * * @retval None */ void HAL_SYSCFG_DisableIOSwitchVDD(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } /** @brief CCMSRAM page write protection enable * @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP * @note write protection can only be disabled by a system reset * @retval None */ void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page) { assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page)); SET_BIT(SYSCFG->SWPR, (uint32_t)(Page)); } /** * @} */ /** * @} */ #endif /* HAL_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * + Peripheral State functions * Other functions (extended functions) are available in file * "stm32g4xx_hal_adc_ex.c". * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### ADC peripheral features ##### ============================================================================== [..] (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. (+) Interrupt generation at the end of regular conversion and in case of analog watchdog or overrun events. (+) Single and continuous conversion modes. (+) Scan mode for conversion of several channels sequentially. (+) Data alignment with in-built data coherency. (+) Programmable sampling time (channel wise) (+) External trigger (timer or EXTI) with configurable polarity (+) DMA request generation for transfer of conversions data of regular group. (+) Configurable delay between conversions in Dual interleaved mode. (+) ADC channels selectable single/differential input. (+) ADC offset shared on 4 offset instances. (+) ADC gain compensation (+) ADC calibration (+) ADC conversion of regular group. (+) ADC supply requirements: 1.62 V to 3.6 V. (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). ##### How to use this driver ##### ============================================================================== [..] *** Configuration of top level parameters related to ADC *** ============================================================ [..] (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. (++) Two clock settings are mandatory: (+++) ADC clock (core clock, also possibly conversion clock). (+++) ADC clock (conversions clock). Two possible clock sources: synchronous clock derived from AHB clock or asynchronous clock derived from system clock or PLL (output divider P) running up to 75MHz. (+++) Example: Into HAL_ADC_MspInit() (recommended code location) or with other device clock parameters configuration: (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory) RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected) (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit; (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL; (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); (++) ADC clock source and clock prescaler are configured at ADC level with parameter "ClockPrescaler" using function HAL_ADC_Init(). (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_ENABLE() (++) Configure these ADC pins in analog mode using function HAL_GPIO_Init() (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: (++) Configure the DMA (DMA channel, mode normal or circular, ...) using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, group regular, channels parameters *** ================================================================ [..] (#) Configure the ADC parameters (resolution, data alignment, ...) and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). (#) Optionally, configure the analog watchdog parameters (channels monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). *** Execution of ADC conversions *** ==================================== [..] (#) Optionally, perform an automatic ADC calibration to improve the conversion accuracy using function HAL_ADCEx_Calibration_Start(). (#) ADC driver can be used among three modes: polling, interruption, transfer by DMA. (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() (+++) Retrieve conversion results using function HAL_ADC_GetValue() (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() [..] (@) Callback functions must be implemented in user program: (+@) HAL_ADC_ErrorCallback() (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) (+@) HAL_ADC_ConvCpltCallback() (+@) HAL_ADC_ConvHalfCpltCallback *** Deinitialization of ADC *** ============================================================ [..] (#) Disable the ADC interface (++) ADC clock can be hard reset and disabled at RCC top level. (++) Hard reset of ADC peripherals using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). (++) ADC clock disable using the equivalent macro/functions as configuration step. (+++) Example: Into HAL_ADC_MspDeInit() (recommended code location) or with other device clock parameters configuration: (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); (#) ADC pins configuration (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() (#) Optionally, in case of usage of ADC with interruptions: (++) Disable the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA using function HAL_DMA_Init(). (++) Disable the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_ADC_RegisterCallback() to register an interrupt callback. [..] Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback (+) EndOfSamplingCallback : ADC end of sampling callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback (+) EndOfSamplingCallback : ADC end of sampling callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback [..] By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() or @ref HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup ADC ADC * @brief ADC HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADC_Private_Constants ADC Private Constants * @{ */ #define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES | ADC_CFGR_ALIGN |\ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* - maximum sampling time (640.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ /* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */ /* - ADC oversampling ratio 256 */ /* Calculation: 653 * 4096 * 256 CPU clock cycles max */ /* Unit: cycles of CPU clock. */ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief ADC Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** * @brief Initialize the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (refer to description of RCC configuration for ADC * in header of this file). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @note Parameters related to common ADC registers (ADC clock mode) are set * only if all ADCs are disabled. * If this is not the case, these common parameters setting are * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_cfgr; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0UL; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv)); assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if (hadc->Init.DiscontinuousConvMode == ENABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) && (tmp_adc_is_conversion_on_going_regular == 0UL) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { /* Reset configuration of ADC common register CCR: */ /* */ /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ /* according to adc->Init.ClockPrescaler. It selects the clock */ /* source and sets the clock division factor. */ /* */ /* Some parameters of this register are not reset, since they are set */ /* by other functions and must be kept in case of usage of this */ /* function on the fly (update of a parameter of ADC_InitTypeDef */ /* without needing to reconfigure all other ADC groups/channels */ /* parameters): */ /* - when multimode feature is available, multimode-related */ /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); } } /* Configuration of ADC: */ /* - resolution Init.Resolution */ /* - data alignment Init.DataAlign */ /* - external trigger to start conversion Init.ExternalTrigConv */ /* - external trigger polarity Init.ExternalTrigConvEdge */ /* - continuous conversion mode Init.ContinuousConvMode */ /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | hadc->Init.Overrun | hadc->Init.DataAlign | hadc->Init.Resolution | ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); if (hadc->Init.DiscontinuousConvMode == ENABLE) { tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); } /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) | hadc->Init.ExternalTrigConvEdge ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Gain Compensation Init.GainCompensation */ /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); if (hadc->Init.GainCompensation != 0UL) { SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); } else { CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); } if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TROVS | ADC_CFGR2_ROVSM, ADC_CFGR2_ROVSE | hadc->Init.Oversampling.Ratio | hadc->Init.Oversampling.RightBitShift | hadc->Init.Oversampling.TriggeredMode | hadc->Init.Oversampling.OversamplingStopReset ); } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } } /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: * all ADC instances use the same core clock at RCC level, disabling * the core clock reset all ADC instances). * If this is not the case, reset of these common parameters reset is * bypassed without error reporting: it can be the intended behavior in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: * this saves more power by reducing leakage currents * and is particularly interesting before entering MCU low-power modes. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ /* Flush register JSQR: reset the queue sequencer when injected */ /* queue sequencer is enabled and ADC disabled. */ /* The software and hardware triggers of the injected sequence are both */ /* internally disabled just after the completion of the last valid */ /* injected sequence. */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; } } /* Note: HAL ADC deInit is done independently of ADC conversion stop */ /* and disable return status. In case of status fail, attempt to */ /* perform deinitialization anyway and it is up user code in */ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ /* system RCC hard reset. */ /* ========== Reset ADC registers ========== */ /* Reset register IER */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF | ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC | ADC_IT_EOSMP | ADC_IT_RDY)); /* Reset register ISR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF | ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); /* Reset register CR */ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": no direct reset applicable. Update CR register to reset value where doable by software */ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); /* Reset register CFGR */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); /* Reset register CFGR2 */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); /* Reset register TR1 */ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); /* Reset register TR2 */ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); /* Reset register TR3 */ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L); /* Reset register SQR2 */ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5); /* Reset register SQR3 */ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10); /* Reset register SQR4 */ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); /* Register JSQR was reset when the ADC was disabled */ /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ /* Reset register OFR1 */ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); /* Reset register OFR3 */ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); /* Reset register OFR4 */ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ /* Reset register AWD2CR */ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); /* Reset register AWD3CR */ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); /* Reset register DIFSEL */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); /* Reset register CALFACT */ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); /* ========== Reset common ADC registers ========== */ /* Software is allowed to change common parameters only when all the other ADCs are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { /* Reset configuration of ADC common register CCR: - clock mode: CKMODE, PRESCEN - multimode related parameters (when this feature is available): MDMA, DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API) - internal measurement paths: Vbat, temperature sensor, Vref (set into HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripherals instances */ /* sharing the same common ADC instance: ADC state is forced to */ /* a similar state as after device power-on. */ /* Note: A possible implementation is to add RCC bus reset of ADC */ /* (for example, using macro */ /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } /* DeInit the low level hardware */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Reset injected channel configuration parameters */ hadc->InjectionConfig.ContextQueue = 0; hadc->InjectionConfig.ChannelCount = 0; /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Initialize the ADC MSP. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. */ } /** * @brief DeInitialize the ADC MSP. * @param hadc ADC handle * @note All ADC instances use the same core clock at RCC level, disabling * the core clock reset all ADC instances). * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. */ } #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief Register a User ADC Callback * To be used instead of the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; return HAL_ERROR; } if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = pCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = pCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = pCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = pCallback; break; case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = pCallback; break; case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = pCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } /** * @brief Unregister a ADC Callback * ADC callback is redirected to the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; break; case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions * @brief ADC IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular group. (+) Stop conversion of regular group. (+) Poll for conversion complete on regular group. (+) Poll for conversion event. (+) Get result of regular channel conversion. (+) Start conversion of regular group and enable interruptions. (+) Stop conversion of regular group and disable interruptions. (+) Handle ADC interrupt request (+) Start conversion of regular group and enable DMA transfer. (+) Stop conversion of regular group and disable ADC DMA transfer. @endverbatim * @{ */ /** * @brief Enable ADC, start conversion of regular group. * @note Interruptions enabled in this function: None. * @note Case of multimode enabled (when multimode feature is available): * if ADC is Slave, ADC is enabled but conversion is not started, * if ADC is master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* if Master ADC JAUTO bit is set, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } #else if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); #endif /* ADC_MULTIMODE_SUPPORT */ } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for regular group conversion to be completed. * @note ADC conversion flags EOS (end of sequence) and EOC (end of * conversion) are cleared by this function, with an exception: * if low power feature "LowPowerAutoWait" is enabled, flags are * not cleared to not interfere with this feature until data register * is read using function HAL_ADC_GetValue(). * @note This function cannot be used in a particular setup: ADC configured * in DMA mode and polling for end of each conversion (ADC init * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_End; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_Flag_End = ADC_FLAG_EOS; } /* If end of conversion selected to end of unitary conversion */ else /* ADC_EOC_SINGLE_CONV */ { /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* Check ADC DMA mode in independent mode on ADC group regular */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } else { tmp_Flag_End = (ADC_FLAG_EOC); } } else { /* Check ADC DMA mode in multimode on ADC group regular */ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } else { tmp_Flag_End = (ADC_FLAG_EOC); } } #else /* Check ADC DMA mode */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } else { tmp_Flag_End = (ADC_FLAG_EOC); } #endif /* ADC_MULTIMODE_SUPPORT */ } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait until End of unitary conversion or sequence conversions flag is raised */ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Check whether end of sequence is reached */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* Retrieve Master ADC CFGR register */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* ADC_MULTIMODE_SUPPORT */ /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); } else { /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } } /* Return function status */ return HAL_OK; } /** * @brief Poll for ADC event. * @param hadc ADC handle * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on * all STM32 series) * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on * all STM32 series) * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on * all STM32 series) * @arg @ref ADC_OVR_EVENT ADC Overrun event * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. * Indeed, the latter is reset only if hadc->Init.Overrun field is set * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten * by a new converted data as soon as OVR is cleared. * To reset OVR flag once the preserved data is retrieved, the user can resort * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick count */ tickstart = HAL_GetTick(); /* Check selected event flag */ while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } switch (EventType) { /* End Of Sampling event */ case ADC_EOSMP_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); /* Clear the End Of Sampling flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); break; /* Analog watchdog (level out of window) event */ /* Note: In case of several analog watchdog enabled, if needed to know */ /* which one triggered and on which ADCx, test ADC state of analog watchdog */ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ /* For example: */ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ /* Check analog watchdog 1 flag */ case ADC_AWD_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); break; /* Check analog watchdog 2 flag */ case ADC_AWD2_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); break; /* Check analog watchdog 3 flag */ case ADC_AWD3_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); break; /* Injected context queue overflow event */ case ADC_JQOVF_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); /* Clear ADC Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); break; /* Overrun event */ default: /* Case ADC_OVR_EVENT */ /* If overrun is set to overwrite previous data, overrun event is not */ /* considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and without */ /* overrun ") */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); } else { /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN otherwise, data register is potentially overwritten by new converted data as soon as OVR is cleared. */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } break; } /* Return function status */ return HAL_OK; } /** * @brief Enable ADC, start conversion of regular group with interruption. * @note Interruptions enabled in this function according to initialization * setting : EOC (end of conversion), EOS (end of sequence), * OVR overrun. * Each of these interruptions has its dedicated callback function. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Start_IT() must be called for ADC Slave first, then for * ADC Master. * For ADC Slave, ADC is enabled only (conversion is not started). * For ADC Master, ADC is enabled and multimode conversion is started. * @note To guarantee a proper reset of all interruptions once all the needed * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure * a correct stop of the IT-based conversions. * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling * interruption. If required (e.g. in case of oversampling with trigger * mode), the user must: * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) * before calling HAL_ADC_Start_IT(). * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Disable all interruptions before enabling the desired ones */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* Enable ADC end of conversion interrupt */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); break; } /* Enable ADC overrun interrupt */ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is ADC_IT_OVR enabled; otherwise data overwrite is considered as normal behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); } /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Enable as well injected interruptions in case HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This allows to start regular and injected conversions when JAUTO is set with a single call to HAL_ADC_Start_IT() */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* if Master ADC JAUTO bit is set, Slave injected interruptions are enabled nevertheless (for same reason as above) */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Next, set Slave injected interruptions */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } } } #else /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Enable as well injected interruptions in case HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This allows to start regular and injected conversions when JAUTO is set with a single call to HAL_ADC_Start_IT() */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); #endif /* ADC_MULTIMODE_SUPPORT */ } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enable ADC, start conversion of regular group and transfer result through DMA. * @note Interruptions enabled in this function: * overrun (if applicable), DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() * is designed for single-ADC mode only. For multimode, the dedicated * HAL_ADCEx_MultiModeStart_DMA() function must be used. * @param hadc ADC handle * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); #if defined(ADC_MULTIMODE_SUPPORT) /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((ADC_IS_INDEPENDENT(hadc) != RESET) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) #endif /* ADC_MULTIMODE_SUPPORT */ { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } #if defined(ADC_MULTIMODE_SUPPORT) else { tmp_hal_status = HAL_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); } #endif /* ADC_MULTIMODE_SUPPORT */ } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on ADC group injected. If ADC group injected is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential ADC group regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent * to flag EOC. * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; } /** * @brief Start ADC conversion sampling phase of regular group * @note: This function should only be called to start sampling when * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling * mode has been selected * - @ref ADC_SOFTWARE_START has been selected as trigger source * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Start sampling */ SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); /* Return function status */ return HAL_OK; } /** * @brief Stop ADC conversion sampling phase of regular group and start conversion * @note: This function should only be called to stop sampling when * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling * mode has been selected * - @ref ADC_SOFTWARE_START has been selected as trigger source * - after sampling has been started using @ref HAL_ADC_StartSampling. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Start sampling */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); /* Return function status */ return HAL_OK; } /** * @brief Handle ADC interrupt request. * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ uint32_t tmp_isr = hadc->Instance->ISR; uint32_t tmp_ier = hadc->Instance->IER; uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); /* ========== Check End of Sampling flag for ADC group regular ========== */ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); } /* End Of Sampling callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->EndOfSamplingCallback(hadc); #else HAL_ADCEx_EndOfSamplingCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); } /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* check CONT bit directly in handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* else need to check Master ADC CONT bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* ADC_MULTIMODE_SUPPORT */ /* Carry on if continuous mode is disabled */ if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } /* Conversion complete callback */ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ /* to determine if conversion has been triggered from EOC or EOS, */ /* possibility to use: */ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved data.*/ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* ADC_MULTIMODE_SUPPORT */ /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) { if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } } /* Injected Conversion complete callback */ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether interruption has been triggered by end of conversion or end of sequence. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } /* ========== Check Analog watchdog 1 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); } /* ========== Check analog watchdog 2 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Level out of window 2 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow2Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow2Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); } /* ========== Check analog watchdog 3 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Level out of window 3 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow3Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow3Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); } /* ========== Check Overrun flag ========== */ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) { /* If overrun is set to overwrite previous data (default setting), */ /* overrun event is not considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and without */ /* overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { overrun_error = 1UL; } else { /* Check DMA configuration */ #if defined(ADC_MULTIMODE_SUPPORT) if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) { /* Multimode (when feature is available) is enabled, Common Control Register MDMA bits must be checked. */ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { overrun_error = 1UL; } } else #endif /* ADC_MULTIMODE_SUPPORT */ { /* Multimode not set or feature not available or ADC independent */ if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) { overrun_error = 1UL; } } } if (overrun_error == 1UL) { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); /* Error callback */ /* Note: In case of overrun, ADC conversion data is preserved until */ /* flag OVR is reset. */ /* Therefore, old ADC conversion data can be retrieved in */ /* function "HAL_ADC_ErrorCallback()". */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } /* ========== Check Injected context queue overflow flag ========== */ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { /* Change ADC state to overrun state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); /* Injected context queue overflow callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedQueueOverflowCallback(hadc); #else HAL_ADCEx_InjectedQueueOverflowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } } /** * @brief Conversion complete callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } /** * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } /** * @brief Analog watchdog 1 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } /** * @brief ADC error callback in non-blocking mode * (ADC conversion with interruption or transfer by DMA). * @note In case of error due to overrun when using ADC with DMA transfer * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } /** * @} */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog @endverbatim * @{ */ /** * @brief Configure a channel to be assigned to ADC group regular. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * These internal paths can be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into ADC group regular, * following calls to this function can be used to reconfigure * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, * without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". * @param hadc ADC handle * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0UL; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff)); assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset)); /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); } else { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); } /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); if (pConfig->OffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign)); assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation)); /* Set ADC selected offset sign & saturation */ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign); LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, (pConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); /* Configuration of differential mode */ if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + 1UL) & 0x1FUL)), pConfig->SamplingTime); } } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } } else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } else { /* nothing to do */ } } } /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Configure the analog watchdog. * @note Possibility to update parameters on the fly: * This function initializes the selected analog watchdog, successive * calls to this function can be used to reconfigure some parameters * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". * @note On this STM32 series, analog watchdog thresholds can be modified * while ADC conversion is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next * ADC EOC (end of unitary conversion). * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc ADC handle * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_awd_high_threshold_shifted; uint32_t tmp_awd_low_threshold_shifted; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode)); assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig)); assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode)); if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel)); } /* Verify thresholds range */ if (hadc->Init.OversamplingMode == ENABLE) { /* Case of oversampling enabled: depending on ratio and shift configuration, analog watchdog thresholds can be higher than ADC resolution. Verify if thresholds are within maximum thresholds range. */ assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold)); } else { /* Verify if thresholds are within the selected ADC resolution */ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold)); } /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on ADC groups regular and injected: */ /* - Analog watchdog channels */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Analog watchdog configuration */ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels, on groups regular and-or injected. */ switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); break; case ADC_ANALOGWATCHDOG_SINGLE_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); break; case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); break; case ADC_ANALOGWATCHDOG_ALL_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); break; case ADC_ANALOGWATCHDOG_ALL_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); break; case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); break; } /* Set the filtering configuration */ MODIFY_REG(hadc->Instance->TR1, ADC_TR1_AWDFILT, pAnalogWDGConfig->FilteringConfig); /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD1(hadc->Instance); /* Configure ADC analog watchdog interrupt */ if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } else { LL_ADC_DisableIT_AWD1(hadc->Instance); } } /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: case ADC_ANALOGWATCHDOG_SINGLE_INJEC: case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } else { SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL))); } break; case ADC_ANALOGWATCHDOG_ALL_REG: case ADC_ANALOGWATCHDOG_ALL_INJEC: case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD2(hadc->Instance); /* Configure ADC analog watchdog interrupt */ if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } else { LL_ADC_DisableIT_AWD2(hadc->Instance); } } /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { /* Update state, clear previous result related to AWD3 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD3(hadc->Instance); /* Configure ADC analog watchdog interrupt */ if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } else { LL_ADC_DisableIT_AWD3(hadc->Instance); } } } } /* Analog watchdog thresholds configuration */ if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0. */ tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); } /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ else { /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */ /* are set to 0. */ tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); } /* Set ADC analog watchdog thresholds value of both thresholds high and low */ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted, tmp_awd_low_threshold_shifted); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @} */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions * @brief ADC Peripheral State functions * @verbatim =============================================================================== ##### Peripheral state and errors functions ##### =============================================================================== [..] This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @endverbatim * @{ */ /** * @brief Return the ADC handle state. * @note ADC state machine is managed by bitfields, ADC status must be * compared with states bits. * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Return ADC handle state */ return hadc->State; } /** * @brief Return the ADC error code. * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); return hadc->ErrorCode; } /** * @} */ /** * @} */ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @brief Stop ADC conversion. * @param hadc ADC handle * @param ConversionGroup ADC group regular and/or injected. * This parameter can be one of the following values: * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { uint32_t tickstart; uint32_t Conversion_Timeout_CPU_cycles = 0UL; uint32_t conversion_group_reassigned = ConversionGroup; uint32_t tmp_ADC_CR_ADSTART_JADSTART; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular != 0UL) || (tmp_adc_is_conversion_on_going_injected != 0UL) ) { /* Particular case of continuous auto-injection mode combined with */ /* auto-delay mode. */ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) && (hadc->Init.ContinuousConvMode == ENABLE) && (hadc->Init.LowPowerAutoWait == ENABLE) ) { /* Use stop of regular group */ conversion_group_reassigned = ADC_REGULAR_GROUP; /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) { if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } Conversion_Timeout_CPU_cycles ++; } /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); } /* Stop potential conversion on going on ADC group regular */ if (conversion_group_reassigned != ADC_INJECTED_GROUP) { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) { /* Stop ADC group regular conversion */ LL_ADC_REG_StopConversion(hadc->Instance); } } } /* Stop potential conversion on going on ADC group injected */ if (conversion_group_reassigned != ADC_REGULAR_GROUP) { /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) { /* Stop ADC group injected conversion */ LL_ADC_INJ_StopConversion(hadc->Instance); } } } /* Selection of start and stop bits with respect to the regular or injected group */ switch (conversion_group_reassigned) { case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); break; case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; break; /* Case ADC_REGULAR_GROUP only*/ default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; break; } /* Wait for conversion effectively stopped */ tickstart = HAL_GetTick(); while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; __IO uint32_t wait_loop_index = 0UL; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) { /* Delay for temperature sensor buffer stabilization time */ /* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of */ /* LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed */ /* in case of ADC enable after a system wake up */ /* from low power mode. */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit has been cleared (after a calibration), ADEN bit is reset by the calibration logic. The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_Enable(hadc->Instance); } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief Disable the selected ADC. * @note Prerequisite condition to use this function: ADC conversions must be * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_disable_on_going == 0UL) ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else /* DMA and-or internal error occurred */ { if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) { /* Call HAL ADC Error Callback function */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } /** * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Peripheral Control functions * Other functions (generic functions) are available in file * "stm32g4xx_hal_adc.c". * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32g4xx_hal_adc.c". [..] @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup ADCEx ADCEx * @brief ADC Extended HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants * @{ */ #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ /* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value */ /* considering both possible ADC clocking scheme: */ /* - ADC clock from synchronous clock with AHB prescaler 512, */ /* ADC prescaler 4. */ /* Ratio max = 512 *4 = 2048 */ /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ /* Highest CPU clock PLL (PLLR). */ /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ /* = 3968 ) */ /* Calibration_time MAX = 81 / f_ADC */ /* = 81 / (f_CPU/3938) = 318978 CPU cycles */ #define ADC_CALIBRATION_TIMEOUT (318978UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions * @{ */ /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions * @brief Extended IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. (+) Start conversion of ADC group injected. (+) Stop conversion of ADC group injected. (+) Poll for conversion complete on ADC group injected. (+) Get result of ADC group injected channel conversion. (+) Start conversion of ADC group injected and enable interruptions. (+) Stop conversion of ADC group injected and disable interruptions. (+) When multimode feature is available, start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. @endverbatim * @{ */ /** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @param hadc ADC handle * @param SingleDiff Selection of single-ended or differential input * This parameter can be one of the following values: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, SingleDiff); /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { wait_loop_index++; if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Get the calibration factor. * @param hadc ADC handle. * @param SingleDiff This parameter can be only: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Return the selected ADC calibration value */ return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); } /** * @brief Set the calibration factor to overwrite automatic conversion result. * ADC must be enabled and no conversion is ongoing. * @param hadc ADC handle * @param SingleDiff This parameter can be only: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); /* Process locked */ __HAL_LOCK(hadc); /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Set the selected ADC calibration value */ LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor); } else { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Update ADC error code */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Update ADC state machine to error */ tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enable ADC, start conversion of injected group. * @note Interruptions enabled in this function: None. * @note Case of multimode enabled when multimode feature is available: * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Check if a regular conversion is ongoing */ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* if ADC is slave, */ /* - ADC is enabled only (conversion is not started), */ /* - if multimode only concerns regular conversion, ADC is enabled */ /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { LL_ADC_INJ_StartConversion(hadc->Instance); } } else { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #else if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { /* Start ADC group injected conversion */ LL_ADC_INJ_StartConversion(hadc->Instance); } #endif /* ADC_MULTIMODE_SUPPORT */ } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } } /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of multimode enabled (when multimode feature is available), * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on regular group is on-going */ if (tmp_hal_status == HAL_OK) { if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for injected group conversion to be completed. * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is * checked and cleared depending on AUTDLY bit status. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_flag_end; uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of sequence selected */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_flag_end = ADC_FLAG_JEOS; } else /* end of conversion selected */ { tmp_flag_end = ADC_FLAG_JEOC; } /* Get timeout */ tickstart = HAL_GetTick(); /* Wait until End of Conversion or Sequence flag is raised */ while ((hadc->Instance->ISR & tmp_flag_end) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->ISR & tmp_flag_end) == 0UL) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* ADC_MULTIMODE_SUPPORT */ /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) { /* Check whether end of sequence is reached */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } } /* Clear polled flag */ if (tmp_flag_end == ADC_FLAG_JEOS) { /* Clear end of sequence JEOS flag of injected group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ /* For injected groups, no new conversion will start before JEOS is */ /* cleared. */ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); } } else { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); } /* Return API HAL status */ return HAL_OK; } /** * @brief Enable ADC, start conversion of injected group with interruption. * @note Interruptions enabled in this function according to initialization * setting : JEOC (end of conversion) or JEOS (end of sequence) * @note Case of multimode enabled (when multimode feature is enabled): * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* ADC_MULTIMODE_SUPPORT */ /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Check if a regular conversion is ongoing */ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) { __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); } /* Enable ADC end of conversion interrupt */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* if ADC is slave, */ /* - ADC is enabled only (conversion is not started), */ /* - if multimode only concerns regular conversion, ADC is enabled */ /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { LL_ADC_INJ_StartConversion(hadc->Instance); } } else { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #else if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { /* Start ADC group injected conversion */ LL_ADC_INJ_StartConversion(hadc->Instance); } #endif /* ADC_MULTIMODE_SUPPORT */ } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } } /** * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, * then for ADC slave. * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on the other group (regular group) is intended to */ /* continue. */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. * @note Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: * overrun, DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. * @note State field of Slave ADC handle is not updated in this configuration: * user should not rely on it for information related to Slave regular * conversions. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @param pData Destination Buffer address. * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmp_hadc_slave; ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { /* Process locked */ __HAL_LOCK(hadc); /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); if (tmp_hadc_slave.Instance == NULL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Enable(&tmp_hadc_slave); } /* Start multimode conversion of ADCs pair */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } } /** * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral. * @note Multimode is kept enabled after this function. MultiMode DMA bits * (MDMA and DMACFG bits of common CCR register) are maintained. To disable * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can * resort to HAL_ADCEx_DisableMultiMode() API. * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmp_hadc_slave; uint32_t tmp_hadc_slave_conversion_on_going; HAL_StatusTypeDef tmp_hadc_slave_disable_status; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential multimode conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmp_hadc_slave_conversion_on_going == 1UL) ) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmp_hadc_slave_conversion_on_going == 1UL) ) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADC_Stop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_ERROR) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripherals: master and slave */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave); if ((ADC_Disable(hadc) == HAL_OK) && (tmp_hadc_slave_disable_status == HAL_OK)) { tmp_hal_status = HAL_OK; } } else { /* In case of error, attempt to disable ADC master and slave without status assert */ (void) ADC_Disable(hadc); (void) ADC_Disable(&tmp_hadc_slave); } /* Set ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Prevent unused argument(s) compilation warning if no assert_param check */ /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ UNUSED(hadc); /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Return the multi mode conversion value */ return tmpADC_Common->CDR; } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent * to flag JEOC. * - If sequencer is composed of several ranks, during the scan * sequence flag JEOC only is raised, at the end of the scan sequence * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 series). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc ADC handle * @param InjectedRank the converted ADC injected rank. * This parameter can be one of the following values: * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); /* Get ADC converted value */ switch (InjectedRank) { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: default: tmp_jdr = hadc->Instance->JDR1; break; } /* Return ADC converted value */ return tmp_jdr; } /** * @brief Injected conversion complete callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. */ } /** * @brief Injected context queue overflow callback. * @note This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts). * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } /** * @brief Analog watchdog 2 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. */ } /** * @brief Analog watchdog 3 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. */ } /** * @brief End Of Sampling callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. */ } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral if no * conversion is on going on injected group. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if regular conversions are effectively stopped and if no injected conversions are on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of ADC groups regular and injected, * disable interrution of end-of-conversion, * disable ADC peripheral if no conversion is on going * on injected group. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Disable all regular-related interrupts */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable ADC peripheral if no injected conversions are on-going */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { tmp_hal_status = ADC_Disable(hadc); /* if no issue reported */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral if no conversion is on going * on injected group. * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. * For multimode (when multimode feature is available), * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected * conversion is on-going. * @note Multimode is kept enabled after this function. Multimode DMA bits * (MDMA and DMACFG bits of common CCR register) are maintained. To disable * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can * resort to HAL_ADCEx_DisableMultiMode() API. * @note In case of DMA configured in circular mode, function * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmp_hadc_slave; uint32_t tmp_hadc_slave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential multimode conversion on going, on regular groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmp_hadc_slave_conversion_on_going == 1UL) ) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmp_hadc_slave_conversion_on_going == 1UL) ) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADCEx_RegularStop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripherals: master and slave if no injected */ /* conversion is on-going. */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { tmp_hal_status = ADC_Disable(hadc); if (tmp_hal_status == HAL_OK) { if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL) { tmp_hal_status = ADC_Disable(&tmp_hadc_slave); } } } if (tmp_hal_status == HAL_OK) { /* Both Master and Slave ADC's could be disabled. Update Master State */ /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } else { /* injected (Master or Slave) conversions are still on-going, no Master State change */ } } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions * @brief ADC Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on injected group (+) Configure multimode when multimode feature is available (+) Enable or Disable Injected Queue (+) Disable ADC voltage regulator (+) Enter ADC deep-power-down mode @endverbatim * @{ */ /** * @brief Configure a channel to be assigned to ADC group injected. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_InjectionConfTypeDef". * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * These internal paths can be disabled using function * HAL_ADC_DeInit(). * @note Caution: For Injected Context Queue use, a context must be fully * defined before start of injected conversion. All channels are configured * consecutively for the same ADC instance. Therefore, the number of calls to * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter * InjectedNbrOfConversion for each context. * - Example 1: If 1 context is intended to be used (or if there is no use of the * Injected Queue Context feature) and if the context contains 3 injected ranks * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be * called once for each channel (i.e. 3 times) before starting a conversion. * This function must not be called to configure a 4th injected channel: * it would start a new context into context queue. * - Example 2: If 2 contexts are intended to be used and each of them contains * 3 injected ranks (InjectedNbrOfConversion = 3), * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and * for each context (3 channels x 2 contexts = 6 calls). Conversion can * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. * @param hadc ADC handle * @param pConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *pConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_offset_shifted; uint32_t tmp_config_internal_channel; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0; uint32_t tmp_jsqr_context_queue_being_built = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff)); assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext)); assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge)); assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset)); assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign)); assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation)); assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode)); } /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (pConfigInjected->InjecOversamplingMode == ENABLE))); /* JDISCEN and JAUTO bits can't be set at the same time */ assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE))); /* DISCEN and JAUTO bits can't be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE))); /* Verification of channel number */ if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* Hardware constraint: Must fully define injected context register JSQR */ /* before make it entering into injected sequencer queue. */ /* */ /* - if scan mode is disabled: */ /* * Injected channels sequence length is set to 0x00: 1 channel */ /* converted (channel on injected rank 1) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* * Injected context register JSQR setting is simple: register is fully */ /* defined on one call of this function (for injected rank 1) and can */ /* be entered into queue directly. */ /* - if scan mode is enabled: */ /* * Injected channels sequence length is set to parameter */ /* "InjectedNbrOfConversion". */ /* * Injected context register JSQR setting more complex: register is */ /* fully defined over successive calls of this function, for each */ /* injected channel rank. It is entered into queue only when all */ /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || (pConfigInjected->InjectedNbrOfConversion == 1U)) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ /* (scan mode disabled, only rank 1 used) */ /* - external trigger to start conversion */ /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) | pConfigInjected->ExternalTrigInjecConvEdge ); } else { tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); } MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built; } } else { /* Case of scan mode enabled, several channels to set into injected group */ /* sequencer. */ /* */ /* Procedure to define injected context register JSQR over successive */ /* calls of this function, for each injected channel rank: */ /* 1. Start new context and set parameters related to all injected */ /* channels: injected sequence length and trigger. */ /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ /* call of the context under setting */ if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion; /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ hadc->InjectionConfig.ContextQueue = 0x00000000U; /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ /* - external trigger to start conversion */ /* - external trigger polarity */ /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U) | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) | pConfigInjected->ExternalTrigInjecConvEdge ); } else { tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)); } } /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank); /* Set the JSQx bits for the selected rank */ tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank); /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel() call, aggregate the setting to those already built during the previous HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built; /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ if (hadc->InjectionConfig.ChannelCount == 0U) { MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on injected group: */ /* - Injected context queue: Queue disable (active context is kept) or */ /* enable (context decremented, up to 2 contexts queued) */ /* - Injected discontinuous mode: can be enabled only if auto-injected */ /* mode is disabled. */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* If auto-injected mode is disabled: no constraint */ if (pConfigInjected->AutoInjectedConv == DISABLE) { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext) | ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode)); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext)); } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Automatic injected conversion: can be enabled if injected group */ /* external triggers are disabled. */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) { if (pConfigInjected->AutoInjectedConv == ENABLE) { SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } else { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } } /* If Automatic injected conversion was intended to be set and could not */ /* due to injected group external triggers enabled, error is reported. */ else { if (pConfigInjected->AutoInjectedConv == ENABLE) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } else { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } } if (pConfigInjected->InjecOversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift)); /* JOVSE must be reset in case of triggered regular mode */ assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); /* Configuration of Injected Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* Enable OverSampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS, ADC_CFGR2_JOVSE | pConfigInjected->InjecOversampling.Ratio | pConfigInjected->InjecOversampling.RightBitShift ); } else { /* Disable Regular OverSampling */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); } /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); } else { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSamplingTime); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); } /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset); if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel, tmp_offset_shifted); /* Set ADC selected offset sign & saturation */ LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign); LL_ADC_SetOffsetSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber, (pConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff); /* Configuration of differential mode */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( (__LL_ADC_CHANNEL_TO_DECIMAL_NB( (uint32_t)pConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), pConfigInjected->InjectedSamplingTime); } } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5)) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } } else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } else { /* nothing to do */ } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: * This function initializes multimode parameters, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_MultiModeTypeDef" on the fly, without resetting * the ADCs. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc Master ADC handle * @param pMultimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmp_hadc_slave; uint32_t tmp_hadc_slave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MULTIMODE(pMultimode->Mode)); if (pMultimode->Mode != ADC_MODE_INDEPENDENT) { assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); if (tmp_hadc_slave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) && (tmp_hadc_slave_conversion_on_going == 0UL)) { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (pMultimode->Mode != ADC_MODE_INDEPENDENT) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, pMultimode->DMAAccessMode | ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ /* Note: Delay range depends on selected resolution: */ /* from 1 to 12 clock cycles for 12 bits */ /* from 1 to 10 clock cycles for 10 bits, */ /* from 1 to 8 clock cycles for 8 bits */ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, pMultimode->Mode | pMultimode->TwoSamplingDelay ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); } } } /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Enable Injected Queue * @note This function resets CFGR register JQDIS bit in order to enable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); /* Parameter can be set only if no conversion is on-going */ if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); /* Update state, clear previous result related to injected queue overflow */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @brief Disable Injected Queue * @note This function sets CFGR register JQDIS bit in order to disable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); /* Parameter can be set only if no conversion is on-going */ if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @brief Disable ADC voltage regulator. * @note Disabling voltage regulator allows to save power. This operation can * be carried out only when ADC is disabled. * @note To enable again the voltage regulator, the user is expected to * resort to HAL_ADC_Init() API. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_DisableInternalRegulator(hadc->Instance); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @brief Enter ADC deep-power-down mode * @note This mode is achieved in setting DEEPPWD bit and allows to save power * in reducing leakage currents. It is particularly interesting before * entering stop modes. * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the * ADC voltage regulator. This means that this API encompasses * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal * calibration is lost. * @note To exit the ADC deep-power-down mode, the user is expected to * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously * saved calibration factor. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_EnableDeepPowerDown(hadc->Instance); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @} */ /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_cortex.c * @author MCD Application Team * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: * + Initialization and Configuration functions * + Peripheral Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== [..] This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the sub priority. -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest pre-emption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) [..] *** How to configure SysTick using CORTEX HAL driver *** ======================================================== [..] Setup SysTick Timer for time base. (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. (++) Configures the SysTick IRQ priority to the lowest value (0x0F). (++) Resets the SysTick Counter register. (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined inside the stm32g4xx_hal_cortex.h file. (+) You can change the SysTick IRQ priority by calling the HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF @endverbatim ****************************************************************************** The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. ========================================================================================================================== NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ========================================================================================================================== NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority | | | 4 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority | | | 3 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bit for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority | | | 0 bit for subpriority ========================================================================================================================== */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup CORTEX * @{ */ #ifdef HAL_CORTEX_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions * @{ */ /** @addtogroup CORTEX_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and Configuration functions ##### ============================================================================== [..] This section provides the CORTEX HAL driver functions allowing to configure Interrupts SysTick functionalities @endverbatim * @{ */ /** * @brief Set the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, * 1 bit for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, * 0 bit for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } /** * @brief Set the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @param PreemptPriority: The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t prioritygroup; /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enable a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } /** * @brief Disable a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } /** * @brief Initiate a system reset request to reset the MCU. * @retval None */ void HAL_NVIC_SystemReset(void) { /* System Reset */ NVIC_SystemReset(); } /** * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): * Counter is in free running mode to generate periodic interrupts. * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } /** * @} */ /** @addtogroup CORTEX_Exported_Functions_Group2 * @brief Cortex control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX (NVIC, SYSTICK, MPU) functionalities. @endverbatim * @{ */ /** * @brief Get the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) */ uint32_t HAL_NVIC_GetPriorityGrouping(void) { /* Get the PRIGROUP[10:8] field value */ return NVIC_GetPriorityGrouping(); } /** * @brief Get the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, * 1 bit for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, * 0 bit for subpriority * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). * @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Get priority for Cortex-M system or device specific interrupts */ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); } /** * @brief Set Pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** * @brief Get Pending Interrupt (read the pending register in the NVIC * and return the pending bit for the specified interrupt). * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } /** * @brief Clear the pending bit of an external interrupt. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } /** * @brief Get active interrupt (read the active register in NVIC and return the active bit). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) { /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } /** * @brief Configure the SysTick clock source. * @param CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); if (CLKSource == SYSTICK_CLKSOURCE_HCLK) { SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; } else { SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; } } /** * @brief Handle SYSTICK interrupt request. * @retval None */ void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); } /** * @brief SYSTICK callback. * @retval None */ __weak void HAL_SYSTICK_Callback(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_SYSTICK_Callback could be implemented in the user file */ } #if (__MPU_PRESENT == 1) /** * @brief Enable the MPU. * @param MPU_Control: Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged accessto the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); /* Ensure MPU setting take effects */ __DSB(); __ISB(); } /** * @brief Disable the MPU. * @retval None */ void HAL_MPU_Disable(void) { /* Make sure outstanding transfers are done */ __DMB(); /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; } /** * @brief Initialize and configure the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; if ((MPU_Init->Enable) != 0U) { /* Check the parameters */ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); MPU->RBAR = MPU_Init->BaseAddress; MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } else { MPU->RBAR = 0x00; MPU->RASR = 0x00; } } #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ #endif /* HAL_CORTEX_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac.c * @author MCD Application Team * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions * * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### ============================================================================== [..] *** DAC Channels *** ==================== [..] STM32G4 devices integrate up to seven 12-bit Digital Analog Converters, up to six of them grouped by pair forming a DAC instance. The 2 converters of an single instance (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode): (#) DAC channel1 with DAC_OUT1 as output (not for all) or connected to on-chip peripherals (ex. comparators, operational amplifier). (#) DAC channel2 with DAC_OUT2 as output (not for all) or connected to on-chip peripherals (ex. comparators, operational amplifier). Note: when an instance only includes one converter, only independent mode is supported by this converter. STM32G4 instances & converters availability and output PIO mapping (DAC_OUTx): ---------------------------------------------------------------------------- | DAC1 | DAC2 | DAC3 | DAC4 | ---------------------------------------------------------------------------- Channel 1 | | YES | YES | YES | YES | DAC_OUT1 | PA4 | PA6 | - | - ---------------------------------------------------------------------------- Channel 2 | | YES | NO | YES | YES | DAC_OUT2 | PA5 | - | - | - ---------------------------------------------------------------------------- Note: On this STM32 series, all devices do not include each DAC instances listed above. Refer to device datasheet for DACx instance availability. *** DAC Triggers *** ==================== [..] Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. [..] Digital to Analog conversion can be triggered by: (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. The used pin (GPIOx_PIN_9) must be configured in input mode. (#) Timers TRGO: TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM8 and TIM15 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) (#) Software using DAC_TRIGGER_SOFTWARE (#) HRTimer TRGO: HRTIM1 (1) (DAC_TRIGGER_HRTIM_TRG01, DAC_TRIGGER_HRTIM_TRG02...) [..] Specific triggers for sawtooth generation: (#) External event: EXTI Line 10 (any GPIOx_PIN_10) using DAC_TRIGGER_EXT_IT10. The used pin (GPIOx_PIN_10) must be configured in input mode. (#) HRTimer Step & Reset: HRTIM1 (1) (DAC_TRIGGER_HRTIM_RST_TRG1, DAC_TRIGGER_HRTIM_STEP_TRG1...) Note: On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) *** DAC Buffer mode feature *** =============================== [..] Each DAC channel integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. To enable, the output buffer use sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; [..] (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. *** DAC connect feature *** =============================== [..] Each DAC channel can be connected internally. To connect, use sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL; or sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH; *** GPIO configurations guidelines *** ===================== [..] When a DAC channel is used (ex channel1 on PA4) and the other is not (ex channel2 on PA5 is configured in Analog and disabled). Channel1 may disturb channel2 as coupling effect. Note that there is no coupling on channel2 as soon as channel2 is turned on. Coupling on adjacent channel could be avoided as follows: when unused PA5 is configured as INPUT PULL-UP or DOWN. PA5 is configured in ANALOG just before it is turned on. *** DAC Sample and Hold feature *** ======================== [..] For each converter, 2 modes are supported: normal mode and "sample and hold" mode (i.e. low power mode). In the sample and hold mode, the DAC core converts data, then holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is tri-stated, therefore reducing the overall power consumption. A new stabilization period is needed before each new conversion. The sample and hold allow setting internal or external voltage @ low power consumption cost (output value can be at any given rate either by CPU or DMA). The Sample and hold block and registers uses either LSI & run in several power modes: run mode, sleep mode, low power run, low power sleep mode & stop1 mode. Low power stop1 mode allows only static conversion. To enable Sample and Hold mode Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI & RCC_LSI_ON parameters. Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE; & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime, DAC_HoldTime & DAC_RefreshTime; *** DAC calibration feature *** =================================== [..] (#) The 2 converters (channel1 & channel2) provide calibration capabilities. (++) Calibration aims at correcting some offset of output buffer. (++) The DAC uses either factory calibration settings OR user defined calibration (trimming) settings (i.e. trimming mode). (++) The user defined settings can be figured out using self calibration handled by HAL_DACEx_SelfCalibrate. (++) HAL_DACEx_SelfCalibrate: (+++) Runs automatically the calibration. (+++) Enables the user trimming mode (+++) Updates a structure with trimming values with fresh calibration results. The user may store the calibration results for larger (ex monitoring the trimming as a function of temperature for instance) *** DAC wave generation feature *** =================================== [..] Both DAC channels can be used to generate (#) Noise wave (#) Triangle wave (#) Sawtooth wave *** DAC data format *** ======================= [..] The DAC data format can be: (#) 8-bit right alignment using DAC_ALIGN_8B_R (#) 12-bit left alignment using DAC_ALIGN_12B_L (#) 12-bit right alignment using DAC_ALIGN_12B_R *** DAC data value to voltage correspondence *** ================================================ [..] The analog output voltage on each DAC channel pin is determined by the following equation: [..] DAC_OUTx = VREF+ * DOR / 4095 (+) with DOR is the Data Output Register [..] VREF+ is the input voltage reference (refer to the device datasheet) [..] e.g. To set DAC_OUT1 to 0.7V, use (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V *** DMA requests *** ===================== [..] A DMAMUX request can be generated when an external trigger (but not a software trigger) occurs if DMAMUX requests are enabled using HAL_DAC_Start_DMA(). DMAMUX requests are mapped as following: ---------------------------------------------------------------------------- | DAC1 | DAC2 | DAC3 | DAC4 | ---------------------------------------------------------------------------- Channel 1 | | 6 | 41 | 102 | 104 ---------------------------------------------------------------------------- Channel 2 | | 7 | - | 103 | 105 ---------------------------------------------------------------------------- Note: On this STM32 series, all devices do not include each DAC instances listed above. Refer to device datasheet for DACx instance availability. *** High frequency interface mode *** ===================================== [..] The high frequency interface informs DAC instance about the bus frequency in use. It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent) provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function. Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended function figured out the correct setting. The high frequency mode is same for all converters of a same DAC instance. Either same parameter DAC_HighFrequency is used for all DAC converters or again self DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter. [..] (@) For Dual mode and specific signal (Sawtooth, triangle and noise) generation please refer to Extended Features Driver description ##### How to use this driver ##### ============================================================================== [..] (+) DAC APB clock must be enabled to get write access to DAC registers using HAL_DAC_Init() (+) If available & needed, configure DAC_OUTx (DAC_OUT1, DAC_OUT2) in analog mode. (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. *** Calibration mode IO operation *** ====================================== [..] (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset() (+) Run the calibration using HAL_DACEx_SelfCalibrate() (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming() *** Polling mode IO operation *** ================================= [..] (+) Start the DAC peripheral using HAL_DAC_Start() (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. (+) Stop the DAC peripheral using HAL_DAC_Stop() *** DMA mode IO operation *** ============================== [..] (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length of data to be transferred at each end of conversion First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() *** Callback registration *** ============================================= [..] The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. (+) MspInitCallback : DAC MspInit. (+) MspDeInitCallback : DAC MspdeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default weak (overridden) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. (+) MspInitCallback : DAC MspInit. (+) MspDeInitCallback : DAC MspdeInit. (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET all callbacks are reset to the corresponding legacy weak (overridden) functions. Exception done for MspInit and MspDeInit callbacks that are respectively reset to the legacy weak (overridden) functions in the HAL_DAC_Init and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit or HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (overridden) callbacks are used. *** DAC HAL driver macros list *** ============================================= [..] Below the list of most used macros in DAC HAL driver. (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status [..] (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ #ifdef HAL_DAC_MODULE_ENABLED #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @defgroup DAC DAC * @brief DAC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup DAC_Private_Constants DAC Private Constants * @{ */ #define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */ #define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */ #define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions -------------------------------------------------------*/ /** @defgroup DAC_Exported_Functions DAC Exported Functions * @{ */ /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DAC. (+) De-initialize the DAC. @endverbatim * @{ */ /** * @brief Initialize the DAC peripheral according to the specified parameters * in the DAC_InitStruct and initialize the associated handle. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) { #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the DAC Callback settings */ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; if (hdac->MspInitCallback == NULL) { hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Deinitialize the DAC peripheral registers to their default reset values. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) if (hdac->MspDeInitCallback == NULL) { hdac->MspDeInitCallback = HAL_DAC_MspDeInit; } /* DeInit the low level hardware */ hdac->MspDeInitCallback(hdac); #else /* DeInit the low level hardware */ HAL_DAC_MspDeInit(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; /* Change DAC state */ hdac->State = HAL_DAC_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Initialize the DAC MSP. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file */ } /** * @brief DeInitialize the DAC MSP. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file */ } /** * @} */ /** @defgroup DAC_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @verbatim ============================================================================== ##### IO operation functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. @endverbatim * @{ */ /** * @brief Enables DAC and starts conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { __IO uint32_t wait_loop_index; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */ /* bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } if (Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Disables DAC and stop conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Enables DAC and starts conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; uint32_t tmpreg; __IO uint32_t wait_loop_index; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); /* Case of use of channel 1 */ switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R1; break; case DAC_ALIGN_12B_L: /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; } } else { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); /* Case of use of channel 2 */ switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R2; break; case DAC_ALIGN_12B_L: /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; } } if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Process Unlocked */ __HAL_UNLOCK(hdac); if (status == HAL_OK) { /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } else { hdac->ErrorCode |= HAL_DAC_ERROR_DMA; } /* Return function status */ return status; } /** * @brief Disables DAC and stop conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Disable the selected DAC channel DMA request */ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); /* Disable the DMA channel */ /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { /* Disable the DMA channel */ (void)HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } else /* Channel2 is used for */ { /* Disable the DMA channel */ (void)HAL_DMA_Abort(hdac->DMA_Handle2); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Handles DAC interrupt request * This function uses the interruption of DMA * underrun. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { uint32_t itsource = hdac->Instance->CR; uint32_t itflag = hdac->Instance->SR; if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } /** * @brief Set the specified data holding register value for DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { __IO uint32_t tmp = 0UL; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */ if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL) { assert_param(IS_DAC_DATA(Data)); } tmp = (uint32_t)hdac->Instance; if (Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; /* Return function status */ return HAL_OK; } /** * @brief Conversion complete callback in non-blocking mode for Channel1 * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file */ } /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file */ } /** * @brief Error DAC callback for Channel1. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file */ } /** * @brief DMA underrun DAC callback for channel1. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } /** * @} */ /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure channels. (+) Set the specified data holding register value for DAC channel. @endverbatim * @{ */ /** * @brief Returns the last data output value of the selected DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval The selected DAC channel data output value. */ uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t result; /* Check the DAC peripheral handle */ assert_param(hdac != NULL); /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); if (Channel == DAC_CHANNEL_1) { result = hdac->Instance->DOR1; } else { result = hdac->Instance->DOR2; } /* Returns the DAC channel data output register value */ return result; } /** * @brief Configures the selected DAC channel. * @note By calling this function, the high frequency interface mode (HFSEL bits) * will be set. This parameter scope is the DAC instance. As the function * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig * must be the same at each call. * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect). * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig DAC configuration structure. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg1; uint32_t tmpreg2; uint32_t tickstart; uint32_t hclkfreq; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) { return HAL_ERROR; } /* Check the DAC parameters */ assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger)); assert_param(IS_DAC_TRIGGER2(hdac->Instance, sConfig->DAC_Trigger2)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) { assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); } assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) { assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) { /* Get timeout */ tickstart = HAL_GetTick(); if (Channel == DAC_CHANNEL_1) { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } else /* Channel 2 */ { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) { connectOnChip = 0x00000000UL; } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) { connectOnChip = DAC_MCR_MODE1_0; } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) { connectOnChip = DAC_MCR_MODE1_0; } else { connectOnChip = 0x00000000UL; } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); /* Clear DAC_MCR_DMADOUBLEx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: DMA double data mode */ tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; /* Clear DAC_MCR_SINFORMATx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: Signed format */ tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; /* Clear DAC_MCR_HFSEL bits */ tmpreg1 &= ~(DAC_MCR_HFSEL); /* Configure for both DAC channels: high frequency mode */ if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) { hclkfreq = HAL_RCC_GetHCLKFreq(); if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ) { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ; } else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ; } else { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE; } } else { tmpreg1 |= sConfig->DAC_HighFrequency; } /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */ tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; /* Modify STMODR register value depending on DAC_Channel */ MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return status; } /** * @} */ /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * @verbatim ============================================================================== ##### Peripheral State and Errors functions ##### ============================================================================== [..] This subsection provides functions allowing to (+) Check the DAC state. (+) Check the DAC Errors. @endverbatim * @{ */ /** * @brief return the DAC handle state * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; } /** * @brief Return the DAC error code * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup DAC_Exported_Functions * @{ */ /** @addtogroup DAC_Exported_Functions_Group1 * @{ */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback * To be used instead of the weak (overridden) predefined callback * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } if (pCallback == NULL) { /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; return HAL_ERROR; } if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) { case HAL_DAC_CH1_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh1 = pCallback; break; case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh1 = pCallback; break; case HAL_DAC_CH1_ERROR_ID : hdac->ErrorCallbackCh1 = pCallback; break; case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = pCallback; break; case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = pCallback; break; case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh2 = pCallback; break; case HAL_DAC_CH2_ERROR_ID : hdac->ErrorCallbackCh2 = pCallback; break; case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = pCallback; break; case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else if (hdac->State == HAL_DAC_STATE_RESET) { switch (CallbackID) { case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; } return status; } /** * @brief Unregister a User DAC Callback * DAC Callback is redirected to the weak (overridden) predefined callback * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks * @retval status */ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) { case HAL_DAC_CH1_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; break; case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; break; case HAL_DAC_CH1_ERROR_ID : hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; break; case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; break; case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; break; case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; break; case HAL_DAC_CH2_ERROR_ID : hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; break; case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; break; case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; case HAL_DAC_ALL_CB_ID : hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; hdac->MspInitCallback = HAL_DAC_MspInit; hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else if (hdac->State == HAL_DAC_STATE_RESET) { switch (CallbackID) { case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; } return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /** * @} */ /** @addtogroup DAC_Private_Functions * @{ */ /** * @brief DMA conversion complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvCpltCallbackCh1(hdac); #else HAL_DAC_ConvCpltCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @brief DMA half transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Conversion complete callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvHalfCpltCallbackCh1(hdac); #else HAL_DAC_ConvHalfCpltCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ErrorCallbackCh1(hdac); #else HAL_DAC_ErrorCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ #endif /* HAL_DAC_MODULE_ENABLED */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac_ex.c * @author MCD Application Team * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. * * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] *** Dual mode IO operation *** ============================== [..] (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion for dual mode operation. If software trigger is selected, using HAL_DACEx_DualStart() will start the conversion of the value previously set by HAL_DACEx_DualSetValue(). (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion for dual mode operation. (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion for dual mode operation using DMA to feed DAC converters. First issued trigger will start the conversion of the value previously set by HAL_DACEx_DualSetValue(). The same callbacks that are used in single mode are called in dual mode to notify transfer completion (half complete or complete), errors or underrun. (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion for dual mode operation using DMA to feed DAC converters. (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : Use HAL_DACEx_DualGetValue() to get digital data to be converted and use HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. *** Signal generation operation *** =================================== [..] (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. (+) Use HAL_DACEx_SawtoothWaveGenerate() to generate sawtooth signal. (+) Use HAL_DACEx_SawtoothWaveDataReset() to reset sawtooth wave. (+) Use HAL_DACEx_SawtoothWaveDataStep() to step sawtooth wave. (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel. (+) HAL_DACEx_SetUserTrimming to set user trimming value. (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting after reset, user setting if HAL_DACEx_SetUserTrimming have been used at least one time after reset). @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ #ifdef HAL_DAC_MODULE_ENABLED #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @defgroup DACEx DACEx * @brief DAC Extended HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Delay for DAC minimum trimming time. */ /* Note: minimum time needed between two calibration steps */ /* The delay below is specified under conditions: */ /* - DAC channel output buffer enabled */ /* Literal set to maximum value (refer to device datasheet, */ /* electrical characteristics, parameter "tTRIM"). */ /* Unit: us */ #define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup DACEx_Exported_Functions DACEx Exported Functions * @{ */ /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions * @brief Extended IO operation functions * @verbatim ============================================================================== ##### Extended features functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. (+) Get result of dual mode conversion. @endverbatim * @{ */ /** * @brief Enables DAC and starts conversion of both channels. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { uint32_t tmp_swtrig = 0UL; __IO uint32_t wait_loop_index; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG1; } if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL))) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG2; } /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Disables DAC and stop conversion of both channels. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The DAC channel that will request data from DMA. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @param pData The destination peripheral Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; uint32_t tmpreg = 0UL; __IO uint32_t wait_loop_index; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Ensure Channel 2 exists for this particular DAC instance */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); assert_param(IS_DAC_ALIGN(Alignment)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); } else { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); } switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12RD; break; case DAC_ALIGN_12B_L: /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12LD; break; case DAC_ALIGN_8B_R: /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8RD; break; default: break; } /* Enable the DMA channel */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Process Unlocked */ __HAL_UNLOCK(hdac); if (status == HAL_OK) { /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } else { hdac->ErrorCode |= HAL_DAC_ERROR_DMA; } /* Return function status */ return status; } /** * @brief Disables DAC and stop conversion both channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The DAC channel that requests data from DMA. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { HAL_StatusTypeDef status; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Ensure Channel 2 exists for this particular DAC instance */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); /* Disable the selected DAC channel DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); /* Disable the DMA channel */ /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } else { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle2); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } /* Check if DMA Channel effectively disabled */ if (status != HAL_OK) { /* Update DAC state machine to error */ hdac->State = HAL_DAC_STATE_ERROR; } else { /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } /* Return function status */ return status; } /** * @brief Enable or disable the selected DAC channel wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the triangle wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Enable or disable the selected DAC channel wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the noise wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Enable or disable the selected DAC channel sawtooth wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Polarity polarity to be used for wave generation. * This parameter can be one of the following values: * @arg DAC_SAWTOOTH_POLARITY_DECREMENT * @arg DAC_SAWTOOTH_POLARITY_INCREMENT * @param ResetData Sawtooth wave reset value. * Range is from 0 to DAC full range 4095 (0xFFF) * @param StepData Sawtooth wave step value. * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa * Step value step is 1/16 = 0.0625 * Step value range is 0.0000 to 4095.9375 (0xFFF.F) * @note Sawtooth reset and step triggers are configured by calling @ref HAL_DAC_ConfigChannel * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData) { /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_SAWTOOTH_POLARITY(Polarity)); assert_param(IS_DAC_RESET_DATA(ResetData)); assert_param(IS_DAC_STEP_DATA(StepData)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Configure the sawtooth wave generation data parameters */ MODIFY_REG(hdac->Instance->STR1, DAC_STR1_STINCDATA1 | DAC_STR1_STDIR1 | DAC_STR1_STRSTDATA1, (StepData << DAC_STR1_STINCDATA1_Pos) | Polarity | (ResetData << DAC_STR1_STRSTDATA1_Pos)); } else { /* Configure the sawtooth wave generation data parameters */ MODIFY_REG(hdac->Instance->STR2, DAC_STR2_STINCDATA2 | DAC_STR2_STDIR2 | DAC_STR2_STRSTDATA2, (StepData << DAC_STR2_STINCDATA2_Pos) | Polarity | (ResetData << DAC_STR2_STRSTDATA2_Pos)); } /* Enable the sawtooth wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1) << (Channel & 0x10UL), (uint32_t)(DAC_CR_WAVE1_1 | DAC_CR_WAVE1_0) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Trig sawtooth wave reset * @note This function allows to reset sawtooth wave in case of SW trigger * has been configured for this usage. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0UL /* SW TRIGGER */) { /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } else { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } else { status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return status; } /** * @brief Trig sawtooth wave step * @note This function allows to generate step in sawtooth wave in case of * SW trigger has been configured for this usage. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0UL /* SW TRIGGER */) { /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB1); } else { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB2); } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } else { status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return status; } /** * @brief Set the specified data holding register value for dual DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) { uint32_t data; uint32_t tmp; /* Check the DAC peripheral handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { data = ((uint32_t)Data2 << 8U) | Data1; } else { data = ((uint32_t)Data2 << 16U) | Data1; } tmp = (uint32_t)hdac->Instance; tmp += DAC_DHR12RD_ALIGNMENT(Alignment); /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; /* Return function status */ return HAL_OK; } /** * @brief Conversion complete callback in non-blocking mode for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file */ } /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file */ } /** * @brief Error DAC callback for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file */ } /** * @brief DMA underrun DAC callback for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } /** * @brief Run the self calibration of one DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig DAC channel configuration structure. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming * @retval HAL status * @note Calibration runs about 7 ms. */ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t trimmingvalue; uint32_t delta; __IO uint32_t wait_loop_index; /* store/restore channel configuration structure purpose */ uint32_t oldmodeconfiguration; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Check the DAC handle allocation */ /* Check if DAC running */ if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } else if (hdac->State == HAL_DAC_STATE_BUSY) { status = HAL_ERROR; } else { /* Process locked */ __HAL_LOCK(hdac); /* Store configuration */ oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL))); /* Disable the selected DAC channel */ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); /* Wait for ready bit to be de-asserted */ HAL_Delay(1); /* Set mode in MCR for calibration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); /* Init trimming counter */ /* Medium value */ trimmingvalue = 16UL; delta = 8UL; while (delta != 0UL) { /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); /* Wait minimum time needed between two calibration steps (OTRIM) */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ /* 32 bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) { /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */ trimmingvalue -= delta; } else { /* DAC_SR_CAL_FLAGx is LOW try lower trimming */ trimmingvalue += delta; } delta >>= 1UL; } /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */ /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); /* Wait minimum time needed between two calibration steps (OTRIM) */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */ /* 32 bits register capacity and handle low frequency. */ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { /* Trimming is actually one value more */ trimmingvalue++; /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } /* Disable the selected DAC channel calibration */ /* i.e. clear DAC_CR_CENx bit */ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); sConfig->DAC_TrimmingValue = trimmingvalue; sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; /* Restore configuration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration); /* Process unlocked */ __HAL_UNLOCK(hdac); } return status; } /** * @brief Set the trimming mode and trimming value (user trimming mode applied). * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig DAC configuration structure updated with new DAC trimming value. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param NewTrimmingValue DAC new trimming value * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); /* Check the DAC handle and channel configuration struct allocation */ if ((hdac == NULL) || (sConfig == NULL)) { status = HAL_ERROR; } else { /* Process locked */ __HAL_LOCK(hdac); /* Set new trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL))); /* Update trimming mode */ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; sConfig->DAC_TrimmingValue = NewTrimmingValue; /* Process unlocked */ __HAL_UNLOCK(hdac); } return status; } /** * @brief Return the DAC trimming value. * @param hdac DAC handle * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Trimming value : range: 0->31 * */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Retrieve trimming */ return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); } /** * @} */ /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Set the specified data holding register value for DAC channel. @endverbatim * @{ */ /** * @brief Return the last data output value of the selected DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac) { uint32_t tmp = 0UL; tmp |= hdac->Instance->DOR1; tmp |= hdac->Instance->DOR2 << 16UL; /* Returns the DAC channel data output register value */ return tmp; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions * @brief Extended private functions * @{ */ /** * @brief DMA conversion complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvCpltCallbackCh2(hdac); #else HAL_DACEx_ConvCpltCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @brief DMA half transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Conversion complete callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvHalfCpltCallbackCh2(hdac); #else HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ErrorCallbackCh2(hdac); #else HAL_DACEx_ErrorCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ #endif /* HAL_DAC_MODULE_ENABLED */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma.c * @author MCD Application Team * @brief DMA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. (#) For a given Channel, program the required configuration through the following parameters: Channel request, Transfer Direction, Source and Destination data formats, Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX thanks to: (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. (#) Use HAL_DMA_Abort() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** ================================= [..] (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. *** Interrupt mode IO operation *** =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function to register callbacks with HAL_DMA_RegisterCallback(). *** DMA HAL driver macros list *** ============================================= [..] Below the list of macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup DMA DMA * @brief DMA HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup DMA_Exported_Functions DMA Exported Functions * @{ */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in reference manual. @endverbatim * @{ */ /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } else { hdma->DMAmuxRequestGen = 0U; hdma->DMAmuxRequestGenStatus = 0U; hdma->DMAmuxRequestGenStatusMask = 0U; } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; return HAL_OK; } /** * @brief DeInitialize the DMA peripheral. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if (NULL == hdma) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); /* Reset the DMAMUX channel that corresponds to the DMA channel */ hdma->DMAmuxChannel->CCR = 0; /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Reset Request generator parameters if any */ if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } hdma->DMAmuxRequestGen = 0U; hdma->DMAmuxRequestGenStatus = 0U; hdma->DMAmuxRequestGenStatusMask = 0U; /* Clean callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions * @brief Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete (+) Handle DMA interrupt request @endverbatim * @{ */ /** * @brief Start the DMA Transfer. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); status = HAL_BUSY; } return status; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; } if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; } return status; } /** * @brief Abort the DMA Transfer. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if(hdma->State != HAL_DMA_STATE_BUSY) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return status; } /** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } } return status; } /** * @brief Polling for transfer complete. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CompleteLevel Specifies the DMA level complete. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Polling mode not supported in circular mode */ if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC)) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } /* Get the level transfer complete flag */ if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Transfer Complete flag */ temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU); } else { /* Half Transfer Complete flag */ temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU); } /* Get tick */ tickstart = HAL_GetTick(); while (0U == (hdma->DmaBaseAddress->ISR & temp)) { if ((0U != (hdma->DmaBaseAddress->ISR & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } } } /*Check for DMAMUX Request generator (if used) overrun status */ if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) { /* Disable the request gen overrun interrupt */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; } } /* Check for DMAMUX Synchronization overrun */ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; } if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)); } /* Process unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @brief Handle DMA interrupt request. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT))) { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU)); /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_TC))) { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU)); /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } } /* Transfer Error Interrupt management **************************************/ else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_TE))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } else { /* Nothing To Do */ } return; } /** * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = pCallback; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = pCallback; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = pCallback; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = pCallback; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; break; case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state (+) Get error code @endverbatim * @{ */ /** * @brief Return the DMA hande state. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { /* Return DMA handle state */ return hdma->State; } /** * @brief Return the DMA error code. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup DMA_Private_Functions * @{ */ /** * @brief Sets the DMA Transfer parameter. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (hdma->DMAmuxRequestGen != 0U) { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } /** * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t dmamux_base_addr; uint32_t channel_number; DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; /* check if instance is not outside the DMA channel range */ if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) { /* DMA1 */ DMAMUX1_ChannelBase = DMAMUX1_Channel0; } else { /* DMA2 */ #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) DMAMUX1_ChannelBase = DMAMUX1_Channel8; #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) DMAMUX1_ChannelBase = DMAMUX1_Channel6; #else DMAMUX1_ChannelBase = DMAMUX1_Channel7; #endif /* STM32G4x1xx) */ } dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); } /** * @brief Updates the DMA handle with the DMAMUX request generator params * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); } /** * @} */ /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma_ex.c * @author MCD Application Team * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: * + Extended features functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The DMA Extension HAL driver can be used as follows: (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used to respectively enable/disable the request generator. (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) @endverbatim */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup DMAEx DMAEx * @brief DMA Extended HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private Constants ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions * @{ */ /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions * @brief Extended features functions * @verbatim =============================================================================== ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used to respectively enable/disable the request generator. @endverbatim * @{ */ /** * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); /*Check if the DMA state is ready */ if (hdma->State == HAL_DMA_STATE_READY) { /* Process Locked */ __HAL_LOCK(hdma); /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ MODIFY_REG(hdma->DMAmuxChannel->CCR, \ (~DMAMUX_CxCR_DMAREQ_ID), \ ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); /* Process UnLocked */ __HAL_UNLOCK(hdma); return HAL_OK; } else { /*DMA State not Ready*/ return HAL_ERROR; } } /** * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : * contains the request generator parameters. * * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) { /* Process Locked */ __HAL_LOCK(hdma); /* Set the request generator new parameters */ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ ((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(DMAMUX_RGxCR_GNBREQ) & 0x1FU)) | \ pRequestGeneratorConfig->Polarity; /* Process UnLocked */ __HAL_UNLOCK(hdma); return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) { /* Enable the request generator*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) { /* Disable the request generator*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Handles DMAMUX interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @retval None */ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) { /* Check for DMAMUX Synchronization overrun */ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) { /* Disable the synchro overrun interrupt */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } if (hdma->DMAmuxRequestGen != 0) { /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) { /* Disable the request gen overrun interrupt */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } } } /** * @} */ /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_exti.c * @author MCD Application Team * @brief EXTI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: * functionalities of the General Purpose Input/Output (EXTI) peripheral: * + Initialization and de-initialization functions * + IO operation functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### EXTI Peripheral features ##### ============================================================================== [..] (+) Each Exti line can be configured within this driver. (+) Exti line can be configured in 3 different modes (++) Interrupt (++) Event (++) Both of them (+) Configurable Exti lines can be configured with 3 different triggers (++) Rising (++) Falling (++) Both of them (+) When set in interrupt mode, configurable Exti lines have two different interrupt pending registers which allow to distinguish which transition occurs: (++) Rising edge pending interrupt (++) Falling (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can be selected through multiplexer. ##### How to use this driver ##### ============================================================================== [..] (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). (++) Choose the interrupt line number by setting "Line" member from EXTI_ConfigTypeDef structure. (++) Configure the interrupt and/or event mode using "Mode" member from EXTI_ConfigTypeDef structure. (++) For configurable lines, configure rising and/or falling trigger "Trigger" member from EXTI_ConfigTypeDef structure. (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" member from GPIO_InitTypeDef structure. (#) Get current Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). (++) Provide exiting handle as first parameter. (++) Provide which callback will be registered using one value from EXTI_CallbackIDTypeDef. (++) Provide callback function pointer. (#) Get interrupt pending bit using HAL_EXTI_GetPending(). (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup EXTI * @{ */ /** MISRA C:2012 deviation rule has been granted for following rule: * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out * of bounds [0,3] in following API : * HAL_EXTI_SetConfigLine * HAL_EXTI_GetConfigLine * HAL_EXTI_ClearConfigLine */ #ifdef HAL_EXTI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines ------------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ #define EXTI_MODE_OFFSET 0x08U /* 0x20: offset between MCU IMR/EMR registers */ #define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup EXTI_Exported_Functions * @{ */ /** @addtogroup EXTI_Exported_Functions_Group1 * @brief Configuration functions * @verbatim =============================================================================== ##### Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Set configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on EXTI configuration to be set. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_EXTI_LINE(pExtiConfig->Line)); assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); /* Assign line number to handle */ hexti->Line = pExtiConfig->Line; /* Compute line register offset */ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line position */ linepos = (pExtiConfig->Line & EXTI_PIN_MASK); /* Compute line mask */ maskline = (1uL << linepos); /* Configure triggers for configurable lines */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); /* Configure rising trigger */ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store rising trigger mode */ *regaddr = regval; /* Configure falling trigger */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store falling trigger mode */ *regaddr = regval; /* Configure gpio port selection in case of gpio exti line */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); SYSCFG->EXTICR[linepos >> 2u] = regval; } } /* Configure interrupt mode : read current mode */ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store interrupt mode */ *regaddr = regval; /* Configure event mode : read current mode */ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store event mode */ *regaddr = regval; return HAL_OK; } /** * @brief Get configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on structure to store Exti configuration. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* Store handle line number to configuration structure */ pExtiConfig->Line = hexti->Line; /* Compute line register offset and line mask */ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line position */ linepos = (pExtiConfig->Line & EXTI_PIN_MASK); /* Compute mask */ maskline = (1uL << linepos); /* 1] Get core mode : interrupt */ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Check if selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Mode = EXTI_MODE_INTERRUPT; } else { pExtiConfig->Mode = EXTI_MODE_NONE; } /* Get event mode */ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Check if selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Mode |= EXTI_MODE_EVENT; } /* Get default Trigger and GPIOSel configuration */ pExtiConfig->Trigger = EXTI_TRIGGER_NONE; pExtiConfig->GPIOSel = 0x00u; /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } /* Get falling configuration */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; } /* Get Gpio port selection for gpio lines */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; } } return HAL_OK; } /** * @brief Clear whole configuration of a dedicated Exti line. * @param hexti Exti handle. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* compute line register offset and line mask */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* compute line position */ linepos = (hexti->Line & EXTI_PIN_MASK); /* compute line mask */ maskline = (1uL << linepos); /* 1] Clear interrupt mode */ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* 2] Clear event mode */ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* 3] Clear triggers in case of configurable lines */ if ((hexti->Line & EXTI_CONFIG) != 0x00u) { regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* Get Gpio port selection for gpio lines */ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); SYSCFG->EXTICR[linepos >> 2u] = regval; } } return HAL_OK; } /** * @brief Register callback for a dedicated Exti line. * @param hexti Exti handle. * @param CallbackID User callback identifier. * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. * @param pPendingCbfn function pointer to be stored as callback. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_EXTI_CB(CallbackID)); switch (CallbackID) { /* set common callback */ case HAL_EXTI_COMMON_CB_ID: hexti->PendingCallback = pPendingCbfn; break; default: hexti->PendingCallback = NULL; status = HAL_ERROR; break; } return status; } /** * @brief Store line number as handle private field. * @param hexti Exti handle. * @param ExtiLine Exti line number. * This parameter can be from 0 to @ref EXTI_LINE_NB. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) { /* Check the parameters */ assert_param(IS_EXTI_LINE(ExtiLine)); /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } else { /* Store line number as handle private field */ hexti->Line = ExtiLine; return HAL_OK; } } /** * @} */ /** @addtogroup EXTI_Exported_Functions_Group2 * @brief EXTI IO functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Handle EXTI interrupt request. * @param hexti Exti handle. * @retval none. */ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; uint32_t maskline; uint32_t offset; /* Compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Get pending bit */ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & maskline); if (regval != 0x00u) { /* Clear pending bit */ *regaddr = maskline; /* Call pending callback */ if (hexti->PendingCallback != NULL) { hexti->PendingCallback(); } } } /** * @brief Get interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge unused * @retval 1 if interrupt is pending else 0. */ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); UNUSED(Edge); /* Compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line position */ linepos = (hexti->Line & EXTI_PIN_MASK); /* Compute line mask */ maskline = (1uL << linepos); /* Get pending bit */ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); /* return 1 if bit is set else 0 */ regval = ((*regaddr & maskline) >> linepos); return regval; } /** * @brief Clear interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge unused * @retval None. */ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; uint32_t offset; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); UNUSED(Edge); /* Compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Get pending register address */ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); /* Clear Pending bit */ *regaddr = maskline; } /** * @brief Generate a software interrupt for a dedicated line. * @param hexti Exti handle. * @retval None. */ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; uint32_t offset; /* Check parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); /* compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); *regaddr = maskline; } /** * @} */ /** * @} */ #endif /* HAL_EXTI_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash.c * @author MCD Application Team * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions * + Memory Control functions * + Peripheral Errors functions * @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. [..] The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines. [..] The FLASH main features are: (+) Flash memory read operations (+) Flash memory program/erase operations (+) Read / write protections (+) Option bytes programming (+) Prefetch on I-Code (+) 32 cache lines of 4*64 or 2*128 bits on I-Code (+) 8 cache lines of 4*64 or 2*128 bits on D-Code (+) Error code correction (ECC) : Data in flash are 72-bits word (8 bits added per double word) ##### How to use this driver ##### ============================================================================== [..] This driver provides functions and macros to configure and program the FLASH memory of all STM32G4xx devices. (#) Flash Memory IO Programming functions: (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Program functions: double word and fast program (full row programming) (++) There are two modes of programming : (+++) Polling mode using HAL_FLASH_Program() function (+++) Interrupt mode using HAL_FLASH_Program_IT() function (#) Interrupts and flags management functions: (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() (++) Callback functions are called when the flash operations are finished : HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise HAL_FLASH_OperationErrorCallback() (++) Get error flag status by calling HAL_GetError() (#) Option bytes management functions: (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and HAL_FLASH_OB_Lock() functions (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. In this case, a reset is generated [..] In addition to these functions, this driver includes a set of macros allowing to handle the following operations: (+) Set the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the Instruction cache and the Data cache (+) Reset the Instruction cache and the Data cache (+) Enable/Disable the Flash power-down during low-power run and sleep modes (+) Enable/Disable the Flash interrupts (+) Monitor the Flash flags status @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup FLASH FLASH * @brief FLASH HAL module driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ #define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables * @{ */ /** * @brief Variable used for Program/Erase sectors under interruption */ FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, .ErrorCode = HAL_FLASH_ERROR_NONE, .ProcedureOnGoing = FLASH_PROC_NONE, .Address = 0U, .Bank = FLASH_BANK_1, .Page = 0U, .NbPagesToErase = 0U, .CacheToReactivate = FLASH_CACHE_DISABLED}; /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions * @{ */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions * @brief Programming operation functions * @verbatim =============================================================================== ##### Programming operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the FLASH program operations. @endverbatim * @{ */ /** * @brief Program double word or fast program of a row at a specified address. * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program. * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * This parameter is the data for the double word program and the address where * are stored the data for the row fast program. * * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status; uint32_t prog_bit = 0; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Process Locked */ __HAL_LOCK(&pFlash); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the data cache if they are activated to avoid data misbehavior */ if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) { /* Program double-word (64-bit) at a specified address */ FLASH_Program_DoubleWord(Address, Data); prog_bit = FLASH_CR_PG; } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) { /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); /* If it is the last row, the bit will be cleared at the end of the operation */ if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) { prog_bit = FLASH_CR_FSTPG; } } else { /* Nothing to do */ } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG or FSTPG Bit */ if (prog_bit != 0U) { CLEAR_BIT(FLASH->CR, prog_bit); } /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches(); } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); /* return status */ return status; } /** * @brief Program double word or fast program of a row at a specified address with interrupt enabled. * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program. * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * This parameter is the data for the double word program and the address where * are stored the data for the row fast program. * * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Process Locked */ __HAL_LOCK(&pFlash); /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the data cache if they are activated to avoid data misbehavior */ if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } else { /* Set internal variables used by the IRQ handler */ if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; } pFlash.Address = Address; /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) { /* Program double-word (64-bit) at a specified address */ FLASH_Program_DoubleWord(Address, Data); } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) { /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); } else { /* Nothing to do */ } } return status; } /** * @brief Handle FLASH interrupt request. * @retval None */ void HAL_FLASH_IRQHandler(void) { uint32_t tmp_page; uint32_t error; FLASH_ProcedureTypeDef procedure; /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); #if defined (FLASH_OPTR_DBANK) CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); #endif /* Disable the FSTPG Bit only if it is the last row programmed */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) { CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG); } /* Check FLASH operation error flags */ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); if (error != 0U) { /* Save the error code */ pFlash.ErrorCode |= error; /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(error); /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches(); /* FLASH error interrupt user callback */ procedure = pFlash.ProcedureOnGoing; if (procedure == FLASH_PROC_PAGE_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Page); } else if (procedure == FLASH_PROC_MASS_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Bank); } else if ((procedure == FLASH_PROC_PROGRAM) || (procedure == FLASH_PROC_PROGRAM_LAST)) { HAL_FLASH_OperationErrorCallback(pFlash.Address); } else { /* Nothing to do */ } /*Stop the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) { /* Nb of pages to erased can be decreased */ pFlash.NbPagesToErase--; /* Check if there are still pages to erase*/ if (pFlash.NbPagesToErase != 0U) { /* Indicate user which page has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Page); /* Increment page number */ pFlash.Page++; tmp_page = pFlash.Page; FLASH_PageErase(tmp_page, pFlash.Bank); } else { /* No more pages to Erase */ /* Reset Address and stop Erase pages procedure */ pFlash.Page = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches(); /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Page); } } else { /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches(); procedure = pFlash.ProcedureOnGoing; if (procedure == FLASH_PROC_MASS_ERASE) { /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Bank); } else if ((procedure == FLASH_PROC_PROGRAM) || (procedure == FLASH_PROC_PROGRAM_LAST)) { /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Address); } else { /* Nothing to do */ } /*Clear the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { /* Disable End of Operation and Error interrupts */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } } /** * @brief FLASH end of operation interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure: * @arg Mass Erase: Bank number which has been requested to erase * @arg Page Erase: Page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * @arg Program: Address which was selected for data program * @retval None */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file */ } /** * @brief FLASH operation error interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure: * @arg Mass Erase: Bank number which has been requested to erase * @arg Page Erase: Page number which returned an error * @arg Program: Address which was selected for data program * @retval None */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions * @brief Management functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim * @{ */ /** * @brief Unlock the FLASH control register access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* verify Flash is unlocked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { status = HAL_ERROR; } } return status; } /** * @brief Lock the FLASH control register access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { HAL_StatusTypeDef status = HAL_ERROR; /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); /* verify Flash is locked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { status = HAL_OK; } return status; } /** * @brief Unlock the FLASH Option Bytes Registers access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); /* verify option bytes are unlocked */ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { status = HAL_ERROR; } } return status; } /** * @brief Lock the FLASH Option Bytes Registers access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { HAL_StatusTypeDef status = HAL_ERROR; /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); /* Verify option bytes are locked */ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { status = HAL_OK; } return status; } /** * @brief Launch the option byte loading. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { /* Set the bit to force the option byte reloading */ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); /* Wait for last operation to be completed */ return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral Errors functions * @verbatim =============================================================================== ##### Peripheral Errors functions ##### =============================================================================== [..] This subsection permits to get in run-time Errors of the FLASH peripheral. @endverbatim * @{ */ /** * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode. The returned value can be: * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag * @arg HAL_FLASH_ERROR_NONE: No error set * @arg HAL_FLASH_ERROR_OP: FLASH Operation error * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error * @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error */ uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout. * @retval HAL_Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); uint32_t error; while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { if ((HAL_GetTick() - tickstart) > Timeout) { return HAL_TIMEOUT; } } /* Check FLASH operation error flags */ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); if (error != 0u) { /* Save the error code */ pFlash.ErrorCode |= error; /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(error); return HAL_ERROR; } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } /* If there is an error flag set */ return HAL_OK; } /** * @brief Program double-word (64-bit) at a specified address. * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) { /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Set PG bit */ SET_BIT(FLASH->CR, FLASH_CR_PG); /* Program first word */ *(uint32_t *)Address = (uint32_t)Data; /* Barrier to ensure programming is performed in 2 steps, in right order (independently of compiler optimization behavior) */ __ISB(); /* Program second word */ *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); } /** * @brief Fast program a row double-word (64-bit) at a specified address. * @param Address specifies the address to be programmed. * @param DataAddress specifies the address where the data are stored. * @retval None */ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) { uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW); uint32_t *dest_addr = (uint32_t *)Address; uint32_t *src_addr = (uint32_t *)DataAddress; uint32_t primask_bit; /* Check the parameters */ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); /* Set FSTPG bit */ SET_BIT(FLASH->CR, FLASH_CR_FSTPG); /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ primask_bit = __get_PRIMASK(); __disable_irq(); /* Program the double words of the row */ do { *dest_addr = *src_addr; dest_addr++; src_addr++; row_index--; } while (row_index != 0U); /* Exit critical section: restore previous priority mask */ __set_PRIMASK(primask_bit); } /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ex.c * @author MCD Application Team * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extended peripheral: * + Extended programming operations functions * @verbatim ============================================================================== ##### Flash Extended features ##### ============================================================================== [..] Comparing to other previous devices, the FLASH interface for STM32G4xx devices contains the following additional features (+) Capacity up to 512 Kbytes with dual bank architecture supporting read-while-write capability (RWW) (+) Dual bank 64-bits memory organization with possibility of single bank 128-bits (+) Protected areas including WRP, PCROP and Securable memory ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the FLASH memory of all STM32G4xx devices. It includes (#) Flash Memory Erase functions: (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Erase function: Erase pages, or mass erase banks (++) There are two modes of erase : (+++) Polling Mode using HAL_FLASHEx_Erase() (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to: (++) Configure the write protection areas (WRP) (++) Set the Read protection Level (RDP) (++) Program the user Option Bytes (++) Configure the Proprietary Code ReadOut protection areas (PCROP) (++) Configure the Securable memory areas (++) Configure the Boot Lock (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to: (++) Get the configuration of write protection areas (WRP) (++) Get the level of read protection (RDP) (++) Get the value of the user Option Bytes (++) Get the configuration of Proprietary Code ReadOut Protection areas (PCROP) (++) Get the configuration of Securable memory areas (++) Get the status of Boot Lock (#) Activation of Securable memory area: Use HAL_FLASHEx_EnableSecMemProtection() (++) Deny the access to securable memory area (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or HAL_FLASHEx_DisableDebugger() @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup FLASHEx FLASHEx * @brief FLASH Extended HAL module driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ static void FLASH_MassErase(uint32_t Banks); static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr); static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); static uint32_t FLASH_OB_GetRDP(void); static uint32_t FLASH_OB_GetUser(void); static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr); static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecMemBank, uint32_t SecMemSize); static void FLASH_OB_GetSecMem(uint32_t SecMemBank, uint32_t *SecMemSize); static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig); static uint32_t FLASH_OB_GetBootLock(void); /** * @} */ /* Exported functions -------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions * @brief Extended IO operation functions * @verbatim =============================================================================== ##### Extended programming operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the Extended FLASH programming operations Operations. @endverbatim * @{ */ /** * @brief Perform a mass erase or erase the specified FLASH memory pages. * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * @param[out] PageError pointer to variable that contains the configuration * information on faulty page in case of error (0xFFFFFFFF means that all * the pages have been correctly erased). * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status; uint32_t page_index; /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Process Locked */ __HAL_LOCK(&pFlash); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /* Mass erase to be done */ FLASH_MassErase(pEraseInit->Banks); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); #if defined (FLASH_OPTR_DBANK) /* If the erase operation is completed, disable the MER1 and MER2 Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); #else /* If the erase operation is completed, disable the MER1 Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1)); #endif } else { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) { FLASH_PageErase(page_index, pEraseInit->Banks); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB)); if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty page */ *PageError = page_index; break; } } } /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches(); } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); pFlash.Bank = pEraseInit->Banks; if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /* Mass erase to be done */ pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE; FLASH_MassErase(pEraseInit->Banks); } else { /* Erase by page to be done */ pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE; pFlash.NbPagesToErase = pEraseInit->NbPages; pFlash.Page = pEraseInit->Page; /*Erase 1st page and wait for IT */ FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); } return status; } /** * @brief Program Option bytes. * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /* Process Locked */ __HAL_LOCK(&pFlash); pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Write protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) { /* Configure of Write protection on the selected area */ if (FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK) { status = HAL_ERROR; } } /* Read protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) { /* Configure the Read protection level */ if (FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) { status = HAL_ERROR; } } /* User Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) { /* Configure the user option bytes */ if (FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) { status = HAL_ERROR; } } /* PCROP Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) { if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) { /* Configure the Proprietary code readout protection */ if (FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK) { status = HAL_ERROR; } } } /* Securable memory Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0U) { /* Configure the securable memory area */ if (FLASH_OB_SecMemConfig(pOBInit->SecBank, pOBInit->SecSize) != HAL_OK) { status = HAL_ERROR; } } /* Boot Entry Point Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) { /* Configure the boot unique entry point option */ if (FLASH_OB_BootLockConfig(pOBInit->BootEntryPoint) != HAL_OK) { status = HAL_ERROR; } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Get the Option bytes configuration. * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the * configuration information. * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate * which area is requested for the WRP and PCROP, else no information will be returned. * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); #if defined (FLASH_OPTR_DBANK) if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) #else if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB)) #endif { pOBInit->OptionType |= OPTIONBYTE_WRP; /* Get write protection on the selected area */ FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); } /* Get Read protection level */ pOBInit->RDPLevel = FLASH_OB_GetRDP(); /* Get the user option bytes */ pOBInit->USERConfig = FLASH_OB_GetUser(); #if defined (FLASH_OPTR_DBANK) if ((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) #else if (pOBInit->PCROPConfig == FLASH_BANK_1) #endif { pOBInit->OptionType |= OPTIONBYTE_PCROP; /* Get the Proprietary code readout protection */ FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr)); } pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK; /* Get the boot entry point */ pOBInit->BootEntryPoint = FLASH_OB_GetBootLock(); /* Get the securable memory area configuration */ #if defined (FLASH_OPTR_DBANK) if ((pOBInit->SecBank == FLASH_BANK_1) || (pOBInit->SecBank == FLASH_BANK_2)) #else if (pOBInit->SecBank == FLASH_BANK_1) #endif { pOBInit->OptionType |= OPTIONBYTE_SEC; FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize)); } } /** * @brief Enable the FLASH Securable Memory protection. * @param Bank: Bank to be protected * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be protected * @arg FLASH_BANK_2: Bank2 to be protected (*) * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*) * @note (*) availability depends on devices * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank) { #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) { /* Check the parameters */ assert_param(IS_FLASH_BANK(Bank)); /* Enable the Securable Memory Protection Bit for the bank 1 if requested */ if ((Bank & FLASH_BANK_1) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1); } /* Enable the Securable Memory Protection Bit for the bank 2 if requested */ if ((Bank & FLASH_BANK_2) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT2); } } else { SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1); } #else /* Prevent unused argument(s) compilation warning */ UNUSED(Bank); SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1); #endif /* FLASH_OPTR_DBANK */ return HAL_OK; } /** * @brief Enable Debugger. * @note After calling this API, flash interface allow debugger intrusion. * @retval None */ void HAL_FLASHEx_EnableDebugger(void) { FLASH->ACR |= FLASH_ACR_DBG_SWEN; } /** * @brief Disable Debugger. * @note After calling this API, Debugger is disabled: it's no more possible to * break, see CPU register, etc... * @retval None */ void HAL_FLASHEx_DisableDebugger(void) { FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @addtogroup FLASHEx_Private_Functions * @{ */ /** * @brief Mass erase of FLASH memory. * @param Banks Banks to be erased. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased (*) * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*) * @note (*) availability depends on devices * @retval None */ static void FLASH_MassErase(uint32_t Banks) { #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) #endif { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Set the Mass Erase Bit for the bank 1 if requested */ if ((Banks & FLASH_BANK_1) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER1); } #if defined (FLASH_OPTR_DBANK) /* Set the Mass Erase Bit for the bank 2 if requested */ if ((Banks & FLASH_BANK_2) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER2); } #endif } #if defined (FLASH_OPTR_DBANK) else { SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); } #endif /* Proceed to erase all sectors */ SET_BIT(FLASH->CR, FLASH_CR_STRT); } /** * @brief Erase the specified FLASH memory page. * @param Page FLASH page to erase. * This parameter must be a value between 0 and (max number of pages in the bank - 1). * @param Banks Bank where the page will be erased. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Page in bank 1 to be erased * @arg FLASH_BANK_2: Page in bank 2 to be erased (*) * @note (*) availability depends on devices * @retval None */ void FLASH_PageErase(uint32_t Page, uint32_t Banks) { /* Check the parameters */ assert_param(IS_FLASH_PAGE(Page)); #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } else { assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); if ((Banks & FLASH_BANK_1) != 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } else { SET_BIT(FLASH->CR, FLASH_CR_BKER); } } #else /* Prevent unused argument(s) compilation warning */ UNUSED(Banks); #endif /* FLASH_OPTR_DBANK */ /* Proceed to erase the page */ MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos)); SET_BIT(FLASH->CR, FLASH_CR_PER); SET_BIT(FLASH->CR, FLASH_CR_STRT); } /** * @brief Flush the instruction and data caches. * @retval None */ void FLASH_FlushCaches(void) { FLASH_CacheTypeDef cache = pFlash.CacheToReactivate; /* Flush instruction cache */ if ((cache == FLASH_CACHE_ICACHE_ENABLED) || (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); /* Reset instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); /* Enable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); } /* Flush data cache */ if ((cache == FLASH_CACHE_DCACHE_ENABLED) || (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Reset data cache */ __HAL_FLASH_DATA_CACHE_RESET(); /* Enable data cache */ __HAL_FLASH_DATA_CACHE_ENABLE(); } /* Reset internal variable */ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } /** * @brief Configure the write protection area into Option Bytes. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase Flash memory if the CPU debug * features are connected (JTAG or single wire) or boot code is being * executed from RAM or System flash, even if WRP is not activated. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param WRPArea specifies the area to be configured. * This parameter can be one of the following values: * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*) * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*) * @note (*) availability depends on devices * @param WRPStartOffset specifies the start page of the write protected area. * This parameter can be page number between 0 and (max number of pages in the bank - 1). * @param WRDPEndOffset specifies the end page of the write protected area. * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1). * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_WRPAREA(WRPArea)); assert_param(IS_FLASH_PAGE(WRPStartOffset)); assert_param(IS_FLASH_PAGE(WRDPEndOffset)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Configure the write protected area */ if (WRPArea == OB_WRPAREA_BANK1_AREAA) { FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset); } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) { FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset); } #if defined (FLASH_OPTR_DBANK) else if (WRPArea == OB_WRPAREA_BANK2_AREAA) { FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset); } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) { FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset); } #endif else { /* Nothing to do */ } /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Set the read protection level into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible * to go back to level 1 or 0 !!! * @param RDPLevel specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Memory Read protection * @arg OB_RDP_LEVEL_2: Full chip protection * * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(RDPLevel)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Configure the RDP level in the option bytes register */ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Program the FLASH User Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param UserType The FLASH User Option Bytes to be modified. * This parameter can be a combination of @ref FLASH_OB_USER_Type. * @param UserConfig The selected User Option Bytes values: * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY , * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW, * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1, * @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST, * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, * @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER * @note (*) availability depends on devices * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) { uint32_t optr_reg_val = 0; uint32_t optr_reg_mask = 0; HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_USER_TYPE(UserType)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { #if defined(FLASH_OPTR_PB4_PUPEN) if ((UserType & OB_USER_PB4_PUPEN) != 0U) { /* PB4_PUPEN option byte should be modified */ assert_param(IS_OB_USER_PB4_PUPEN(UserConfig & FLASH_OPTR_PB4_PUPEN)); /* Set value and mask for PB4_PUPEN option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_PB4_PUPEN); optr_reg_mask |= FLASH_OPTR_PB4_PUPEN; } #endif /* FLASH_OPTR_PB4_PUPEN */ if ((UserType & OB_USER_BOR_LEV) != 0U) { /* BOR level option byte should be modified */ assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); /* Set value and mask for BOR level option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); optr_reg_mask |= FLASH_OPTR_BOR_LEV; } if ((UserType & OB_USER_nRST_STOP) != 0U) { /* nRST_STOP option byte should be modified */ assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); /* Set value and mask for nRST_STOP option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); optr_reg_mask |= FLASH_OPTR_nRST_STOP; } if ((UserType & OB_USER_nRST_STDBY) != 0U) { /* nRST_STDBY option byte should be modified */ assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); /* Set value and mask for nRST_STDBY option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); optr_reg_mask |= FLASH_OPTR_nRST_STDBY; } if ((UserType & OB_USER_nRST_SHDW) != 0U) { /* nRST_SHDW option byte should be modified */ assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); /* Set value and mask for nRST_SHDW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); optr_reg_mask |= FLASH_OPTR_nRST_SHDW; } if ((UserType & OB_USER_IWDG_SW) != 0U) { /* IWDG_SW option byte should be modified */ assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); /* Set value and mask for IWDG_SW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); optr_reg_mask |= FLASH_OPTR_IWDG_SW; } if ((UserType & OB_USER_IWDG_STOP) != 0U) { /* IWDG_STOP option byte should be modified */ assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); /* Set value and mask for IWDG_STOP option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); optr_reg_mask |= FLASH_OPTR_IWDG_STOP; } if ((UserType & OB_USER_IWDG_STDBY) != 0U) { /* IWDG_STDBY option byte should be modified */ assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); /* Set value and mask for IWDG_STDBY option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; } if ((UserType & OB_USER_WWDG_SW) != 0U) { /* WWDG_SW option byte should be modified */ assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); /* Set value and mask for WWDG_SW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); optr_reg_mask |= FLASH_OPTR_WWDG_SW; } #if defined (FLASH_OPTR_BFB2) if ((UserType & OB_USER_BFB2) != 0U) { /* BFB2 option byte should be modified */ assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); /* Set value and mask for BFB2 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2); optr_reg_mask |= FLASH_OPTR_BFB2; } #endif if ((UserType & OB_USER_nBOOT1) != 0U) { /* nBOOT1 option byte should be modified */ assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); /* Set value and mask for nBOOT1 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1); optr_reg_mask |= FLASH_OPTR_nBOOT1; } if ((UserType & OB_USER_SRAM_PE) != 0U) { /* SRAM_PE option byte should be modified */ assert_param(IS_OB_USER_SRAM_PARITY(UserConfig & FLASH_OPTR_SRAM_PE)); /* Set value and mask for SRAM_PE option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE); optr_reg_mask |= FLASH_OPTR_SRAM_PE; } if ((UserType & OB_USER_CCMSRAM_RST) != 0U) { /* CCMSRAM_RST option byte should be modified */ assert_param(IS_OB_USER_CCMSRAM_RST(UserConfig & FLASH_OPTR_CCMSRAM_RST)); /* Set value and mask for CCMSRAM_RST option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST); optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST; } if ((UserType & OB_USER_nSWBOOT0) != 0U) { /* nSWBOOT0 option byte should be modified */ assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); /* Set value and mask for nSWBOOT0 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); optr_reg_mask |= FLASH_OPTR_nSWBOOT0; } if ((UserType & OB_USER_nBOOT0) != 0U) { /* nBOOT0 option byte should be modified */ assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); /* Set value and mask for nBOOT0 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); optr_reg_mask |= FLASH_OPTR_nBOOT0; } if ((UserType & OB_USER_NRST_MODE) != 0U) { /* Reset Configuration option byte should be modified */ assert_param(IS_OB_USER_NRST_MODE(UserConfig & FLASH_OPTR_NRST_MODE)); /* Set value and mask for Reset Configuration option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_NRST_MODE); optr_reg_mask |= FLASH_OPTR_NRST_MODE; } if ((UserType & OB_USER_IRHEN) != 0U) { /* IRH option byte should be modified */ assert_param(IS_OB_USER_IRHEN(UserConfig & FLASH_OPTR_IRHEN)); /* Set value and mask for IRH option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IRHEN); optr_reg_mask |= FLASH_OPTR_IRHEN; } /* Configure the option bytes register */ MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Configure the Proprietary code readout protection area into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option). * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 (*) * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE. * @note (*) availability depends on devices * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection. * This parameter can be an address between begin and end of the bank. * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection. * This parameter can be an address between PCROPStartAddr and end of the bank. * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) { HAL_StatusTypeDef status; uint32_t reg_value; uint32_t bank1_addr; #if defined (FLASH_OPTR_DBANK) uint32_t bank2_addr; #endif /* Check the parameters */ assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH)); assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr)); assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { #if defined (FLASH_OPTR_DBANK) /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; } else { bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; bank2_addr = FLASH_BASE; } #else bank1_addr = FLASH_BASE; #endif #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { /* Configure the Proprietary code readout protection */ if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } else { /* Nothing to do */ } } else #endif { /* Configure the Proprietary code readout protection */ if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = ((PCROPStartAddr - bank1_addr) >> 3); MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); reg_value = ((PCROPEndAddr - bank1_addr) >> 3); MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } #if defined (FLASH_OPTR_DBANK) else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = ((PCROPStartAddr - bank2_addr) >> 3); MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); reg_value = ((PCROPEndAddr - bank2_addr) >> 3); MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } #endif else { /* Nothing to do */ } } MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Configure the Securable memory area into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param SecBank specifies bank of securable memory area to be configured. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Securable memory in Bank1 to be configured * @arg FLASH_BANK_2: Securable memory in Bank2 to be configured (*) * @note (*) availability depends on devices * @param SecSize specifies the number of pages of the Securable memory area, * starting from first page of the bank. * This parameter can be page number between 0 and (max number of pages in the bank - 1) * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecBank, uint32_t SecSize) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_FLASH_BANK_EXCLUSIVE(SecBank)); assert_param(IS_OB_SECMEM_SIZE(SecSize)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Configure the write protected area */ if (SecBank == FLASH_BANK_1) { MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1, SecSize); } #if defined (FLASH_OPTR_DBANK) else if (SecBank == FLASH_BANK_2) { MODIFY_REG(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2, SecSize); } else { /* Nothing to do */ } #endif /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Configure the Boot Lock into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param BootLockConfig specifies the boot lock configuration. * This parameter can be one of the following values: * @arg OB_BOOT_LOCK_ENABLE: Enable Boot Lock * @arg OB_BOOT_LOCK_DISABLE: Disable Boot Lock * * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_BOOT_LOCK(BootLockConfig)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_BOOT_LOCK, BootLockConfig); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Return the Securable memory area configuration into Option Bytes. * @param[in] SecBank specifies the bank where securable memory area is located. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Securable memory in Bank1 * @arg FLASH_BANK_2: Securable memory in Bank2 (*) * @note (*) availability depends on devices * @param[out] SecSize specifies the number of pages used in the securable memory area of the bank. * @retval None */ static void FLASH_OB_GetSecMem(uint32_t SecBank, uint32_t *SecSize) { /* Get the configuration of the securable memory area */ if (SecBank == FLASH_BANK_1) { *SecSize = READ_BIT(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1); } #if defined (FLASH_OPTR_DBANK) else if (SecBank == FLASH_BANK_2) { *SecSize = READ_BIT(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2); } else { /* Nothing to do */ } #endif } /** * @brief Return the Boot Lock configuration into Option Byte. * @retval BootLockConfig. * This return value can be one of the following values: * @arg OB_BOOT_LOCK_ENABLE: Boot lock enabled * @arg OB_BOOT_LOCK_DISABLE: Boot lock disabled */ static uint32_t FLASH_OB_GetBootLock(void) { return (READ_REG(FLASH->SEC1R) & FLASH_SEC1R_BOOT_LOCK); } /** * @brief Return the Write Protection configuration into Option Bytes. * @param[in] WRPArea specifies the area to be returned. * This parameter can be one of the following values: * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32G43x/STM32G44x devices) * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32G43x/STM32G44x devices) * @param[out] WRPStartOffset specifies the address where to copied the start page * of the write protected area. * @param[out] WRDPEndOffset specifies the address where to copied the end page of * the write protected area. * @retval None */ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset) { /* Get the configuration of the write protected area */ if (WRPArea == OB_WRPAREA_BANK1_AREAA) { *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos); } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) { *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos); } #if defined (FLASH_OPTR_DBANK) else if (WRPArea == OB_WRPAREA_BANK2_AREAA) { *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos); } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) { *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos); } #endif else { /* Nothing to do */ } } /** * @brief Return the FLASH Read Protection level into Option Bytes. * @retval RDP_Level * This return value can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory * @arg OB_RDP_LEVEL_2: Full chip protection */ static uint32_t FLASH_OB_GetRDP(void) { uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) { return (OB_RDP_LEVEL_1); } else { return rdp_level; } } /** * @brief Return the FLASH User Option Byte value. * @retval OB_user_config * This return value is a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW, * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_DBANK (*), * @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE, * @ref FLASH_OB_USER_CCMSRAM_RST, @ref OB_USER_nSWBOOT0,@ref FLASH_OB_USER_nBOOT0, * @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER * @note (*) availability depends on devices */ static uint32_t FLASH_OB_GetUser(void) { uint32_t user_config = READ_REG(FLASH->OPTR); CLEAR_BIT(user_config, FLASH_OPTR_RDP); return user_config; } /** * @brief Return the FLASH PCROP configuration into Option Bytes. * @param[in,out] PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option). * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE. * @param[out] PCROPStartAddr specifies the address where to copied the start address * of the Proprietary code readout protection. * @param[out] PCROPEndAddr specifies the address where to copied the end address of * the Proprietary code readout protection. * @retval None */ static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr) { uint32_t reg_value; uint32_t bank1_addr; #if defined (FLASH_OPTR_DBANK) uint32_t bank2_addr; /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; } else { bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; bank2_addr = FLASH_BASE; } #else bank1_addr = FLASH_BASE; #endif #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; } else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; } else { /* Nothing to do */ } } else #endif { if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); *PCROPStartAddr = (reg_value << 3) + bank1_addr; reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); *PCROPEndAddr = (reg_value << 3) + bank1_addr; } #if defined (FLASH_OPTR_DBANK) else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); *PCROPStartAddr = (reg_value << 3) + bank2_addr; reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); *PCROPEndAddr = (reg_value << 3) + bank2_addr; } #endif else { /* Nothing to do */ } } *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ramfunc.c * @author MCD Application Team * @brief FLASH RAMFUNC driver. * This file provides a Flash firmware functions which should be * executed from internal SRAM * + FLASH Power Down in Run mode * + FLASH DBANK User Option Byte * * @verbatim ============================================================================== ##### Flash RAM functions ##### ============================================================================== *** ARM Compiler *** -------------------- [..] RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the Options for Target' dialog. *** ICCARM Compiler *** ----------------------- [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". *** GNU Compiler *** -------------------- [..] RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC * @brief FLASH functions executed from RAM * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions -------------------------------------------------------*/ /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions * @{ */ /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions * @brief Data transfers functions * @verbatim =============================================================================== ##### ramfunc functions ##### =============================================================================== [..] This subsection provides a set of functions that should be executed from RAM. @endverbatim * @{ */ /** * @brief Enable the Power down in Run Mode * @note This function should be called and executed from SRAM memory. * @retval None */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void) { /* Enable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_ENABLE(); return HAL_OK; } /** * @brief Disable the Power down in Run Mode * @note This function should be called and executed from SRAM memory. * @retval None */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) { /* Disable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_DISABLE(); return HAL_OK; } #if defined (FLASH_OPTR_DBANK) /** * @brief Program the FLASH DBANK User Option Byte. * * @note To configure the user option bytes, the option lock bit OPTLOCK must * be cleared with the call of the HAL_FLASH_OB_Unlock() function. * @note To modify the DBANK option byte, no PCROP region should be defined. * To deactivate PCROP, user should perform RDP changing. * * @param DBankConfig The FLASH DBANK User Option Byte value. * This parameter can be one of the following values: * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data * * @retval HAL_Status */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) { uint32_t count, reg; HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check if the PCROP is disabled */ reg = FLASH->PCROP1SR; if (reg > FLASH->PCROP1ER) { reg = FLASH->PCROP2SR; if (reg > FLASH->PCROP2ER) { /* Disable Flash prefetch */ __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable Flash instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); /* Flush Flash instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); } if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable Flash data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); /* Flush Flash data cache */ __HAL_FLASH_DATA_CACHE_RESET(); } /* Disable WRP zone A of 1st bank if needed */ reg = FLASH->WRP1AR; if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <= ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos)) { MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); } /* Disable WRP zone B of 1st bank if needed */ reg = FLASH->WRP1BR; if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <= ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos)) { MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); } /* Disable WRP zone A of 2nd bank if needed */ reg = FLASH->WRP2AR; if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <= ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos)) { MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); } /* Disable WRP zone B of 2nd bank if needed */ reg = FLASH->WRP2BR; if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <= ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos)) { MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); } /* Modify the DBANK user option byte */ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U); do { if (count == 0U) { break; } count--; } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); /* If the option byte program operation is completed, disable the OPTSTRT Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Set the bit to force the option byte reloading */ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } #endif /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_gpio.c * @author MCD Application Team * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### ============================================================================== [..] (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: (++) Input mode (++) Analog mode (++) Output mode (++) Alternate function mode (++) External interrupt/event lines (+) During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. (+) The microcontroller IO pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an IO pin at a time. In this way, there can be no conflict between peripherals sharing the same IO pin. (+) All ports have external interrupt/event capability. To use external interrupt lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. (+) The external interrupt/event controller consists of up to 44 edge detectors (16 lines are connected to GPIO) for generating event/interrupt requests (each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also be masked independently. ##### How to use this driver ##### ============================================================================== [..] (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure. (++) In alternate mode is selection, the alternate function connected to the IO is configured through "Alternate" member from GPIO_InitTypeDef structure. (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. (++) In case of external interrupt/event selection the "Mode" member from GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general purpose PF0 and PF1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup GPIO * @{ */ /** MISRA C:2012 deviation rule has been granted for following rules: * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of * range of the shift operator in following API : * HAL_GPIO_Init * HAL_GPIO_DeInit */ #ifdef HAL_GPIO_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ #define GPIO_NUMBER (16U) /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions * @{ */ /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0x00U; uint32_t iocurrent; uint32_t temp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); temp |= (GPIO_Init->Speed << (position * 2U)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT0 << position) ; temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; temp &= ~(0xFU << ((position & 0x07U) * 4U)); temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); GPIOx->AFR[position >> 3U] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); GPIOx->MODER = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2U]; temp &= ~(0x0FUL << (4U * (position & 0x03U))); temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } EXTI->RTSR1 = temp; temp = EXTI->FTSR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } EXTI->FTSR1 = temp; temp = EXTI->EMR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } EXTI->EMR1 = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } EXTI->IMR1 = temp; } } position++; } } /** * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bit to be written. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { uint32_t position = 0x00U; uint32_t iocurrent; uint32_t tmp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0U) { /* Get current io position */ iocurrent = (GPIO_Pin) & (1UL << position); if (iocurrent != 0x00u) { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = SYSCFG->EXTICR[position >> 2U]; tmp &= (0x0FUL << (4U * (position & 0x03U))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); EXTI->EMR1 &= ~(iocurrent); /* Clear Rising Falling edge configuration */ EXTI->FTSR1 &= ~(iocurrent); EXTI->RTSR1 &= ~(iocurrent); tmp = 0x0FUL << (4U * (position & 0x03U)); SYSCFG->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)); /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); } position++; } } /** * @} */ /** @addtogroup GPIO_Exported_Functions_Group2 * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Read the specified input port pin. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bit to read. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) { bitstatus = GPIO_PIN_SET; } else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } /** * @brief Set or clear the selected data port bit. * * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bit to be written. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) { GPIOx->BSRR = (uint32_t)GPIO_Pin; } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } /** * @brief Toggle the specified GPIO pin. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the pin to be toggled. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { uint32_t odr; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** * @brief Lock GPIO Pins configuration registers. * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { __IO uint32_t tmp = GPIO_LCKR_LCKK; /* Check the parameters */ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Apply lock key write sequence */ tmp |= GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Read LCKK register. This read is mandatory to complete key lock sequence */ tmp = GPIOx->LCKR; /* read again in order to confirm lock is active */ if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) { return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } } /** * @brief EXTI line detection callback. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* Prevent unused argument(s) compilation warning */ UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_GPIO_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr.c * @author MCD Application Team * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization/de-initialization functions * + Peripheral Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup PWR PWR * @brief PWR HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup PWR_Private_Defines PWR Private Defines * @{ */ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ /** * @} */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] @endverbatim * @{ */ /** * @brief Deinitialize the HAL PWR peripheral registers to their default reset values. * @retval None */ void HAL_PWR_DeInit(void) { __HAL_RCC_PWR_FORCE_RESET(); __HAL_RCC_PWR_RELEASE_RESET(); } /** * @brief Enable access to the backup domain * (RTC registers, RTC backup data registers). * @note After reset, the backup domain is protected against * possible unwanted write accesses. * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. * In order to set or modify the RTC clock, the backup domain access must be * disabled. * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * back-up domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { SET_BIT(PWR->CR1, PWR_CR1_DBP); } /** * @brief Disable access to the backup domain * (RTC registers, RTC backup data registers). * @retval None */ void HAL_PWR_DisableBkUpAccess(void) { CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); } /** * @} */ /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] *** PVD configuration *** ========================= [..] (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register). (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through __HAL_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. *** WakeUp pin configuration *** ================================ [..] (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. The polarity of these pins can be set to configure event detection on high level (rising edge) or low level (falling edge). *** Low Power modes configuration *** ===================================== [..] The devices feature 8 low-power modes: (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on. (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on. (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on. (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. *** Low-power run mode *** ========================== [..] (+) Entry: (from main run mode) (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. (+) Exit: (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only then can the system clock frequency be increased above 2 MHz. *** Sleep mode / Low-power sleep mode *** ========================================= [..] (+) Entry: The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction (+) WFI Exit: (++) Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) or any wake-up event. (+) WFE Exit: (++) Any wake-up event such as an EXTI line configured in event mode. [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, the MCU is in Low-power Run mode. *** Stop 0, Stop 1 modes *** =============================== [..] (+) Entry: The Stop 0, Stop 1 modes are entered through the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (++) PWR_MAINREGULATOR_ON (++) PWR_LOWPOWERREGULATOR_ON (+) Exit (interrupt or event-triggered, specified when entering STOP mode): (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction (+) WFI Exit: (++) Any EXTI Line (Internal or External) configured in Interrupt mode. (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts when programmed in wakeup mode. (+) WFE Exit: (++) Any EXTI Line (Internal or External) configured in Event mode. [..] When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode depending on the LPR bit setting. *** Standby mode *** ==================== [..] The Standby mode offers two options: (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers and Standby circuitry. (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). SRAM and register contents are lost except for the RTC registers, RTC backup registers and Standby circuitry. (++) Entry: (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit. (++) Exit: (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. *** Shutdown mode *** ====================== [..] In Shutdown mode, voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. SRAM and registers contents are lost except for backup domain registers. (+) Entry: The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API. (+) Exit: (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin. [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event or a time-stamp event, without depending on an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to configure the RTC to detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. @endverbatim * @{ */ /** * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD * configuration information. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each * detection level. * @retval None */ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); /* Set PLS bits according to PVDLevel value */ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } return HAL_OK; } /** * @brief Enable the Power Voltage Detector (PVD). * @retval None */ void HAL_PWR_EnablePVD(void) { SET_BIT(PWR->CR2, PWR_CR2_PVDE); } /** * @brief Disable the Power Voltage Detector (PVD). * @retval None */ void HAL_PWR_DisablePVD(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); } /** * @brief Enable the WakeUp PINx functionality. * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. * This parameter can be one of the following legacy values which set the default polarity * i.e. detection on high level (rising edge): * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 * * or one of the following value where the user can explicitly specify the enabled pin and * the chosen polarity: * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) { assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); /* Specifies the Wake-Up pin polarity for the event detection (rising or falling edge) */ MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); /* Enable wake-up pin */ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); } /** * @brief Disable the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); } /** * @brief Enter Sleep or Low-power Sleep mode. * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode. * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must * be done before calling HAL_PWR_EnterSLEEPMode() API. * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction * @note When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Set Regulator parameter */ if (Regulator == PWR_MAINREGULATOR_ON) { /* If in low-power run mode at this point, exit it */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) { (void)HAL_PWREx_DisableLowPowerRunMode(); } /* Regulator now in main mode. */ } else { /* If in run mode, first move to low-power run mode. The system clock frequency must be below 2 MHz at this point. */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U) { HAL_PWREx_EnableLowPowerRunMode(); } } /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } } /** * @brief Enter Stop mode * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running * on devices where only "Stop mode" is mentioned with main or low power regulator ON. * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note All clocks in the VCORE domain are stopped; the PLL, * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode (Stop 1), an additional * startup delay is incurred when waking up. * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption * is higher although the startup time is reduced. * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction. * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); if(Regulator == PWR_LOWPOWERREGULATOR_ON) { HAL_PWREx_EnterSTOP1Mode(STOPEntry); } else { HAL_PWREx_EnterSTOP0Mode(STOPEntry); } } /** * @brief Enter Standby mode. * @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched * off. The voltage regulator is disabled, except when SRAM2 content is preserved * in which case the regulator is in low-power mode. * SRAM1 and register contents are lost except for registers in the Backup domain and * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API * to set RRS bit. * The BOR is available. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the * same. * These states are effective in Standby mode only if APC bit is set through * HAL_PWREx_EnablePullUpPullDownConfig() API. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) { /* Set Stand-by mode */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) { /* Set SLEEPONEXIT bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) { /* Clear SLEEPONEXIT bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Enable CORTEX M4 SEVONPEND bit. * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_EnableSEVOnPend(void) { /* Set SEVONPEND bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief Disable CORTEX M4 SEVONPEND bit. * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) { /* Clear SEVONPEND bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief PWR PVD interrupt callback * @retval None */ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function should not be modified; when the callback is needed, the HAL_PWR_PVDCallback can be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr_ex.c * @author MCD Application Team * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup PWREx PWREx * @brief PWR Extended HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) #define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */ #define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */ #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx) #define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */ #define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */ #endif /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask * @{ */ #define PVM_MODE_IT 0x00010000U /*!< Mask for interruption yielded by PVM threshold crossing */ #define PVM_MODE_EVT 0x00020000U /*!< Mask for event yielded by PVM threshold crossing */ #define PVM_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as PVM trigger */ #define PVM_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as PVM trigger */ /** * @} */ /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value * @{ */ #define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */ /** * @} */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Extended Peripheral Initialization and de-initialization functions ##### =============================================================================== [..] @endverbatim * @{ */ /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) */ uint32_t HAL_PWREx_GetVoltageRange(void) { if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) { return PWR_REGULATOR_VOLTAGE_SCALE2; } else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) { /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ return PWR_REGULATOR_VOLTAGE_SCALE1; } else { return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; } } /** * @brief Configure the main internal regulator output voltage. * @param VoltageScaling: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, * typical output voltage at 1.28 V, * system frequency up to 170 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, * typical output voltage at 1.2 V, * system frequency up to 150 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, * typical output voltage at 1.0 V, * system frequency up to 26 MHz. * @note When moving from Range 1 to Range 2, the system frequency must be decreased to * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 2 to Range 1, the system frequency can be increased to * a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to * a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API. * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; } } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); } } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; } } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; } /** * @brief Enable battery charging. * When VDD is present, charge the external battery on VBAT through an internal resistor. * @param ResistorSelection: specifies the resistor impedance. * This parameter can be one of the following values: * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor * @retval None */ void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) { assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); /* Specify resistor selection */ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); /* Enable battery charging */ SET_BIT(PWR->CR4, PWR_CR4_VBE); } /** * @brief Disable battery charging. * @retval None */ void HAL_PWREx_DisableBatteryCharging(void) { CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); } /** * @brief Enable Internal Wake-up Line. * @retval None */ void HAL_PWREx_EnableInternalWakeUpLine(void) { SET_BIT(PWR->CR3, PWR_CR3_EIWF); } /** * @brief Disable Internal Wake-up Line. * @retval None */ void HAL_PWREx_DisableInternalWakeUpLine(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); } /** * @brief Enable GPIO pull-up state in Standby and Shutdown modes. * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in * pull-up state in Standby and Shutdown modes. * @note This state is effective in Standby and Shutdown modes only if APC bit * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. * @note The configuration is lost when exiting the Shutdown mode due to the * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding * PDy bit of PWR_PDCRx register is cleared unless it is reserved. * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input * parameter at the same time are set. * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to set * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); break; case PWR_GPIO_B: SET_BIT(PWR->PUCRB, GPIONumber); CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); break; case PWR_GPIO_C: SET_BIT(PWR->PUCRC, GPIONumber); CLEAR_BIT(PWR->PDCRC, GPIONumber); break; case PWR_GPIO_D: SET_BIT(PWR->PUCRD, GPIONumber); CLEAR_BIT(PWR->PDCRD, GPIONumber); break; case PWR_GPIO_E: SET_BIT(PWR->PUCRE, GPIONumber); CLEAR_BIT(PWR->PDCRE, GPIONumber); break; case PWR_GPIO_F: SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O * in pull-up state in Standby and Shutdown modes. * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input * parameter at the same time are reset. * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to reset * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); break; case PWR_GPIO_B: CLEAR_BIT(PWR->PUCRB, GPIONumber); break; case PWR_GPIO_C: CLEAR_BIT(PWR->PUCRC, GPIONumber); break; case PWR_GPIO_D: CLEAR_BIT(PWR->PUCRD, GPIONumber); break; case PWR_GPIO_E: CLEAR_BIT(PWR->PUCRE, GPIONumber); break; case PWR_GPIO_F: CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Enable GPIO pull-down state in Standby and Shutdown modes. * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in * pull-down state in Standby and Shutdown modes. * @note This state is effective in Standby and Shutdown modes only if APC bit * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. * @note The configuration is lost when exiting the Shutdown mode due to the * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding * PUy bit of PWR_PUCRx register is cleared unless it is reserved. * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input * parameter at the same time are set. * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to set * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); break; case PWR_GPIO_B: SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); CLEAR_BIT(PWR->PUCRB, GPIONumber); break; case PWR_GPIO_C: SET_BIT(PWR->PDCRC, GPIONumber); CLEAR_BIT(PWR->PUCRC, GPIONumber); break; case PWR_GPIO_D: SET_BIT(PWR->PDCRD, GPIONumber); CLEAR_BIT(PWR->PUCRD, GPIONumber); break; case PWR_GPIO_E: SET_BIT(PWR->PDCRE, GPIONumber); CLEAR_BIT(PWR->PUCRE, GPIONumber); break; case PWR_GPIO_F: SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: SET_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Disable GPIO pull-down state in Standby and Shutdown modes. * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O * in pull-down state in Standby and Shutdown modes. * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input * parameter at the same time are reset. * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to reset * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); break; case PWR_GPIO_B: CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); break; case PWR_GPIO_C: CLEAR_BIT(PWR->PDCRC, GPIONumber); break; case PWR_GPIO_D: CLEAR_BIT(PWR->PDCRD, GPIONumber); break; case PWR_GPIO_E: CLEAR_BIT(PWR->PDCRE, GPIONumber); break; case PWR_GPIO_F: CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Enable pull-up and pull-down configuration. * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there * is no conflict when setting PUy or PDy bit. * @retval None */ void HAL_PWREx_EnablePullUpPullDownConfig(void) { SET_BIT(PWR->CR3, PWR_CR3_APC); } /** * @brief Disable pull-up and pull-down configuration. * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. * @retval None */ void HAL_PWREx_DisablePullUpPullDownConfig(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_APC); } /** * @brief Enable SRAM2 content retention in Standby mode. * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in * Standby mode and its content is kept. * @retval None */ void HAL_PWREx_EnableSRAM2ContentRetention(void) { SET_BIT(PWR->CR3, PWR_CR3_RRS); } /** * @brief Disable SRAM2 content retention in Standby mode. * @note When RRS bit is reset, SRAM2 is powered off in Standby mode * and its content is lost. * @retval None */ void HAL_PWREx_DisableSRAM2ContentRetention(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); } #if defined(PWR_CR2_PVME1) /** * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage. * @retval None */ void HAL_PWREx_EnablePVM1(void) { SET_BIT(PWR->CR2, PWR_PVM_1); } /** * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage. * @retval None */ void HAL_PWREx_DisablePVM1(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_1); } #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) /** * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage. * @retval None */ void HAL_PWREx_EnablePVM2(void) { SET_BIT(PWR->CR2, PWR_PVM_2); } /** * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage. * @retval None */ void HAL_PWREx_DisablePVM2(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_2); } #endif /* PWR_CR2_PVME2 */ /** * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V. * @retval None */ void HAL_PWREx_EnablePVM3(void) { SET_BIT(PWR->CR2, PWR_PVM_3); } /** * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V. * @retval None */ void HAL_PWREx_DisablePVM3(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_3); } /** * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V. * @retval None */ void HAL_PWREx_EnablePVM4(void) { SET_BIT(PWR->CR2, PWR_PVM_4); } /** * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V. * @retval None */ void HAL_PWREx_DisablePVM4(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_4); } /** * @brief Configure the Peripheral Voltage Monitoring (PVM). * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the * PVM configuration information. * @note The API configures a single PVM according to the information contained * in the input structure. To configure several PVMs, the API must be singly * called for each PVM used. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each * detection level and to each monitored supply. * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); /* Configure EXTI 35 to 38 interrupts if so required: scan through PVMType to detect which PVMx is set and configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { #if defined(PWR_CR2_PVME1) case PWR_PVM_1: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM1_EXTI_DISABLE_IT(); __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM1_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); } break; #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) case PWR_PVM_2: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM2_EXTI_DISABLE_IT(); __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM2_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); } break; #endif /* PWR_CR2_PVME2 */ case PWR_PVM_3: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM3_EXTI_DISABLE_IT(); __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM3_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); } break; case PWR_PVM_4: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM4_EXTI_DISABLE_IT(); __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM4_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); } break; default: status = HAL_ERROR; break; } return status; } /** * @brief Enter Low-power Run mode * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. * @retval None */ void HAL_PWREx_EnableLowPowerRunMode(void) { /* Set Regulator parameter */ SET_BIT(PWR->CR1, PWR_CR1_LPR); } /** * @brief Exit Low-power Run mode. * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode * returns HAL_TIMEOUT status). The system clock frequency can then be * increased above 2 MHz. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { uint32_t wait_loop_index; /* Clear LPR bit */ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); /* Wait until REGLPF is reset */ wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) { return HAL_TIMEOUT; } return HAL_OK; } /** * @brief Enter Stop 0 mode. * @note In Stop 0 mode, main and low voltage regulators are ON. * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. * @note All clocks in the VCORE domain are stopped; the PLL, the HSI * and the HSE oscillators are disabled. Some peripherals with the wakeup capability * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register * is set; the HSI oscillator is selected if STOPWUCK is cleared. * @note By keeping the internal regulator ON during Stop 0 mode, the consumption * is higher although the startup time is reduced. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction * @retval None */ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); /* Stop 0 mode with Main Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ if(STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Enter Stop 1 mode. * @note In Stop 1 mode, only low power voltage regulator is ON. * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. * @note All clocks in the VCORE domain are stopped; the PLL, the HSI * and the HSE oscillators are disabled. Some peripherals with the wakeup capability * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register * is set. * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction * @retval None */ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); /* Stop 1 mode with Low-Power Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ if(STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Enter Shutdown mode. * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched * off. The voltage regulator is disabled and Vcore domain is powered off. * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. * The BOR is not available. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * @retval None */ void HAL_PWREx_EnterSHUTDOWNMode(void) { /* Set Shutdown mode */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @brief This function handles the PWR PVD/PVMx interrupt request. * @note This API should be called under the PVD_PVM_IRQHandler(). * @retval None */ void HAL_PWREx_PVD_PVM_IRQHandler(void) { /* Check PWR exti flag */ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); /* Clear PVD exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } /* Next, successively check PVMx exti flags */ #if defined(PWR_CR2_PVME1) if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) { /* PWR PVM1 interrupt user callback */ HAL_PWREx_PVM1Callback(); /* Clear PVM1 exti pending bit */ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); } #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U) { /* PWR PVM2 interrupt user callback */ HAL_PWREx_PVM2Callback(); /* Clear PVM2 exti pending bit */ __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); } #endif /* PWR_CR2_PVME2 */ if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) { /* PWR PVM3 interrupt user callback */ HAL_PWREx_PVM3Callback(); /* Clear PVM3 exti pending bit */ __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); } if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U) { /* PWR PVM4 interrupt user callback */ HAL_PWREx_PVM4Callback(); /* Clear PVM4 exti pending bit */ __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); } } #if defined(PWR_CR2_PVME1) /** * @brief PWR PVM1 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM1Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM1Callback() API can be implemented in the user file */ } #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) /** * @brief PWR PVM2 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM2Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM2Callback() API can be implemented in the user file */ } #endif /* PWR_CR2_PVME2 */ /** * @brief PWR PVM3 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM3Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM3Callback() API can be implemented in the user file */ } /** * @brief PWR PVM4 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM4Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM4Callback() API can be implemented in the user file */ } #if defined(PWR_CR3_UCPD_STDBY) /** * @brief Enable UCPD configuration memorization in Standby. * @retval None */ void HAL_PWREx_EnableUCPDStandbyMode(void) { /* Memorize UCPD configuration when entering standby mode */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } /** * @brief Disable UCPD configuration memorization in Standby. * @note This function must be called on exiting the Standby mode and before any UCPD * configuration update. * @retval None */ void HAL_PWREx_DisableUCPDStandbyMode(void) { /* Write 0 immediately after Standby exit when using UCPD, and before writing any UCPD registers */ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } #endif /* PWR_CR3_UCPD_STDBY */ #if defined(PWR_CR3_UCPD_DBDIS) /** * @brief Enable the USB Type-C dead battery pull-down behavior * on UCPDx_CC1 and UCPDx_CC2 pins * @retval None */ void HAL_PWREx_EnableUCPDDeadBattery(void) { /* Write 0 to enable the USB Type-C dead battery pull-down behavior */ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } /** * @brief Disable the USB Type-C dead battery pull-down behavior * on UCPDx_CC1 and UCPDx_CC2 pins * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, * which may have a pull-down effect on CC1 and CC2 pins. * It is recommended to disable it in all cases, either to stop this pull-down * or to hand over control to the UCPD (which should therefore be * initialized before doing the disable). * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } #endif /* PWR_CR3_UCPD_DBDIS */ /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc.c * @author MCD Application Team * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== [..] After reset the device is running from High Speed Internal oscillator (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in analog mode, except the JTAG pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs, UCPD, I2S, I2C, LPTIM, ADC, QSPI) @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup RCC RCC * @brief RCC HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ #define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) #define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) #define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) #define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__))) #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCC_Private_Functions RCC Private Functions * @{ */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ */ /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal and external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC clock source. (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also optionally as RTC clock source. (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks: (++) The first output is used to generate the high speed system clock (up to 170 MHz). (++) The second output is used to generate the clock for the USB (48 MHz), the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S. (++) The third output is used to generate a clock for ADC (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs (HSE used directly or through PLL as System clock source), the System clock is automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE, main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin. [..] System, AHB and APB buses clocks configuration (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and main PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these buses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 2 to 31. You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz to work correctly, while the RNG peripheral requires a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL through PLLQ divider. You have to enable the peripheral clock and use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) IWDG clock which is always the LSI clock. (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170 MHz. The clock source frequency should be adapted depending on the device voltage range as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. @endverbatim Table 1. HCLK clock frequency for STM32G4xx devices +----------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |----------------------------------------------------------| | | voltage range 1 | voltage range 1 | voltage range 2 | | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | |-----------------|-------------------|-------------------|------------------| |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 13 | |-----------------|-------------------|-------------------|------------------| |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 26 | |-----------------|-------------------|-------------------|------------------| |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | - | |-----------------|-------------------|-------------------|------------------| |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | |-----------------|-------------------|-------------------|------------------| |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | +----------------------------------------------------------------------------+ * @{ */ /** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 OFF * - All interrupts disabled * - All interrupt and reset flags cleared * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Set HSION bit to the reset value */ SET_BIT(RCC->CR, RCC_CR_HSION); /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Set HSITRIM[6:0] bits to the reset value */ SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Reset CFGR register (HSI is selected as system clock source) */ RCC->CFGR = 0x00000001u; /* Wait till HSI is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ RCC->CR = RCC_CR_HSION; /* Then again to HSEBYP in case bypass was enabled */ RCC->CR = RCC_CR_HSION; /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is OFF */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* once PLL is OFF, reset PLLCFGR register to default value */ RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4; /* Disable all interrupts */ CLEAR_REG(RCC->CIER); /* Clear all interrupt flags */ WRITE_REG(RCC->CICR, 0xFFFFFFFFU); /* Clear all reset flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); return HAL_OK; } /** * @brief Initialize the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not * supported by this macro. User should request a transition to LSE Off * first and then LSE On or LSE Bypass. * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) { /* When HSI is used as system clock it will not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) { return HAL_ERROR; } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { FlagStatus pwrclkchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLM, RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Unselect PLL clock source and disable outputs to save power */ RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) { return HAL_ERROR; } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) { return HAL_ERROR; } } } } return HAL_OK; } /** * @brief Initialize the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. * @param FLatency FLASH Latency * This parameter can be one of the following values: * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used by default as system clock source after * startup from Reset, wake-up from STANDBY mode. After restart from Reset, * the HSI frequency is set to its default value 16 MHz. * * @note The HSI can be selected as system clock source after * from STOP modes or in case of failure of the HSE used directly or indirectly * as system clock (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source is ready. * * @note You can use HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * * @note Depending on the device voltage range, the software has to set correctly * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart; uint32_t pllfreq; uint32_t hpre = RCC_SYSCLK_DIV1; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* PLL is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { return HAL_ERROR; } /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ pllfreq = RCC_GetSysClockFreqFromPLLSource(); /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ if(pllfreq > 80000000U) { if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); hpre = RCC_SYSCLK_DIV2; } } } else { /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { return HAL_ERROR; } } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { return HAL_ERROR; } } /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ pllfreq = HAL_RCC_GetSysClockFreq(); /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ if(pllfreq > 80000000U) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); hpre = RCC_SYSCLK_DIV2; } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick*/ tickstart = HAL_GetTick(); while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } else { /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ if(hpre == RCC_SYSCLK_DIV2) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); while (__HAL_FLASH_GET_LATENCY() != FLatency) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); } /** * @} */ /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to: (+) Output clock to MCO pin. (+) Retrieve current clock frequencies. (+) Enable the Clock Security System. @endverbatim * @{ */ /** * @brief Select the clock source to output on MCO pin(PA8/PG10). * @note PA8/PG10 should be configured in alternate function mode. * @note The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin) * and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it * as an MCO pin. * The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value. * @param RCC_MCOx specifies the output direction for the clock source. * For STM32G4xx family this parameter can have only one value: * @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8). * @arg @ref RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 * @param RCC_MCODiv specifies the MCO prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 no division applied to MCO clock * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock * @retval None */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio_initstruct; uint32_t mcoindex; uint32_t mco_gpio_index; GPIO_TypeDef * mco_gpio_port; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); /* Common GPIO init parameters */ gpio_initstruct.Mode = GPIO_MODE_AF_PP; gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; gpio_initstruct.Pull = GPIO_NOPULL; /* Get MCOx selection */ mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK; /* Get MCOx GPIO Port */ mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); /* MCOx Clock Enable */ mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index )); /* Configure the MCOx pin in alternate function mode */ gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); if (mcoindex == RCC_MCO1_INDEX) { assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); } } /** * @brief Return the SYSCLK frequency. * * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), * HSI_VALUE(*) Value multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) { /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; } else { sysclockfreq = 0U; } return sysclockfreq; } /** * @brief Return the HCLK frequency. * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; } /** * @brief Return the PCLK1 frequency. * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); } /** * @brief Return the PCLK2 frequency. * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); } /** * @brief Configure the RCC_OscInitStruct according to the internal * RCC configuration registers. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ assert_param(RCC_OscInitStruct != (void *)NULL); /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; /* Get the HSE configuration -----------------------------------------------*/ if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } else { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } /* Get the HSI configuration -----------------------------------------------*/ if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } else { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; /* Get the LSE configuration -----------------------------------------------*/ if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } else { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } /* Get the LSI configuration -----------------------------------------------*/ if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } else { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } /* Get the HSI48 configuration ---------------------------------------------*/ if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) { RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; } else { RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; } /* Get the PLL configuration -----------------------------------------------*/ if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } else { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; } /** * @brief Configure the RCC_ClkInitStruct according to the internal * RCC configuration registers. * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Check the parameters */ assert_param(RCC_ClkInitStruct != (void *)NULL); assert_param(pFLatency != (void *)NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = __HAL_FLASH_GET_LATENCY(); } /** * @brief Enable the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @note The Clock Security System can only be cleared by reset. * @retval None */ void HAL_RCC_EnableCSS(void) { SET_BIT(RCC->CR, RCC_CR_CSSON) ; } /** * @brief Enable the LSE Clock Security System. * @note If a failure is detected on the external 32 kHz oscillator, * the LSE clock is no longer supplied to the RTC but no hardware action * is made to the registers. If enabled, an interrupt will be generated * and handle through @ref RCCEx_EXTI_LINE_LSECSS * @note The Clock Security System can only be cleared by reset or after a LSE failure detection. * @retval None */ void HAL_RCC_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; } /** * @brief Disable the LSE Clock Security System. * @note After LSE failure detection, the software must disable LSECSSON * @note The Clock Security System can only be cleared by reset otherwise. * @retval None */ void HAL_RCC_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; } /** * @brief Handle the RCC Clock Security System interrupt request. * @note This API should be called under the NMI_Handler(). * @retval None */ void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF interrupt flag */ if(__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } } /** * @brief RCC Clock Security System interrupt callback. * @retval none */ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_RCC_CSSCallback should be implemented in the user file */ } /** * @} */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup RCC_Private_Functions * @{ */ /** * @brief Compute SYSCLK frequency based on PLL SYSCLK source. * @retval SYSCLK frequency */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; return sysclockfreq; } /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc_ex.c * @author MCD Application Team * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extended peripheral: * + Extended Peripheral Control functions * + Extended Clock management functions * + Extended Clock Recovery System Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup RCCEx RCCEx * @brief RCC Extended HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define DIVIDER_P_UPDATE 0U #define DIVIDER_Q_UPDATE 1U #define DIVIDER_R_UPDATE 2U #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define LSCO_GPIO_PORT GPIOA #define LSCO_PIN GPIO_PIN_2 /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values. @endverbatim * @{ */ /** * @brief Initialize the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains a field PeriphClockSelection which can be a combination of the following values: * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN) * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5) * @arg @ref RCC_PERIPHCLK_QSPI QuadSPI peripheral clock (only for devices with QuadSPI) * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ HAL_StatusTypeDef status = HAL_OK; /* Final status */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) { FlagStatus pwrclkchanged = RESET; /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while((PWR->CR1 & PWR_CR1_DBP) == 0U) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { ret = HAL_TIMEOUT; break; } } if(ret == HAL_OK) { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { ret = HAL_TIMEOUT; break; } } } if(ret == HAL_OK) { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } else { /* set overall return value */ status = ret; } } else { /* set overall return value */ status = ret; } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); } /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); } #endif /* UART4 */ #if defined(UART5) /*-------------------------- UART5 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); } /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } #if defined(I2C4) /*-------------------------- I2C4 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); } } #if defined(ADC345_COMMON) /*-------------------------- ADC345 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) { /* Check the parameters */ assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection)); /* Configure the ADC345 interface clock source */ __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection); if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL) { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); } } #endif /* ADC345_COMMON */ #if defined(QUADSPI) /*-------------------------- QuadSPIx clock source configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) { /* Check the parameters */ assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection)); /* Configure the QuadSPI clock source */ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #endif /* QUADSPI */ return status; } /** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals * clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2, I2C3, I2C4, * LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ #if defined(STM32G474xx) || defined(STM32G484xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_I2C4 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G491xx) || defined(STM32G4A1xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G473xx) || defined(STM32G483xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_I2C4 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G471xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_I2C4 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G431xx) || defined(STM32G441xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_RTC; #elif defined(STM32GBK1CB) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_RTC; #endif /* STM32G431xx */ /* Get the USART1 clock source ---------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); /* Get the USART2 clock source ---------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); /* Get the USART3 clock source ---------------------------------------------*/ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); #if defined(UART4) /* Get the UART4 clock source ----------------------------------------------*/ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); #endif /* UART4 */ #if defined(UART5) /* Get the UART5 clock source ----------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); #endif /* UART5 */ /* Get the LPUART1 clock source --------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); /* Get the I2C1 clock source -----------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); /* Get the I2C2 clock source ----------------------------------------------*/ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); /* Get the I2C3 clock source -----------------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); #if defined(I2C4) /* Get the I2C4 clock source -----------------------------------------------*/ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); #endif /* I2C4 */ /* Get the LPTIM1 clock source ---------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); /* Get the SAI1 clock source -----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); /* Get the I2S clock source -----------------------------------------------*/ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); #if defined(FDCAN1) /* Get the FDCAN clock source -----------------------------------------------*/ PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); #endif /* FDCAN1 */ #if defined(USB) /* Get the USB clock source ------------------------------------------------*/ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); #endif /* USB */ /* Get the RNG clock source ------------------------------------------------*/ PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); /* Get the ADC12 clock source -----------------------------------------------*/ PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE(); #if defined(ADC345_COMMON) /* Get the ADC345 clock source ----------------------------------------------*/ PeriphClkInit->Adc345ClockSelection = __HAL_RCC_GET_ADC345_SOURCE(); #endif /* ADC345_COMMON */ #if defined(QUADSPI) /* Get the QuadSPIclock source --------------------------------------------*/ PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); #endif /* QUADSPI */ /* Get the RTC clock source ------------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); } /** * @brief Return the peripheral clock frequency for peripherals with clock source from PLL * @note Return 0 if peripheral clock identifier not managed by this API * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S SPI peripheral clock * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN) * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5) * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock (only for devices with QSPI) * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { uint32_t frequency = 0U; uint32_t srcclk; uint32_t pllvco, plln, pllp; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); if(PeriphClk == RCC_PERIPHCLK_RTC) { /* Get the current RTC source */ srcclk = __HAL_RCC_GET_RTC_SOURCE(); /* Check if LSE is ready and if RTC clock selection is LSE */ if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Check if LSI is ready and if RTC clock selection is LSI */ else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) { frequency = LSI_VALUE; } /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) { frequency = HSE_VALUE / 32U; } /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0 */ } } else { /* Other external peripheral clock source than RTC */ /* Compute PLL clock input */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { pllvco = HSI_VALUE; } else { pllvco = 0U; } } else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) { pllvco = HSE_VALUE; } else { pllvco = 0U; } } else /* No source */ { pllvco = 0U; } /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); switch(PeriphClk) { case RCC_PERIPHCLK_USART1: /* Get the current USART1 source */ srcclk = __HAL_RCC_GET_USART1_SOURCE(); if(srcclk == RCC_USART1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); } else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI) ) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for USART1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_USART2: /* Get the current USART2 source */ srcclk = __HAL_RCC_GET_USART2_SOURCE(); if(srcclk == RCC_USART2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for USART2 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_USART3: /* Get the current USART3 source */ srcclk = __HAL_RCC_GET_USART3_SOURCE(); if(srcclk == RCC_USART3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for USART3 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(UART4) case RCC_PERIPHCLK_UART4: /* Get the current UART4 source */ srcclk = __HAL_RCC_GET_UART4_SOURCE(); if(srcclk == RCC_UART4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for UART4 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* UART4 */ #if defined(UART5) case RCC_PERIPHCLK_UART5: /* Get the current UART5 source */ srcclk = __HAL_RCC_GET_UART5_SOURCE(); if(srcclk == RCC_UART5CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for UART5 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* UART5 */ case RCC_PERIPHCLK_LPUART1: /* Get the current LPUART1 source */ srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for LPUART1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2C1: /* Get the current I2C1 source */ srcclk = __HAL_RCC_GET_I2C1_SOURCE(); if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2C2: /* Get the current I2C2 source */ srcclk = __HAL_RCC_GET_I2C2_SOURCE(); if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C2 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2C3: /* Get the current I2C3 source */ srcclk = __HAL_RCC_GET_I2C3_SOURCE(); if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C3 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(I2C4) case RCC_PERIPHCLK_I2C4: /* Get the current I2C4 source */ srcclk = __HAL_RCC_GET_I2C4_SOURCE(); if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C4 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* I2C4 */ case RCC_PERIPHCLK_LPTIM1: /* Get the current LPTIM1 source */ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) { frequency = LSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for LPTIM1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_SAI1: /* Get the current SAI1 source */ srcclk = __HAL_RCC_GET_SAI1_SOURCE(); if(srcclk == RCC_SAI1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if(srcclk == RCC_SAI1CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } } else if(srcclk == RCC_SAI1CLKSOURCE_EXT) { /* External clock used.*/ frequency = EXTERNAL_CLOCK_VALUE; } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SAI1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for SAI1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2S: /* Get the current I2Sx source */ srcclk = __HAL_RCC_GET_I2S_SOURCE(); if(srcclk == RCC_I2SCLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if(srcclk == RCC_I2SCLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } } else if(srcclk == RCC_I2SCLKSOURCE_EXT) { /* External clock used.*/ frequency = EXTERNAL_CLOCK_VALUE; } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2SCLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2S */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(FDCAN1) case RCC_PERIPHCLK_FDCAN: /* Get the current FDCANx source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); if(srcclk == RCC_FDCANCLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_FDCANCLKSOURCE_HSE) { frequency = HSE_VALUE; } else if(srcclk == RCC_FDCANCLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } } /* Clock not enabled for FDCAN */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* FDCAN1 */ #if defined(USB) case RCC_PERIPHCLK_USB: /* Get the current USB source */ srcclk = __HAL_RCC_GET_USB_SOURCE(); if(srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */ { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else if((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) /* HSI48 ? */ { frequency = HSI48_VALUE; } else /* No clock source */ { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* USB */ case RCC_PERIPHCLK_RNG: /* Get the current RNG source */ srcclk = __HAL_RCC_GET_RNG_SOURCE(); if(srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */ { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else if( (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) /* HSI48 ? */ { frequency = HSI48_VALUE; } else /* No clock source */ { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_ADC12: /* Get the current ADC12 source */ srcclk = __HAL_RCC_GET_ADC12_SOURCE(); if(srcclk == RCC_ADC12CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) { /* f(PLLP) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) { pllp = 17U; } else { pllp = 7U; } } frequency = (pllvco * plln) / pllp; } } else if(srcclk == RCC_ADC12CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Clock not enabled for ADC12 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(ADC345_COMMON) case RCC_PERIPHCLK_ADC345: /* Get the current ADC345 source */ srcclk = __HAL_RCC_GET_ADC345_SOURCE(); if(srcclk == RCC_ADC345CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) { /* f(PLLP) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) { pllp = 17U; } else { pllp = 7U; } } frequency = (pllvco * plln) / pllp; } } else if(srcclk == RCC_ADC345CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Clock not enabled for ADC345 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* ADC345_COMMON */ #if defined(QUADSPI) case RCC_PERIPHCLK_QSPI: /* Get the current QSPI source */ srcclk = __HAL_RCC_GET_QSPI_SOURCE(); if(srcclk == RCC_QSPICLKSOURCE_PLL) /* PLL ? */ { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else if(srcclk == RCC_QSPICLKSOURCE_HSI) { frequency = HSI_VALUE; } else if(srcclk == RCC_QSPICLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else /* No clock source */ { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* QUADSPI */ default: break; } } return(frequency); } /** * @} */ /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions * @verbatim =============================================================================== ##### Extended clock management functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the activation or deactivation of LSE CSS, Low speed clock output and clock after wake-up from STOP mode. @endverbatim * @{ */ /** * @brief Enable the LSE Clock Security System. * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC * clock with HAL_RCCEx_PeriphCLKConfig(). * @retval None */ void HAL_RCCEx_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; } /** * @brief Disable the LSE Clock Security System. * @note LSE Clock Security System can only be disabled after a LSE failure detection. * @retval None */ void HAL_RCCEx_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; /* Disable LSE CSS IT if any */ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } /** * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19 * @retval None */ void HAL_RCCEx_EnableLSECSS_IT(void) { /* Enable LSE CSS */ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; /* Enable LSE CSS IT */ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); /* Enable IT on EXTI Line 19 */ __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); } /** * @brief Handle the RCC LSE Clock Security System interrupt request. * @retval None */ void HAL_RCCEx_LSECSS_IRQHandler(void) { /* Check RCC LSE CSSF flag */ if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) { /* RCC LSE Clock Security System interrupt user callback */ HAL_RCCEx_LSECSS_Callback(); /* Clear RCC LSE CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); } } /** * @brief RCCEx LSE Clock Security System interrupt callback. * @retval none */ __weak void HAL_RCCEx_LSECSS_Callback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file */ } /** * @brief Select the Low Speed clock source to output on LSCO pin (PA2). * @param LSCOSource specifies the Low Speed clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source * @retval None */ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) { GPIO_InitTypeDef GPIO_InitStruct; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); /* LSCO Pin Clock Enable */ __LSCO_CLK_ENABLE(); /* Configure the LSCO pin in analog mode */ GPIO_InitStruct.Pin = LSCO_PIN; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); /* Update LSCOSEL clock source in Backup Domain control register */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); if(backupchanged == SET) { HAL_PWR_DisableBkUpAccess(); } if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /** * @brief Disable the Low Speed clock output. * @retval None */ void HAL_RCCEx_DisableLSCO(void) { FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; /* Update LSCOEN bit in Backup Domain control register */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable access to the backup domain */ HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); /* Restore previous configuration */ if(backupchanged == SET) { /* Disable access to the backup domain */ HAL_PWR_DisableBkUpAccess(); } if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /** * @} */ #if defined(CRS) /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions * @verbatim =============================================================================== ##### Extended Clock Recovery System Control functions ##### =============================================================================== [..] For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: (#) In System clock config, HSI48 needs to be enabled (#) Enable CRS clock in IP MSP init which will use CRS functions (#) Call CRS functions as follows: (##) Prepare synchronization configuration necessary for HSI48 calibration (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate directly reload value with target and sychronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. (+++) Configures CRS registers with synchronization configuration (+++) Enables automatic calibration and frequency error counter feature Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. (##) A polling function is provided to wait for complete synchronization (+++) Call function HAL_RCCEx_CRSWaitSynchronization() (+++) According to CRS status, user can decide to adjust again the calibration or continue application if synchronization is OK (#) User can retrieve information related to synchronization in calling function HAL_RCCEx_CRSGetSynchronizationInfo() (#) Regarding synchronization status and synchronization information, user can try a new calibration in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), it means that the actual frequency is lower than the target (and so, that the TRIM value should be incremented), while when it is detected during the upcounting phase it means that the actual frequency is higher (and that the TRIM value should be decremented). (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler (CRS_IRQn/CRS_IRQHandler) (++) Call function HAL_RCCEx_CRSConfig() (++) Enable CRS_IRQn (thanks to NVIC functions) (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) (++) Implement CRS status management in the following user callbacks called from HAL_RCCEx_CRS_IRQHandler(): (+++) HAL_RCCEx_CRS_SyncOkCallback() (+++) HAL_RCCEx_CRS_SyncWarnCallback() (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() (+++) HAL_RCCEx_CRS_ErrorCallback() (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) @endverbatim * @{ */ /** * @brief Start automatic synchronization for polling mode * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { uint32_t value; /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); /* CONFIGURATION */ /* Before configuration, reset CRS registers to their default values*/ __HAL_RCC_CRS_FORCE_RESET(); __HAL_RCC_CRS_RELEASE_RESET(); /* Set the SYNCDIV[2:0] bits according to Prescaler value */ /* Set the SYNCSRC[1:0] bits according to Source value */ /* Set the SYNCSPOL bit according to Polarity value */ value = (pInit->Prescaler | pInit->Source | pInit->Polarity); /* Set the RELOAD[15:0] bits according to ReloadValue value */ value |= pInit->ReloadValue; /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); WRITE_REG(CRS->CFGR, value); /* Adjust HSI48 oscillator smooth trimming */ /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); /* START AUTOMATIC SYNCHRONIZATION*/ /* Enable Automatic trimming & Frequency error counter */ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); } /** * @brief Generate the software synchronization event * @retval None */ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) { SET_BIT(CRS->CR, CRS_CR_SWSYNC); } /** * @brief Return synchronization info * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure * @retval None */ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) { /* Check the parameter */ assert_param(pSynchroInfo != (void *)NULL); /* Get the reload value */ pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); /* Get HSI48 oscillator smooth trimming */ pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); /* Get Frequency error capture */ pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); /* Get Frequency error direction */ pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); } /** * @brief Wait for CRS Synchronization status. * @param Timeout Duration of the timeout * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization * frequency. * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. * @retval Combination of Synchronization status * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_TIMEOUT * @arg @ref RCC_CRS_SYNCOK * @arg @ref RCC_CRS_SYNCWARN * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS * @arg @ref RCC_CRS_TRIMOVF */ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; uint32_t tickstart; /* Get timeout */ tickstart = HAL_GetTick(); /* Wait for CRS flag or timeout detection */ do { if(Timeout != HAL_MAX_DELAY) { if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { crsstatus = RCC_CRS_TIMEOUT; } } /* Check CRS SYNCOK flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) { /* CRS SYNC event OK */ crsstatus |= RCC_CRS_SYNCOK; /* Clear CRS SYNC event OK bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); } /* Check CRS SYNCWARN flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ crsstatus |= RCC_CRS_SYNCWARN; /* Clear CRS SYNCWARN bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); } /* Check CRS TRIM overflow flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_TRIMOVF; /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); } /* Check CRS Error flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_SYNCERR; /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); } /* Check CRS SYNC Missed flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) { /* CRS SYNC Missed */ crsstatus |= RCC_CRS_SYNCMISS; /* Clear CRS SYNC Missed bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); } /* Check CRS Expected SYNC flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) { /* frequency error counter reached a zero value */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); } } while(RCC_CRS_NONE == crsstatus); return crsstatus; } /** * @brief Handle the Clock Recovery System interrupt request. * @retval None */ void HAL_RCCEx_CRS_IRQHandler(void) { uint32_t crserror = RCC_CRS_NONE; /* Get current IT flags and IT sources values */ uint32_t itflags = READ_REG(CRS->ISR); uint32_t itsources = READ_REG(CRS->CR); /* Check CRS SYNCOK flag */ if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) { /* Clear CRS SYNC event OK flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); /* user callback */ HAL_RCCEx_CRS_SyncOkCallback(); } /* Check CRS SYNCWARN flag */ else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) { /* Clear CRS SYNCWARN flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); /* user callback */ HAL_RCCEx_CRS_SyncWarnCallback(); } /* Check CRS Expected SYNC flag */ else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) { /* frequency error counter reached a zero value */ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); /* user callback */ HAL_RCCEx_CRS_ExpectedSyncCallback(); } /* Check CRS Error flags */ else { if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) { if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) { crserror |= RCC_CRS_SYNCERR; } if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) { crserror |= RCC_CRS_SYNCMISS; } if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) { crserror |= RCC_CRS_TRIMOVF; } /* Clear CRS Error flags */ WRITE_REG(CRS->ICR, CRS_ICR_ERRC); /* user error callback */ HAL_RCCEx_CRS_ErrorCallback(crserror); } } } /** * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. * @retval none */ __weak void HAL_RCCEx_CRS_SyncOkCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file */ } /** * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. * @retval none */ __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file */ } /** * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. * @retval none */ __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file */ } /** * @brief RCCEx Clock Recovery System Error interrupt callback. * @param Error Combination of Error status. * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS * @arg @ref RCC_CRS_TRIMOVF * @retval none */ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) { /* Prevent unused argument(s) compilation warning */ UNUSED(Error); /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file */ } /** * @} */ #endif /* CRS */ /** * @} */ /** @addtogroup RCCEx_Private_Functions * @{ */ /** * @} */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + TIM Time Base Initialization * + TIM Time Base Start * + TIM Time Base Start Interruption * + TIM Time Base Start DMA * + TIM Output Compare/PWM Initialization * + TIM Output Compare/PWM Channel Configuration * + TIM Output Compare/PWM Start * + TIM Output Compare/PWM Start Interruption * + TIM Output Compare/PWM Start DMA * + TIM Input Capture Initialization * + TIM Input Capture Channel Configuration * + TIM Input Capture Start * + TIM Input Capture Start Interruption * + TIM Input Capture Start DMA * + TIM One Pulse Initialization * + TIM One Pulse Channel Configuration * + TIM One Pulse Start * + TIM Encoder Interface Initialization * + TIM Encoder Interface Start * + TIM Encoder Interface Start Interruption * + TIM Encoder Interface Start DMA * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### TIMER Generic features ##### ============================================================================== [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. (#) Up to 4 independent channels for: (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Supports incremental encoder for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() (++) Output Compare : HAL_TIM_OC_MspInit() (++) PWM generation : HAL_TIM_PWM_MspInit() (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() (++) Encoder mode output : HAL_TIM_Encoder_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare: to use the Timer to generate an Output Compare signal. (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). (#) The DMA Burst is managed with the two following functions: HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() *** Callback registration *** ============================================= [..] The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] Use Function HAL_TIM_RegisterCallback() to register a callback. HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: (+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. (+) IC_MspInitCallback : TIM IC Msp Init Callback. (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. (+) OC_MspInitCallback : TIM OC Msp Init Callback. (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. (+) PeriodElapsedCallback : TIM Period Elapsed Callback. (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. (+) TriggerCallback : TIM Trigger Callback. (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. (+) IC_CaptureCallback : TIM Input Capture Callback. (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. (+) ErrorCallback : TIM Error Callback. (+) CommutationCallback : TIM Commutation Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. (+) BreakCallback : TIM Break Callback. (+) Break2Callback : TIM Break2 Callback. (+) EncoderIndexCallback : TIM Encoder Index Callback. (+) DirectionChangeCallback : TIM Direction Change Callback (+) IndexErrorCallback : TIM Index Error Callback. (+) TransitionErrorCallback : TIM Transition Error Callback [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init / DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered beforehand) [..] Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Exception done MspInit / MspDeInit that can be registered / unregistered in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks using HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup TIM TIM * @brief TIM HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup TIM_Private_Constants * @{ */ #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions * @{ */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM base. (+) De-initialize the TIM base. (+) Start the Time Base. (+) Stop the Time Base. (+) Start the Time Base and enable interrupt. (+) Stop the Time Base and disable interrupt. (+) Start the Time Base and enable DMA transfer. (+) Stop the Time Base and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Base_MspInitCallback == NULL) { htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Base peripheral * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Base_MspDeInitCallback == NULL) { htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; } /* DeInit the low level hardware */ htim->Base_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in DMA mode. * @param htim TIM Base handle * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in DMA mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @verbatim ============================================================================== ##### TIM Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. (+) Start the TIM Output Compare. (+) Stop the TIM Output Compare. (+) Start the TIM Output Compare and enable interrupt. (+) Stop the TIM Output Compare and disable interrupt. (+) Start the TIM Output Compare and enable DMA transfer. (+) Stop the TIM Output Compare and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OC_MspInitCallback == NULL) { htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OC_MspDeInitCallback == NULL) { htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; } /* DeInit the low level hardware */ htim->OC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @verbatim ============================================================================== ##### TIM PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. (+) Start the TIM PWM. (+) Stop the TIM PWM. (+) Start the TIM PWM and enable interrupt. (+) Stop the TIM PWM and disable interrupt. (+) Start the TIM PWM and enable DMA transfer. (+) Stop the TIM PWM and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->PWM_MspInitCallback == NULL) { htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->PWM_MspDeInitCallback == NULL) { htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; } /* DeInit the low level hardware */ htim->PWM_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspDeInit could be implemented in the user file */ } /** * @brief Starts the PWM signal generation. * @param htim TIM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @verbatim ============================================================================== ##### TIM Input Capture functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. (+) Start the TIM Input Capture. (+) Stop the TIM Input Capture. (+) Start the TIM Input Capture and enable interrupt. (+) Stop the TIM Input Capture and disable interrupt. (+) Start the TIM Input Capture and enable DMA transfer. (+) Stop the TIM Input Capture and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->IC_MspInitCallback == NULL) { htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->IC_MspDeInitCallback == NULL) { htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; } /* DeInit the low level hardware */ htim->IC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Input Capture MSP. * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return status; } /** * @brief Stops the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @verbatim ============================================================================== ##### TIM One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. (+) Start the TIM One Pulse. (+) Stop the TIM One Pulse. (+) Start the TIM One Pulse and enable interrupt. (+) Stop the TIM One Pulse and disable interrupt. (+) Start the TIM One Pulse and enable DMA transfer. (+) Stop the TIM One Pulse and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() * @note When the timer instance is initialized in One Pulse mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OnePulse_MspInitCallback == NULL) { htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OnePulse_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM One Pulse * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OnePulse_MspDeInitCallback == NULL) { htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; } /* DeInit the low level hardware */ htim->OnePulse_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @verbatim ============================================================================== ##### TIM Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. (+) Start the TIM Encoder. (+) Stop the TIM Encoder. (+) Start the TIM Encoder and enable interrupt. (+) Stop the TIM Encoder and disable interrupt. (+) Start the TIM Encoder and enable DMA transfer. (+) Stop the TIM Encoder and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa * @note When the timer instance is initialized in Encoder mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Encoder_MspInitCallback == NULL) { htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Encoder interface * @param htim TIM Encoder Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Encoder_MspDeInitCallback == NULL) { htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; } /* DeInit the low level hardware */ htim->Encoder_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 and 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @param pData1 The destination Buffer address for IC1. * @param pData2 The destination Buffer address for IC2. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData1 == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData2 == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); break; } default: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); break; } } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 and 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief TIM IRQ handler management * @verbatim ============================================================================== ##### IRQ handler management ##### ============================================================================== [..] This section provides Timer IRQ handler function. @endverbatim * @{ */ /** * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { uint32_t itsource = htim->Instance->DIER; uint32_t itflag = htim->Instance->SR; /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Encoder index event */ if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) { if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else HAL_TIMEx_EncoderIndexCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Direction change event */ if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) { if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else HAL_TIMEx_DirectionChangeCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Index error event */ if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) { if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else HAL_TIMEx_IndexErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Transition error event */ if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) { if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else HAL_TIMEx_TransitionErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief TIM Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. (+) Configure External Clock source. (+) Configure Complementary channels, break features and dead time. (+) Configure Master and the Slave synchronization. (+) Configure the DMA Burst Mode. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM Output Compare handle * @param sConfig TIM Output Compare configuration structure * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the TIM Channel 5 in Output Compare */ TIM_OC5_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the TIM Channel 6 in Output Compare */ TIM_OC6_SetConfig(htim->Instance, sConfig); break; } default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. * @param htim TIM IC handle * @param sConfig TIM Input Capture configuration structure * @param Channel TIM Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; } else if (Channel == TIM_CHANNEL_2) { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } else if (Channel == TIM_CHANNEL_4) { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } else { status = HAL_ERROR; } __HAL_UNLOCK(htim); return status; } /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM PWM handle * @param sConfig TIM PWM configuration structure * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; htim->Instance->CCMR2 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; break; } case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; htim->Instance->CCMR3 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; break; } default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. * @param htim TIM One Pulse handle * @param sConfig TIM One Pulse configuration structure * @param OutputChannel TIM output channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @param InputChannel TIM input Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @note To output a waveform with a minimum delay user can enable the fast * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx * output is forced in response to the edge detection on TIx input, * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { HAL_StatusTypeDef status = HAL_OK; TIM_OC_InitTypeDef temp1; /* Check the parameters */ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Extract the Output compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; temp1.OCNPolarity = sConfig->OCNPolarity; temp1.OCIdleState = sConfig->OCIdleState; temp1.OCNIdleState = sConfig->OCNIdleState; switch (OutputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_OC1_SetConfig(htim->Instance, &temp1); break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_OC2_SetConfig(htim->Instance, &temp1); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { switch (InputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1FP1; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI2FP2; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } default: status = HAL_ERROR; break; } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return status; } else { return HAL_ERROR; } } /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status; status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); return status; } /** * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ return status; } /** * @brief Stops the TIM DMA Burst mode * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; } /* Return function status */ return status; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status; status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); return status; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ return status; } /** * @brief Stop the DMA burst reading * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; } /* Return function status */ return status; } /** * @brief Generate a software event * @param htim TIM handle * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source * @arg TIM_EVENTSOURCE_COM: Timer COM event source * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source * @note Basic timers can only generate an update event. * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant * only for timer instances supporting break input(s). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_EVENT_SOURCE(EventSource)); /* Process Locked */ __HAL_LOCK(htim); /* Change the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the event sources */ htim->Instance->EGR = EventSource; /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); /* Return function status */ return HAL_OK; } /** * @brief Configures the OCRef clear feature * @param htim TIM handle * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { /* Clear the OCREF clear selection bit and the the ETR Bits */ if (IS_TIM_OCCS_INSTANCE(htim->Instance)) { CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); /* Clear TIMx_AF2_OCRSEL (reset value) */ CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); } else { CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); } break; } case TIM_CLEARINPUTSOURCE_COMP1: case TIM_CLEARINPUTSOURCE_COMP2: case TIM_CLEARINPUTSOURCE_COMP3: case TIM_CLEARINPUTSOURCE_COMP4: #if defined (COMP5) case TIM_CLEARINPUTSOURCE_COMP5: #endif /* COMP5 */ #if defined (COMP6) case TIM_CLEARINPUTSOURCE_COMP6: #endif /* COMP6 */ #if defined (COMP7) case TIM_CLEARINPUTSOURCE_COMP7: #endif /* COMP7 */ { if (IS_TIM_OCCS_INSTANCE(htim->Instance)) { /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); } /* Set the clear input source */ MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); break; } case TIM_CLEARINPUTSOURCE_ETR: { /* Check the parameters */ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); if (IS_TIM_OCCS_INSTANCE(htim->Instance)) { /* Set the OCREF clear selection bit */ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); /* Clear TIMx_AF2_OCRSEL (reset value) */ CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); } break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { switch (Channel) { case TIM_CHANNEL_1: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 1 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } else { /* Disable the OCREF clear feature for Channel 1 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } break; } case TIM_CHANNEL_2: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 2 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } else { /* Disable the OCREF clear feature for Channel 2 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } break; } case TIM_CHANNEL_3: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 3 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } else { /* Disable the OCREF clear feature for Channel 3 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } break; } case TIM_CHANNEL_4: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 4 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } else { /* Disable the OCREF clear feature for Channel 4 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } break; } case TIM_CHANNEL_5: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 5 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } else { /* Disable the OCREF clear feature for Channel 5 */ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } break; } case TIM_CHANNEL_6: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 6 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } else { /* Disable the OCREF clear feature for Channel 6 */ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } break; } default: break; } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return status; } /** * @brief Configures the clock source to be used * @param htim TIM handle * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); htim->Instance->SMCR = tmpsmcr; switch (sClockSourceConfig->ClockSource) { case TIM_CLOCKSOURCE_INTERNAL: { assert_param(IS_TIM_INSTANCE(htim->Instance)); break; } case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; break; } case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; break; } case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); break; } case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); break; } case TIM_CLOCKSOURCE_TI1ED: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); break; } case TIM_CLOCKSOURCE_ITR0: case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: #if defined (TIM5) case TIM_CLOCKSOURCE_ITR4: #endif /* TIM5 */ case TIM_CLOCKSOURCE_ITR5: case TIM_CLOCKSOURCE_ITR6: case TIM_CLOCKSOURCE_ITR7: case TIM_CLOCKSOURCE_ITR8: #if defined (TIM20) case TIM_CLOCKSOURCE_ITR9: #endif /* TIM20 */ #if defined (HRTIM1) case TIM_CLOCKSOURCE_ITR10: #endif /* HRTIM1 */ case TIM_CLOCKSOURCE_ITR11: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); break; } default: status = HAL_ERROR; break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return status; } /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input * @param htim TIM handle. * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 * pins are connected to the TI1 input (XOR combination) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Reset the TI1 selection */ tmpcr2 &= ~TIM_CR2_TI1S; /* Set the TI1 selection */ tmpcr2 |= TI1_Selection; /* Write to TIMxCR2 */ htim->Instance->CR2 = tmpcr2; return HAL_OK; } /** * @brief Configures the TIM in Slave mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Enable Trigger Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Read the captured value from Capture Compare unit * @param htim TIM handle. * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; break; } default: break; } return tmpreg; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== [..] This section provides TIM callback functions: (+) TIM Period elapsed callback (+) TIM Output Compare callback (+) TIM Input capture callback (+) TIM Trigger callback (+) TIM Error callback (+) TIM Index callback (+) TIM Direction change callback (+) TIM Index error callback (+) TIM Transition error callback @endverbatim * @{ */ /** * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } /** * @brief Period elapsed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file */ } /** * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } /** * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } /** * @brief Input Capture half complete callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file */ } /** * @brief Timer error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Register a User TIM callback to be used instead of the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID * @param pCallback pointer to the callback function * @retval status */ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { return HAL_ERROR; } if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : htim->PeriodElapsedCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : htim->PeriodElapsedHalfCpltCallback = pCallback; break; case HAL_TIM_TRIGGER_CB_ID : htim->TriggerCallback = pCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : htim->TriggerHalfCpltCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : htim->IC_CaptureCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : htim->IC_CaptureHalfCpltCallback = pCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : htim->OC_DelayElapsedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : htim->PWM_PulseFinishedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : htim->PWM_PulseFinishedHalfCpltCallback = pCallback; break; case HAL_TIM_ERROR_CB_ID : htim->ErrorCallback = pCallback; break; case HAL_TIM_COMMUTATION_CB_ID : htim->CommutationCallback = pCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : htim->CommutationHalfCpltCallback = pCallback; break; case HAL_TIM_BREAK_CB_ID : htim->BreakCallback = pCallback; break; case HAL_TIM_BREAK2_CB_ID : htim->Break2Callback = pCallback; break; case HAL_TIM_ENCODER_INDEX_CB_ID : htim->EncoderIndexCallback = pCallback; break; case HAL_TIM_DIRECTION_CHANGE_CB_ID : htim->DirectionChangeCallback = pCallback; break; case HAL_TIM_INDEX_ERROR_CB_ID : htim->IndexErrorCallback = pCallback; break; case HAL_TIM_TRANSITION_ERROR_CB_ID : htim->TransitionErrorCallback = pCallback; break; default : /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = pCallback; break; default : /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } return status; } /** * @brief Unregister a TIM callback * TIM callback is redirected to the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : /* Legacy weak Base MspInit Callback */ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : /* Legacy weak Base Msp DeInit Callback */ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : /* Legacy weak IC Msp Init Callback */ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : /* Legacy weak IC Msp DeInit Callback */ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : /* Legacy weak OC Msp Init Callback */ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : /* Legacy weak OC Msp DeInit Callback */ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : /* Legacy weak PWM Msp Init Callback */ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : /* Legacy weak PWM Msp DeInit Callback */ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : /* Legacy weak One Pulse Msp Init Callback */ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : /* Legacy weak One Pulse Msp DeInit Callback */ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : /* Legacy weak Encoder Msp Init Callback */ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : /* Legacy weak Encoder Msp DeInit Callback */ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : /* Legacy weak Hall Sensor Msp Init Callback */ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : /* Legacy weak Hall Sensor Msp DeInit Callback */ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : /* Legacy weak Period Elapsed Callback */ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : /* Legacy weak Period Elapsed half complete Callback */ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : /* Legacy weak Trigger Callback */ htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : /* Legacy weak Trigger half complete Callback */ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : /* Legacy weak IC Capture Callback */ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : /* Legacy weak IC Capture half complete Callback */ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : /* Legacy weak OC Delay Elapsed Callback */ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : /* Legacy weak PWM Pulse Finished Callback */ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : /* Legacy weak PWM Pulse Finished half complete Callback */ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : /* Legacy weak Error Callback */ htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : /* Legacy weak Commutation Callback */ htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : /* Legacy weak Commutation half complete Callback */ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : /* Legacy weak Break Callback */ htim->BreakCallback = HAL_TIMEx_BreakCallback; break; case HAL_TIM_BREAK2_CB_ID : /* Legacy weak Break2 Callback */ htim->Break2Callback = HAL_TIMEx_Break2Callback; break; case HAL_TIM_ENCODER_INDEX_CB_ID : /* Legacy weak Encoder Index Callback */ htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; break; case HAL_TIM_DIRECTION_CHANGE_CB_ID : /* Legacy weak Direction Change Callback */ htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; break; case HAL_TIM_INDEX_ERROR_CB_ID : /* Legacy weak Index Error Callback */ htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; break; case HAL_TIM_TRANSITION_ERROR_CB_ID : /* Legacy weak Transition Error Callback */ htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; break; default : /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : /* Legacy weak Base MspInit Callback */ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : /* Legacy weak Base Msp DeInit Callback */ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : /* Legacy weak IC Msp Init Callback */ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : /* Legacy weak IC Msp DeInit Callback */ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : /* Legacy weak OC Msp Init Callback */ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : /* Legacy weak OC Msp DeInit Callback */ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : /* Legacy weak PWM Msp Init Callback */ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : /* Legacy weak PWM Msp DeInit Callback */ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : /* Legacy weak One Pulse Msp Init Callback */ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : /* Legacy weak One Pulse Msp DeInit Callback */ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : /* Legacy weak Encoder Msp Init Callback */ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : /* Legacy weak Encoder Msp DeInit Callback */ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : /* Legacy weak Hall Sensor Msp Init Callback */ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : /* Legacy weak Hall Sensor Msp DeInit Callback */ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief TIM Peripheral State functions * @verbatim ============================================================================== ##### Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Base handle state. * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM OC handle state. * @param htim TIM Output Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM PWM handle state. * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Input Capture handle state. * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM One Pulse Mode handle state. * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM Encoder Interface handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM handle * @retval Active channel */ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } /** * @brief Return actual state of the TIM channel. * @param htim TIM handle * @param Channel TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); return channel_state; } /** * @brief Return actual state of a DMA burst operation. * @param htim TIM handle * @retval DMA burst state */ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); return htim->DMABurstState; } /** * @} */ /** * @} */ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ /** * @brief TIM DMA error callback * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } else { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedHalfCpltCallback(htim); #else HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureHalfCpltCallback(htim); #else HAL_TIM_IC_CaptureHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Period Elapse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Period Elapse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else HAL_TIM_PeriodElapsedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else HAL_TIM_TriggerHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief Time Base configuration * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); } } /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; tmpcr2 &= ~TIM_CR2_OIS2N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC4NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 12U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC4NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; /* Reset the Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 6U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Slave Timer configuration function * @param htim TIM handle * @param sSlaveConfig Slave timer configuration * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Reset the Trigger Selection Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source */ tmpsmcr |= sSlaveConfig->InputTrigger; /* Reset the slave mode Bits */ tmpsmcr &= ~TIM_SMCR_SMS; /* Set the slave mode */ tmpsmcr |= sSlaveConfig->SlaveMode; /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { case TIM_TS_ETRF: { /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \ (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) { return HAL_ERROR; } /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = htim->Instance->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; htim->Instance->CCER = tmpccer; break; } case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_ITR0: case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: #if defined (TIM5) case TIM_TS_ITR4: #endif /* TIM5 */ case TIM_TS_ITR5: case TIM_TS_ITR6: case TIM_TS_ITR7: case TIM_TS_ITR8: #if defined (TIM20) case TIM_TS_ITR9: #endif /* TIM20 */ #if defined (HRTIM1) case TIM_TS_ITR10: #endif /* HRTIM1 */ case TIM_TS_ITR11: { /* Check the parameter */ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); break; } default: status = HAL_ERROR; break; } return status; } /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= TIM_ICPolarity; /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; tmpccmr2 |= TIM_ICSelection; /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer ; } /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @arg TIM_TS_ITR4: Internal Trigger 4 (*) * @arg TIM_TS_ITR5: Internal Trigger 5 * @arg TIM_TS_ITR6: Internal Trigger 6 * @arg TIM_TS_ITR7: Internal Trigger 7 * @arg TIM_TS_ITR8: Internal Trigger 8 * @arg TIM_TS_ITR9: Internal Trigger 9 (*) * @arg TIM_TS_ITR10: Internal Trigger 10 * @arg TIM_TS_ITR11: Internal Trigger 11 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { uint32_t tmp; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Reset interrupt callbacks to the legacy weak callbacks. * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; htim->TriggerCallback = HAL_TIM_TriggerCallback; htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; htim->ErrorCallback = HAL_TIM_ErrorCallback; htim->CommutationCallback = HAL_TIMEx_CommutCallback; htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; htim->BreakCallback = HAL_TIMEx_BreakCallback; htim->Break2Callback = HAL_TIMEx_Break2Callback; htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim_ex.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: * + Time Hall Sensor Interface Initialization * + Time Hall Sensor Interface Start * + Time Complementary signal break and dead time configuration * + Time Master and Slave synchronization configuration * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) * + Time OCRef clear configuration * + Timer remapping capabilities configuration * + Timer encoder index configuration ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### TIMER Extended features ##### ============================================================================== [..] The Timer Extended features include: (#) Complementary outputs with programmable dead-time for : (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Break input to put the timer output signals in reset state or in a known state. (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes (#) In case of Pulse on compare, configure pulse length and delay (#) Encoder index configuration ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the Timer Hall Sensor Interface and the commutation event with the corresponding Interrupt and DMA request if needed (Note that One Timer is used to interface with the Hall sensor Interface and another Timer should be used to use the commutation event). (#) In case of Pulse On Compare: (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup TIMEx TIMEx * @brief TIM Extended HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants * @{ */ /* Timeout for break input rearm */ #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ /** * @} */ /* End of private constants --------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @verbatim ============================================================================== ##### Timer Hall Sensor functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure TIM HAL Sensor. (+) De-initialize TIM HAL Sensor. (+) Start the Hall Sensor Interface. (+) Stop the Hall Sensor Interface. (+) Start the Hall Sensor Interface and enable interrupts. (+) Stop the Hall Sensor Interface and disable interrupts. (+) Start the Hall Sensor Interface and enable DMA transfers. (+) Stop the Hall Sensor Interface and disable DMA transfers. @endverbatim * @{ */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. * @note When the timer instance is initialized in Hall Sensor Interface mode, * timer channels 1 and channel 2 are reserved and cannot be used for * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy week callbacks */ TIM_ResetCallback(htim); if (htim->HallSensor_MspInitCallback == NULL) { htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->HallSensor_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->IC1Prescaler; /* Enable the Hall sensor interface (XOR function of the three inputs) */ htim->Instance->CR2 |= TIM_CR2_TI1S; /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1F_ED; /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ OC_Config.OCFastMode = TIM_OCFAST_DISABLE; OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; OC_Config.OCMode = TIM_OCMODE_PWM2; OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; OC_Config.Pulse = sConfig->Commutation_Delay; TIM_OC2_SetConfig(htim->Instance, &OC_Config); /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to 101 */ htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Hall Sensor interface * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->HallSensor_MspDeInitCallback == NULL) { htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; } /* DeInit the low level hardware */ htim->HallSensor_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Hall Sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 event */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @verbatim ============================================================================== ##### Timer Complementary Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary Output Compare/PWM. (+) Stop the Complementary Output Compare/PWM. (+) Start the Complementary Output Compare/PWM and enable interrupts. (+) Stop the Complementary Output Compare/PWM and disable interrupts. (+) Start the Complementary Output Compare/PWM and enable DMA transfers. (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. @endverbatim * @{ */ /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM OC handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @verbatim ============================================================================== ##### Timer Complementary PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary PWM. (+) Stop the Complementary PWM. (+) Start the Complementary PWM and enable interrupts. (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. @endverbatim * @{ */ /** * @brief Starts the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @verbatim ============================================================================== ##### Timer Complementary One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. (+) Select timer input source. (+) Enable or disable channel grouping. (+) Configure Pulse on compare. (+) Configure Encoder index. @endverbatim * @{ */ /** * @brief Configure the TIM commutation event sequence. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_ITR4: Internal trigger 4 selected (*) * @arg TIM_TS_ITR5: Internal trigger 5 selected * @arg TIM_TS_ITR6: Internal trigger 6 selected * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_ITR9: Internal trigger 9 selected (*) * @arg TIM_TS_ITR10: Internal trigger 10 selected * @arg TIM_TS_ITR11: Internal trigger 11 selected * @arg TIM_TS_NONE: No trigger is needed * * (*) Value not defined in all devices. * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); __HAL_LOCK(htim); #if defined(TIM5) && defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM5) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with interrupt. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_ITR4: Internal trigger 4 selected (*) * @arg TIM_TS_ITR5: Internal trigger 5 selected * @arg TIM_TS_ITR6: Internal trigger 6 selected * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_ITR9: Internal trigger 9 selected (*) * @arg TIM_TS_ITR10: Internal trigger 10 selected * @arg TIM_TS_ITR11: Internal trigger 11 selected * @arg TIM_TS_NONE: No trigger is needed * * (*) Value not defined in all devices. * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); __HAL_LOCK(htim); #if defined(TIM5) && defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM5) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); /* Enable the Commutation Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with DMA. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_ITR4: Internal trigger 4 selected (*) * @arg TIM_TS_ITR5: Internal trigger 5 selected * @arg TIM_TS_ITR6: Internal trigger 6 selected * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_ITR9: Internal trigger 9 selected (*) * @arg TIM_TS_ITR10: Internal trigger 10 selected * @arg TIM_TS_ITR11: Internal trigger 11 selected * @arg TIM_TS_NONE: No trigger is needed * * (*) Value not defined in all devices. * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); __HAL_LOCK(htim); #if defined(TIM5) && defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM5) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Enable the Commutation DMA Request */ /* Set the DMA Commutation Callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Enable the Commutation DMA Request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in master mode. * @param htim TIM handle. * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @note Interrupts can be generated when an active level is detected on the * break input, the break 2 input or the system break input. Break * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the break input source. * @param htim TIM handle. * @param BreakInput Break input to configure * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input * @param sBreakInputConfig Break input source configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; uint32_t bkin_enable_mask; uint32_t bkin_polarity_mask; uint32_t bkin_enable_bitpos; uint32_t bkin_polarity_bitpos; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); /* Check input state */ __HAL_LOCK(htim); switch (sBreakInputConfig->Source) { case TIM_BREAKINPUTSOURCE_BKIN: { bkin_enable_mask = TIM1_AF1_BKINE; bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; bkin_polarity_mask = TIM1_AF1_BKINP; bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP1: { bkin_enable_mask = TIM1_AF1_BKCMP1E; bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP1P; bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP2: { bkin_enable_mask = TIM1_AF1_BKCMP2E; bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP2P; bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP3: { bkin_enable_mask = TIM1_AF1_BKCMP3E; bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP3P; bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP4: { bkin_enable_mask = TIM1_AF1_BKCMP4E; bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP4P; bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos; break; } #if defined (COMP5) case TIM_BREAKINPUTSOURCE_COMP5: { bkin_enable_mask = TIM1_AF1_BKCMP5E; bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; } #endif /* COMP5 */ #if defined (COMP6) case TIM_BREAKINPUTSOURCE_COMP6: { bkin_enable_mask = TIM1_AF1_BKCMP6E; bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; } #endif /* COMP7 */ #if defined (COMP7) case TIM_BREAKINPUTSOURCE_COMP7: { bkin_enable_mask = TIM1_AF1_BKCMP7E; bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; } #endif /* COMP7 */ default: { bkin_enable_mask = 0U; bkin_polarity_mask = 0U; bkin_enable_bitpos = 0U; bkin_polarity_bitpos = 0U; break; } } switch (BreakInput) { case TIM_BREAKINPUT_BRK: { /* Get the TIMx_AF1 register value */ tmporx = htim->Instance->AF1; /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; /* Set the break input polarity */ tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; /* Set TIMx_AF1 */ htim->Instance->AF1 = tmporx; break; } case TIM_BREAKINPUT_BRK2: { /* Get the TIMx_AF2 register value */ tmporx = htim->Instance->AF2; /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; /* Set the break input polarity */ tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; /* Set TIMx_AF2 */ htim->Instance->AF2 = tmporx; break; } default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. * @param Remap specifies the TIM remapping source. * For TIM1, the parameter can take one of the following values: * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output * @arg TIM_TIM1_ETR_COMP3 TIM1 ETR is connected to COMP3 output * @arg TIM_TIM1_ETR_COMP4 TIM1 ETR is connected to COMP4 output * @arg TIM_TIM1_ETR_COMP5 TIM1 ETR is connected to COMP5 output (*) * @arg TIM_TIM1_ETR_COMP6 TIM1 ETR is connected to COMP6 output (*) * @arg TIM_TIM1_ETR_COMP7 TIM1 ETR is connected to COMP7 output (*) * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 (*) * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 (*) * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 (*) * * For TIM2, the parameter can take one of the following values: * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output * @arg TIM_TIM2_ETR_COMP3 TIM2 ETR is connected to COMP3 output * @arg TIM_TIM2_ETR_COMP4 TIM2 ETR is connected to COMP4 output * @arg TIM_TIM2_ETR_COMP5 TIM2 ETR is connected to COMP5 output (*) * @arg TIM_TIM2_ETR_COMP6 TIM2 ETR is connected to COMP6 output (*) * @arg TIM_TIM2_ETR_COMP7 TIM2 ETR is connected to COMP7 output (*) * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*) * @arg TIM_TIM2_ETR_LSE * * For TIM3, the parameter can take one of the following values: * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output * @arg TIM_TIM3_ETR_COMP3 TIM3 ETR is connected to COMP3 output * @arg TIM_TIM3_ETR_COMP4 TIM3 ETR is connected to COMP4 output * @arg TIM_TIM3_ETR_COMP5 TIM3 ETR is connected to COMP5 output (*) * @arg TIM_TIM3_ETR_COMP6 TIM3 ETR is connected to COMP6 output (*) * @arg TIM_TIM3_ETR_COMP7 TIM3 ETR is connected to COMP7 output (*) * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin * @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2 AWD1 * @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2 AWD2 * @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2 AWD3 * * For TIM4, the parameter can take one of the following values: * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output * @arg TIM_TIM4_ETR_COMP3 TIM4 ETR is connected to COMP3 output * @arg TIM_TIM4_ETR_COMP4 TIM4 ETR is connected to COMP4 output * @arg TIM_TIM4_ETR_COMP5 TIM4 ETR is connected to COMP5 output (*) * @arg TIM_TIM4_ETR_COMP6 TIM4 ETR is connected to COMP6 output (*) * @arg TIM_TIM4_ETR_COMP7 TIM4 ETR is connected to COMP7 output (*) * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin (*) * * For TIM5, the parameter can take one of the following values: (**) * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO (*) * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output (*) * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*) * @arg TIM_TIM5_ETR_COMP3 TIM5 ETR is connected to COMP3 output (*) * @arg TIM_TIM5_ETR_COMP4 TIM5 ETR is connected to COMP4 output (*) * @arg TIM_TIM5_ETR_COMP5 TIM5 ETR is connected to COMP5 output (*) * @arg TIM_TIM5_ETR_COMP6 TIM5 ETR is connected to COMP6 output (*) * @arg TIM_TIM5_ETR_COMP7 TIM5 ETR is connected to COMP7 output (*) * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin (*) * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin (*) * * For TIM8, the parameter can take one of the following values: * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output * @arg TIM_TIM8_ETR_COMP3 TIM8 ETR is connected to COMP3 output * @arg TIM_TIM8_ETR_COMP4 TIM8 ETR is connected to COMP4 output * @arg TIM_TIM8_ETR_COMP5 TIM8 ETR is connected to COMP5 output (*) * @arg TIM_TIM8_ETR_COMP6 TIM8 ETR is connected to COMP6 output (*) * @arg TIM_TIM8_ETR_COMP7 TIM8 ETR is connected to COMP7 output (*) * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2 AWD1 * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2 AWD2 * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2 AWD3 * @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3 AWD1 (*) * @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3 AWD2 (*) * @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3 AWD3 (*) * * For TIM20, the parameter can take one of the following values: (**) * @arg TIM_TIM20_ETR_GPIO TIM20 ETR is connected to GPIO * @arg TIM_TIM20_ETR_COMP1 TIM20 ETR is connected to COMP1 output (*) * @arg TIM_TIM20_ETR_COMP2 TIM20 ETR is connected to COMP2 output (*) * @arg TIM_TIM20_ETR_COMP3 TIM20 ETR is connected to COMP3 output (*) * @arg TIM_TIM20_ETR_COMP4 TIM20 ETR is connected to COMP4 output (*) * @arg TIM_TIM20_ETR_COMP5 TIM20 ETR is connected to COMP5 output (*) * @arg TIM_TIM20_ETR_COMP6 TIM20 ETR is connected to COMP6 output (*) * @arg TIM_TIM20_ETR_COMP7 TIM20 ETR is connected to COMP7 output (*) * @arg TIM_TIM20_ETR_ADC3_AWD1 TIM20 ETR is connected to ADC3 AWD1 (*) * @arg TIM_TIM20_ETR_ADC3_AWD2 TIM20 ETR is connected to ADC3 AWD2 (*) * @arg TIM_TIM20_ETR_ADC3_AWD3 TIM20 ETR is connected to ADC3 AWD3 (*) * @arg TIM_TIM20_ETR_ADC5_AWD1 TIM20 ETR is connected to ADC5 AWD1 (*) * @arg TIM_TIM20_ETR_ADC5_AWD2 TIM20 ETR is connected to ADC5 AWD2 (*) * @arg TIM_TIM20_ETR_ADC5_AWD3 TIM20 ETR is connected to ADC5 AWD3 (*) * * (*) Value not defined in all devices. \n * (**) Register not available in all devices. * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { /* Check parameters */ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); assert_param(IS_TIM_REMAP(Remap)); __HAL_LOCK(htim); MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Select the timer input source * @param htim TIM handle. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TI1 input channel * @arg TIM_CHANNEL_2: TI2 input channel * @arg TIM_CHANNEL_3: TI3 input channel * @arg TIM_CHANNEL_4: TI4 input channel * @param TISelection specifies the timer input source * For TIM1 this parameter can be one of the following values: * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output * @arg TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to COMP3 output * @arg TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to COMP4 output * * For TIM2 this parameter can be one of the following values: * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output * @arg TIM_TIM2_TI1_COMP3: TIM2 TI1 is connected to COMP3 output * @arg TIM_TIM2_TI1_COMP4: TIM2 TI1 is connected to COMP4 output * @arg TIM_TIM2_TI1_COMP5: TIM2 TI1 is connected to COMP5 output (*) * * @arg TIM_TIM2_TI2_GPIO: TIM1 TI2 is connected to GPIO * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output * @arg TIM_TIM2_TI2_COMP3: TIM2 TI2 is connected to COMP3 output * @arg TIM_TIM2_TI2_COMP4: TIM2 TI2 is connected to COMP4 output * @arg TIM_TIM2_TI2_COMP6: TIM2 TI2 is connected to COMP6 output (*) * * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO * @arg TIM_TIM2_TI3_COMP4: TIM2 TI3 is connected to COMP4 output * * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output * * For TIM3 this parameter can be one of the following values: * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output * @arg TIM_TIM3_TI1_COMP3: TIM3 TI1 is connected to COMP3 output * @arg TIM_TIM3_TI1_COMP4: TIM3 TI1 is connected to COMP4 output * @arg TIM_TIM3_TI1_COMP5: TIM3 TI1 is connected to COMP5 output (*) * @arg TIM_TIM3_TI1_COMP6: TIM3 TI1 is connected to COMP6 output (*) * @arg TIM_TIM3_TI1_COMP7: TIM3 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output * @arg TIM_TIM3_TI2_COMP3: TIM3 TI2 is connected to COMP3 output * @arg TIM_TIM3_TI2_COMP4: TIM3 TI2 is connected to COMP4 output * @arg TIM_TIM3_TI2_COMP5: TIM3 TI2 is connected to COMP5 output (*) * @arg TIM_TIM3_TI2_COMP6: TIM3 TI2 is connected to COMP6 output (*) * @arg TIM_TIM3_TI2_COMP7: TIM3 TI2 is connected to COMP7 output (*) * * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output * * For TIM4 this parameter can be one of the following values: * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output * @arg TIM_TIM4_TI1_COMP3: TIM4 TI1 is connected to COMP3 output * @arg TIM_TIM4_TI1_COMP4: TIM4 TI1 is connected to COMP4 output * @arg TIM_TIM4_TI1_COMP5: TIM4 TI1 is connected to COMP5 output (*) * @arg TIM_TIM4_TI1_COMP6: TIM4 TI1 is connected to COMP6 output (*) * @arg TIM_TIM4_TI1_COMP7: TIM4 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output * @arg TIM_TIM4_TI2_COMP3: TIM4 TI2 is connected to COMP3 output * @arg TIM_TIM4_TI2_COMP4: TIM4 TI2 is connected to COMP4 output * @arg TIM_TIM4_TI2_COMP5: TIM4 TI2 is connected to COMP5 output (*) * @arg TIM_TIM4_TI2_COMP6: TIM4 TI2 is connected to COMP6 output (*) * @arg TIM_TIM4_TI2_COMP7: TIM4 TI2 is connected to COMP7 output (*) * * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO * @arg TIM_TIM4_TI3_COMP5: TIM4 TI3 is connected to COMP5 output (*) * * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO * @arg TIM_TIM4_TI4_COMP6: TIM4 TI4 is connected to COMP6 output (*) * * For TIM5 this parameter can be one of the following values: (**) * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI clock (*) * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE clock (*) * @arg TIM_TIM5_TI1_RTC_WK: TIM5 TI1 is connected to RTC Wakeup (*) * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output (*) * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*) * @arg TIM_TIM5_TI1_COMP3: TIM5 TI1 is connected to COMP3 output (*) * @arg TIM_TIM5_TI1_COMP4: TIM5 TI1 is connected to COMP4 output (*) * @arg TIM_TIM5_TI1_COMP5: TIM5 TI1 is connected to COMP5 output (*) * @arg TIM_TIM5_TI1_COMP6: TIM5 TI1 is connected to COMP6 output (*) * @arg TIM_TIM5_TI1_COMP7: TIM5 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output * @arg TIM_TIM5_TI2_COMP3: TIM5 TI2 is connected to COMP3 output * @arg TIM_TIM5_TI2_COMP4: TIM5 TI2 is connected to COMP4 output * @arg TIM_TIM5_TI2_COMP5: TIM5 TI2 is connected to COMP5 output (*) * @arg TIM_TIM5_TI2_COMP6: TIM5 TI2 is connected to COMP6 output (*) * @arg TIM_TIM5_TI2_COMP7: TIM5 TI2 is connected to COMP7 output (*) * * For TIM8 this parameter can be one of the following values: * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output * @arg TIM_TIM8_TI1_COMP3: TIM8 TI1 is connected to COMP3 output * @arg TIM_TIM8_TI1_COMP4: TIM8 TI1 is connected to COMP4 output * * For TIM15 this parameter can be one of the following values: * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE clock * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output * @arg TIM_TIM15_TI1_COMP5: TIM15 TI1 is connected to COMP5 output (*) * @arg TIM_TIM15_TI1_COMP7: TIM15 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output * @arg TIM_TIM15_TI2_COMP3: TIM15 TI2 is connected to COMP3 output * @arg TIM_TIM15_TI2_COMP6: TIM15 TI2 is connected to COMP6 output (*) * @arg TIM_TIM15_TI2_COMP7: TIM15 TI2 is connected to COMP7 output (*) * * For TIM16 this parameter can be one of the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_TI1_COMP6: TIM16 TI1 is connected to COMP6 output (*) * @arg TIM_TIM16_TI1_MCO: TIM15 TI1 is connected to MCO output * @arg TIM_TIM16_TI1_HSE_32: TIM15 TI1 is connected to HSE div 32 * @arg TIM_TIM16_TI1_RTC_WK: TIM15 TI1 is connected to RTC wakeup * @arg TIM_TIM16_TI1_LSE: TIM15 TI1 is connected to LSE clock * @arg TIM_TIM16_TI1_LSI: TIM15 TI1 is connected to LSI clock * * For TIM17 this parameter can be one of the following values: * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO * @arg TIM_TIM17_TI1_COMP5: TIM17 TI1 is connected to COMP5 output (*) * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO output * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 * @arg TIM_TIM17_TI1_RTC_WK: TIM17 TI1 is connected to RTC wakeup * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE clock * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI clock * For TIM20 this parameter can be one of the following values: (**) * @arg TIM_TIM20_TI1_GPIO: TIM20 TI1 is connected to GPIO * @arg TIM_TIM20_TI1_COMP1: TIM20 TI1 is connected to COMP1 output (*) * @arg TIM_TIM20_TI1_COMP2: TIM20 TI1 is connected to COMP2 output (*) * @arg TIM_TIM20_TI1_COMP3: TIM20 TI1 is connected to COMP3 output (*) * @arg TIM_TIM20_TI1_COMP4: TIM20 TI1 is connected to COMP4 output (*) * * (*) Value not defined in all devices. \n * (**) Register not available in all devices. * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check parameters */ assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_TISEL(TISelection)); __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); /* If required, set OR bit to request HSE/32 clock */ if (IS_TIM_HSE32_INSTANCE(htim->Instance)) { SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN); } else { CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN); } break; case TIM_CHANNEL_2: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); break; case TIM_CHANNEL_3: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); break; case TIM_CHANNEL_4: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); break; default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Group channel 5 and channel 1, 2 or 3 * @param htim TIM handle. * @param Channels specifies the reference signal(s) the OC5REF is combined with. * This parameter can be any combination of the following values: * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) { /* Check parameters */ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); assert_param(IS_TIM_GROUPCH5(Channels)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Clear GC5Cx bit fields */ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); /* Set GC5Cx bit fields */ htim->Instance->CCR5 |= Channels; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Disarm the designated break input (when it operates in bidirectional mode). * @param htim TIM handle. * @param BreakInput Break input to disarm * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input * @note The break input can be disarmed only when it is configured in * bidirectional mode and when when MOE is reset. * @note Purpose is to be able to have the input voltage back to high-state, * whatever the time constant on the output . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpbdtr; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) { case TIM_BREAKINPUT_BRK: { /* Check initial conditions */ tmpbdtr = READ_REG(htim->Instance->BDTR); if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) { /* Break input BRK is disarmed */ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); } break; } case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ tmpbdtr = READ_REG(htim->Instance->BDTR); if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) { /* Break input BRK is disarmed */ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); } break; } default: status = HAL_ERROR; break; } return status; } /** * @brief Arm the designated break input (when it operates in bidirectional mode). * @param htim TIM handle. * @param BreakInput Break input to arm * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input * @note Arming is possible at anytime, even if fault is present. * @note Break input is automatically armed as soon as MOE bit is set. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) { case TIM_BREAKINPUT_BRK: { /* Check initial conditions */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) { /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { return HAL_TIMEOUT; } } } } break; } case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) { /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { return HAL_TIMEOUT; } } } } break; } default: status = HAL_ERROR; break; } return status; } /** * @brief Enable dithering * @param htim TIM handle * @note Main usage is PWM mode * @note This function must be called when timer is stopped or disabled (CEN =0) * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers * (corresponds to 4094 for the integer part and 15 for the dithered part). * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() * can be used to calculate period (ARR) and delay (CCRx) value. * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); return HAL_OK; } /** * @brief Disable dithering * @param htim TIM handle * @note This function must be called when timer is stopped or disabled (CEN =0) * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers * - ARR and CCRx values are limited to 0xFFEF in dithering mode * (corresponds to 4094 for the integer part and 15 for the dithered part). * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); return HAL_OK; } /** * @brief Initializes the pulse on compare pulse width and pulse prescaler * @param htim TIM Output Compare handle * @param PulseWidthPrescaler Pulse width prescaler * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7 * @param PulseWidth Pulse width * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth) { uint32_t tmpecr; /* Check the parameters */ assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance)); assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth)); assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler)); /* Process Locked */ __HAL_LOCK(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx ECR register value */ tmpecr = htim->Instance->ECR; /* Reset the Pulse width prescaler and the Pulse width */ tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW); /* Set the Pulse width prescaler and Pulse width*/ tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos; tmpecr |= PulseWidth << TIM_ECR_PW_Pos; /* Write to TIMx ECR */ htim->Instance->ECR = tmpecr; /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register) * @param htim TIM handle * @param Source Source of slave mode selection preload * This parameter can be one of the following values: * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source)); MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source); return HAL_OK; } /** * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register) * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); return HAL_OK; } /** * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register) * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); return HAL_OK; } /** * @brief Enable deadtime preload * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); return HAL_OK; } /** * @brief Disable deadtime preload * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); return HAL_OK; } /** * @brief Configure deadtime * @param htim TIM handle * @param Deadtime Deadtime value * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_DEADTIME(Deadtime)); MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime); return HAL_OK; } /** * @brief Configure asymmetrical deadtime * @param htim TIM handle * @param FallingDeadtime Falling edge deadtime value * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_DEADTIME(FallingDeadtime)); MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); return HAL_OK; } /** * @brief Enable asymmetrical deadtime * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); return HAL_OK; } /** * @brief Disable asymmetrical deadtime * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); return HAL_OK; } /** * @brief Configures the encoder index. * @note warning in case of encoder mode clock plus direction * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN * @param htim TIM handle. * @param sEncoderIndexConfig Encoder index configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity)); assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler)); assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter)); assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable)); assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position)); assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction)); /* Process Locked */ __HAL_LOCK(htim); /* Configures the TIMx External Trigger (ETR) which is used as Index input */ TIM_ETR_SetConfig(htim->Instance, sEncoderIndexConfig->Prescaler, sEncoderIndexConfig->Polarity, sEncoderIndexConfig->Filter); /* Configures the encoder index */ MODIFY_REG(htim->Instance->ECR, TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, (sEncoderIndexConfig->Direction | ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | sEncoderIndexConfig->Position | TIM_ECR_IE)); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Enable encoder index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->ECR, TIM_ECR_IE); return HAL_OK; } /** * @brief Disable encoder index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); return HAL_OK; } /** * @brief Enable encoder first index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); return HAL_OK; } /** * @brief Disable encoder first index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @verbatim ============================================================================== ##### Extended Callbacks functions ##### ============================================================================== [..] This section provides Extended TIM callback functions: (+) Timer Commutation callback (+) Timer Break callback @endverbatim * @{ */ /** * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } /** * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file */ } /** * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } /** * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } /** * @brief Encoder index callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file */ } /** * @brief Direction change callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file */ } /** * @brief Index error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_IndexErrorCallback could be implemented in the user file */ } /** * @brief Transition error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @verbatim ============================================================================== ##### Extended Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Hall Sensor interface handle state. * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return actual state of the TIM complementary channel. * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); return channel_state; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ /** * @brief TIM DMA Commutation callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Commutation half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationHalfCpltCallback(htim); #else HAL_TIMEx_CommutHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Delay Pulse complete callback (complementary channel). * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA error callback (complementary channel) * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { uint32_t tmp; tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ } /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_ll_adc.c * @author MCD Application Team * @brief ADC LL module driver ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_ll_adc.h" #include "stm32g4xx_ll_bus.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G4xx_LL_Driver * @{ */ #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) /** @addtogroup ADC_LL ADC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADC_LL_Private_Constants * @{ */ /* Definitions of ADC hardware constraints delays */ /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values: */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ /* values definition. */ /* Note: ADC timeout values are defined here in CPU cycles to be independent */ /* of device clock setting. */ /* In user application, ADC timeout values should be defined with */ /* temporal values, in function of device clock settings. */ /* Highest ratio CPU clock frequency vs ADC clock frequency: */ /* - ADC clock from synchronous clock with AHB prescaler 512, */ /* ADC prescaler 4. */ /* Ratio max = 512 *4 = 2048 */ /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ /* Highest CPU clock PLL (PLLR). */ /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ /* = 3968 */ /* Unit: CPU cycles. */ #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL) #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup ADC_LL_Private_Macros * @{ */ /* Check of parameters for configuration of ADC hierarchical scope: */ /* common to several ADC instances. */ #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ ) /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC instance. */ #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ ) #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ ) #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ ) /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC group regular */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) \ ) \ ) \ ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ ) \ ) \ ) #elif defined(STM32G471xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || (((__ADC_INSTANCE__) == ADC3) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ ) \ ) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || (((__ADC_INSTANCE__) == ADC3) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ ) \ ) \ ) #endif /* STM32G4xx */ #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ ) #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ ) #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ ) #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ ) #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ ) /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC group injected */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #elif defined(STM32G471xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #endif /* STM32G4xx */ #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ ) #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ ) #if defined(ADC_MULTIMODE_SUPPORT) /* Check of parameters for configuration of ADC hierarchical scope: */ /* multimode. */ #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ ) #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \ ) #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ ) #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ ) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_LL_Exported_Functions * @{ */ /** @addtogroup ADC_LL_EF_Init * @{ */ /** * @brief De-initialize registers of all ADC instances belonging to * the same ADC common instance to their default reset values. * @note This function is performing a hard reset, using high level * clock source RCC ADC reset. * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * To de-initialize only 1 ADC instance, use * function @ref LL_ADC_DeInit(). * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); if (ADCxy_COMMON == ADC12_COMMON) { /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12); /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12); } #if defined(ADC345_COMMON) else { /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345); /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345); } #endif /* ADC345_COMMON */ return SUCCESS; } /** * @brief Initialize some features of ADC common parameters * (all ADC instances belonging to the same ADC common instance) * and multimode (for devices with several ADC instances available). * @note The setting of ADC common parameters is conditioned to * ADC instances state: * All ADC instances belonging to the same ADC common instance * must be disabled. * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock)); #if defined(ADC_MULTIMODE_SUPPORT) assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode)); if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer)); assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay)); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ /* (all ADC instances belonging to the same ADC common instance) */ /* - Set ADC clock (conversion clock) */ /* - multimode (if several ADC instances available on the */ /* selected device) */ /* - Set ADC multimode configuration */ /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY , pADC_CommonInitStruct->CommonClock | pADC_CommonInitStruct->Multimode | pADC_CommonInitStruct->MultiDMATransfer | pADC_CommonInitStruct->MultiTwoSamplingDelay ); } else { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY , pADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } #else LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock); #endif /* ADC_MULTIMODE_SUPPORT */ } else { /* Initialization error: One or several ADC instances belonging to */ /* the same ADC common instance are not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { /* Set pADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ pADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; pADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; #endif /* ADC_MULTIMODE_SUPPORT */ } /** * @brief De-initialize registers of the selected ADC instance * to their default reset values. * @note To reset all ADC instances quickly (perform a hard reset), * use function @ref LL_ADC_CommonDeInit(). * @note If this functions returns error status, it means that ADC instance * is in an unknown state. * In this case, perform a hard reset using high level * clock source RCC ADC reset. * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * Refer to function @ref LL_ADC_CommonDeInit(). * @param ADCx ADC instance * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are de-initialized * - ERROR: ADC registers are not de-initialized */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { ErrorStatus status = SUCCESS; __IO uint32_t timeout_cpu_cycles = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); /* Disable ADC instance if not already disabled. */ if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Stop potential ADC conversion on going on ADC group regular. */ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_REG_StopConversion(ADCx); } } /* Stop potential ADC conversion on going on ADC group injected. */ if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_INJ_StopConversion(ADCx); } } /* Wait for ADC conversions are effectively stopped */ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) { timeout_cpu_cycles--; if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; break; } } /* Flush group injected contexts queue (register JSQR): */ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ /* contexts queue is maintained with the last active context). */ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); /* Disable the ADC instance */ LL_ADC_Disable(ADCx); /* Wait for ADC instance is effectively disabled */ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) { timeout_cpu_cycles--; if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; break; } } } /* Check whether ADC state is compliant with expected state */ if (READ_BIT(ADCx->CR, (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) ) == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ CLEAR_BIT(ADCx->IER, (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR | LL_ADC_IT_EOSMP | LL_ADC_IT_JEOC | LL_ADC_IT_JEOS | LL_ADC_IT_JQOVF | LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3 ) ); /* Reset register ISR */ SET_BIT(ADCx->ISR, (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP | LL_ADC_FLAG_JEOC | LL_ADC_FLAG_JEOS | LL_ADC_FLAG_JQOVF | LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3 ) ); /* Reset register CR */ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ /* access mode "read-set": no direct reset applicable. */ /* - Reset Calibration mode to default setting (single ended). */ /* - Disable ADC internal voltage regulator. */ /* - Enable ADC deep power down. */ /* Note: ADC internal voltage regulator disable and ADC deep power */ /* down enable are conditioned to ADC state disabled: */ /* already done above. */ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); /* Reset register CFGR */ MODIFY_REG(ADCx->CFGR, (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN), ADC_CFGR_JQDIS ); /* Reset register CFGR2 */ CLEAR_BIT(ADCx->CFGR2, (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG | ADC_CFGR2_GCOMP | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) ); /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) ); /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) ); /* Reset register TR1 */ MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); /* Reset register TR2 */ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); /* Reset register TR3 */ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L) ); /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) ); /* Reset register SQR3 */ CLEAR_BIT(ADCx->SQR3, (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) ); /* Reset register SQR4 */ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); /* Reset register DR */ /* Note: bits in access mode read only, no direct reset applicable */ /* Reset register OFR1 */ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS); /* Reset register OFR2 */ CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS); /* Reset register OFR3 */ CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); /* Reset register OFR4 */ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ /* Reset register AWD2CR */ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); /* Reset register AWD3CR */ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); /* Reset register DIFSEL */ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); /* Reset register CALFACT */ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); /* Reset register GCOMP */ CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF); } else { /* ADC instance is in an unknown state */ /* Need to performing a hard reset of ADC instance, using high level */ /* clock source RCC ADC reset. */ /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ status = ERROR; } return status; } /** * @brief Initialize some features of ADC instance. * @note These parameters have an impact on ADC scope: ADC instance. * Affects both group regular and group injected (availability * of ADC group injected depends on STM32 series). * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Instance . * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. * @note After using this function, some other features must be configured * using LL unitary functions. * The minimum configuration remaining to be done is: * - Set ADC group regular or group injected sequencer: * map channel on the selected sequencer rank. * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution)); assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment)); assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ /* - Set ADC data resolution */ /* - Set ADC conversion data alignment */ /* - Set ADC low power mode */ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_AUTDLY , pADC_InitStruct->Resolution | pADC_InitStruct->DataAlignment | pADC_InitStruct->LowPowerMode ); } else { /* Initialization error: ADC instance is not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_InitTypeDef field to default value. * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) { /* Set pADC_InitStruct fields to default values */ /* Set fields of ADC instance */ pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; } /** * @brief Initialize some features of ADC group regular. * @note These parameters have an impact on ADC scope: ADC group regular. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "REG"). * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. * @note After using this function, other features must be configured * using LL unitary functions. * The minimum configuration remaining to be done is: * - Set ADC group regular or group injected sequencer: * map channel on the selected sequencer rank. * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, pADC_RegInitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont)); /* ADC group regular continuous mode and discontinuous mode */ /* can not be enabled simultenaeously */ assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer)); assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ /* - Set ADC group regular trigger source */ /* - Set ADC group regular sequencer length */ /* - Set ADC group regular sequencer discontinuous mode */ /* - Set ADC group regular continuous mode */ /* - Set ADC group regular conversion data transfer: no transfer or */ /* transfer by DMA, and DMA requests mode */ /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD , pADC_RegInitStruct->TriggerSource | pADC_RegInitStruct->SequencerDiscont | pADC_RegInitStruct->ContinuousMode | pADC_RegInitStruct->DMATransfer | pADC_RegInitStruct->Overrun ); } else { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD , pADC_RegInitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE | pADC_RegInitStruct->ContinuousMode | pADC_RegInitStruct->DMATransfer | pADC_RegInitStruct->Overrun ); } /* Set ADC group regular sequencer length and scan direction */ LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength); } else { /* Initialization error: ADC instance is not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { /* Set pADC_RegInitStruct fields to default values */ /* Set fields of ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; } /** * @brief Initialize some features of ADC group injected. * @note These parameters have an impact on ADC scope: ADC group injected. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "INJ"). * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. * @note After using this function, other features must be configured * using LL unitary functions. * The minimum configuration remaining to be done is: * - Set ADC group injected sequencer: * map channel on the selected sequencer rank. * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @note Caution if feature ADC group injected contexts queue is enabled * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): * using successively several times this function will appear as * having no effect. * To set several features of ADC group injected, use * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, pADC_InjInitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength)); if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ /* - Set ADC group injected trigger source */ /* - Set ADC group injected sequencer length */ /* - Set ADC group injected sequencer discontinuous mode */ /* - Set ADC group injected conversion trigger: independent or */ /* from ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO , pADC_InjInitStruct->SequencerDiscont | pADC_InjInitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO , LL_ADC_REG_SEQ_DISCONT_DISABLE | pADC_InjInitStruct->TrigAuto ); } MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL , pADC_InjInitStruct->TriggerSource | pADC_InjInitStruct->SequencerLength ); } else { /* Initialization error: ADC instance is not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. * @param pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct) { /* Set pADC_InjInitStruct fields to default values */ /* Set fields of ADC group injected */ pADC_InjInitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; pADC_InjInitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; pADC_InjInitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; } /** * @} */ /** * @} */ /** * @} */ #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ ================================================ FILE: Production Modules/2OPFM/firmware/2OPFM_G431/STM32G431KBUX_FLASH.ld ================================================ /* ****************************************************************************** ** ** @file : LinkerScript.ld ** ** @author : Auto-generated by STM32CubeIDE ** ** @brief : Linker script for STM32G431KBUx Device from STM32G4 series ** 128Kbytes FLASH ** 32Kbytes RAM ** ** Set heap size, stack size and stack location according ** to application requirements. ** ** Set memory bank area and size if external memory is used ** ** Target : STMicroelectronics STM32 ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ****************************************************************************** ** @attention ** ** Copyright (c) 2024 STMicroelectronics. ** All rights reserved. ** ** This software is licensed under terms that can be found in the LICENSE file ** in the root directory of this software component. ** If no LICENSE file comes with this software, it is provided AS-IS. ** ****************************************************************************** */ /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ _Min_Heap_Size = 0x0 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K } /* Sections */ SECTIONS { /* The startup code into "FLASH" Rom type memory */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >FLASH /* The program code and other data into "FLASH" Rom type memory */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ *(.glue_7) /* glue arm to thumb code */ *(.glue_7t) /* glue thumb to arm code */ *(.eh_frame) KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ } >FLASH /* Constant data into "FLASH" Rom type memory */ .rodata : { . = ALIGN(4); *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); } >FLASH .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH .ARM : { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; . = ALIGN(4); } >FLASH .preinit_array : { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); } >FLASH .init_array : { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); } >FLASH .fini_array : { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); . = ALIGN(4); } >FLASH /* Used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections into "RAM" Ram type memory */ .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ *(.RamFunc) /* .RamFunc sections */ *(.RamFunc*) /* .RamFunc* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH /* Uninitialized data section into "RAM" Ram type memory */ . = ALIGN(4); .bss : { /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; } >RAM /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ ._user_heap_stack : { . = ALIGN(8); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM /* Remove information from the compiler libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } .ARM.attributes 0 : { *(.ARM.attributes) } } ================================================ FILE: Production Modules/2OPFM/firmware/README.md ================================================ If you're not making any modifications, use STM32CubeProgrammer to flash the .elf file and you'll be good to go. This is the recommended approach! This is the recommended approach! Make sure to match the REV (either REV4 or REV5) to your hardware. REV5 is harder to solder by hand, but includes a V/OCT jumper and is the recommended version. The .elfs are named according to hardware version, but the folders of source code are named consistent with their STM32CubeIDE projects. 2OPFM_G431 is the latest, 2OPFM_2020 is older. I will eventually put detailed import and build instructions up, but for now: 1: Import the project to STM32CubeIDE 2: Make sure optimization is set to "For Speed" 3: Build and run it! These obviously assume familiarity with the process. If you are not and have questions about how to get it rolling, please don't hesitate to reach out (but google first!) You may notice that this code is organized poorly, and I may agree. Instead of doing a song and dance to provide something especially clean, I wanted to share what the 2OPFM module really is and how it does its thang. ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/.cproject ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/.mxproject ================================================ [PreviousLibFiles] LibFiles=Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_crs.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h;Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_crs.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h;Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h;Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h;Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h;Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h;Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h;Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h; [PreviousUsedCubeIDEFiles] SourceFiles=Core/Src/main.c;Core/Src/stm32f3xx_it.c;Core/Src/stm32f3xx_hal_msp.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c;Core/Src/system_stm32f3xx.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c;Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c;Core/Src/system_stm32f3xx.c;Drivers/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c;; HeaderPath=Drivers/STM32F3xx_HAL_Driver/Inc;Drivers/STM32F3xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F3xx/Include;Drivers/CMSIS/Include;Core/Inc; CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32F334x8;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=4 HeaderFiles#0=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Inc/stm32f3xx_it.h HeaderFiles#1=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Inc/stm32_assert.h HeaderFiles#2=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Inc/stm32f3xx_hal_conf.h HeaderFiles#3=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Inc/main.h HeaderFolderListSize=1 HeaderPath#0=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Inc HeaderFiles=; SourceFileListSize=3 SourceFiles#0=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Src/stm32f3xx_it.c SourceFiles#1=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Src/stm32f3xx_hal_msp.c SourceFiles#2=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Src/main.c SourceFolderListSize=1 SourcePath#0=/Users/SUPER/Desktop/Things/STM32CubeIDE/CubeIDE - Super/2OPFM_2020/Core/Src SourceFiles=; ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/.project ================================================ 2OPFM_2020 org.eclipse.cdt.managedbuilder.core.genmakebuilder clean,full,incremental, org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder full,incremental, com.st.stm32cube.ide.mcu.MCUProjectNature com.st.stm32cube.ide.mcu.MCUCubeProjectNature org.eclipse.cdt.core.cnature com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature com.st.stm32cube.ide.mcu.MCURootProjectNature org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/.settings/language.settings.xml ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/.settings/stm32cubeide.project.prefs ================================================ 2F62501ED4689FB349E356AB974DBE57=D0B8994BE5D696B009884EA60EF3F057 8DF89ED150041C4CBC7CB9A9CAA90856=D0B8994BE5D696B009884EA60EF3F057 DC22A860405A8BF2F2C095E5B6529F12=2E2E5BD1907FCB788DCFA2DA90FE2A18 eclipse.preferences.version=1 ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/2OPFM_2020 Debug.launch ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/2OPFM_2020.ioc ================================================ #MicroXplorer Configuration settings - do not modify ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1 ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_2 ADC1.Channel-2\#ChannelRegularConversion=ADC_CHANNEL_3 ADC1.Channel-3\#ChannelRegularConversion=ADC_CHANNEL_4 ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_11 ADC1.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_12 ADC1.Channel-6\#ChannelRegularConversion=ADC_CHANNEL_VREFINT ADC1.ContinuousConvMode=DISABLE ADC1.DMAContinuousRequests=ENABLE ADC1.EOCSelection=ADC_EOC_SEQ_CONV ADC1.EnableInjectedConversion=DISABLE ADC1.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T3_TRGO ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,Offset-0\#ChannelRegularConversion,NbrOfConversionFlag,Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,Offset-1\#ChannelRegularConversion,Rank-2\#ChannelRegularConversion,Channel-2\#ChannelRegularConversion,SamplingTime-2\#ChannelRegularConversion,OffsetNumber-2\#ChannelRegularConversion,Offset-2\#ChannelRegularConversion,Rank-3\#ChannelRegularConversion,Channel-3\#ChannelRegularConversion,SamplingTime-3\#ChannelRegularConversion,OffsetNumber-3\#ChannelRegularConversion,Offset-3\#ChannelRegularConversion,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,OffsetNumber-4\#ChannelRegularConversion,Offset-4\#ChannelRegularConversion,NbrOfConversion,ContinuousConvMode,DMAContinuousRequests,EnableInjectedConversion,EOCSelection,ExternalTrigConv,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,OffsetNumber-5\#ChannelRegularConversion,Offset-5\#ChannelRegularConversion,Rank-6\#ChannelRegularConversion,Channel-6\#ChannelRegularConversion,SamplingTime-6\#ChannelRegularConversion,OffsetNumber-6\#ChannelRegularConversion,Offset-6\#ChannelRegularConversion,master,SubFamily,Resolution ADC1.NbrOfConversion=7 ADC1.NbrOfConversionFlag=1 ADC1.Offset-0\#ChannelRegularConversion=0 ADC1.Offset-1\#ChannelRegularConversion=0 ADC1.Offset-2\#ChannelRegularConversion=0 ADC1.Offset-3\#ChannelRegularConversion=0 ADC1.Offset-4\#ChannelRegularConversion=0 ADC1.Offset-5\#ChannelRegularConversion=0 ADC1.Offset-6\#ChannelRegularConversion=0 ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-2\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-3\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-4\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-5\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.OffsetNumber-6\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.Rank-1\#ChannelRegularConversion=2 ADC1.Rank-2\#ChannelRegularConversion=3 ADC1.Rank-3\#ChannelRegularConversion=4 ADC1.Rank-4\#ChannelRegularConversion=5 ADC1.Rank-5\#ChannelRegularConversion=6 ADC1.Rank-6\#ChannelRegularConversion=7 ADC1.Resolution=ADC_RESOLUTION_12B ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC1.SamplingTime-2\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC1.SamplingTime-3\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC1.SamplingTime-6\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC1.SubFamily=STM32F334x8 ADC1.master=1 ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_2 ADC2.DMAContinuousRequests=ENABLE ADC2.ExternalTrigConv=ADC_EXTERNALTRIGCONV_T1_TRGO ADC2.IPParameters=SubFamily,Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,Offset-0\#ChannelRegularConversion,NbrOfConversionFlag,ExternalTrigConv,DMAContinuousRequests,Resolution ADC2.NbrOfConversionFlag=1 ADC2.Offset-0\#ChannelRegularConversion=0 ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE ADC2.Rank-0\#ChannelRegularConversion=1 ADC2.Resolution=ADC_RESOLUTION_12B ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_601CYCLES_5 ADC2.SubFamily=STM32F334x8 Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY Dma.ADC1.0.Instance=DMA1_Channel1 Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.ADC1.0.MemInc=DMA_MINC_ENABLE Dma.ADC1.0.Mode=DMA_CIRCULAR Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE Dma.ADC1.0.Priority=DMA_PRIORITY_LOW Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority Dma.ADC2.1.Direction=DMA_PERIPH_TO_MEMORY Dma.ADC2.1.Instance=DMA1_Channel2 Dma.ADC2.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.ADC2.1.MemInc=DMA_MINC_ENABLE Dma.ADC2.1.Mode=DMA_CIRCULAR Dma.ADC2.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.ADC2.1.PeriphInc=DMA_PINC_DISABLE Dma.ADC2.1.Priority=DMA_PRIORITY_LOW Dma.ADC2.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority Dma.Request0=ADC1 Dma.Request1=ADC2 Dma.RequestsNb=2 File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.Family=STM32F3 Mcu.IP0=ADC1 Mcu.IP1=ADC2 Mcu.IP10=TIM3 Mcu.IP2=DAC1 Mcu.IP3=DAC2 Mcu.IP4=DMA Mcu.IP5=NVIC Mcu.IP6=RCC Mcu.IP7=SYS Mcu.IP8=TIM1 Mcu.IP9=TIM2 Mcu.IPNb=11 Mcu.Name=STM32F334K(4-6-8)Tx Mcu.Package=LQFP32 Mcu.Pin0=PA0 Mcu.Pin1=PA1 Mcu.Pin10=VP_ADC1_Vref_Input Mcu.Pin11=VP_SYS_VS_Systick Mcu.Pin12=VP_TIM1_VS_ClockSourceINT Mcu.Pin13=VP_TIM2_VS_ClockSourceINT Mcu.Pin14=VP_TIM3_VS_ClockSourceINT Mcu.Pin2=PA2 Mcu.Pin3=PA3 Mcu.Pin4=PA4 Mcu.Pin5=PA5 Mcu.Pin6=PA6 Mcu.Pin7=PA7 Mcu.Pin8=PB0 Mcu.Pin9=PB1 Mcu.PinsNb=15 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F334K8Tx MxCube.Version=5.5.0 MxDb.Version=DB.5.0.50 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.TIM1_UP_TIM16_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.TIM3_IRQn=true\:0\:0\:false\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false PA0.Locked=true PA0.Mode=IN1-Single-Ended PA0.Signal=ADC1_IN1 PA1.Locked=true PA1.Mode=IN2-Single-Ended PA1.Signal=ADC1_IN2 PA2.Locked=true PA2.Mode=IN3-Single-Ended PA2.Signal=ADC1_IN3 PA3.Locked=true PA3.Mode=IN4-Single-Ended PA3.Signal=ADC1_IN4 PA4.Locked=true PA4.Signal=COMP_DAC11_group PA5.Locked=true PA5.Mode=IN2-Single-Ended PA5.Signal=ADC2_IN2 PA6.Locked=true PA6.Signal=COMP_DAC21_group PA7.GPIOParameters=GPIO_PuPd PA7.GPIO_PuPd=GPIO_PULLUP PA7.Locked=true PA7.Signal=GPIO_Input PB0.Locked=true PB0.Mode=IN11-Single-Ended PB0.Signal=ADC1_IN11 PB1.Locked=true PB1.Mode=IN12-Single-Ended PB1.Signal=ADC1_IN12 PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=false ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=false ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F334K8Tx ProjectManager.FirmwarePackage=STM32Cube FW_F3 V1.11.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Core/Src ProjectManager.NoMain=false ProjectManager.PreviousToolchain=STM32CubeIDE ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=2OPFM_2020.ioc ProjectManager.ProjectName=2OPFM_2020 ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-LL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_DAC1_Init-DAC1-false-LL-true,6-MX_DAC2_Init-DAC2-false-LL-true,7-MX_TIM2_Init-TIM2-false-LL-true,8-MX_TIM3_Init-TIM3-false-LL-true,9-MX_ADC2_Init-ADC2-false-HAL-true,10-MX_TIM1_Init-TIM1-false-LL-true RCC.ADC12outputFreq_Value=64000000 RCC.AHBFreq_Value=64000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 RCC.APB1Freq_Value=32000000 RCC.APB1TimFreq_Value=64000000 RCC.APB2Freq_Value=64000000 RCC.APB2TimFreq_Value=64000000 RCC.CortexFreq_Value=64000000 RCC.FCLKCortexFreq_Value=64000000 RCC.FamilyName=M RCC.HCLKFreq_Value=64000000 RCC.HRTIM1Freq_Value=64000000 RCC.HSEPLLFreq_Value=8000000 RCC.HSE_VALUE=8000000 RCC.HSIPLLFreq_Value=4000000 RCC.HSI_VALUE=8000000 RCC.I2C1Freq_Value=8000000 RCC.IPParameters=ADC12outputFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSEPLLFreq_Value,HSE_VALUE,HSIPLLFreq_Value,HSI_VALUE,I2C1Freq_Value,LSI_VALUE,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSourceVirtual,TIM1Freq_Value,TIM2Freq_Value,USART1Freq_Value,VCOOutput2Freq_Value RCC.LSI_VALUE=40000 RCC.MCOFreq_Value=64000000 RCC.PLLCLKFreq_Value=64000000 RCC.PLLMCOFreq_Value=64000000 RCC.PLLMUL=RCC_PLL_MUL16 RCC.RTCFreq_Value=40000 RCC.RTCHSEDivFreq_Value=250000 RCC.SYSCLKFreq_VALUE=64000000 RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK RCC.TIM1Freq_Value=64000000 RCC.TIM2Freq_Value=64000000 RCC.USART1Freq_Value=32000000 RCC.VCOOutput2Freq_Value=4000000 SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1 SH.COMP_DAC11_group.ConfNb=1 SH.COMP_DAC21_group.0=DAC2_OUT1,Switch_Enable_OUT1 SH.COMP_DAC21_group.ConfNb=1 TIM1.IPParameters=TIM_MasterOutputTrigger,Period TIM1.Period=4800 TIM1.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM2.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE TIM2.IPParameters=Prescaler,Period,AutoReloadPreload,TIM_MasterOutputTrigger TIM2.Period=1600 TIM2.Prescaler=0 TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM3.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE TIM3.IPParameters=Period,AutoReloadPreload,TIM_MasterOutputTrigger,Prescaler TIM3.Period=12800 TIM3.Prescaler=0 TIM3.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE VP_ADC1_Vref_Input.Mode=IN-Vrefint VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM1_VS_ClockSourceINT.Mode=Internal VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT VP_TIM3_VS_ClockSourceINT.Mode=Internal VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT board=custom isbadioc=false ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/2op_main.h ================================================ /* * 2op_main.h * * Created on: Jun 4, 2020 * Author: SUPER */ #ifndef INC_2OP_MAIN_H_ #define INC_2OP_MAIN_H_ #include "main.h" //***************************************************************************************** uint16_t expo_lut[1024]; typedef enum { ATTACK, DECAY, RELEASE, OFF, RETRIG } envelope_stage; typedef struct { volatile float output; volatile envelope_stage stage; volatile float rate; volatile float rate_offset; volatile float attack_offset; volatile float release_offset; volatile float cutoff; volatile float target; volatile float attack; volatile float decay; volatile float sustain; volatile float release; volatile char one_shot; volatile uint8_t gate; volatile uint8_t trig; } soft_adsr; void adsr_structinit(soft_adsr* adsr); void run_adsr(soft_adsr* adsr); void run_ar(soft_adsr* adsr); //************************************************************************************************ //#define ONLY_ONE_SHOTS #define SMOOTH_ATTACK #define SMOOTH_ATTACK_INCREMENT 0.1f //#define VOCT #ifdef VOCT #define KHZ_IN_SCALING 0.1395f #else #define KHZ_IN_SCALING 0.25f #endif #define ENV_INIT 1.0f #define KHZ_PRE_FILTER float noise_offset; typedef struct { //uint is cool! int32_t output; float amplitude; float frequency; uint32_t phase_increment; uint32_t phase_index; //uint is cool! int32_t modulation; soft_adsr ADSR; } Operator; float filtered_decay_jack; float decay_sum; float ENV_AMT; float ENV_OFFSET; int32_t output, voice1, voice2; float env_lowpass; uint32_t dummy; //int32_t freqSum; float freqSum; float khz_pot; float khz_in; float filtered_khz_in; uint8_t note; float fm_ratio; uint8_t gate, trig, last_trig, last_gate; float env_lp; Operator OP1, OP2; uint32_t operator_run(Operator *OP, float envelope); void operator_structinit(Operator *OP); void check_gate(); void check_trig(); void set_adsr_parameters(soft_adsr *adsr); void slow_2op_parameter_loop(); int16_t tanh_table[256]; void tanh_table_init(); void main_2OP_loop(); //todo needs to run in slow loop // run_ar(&OP1.ADSR); #endif /* INC_2OP_MAIN_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/big_expo.h ================================================ /* * big_expo.h * * Created on: Dec 1, 2020 * Author: SUPER */ #ifndef INC_BIG_EXPO_H_ #define INC_BIG_EXPO_H_ static const float big_expo[4096] = {0,1,2}; #endif /* INC_BIG_EXPO_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/big_sine_wave.h ================================================ /* * big_sine_wave.h * * Created on: Mar 31, 2020 * Author: SUPER */ #ifndef BIG_SINE_WAVE_H_ #define BIG_SINE_WAVE_H_ #include "main.h" static const uint16_t big_sine_wave[1024] = { 32768, 32969, 33170, 33371, 33572, 33773, 33974, 34174, 34375, 34576, 34777, 34977, 35178, 35378, 35579, 35779, 35979, 36179, 36379, 36579, 36779, 36978, 37177, 37377, 37575, 37774, 37973, 38171, 38369, 38567, 38765, 38963, 39160, 39357, 39554, 39751, 39947, 40143, 40339, 40534, 40729, 40924, 41119, 41313, 41507, 41701, 41894, 42087, 42279, 42472, 42663, 42855, 43046, 43237, 43427, 43617, 43807, 43996, 44184, 44373, 44560, 44748, 44935, 45121, 45307, 45493, 45678, 45862, 46046, 46230, 46413, 46595, 46777, 46959, 47140, 47320, 47500, 47679, 47858, 48036, 48214, 48391, 48567, 48743, 48919, 49093, 49267, 49441, 49613, 49785, 49957, 50128, 50298, 50468, 50636, 50805, 50972, 51139, 51305, 51471, 51635, 51799, 51963, 52125, 52287, 52448, 52609, 52768, 52927, 53085, 53243, 53399, 53555, 53710, 53864, 54018, 54170, 54322, 54473, 54623, 54773, 54921, 55069, 55216, 55362, 55507, 55652, 55795, 55938, 56079, 56220, 56360, 56499, 56637, 56775, 56911, 57047, 57181, 57315, 57448, 57579, 57710, 57840, 57969, 58097, 58224, 58350, 58475, 58600, 58723, 58845, 58966, 59087, 59206, 59324, 59441, 59558, 59673, 59787, 59900, 60013, 60124, 60234, 60343, 60451, 60558, 60664, 60769, 60873, 60976, 61078, 61178, 61278, 61377, 61474, 61571, 61666, 61760, 61853, 61945, 62036, 62126, 62215, 62302, 62389, 62474, 62559, 62642, 62724, 62805, 62885, 62963, 63041, 63117, 63192, 63266, 63339, 63411, 63482, 63551, 63620, 63687, 63753, 63818, 63881, 63944, 64005, 64065, 64124, 64182, 64238, 64294, 64348, 64401, 64453, 64504, 64553, 64601, 64648, 64694, 64739, 64782, 64825, 64866, 64905, 64944, 64981, 65018, 65053, 65086, 65119, 65150, 65180, 65209, 65237, 65263, 65289, 65313, 65335, 65357, 65377, 65396, 65414, 65431, 65446, 65460, 65473, 65485, 65496, 65505, 65513, 65520, 65525, 65529, 65533, 65534, 65535, 65534, 65533, 65529, 65525, 65520, 65513, 65505, 65496, 65485, 65473, 65460, 65446, 65431, 65414, 65396, 65377, 65357, 65335, 65313, 65289, 65263, 65237, 65209, 65180, 65150, 65119, 65086, 65053, 65018, 64981, 64944, 64905, 64866, 64825, 64782, 64739, 64694, 64648, 64601, 64553, 64504, 64453, 64401, 64348, 64294, 64238, 64182, 64124, 64065, 64005, 63944, 63881, 63818, 63753, 63687, 63620, 63551, 63482, 63411, 63339, 63266, 63192, 63117, 63041, 62963, 62885, 62805, 62724, 62642, 62559, 62474, 62389, 62302, 62215, 62126, 62036, 61945, 61853, 61760, 61666, 61571, 61474, 61377, 61278, 61178, 61078, 60976, 60873, 60769, 60664, 60558, 60451, 60343, 60234, 60124, 60013, 59900, 59787, 59673, 59558, 59441, 59324, 59206, 59087, 58966, 58845, 58723, 58600, 58475, 58350, 58224, 58097, 57969, 57840, 57710, 57579, 57448, 57315, 57181, 57047, 56911, 56775, 56637, 56499, 56360, 56220, 56079, 55938, 55795, 55652, 55507, 55362, 55216, 55069, 54921, 54773, 54623, 54473, 54322, 54170, 54018, 53864, 53710, 53555, 53399, 53243, 53085, 52927, 52768, 52609, 52448, 52287, 52125, 51963, 51799, 51635, 51471, 51305, 51139, 50972, 50805, 50636, 50468, 50298, 50128, 49957, 49785, 49613, 49441, 49267, 49093, 48919, 48743, 48567, 48391, 48214, 48036, 47858, 47679, 47500, 47320, 47140, 46959, 46777, 46595, 46413, 46230, 46046, 45862, 45678, 45493, 45307, 45121, 44935, 44748, 44560, 44373, 44184, 43996, 43807, 43617, 43427, 43237, 43046, 42855, 42663, 42472, 42279, 42087, 41894, 41701, 41507, 41313, 41119, 40924, 40729, 40534, 40339, 40143, 39947, 39751, 39554, 39357, 39160, 38963, 38765, 38567, 38369, 38171, 37973, 37774, 37575, 37377, 37177, 36978, 36779, 36579, 36379, 36179, 35979, 35779, 35579, 35378, 35178, 34977, 34777, 34576, 34375, 34174, 33974, 33773, 33572, 33371, 33170, 32969, 32768, 32566, 32365, 32164, 31963, 31762, 31561, 31361, 31160, 30959, 30758, 30558, 30357, 30157, 29956, 29756, 29556, 29356, 29156, 28956, 28756, 28557, 28358, 28158, 27960, 27761, 27562, 27364, 27166, 26968, 26770, 26572, 26375, 26178, 25981, 25784, 25588, 25392, 25196, 25001, 24806, 24611, 24416, 24222, 24028, 23834, 23641, 23448, 23256, 23063, 22872, 22680, 22489, 22298, 22108, 21918, 21728, 21539, 21351, 21162, 20975, 20787, 20600, 20414, 20228, 20042, 19857, 19673, 19489, 19305, 19122, 18940, 18758, 18576, 18395, 18215, 18035, 17856, 17677, 17499, 17321, 17144, 16968, 16792, 16616, 16442, 16268, 16094, 15922, 15750, 15578, 15407, 15237, 15067, 14899, 14730, 14563, 14396, 14230, 14064, 13900, 13736, 13572, 13410, 13248, 13087, 12926, 12767, 12608, 12450, 12292, 12136, 11980, 11825, 11671, 11517, 11365, 11213, 11062, 10912, 10762, 10614, 10466, 10319, 10173, 10028, 9883, 9740, 9597, 9456, 9315, 9175, 9036, 8898, 8760, 8624, 8488, 8354, 8220, 8087, 7956, 7825, 7695, 7566, 7438, 7311, 7185, 7060, 6935, 6812, 6690, 6569, 6448, 6329, 6211, 6094, 5977, 5862, 5748, 5635, 5522, 5411, 5301, 5192, 5084, 4977, 4871, 4766, 4662, 4559, 4457, 4357, 4257, 4158, 4061, 3964, 3869, 3775, 3682, 3590, 3499, 3409, 3320, 3233, 3146, 3061, 2976, 2893, 2811, 2730, 2650, 2572, 2494, 2418, 2343, 2269, 2196, 2124, 2053, 1984, 1915, 1848, 1782, 1717, 1654, 1591, 1530, 1470, 1411, 1353, 1297, 1241, 1187, 1134, 1082, 1031, 982, 934, 887, 841, 796, 753, 710, 669, 630, 591, 554, 517, 482, 449, 416, 385, 355, 326, 298, 272, 246, 222, 200, 178, 158, 139, 121, 104, 89, 75, 62, 50, 39, 30, 22, 15, 10, 6, 2, 1, 0, 1, 2, 6, 10, 15, 22, 30, 39, 50, 62, 75, 89, 104, 121, 139, 158, 178, 200, 222, 246, 272, 298, 326, 355, 385, 416, 449, 482, 517, 554, 591, 630, 669, 710, 753, 796, 841, 887, 934, 982, 1031, 1082, 1134, 1187, 1241, 1297, 1353, 1411, 1470, 1530, 1591, 1654, 1717, 1782, 1848, 1915, 1984, 2053, 2124, 2196, 2269, 2343, 2418, 2494, 2572, 2650, 2730, 2811, 2893, 2976, 3061, 3146, 3233, 3320, 3409, 3499, 3590, 3682, 3775, 3869, 3964, 4061, 4158, 4257, 4357, 4457, 4559, 4662, 4766, 4871, 4977, 5084, 5192, 5301, 5411, 5522, 5635, 5748, 5862, 5977, 6094, 6211, 6329, 6448, 6569, 6690, 6812, 6935, 7060, 7185, 7311, 7438, 7566, 7695, 7825, 7956, 8087, 8220, 8354, 8488, 8624, 8760, 8898, 9036, 9175, 9315, 9456, 9597, 9740, 9883, 10028, 10173, 10319, 10466, 10614, 10762, 10912, 11062, 11213, 11365, 11517, 11671, 11825, 11980, 12136, 12292, 12450, 12608, 12767, 12926, 13087, 13248, 13410, 13572, 13736, 13900, 14064, 14230, 14396, 14563, 14730, 14899, 15067, 15237, 15407, 15578, 15750, 15922, 16094, 16268, 16442, 16616, 16792, 16968, 17144, 17321, 17499, 17677, 17856, 18035, 18215, 18395, 18576, 18758, 18940, 19122, 19305, 19489, 19673, 19857, 20042, 20228, 20414, 20600, 20787, 20975, 21162, 21351, 21539, 21728, 21918, 22108, 22298, 22489, 22680, 22872, 23063, 23256, 23448, 23641, 23834, 24028, 24222, 24416, 24611, 24806, 25001, 25196, 25392, 25588, 25784, 25981, 26178, 26375, 26572, 26770, 26968, 27166, 27364, 27562, 27761, 27960, 28158, 28358, 28557, 28756, 28956, 29156, 29356, 29556, 29756, 29956, 30157, 30357, 30558, 30758, 30959, 31160, 31361, 31561, 31762, 31963, 32164, 32365, 32566 }; #endif /* BIG_SINE_WAVE_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/dac.h ================================================ /* * dac.h * * Created on: Apr 3, 2020 * Author: SUPER */ #ifndef INC_DAC_H_ #define INC_DAC_H_ #include "main.h" void dac_out(uint16_t _out_val); void dac2_ch1(uint16_t _out_val); void dac1_ch1(uint16_t _out_val); #endif /* INC_DAC_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/dynamic_smooth.h ================================================ /* * dynamic_smooth.h * * Created on: Sep 19, 2020 * Author: SUPER */ #ifndef INC_DYNAMIC_SMOOTH_H_ #define INC_DYNAMIC_SMOOTH_H_ #include "main.h" typedef struct { //init values float g0; float sense; //tick values float low1; float low2; float low1z; float low2z; float bandz; float out; }dynamic_smooth; dynamic_smooth dynamic_smooth_a; float dynamic_smooth_tick(dynamic_smooth* _smooth, float in); void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity); #endif /* INC_DYNAMIC_SMOOTH_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/global_variables.h ================================================ /* * global_variables.h * * Created on: Apr 2, 2020 * Author: SUPER */ #ifndef INC_GLOBAL_VARIABLES_H_ #define INC_GLOBAL_VARIABLES_H_ #include "stm32f3xx.h" #define NUM_ADC_CHANNELS 7 uint16_t adc_data[NUM_ADC_CHANNELS]; uint16_t adc_data_10b[NUM_ADC_CHANNELS-1]; uint16_t voct_data[1]; uint16_t vdd_mv; uint32_t vdd_cal; float khz_correction; uint16_t ramp; uint16_t khz_in_mv; #endif /* INC_GLOBAL_VARIABLES_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/loop.h ================================================ /* * loop.h * * Created on: Apr 2, 2020 * Author: SUPER */ #ifndef INC_LOOP_H_ #define INC_LOOP_H_ void loop(void); #endif /* INC_LOOP_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/main.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.h * @brief : Header for main.c file. * This file contains the common defines of the application. ****************************************************************************** * @attention * *

© Copyright (c) 2020 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MAIN_H #define __MAIN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" #include "stm32f3xx_ll_dac.h" #include "stm32f3xx_ll_rcc.h" #include "stm32f3xx_ll_bus.h" #include "stm32f3xx_ll_system.h" #include "stm32f3xx_ll_exti.h" #include "stm32f3xx_ll_cortex.h" #include "stm32f3xx_ll_utils.h" #include "stm32f3xx_ll_pwr.h" #include "stm32f3xx_ll_dma.h" #include "stm32f3xx_ll_tim.h" #include "stm32f3xx.h" #include "stm32f3xx_ll_gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ //#include "math.h" #include "pin_map.h" #include "loop.h" #include "global_variables.h" #include "noise.h" #include "big_sine_wave.h" #include "dac.h" #include "dynamic_smooth.h" #include "2op_main.h" /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ /* USER CODE BEGIN ET */ /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ /* USER CODE BEGIN EC */ /* USER CODE END EC */ /* Exported macro ------------------------------------------------------------*/ /* USER CODE BEGIN EM */ /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ /* USER CODE BEGIN Private defines */ #define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */ #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FFFF7BAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ (((__DATA__) \ << ((__ADC_RESOLUTION_CURRENT__) >> (0U))) \ >> ((__ADC_RESOLUTION_TARGET__) >> (0U)) \ ) #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ (__ADC_RESOLUTION__), \ LL_ADC_RESOLUTION_12B) \ ) /* USER CODE END Private defines */ #ifdef __cplusplus } #endif #endif /* __MAIN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/noise.h ================================================ /* * noise.h * * Created on: Mar 31, 2020 * Author: SUPER */ #ifndef NOISE_H_ #define NOISE_H_ #include "main.h" uint32_t noise(void); #endif /* NOISE_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/pin_map.h ================================================ /* * pin_map.h * * Created on: Jun 4, 2020 * Author: SUPER */ #ifndef INC_PIN_MAP_H_ #define INC_PIN_MAP_H_ #define GATE_PORT GPIOA #define GATE_PIN GPIO_PIN_7 #define TRIG_PORT GPIOA #define TRIG_PIN GPIO_PIN_7 #define KHZ_POT 3 #define RATIO_POT 2 #define DECAY_SLIDER 5 #define DECAY_JACK 0 #define FM_SLIDER 4 #define FM_JACK 1 #endif /* INC_PIN_MAP_H_ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/stm32_assert.h ================================================ /** ****************************************************************************** * @file stm32_assert.h * @brief STM32 assert file. ****************************************************************************** * @attention * *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32_ASSERT_H #define __STM32_ASSERT_H #ifdef __cplusplus extern "C" { #endif /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* __STM32_ASSERT_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/stm32f3xx_hal_conf.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_conf.h * @brief HAL configuration file. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_CONF_H #define __STM32F3xx_HAL_CONF_H #ifdef __cplusplus extern "C" { #endif /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* ########################## Module Selection ############################## */ /** * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */ /*#define HAL_CEC_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_PCCARD_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_HRTIM_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ /*#define HAL_SDADC_MODULE_ENABLED */ /*#define HAL_TSC_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_DAC_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_IWDG_MODULE_ENABLED */ /*#define HAL_LCD_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */ /*#define HAL_RNG_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_UART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED /* ########################## HSE/HSI Values adaptation ##################### */ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** * @brief In the following line adjust the External High Speed oscillator (HSE) Startup * Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup * Timeout value */ #if !defined (HSI_STARTUP_TIMEOUT) #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ #endif /* HSI_STARTUP_TIMEOUT */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) #define LSI_VALUE ((uint32_t)40000) #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. */ #if !defined (LSE_VALUE) #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ /** * @brief Time out for LSE start up value in ms. */ #if !defined (LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** * @brief External clock source for I2S peripheral * This value is used by the I2S HAL module to compute the I2S clock source * frequency, this source is inserted directly through I2S_CKIN pad. * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal) * - External clock not generated on EVAL 373 */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 #define INSTRUCTION_CACHE_ENABLE 0 #define DATA_CACHE_ENABLE 0 #define USE_SPI_CRC 0U #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ #define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ #define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ #define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ /* ########################## Assert Selection ############################## */ /** * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32f3xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32f3xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ #ifdef HAL_EXTI_MODULE_ENABLED #include "stm32f3xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32f3xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32f3xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ #ifdef HAL_ADC_MODULE_ENABLED #include "stm32f3xx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ #ifdef HAL_CAN_MODULE_ENABLED #include "stm32f3xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ #ifdef HAL_CAN_LEGACY_MODULE_ENABLED #include "stm32f3xx_hal_can_legacy.h" #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f3xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ #ifdef HAL_COMP_MODULE_ENABLED #include "stm32f3xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f3xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED #include "stm32f3xx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f3xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32f3xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ #ifdef HAL_NOR_MODULE_ENABLED #include "stm32f3xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ #ifdef HAL_NAND_MODULE_ENABLED #include "stm32f3xx_hal_nand.h" #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_PCCARD_MODULE_ENABLED #include "stm32f3xx_hal_pccard.h" #endif /* HAL_PCCARD_MODULE_ENABLED */ #ifdef HAL_HRTIM_MODULE_ENABLED #include "stm32f3xx_hal_hrtim.h" #endif /* HAL_HRTIM_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED #include "stm32f3xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_I2S_MODULE_ENABLED #include "stm32f3xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED #include "stm32f3xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED #include "stm32f3xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32f3xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED #include "stm32f3xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED #include "stm32f3xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED #include "stm32f3xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SDADC_MODULE_ENABLED #include "stm32f3xx_hal_sdadc.h" #endif /* HAL_SDADC_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED #include "stm32f3xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED #include "stm32f3xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED #include "stm32f3xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED #include "stm32f3xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_TSC_MODULE_ENABLED #include "stm32f3xx_hal_tsc.h" #endif /* HAL_TSC_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED #include "stm32f3xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED #include "stm32f3xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED #include "stm32f3xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_CONF_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Inc/stm32f3xx_it.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32f3xx_it.h * @brief This file contains the headers of the interrupt handlers. ****************************************************************************** * @attention * *

© Copyright (c) 2020 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_IT_H #define __STM32F3xx_IT_H #ifdef __cplusplus extern "C" { #endif /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ /* USER CODE BEGIN ET */ /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ /* USER CODE BEGIN EC */ /* USER CODE END EC */ /* Exported macro ------------------------------------------------------------*/ /* USER CODE BEGIN EM */ /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ void NMI_Handler(void); void HardFault_Handler(void); void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void DMA1_Channel1_IRQHandler(void); void DMA1_Channel2_IRQHandler(void); void TIM1_UP_TIM16_IRQHandler(void); void TIM2_IRQHandler(void); void TIM3_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_IT_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/2op_main.c ================================================ /* * 2op_main.c * * Created on: Jun 4, 2020 * Author: SUPER */ #include "2op_main.h" #include "big_expo.h" uint16_t expo_lut[1024] = { 65535, 64771, 64017, 63271, 62534, 61805, 61085, 60374, 59670, 58975, 58288, 57609, 56938, 56274, 55619, 54971, 54330, 53697, 53072, 52454, 51842, 51238, 50642, 50052, 49468, 48892, 48322, 47760, 47203, 46653, 46110, 45572, 45042, 44517, 43998, 43486, 42979, 42478, 41983, 41494, 41011, 40533, 40061, 39594, 39133, 38677, 38226, 37781, 37341, 36906, 36476, 36051, 35631, 35216, 34805, 34400, 33999, 33603, 33212, 32825, 32442, 32064, 31691, 31321, 30957, 30596, 30239, 29887, 29539, 29195, 28855, 28519, 28186, 27858, 27533, 27213, 26896, 26582, 26272, 25966, 25664, 25365, 25069, 24777, 24489, 24203, 23921, 23643, 23367, 23095, 22826, 22560, 22297, 22037, 21781, 21527, 21276, 21028, 20783, 20541, 20302, 20065, 19832, 19600, 19372, 19146, 18923, 18703, 18485, 18270, 18057, 17846, 17639, 17433, 17230, 17029, 16831, 16635, 16441, 16249, 16060, 15873, 15688, 15505, 15325, 15146, 14970, 14795, 14623, 14452, 14284, 14118, 13953, 13791, 13630, 13471, 13314, 13159, 13006, 12854, 12705, 12557, 12410, 12266, 12123, 11982, 11842, 11704, 11568, 11433, 11300, 11168, 11038, 10909, 10782, 10657, 10532, 10410, 10288, 10169, 10050, 9933, 9817, 9703, 9590, 9478, 9368, 9259, 9151, 9044, 8939, 8835, 8732, 8630, 8529, 8430, 8332, 8235, 8139, 8044, 7950, 7858, 7766, 7676, 7586, 7498, 7410, 7324, 7239, 7154, 7071, 6989, 6907, 6827, 6747, 6669, 6591, 6514, 6438, 6363, 6289, 6216, 6144, 6072, 6001, 5931, 5862, 5794, 5726, 5660, 5594, 5529, 5464, 5400, 5338, 5275, 5214, 5153, 5093, 5034, 4975, 4917, 4860, 4803, 4747, 4692, 4637, 4583, 4530, 4477, 4425, 4373, 4323, 4272, 4222, 4173, 4125, 4077, 4029, 3982, 3936, 3890, 3845, 3800, 3755, 3712, 3668, 3626, 3583, 3542, 3500, 3460, 3419, 3380, 3340, 3301, 3263, 3225, 3187, 3150, 3113, 3077, 3041, 3006, 2971, 2936, 2902, 2868, 2835, 2802, 2769, 2737, 2705, 2673, 2642, 2612, 2581, 2551, 2521, 2492, 2463, 2434, 2406, 2378, 2350, 2323, 2296, 2269, 2242, 2216, 2191, 2165, 2140, 2115, 2090, 2066, 2042, 2018, 1995, 1971, 1948, 1926, 1903, 1881, 1859, 1837, 1816, 1795, 1774, 1753, 1733, 1713, 1693, 1673, 1654, 1634, 1615, 1596, 1578, 1559, 1541, 1523, 1506, 1488, 1471, 1454, 1437, 1420, 1403, 1387, 1371, 1355, 1339, 1323, 1308, 1293, 1278, 1263, 1248, 1234, 1219, 1205, 1191, 1177, 1163, 1150, 1136, 1123, 1110, 1097, 1084, 1072, 1059, 1047, 1035, 1023, 1011, 999, 987, 976, 964, 953, 942, 931, 920, 910, 899, 889, 878, 868, 858, 848, 838, 828, 819, 809, 800, 790, 781, 772, 763, 754, 745, 737, 728, 720, 711, 703, 695, 687, 679, 671, 663, 655, 648, 640, 633, 625, 618, 611, 604, 597, 590, 583, 576, 569, 563, 556, 550, 543, 537, 531, 524, 518, 512, 506, 500, 495, 489, 483, 477, 472, 466, 461, 456, 450, 445, 440, 435, 430, 425, 420, 415, 410, 405, 400, 396, 391, 387, 382, 378, 373, 369, 365, 360, 356, 352, 348, 344, 340, 336, 332, 328, 324, 321, 317, 313, 309, 306, 302, 299, 295, 292, 288, 285, 282, 278, 275, 272, 269, 266, 263, 260, 257, 254, 251, 248, 245, 242, 239, 236, 234, 231, 228, 226, 223, 220, 218, 215, 213, 210, 208, 205, 203, 201, 198, 196, 194, 191, 189, 187, 185, 183, 181, 178, 176, 174, 172, 170, 168, 166, 164, 162, 161, 159, 157, 155, 153, 151, 150, 148, 146, 144, 143, 141, 139, 138, 136, 135, 133, 132, 130, 129, 127, 126, 124, 123, 121, 120, 118, 117, 116, 114, 113, 112, 110, 109, 108, 107, 105, 104, 103, 102, 100, 99, 98, 97, 96, 95, 94, 93, 91, 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, 79, 79, 78, 77, 76, 75, 74, 73, 72, 72, 71, 70, 69, 68, 67, 67, 66, 65, 64, 64, 63, 62, 61, 61, 60, 59, 59, 58, 57, 57, 56, 55, 55, 54, 53, 53, 52, 52, 51, 50, 50, 49, 49, 48, 47, 47, 46, 46, 45, 45, 44, 44, 43, 43, 42, 42, 41, 41, 40, 40, 39, 39, 38, 38, 38, 37, 37, 36, 36, 35, 35, 35, 34, 34, 33, 33, 33, 32, 32, 31, 31, 31, 30, 30, 30, 29, 29, 29, 28, 28, 28, 27, 27, 27, 26, 26, 26, 26, 25, 25, 25, 24, 24, 24, 23, 23, 23, 23, 22, 22, 22, 22, 21, 21, 21, 21, 20, 20, 20, 20, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; void adsr_structinit(soft_adsr *adsr) { adsr->output = ENV_INIT; adsr->attack = 0.0f; adsr->decay = 0.0f; adsr->sustain = 0.0f; adsr->release = 0.0f; adsr->stage = OFF; adsr->rate = 0.0f; adsr->rate_offset = 0.0f; adsr->cutoff = 0.0f; adsr->target = ENV_INIT; adsr->one_shot = 0; } void run_adsr(soft_adsr *adsr) { if (adsr->output < 0.01f) { adsr->one_shot = 0; } if (adsr->stage == ATTACK) { adsr->target = 1.0f; adsr->rate = adsr->attack; //attack threshold if (adsr->output > 0.9f) { adsr->stage = DECAY; } } //sustain at decay if (adsr->stage == DECAY) { adsr->rate = adsr->decay; adsr->target = adsr->sustain; if (adsr->one_shot) { if (adsr->output < (adsr->sustain + 0.01f)) { adsr->stage = RELEASE; } } } //low at release if (adsr->stage == RELEASE) { adsr->rate = adsr->release; adsr->target = 0.0f; } adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; if (adsr->cutoff > 0.99) { adsr->cutoff = 0.99; } if (adsr->cutoff < 0.0) { adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } void run_ar(soft_adsr *adsr) { if (adsr->output < 0.01f) { adsr->one_shot = 0; } if (adsr->stage == ATTACK) { adsr->target = 1.0f; adsr->rate = adsr->attack + adsr->attack_offset; //attack threshold if (adsr->one_shot) { if (adsr->output > 0.9f) { adsr->stage = RELEASE; } } } //low at release if (adsr->stage == RELEASE) { adsr->rate = adsr->release + adsr->release_offset; adsr->target = 0.0f; } adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; //adsr->cutoff = adsr->rate; if (adsr->cutoff > 0.99) { adsr->cutoff = 0.99; } if (adsr->cutoff < 0.0) { adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } void run_linear_a_expo_r(soft_adsr *adsr) { //one shot style smooth attack if (adsr->output < 0.01f) { adsr->one_shot = 0; } if (adsr->stage == ATTACK) { adsr->output += SMOOTH_ATTACK_INCREMENT; adsr->rate = adsr->attack + adsr->attack_offset; //attack threshold if (adsr->output > 0.95f) { adsr->stage = RELEASE; } } else { //low at release if (adsr->stage == RELEASE) { adsr->rate = adsr->release + adsr->release_offset; adsr->target = 0.0f; } adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; //adsr->cutoff = adsr->rate; if (adsr->cutoff > 0.99) { adsr->cutoff = 0.99; } if (adsr->cutoff < 0.0) { adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } } //***************************************************************************************************** uint32_t operator_run(Operator *OP, float envelope) { OP->phase_index += OP->phase_increment; OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; return OP->phase_index; } void operator_structinit(Operator *OP) { OP->output = 0; OP->amplitude = 1.0f; OP->frequency = 440.0f; OP->phase_increment = ((4294967295) * (OP->frequency)) / 44100.0f; } void check_gate() { //read gate gate = !HAL_GPIO_ReadPin(GATE_PORT, GATE_PIN); //if low to high transition occurs if (gate) { if (!last_gate) { //set stage to attack #ifdef ONLY_ONE_SHOTS OP1.phase_index = 0; OP2.phase_index = 0; OP1.ADSR.output = 1.0f; OP1.ADSR.stage = RELEASE; OP1.ADSR.one_shot = 0; #else //OP1.phase_index = 0; //OP2.phase_index = 0; OP1.ADSR.stage = ATTACK; //OP1.ADSR.output = 1.0f; OP1.ADSR.one_shot = 0; #endif } } last_gate = gate; } void check_trig() { //read trig trig = !HAL_GPIO_ReadPin(TRIG_PORT, TRIG_PIN); //if low to high transition occurs if (trig) { if (!last_trig) { if (OP1.ADSR.output < 0.3f) { //set stage to attack OP1.phase_index = 0; OP2.phase_index = 0; OP1.ADSR.output = 1.0f; OP1.ADSR.stage = RELEASE; OP1.ADSR.one_shot = 0; } } } //if high to low transistion occurs if (!trig) { if (last_trig) { //set stage to release } } last_trig = trig; } void set_adsr_parameters(soft_adsr *adsr) { adsr->rate_offset = 0.0005f; adsr->attack = 7.0f; filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; int16_t jin_offset; jin_offset = adc_data_10b[DECAY_SLIDER] - (adc_data_10b[DECAY_JACK] - 495); if (jin_offset < 0) { jin_offset = 0; } if (jin_offset > 1023) { jin_offset = 1023; } decay_sum = expo_lut[jin_offset] + 100.0f; adsr->release = (decay_sum) / 100000.0f; } void slow_2op_parameter_loop() { //loop check_gate(); check_trig(); set_adsr_parameters(&OP1.ADSR); } //fast interrupt for audio void main_2OP_loop() { ENV_OFFSET += (((((960 - adc_data_10b[FM_JACK]) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; ENV_AMT = (adc_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; if (ENV_AMT < 0.0f) { ENV_AMT = 0.0f; } //khz pot, 1p filter khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; #ifdef KHZ_PRE_FILTER //khz input, 1p filter filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; //khz input, 2p adaptive filter khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; #else //khz input, 2p adaptive filter khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (voct_data[0] - 2048)) * KHZ_IN_SCALING; #endif freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; //filtered fm ratio fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); if (adc_data_10b[DECAY_SLIDER] > 1000) { OP1.ADSR.output = 1.0f; } operator_run(&OP1, OP1.ADSR.output); operator_run(&OP2, OP1.ADSR.output * OP1.ADSR.output); OP1.modulation = (OP2.output) >> 3; //original voice1 = (OP1.output) >> 5; output = voice1; //hard clipping if (output > 2047) { output = 2047; } if (output < -2047) { output = -2047; } //DAC output dac1_ch1((output) + 2048); } ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/dac.c ================================================ /* * dac.c * * Created on: Apr 3, 2020 * Author: SUPER */ #include "dac.h" #include "main.h" inline void dac2_ch1(uint16_t _out_val) { LL_DAC_ConvertData12RightAligned(DAC2, LL_DAC_CHANNEL_1, _out_val); } inline void dac1_ch1(uint16_t _out_val) { LL_DAC_ConvertData12RightAligned(DAC1, LL_DAC_CHANNEL_1, _out_val); } ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/dynamic_smooth.c ================================================ /* * dynamic_smooth.c * * Created on: Sep 19, 2020 * Author: SUPER */ #include "dynamic_smooth.h" float cm_min(float a, float b) { return ((a) < (b) ? a : b); } float cm_abs(float a) { if (a < 0.000f) { return a*-1.0; } else { return a; } } void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity) { float basefreq, sensitivity, wc, gc; //init values basefreq = _base; sensitivity = _sensitivity; wc = basefreq / 22050.0f; //gc = tan(3.14f * wc); gc = .00000712018209f; _smooth->g0 = 2*gc/(1+gc); _smooth->sense = sensitivity * 4.0f; //tick values _smooth->low1 = 0.0f; _smooth->low2 = 0.0f; _smooth->low1z = 0.0f; _smooth->low2z = 0.0f; _smooth->bandz = 0.0f; _smooth->out = 0.0f; } float dynamic_smooth_tick(dynamic_smooth* _smooth, float in) { float g; _smooth->low1z = _smooth->low1; _smooth->low2z = _smooth->low2; _smooth->bandz = _smooth->low2z - _smooth->low1z; g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); return _smooth->low2; } ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/loop.c ================================================ /* * loop.c * * Created on: Apr 2, 2020 * Author: SUPER */ #include "loop.h" #include "main.h" void loop(void) { //dac1_ch1(ramp); dac2_ch1(2047); vdd_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(adc_data[6],LL_ADC_RESOLUTION_12B); vdd_cal = (uint32_t)(*VREFINT_CAL_ADDR); khz_correction = vdd_mv / 3300.0f; khz_in_mv = voct_data[0] * 3300 >> 12; } ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/main.c ================================================ /* USER CODE BEGIN Header */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN PTD */ /* USER CODE END PTD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ //#define ADC_12_BIT /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; DMA_HandleTypeDef hdma_adc1; DMA_HandleTypeDef hdma_adc2; /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_DMA_Init(void); static void MX_ADC1_Init(void); static void MX_DAC1_Init(void); static void MX_DAC2_Init(void); static void MX_TIM2_Init(void); static void MX_TIM3_Init(void); static void MX_ADC2_Init(void); static void MX_TIM1_Init(void); /* USER CODE BEGIN PFP */ static void start_adc(void); /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /** * @brief The application entry point. * @retval int */ int main(void) { /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_DMA_Init(); MX_ADC1_Init(); MX_DAC1_Init(); MX_DAC2_Init(); MX_TIM2_Init(); MX_TIM3_Init(); MX_ADC2_Init(); MX_TIM1_Init(); /* USER CODE BEGIN 2 */ start_adc(); dynamic_smooth_init(&dynamic_smooth_a, 0.05f, 0.5f); adsr_structinit(&OP1.ADSR); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { loop(); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { LL_FLASH_SetLatency(LL_FLASH_LATENCY_2); if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_2) { Error_Handler(); } LL_RCC_HSI_Enable(); /* Wait till HSI is ready */ while (LL_RCC_HSI_IsReady() != 1) { } LL_RCC_HSI_SetCalibTrimming(16); LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_16); LL_RCC_PLL_Enable(); /* Wait till PLL is ready */ while (LL_RCC_PLL_IsReady() != 1) { } LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2); LL_RCC_SetAPB2Prescaler(LL_RCC_APB1_DIV_1); LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); /* Wait till System clock is ready */ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) { } LL_SetSystemCoreClock(64000000); /* Update the time base */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { Error_Handler(); }; LL_RCC_SetTIMClockSource(LL_RCC_TIM1_CLKSOURCE_PCLK2); LL_RCC_SetADCClockSource(LL_RCC_ADC12_CLKSRC_PLL_DIV_1); } /** * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = { 0 }; ADC_ChannelConfTypeDef sConfig = { 0 }; /* USER CODE BEGIN ADC1_Init 1 */ //#define BEANS_12 /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; hadc1.Init.Resolution = ADC_RESOLUTION_12B; hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.NbrOfConversion = 7; hadc1.Init.DMAContinuousRequests = ENABLE; hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; hadc1.Init.LowPowerAutoWait = DISABLE; hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; if (HAL_ADC_Init(&hadc1) != HAL_OK) { Error_Handler(); } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.SamplingTime = ADC_SAMPLETIME_601CYCLES_5; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; sConfig.Rank = ADC_REGULAR_RANK_2; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; sConfig.Rank = ADC_REGULAR_RANK_3; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; sConfig.Rank = ADC_REGULAR_RANK_4; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; sConfig.Rank = ADC_REGULAR_RANK_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_12; sConfig.Rank = ADC_REGULAR_RANK_6; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; sConfig.Rank = ADC_REGULAR_RANK_7; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } /** * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = { 0 }; /* USER CODE BEGIN ADC2_Init 1 */ /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; hadc2.Init.Resolution = ADC_RESOLUTION_12B; hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; hadc2.Init.ContinuousConvMode = DISABLE; hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_TRGO; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.NbrOfConversion = 1; hadc2.Init.DMAContinuousRequests = ENABLE; hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; hadc2.Init.LowPowerAutoWait = DISABLE; hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; if (HAL_ADC_Init(&hadc2) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_2; sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.SamplingTime = ADC_SAMPLETIME_601CYCLES_5; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } /** * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ LL_DAC_InitTypeDef DAC_InitStruct = { 0 }; LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; /* Peripheral clock enable */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC1); LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 */ GPIO_InitStruct.Pin = LL_GPIO_PIN_4; GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; LL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ /** DAC channel OUT1 config */ DAC_InitStruct.TriggerSource = LL_DAC_TRIG_SOFTWARE; DAC_InitStruct.WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; DAC_InitStruct.OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE; LL_DAC_Init(DAC1, LL_DAC_CHANNEL_1, &DAC_InitStruct); LL_SYSCFG_SetRemapTrigger_DAC(LL_SYSCFG_DAC1_TRIG5_RMP_NO); LL_DAC_DisableTrigger(DAC1, LL_DAC_CHANNEL_1); /* USER CODE BEGIN DAC1_Init 2 */ LL_DAC_Enable(DAC1, LL_DAC_CHANNEL_1); /* USER CODE END DAC1_Init 2 */ } /** * @brief DAC2 Initialization Function * @param None * @retval None */ static void MX_DAC2_Init(void) { /* USER CODE BEGIN DAC2_Init 0 */ /* USER CODE END DAC2_Init 0 */ LL_DAC_InitTypeDef DAC_InitStruct = { 0 }; LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; /* Peripheral clock enable */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC2); LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); /**DAC2 GPIO Configuration PA6 ------> DAC2_OUT1 */ GPIO_InitStruct.Pin = LL_GPIO_PIN_6; GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; LL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN DAC2_Init 1 */ /* USER CODE END DAC2_Init 1 */ /** DAC channel OUT1 config */ DAC_InitStruct.TriggerSource = LL_DAC_TRIG_SOFTWARE; DAC_InitStruct.WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; DAC_InitStruct.OutputBuffer = LL_DAC_OUTPUT_SWITCH_ENABLE; LL_DAC_Init(DAC2, LL_DAC_CHANNEL_1, &DAC_InitStruct); LL_DAC_DisableTrigger(DAC2, LL_DAC_CHANNEL_1); /* USER CODE BEGIN DAC2_Init 2 */ LL_DAC_Enable(DAC2, LL_DAC_CHANNEL_1); /* USER CODE END DAC2_Init 2 */ } /** * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ LL_TIM_InitTypeDef TIM_InitStruct = { 0 }; /* Peripheral clock enable */ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1); /* TIM1 interrupt Init */ NVIC_SetPriority(TIM1_UP_TIM16_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ TIM_InitStruct.Prescaler = 0; TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct.Autoreload = 4800; TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; TIM_InitStruct.RepetitionCounter = 0; LL_TIM_Init(TIM1, &TIM_InitStruct); LL_TIM_DisableARRPreload(TIM1); LL_TIM_SetClockSource(TIM1, LL_TIM_CLOCKSOURCE_INTERNAL); LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_UPDATE); LL_TIM_SetTriggerOutput2(TIM1, LL_TIM_TRGO2_RESET); LL_TIM_DisableMasterSlaveMode(TIM1); /* USER CODE BEGIN TIM1_Init 2 */ LL_TIM_EnableIT_UPDATE(TIM1); LL_TIM_EnableCounter(TIM1); /* USER CODE END TIM1_Init 2 */ } /** * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ LL_TIM_InitTypeDef TIM_InitStruct = { 0 }; /* Peripheral clock enable */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); /* TIM2 interrupt Init */ NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_EnableIRQ(TIM2_IRQn); /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ TIM_InitStruct.Prescaler = 0; TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct.Autoreload = 1600; TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; LL_TIM_Init(TIM2, &TIM_InitStruct); LL_TIM_EnableARRPreload(TIM2); LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL); LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_UPDATE); LL_TIM_DisableMasterSlaveMode(TIM2); /* USER CODE BEGIN TIM2_Init 2 */ LL_TIM_EnableIT_UPDATE(TIM2); LL_TIM_EnableCounter(TIM2); NVIC_DisableIRQ(TIM2_IRQn); NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_EnableIRQ(TIM2_IRQn); /* USER CODE END TIM2_Init 2 */ } /** * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ LL_TIM_InitTypeDef TIM_InitStruct = { 0 }; /* Peripheral clock enable */ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3); /* TIM3 interrupt Init */ NVIC_SetPriority(TIM3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0)); NVIC_EnableIRQ(TIM3_IRQn); /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ TIM_InitStruct.Prescaler = 0; TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct.Autoreload = 12800; TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; LL_TIM_Init(TIM3, &TIM_InitStruct); LL_TIM_EnableARRPreload(TIM3); LL_TIM_SetClockSource(TIM3, LL_TIM_CLOCKSOURCE_INTERNAL); LL_TIM_SetTriggerOutput(TIM3, LL_TIM_TRGO_UPDATE); LL_TIM_DisableMasterSlaveMode(TIM3); /* USER CODE BEGIN TIM3_Init 2 */ NVIC_DisableIRQ(TIM3_IRQn); NVIC_SetPriority(TIM3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 2)); NVIC_EnableIRQ(TIM3_IRQn); LL_TIM_EnableIT_UPDATE(TIM3); LL_TIM_EnableCounter(TIM3); /* USER CODE END TIM3_Init 2 */ } /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); } /** * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; /* GPIO Ports Clock Enable */ LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOA); LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); /**/ GPIO_InitStruct.Pin = LL_GPIO_PIN_7; GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; LL_GPIO_Init(GPIOA, &GPIO_InitStruct); } /* USER CODE BEGIN 4 */ void start_adc() { HAL_ADC_Start_DMA(&hadc1, (uint32_t*) adc_data, NUM_ADC_CHANNELS); HAL_ADC_Start_DMA(&hadc2, (uint32_t*) voct_data, 1); LL_TIM_EnableCounter(TIM3); LL_TIM_EnableCounter(TIM1); } /* USER CODE END 4 */ /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. * @param file: pointer to the source file name * @param line: assert_param error line source number * @retval None */ void assert_failed(char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/noise.c ================================================ /* * noise.c * * Created on: Apr 3, 2020 * Author: SUPER */ #include "noise.h" #include "main.h" uint32_t noise_m_z = 362436069; uint32_t noise_m_w = 521288629; uint32_t noise(void) { noise_m_z = 36969 * (noise_m_z & 65535) + (noise_m_z >> 16); noise_m_w = 18000 * (noise_m_w & 65535) + (noise_m_w >> 16); return (noise_m_z << 16) + noise_m_w; } ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/stm32f3xx_hal_msp.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * File Name : stm32f3xx_hal_msp.c * Description : This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention * *

© Copyright (c) 2020 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern DMA_HandleTypeDef hdma_adc1; extern DMA_HandleTypeDef hdma_adc2; /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN Macro */ /* USER CODE END Macro */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* External functions --------------------------------------------------------*/ /* USER CODE BEGIN ExternalFunctions */ /* USER CODE END ExternalFunctions */ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE(); /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0; /** * @brief ADC MSP Initialization * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hadc->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; if(HAL_RCC_ADC12_CLK_ENABLED==1){ __HAL_RCC_ADC12_CLK_ENABLE(); } __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /**ADC1 GPIO Configuration PA0 ------> ADC1_IN1 PA1 ------> ADC1_IN2 PA2 ------> ADC1_IN3 PA3 ------> ADC1_IN4 PB0 ------> ADC1_IN11 PB1 ------> ADC1_IN12 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel1; hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_adc1.Init.Mode = DMA_CIRCULAR; hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) { Error_Handler(); } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } else if(hadc->Instance==ADC2) { /* USER CODE BEGIN ADC2_MspInit 0 */ /* USER CODE END ADC2_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; if(HAL_RCC_ADC12_CLK_ENABLED==1){ __HAL_RCC_ADC12_CLK_ENABLE(); } __HAL_RCC_GPIOA_CLK_ENABLE(); /**ADC2 GPIO Configuration PA5 ------> ADC2_IN2 */ GPIO_InitStruct.Pin = GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* ADC2 DMA Init */ /* ADC2 Init */ hdma_adc2.Instance = DMA1_Channel2; hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_adc2.Init.Mode = DMA_CIRCULAR; hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) { Error_Handler(); } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } /** * @brief ADC MSP De-Initialization * This function freeze the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) { if(hadc->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspDeInit 0 */ /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC12_CLK_ENABLED--; if(HAL_RCC_ADC12_CLK_ENABLED==0){ __HAL_RCC_ADC12_CLK_DISABLE(); } /**ADC1 GPIO Configuration PA0 ------> ADC1_IN1 PA1 ------> ADC1_IN2 PA2 ------> ADC1_IN3 PA3 ------> ADC1_IN4 PB0 ------> ADC1_IN11 PB1 ------> ADC1_IN12 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3); HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1); /* ADC1 DMA DeInit */ HAL_DMA_DeInit(hadc->DMA_Handle); /* USER CODE BEGIN ADC1_MspDeInit 1 */ /* USER CODE END ADC1_MspDeInit 1 */ } else if(hadc->Instance==ADC2) { /* USER CODE BEGIN ADC2_MspDeInit 0 */ /* USER CODE END ADC2_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC12_CLK_ENABLED--; if(HAL_RCC_ADC12_CLK_ENABLED==0){ __HAL_RCC_ADC12_CLK_DISABLE(); } /**ADC2 GPIO Configuration PA5 ------> ADC2_IN2 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); /* ADC2 DMA DeInit */ HAL_DMA_DeInit(hadc->DMA_Handle); /* USER CODE BEGIN ADC2_MspDeInit 1 */ /* USER CODE END ADC2_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/stm32f3xx_it.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32f3xx_it.c * @brief Interrupt Service Routines. ****************************************************************************** * @attention * *

© Copyright (c) 2020 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "stm32f3xx_it.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ extern DMA_HandleTypeDef hdma_adc1; extern DMA_HandleTypeDef hdma_adc2; /* USER CODE BEGIN EV */ /* USER CODE END EV */ /******************************************************************************/ /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_HardFault_IRQn 0 */ /* USER CODE END W1_HardFault_IRQn 0 */ } } /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ /* USER CODE END W1_MemoryManagement_IRQn 0 */ } } /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_BusFault_IRQn 0 */ /* USER CODE END W1_BusFault_IRQn 0 */ } } /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ /* USER CODE END W1_UsageFault_IRQn 0 */ } } /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { /* USER CODE BEGIN SVCall_IRQn 0 */ /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { /* USER CODE BEGIN DebugMonitor_IRQn 0 */ /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { /* USER CODE BEGIN PendSV_IRQn 0 */ /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); /* USER CODE BEGIN SysTick_IRQn 1 */ //GPIOA->ODR ^= LL_GPIO_PIN_8; /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ /* STM32F3xx Peripheral Interrupt Handlers */ /* Add here the Interrupt Handlers for the used peripherals. */ /* For the available peripheral interrupt handler names, */ /* please refer to the startup file (startup_stm32f3xx.s). */ /******************************************************************************/ /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } /** * @brief This function handles TIM1 update and TIM16 interrupts. */ void TIM1_UP_TIM16_IRQHandler(void) { /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */ if (LL_TIM_IsActiveFlag_UPDATE(TIM1)) { LL_TIM_ClearFlag_UPDATE(TIM1); } /* USER CODE END TIM1_UP_TIM16_IRQn 0 */ /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */ /* USER CODE END TIM1_UP_TIM16_IRQn 1 */ } /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ /* USER CODE BEGIN TIM2_IRQn 1 */ if (LL_TIM_IsActiveFlag_UPDATE(TIM2)) { LL_TIM_ClearFlag_UPDATE(TIM2); main_2OP_loop(); } /* USER CODE END TIM2_IRQn 1 */ } /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ /* USER CODE BEGIN TIM3_IRQn 1 */ if (LL_TIM_IsActiveFlag_UPDATE(TIM3)) { LL_TIM_ClearFlag_UPDATE(TIM3); for (uint8_t i = 0; i < (NUM_ADC_CHANNELS - 1); i++) { adc_data_10b[i] = adc_data[i] >> 2; } #ifdef SMOOTH_ATTACK run_linear_a_expo_r(&OP1.ADSR); #else run_ar(&OP1.ADSR); #endif check_gate(); set_adsr_parameters(&OP1.ADSR); } /* USER CODE END TIM3_IRQn 1 */ } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/syscalls.c ================================================ /** ***************************************************************************** ** ** File : syscalls.c ** ** Author : Auto-generated by STM32CubeIDE ** ** Abstract : STM32CubeIDE Minimal System calls file ** ** For more information about which c-functions ** need which of these lowlevel functions ** please consult the Newlib libc-manual ** ** Environment : STM32CubeIDE MCU ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ***************************************************************************** ** **

© COPYRIGHT(c) 2018 STMicroelectronics

** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** 1. Redistributions of source code must retain the above copyright notice, ** this list of conditions and the following disclaimer. ** 2. Redistributions in binary form must reproduce the above copyright notice, ** this list of conditions and the following disclaimer in the documentation ** and/or other materials provided with the distribution. ** 3. Neither the name of STMicroelectronics nor the names of its contributors ** may be used to endorse or promote products derived from this software ** without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** ***************************************************************************** */ /* Includes */ #include #include #include #include #include #include #include #include /* Variables */ //#undef errno extern int errno; extern int __io_putchar(int ch) __attribute__((weak)); extern int __io_getchar(void) __attribute__((weak)); register char * stack_ptr asm("sp"); char *__env[1] = { 0 }; char **environ = __env; /* Functions */ void initialise_monitor_handles() { } int _getpid(void) { return 1; } int _kill(int pid, int sig) { errno = EINVAL; return -1; } void _exit (int status) { _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) { *ptr++ = __io_getchar(); } return len; } __attribute__((weak)) int _write(int file, char *ptr, int len) { int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) { __io_putchar(*ptr++); } return len; } int _close(int file) { return -1; } int _fstat(int file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } int _isatty(int file) { return 1; } int _lseek(int file, int ptr, int dir) { return 0; } int _open(char *path, int flags, ...) { /* Pretend like we always fail */ return -1; } int _wait(int *status) { errno = ECHILD; return -1; } int _unlink(char *name) { errno = ENOENT; return -1; } int _times(struct tms *buf) { return -1; } int _stat(char *file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } int _link(char *old, char *new) { errno = EMLINK; return -1; } int _fork(void) { errno = EAGAIN; return -1; } int _execve(char *name, char **argv, char **env) { errno = ENOMEM; return -1; } ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/sysmem.c ================================================ /** ***************************************************************************** ** ** File : sysmem.c ** ** Author : Auto-generated by STM32CubeIDE ** ** Abstract : STM32CubeIDE Minimal System Memory calls file ** ** For more information about which c-functions ** need which of these lowlevel functions ** please consult the Newlib libc-manual ** ** Environment : STM32CubeIDE MCU ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ***************************************************************************** ** **

© COPYRIGHT(c) 2018 STMicroelectronics

** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** 1. Redistributions of source code must retain the above copyright notice, ** this list of conditions and the following disclaimer. ** 2. Redistributions in binary form must reproduce the above copyright notice, ** this list of conditions and the following disclaimer in the documentation ** and/or other materials provided with the distribution. ** 3. Neither the name of STMicroelectronics nor the names of its contributors ** may be used to endorse or promote products derived from this software ** without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** ***************************************************************************** */ /* Includes */ #include #include /* Variables */ extern int errno; register char * stack_ptr asm("sp"); /* Functions */ /** _sbrk Increase program data space. Malloc and related functions depend on this **/ caddr_t _sbrk(int incr) { extern char end asm("end"); static char *heap_end; char *prev_heap_end; if (heap_end == 0) heap_end = &end; prev_heap_end = heap_end; if (heap_end + incr > stack_ptr) { errno = ENOMEM; return (caddr_t) -1; } heap_end += incr; return (caddr_t) prev_heap_end; } ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Src/system_stm32f3xx.c ================================================ /** ****************************************************************************** * @file system_stm32f3xx.c * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f3xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the HSI (8 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to * configure the system clock before to branch to main program. * * 3. This file configures the system clock as follows: *============================================================================= * Supported STM32F3xx device *----------------------------------------------------------------------------- * System Clock source | HSI *----------------------------------------------------------------------------- * SYSCLK(Hz) | 8000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 8000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB2 Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 1 *----------------------------------------------------------------------------- * USB Clock | DISABLE *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f3xx_system * @{ */ /** @addtogroup STM32F3xx_System_Private_Includes * @{ */ #include "stm32f3xx.h" /** * @} */ /** @addtogroup STM32F3xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F3xx_System_Private_Defines * @{ */ #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /** * @} */ /** @addtogroup STM32F3xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32F3xx_System_Private_Variables * @{ */ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ uint32_t SystemCoreClock = 8000000; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} */ /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes * @{ */ /** * @} */ /** @addtogroup STM32F3xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * @param None * @retval None */ void SystemInit(void) { /* FPU settings --------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * * @param None * @retval None */ void SystemCoreClockUpdate (void) { uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; pllmull = ( pllmull >> 18) + 2; #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; } else { /* HSI oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; } #else if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; } else { predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ break; default: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Core/Startup/startup_stm32f334k8tx.s ================================================ /** ****************************************************************************** * @file startup_stm32f334x8.s * @author MCD Application Team * @brief STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address, * - Configure the clock system * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main LoopForever: b LoopForever .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex-M4. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler .word PVD_IRQHandler .word TAMP_STAMP_IRQHandler .word RTC_WKUP_IRQHandler .word FLASH_IRQHandler .word RCC_IRQHandler .word EXTI0_IRQHandler .word EXTI1_IRQHandler .word EXTI2_TSC_IRQHandler .word EXTI3_IRQHandler .word EXTI4_IRQHandler .word DMA1_Channel1_IRQHandler .word DMA1_Channel2_IRQHandler .word DMA1_Channel3_IRQHandler .word DMA1_Channel4_IRQHandler .word DMA1_Channel5_IRQHandler .word DMA1_Channel6_IRQHandler .word DMA1_Channel7_IRQHandler .word ADC1_2_IRQHandler .word CAN_TX_IRQHandler .word CAN_RX0_IRQHandler .word CAN_RX1_IRQHandler .word CAN_SCE_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_TIM15_IRQHandler .word TIM1_UP_TIM16_IRQHandler .word TIM1_TRG_COM_TIM17_IRQHandler .word TIM1_CC_IRQHandler .word TIM2_IRQHandler .word TIM3_IRQHandler .word 0 .word I2C1_EV_IRQHandler .word I2C1_ER_IRQHandler .word 0 .word 0 .word SPI1_IRQHandler .word 0 .word USART1_IRQHandler .word USART2_IRQHandler .word USART3_IRQHandler .word EXTI15_10_IRQHandler .word RTC_Alarm_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word TIM6_DAC1_IRQHandler .word TIM7_DAC2_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word COMP2_IRQHandler .word COMP4_6_IRQHandler .word 0 .word HRTIM1_Master_IRQHandler .word HRTIM1_TIMA_IRQHandler .word HRTIM1_TIMB_IRQHandler .word HRTIM1_TIMC_IRQHandler .word HRTIM1_TIMD_IRQHandler .word HRTIM1_TIME_IRQHandler .word HRTIM1_FLT_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word FPU_IRQHandler /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_TSC_IRQHandler .thumb_set EXTI2_TSC_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler .weak DMA1_Channel7_IRQHandler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler .weak CAN_TX_IRQHandler .thumb_set CAN_TX_IRQHandler,Default_Handler .weak CAN_RX0_IRQHandler .thumb_set CAN_RX0_IRQHandler,Default_Handler .weak CAN_RX1_IRQHandler .thumb_set CAN_RX1_IRQHandler,Default_Handler .weak CAN_SCE_IRQHandler .thumb_set CAN_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM15_IRQHandler .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler .weak TIM1_UP_TIM16_IRQHandler .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM17_IRQHandler .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak TIM6_DAC1_IRQHandler .thumb_set TIM6_DAC1_IRQHandler,Default_Handler .weak TIM7_DAC2_IRQHandler .thumb_set TIM7_DAC2_IRQHandler,Default_Handler .weak COMP2_IRQHandler .thumb_set COMP2_IRQHandler,Default_Handler .weak COMP4_6_IRQHandler .thumb_set COMP4_6_IRQHandler,Default_Handler .weak HRTIM1_Master_IRQHandler .thumb_set HRTIM1_Master_IRQHandler,Default_Handler .weak HRTIM1_TIMA_IRQHandler .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler .weak HRTIM1_TIMB_IRQHandler .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler .weak HRTIM1_TIMC_IRQHandler .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler .weak HRTIM1_TIMD_IRQHandler .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler .weak HRTIM1_TIME_IRQHandler .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler .weak HRTIM1_FLT_IRQHandler .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/2OPFM_2020.hex ================================================ :020000040800F2 :100000000030002099140008B5130008B913000847 :10001000BD130008C1130008C5130008000000004C :10002000000000000000000000000000C9130008EC :10003000CD13000800000000D1130008D5130008FC :10004000E9140008E9140008E9140008E91400089C :10005000E9140008E9140008E9140008E91400088C :10006000E9140008E9140008E9140008D91300088D :10007000E5130008E9140008E9140008E914000871 :10008000E9140008E9140008E9140008E91400085C :10009000E9140008E9140008E9140008E91400084C :1000A000E9140008F1130008E9140008E914000835 :1000B000051400081D14000800000000E9140008E1 :1000C000E91400080000000000000000E914000826 :1000D00000000000E9140008E9140008E914000811 :1000E000E9140008E9140008000000000000000006 :1000F0000000000000000000000000000000000000 :1001000000000000000000000000000000000000EF :100110000000000000000000E9140008E9140008D5 :1001200000000000000000000000000000000000CF :1001300000000000000000000000000000000000BF :10014000E9140008E914000800000000E9140008A0 :10015000E9140008E9140008E9140008E91400088B :10016000E9140008E9140008000000000000000085 :10017000000000000000000000000000000000007F :0801800000000000E914000872 :1001880010B5054C237833B9044B13B10448AFF3C9 :1001980000800123237010BD0C080020000000001F :1001A800B824000808B5034B1BB103490348AFF353 :1001B800008008BD0000000010080020B8240008D6 :1001C80081F0004102E000BF83F0004330B54FEA00 :1001D80041044FEA430594EA050F08BF90EA020F6D :1001E8001FBF54EA000C55EA020C7FEA645C7FEA00 :1001F800655C00F0E2804FEA5454D4EB5555B8BF23 :100208006D420CDD2C4480EA020281EA030382EA93 :10021800000083EA010180EA020281EA0303362D25 :1002280088BF30BD11F0004F4FEA01314FF4801CF8 :100238004CEA113102D0404261EB410113F0004F0A :100248004FEA03334CEA133302D0524263EB4303C1 :1002580094EA050F00F0A780A4F10104D5F1200E5F :100268000DDB02FA0EFC22FA05F2801841F10001BA :1002780003FA0EF2801843FA05F359410EE0A5F18E :1002880020050EF1200E012A03FA0EFC28BF4CF0BF :10029800020C43FA05F3C01851EBE37101F0004575 :1002A80007D54FF0000EDCF1000C7EEB00006EEB82 :1002B8000101B1F5801F1BD3B1F5001F0CD349080C :1002C8005FEA30004FEA3C0C04F101044FEA445263 :1002D80012F5800F80F09A80BCF1004F08BF5FEAEA :1002E800500C50F1000041EB045141EA050130BDCA :1002F8005FEA4C0C404141EB0101013C28BFB1F5DC :10030800801FE9D291F0000F04BF01460020B1FA26 :1003180081F308BF2033A3F10B03B3F120020CDAF9 :100328000C3208DD02F1140CC2F10C0201FA0CF0D7 :1003380021FA02F10CE002F11402D8BFC2F1200C3C :1003480001FA02F120FA0CFCDCBF41EA0C019040F2 :10035800E41AA2BF01EB0451294330BD6FEA04043B :100368001F3C1CDA0C340EDC04F11404C4F1200226 :1003780020FA04F001FA02F340EA030021FA04F338 :1003880045EA030130BDC4F10C04C4F1200220FA8F :1003980002F001FA04F340EA0300294630BD21FACD :1003A80004F0294630BD94F0000F83F4801306BF93 :1003B80081F480110134013D4EE77FEA645C18BF87 :1003C8007FEA655C29D094EA050F08BF90EA020F1E :1003D80005D054EA000C04BF1946104630BD91EA16 :1003E800030F1EBF0021002030BD5FEA545C05D119 :1003F8004000494128BF41F0004130BD14F5800458 :100408003CBF01F5801130BD01F0004545F0FE41CB :1004180041F470014FF0000030BD7FEA645C1ABF00 :10042800194610467FEA655C1CBF0B46024650EA37 :10043800013406BF52EA033591EA030F41F4002163 :1004480030BD00BF90F0000F04BF0021704730B5E9 :100458004FF4806404F132044FF000054FF00001BE :1004680050E700BF90F0000F04BF0021704730B57F :100478004FF4806404F1320410F0004548BF404254 :100488004FF000013EE700BF42004FEAE2014FEAA9 :1004980031014FEA02701FBF12F07F4393F07F4F84 :1004A80081F06051704732F07F4208BF704793F087 :1004B8007F4F04BF41F40021704730B54FF460749A :1004C80001F0004521F000411CE700BF50EA01029D :1004D80008BF704730B54FF000050AE050EA010246 :1004E80008BF704730B511F0004502D5404261EBB6 :1004F80041014FF4806404F132045FEA915C3FF4F7 :10050800D8AE4FF003025FEADC0C18BF03325FEA93 :10051800DC0C18BF033202EBDC02C2F1200300FA44 :1005280003FC20FA02F001FA03FE40EA0E0021FA69 :1005380002F11444BDE600BF4FF0FF3C06E000BFE7 :100548004FF0010C02E000BF4FF0010C4DF804CD54 :100558004FEA410C7FEA6C5C4FEA430C18BF7FEA14 :100568006C5C1BD001B050EA410C0CBF52EA430C42 :1005780091EA030F02BF90EA020F0020704710F1C2 :10058800000F91EA030F58BF994208BF90422CBF51 :10059800D8176FEAE37040F0010070474FEA410C4A :1005A8007FEA6C5C02D150EA013C07D14FEA430C68 :1005B8007FEA6C5CD6D152EA033CD3D05DF8040BD9 :1005C800704700BF8446104662468C46194663460B :1005D80000E000BF01B5FFF7B7FF002848BF10F1E2 :1005E800000F01BD4DF808EDFFF7F4FF0CBF012027 :1005F80000205DF808FB00BF4DF808EDFFF7EAFFA3 :1006080034BF012000205DF808FB00BF4DF808ED5D :10061800FFF7E0FF94BF012000205DF808FB00BF52 :100628004DF808EDFFF7CEFF94BF012000205DF8DC :1006380008FB00BF4DF808EDFFF7C4FF34BF0120E9 :1006480000205DF808FB00BF002310B44FF07E5275 :10065800032400210260036243628362C36204715F :1006680083605DF8044BC3608361C26180F8301019 :10067800704700BF0000000090ED007ADFED367A89 :1006880010B5B4EEE77AF1EE10FA44BF002380F813 :10069800303003790446DBB9D0ED007ADFED2F6AFC :1006A8009FED2F7A77EEA67AC0ED007AD0ED087A22 :1006B800D0ED046A77EEA67AC0ED027AD0ED007A22 :1006C800F4EEC77AF1EE10FA01DD0223037110BDD2 :1006D8000379022B2ED0D4ED027AD4ED036A9FED74 :1006E8001F7A77EEA67A67EE877AC4ED067AA06954 :1006F800FFF7CAFE16A3D3E90023FFF79BFF08B153 :10070800184BA361D4ED067AF5EEC07A0023F1EE1A :1007180010FA48BFA36194ED077A94ED006AD4ED0E :10072800066AD4ED007A37EE467AE7EE267AC4ED0B :10073800007A10BDD0ED0B7A90ED057A77EE877AC6 :100748000023C0ED027AC361C5E700BFAFF30080A4 :10075800AE47E17A14AEEF3F0AD7233CCDCCCC3D6F :100768003333733FA4707D3F10B580214FF0904024 :1007780001F046FD084A09491478B0FA80F320438D :100788005B0910F0FF000B7003D10549087781F869 :100798004800137010BD00BFAB0800208C08002073 :1007A8003C0800201A4A1B49538912889FED1A5A9F :1007B80031F812C0DFED195A9FED196A03F2EF13F1 :1007C8009B1A1BB283F30A03164A31F81330D2ED91 :1007D800006A154907EE10CA07EE903AB8EEC77AD4 :1007E800F8EEE77A37EE667A77EE857AE7EE256AED :1007F80010B427EE867A0D4C0D4BC460C1ED007A1B :1008080003625DF8044BC2ED006A80ED0B7A704715 :10081800B4080020000000200000C8420AD7A33C0A :10082800ACC5273790080020AC0800206F12033AA7 :100838000000E040F8B5954C954A6388D2ED007AFF :100848009FED945ADFED945A21899FED946AC3F580 :10085800E07307EE103AB8EEC77AF0EE674AD7EEC3 :10086800054A06EE901AE4EEA57AF8EEE66AB0EECE :10087800677AA6EE867AC2ED007AB5EEC07AF1EE16 :1008880010FA00F1F880864E86ED007A854AE388F2 :1008980012888549854D91ED000AD5ED006A9FEDD6 :1008A800846A8448844FC3F57F73A2F500620333DA :1008B80007EE102A07EE903AB8EEC77AF8EEE77A14 :1008C80037EE407A77EEE67AA7EE060AE7EE866A12 :1008D80081ED000AC5ED006A00F03EF9774B784AD1 :1008E80093ED007AA38892ED006AD7ED005A95ED52 :1008F800005ADFED743A9FED744ADFED674AB4F8A9 :100908000AC0724CDFED726ADFED727A7249734881 :10091800B5EE003A27EE037AB0EE463A27EE000A23 :1009280007EE103AB8EEC77A35EE655A97EE233AD5 :100938006B4B35EE005AA3EE246ABCF57A7FE5EEE0 :10094800045AB0EE467ABCEEE56A83ED000A16EE6C :10095800103AC3F3090367EE266A34F8133082EDC0 :10096800007A06EE103AB8EE466AC7ED005A66EE0F :10097800866A26EE277A66EEA77ABCEEC77AFCEE80 :10098800E77A17EE105A17EE904AC0ED037AD1EDC8 :10099800057A81ED037AB8EEE77AD0ED057A81ED34 :1009A800026A96ED006A0F690669C0ED026AF8EE00 :1009B800E77A27EE067A67EE867ABDEEC77AFDEE0D :1009C800E77A88BF4FF07E5317EE102A88BF8B61F5 :1009D8003D4417EE903A344402EB9552414ED1ED26 :1009E800065AD1ED066A91ED065A046103EB945359 :1009F800C2F30902C3F3090336F8122036F813309C :100A0800394E0D61A2F5004207EE102AA3F5004306 :100A180007EE903AB8EEC77AF8EEE77A66EE856A9E :100A280027EE257A67EEA67ABDEEC77AFDEEE77A5D :100A380017EE102A17EE903A5411DD10B4F5006F36 :100A480081ED007A3460C0ED007A4D6109DB274BF7 :100A580040F2FF721A6040F6FF70BDE8F84000F0FF :100A680059B8234B9C420ADA204A01201360BDE89A :100A7800F84000F04FB80A4E0021316006E71B4BE2 :100A880004F500601C6080B2E7E700BFB4080020EE :100A9800340800200000003B0AD7233C0AD7233A39 :100AA800380800205C0B0020040B0020940800206C :100AB800CDCC4C3DDC0A0020A0080020A408002072 :100AC800C00800200210003A0AD7A33D0000002009 :100AD80000000042ACC527473C0800200C0B002052 :100AE8002C080020D0240008000B002098080020C3 :100AF80001F8FFFF4FF4702393FAA3F304498B68BE :100B080023F47F6323F00F0318438860704700BF06 :100B1800009800404FF4702393FAA3F304498B68BC :100B280023F47F6323F00F0318438860704700BFE6 :100B380000740040F1EE007A60EEA70A0023054A2F :100B48000260C0ED010A8360C36003614361836191 :100B5800C361704776E96E3790ED027AD0ED037A7B :100B680090ED015AD0ED006A80ED047A37EEC76A3D :100B7800F7EE005AF0EEC64AE4EE856A30EE470A10 :100B8800F4EEE56AF1EE10FA88BFF0EE656AA0EEC1 :100B9800267AC0ED057A77EE675A80ED066AE5EEAB :100BA800A67A80ED027AB0EE670AC0ED037A704744 :100BB80038B540F2FF70FFF79DFF1149114B0A88C5 :100BC80011481C8885899FED117A114840F6E44345 :100BD80003FB02F2B2FBF5F295B207EE905AF8EE7B :100BE800E77A02800B4D0C480C4A0988296067EEA9 :100BF800877A03FB04F31B130380C2ED007A38BD28 :100C0800BAF7FF1F5C0B0020C40800200AE09E39D9 :100C18008E080020FC0A002030080020A4080020CC :100C280029492A4B0A6822F0070242F0020210B54D :100C38000A600A681A6842F001021A601A68920784 :100C4800FCD51968214A21F0F80141F080011960AA :100C5800596821F4741141F460115960D96A21F07E :100C68000F01D962196841F08071196013689B01FE :100C7800FCD55368154C23F0F0035360536823F4F4 :100C8800E06343F480635360536823F46053536014 :100C9800536823F0030343F002035360636803F0CF :100CA8000C03082BFAD10A4801F0D8FB002000F009 :100CB80019FC236B23F480732363E36A23F4F8732A :100CC80043F48073E36210BD00200240001002402C :100CD8000090D0032DE98048002495B000F026FC50 :100CE800FFF79EFFCDE91244CDE91044C94DCA4E25 :100CF8006A69DFF83CB3DFF83CA342F400326A616A :100D08006A6902F400320892089A6A6942F48022F9 :100D18006A616A6902F48022012709920EA94FF0DC :100D280080084FF000094FF09040CDE90E89099AEC :100D3800129701F09BFA6A693A436A616A693A4014 :100D48000792214622460B20DDF81CC001F05AF814 :100D58000B2001F08FF8224621460C2001F052F8B2 :100D68000C2001F087F84FF480624FF480704FF048 :100D7800070C4FF0A0413483F262B062082230467B :100D8800C6F81CC07261C6E90347C6E9014486F883 :100D9800204086F8307074633160CDE90E44CDE9A7 :100DA8001044CDE91244CDE90B440A944FF00108F0 :100DB80000F080FC4FF001090AA930460A9400F0BF :100DC8009BFFCDE90E894FF007084FF00009CDE9E8 :100DD80010890EA930464FF000084FF00009CDE900 :100DE800128900F0F1FD4FF002080EA930464FF0CD :100DF8000209CDE90E8900F0E7FD4FF003080EA9BE :100E080030464FF00309CDE90E8900F0DDFD4FF0C3 :100E180004080EA930464FF00409CDE90E8900F008 :100E2800D3FD4FF00B080EA930464FF00509CDE968 :100E38000E8900F0C9FD4FF00C080EA930464FF09E :100E48000609CDE90E89072700F0BEFD0EA9304638 :100E58001226CDE90E6700F0B7FDCDE91244CDE9C1 :100E68000A44CDE90C44CDE91044EA6942F0005245 :100E7800EA61EA6902F000520592059A6A6942F449 :100E880000326A616A69129402F4003206920EA96D :100E9800102603274FF09040CDE90E67069A5F4F62 :100EA80001F0E4F95E4B5F490D944FF038084FF0BC :100EB80000090AAA1846CDE90A8901F0A7F95A4992 :100EC800574B0A6822F400320A601A6822F00402BA :100ED8001A601A6842F001021A60CDE91244CDE99D :100EE8000A44CDE90C44CDE91044EB6943F0806332 :100EF800EB61EB6903F080630393039B6B6943F435 :100F080000336B616B69129403F400330493049803 :100F18000EA9402203234FF09040CDE90E2301F0A3 :100F2800A5F90AAA02233F490D935846CDE90A8933 :100F380001F06CF9DBF80030DFF8FC8023F00403E3 :100F4800CBF80030DBF8003043F00103CBF8003079 :100F5800CDE90E44CDE910441294EB6943F0010346 :100F6800EB61EB6903F001030A934FF080560A9B8B :100F7800DAF80C3087F81C434FF4C8633E600EA9BA :100F88004FF08040CDE91034ADF838400F9401F0AF :100F98001DFA4FF080431A6842F080021A609A687E :100FA80002EA08029A605A6822F0700242F02002AF :100FB8005A609A6822F080029A60DA6842F0010268 :100FC800DA601A6842F001021A60C7F88060BFF35D :100FD8004F8FBFF36F8FDAF80C3087F81C433E60F1 :100FE800CDE90E44CDE910441294EB690F4E43F05D :100FF8000203EB61EB6903F0020302934FF0005523 :10100800029BDAF80C3087F81D434FF448533D60D3 :101018000EA913E000100240B00B002000E100E030 :10102800007400400100100250000140000400401C :101038000098004000ED00E0F8BFFEFF3046CDE923 :101048001034ADF838400F9401F0C0F9336843F01C :1010580080033360B36803EA0803B360736823F05E :10106800700343F020037360B36823F08003B36018 :10107800C7F88050BFF34F8FBFF36F8FDAF80C209B :10108800DFF8B0915F4F604E604DC2F30222C2F1AB :101098000703111D042B28BF0423062988BFD41E6B :1010A8004FF0FF3202FA03F3DB43A24003F00203DE :1010B800D243A34002F0020213431B01DBB24FF0FC :1010C800005189F81D33C9F80010FB68504A43F0F5 :1010D8000103FB603B684FF4806443F001033B600D :1010E800F46200244FF001084FF4107104233046D5 :1010F8003483B16232607361CDE90E44CDE91044A6 :10110800CDE91244C6E90144C6E9034486F8204003 :101118007463C6F81C8086F8308000F0CBFA02228F :101128000123CDE90E2307220023CDE910230EA9C0 :10113800002200233046CDE9122300F045FCCDE91A :101148000E44CDE91044334B12949A69324842F464 :1011580000629A619B6903F4006301934FF0007386 :10116800019AC26889F819430EA9C9F800302846BF :101178004FF496531093ADF838400F9411948DF8AE :10118800484001F023F92B682449254823F08003BF :101198002B60AB6823F4A03323F00703AB606B68C4 :1011A80023F0700343F020036B606B6823F4700333 :1011B8006B60AB6823F08003AB60EB6843EA08031D :1011C800EB602B6843EA08032B60072200F078FBEA :1011D80014494246304600F073FB3B6812489FEDC5 :1011E800130A43EA08033B602B6843EA08032B60B1 :1011F800F6EE000AFFF79EFC0D48FFF725FAFFF709 :10120800D7FCFCE700040040600B0020002C0140E4 :10121800000100500010024000ED00E0C40800206A :10122800B00B00205C0B0020DC0A0020CDCC4C3D2C :101238005408002000E100E0704700BF0A4B9A699B :1012480042F001029A619A6982B002F001020092AA :10125800009ADA6942F08052DA61DB6903F0805360 :101268000193019B02B070470010024070B50268FC :101278008CB00023B2F1A04FCDE90633CDE9083395 :1012880004460A9338D0414B9A4201D00CB070BD45 :101298003F4A13680133012B136068D03D4B3E4D24 :1012A8005A6942F400325A615B6903F400330593CA :1012B80005980323202206A900264FF09040CDE987 :1012C8000623089600F0BCFE344B2B6080204FF4B8 :1012D80080714FF480622023E860C5E904126E60D3 :1012E800AE60EE612846AB6100F0ECFD002849D104 :1012F800A5636C620CB070BD254A13680133012BDD :10130800136029D0234B264D5A6942F400325A61A2 :101318005A6902F400320292029A5A6942F480220F :101328005A615B6903F4802303930F220323039913 :10133800002606A94FF09040CDE90623089600F054 :101348007FFE032303221748089606A9CDE9062342 :1013580000F076FE144BB8E70E4B5A6942F0805203 :101368005A615B6903F080530193019BCAE7094BFB :101378005A6942F080525A615B6903F080530493C2 :10138800049B8BE7FFF758FFB2E700BF000100504E :101398002808002000100240440C00201C000240D5 :1013A800000C00200004004808000240704700BFFD :1013B800FEE700BFFEE700BFFEE700BFFEE700BF95 :1013C800704700BF704700BF704700BF00F0C0B84B :1013D800014800F0EBBD00BF000C0020014800F000 :1013E800E5BD00BF440C0020034B1A69D20744BF77 :1013F8006FF001021A617047002C01404FF08043E2 :101408001A69D20700D470476FF001021A61FFF71A :1014180011BA00BF134B1A69D20721D5124A70B509 :10142800508816889588D4886FF0010119610F4B90 :10143800118952898008890892085880B608AD0831 :10144800A4080B481E809D80DC8019815A81FFF713 :1014580013F9FFF789F9BDE870400548FFF7A2B90D :10146800704700BF00040040C4080020B4080020F2 :1014780054080020054BD3F888204FF0006142F44F :101488007002C3F888209960704700BF00ED00E043 :10149800DFF834D0002103E00C4B5B584350043193 :1014A8000B480C4B42189A42F6D30B4A02E0002331 :1014B80042F8043B094B9A42F9D3FFF7DBFF00F0EF :1014C800D3FFFFF707FCFEE700300020D82C000808 :1014D800000000200C0800200C0800208C0C0020C4 :1014E800FEE7000038B50E4A0E4B12781B68054619 :1014F8004FF47A70B0FBF2F0B3FBF0F000F0C8FCE8 :1015080008B90F2D01D9012038BD044602462946E5 :101518004FF0FF3000F076FC034B20461D6038BDCD :10152800040800200008002008080020074A08B521 :10153800136843F010031360032000F04FFC0020F1 :10154800FFF7D0FFFFF77AFE002008BD0020024019 :10155800034A044B11681B780B441360704700BFA3 :10156800880C002004080020014B1868704700BF51 :10157800880C0020704700BF704700BF704700BF4D :10158800406A036C43F040030364436C43F0040374 :101598004364FFF7F3BF00BF406AFFF7EDBF00BF2A :1015A800436A1A6C12F0500F18D11A6C196842F479 :1015B80000721A64CA6812F4406F0CD15A7E52B98C :1015C8001A6C22F480721A641A6CD20403D41A6C4E :1015D80042F001021A641846FFF7CCBF9B6B1B6BE5 :1015E800184700BF026838B5936803F00303012B5E :1015F80001D0002038BD1168C907FAD5916801F0FB :101608000D010129044609D0026C42F0100202645F :10161800426C42F001021846626438BD93680321A7 :1016280043F0020393601160FFF79EFF05462368AD :101638009B68DB07DDD5FFF797FF401B0228F6D92B :10164800236C43F010032364636C43F00103636469 :10165800012038BD026838B5936803F00303012BF5 :10166800044620D09168124B194209D0236C43F0EC :1016780010032364636C43F001036364012038BDE5 :10168800936843F001039360FFF76EFF054604E09B :10169800FFF76AFF431B022BE8D823681B68DB07A8 :1016A800F6D5002038BD1368D907DBD50020F9E747 :1016B8003F00008070B582B000230193002800F03D :1016C8008F80036C13F01003044617D1056C002DAE :1016D80000F0898022689168CE0075D591688D00E8 :1016E80072D4216CC80600D463B1236C23F01203B2 :1016F80043F010030120236402B070BD036CD806C8 :10170800F3D42268906810F00400EED1216C674B86 :1017180021F4817141F0020121649168B2F1A04F76 :1017280001F0030118BF4FF0A043012900F0A98080 :10173800996801F00301012900F0A8805C496568F7 :101748008B6823F440332B438B60D4E90231666BFA :10175800657E0B4394F82010012E18BF4FF480507B :1017680043EA4533012943EA000300F08280A16A75 :10177800012902D0E06A01430B43916811F00C0F74 :101788000CD1D16821F4804121F00201D16094F894 :101798003010207E490041EA80310B43D568454925 :1017A800206929400B430128D3605AD0136B23F0DA :1017B8000F03136300206064236C23F0030343F0DA :1017C8000103236402B070BD236C23F0120343F0BD :1017D80010032364636C43F001036364236C84E7A0 :1017E800012002B070BDC0E91255456480F83C5034 :1017F800FFF73CFD22689368D90001D52B466AE7BC :101808002046FFF7EFFE226CD20603463FF562AF93 :1018180000287FF45FAF206C22682749274D0968AC :1018280020F4885020F0020040F002002064906804 :1018380020F040509060A5FB0101890C906801EBF5 :101848008101490040F08050906001910199002980 :101858003FF441AF01990139019101990029F9D16A :1018680039E7116BE36921F00F01013B0B43136367 :10187800A0E785B9616A013943EA414343F48033FB :1018880075E71168C9073FF560AF51E71B68DB07CB :101898003FF55BAF52E7216C21F0220141F02001B6 :1018A8002164616C41F00101616460E7000100504E :1018B8000003005007C0F0FF0008002083DE1B4330 :1018C80003682DE9F0479D6815F0040513D190F8D9 :1018D8003C30012B04460ED0DFF8E8A0012780F841 :1018E8003C70DAF8086016F01F0608D080F83C5003 :1018F8003846BDE8F08702273846BDE8F0878846B5 :101908009146FFF7A7FE0746002850D1236C2168AF :1019180023F4706323F0010343F480732364DAF83B :101928000830D8063BD0B1F1A04F38D0236C214AFB :1019380043F48013914223640AD14FF0A043DB683B :101948009B0105D5236C23F4405343F4805323644F :10195800236CA06B184A13F480531CBF636C23F0EC :10196800060363640026154B84F83C608262C362F8 :10197800134A02631C230B604B6843F010034B604F :10198800CE6846F001064B464246CE60403100F034 :10199800CBFA2268936843F004039360A8E7236CAA :1019A80023F480132364CB689A01D1D5CAE784F85D :1019B8003C609DE700010050A9150008A11500082A :1019C8008915000800030050F0B490F83C20CC685A :1019D80082B00346012A4FF00000019000F0C38056 :1019E8001A68012083F83C0095686D0736D448686A :1019F80004287DD800EB4000166B0D6840001F27B7 :101A0800874026EA070605FA00F03043106390681D :101A180010F00C0F35D1092D40F2938005EB4507E6 :101A280090698E681E3F4FF0070C0CFA07FC20EAFD :101A38000C00BE4030439061D1E90467D068C0F320 :101A4800C1004000013E07FA00F0032E00F21D819C :101A5800DFE816F00E00E400DA00D0001A6C42F05D :101A680020021A64002283F83C2002B0F0BC7047C0 :101A7800176E9C4E3E4046EA8566304340F0004073 :101A88001066906800F00300012868D0012C6ED021 :101A9800D2F8B0100120A84021EA0001C2F8B01025 :101AA800102D39D0112D79D18F498968CE0137D4BD :101AB80090688E49B2F1A04F00F0030018BF4FF0B4 :101AC800A041012800F08C80886800F003000128FC :101AD80000F0D780102D00F0B680112D00F0A880FE :101AE800122D1DD180498A6842F480028A6017E06D :101AF800092817D90E2800EB40004FEA400063D8A8 :101B0800966B0D683C381F27874026EA070605FABA :101B180000F0304390637AE7734989680F02C7D5AC :101B280000209FE700EB40004000566B0D681E3810 :101B38001F27874026EA070605FA00F0304350635E :101B480065E750698E6805EB450C072707FA0CF71F :101B580020EA070006FA0CF6304350616CE710687B :101B6800C00793D5DCE7022002B0F0BC7047D2F87A :101B7800B000AC400443092DC2F8B04015D905EBBC :101B880045008E689469A0F11B0107278F4006FA6B :101B980001F024EA07010143916181E7122DBFD1C9 :101BA800514989684C02BBD482E70135886851697C :101BB80005EB45050724AC4021EA040100FA05F5C8 :101BC8002943516100204DE7D66B0D685A381F270D :101BD800874026EA070605FA00F03043D06316E787 :101BE8001068C0077FF570AF1A6C42F020021A64C3 :101BF800012037E7D76E3B4E3E4046EA85663043C4 :101C080040F00040D0663CE7976E364E3E4046EACC :101C18008566304340F00040906632E7576E314E9B :101C28003E4046EA8566304340F00040506628E76B :101C3800B2F1A04F7FF474AF2B498A6842F08072EA :101C48008A6000200EE7B2F1A04F7FF469AF264901 :101C5800274C8A68274842F400028A602268A0FB61 :101C68000212920C02EB820252000192019A002A9F :101C78003FF456AF019A013A0192019A002AF9D12C :101C88004EE70968C907AFD424E7106E00F0F840A2 :101C9800B0EB856F4FEA856614D0506E00F0F840BF :101CA800864214D0906E00F0F840864214D0D06E70 :101CB80000F0F84086427FF4E4AED06E20F0004099 :101CC800D066DEE6106E20F000401066E5E7506E44 :101CD80020F000405066E5E7906E20F000409066E6 :101CE800E5E700BF00F0FF8300030050000100504B :101CF8000008002083DE1B43F0B4034635481C6807 :101D080093F83C20B4F1A04F18BF4FF0A040012A2F :101D180035D001220D6883F83C20A268570709D501 :101D28001A6C42F020021A640120002283F83C2039 :101D3800F0BC704782685607F2D41DB3264F4E6830 :101D4800BA6893F830C022F46042324342EA4C3217 :101D5800BA60A26802F00302012A37D0826802F052 :101D68000302012A2AD01C488968826822F4716219 :101D78000D4322F00F02154385600020D5E70220AD :101D8800F0BC704714498A6822F460428A60A268ED :101D980002F00302012A15D0826802F00302012A28 :101DA80008D00D498A6822F4716222F00F028A6015 :101DB8000020BAE70268D207DFD4F2E70268D0074A :101DC800DBD4D0E72268D107D7D4E5E72268D40767 :101DD800C4D5D2E700010050000300500849CA6882 :101DE80010B400024FF6FF04224000F4E0631343EE :101DF80043F0BF6343F400335DF8044BCB60704796 :101E080000ED00E0194BDB68C3F3022330B4C3F1E3 :101E18000705042D03F1040428BF0425062C19D94D :101E2800033B4FF0FF349C4022EA04024FF0FF349A :101E3800AC4021EA04019940002841EA02010CDB88 :101E480000F1604000F561400901C9B280F8001353 :101E580030BC704700221346E8E7054B00F00F003E :101E680009010344C9B2197630BC704700ED00E09F :101E7800FCEC00E0002807DB00F01F01034A4009E2 :101E880001238B4042F82030704700BF00E100E09A :101E98000138B0F1807F0ED2084B10B4084C58605E :101EA800F02084F823000022072110469A605DF88C :101EB800044B196070470120704700BF10E000E034 :101EC80000ED00E038B370B4D0E90125D0E903147F :101ED80003462A4300685E699D690A4322433243E8 :101EE80004680E490E4E2A43DD6924F47F540144E8 :101EF8002A4324F030042243A6FB01610260094C06 :101F080009094FF48072002089001A84C3E90F413F :101F180070BC986370470120704700BFF8FFFDBF91 :101F2800CDCCCCCC00000240F0B490F82040012C7D :101F380039D090F821500124A54280F8204005D0DE :101F4800002380F82030F0BC022070470468022784 :101F5800002680F8217086632668C76B26F0010C7E :101F6800066CC4F800C0B54046687D606360C36A0B :101F7800102E0BBFA260A160E160E26053B123683C :101F880043F00E032360236843F00103236000201D :101F9800F0BC7047236843F00A032360236823F0EA :101FA80004032360EFE70220F0BC704770B4D0E967 :101FB8000F6204233168046893400B4225680ED0F1 :101FC80015F0040F0BD02268920603D4226822F081 :101FD80004022260C26A7360CAB170BC104702234F :101FE80093400B4215D015F0020F12D022689206CA :101FF80006D42268012122F00A02226080F821100A :10200800826A7360002380F82030002AE5D170BC12 :102018007047082393400B42F9D02B07F7D5236864 :10202800016B23F00E032360012303FA02F24FF43D :1020380080747260836304840029E8D070BC084708 :102048002DE9F04F0D6883B0002D00F0C280DFF855 :10205800ACC100234FF0010876E0D0F800B04FEA99 :102068004309032606FA09F602F003072BEA060BD2 :1020780007FA09F70AF1FF3A47EA0B07BAF1010F25 :102088006FEA0606076040F29180C7688C683E4098 :1020980004FA09F43443C460D40051D5534EB469EA :1020A80044F00104B461B46923F0030606F18046E4 :1020B80004F0010406F58036019403F003044FEAA6 :1020C800840A019FB7680F2404FA0AF9B0F1904F07 :1020D80027EA09070DD0464CA0427DD0454CA042C6 :1020E8007ED0454CA0420CBF0324052404FA0AF410 :1020F8002743B760DCF800406FEA0E06D70354BFE9 :1021080034404EEA0404CCF80040DCF8044097035D :1021180054BF34404EEA0404CCF80440DCF80840CC :10212800D70254BF34404EEA0404CCF80840DCF827 :102138000C40920254BF34404EEA0404CCF80C40E0 :10214800013335FA03F244D008FA03F414EA050E11 :10215800F6D04A6822F0100ABAF1020F7FF47DAF78 :102168004FEAD30900EB890903F00707D9F8206083 :10217800BF004FF00F0A0AFA07FB26EA0B0A0E699E :10218800BE4046EA0A06C9F82060D0F800A04FEA27 :102198004309032606FA09F602F003072AEA060AA3 :1021A80007FA09F747EA0A07F6430760876807EA64 :1021B800060ACF6807FA09F747EA0A078760D0F8DE :1021C80004A0C2F300172AEA04049F40274347608B :1021D8005BE703B0BDE8F08F08FA0AF4274388E705 :1021E8004FF0020909FA0AF4274382E70010024077 :1021F8000004004800080048000C004800040140A2 :102208000369194214BF01200020704770B401F01F :10221800100105680123044603FA01F0A84322D0FF :10222800D2E900036BB9D26825680243FA208840D6 :1022380002FA01F125EA000211431846216070BC38 :102248007047D2E9026503432268334340F6FA70C7 :102258002B43884003FA01F122EA00031943216065 :10226800002070BC7047184670BC70472DE9F047D5 :102278000C6894FAA4F2B2FA82F234FA02F300F08B :10228800A0804F684FF0010C07F1FF3E03264FF086 :102298000F0803E0013234FA02F36ED00CFA02F3AD :1022A8002340F7D0D0F8009093FAA3FABAFA8AFA42 :1022B80093FAA3F5B5FA85F54FEA4A0A6D0006FACE :1022C8000AFA07FA05F529EA0A0949EA0505BEF1F5 :1022D800010F056016D8856893FAA3F9B9FA89F948 :1022E80093FAA3FA4FEA490906FA09F925EA09090E :1022F800BAFA8AFA8D684FEA4A0A05FA0AF549EAEB :1023080005058560C56893FAA3F9B9FA89F993FABE :10231800A3FA4FEA490906FA09F925EA0909BAFAB6 :102328008AFA0D694FEA4A0A05FA0AF549EA0505E3 :10233800022FC560AED193FAA3F9B9FA89F9B9F1B8 :10234800070F4FEA132526DC056A93FAA3FABAFAAF :102358008AFA93FAA3F34FEA8A0A08FA0AFA25EAEC :102368000A09B3FA83F34D699B009D40013249EA9B :10237800050534FA02F3056290D1BEF1010F07D8C2 :10238800CA68436802FB04F223EA04041443446065 :102398000020BDE8F087436A95FAA5FABAFA8AFAE6 :1023A80095FAA5F54FEA8A0A08FA0AFA23EA0A0909 :1023B800B5FA85F54B69AD00AB4049EA03034362C2 :1023C80068E74B6803F1FF3ED7E700BF224A03687E :1023D800904230B438D0B0F1804F15D0A2F5943285 :1023E800904211D002F59E32904221D002F58062CF :1023F80090421DD002F58062904219D08C680A88FC :102408000360C46282620CE04A68D1E9024523F0A5 :102418007003134323F440730A882B430360C46298 :102428008262436943F00103436130BC0020704776 :10243800CC680A8823F44073234303608B68C36223 :1024480082620B7C0363ECE74D68CC680A8823F052 :1024580070032B43EEE700BF002C0140014B1860CE :10246800704700BF0008002070B50D4D0D4C641B6F :10247800A4100026A64209D10B4D0C4C00F018F808 :10248800641BA4100026A64205D170BD55F8043B74 :1024980098470136EEE755F8043B98470136F2E7CE :1024A800D02C0008D02C0008D02C0008D42C000810 :1024B800F8B500BFF8BC08BC9E467047F8B500BF29 :0824C800F8BC08BC9E467047F9 :1024D0000080C98092815B822483ED83B6847E85EF :1024E00047861087D987A1886A89328AFB8AC38B7D :1024F0008B8C538D1B8EE38EAB8F72903991019232 :10250000C7928E9355941B95E195A7966D97339836 :10251000F898BD99829A479B0B9CCF9C939D569EA1 :10252000199FDC9F9FA061A123A2E5A2A6A367A497 :1025300027A5E8A5A7A667A726A8E5A8A3A961AA35 :102540001FABDCAB98AC55AD10AECCAE87AF41B095 :10255000FBB0B5B16EB226B3DEB396B44DB503B6DB :10256000B9B66FB724B8D8B88CB93FBAF2BAA4BB21 :1025700056BC07BDB7BD67BE17BFC5BF73C021C17D :10258000CDC179C225C3D0C37AC424C5CCC575C614 :102590001CC7C3C769C80FC9B3C957CAFBCA9DCBFB :1025A0003FCCE0CC81CD20CEBFCE5DCFFBCF97D04E :1025B00033D1CED168D202D39AD332D4C9D45FD525 :1025C000F5D589D61DD7B0D742D8D3D864D9F3D999 :1025D00082DA0FDB9CDB28DCB3DC3DDDC7DD4FDEC0 :1025E000D7DE5DDFE3DF68E0EBE06EE1F0E171E2B2 :1025F000F1E270E3EEE36BE4E8E463E5DDE556E683 :10260000CFE646E7BCE731E8A6E819E98BE9FCE943 :102610006DEADCEA4AEBB7EB23EC8EECF8EC61ED0B :10262000C9ED30EE96EEFAEE5EEFC1EF22F083F0E8 :10263000E2F040F19DF1F9F154F2AEF207F35EF3EE :10264000B5F30AF45FF4B2F404F555F5A5F5F3F526 :1026500041F68DF6D8F622F76BF7B3F7FAF73FF8A5 :1026600084F8C7F809F94AF989F9C8F905FA41FA6D :102670007CFAB6FAEEFA26FB5CFB91FBC5FBF8FB95 :1026800029FC59FC88FCB6FCE3FC0EFD39FD62FD1B :1026900089FDB0FDD5FDFAFD1DFE3EFE5FFE7EFE0E :1026A0009CFEB9FED5FEEFFE09FF21FF37FF4DFF6F :1026B00061FF74FF86FF97FFA6FFB4FFC1FFCDFF48 :1026C000D8FFE1FFE9FFF0FFF5FFF9FFFDFFFEFF97 :1026D000FFFFFEFFFDFFF9FFF5FFF0FFE9FFE1FF60 :1026E000D8FFCDFFC1FFB4FFA6FF97FF86FF74FFA1 :1026F00061FF4DFF37FF21FF09FFEFFED5FEB9FE59 :102700009CFE7EFE5FFE3EFE1DFEFAFDD5FDB0FD89 :1027100089FD62FD39FD0EFDE3FCB6FC88FC59FC29 :1027200029FCF8FBC5FB91FB5CFB26FBEEFAB6FA35 :102730007CFA41FA05FAC8F989F94AF909F9C7F8A2 :1027400084F83FF8FAF7B3F76BF722F7D8F68DF66F :1027500041F6F3F5A5F555F504F5B2F45FF40AF486 :10276000B5F35EF307F3AEF254F2F9F19DF140F1E7 :10277000E2F083F022F0C1EF5EEFFAEE96EE30EE7B :10278000C9ED61EDF8EC8EEC23ECB7EB4AEBDCEA3B :102790006DEAFCE98BE919E9A6E831E8BCE746E710 :1027A000CFE656E6DDE563E5E8E46BE4EEE370E3EF :1027B000F1E271E2F0E16EE1EBE068E0E3DF5DDFC2 :1027C000D7DE4FDEC7DD3DDDB3DC28DC9CDB0FDB75 :1027D00082DAF3D964D9D3D842D8B0D71DD789D6F5 :1027E000F5D55FD5C9D432D49AD302D368D2CED12D :1027F00033D197D0FBCF5DCFBFCE20CE81CDE0CC03 :102800003FCC9DCBFBCA57CAB3C90FC969C8C3C760 :102810001CC775C6CCC524C57AC4D0C325C379C22C :10282000CDC121C173C0C5BF17BF67BEB7BD07BD4E :1028300056BCA4BBF2BA3FBA8CB9D8B824B86FB7AB :10284000B9B603B64DB596B4DEB326B36EB2B5B124 :10285000FBB041B087AFCCAE10AE55AD98ACDCABA1 :102860001FAB61AAA3A9E5A826A867A7A7A6E8A504 :1028700027A567A4A6A3E5A223A261A19FA0DC9F30 :10288000199F569E939DCF9C0B9C479B829ABD9906 :10289000F89833986D97A796E1951B9555948E936C :1028A000C792019239917290AB8FE38E1B8E538D3C :1028B0008B8CC38BFB8A328A6A89A188D98710875F :1028C00047867E85B684ED8324835B829281C980AE :1028D0000080367F6D7EA47DDB7C127C497B817A13 :1028E000B879EF7826785E779576CD7504753C7467 :1028F0007473AC72E4711C7154708D6FC66EFE6D92 :10290000386D716CAA6BE46A1E6A58699268CC676C :10291000076742667D65B864F46330636C62A961E1 :10292000E6602360605F9E5EDC5D1A5D595C985BCB :10293000D85A175A58599858D9571A575C569E550D :10294000E05423546753AA52EF5133517850BE4F8D :10295000044F4A4E914DD94C214C694BB24AFC4927 :1029600046499048DB4727477346C0450D455B44C1 :10297000A943F84248429841E8403A408C3FDE3E45 :10298000323E863DDA3C2F3C853BDB3A333A8A398E :10299000E3383C389637F0364C36A8350435623487 :1029A000C0331F337E32DF314031A2300430682F14 :1029B000CC2E312E972DFD2C652CCD2B362BA02A1D :1029C0000A2A7629E2284F28BD272C279B260C2689 :1029D0007D25F0246324D7234C23C2223822B02142 :1029E0002821A2201C20971F141F911E0F1E8E1D30 :1029F0000E1D8F1C111C941B171B9C1A221AA9193F :102A00003019B9184318CE175917E616741603165D :102A100092152315B5144814DC13711307139E1275 :102A20003612CF1169110511A1103E10DD0F7C0F78 :102A30001D0FBF0E620E060EAB0D510DF80CA10C52 :102A40004A0CF50BA00B4D0BFB0AAA0A5A0A0C0AFA :102A5000BE0972092709DD0894084C080508C0075B :102A60007B073807F606B50676063706FA05BE0573 :102A7000830549051105D904A3046E043A0407042B :102A8000D603A603770349031C03F102C6029D0285 :102A900076024F022A020502E201C101A001810172 :102AA000630146012A011001F600DE00C800B200F1 :102AB0009E008B007900680059004B003E003200F8 :102AC00027001E0016000F000A0006000200010089 :102AD00000000100020006000A000F0016001E00A0 :102AE000270032003E004B005900680079008B003F :102AF0009E00B200C800DE00F60010012A01460167 :102B000063018101A001C101E20105022A024F0215 :102B100076029D02C602F1021C0349037703A60355 :102B2000D60307043A046E04A304D9041105490529 :102B30008305BE05FA0537067606B506F60638079C :102B40007B07C00705084C089408DD0827097209AF :102B5000BE090C0A5A0AAA0AFB0A4D0BA00BF50B78 :102B60004A0CA10CF80C510DAB0D060E620EBF0EF7 :102B70001D0F7C0FDD0F3E10A11005116911CF1143 :102B800036129E1207137113DC134814B514231563 :102B9000921503167416E6165917CE174318B9186E :102BA0003019A919221A9C1A171B941B111C8F1C6F :102BB0000E1D8E1D0F1E911E141F971F1C20A2207C :102BC0002821B0213822C2224C23D7236324F024A9 :102BD0007D250C269B262C27BD274F28E228762909 :102BE0000A2AA02A362BCD2B652CFD2C972D312EB1 :102BF000CC2E682F0430A2304031DF317E321F33BB :102C0000C03362340435A8354C36F03696373C383C :102C1000E3388A39333ADB3A853B2F3CDA3C863D50 :102C2000323EDE3E8C3F3A40E84098414842F8420E :102C3000A9435B440D45C04573462747DB47904891 :102C40004649FC49B24A694B214CD94C914D4A4EF8 :102C5000044FBE4F78503351EF51AA52675323545B :102C6000E0549E555C561A57D95798585859175AD8 :102C7000D85A985B595C1A5DDC5D9E5E605F23608C :102C8000E660A9616C623063F463B8647D65426696 :102C90000767CC67926858691E6AE46AAA6B716C10 :102CA000386DFE6DC66E8D6F54701C71E471AC7220 :102CB00074733C740475CD7595765E772678EF78DD :102CC000B879817A497B127CDB7CA47D6D7E367F6E :042CD000AD0100084A :042CD400890100086A :102CD800FFFF03FD11FA27F746F46DF19DEED6EBE1 :102CE80016E95FE6B0E309E16ADED2DB43D9BBD679 :102CF8003AD4C1D150CFE6CC82CA26C8D2C584C343 :102D08003CC1FCBEC2BC90BA63B83DB61EB404B2A6 :102D1800F2AFE5ADDEABDEA9E3A7EEA5FFA316A2F1 :102D280033A0559E7D9CAA9ADD9815975295959348 :102D3800DD912A907C8ED38C2F8B9089F5876086C5 :102D4800CF844383BC813980BA7E407DCB7B597A5E :102D5800ED7884771F76BF7463730B72B770676FF3 :102D68001A6ED26C8D6B4D6A1069D667A0666E6557 :102D780040641563ED61C960A95F8B5E715D5B5C42 :102D8800475B375A2A59205819571556155517545D :102D98001C5324522F513D504E4F614E784D904C4C :102DA800AC4BCA4AEB490F4935485E478946B64598 :102DB800E74419444E438542BF41FB403940793FBF :102DC800BC3E013E483D913CDD3B2A3B7A3ACB393B :102DD8001F397438CC3726378136DF353E359F3476 :102DE80002346733CE323632A1310D317A30EA2FD0 :102DF8005B2FCE2E422EB82D302DA92C242CA02BA3 :102E08001E2B9D2A1E2AA1292429AA283028B92741 :102E18004227CD265926E7257625062598242B24F2 :102E2800BF235423EB2283221C22B6215121EE20FA :102E38008C202B20CB1F6C1F0E1FB21E561EFC1D94 :102E4800A21D4A1DF21C9C1C471CF21B9F1B4D1BFC :102E5800FB1AAB1A5B1A0D1ABF1972192619DB185F :102E6800911848180018B81771172B17E616A216EC :102E78005E161C16DA15991558151815DA149B14D0 :102E88005E142114E513AA136F133513FC12C31231 :102E98008B1254121D12E711B2117D11491115112F :102EA800E310B0107E104D101D10ED0FBD0F8E0FEA :102EB800600F320F050FD80EAB0E800E540E2A0E7F :102EC800FF0DD60DAC0D840D5B0D340D0C0DE50C0E :102ED800BF0C990C730C4E0C290C050CE10BBE0BA6 :102EE8009B0B780B560B340B130BF20AD10AB10A61 :102EF800910A710A520A340A150AF709D909BC0954 :102F08009F09820966094A092E091309F808DD088C :102F1800C208A8088F0875085C0843082A08120820 :102F2800FA07E207CB07B3079C0786076F0759071D :102F380043072D0718070307EE06D906C506B1068D :102F48009D068906760662064F063C062A0617067F :102F58000506F305E205D005BF05AE059D058C0500 :102F68007B056B055B054B053B052B051C050D0516 :102F7800FE04EF04E004D204C304B504A7049904D2 :102F88008B047E0470046304560449043C04300432 :102F9800230417040B04FF03F303E703DB03D00345 :102FA800C403B903AE03A30398038E038303790311 :102FB8006E0364035A03500346033C033303290397 :102FC800200316030D030403FB02F202E902E102E7 :102FD800D802D002C702BF02B702AF02A7029F02FF :102FE80097028F0288028002790271026A026302E4 :102FF8005C0255024E0247024002390233022C029B :1030080026021F02190213020C0206020002FA012C :10301800F401EF01E901E301DD01D801D201CD019D :10302800C801C201BD01B801B301AE01A901A401E3 :103038009F019A01950190018C01870183017E010E :103048007A01750171016D016801640160015C011B :103058005801540150014C014801440141013D010E :103068003901350132012E012B01270124012001EC :103078001D011A011601130110010D010A010701B2 :1030880004010101FE00FB00F800F500F200EF006A :10309800EC00EA00E700E400E200DF00DC00DA0010 :1030A800D700D500D200D000CD00CB00C900C600A3 :1030B800C400C200BF00BD00BB00B900B700B50026 :1030C800B200B000AE00AC00AA00A800A600A400A0 :1030D800A200A1009F009D009B0099009700960008 :1030E8009400920090008F008D008B008A00880069 :1030F800870085008400820081007F007E007C00BC :103108007B00790078007600750074007200710009 :1031180070006E006D006C006B006900680067004D :103128006600640063006200610060005F005E008A :103138005D005B005A0059005800570056005500C2 :10314800540053005200510050004F004F004E00F1 :103158004D004C004B004A00490048004800470019 :10316800460045004400430043004200410040003F :1031780040003F003E003D003D003C003B003B005E :103188003A0039003900380037003700360035007A :103198003500340034003300320032003100310091 :1031A80030002F002F002E002E002D002D002C00A7 :1031B8002C002B002B002A002A00290029002800B7 :1031C80028002700270026002600260025002500C5 :1031D80024002400230023002300220022002100D1 :1031E80021002100200020001F001F001F001E00DA :1031F8001E001E001D001D001D001C001C001C00E0 :103208001B001B001B001A001A001A001A001900E4 :1032180019001900180018001800170017001700E7 :1032280017001600160016001600150015001500E8 :1032380015001400140014001400130013001300E8 :1032480013001300120012001200120012001100E5 :1032580011001100110011001000100010001000E2 :1032680010000F000F000F000F000F000F000E00DE :103278000E000E000E000E000E000D000D000D00D9 :103288000D000D000D000C000C000C000C000C00D3 :103298000C000C000B000B000B000B000B000B00CC :1032A8000B000B000A000A000A000A000A000A00C4 :1032B8000A000A000A0009000900090009000900BB :1032C80009000900090009000800080008000800B2 :1032D80008000800080008000800080008000700A7 :1032E800070007000700070007000700070007009E :1032F8000700070007000600060006000600060093 :103308000600060006000600060006000600060085 :10331800060005000500050005000500050005007C :10332800050005000500050005000500050005006D :103338000500050005000400040004000400040062 :103348000400040004000400040004000400040055 :103358000400040004000400040004000400040045 :10336800030003000300030003000300030003003D :10337800030003000300030003000300030003002D :10338800030003000300030003000300030003001D :103398000300030003000300030002000200020010 :1033A8000200020002000200020002000200020005 :1033B80002000200020002000200020002000200F5 :1033C80002000200020002000200020002000200E5 :1033D80002000200020002000200020002000200D5 :1033E80002000200020002000200020002000200C5 :1033F80001000100010001000100010001000100BD :1034080001000100010001000100010001000100AC :10341800010001000100010001000100010001009C :10342800010001000100010001000100010001008C :10343800010001000100010001000100010001007C :10344800010001000100010001000100010001006C :10345800010001000100010001000100010001005C :10346800010001000100010001000100010001004C :10347800010001000100010001000100010001003C :10348800010001000100010001000100010001002C :10349800010001000100010001000100010001001C :1034A800010001000100010001000100000000000E :1034B8000000000000000000000000000000000004 :1034C80000000000000000000000000000000000F4 :0C34D80000127A0001000000100000004B :040000050800149942 :00000001FF ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/2OPFM_2020.list ================================================ 2OPFM_2020.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000188 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00002348 08000188 08000188 00010188 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000800 080024d0 080024d0 000124d0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08002cd0 08002cd0 0002080c 2**0 CONTENTS 4 .ARM 00000000 08002cd0 08002cd0 0002080c 2**0 CONTENTS 5 .preinit_array 00000000 08002cd0 08002cd0 0002080c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08002cd0 08002cd0 00012cd0 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08002cd4 08002cd4 00012cd4 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000080c 20000000 08002cd8 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000480 2000080c 080034e4 0002080c 2**2 ALLOC 10 ._user_heap_stack 00000604 20000c8c 080034e4 00020c8c 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0002080c 2**0 CONTENTS, READONLY 12 .debug_info 00017454 00000000 00000000 0002083c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 0000300d 00000000 00000000 00037c90 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loc 00006d03 00000000 00000000 0003ac9d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00000720 00000000 00000000 000419a0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_ranges 00001550 00000000 00000000 000420c0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 0001e745 00000000 00000000 00043610 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 0000f814 00000000 00000000 00061d55 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000adbe0 00000000 00000000 00071569 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000053 00000000 00000000 0011f149 2**0 CONTENTS, READONLY 21 .debug_frame 000014a4 00000000 00000000 0011f19c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000188 <__do_global_dtors_aux>: 8000188: b510 push {r4, lr} 800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>) 800018c: 7823 ldrb r3, [r4, #0] 800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16> 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>) 8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12> 8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>) 8000196: f3af 8000 nop.w 800019a: 2301 movs r3, #1 800019c: 7023 strb r3, [r4, #0] 800019e: bd10 pop {r4, pc} 80001a0: 2000080c .word 0x2000080c 80001a4: 00000000 .word 0x00000000 80001a8: 080024b8 .word 0x080024b8 080001ac : 80001ac: b508 push {r3, lr} 80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc ) 80001b0: b11b cbz r3, 80001ba 80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 ) 80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 ) 80001b6: f3af 8000 nop.w 80001ba: bd08 pop {r3, pc} 80001bc: 00000000 .word 0x00000000 80001c0: 20000810 .word 0x20000810 80001c4: 080024b8 .word 0x080024b8 080001c8 <__aeabi_drsub>: 80001c8: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 80001cc: e002 b.n 80001d4 <__adddf3> 80001ce: bf00 nop 080001d0 <__aeabi_dsub>: 80001d0: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 080001d4 <__adddf3>: 80001d4: b530 push {r4, r5, lr} 80001d6: ea4f 0441 mov.w r4, r1, lsl #1 80001da: ea4f 0543 mov.w r5, r3, lsl #1 80001de: ea94 0f05 teq r4, r5 80001e2: bf08 it eq 80001e4: ea90 0f02 teqeq r0, r2 80001e8: bf1f itttt ne 80001ea: ea54 0c00 orrsne.w ip, r4, r0 80001ee: ea55 0c02 orrsne.w ip, r5, r2 80001f2: ea7f 5c64 mvnsne.w ip, r4, asr #21 80001f6: ea7f 5c65 mvnsne.w ip, r5, asr #21 80001fa: f000 80e2 beq.w 80003c2 <__adddf3+0x1ee> 80001fe: ea4f 5454 mov.w r4, r4, lsr #21 8000202: ebd4 5555 rsbs r5, r4, r5, lsr #21 8000206: bfb8 it lt 8000208: 426d neglt r5, r5 800020a: dd0c ble.n 8000226 <__adddf3+0x52> 800020c: 442c add r4, r5 800020e: ea80 0202 eor.w r2, r0, r2 8000212: ea81 0303 eor.w r3, r1, r3 8000216: ea82 0000 eor.w r0, r2, r0 800021a: ea83 0101 eor.w r1, r3, r1 800021e: ea80 0202 eor.w r2, r0, r2 8000222: ea81 0303 eor.w r3, r1, r3 8000226: 2d36 cmp r5, #54 ; 0x36 8000228: bf88 it hi 800022a: bd30 pophi {r4, r5, pc} 800022c: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000230: ea4f 3101 mov.w r1, r1, lsl #12 8000234: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000238: ea4c 3111 orr.w r1, ip, r1, lsr #12 800023c: d002 beq.n 8000244 <__adddf3+0x70> 800023e: 4240 negs r0, r0 8000240: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000244: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 8000248: ea4f 3303 mov.w r3, r3, lsl #12 800024c: ea4c 3313 orr.w r3, ip, r3, lsr #12 8000250: d002 beq.n 8000258 <__adddf3+0x84> 8000252: 4252 negs r2, r2 8000254: eb63 0343 sbc.w r3, r3, r3, lsl #1 8000258: ea94 0f05 teq r4, r5 800025c: f000 80a7 beq.w 80003ae <__adddf3+0x1da> 8000260: f1a4 0401 sub.w r4, r4, #1 8000264: f1d5 0e20 rsbs lr, r5, #32 8000268: db0d blt.n 8000286 <__adddf3+0xb2> 800026a: fa02 fc0e lsl.w ip, r2, lr 800026e: fa22 f205 lsr.w r2, r2, r5 8000272: 1880 adds r0, r0, r2 8000274: f141 0100 adc.w r1, r1, #0 8000278: fa03 f20e lsl.w r2, r3, lr 800027c: 1880 adds r0, r0, r2 800027e: fa43 f305 asr.w r3, r3, r5 8000282: 4159 adcs r1, r3 8000284: e00e b.n 80002a4 <__adddf3+0xd0> 8000286: f1a5 0520 sub.w r5, r5, #32 800028a: f10e 0e20 add.w lr, lr, #32 800028e: 2a01 cmp r2, #1 8000290: fa03 fc0e lsl.w ip, r3, lr 8000294: bf28 it cs 8000296: f04c 0c02 orrcs.w ip, ip, #2 800029a: fa43 f305 asr.w r3, r3, r5 800029e: 18c0 adds r0, r0, r3 80002a0: eb51 71e3 adcs.w r1, r1, r3, asr #31 80002a4: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80002a8: d507 bpl.n 80002ba <__adddf3+0xe6> 80002aa: f04f 0e00 mov.w lr, #0 80002ae: f1dc 0c00 rsbs ip, ip, #0 80002b2: eb7e 0000 sbcs.w r0, lr, r0 80002b6: eb6e 0101 sbc.w r1, lr, r1 80002ba: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 80002be: d31b bcc.n 80002f8 <__adddf3+0x124> 80002c0: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 80002c4: d30c bcc.n 80002e0 <__adddf3+0x10c> 80002c6: 0849 lsrs r1, r1, #1 80002c8: ea5f 0030 movs.w r0, r0, rrx 80002cc: ea4f 0c3c mov.w ip, ip, rrx 80002d0: f104 0401 add.w r4, r4, #1 80002d4: ea4f 5244 mov.w r2, r4, lsl #21 80002d8: f512 0f80 cmn.w r2, #4194304 ; 0x400000 80002dc: f080 809a bcs.w 8000414 <__adddf3+0x240> 80002e0: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 80002e4: bf08 it eq 80002e6: ea5f 0c50 movseq.w ip, r0, lsr #1 80002ea: f150 0000 adcs.w r0, r0, #0 80002ee: eb41 5104 adc.w r1, r1, r4, lsl #20 80002f2: ea41 0105 orr.w r1, r1, r5 80002f6: bd30 pop {r4, r5, pc} 80002f8: ea5f 0c4c movs.w ip, ip, lsl #1 80002fc: 4140 adcs r0, r0 80002fe: eb41 0101 adc.w r1, r1, r1 8000302: 3c01 subs r4, #1 8000304: bf28 it cs 8000306: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 800030a: d2e9 bcs.n 80002e0 <__adddf3+0x10c> 800030c: f091 0f00 teq r1, #0 8000310: bf04 itt eq 8000312: 4601 moveq r1, r0 8000314: 2000 moveq r0, #0 8000316: fab1 f381 clz r3, r1 800031a: bf08 it eq 800031c: 3320 addeq r3, #32 800031e: f1a3 030b sub.w r3, r3, #11 8000322: f1b3 0220 subs.w r2, r3, #32 8000326: da0c bge.n 8000342 <__adddf3+0x16e> 8000328: 320c adds r2, #12 800032a: dd08 ble.n 800033e <__adddf3+0x16a> 800032c: f102 0c14 add.w ip, r2, #20 8000330: f1c2 020c rsb r2, r2, #12 8000334: fa01 f00c lsl.w r0, r1, ip 8000338: fa21 f102 lsr.w r1, r1, r2 800033c: e00c b.n 8000358 <__adddf3+0x184> 800033e: f102 0214 add.w r2, r2, #20 8000342: bfd8 it le 8000344: f1c2 0c20 rsble ip, r2, #32 8000348: fa01 f102 lsl.w r1, r1, r2 800034c: fa20 fc0c lsr.w ip, r0, ip 8000350: bfdc itt le 8000352: ea41 010c orrle.w r1, r1, ip 8000356: 4090 lslle r0, r2 8000358: 1ae4 subs r4, r4, r3 800035a: bfa2 ittt ge 800035c: eb01 5104 addge.w r1, r1, r4, lsl #20 8000360: 4329 orrge r1, r5 8000362: bd30 popge {r4, r5, pc} 8000364: ea6f 0404 mvn.w r4, r4 8000368: 3c1f subs r4, #31 800036a: da1c bge.n 80003a6 <__adddf3+0x1d2> 800036c: 340c adds r4, #12 800036e: dc0e bgt.n 800038e <__adddf3+0x1ba> 8000370: f104 0414 add.w r4, r4, #20 8000374: f1c4 0220 rsb r2, r4, #32 8000378: fa20 f004 lsr.w r0, r0, r4 800037c: fa01 f302 lsl.w r3, r1, r2 8000380: ea40 0003 orr.w r0, r0, r3 8000384: fa21 f304 lsr.w r3, r1, r4 8000388: ea45 0103 orr.w r1, r5, r3 800038c: bd30 pop {r4, r5, pc} 800038e: f1c4 040c rsb r4, r4, #12 8000392: f1c4 0220 rsb r2, r4, #32 8000396: fa20 f002 lsr.w r0, r0, r2 800039a: fa01 f304 lsl.w r3, r1, r4 800039e: ea40 0003 orr.w r0, r0, r3 80003a2: 4629 mov r1, r5 80003a4: bd30 pop {r4, r5, pc} 80003a6: fa21 f004 lsr.w r0, r1, r4 80003aa: 4629 mov r1, r5 80003ac: bd30 pop {r4, r5, pc} 80003ae: f094 0f00 teq r4, #0 80003b2: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 80003b6: bf06 itte eq 80003b8: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 80003bc: 3401 addeq r4, #1 80003be: 3d01 subne r5, #1 80003c0: e74e b.n 8000260 <__adddf3+0x8c> 80003c2: ea7f 5c64 mvns.w ip, r4, asr #21 80003c6: bf18 it ne 80003c8: ea7f 5c65 mvnsne.w ip, r5, asr #21 80003cc: d029 beq.n 8000422 <__adddf3+0x24e> 80003ce: ea94 0f05 teq r4, r5 80003d2: bf08 it eq 80003d4: ea90 0f02 teqeq r0, r2 80003d8: d005 beq.n 80003e6 <__adddf3+0x212> 80003da: ea54 0c00 orrs.w ip, r4, r0 80003de: bf04 itt eq 80003e0: 4619 moveq r1, r3 80003e2: 4610 moveq r0, r2 80003e4: bd30 pop {r4, r5, pc} 80003e6: ea91 0f03 teq r1, r3 80003ea: bf1e ittt ne 80003ec: 2100 movne r1, #0 80003ee: 2000 movne r0, #0 80003f0: bd30 popne {r4, r5, pc} 80003f2: ea5f 5c54 movs.w ip, r4, lsr #21 80003f6: d105 bne.n 8000404 <__adddf3+0x230> 80003f8: 0040 lsls r0, r0, #1 80003fa: 4149 adcs r1, r1 80003fc: bf28 it cs 80003fe: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 8000402: bd30 pop {r4, r5, pc} 8000404: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000408: bf3c itt cc 800040a: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 800040e: bd30 popcc {r4, r5, pc} 8000410: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000414: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000418: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 800041c: f04f 0000 mov.w r0, #0 8000420: bd30 pop {r4, r5, pc} 8000422: ea7f 5c64 mvns.w ip, r4, asr #21 8000426: bf1a itte ne 8000428: 4619 movne r1, r3 800042a: 4610 movne r0, r2 800042c: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000430: bf1c itt ne 8000432: 460b movne r3, r1 8000434: 4602 movne r2, r0 8000436: ea50 3401 orrs.w r4, r0, r1, lsl #12 800043a: bf06 itte eq 800043c: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000440: ea91 0f03 teqeq r1, r3 8000444: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 8000448: bd30 pop {r4, r5, pc} 800044a: bf00 nop 0800044c <__aeabi_ui2d>: 800044c: f090 0f00 teq r0, #0 8000450: bf04 itt eq 8000452: 2100 moveq r1, #0 8000454: 4770 bxeq lr 8000456: b530 push {r4, r5, lr} 8000458: f44f 6480 mov.w r4, #1024 ; 0x400 800045c: f104 0432 add.w r4, r4, #50 ; 0x32 8000460: f04f 0500 mov.w r5, #0 8000464: f04f 0100 mov.w r1, #0 8000468: e750 b.n 800030c <__adddf3+0x138> 800046a: bf00 nop 0800046c <__aeabi_i2d>: 800046c: f090 0f00 teq r0, #0 8000470: bf04 itt eq 8000472: 2100 moveq r1, #0 8000474: 4770 bxeq lr 8000476: b530 push {r4, r5, lr} 8000478: f44f 6480 mov.w r4, #1024 ; 0x400 800047c: f104 0432 add.w r4, r4, #50 ; 0x32 8000480: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 8000484: bf48 it mi 8000486: 4240 negmi r0, r0 8000488: f04f 0100 mov.w r1, #0 800048c: e73e b.n 800030c <__adddf3+0x138> 800048e: bf00 nop 08000490 <__aeabi_f2d>: 8000490: 0042 lsls r2, r0, #1 8000492: ea4f 01e2 mov.w r1, r2, asr #3 8000496: ea4f 0131 mov.w r1, r1, rrx 800049a: ea4f 7002 mov.w r0, r2, lsl #28 800049e: bf1f itttt ne 80004a0: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 80004a4: f093 4f7f teqne r3, #4278190080 ; 0xff000000 80004a8: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 80004ac: 4770 bxne lr 80004ae: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 80004b2: bf08 it eq 80004b4: 4770 bxeq lr 80004b6: f093 4f7f teq r3, #4278190080 ; 0xff000000 80004ba: bf04 itt eq 80004bc: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 80004c0: 4770 bxeq lr 80004c2: b530 push {r4, r5, lr} 80004c4: f44f 7460 mov.w r4, #896 ; 0x380 80004c8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80004cc: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80004d0: e71c b.n 800030c <__adddf3+0x138> 80004d2: bf00 nop 080004d4 <__aeabi_ul2d>: 80004d4: ea50 0201 orrs.w r2, r0, r1 80004d8: bf08 it eq 80004da: 4770 bxeq lr 80004dc: b530 push {r4, r5, lr} 80004de: f04f 0500 mov.w r5, #0 80004e2: e00a b.n 80004fa <__aeabi_l2d+0x16> 080004e4 <__aeabi_l2d>: 80004e4: ea50 0201 orrs.w r2, r0, r1 80004e8: bf08 it eq 80004ea: 4770 bxeq lr 80004ec: b530 push {r4, r5, lr} 80004ee: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 80004f2: d502 bpl.n 80004fa <__aeabi_l2d+0x16> 80004f4: 4240 negs r0, r0 80004f6: eb61 0141 sbc.w r1, r1, r1, lsl #1 80004fa: f44f 6480 mov.w r4, #1024 ; 0x400 80004fe: f104 0432 add.w r4, r4, #50 ; 0x32 8000502: ea5f 5c91 movs.w ip, r1, lsr #22 8000506: f43f aed8 beq.w 80002ba <__adddf3+0xe6> 800050a: f04f 0203 mov.w r2, #3 800050e: ea5f 0cdc movs.w ip, ip, lsr #3 8000512: bf18 it ne 8000514: 3203 addne r2, #3 8000516: ea5f 0cdc movs.w ip, ip, lsr #3 800051a: bf18 it ne 800051c: 3203 addne r2, #3 800051e: eb02 02dc add.w r2, r2, ip, lsr #3 8000522: f1c2 0320 rsb r3, r2, #32 8000526: fa00 fc03 lsl.w ip, r0, r3 800052a: fa20 f002 lsr.w r0, r0, r2 800052e: fa01 fe03 lsl.w lr, r1, r3 8000532: ea40 000e orr.w r0, r0, lr 8000536: fa21 f102 lsr.w r1, r1, r2 800053a: 4414 add r4, r2 800053c: e6bd b.n 80002ba <__adddf3+0xe6> 800053e: bf00 nop 08000540 <__gedf2>: 8000540: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 8000544: e006 b.n 8000554 <__cmpdf2+0x4> 8000546: bf00 nop 08000548 <__ledf2>: 8000548: f04f 0c01 mov.w ip, #1 800054c: e002 b.n 8000554 <__cmpdf2+0x4> 800054e: bf00 nop 08000550 <__cmpdf2>: 8000550: f04f 0c01 mov.w ip, #1 8000554: f84d cd04 str.w ip, [sp, #-4]! 8000558: ea4f 0c41 mov.w ip, r1, lsl #1 800055c: ea7f 5c6c mvns.w ip, ip, asr #21 8000560: ea4f 0c43 mov.w ip, r3, lsl #1 8000564: bf18 it ne 8000566: ea7f 5c6c mvnsne.w ip, ip, asr #21 800056a: d01b beq.n 80005a4 <__cmpdf2+0x54> 800056c: b001 add sp, #4 800056e: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8000572: bf0c ite eq 8000574: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 8000578: ea91 0f03 teqne r1, r3 800057c: bf02 ittt eq 800057e: ea90 0f02 teqeq r0, r2 8000582: 2000 moveq r0, #0 8000584: 4770 bxeq lr 8000586: f110 0f00 cmn.w r0, #0 800058a: ea91 0f03 teq r1, r3 800058e: bf58 it pl 8000590: 4299 cmppl r1, r3 8000592: bf08 it eq 8000594: 4290 cmpeq r0, r2 8000596: bf2c ite cs 8000598: 17d8 asrcs r0, r3, #31 800059a: ea6f 70e3 mvncc.w r0, r3, asr #31 800059e: f040 0001 orr.w r0, r0, #1 80005a2: 4770 bx lr 80005a4: ea4f 0c41 mov.w ip, r1, lsl #1 80005a8: ea7f 5c6c mvns.w ip, ip, asr #21 80005ac: d102 bne.n 80005b4 <__cmpdf2+0x64> 80005ae: ea50 3c01 orrs.w ip, r0, r1, lsl #12 80005b2: d107 bne.n 80005c4 <__cmpdf2+0x74> 80005b4: ea4f 0c43 mov.w ip, r3, lsl #1 80005b8: ea7f 5c6c mvns.w ip, ip, asr #21 80005bc: d1d6 bne.n 800056c <__cmpdf2+0x1c> 80005be: ea52 3c03 orrs.w ip, r2, r3, lsl #12 80005c2: d0d3 beq.n 800056c <__cmpdf2+0x1c> 80005c4: f85d 0b04 ldr.w r0, [sp], #4 80005c8: 4770 bx lr 80005ca: bf00 nop 080005cc <__aeabi_cdrcmple>: 80005cc: 4684 mov ip, r0 80005ce: 4610 mov r0, r2 80005d0: 4662 mov r2, ip 80005d2: 468c mov ip, r1 80005d4: 4619 mov r1, r3 80005d6: 4663 mov r3, ip 80005d8: e000 b.n 80005dc <__aeabi_cdcmpeq> 80005da: bf00 nop 080005dc <__aeabi_cdcmpeq>: 80005dc: b501 push {r0, lr} 80005de: f7ff ffb7 bl 8000550 <__cmpdf2> 80005e2: 2800 cmp r0, #0 80005e4: bf48 it mi 80005e6: f110 0f00 cmnmi.w r0, #0 80005ea: bd01 pop {r0, pc} 080005ec <__aeabi_dcmpeq>: 80005ec: f84d ed08 str.w lr, [sp, #-8]! 80005f0: f7ff fff4 bl 80005dc <__aeabi_cdcmpeq> 80005f4: bf0c ite eq 80005f6: 2001 moveq r0, #1 80005f8: 2000 movne r0, #0 80005fa: f85d fb08 ldr.w pc, [sp], #8 80005fe: bf00 nop 08000600 <__aeabi_dcmplt>: 8000600: f84d ed08 str.w lr, [sp, #-8]! 8000604: f7ff ffea bl 80005dc <__aeabi_cdcmpeq> 8000608: bf34 ite cc 800060a: 2001 movcc r0, #1 800060c: 2000 movcs r0, #0 800060e: f85d fb08 ldr.w pc, [sp], #8 8000612: bf00 nop 08000614 <__aeabi_dcmple>: 8000614: f84d ed08 str.w lr, [sp, #-8]! 8000618: f7ff ffe0 bl 80005dc <__aeabi_cdcmpeq> 800061c: bf94 ite ls 800061e: 2001 movls r0, #1 8000620: 2000 movhi r0, #0 8000622: f85d fb08 ldr.w pc, [sp], #8 8000626: bf00 nop 08000628 <__aeabi_dcmpge>: 8000628: f84d ed08 str.w lr, [sp, #-8]! 800062c: f7ff ffce bl 80005cc <__aeabi_cdrcmple> 8000630: bf94 ite ls 8000632: 2001 movls r0, #1 8000634: 2000 movhi r0, #0 8000636: f85d fb08 ldr.w pc, [sp], #8 800063a: bf00 nop 0800063c <__aeabi_dcmpgt>: 800063c: f84d ed08 str.w lr, [sp, #-8]! 8000640: f7ff ffc4 bl 80005cc <__aeabi_cdrcmple> 8000644: bf34 ite cc 8000646: 2001 movcc r0, #1 8000648: 2000 movcs r0, #0 800064a: f85d fb08 ldr.w pc, [sp], #8 800064e: bf00 nop 08000650 : 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; void adsr_structinit(soft_adsr *adsr) { adsr->output = ENV_INIT; adsr->attack = 0.0f; 8000650: 2300 movs r3, #0 void adsr_structinit(soft_adsr *adsr) { 8000652: b410 push {r4} adsr->output = ENV_INIT; 8000654: f04f 527e mov.w r2, #1065353216 ; 0x3f800000 adsr->decay = 0.0f; adsr->sustain = 0.0f; adsr->release = 0.0f; adsr->stage = OFF; 8000658: 2403 movs r4, #3 adsr->rate = 0.0f; adsr->rate_offset = 0.0f; adsr->cutoff = 0.0f; adsr->target = ENV_INIT; adsr->one_shot = 0; 800065a: 2100 movs r1, #0 adsr->output = ENV_INIT; 800065c: 6002 str r2, [r0, #0] adsr->attack = 0.0f; 800065e: 6203 str r3, [r0, #32] adsr->decay = 0.0f; 8000660: 6243 str r3, [r0, #36] ; 0x24 adsr->sustain = 0.0f; 8000662: 6283 str r3, [r0, #40] ; 0x28 adsr->release = 0.0f; 8000664: 62c3 str r3, [r0, #44] ; 0x2c adsr->stage = OFF; 8000666: 7104 strb r4, [r0, #4] adsr->rate = 0.0f; 8000668: 6083 str r3, [r0, #8] } 800066a: f85d 4b04 ldr.w r4, [sp], #4 adsr->rate_offset = 0.0f; 800066e: 60c3 str r3, [r0, #12] adsr->cutoff = 0.0f; 8000670: 6183 str r3, [r0, #24] adsr->target = ENV_INIT; 8000672: 61c2 str r2, [r0, #28] adsr->one_shot = 0; 8000674: f880 1030 strb.w r1, [r0, #48] ; 0x30 } 8000678: 4770 bx lr 800067a: bf00 nop 800067c: 0000 movs r0, r0 ... 08000680 : } void run_linear_a_expo_r(soft_adsr *adsr) { //one shot style smooth attack if (adsr->output < 0.01f) { 8000680: ed90 7a00 vldr s14, [r0] 8000684: eddf 7a36 vldr s15, [pc, #216] ; 8000760 void run_linear_a_expo_r(soft_adsr *adsr) { 8000688: b510 push {r4, lr} if (adsr->output < 0.01f) { 800068a: eeb4 7ae7 vcmpe.f32 s14, s15 800068e: eef1 fa10 vmrs APSR_nzcv, fpscr adsr->one_shot = 0; 8000692: bf44 itt mi 8000694: 2300 movmi r3, #0 8000696: f880 3030 strbmi.w r3, [r0, #48] ; 0x30 } if (adsr->stage == ATTACK) { 800069a: 7903 ldrb r3, [r0, #4] void run_linear_a_expo_r(soft_adsr *adsr) { 800069c: 4604 mov r4, r0 if (adsr->stage == ATTACK) { 800069e: b9db cbnz r3, 80006d8 adsr->output += SMOOTH_ATTACK_INCREMENT; 80006a0: edd0 7a00 vldr s15, [r0] 80006a4: eddf 6a2f vldr s13, [pc, #188] ; 8000764 adsr->rate = adsr->attack + adsr->attack_offset; //attack threshold if (adsr->output > 0.95f) { 80006a8: ed9f 7a2f vldr s14, [pc, #188] ; 8000768 adsr->output += SMOOTH_ATTACK_INCREMENT; 80006ac: ee77 7aa6 vadd.f32 s15, s15, s13 80006b0: edc0 7a00 vstr s15, [r0] adsr->rate = adsr->attack + adsr->attack_offset; 80006b4: edd0 7a08 vldr s15, [r0, #32] 80006b8: edd0 6a04 vldr s13, [r0, #16] 80006bc: ee77 7aa6 vadd.f32 s15, s15, s13 80006c0: edc0 7a02 vstr s15, [r0, #8] if (adsr->output > 0.95f) { 80006c4: edd0 7a00 vldr s15, [r0] 80006c8: eef4 7ac7 vcmpe.f32 s15, s14 80006cc: eef1 fa10 vmrs APSR_nzcv, fpscr 80006d0: dd01 ble.n 80006d6 adsr->stage = RELEASE; 80006d2: 2302 movs r3, #2 80006d4: 7103 strb r3, [r0, #4] adsr->cutoff = 0; } adsr->output += (adsr->target - adsr->output) * adsr->cutoff; } } 80006d6: bd10 pop {r4, pc} if (adsr->stage == RELEASE) { 80006d8: 7903 ldrb r3, [r0, #4] 80006da: 2b02 cmp r3, #2 80006dc: d02e beq.n 800073c adsr->cutoff = (adsr->rate + adsr->rate_offset) * 0.1f; 80006de: edd4 7a02 vldr s15, [r4, #8] 80006e2: edd4 6a03 vldr s13, [r4, #12] 80006e6: ed9f 7a1f vldr s14, [pc, #124] ; 8000764 80006ea: ee77 7aa6 vadd.f32 s15, s15, s13 80006ee: ee67 7a87 vmul.f32 s15, s15, s14 80006f2: edc4 7a06 vstr s15, [r4, #24] if (adsr->cutoff > 0.99) { 80006f6: 69a0 ldr r0, [r4, #24] 80006f8: f7ff feca bl 8000490 <__aeabi_f2d> 80006fc: a316 add r3, pc, #88 ; (adr r3, 8000758 ) 80006fe: e9d3 2300 ldrd r2, r3, [r3] 8000702: f7ff ff9b bl 800063c <__aeabi_dcmpgt> 8000706: b108 cbz r0, 800070c adsr->cutoff = 0.99; 8000708: 4b18 ldr r3, [pc, #96] ; (800076c ) 800070a: 61a3 str r3, [r4, #24] if (adsr->cutoff < 0.0) { 800070c: edd4 7a06 vldr s15, [r4, #24] 8000710: eef5 7ac0 vcmpe.f32 s15, #0.0 8000714: 2300 movs r3, #0 8000716: eef1 fa10 vmrs APSR_nzcv, fpscr adsr->cutoff = 0; 800071a: bf48 it mi 800071c: 61a3 strmi r3, [r4, #24] adsr->output += (adsr->target - adsr->output) * adsr->cutoff; 800071e: ed94 7a07 vldr s14, [r4, #28] 8000722: ed94 6a00 vldr s12, [r4] 8000726: edd4 6a06 vldr s13, [r4, #24] 800072a: edd4 7a00 vldr s15, [r4] 800072e: ee37 7a46 vsub.f32 s14, s14, s12 8000732: eee7 7a26 vfma.f32 s15, s14, s13 8000736: edc4 7a00 vstr s15, [r4] } 800073a: bd10 pop {r4, pc} adsr->rate = adsr->release + adsr->release_offset; 800073c: edd0 7a0b vldr s15, [r0, #44] ; 0x2c 8000740: ed90 7a05 vldr s14, [r0, #20] 8000744: ee77 7a87 vadd.f32 s15, s15, s14 adsr->target = 0.0f; 8000748: 2300 movs r3, #0 adsr->rate = adsr->release + adsr->release_offset; 800074a: edc0 7a02 vstr s15, [r0, #8] adsr->target = 0.0f; 800074e: 61c3 str r3, [r0, #28] 8000750: e7c5 b.n 80006de 8000752: bf00 nop 8000754: f3af 8000 nop.w 8000758: 7ae147ae .word 0x7ae147ae 800075c: 3fefae14 .word 0x3fefae14 8000760: 3c23d70a .word 0x3c23d70a 8000764: 3dcccccd .word 0x3dcccccd 8000768: 3f733333 .word 0x3f733333 800076c: 3f7d70a4 .word 0x3f7d70a4 08000770 : OP->amplitude = 1.0f; OP->frequency = 440.0f; OP->phase_increment = ((4294967295) * (OP->frequency)) / 44100.0f; } void check_gate() { 8000770: b510 push {r4, lr} //read gate gate = !HAL_GPIO_ReadPin(GATE_PORT, GATE_PIN); 8000772: 2180 movs r1, #128 ; 0x80 8000774: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 8000778: f001 fd46 bl 8002208 //if low to high transition occurs if (gate) { if (!last_gate) { 800077c: 4a08 ldr r2, [pc, #32] ; (80007a0 ) gate = !HAL_GPIO_ReadPin(GATE_PORT, GATE_PIN); 800077e: 4909 ldr r1, [pc, #36] ; (80007a4 ) if (!last_gate) { 8000780: 7814 ldrb r4, [r2, #0] gate = !HAL_GPIO_ReadPin(GATE_PORT, GATE_PIN); 8000782: fab0 f380 clz r3, r0 if (!last_gate) { 8000786: 4320 orrs r0, r4 gate = !HAL_GPIO_ReadPin(GATE_PORT, GATE_PIN); 8000788: 095b lsrs r3, r3, #5 if (!last_gate) { 800078a: f010 00ff ands.w r0, r0, #255 ; 0xff gate = !HAL_GPIO_ReadPin(GATE_PORT, GATE_PIN); 800078e: 700b strb r3, [r1, #0] if (!last_gate) { 8000790: d103 bne.n 800079a OP1.ADSR.stage = RELEASE; OP1.ADSR.one_shot = 0; #else //OP1.phase_index = 0; //OP2.phase_index = 0; OP1.ADSR.stage = ATTACK; 8000792: 4905 ldr r1, [pc, #20] ; (80007a8 ) 8000794: 7708 strb r0, [r1, #28] //OP1.ADSR.output = 1.0f; OP1.ADSR.one_shot = 0; 8000796: f881 0048 strb.w r0, [r1, #72] ; 0x48 #endif } } last_gate = gate; 800079a: 7013 strb r3, [r2, #0] } 800079c: bd10 pop {r4, pc} 800079e: bf00 nop 80007a0: 200008ab .word 0x200008ab 80007a4: 2000088c .word 0x2000088c 80007a8: 2000083c .word 0x2000083c 080007ac : void set_adsr_parameters(soft_adsr *adsr) { adsr->rate_offset = 0.0005f; adsr->attack = 7.0f; filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007ac: 4a1a ldr r2, [pc, #104] ; (8000818 ) 80007ae: 491b ldr r1, [pc, #108] ; (800081c ) int16_t jin_offset; jin_offset = adc_data_10b[DECAY_SLIDER] - (adc_data_10b[DECAY_JACK] - 495); 80007b0: 8953 ldrh r3, [r2, #10] filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007b2: 8812 ldrh r2, [r2, #0] jin_offset = 0; } if (jin_offset > 1023) { jin_offset = 1023; } decay_sum = expo_lut[jin_offset] + 100.0f; 80007b4: ed9f 5a1a vldr s10, [pc, #104] ; 8000820 filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007b8: f831 c012 ldrh.w ip, [r1, r2, lsl #1] 80007bc: eddf 5a19 vldr s11, [pc, #100] ; 8000824 adsr->release = (decay_sum) / 100000.0f; 80007c0: ed9f 6a19 vldr s12, [pc, #100] ; 8000828 jin_offset = adc_data_10b[DECAY_SLIDER] - (adc_data_10b[DECAY_JACK] - 495); 80007c4: f203 13ef addw r3, r3, #495 ; 0x1ef 80007c8: 1a9b subs r3, r3, r2 80007ca: b21b sxth r3, r3 decay_sum = expo_lut[jin_offset] + 100.0f; 80007cc: f383 030a usat r3, #10, r3 filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007d0: 4a16 ldr r2, [pc, #88] ; (800082c ) decay_sum = expo_lut[jin_offset] + 100.0f; 80007d2: f831 3013 ldrh.w r3, [r1, r3, lsl #1] filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007d6: edd2 6a00 vldr s13, [r2] decay_sum = expo_lut[jin_offset] + 100.0f; 80007da: 4915 ldr r1, [pc, #84] ; (8000830 ) filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007dc: ee07 ca10 vmov s14, ip decay_sum = expo_lut[jin_offset] + 100.0f; 80007e0: ee07 3a90 vmov s15, r3 filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007e4: eeb8 7ac7 vcvt.f32.s32 s14, s14 decay_sum = expo_lut[jin_offset] + 100.0f; 80007e8: eef8 7ae7 vcvt.f32.s32 s15, s15 filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007ec: ee37 7a66 vsub.f32 s14, s14, s13 decay_sum = expo_lut[jin_offset] + 100.0f; 80007f0: ee77 7a85 vadd.f32 s15, s15, s10 filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 80007f4: eee7 6a25 vfma.f32 s13, s14, s11 void set_adsr_parameters(soft_adsr *adsr) { 80007f8: b410 push {r4} adsr->release = (decay_sum) / 100000.0f; 80007fa: ee27 7a86 vmul.f32 s14, s15, s12 adsr->rate_offset = 0.0005f; 80007fe: 4c0d ldr r4, [pc, #52] ; (8000834 ) adsr->attack = 7.0f; 8000800: 4b0d ldr r3, [pc, #52] ; (8000838 ) adsr->rate_offset = 0.0005f; 8000802: 60c4 str r4, [r0, #12] decay_sum = expo_lut[jin_offset] + 100.0f; 8000804: edc1 7a00 vstr s15, [r1] adsr->attack = 7.0f; 8000808: 6203 str r3, [r0, #32] } 800080a: f85d 4b04 ldr.w r4, [sp], #4 filtered_decay_jack += (expo_lut[adc_data_10b[DECAY_JACK]] - filtered_decay_jack) * 0.02f; 800080e: edc2 6a00 vstr s13, [r2] adsr->release = (decay_sum) / 100000.0f; 8000812: ed80 7a0b vstr s14, [r0, #44] ; 0x2c } 8000816: 4770 bx lr 8000818: 200008b4 .word 0x200008b4 800081c: 20000000 .word 0x20000000 8000820: 42c80000 .word 0x42c80000 8000824: 3ca3d70a .word 0x3ca3d70a 8000828: 3727c5ac .word 0x3727c5ac 800082c: 20000890 .word 0x20000890 8000830: 200008ac .word 0x200008ac 8000834: 3a03126f .word 0x3a03126f 8000838: 40e00000 .word 0x40e00000 0800083c : set_adsr_parameters(&OP1.ADSR); } //fast interrupt for audio void main_2OP_loop() { 800083c: b5f8 push {r3, r4, r5, r6, r7, lr} ENV_OFFSET += (((((960 - adc_data_10b[FM_JACK]) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 800083e: 4c95 ldr r4, [pc, #596] ; (8000a94 ) 8000840: 4a95 ldr r2, [pc, #596] ; (8000a98 ) 8000842: 8863 ldrh r3, [r4, #2] 8000844: edd2 7a00 vldr s15, [r2] 8000848: ed9f 5a94 vldr s10, [pc, #592] ; 8000a9c 800084c: eddf 5a94 vldr s11, [pc, #592] ; 8000aa0 ENV_AMT = (adc_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 8000850: 8921 ldrh r1, [r4, #8] 8000852: ed9f 6a94 vldr s12, [pc, #592] ; 8000aa4 ENV_OFFSET += (((((960 - adc_data_10b[FM_JACK]) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 8000856: f5c3 73e0 rsb r3, r3, #448 ; 0x1c0 800085a: ee07 3a10 vmov s14, r3 800085e: eeb8 7ac7 vcvt.f32.s32 s14, s14 8000862: eef0 4a67 vmov.f32 s9, s15 8000866: eed7 4a05 vfnms.f32 s9, s14, s10 ENV_AMT = (adc_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 800086a: ee06 1a90 vmov s13, r1 ENV_OFFSET += (((((960 - adc_data_10b[FM_JACK]) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 800086e: eee4 7aa5 vfma.f32 s15, s9, s11 ENV_AMT = (adc_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 8000872: eef8 6ae6 vcvt.f32.s32 s13, s13 8000876: eeb0 7a67 vmov.f32 s14, s15 800087a: eea6 7a86 vfma.f32 s14, s13, s12 ENV_OFFSET += (((((960 - adc_data_10b[FM_JACK]) - 512)) / 512.0f) - ENV_OFFSET) * 0.01f; 800087e: edc2 7a00 vstr s15, [r2] if (ENV_AMT < 0.0f) { 8000882: eeb5 7ac0 vcmpe.f32 s14, #0.0 8000886: eef1 fa10 vmrs APSR_nzcv, fpscr 800088a: f100 80f8 bmi.w 8000a7e ENV_AMT = (adc_data_10b[FM_SLIDER] / 1600.0f) + ENV_OFFSET; 800088e: 4e86 ldr r6, [pc, #536] ; (8000aa8 ) 8000890: ed86 7a00 vstr s14, [r6] khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; #ifdef KHZ_PRE_FILTER //khz input, 1p filter filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 8000894: 4a85 ldr r2, [pc, #532] ; (8000aac ) khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 8000896: 88e3 ldrh r3, [r4, #6] filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 8000898: 8812 ldrh r2, [r2, #0] 800089a: 4985 ldr r1, [pc, #532] ; (8000ab0 ) khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 800089c: 4d85 ldr r5, [pc, #532] ; (8000ab4 ) filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 800089e: ed91 0a00 vldr s0, [r1] khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008a2: edd5 6a00 vldr s13, [r5] 80008a6: ed9f 6a84 vldr s12, [pc, #528] ; 8000ab8 //khz input, 2p adaptive filter khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; 80008aa: 4884 ldr r0, [pc, #528] ; (8000abc ) #else //khz input, 2p adaptive filter khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (voct_data[0] - 2048)) * KHZ_IN_SCALING; #endif freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 80008ac: 4f84 ldr r7, [pc, #528] ; (8000ac0 ) khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008ae: f5c3 737f rsb r3, r3, #1020 ; 0x3fc filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008b2: f5a2 6200 sub.w r2, r2, #2048 ; 0x800 khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008b6: 3303 adds r3, #3 filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008b8: ee07 2a10 vmov s14, r2 khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008bc: ee07 3a90 vmov s15, r3 filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008c0: eeb8 7ac7 vcvt.f32.s32 s14, s14 khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008c4: eef8 7ae7 vcvt.f32.s32 s15, s15 filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008c8: ee37 7a40 vsub.f32 s14, s14, s0 khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008cc: ee77 7ae6 vsub.f32 s15, s15, s13 filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008d0: eea7 0a06 vfma.f32 s0, s14, s12 khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008d4: eee7 6a86 vfma.f32 s13, s15, s12 filtered_khz_in += ((voct_data[0] - 2048) - filtered_khz_in) * 0.05f; 80008d8: ed81 0a00 vstr s0, [r1] khz_pot += ((1023 - adc_data_10b[KHZ_POT]) - khz_pot) * 0.05f; 80008dc: edc5 6a00 vstr s13, [r5] khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; 80008e0: f000 f93e bl 8000b60 80008e4: 4b77 ldr r3, [pc, #476] ; (8000ac4 ) //filtered fm ratio fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 80008e6: 4a78 ldr r2, [pc, #480] ; (8000ac8 ) khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; 80008e8: ed93 7a00 vldr s14, [r3] fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 80008ec: 88a3 ldrh r3, [r4, #4] 80008ee: ed92 6a00 vldr s12, [r2] freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 80008f2: edd7 5a00 vldr s11, [r7] 80008f6: ed95 5a00 vldr s10, [r5] fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 80008fa: eddf 3a74 vldr s7, [pc, #464] ; 8000acc freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 80008fe: ed9f 4a74 vldr s8, [pc, #464] ; 8000ad0 fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000902: eddf 4a67 vldr s9, [pc, #412] ; 8000aa0 OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); if (adc_data_10b[DECAY_SLIDER] > 1000) { 8000906: f8b4 c00a ldrh.w ip, [r4, #10] OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 800090a: 4c72 ldr r4, [pc, #456] ; (8000ad4 ) OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 800090c: eddf 6a72 vldr s13, [pc, #456] ; 8000ad8 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 8000910: eddf 7a72 vldr s15, [pc, #456] ; 8000adc OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 8000914: 4972 ldr r1, [pc, #456] ; (8000ae0 ) OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 8000916: 4873 ldr r0, [pc, #460] ; (8000ae4 ) khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; 8000918: eeb5 3a00 vmov.f32 s6, #80 ; 0x3e800000 0.250 800091c: ee27 7a03 vmul.f32 s14, s14, s6 fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000920: eeb0 3a46 vmov.f32 s6, s12 khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; 8000924: ee27 0a00 vmul.f32 s0, s14, s0 fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000928: ee07 3a10 vmov s14, r3 800092c: eeb8 7ac7 vcvt.f32.s32 s14, s14 freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 8000930: ee35 5a65 vsub.f32 s10, s10, s11 fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000934: ee97 3a23 vfnms.f32 s6, s14, s7 khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; 8000938: 4b6b ldr r3, [pc, #428] ; (8000ae8 ) freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 800093a: ee35 5a00 vadd.f32 s10, s10, s0 fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 800093e: eea3 6a24 vfma.f32 s12, s6, s9 if (adc_data_10b[DECAY_SLIDER] > 1000) { 8000942: f5bc 7f7a cmp.w ip, #1000 ; 0x3e8 freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 8000946: eee5 5a04 vfma.f32 s11, s10, s8 fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 800094a: eeb0 7a46 vmov.f32 s14, s12 OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 800094e: eebc 6ae5 vcvt.u32.f32 s12, s11 khz_in = dynamic_smooth_tick(&dynamic_smooth_a, (filtered_khz_in)) * KHZ_IN_SCALING * khz_correction; 8000952: ed83 0a00 vstr s0, [r3] OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 8000956: ee16 3a10 vmov r3, s12 800095a: f3c3 0309 ubfx r3, r3, #0, #10 OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 800095e: ee67 6a26 vmul.f32 s13, s14, s13 OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 8000962: f834 3013 ldrh.w r3, [r4, r3, lsl #1] fm_ratio += ((adc_data_10b[RATIO_POT] / 2047.0f) - fm_ratio) * 0.01f; 8000966: ed82 7a00 vstr s14, [r2] OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 800096a: ee06 3a10 vmov s12, r3 800096e: eeb8 6a46 vcvt.f32.u32 s12, s12 freqSum += ((khz_in + khz_pot) - freqSum) * 0.08f; 8000972: edc7 5a00 vstr s11, [r7] OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 8000976: ee66 6a86 vmul.f32 s13, s13, s12 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 800097a: ee26 7a27 vmul.f32 s14, s12, s15 OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); 800097e: ee66 7aa7 vmul.f32 s15, s13, s15 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 8000982: eebc 7ac7 vcvt.u32.f32 s14, s14 OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); 8000986: eefc 7ae7 vcvt.u32.f32 s15, s15 OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 800098a: ee17 5a10 vmov r5, s14 OP2.phase_increment = ((42949.6710f) * (OP2.frequency)); 800098e: ee17 4a90 vmov r4, s15 8000992: edc0 7a03 vstr s15, [r0, #12] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000996: edd1 7a05 vldr s15, [r1, #20] OP1.phase_increment = ((42949.6710f) * (OP1.frequency)); 800099a: ed81 7a03 vstr s14, [r1, #12] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 800099e: eeb8 7ae7 vcvt.f32.s32 s14, s15 80009a2: edd0 7a05 vldr s15, [r0, #20] OP1.frequency = expo_lut[(uint16_t) (freqSum) & 1023]; 80009a6: ed81 6a02 vstr s12, [r1, #8] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009aa: ed96 6a00 vldr s12, [r6] OP->phase_index += OP->phase_increment; 80009ae: 690f ldr r7, [r1, #16] 80009b0: 6906 ldr r6, [r0, #16] OP2.frequency = OP1.frequency * (fm_ratio * 32.0f); 80009b2: edc0 6a02 vstr s13, [r0, #8] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009b6: eef8 7ae7 vcvt.f32.s32 s15, s15 80009ba: ee27 7a06 vmul.f32 s14, s14, s12 80009be: ee67 7a86 vmul.f32 s15, s15, s12 80009c2: eebd 7ac7 vcvt.s32.f32 s14, s14 80009c6: eefd 7ae7 vcvt.s32.f32 s15, s15 OP1.ADSR.output = 1.0f; 80009ca: bf88 it hi 80009cc: f04f 537e movhi.w r3, #1065353216 ; 0x3f800000 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009d0: ee17 2a10 vmov r2, s14 OP1.ADSR.output = 1.0f; 80009d4: bf88 it hi 80009d6: 618b strhi r3, [r1, #24] OP->phase_index += OP->phase_increment; 80009d8: 443d add r5, r7 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009da: ee17 3a90 vmov r3, s15 OP->phase_index += OP->phase_increment; 80009de: 4434 add r4, r6 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009e0: eb02 5295 add.w r2, r2, r5, lsr #22 80009e4: 4e41 ldr r6, [pc, #260] ; (8000aec ) } operator_run(&OP1, OP1.ADSR.output); 80009e6: edd1 5a06 vldr s11, [r1, #24] operator_run(&OP2, OP1.ADSR.output * OP1.ADSR.output); 80009ea: edd1 6a06 vldr s13, [r1, #24] 80009ee: ed91 5a06 vldr s10, [r1, #24] OP->phase_index += OP->phase_increment; 80009f2: 6104 str r4, [r0, #16] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 80009f4: eb03 5394 add.w r3, r3, r4, lsr #22 80009f8: f3c2 0209 ubfx r2, r2, #0, #10 80009fc: f3c3 0309 ubfx r3, r3, #0, #10 8000a00: f836 2012 ldrh.w r2, [r6, r2, lsl #1] 8000a04: f836 3013 ldrh.w r3, [r6, r3, lsl #1] OP1.modulation = (OP2.output) >> 3; //original voice1 = (OP1.output) >> 5; 8000a08: 4e39 ldr r6, [pc, #228] ; (8000af0 ) OP->phase_index += OP->phase_increment; 8000a0a: 610d str r5, [r1, #16] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a0c: f5a2 4200 sub.w r2, r2, #32768 ; 0x8000 8000a10: ee07 2a10 vmov s14, r2 8000a14: f5a3 4300 sub.w r3, r3, #32768 ; 0x8000 8000a18: ee07 3a90 vmov s15, r3 8000a1c: eeb8 7ac7 vcvt.f32.s32 s14, s14 8000a20: eef8 7ae7 vcvt.f32.s32 s15, s15 operator_run(&OP2, OP1.ADSR.output * OP1.ADSR.output); 8000a24: ee66 6a85 vmul.f32 s13, s13, s10 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a28: ee27 7a25 vmul.f32 s14, s14, s11 8000a2c: ee67 7aa6 vmul.f32 s15, s15, s13 8000a30: eebd 7ac7 vcvt.s32.f32 s14, s14 8000a34: eefd 7ae7 vcvt.s32.f32 s15, s15 8000a38: ee17 2a10 vmov r2, s14 8000a3c: ee17 3a90 vmov r3, s15 voice1 = (OP1.output) >> 5; 8000a40: 1154 asrs r4, r2, #5 OP1.modulation = (OP2.output) >> 3; 8000a42: 10dd asrs r5, r3, #3 output = voice1; //hard clipping if (output > 2047) { 8000a44: f5b4 6f00 cmp.w r4, #2048 ; 0x800 OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a48: ed81 7a00 vstr s14, [r1] voice1 = (OP1.output) >> 5; 8000a4c: 6034 str r4, [r6, #0] OP->output = (big_sine_wave[((OP->phase_index >> 22) + (int32_t) (OP->modulation * ENV_AMT)) & 1023] - 32768) * envelope; 8000a4e: edc0 7a00 vstr s15, [r0] OP1.modulation = (OP2.output) >> 3; 8000a52: 614d str r5, [r1, #20] if (output > 2047) { 8000a54: db09 blt.n 8000a6a output = 2047; 8000a56: 4b27 ldr r3, [pc, #156] ; (8000af4 ) 8000a58: f240 72ff movw r2, #2047 ; 0x7ff 8000a5c: 601a str r2, [r3, #0] 8000a5e: f640 70ff movw r0, #4095 ; 0xfff output = -2047; } //DAC output dac1_ch1((output) + 2048); } 8000a62: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} dac1_ch1((output) + 2048); 8000a66: f000 b859 b.w 8000b1c if (output < -2047) { 8000a6a: 4b23 ldr r3, [pc, #140] ; (8000af8 ) 8000a6c: 429c cmp r4, r3 8000a6e: da0a bge.n 8000a86 output = -2047; 8000a70: 4a20 ldr r2, [pc, #128] ; (8000af4 ) 8000a72: 2001 movs r0, #1 8000a74: 6013 str r3, [r2, #0] } 8000a76: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} dac1_ch1((output) + 2048); 8000a7a: f000 b84f b.w 8000b1c ENV_AMT = 0.0f; 8000a7e: 4e0a ldr r6, [pc, #40] ; (8000aa8 ) 8000a80: 2100 movs r1, #0 8000a82: 6031 str r1, [r6, #0] 8000a84: e706 b.n 8000894 output = voice1; 8000a86: 4b1b ldr r3, [pc, #108] ; (8000af4 ) 8000a88: f504 6000 add.w r0, r4, #2048 ; 0x800 8000a8c: 601c str r4, [r3, #0] 8000a8e: b280 uxth r0, r0 8000a90: e7e7 b.n 8000a62 8000a92: bf00 nop 8000a94: 200008b4 .word 0x200008b4 8000a98: 20000834 .word 0x20000834 8000a9c: 3b000000 .word 0x3b000000 8000aa0: 3c23d70a .word 0x3c23d70a 8000aa4: 3a23d70a .word 0x3a23d70a 8000aa8: 20000838 .word 0x20000838 8000aac: 20000b5c .word 0x20000b5c 8000ab0: 20000b04 .word 0x20000b04 8000ab4: 20000894 .word 0x20000894 8000ab8: 3d4ccccd .word 0x3d4ccccd 8000abc: 20000adc .word 0x20000adc 8000ac0: 200008a0 .word 0x200008a0 8000ac4: 200008a4 .word 0x200008a4 8000ac8: 200008c0 .word 0x200008c0 8000acc: 3a001002 .word 0x3a001002 8000ad0: 3da3d70a .word 0x3da3d70a 8000ad4: 20000000 .word 0x20000000 8000ad8: 42000000 .word 0x42000000 8000adc: 4727c5ac .word 0x4727c5ac 8000ae0: 2000083c .word 0x2000083c 8000ae4: 20000b0c .word 0x20000b0c 8000ae8: 2000082c .word 0x2000082c 8000aec: 080024d0 .word 0x080024d0 8000af0: 20000b00 .word 0x20000b00 8000af4: 20000898 .word 0x20000898 8000af8: fffff801 .word 0xfffff801 08000afc : uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8000afc: f44f 2370 mov.w r3, #983040 ; 0xf0000 8000b00: fa93 f3a3 rbit r3, r3 */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); MODIFY_REG(*preg, 8000b04: 4904 ldr r1, [pc, #16] ; (8000b18 ) 8000b06: 688b ldr r3, [r1, #8] 8000b08: f423 637f bic.w r3, r3, #4080 ; 0xff0 8000b0c: f023 030f bic.w r3, r3, #15 8000b10: 4318 orrs r0, r3 8000b12: 6088 str r0, [r1, #8] #include "dac.h" #include "main.h" inline void dac2_ch1(uint16_t _out_val) { LL_DAC_ConvertData12RightAligned(DAC2, LL_DAC_CHANNEL_1, _out_val); } 8000b14: 4770 bx lr 8000b16: bf00 nop 8000b18: 40009800 .word 0x40009800 08000b1c : 8000b1c: f44f 2370 mov.w r3, #983040 ; 0xf0000 8000b20: fa93 f3a3 rbit r3, r3 8000b24: 4904 ldr r1, [pc, #16] ; (8000b38 ) 8000b26: 688b ldr r3, [r1, #8] 8000b28: f423 637f bic.w r3, r3, #4080 ; 0xff0 8000b2c: f023 030f bic.w r3, r3, #15 8000b30: 4318 orrs r0, r3 8000b32: 6088 str r0, [r1, #8] inline void dac1_ch1(uint16_t _out_val) { LL_DAC_ConvertData12RightAligned(DAC1, LL_DAC_CHANNEL_1, _out_val); } 8000b34: 4770 bx lr 8000b36: bf00 nop 8000b38: 40007400 .word 0x40007400 08000b3c : sensitivity = _sensitivity; wc = basefreq / 22050.0f; //gc = tan(3.14f * wc); gc = .00000712018209f; _smooth->g0 = 2*gc/(1+gc); _smooth->sense = sensitivity * 4.0f; 8000b3c: eef1 7a00 vmov.f32 s15, #16 ; 0x40800000 4.0 8000b40: ee60 0aa7 vmul.f32 s1, s1, s15 //tick values _smooth->low1 = 0.0f; 8000b44: 2300 movs r3, #0 _smooth->g0 = 2*gc/(1+gc); 8000b46: 4a05 ldr r2, [pc, #20] ; (8000b5c ) 8000b48: 6002 str r2, [r0, #0] _smooth->sense = sensitivity * 4.0f; 8000b4a: edc0 0a01 vstr s1, [r0, #4] _smooth->low1 = 0.0f; 8000b4e: 6083 str r3, [r0, #8] _smooth->low2 = 0.0f; 8000b50: 60c3 str r3, [r0, #12] _smooth->low1z = 0.0f; 8000b52: 6103 str r3, [r0, #16] _smooth->low2z = 0.0f; 8000b54: 6143 str r3, [r0, #20] _smooth->bandz = 0.0f; 8000b56: 6183 str r3, [r0, #24] _smooth->out = 0.0f; 8000b58: 61c3 str r3, [r0, #28] } 8000b5a: 4770 bx lr 8000b5c: 376ee976 .word 0x376ee976 08000b60 : float dynamic_smooth_tick(dynamic_smooth* _smooth, float in) { float g; _smooth->low1z = _smooth->low1; 8000b60: ed90 7a02 vldr s14, [r0, #8] _smooth->low2z = _smooth->low2; 8000b64: edd0 7a03 vldr s15, [r0, #12] _smooth->bandz = _smooth->low2z - _smooth->low1z; g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); 8000b68: ed90 5a01 vldr s10, [r0, #4] 8000b6c: edd0 6a00 vldr s13, [r0] _smooth->low1z = _smooth->low1; 8000b70: ed80 7a04 vstr s14, [r0, #16] _smooth->bandz = _smooth->low2z - _smooth->low1z; 8000b74: ee37 6ac7 vsub.f32 s12, s15, s14 return ((a) < (b) ? a : b); 8000b78: eef7 5a00 vmov.f32 s11, #112 ; 0x3f800000 1.0 g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); 8000b7c: eef0 4ac6 vabs.f32 s9, s12 8000b80: eee4 6a85 vfma.f32 s13, s9, s10 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8000b84: ee30 0a47 vsub.f32 s0, s0, s14 return ((a) < (b) ? a : b); 8000b88: eef4 6ae5 vcmpe.f32 s13, s11 8000b8c: eef1 fa10 vmrs APSR_nzcv, fpscr 8000b90: bf88 it hi 8000b92: eef0 6a65 vmovhi.f32 s13, s11 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8000b96: eea0 7a26 vfma.f32 s14, s0, s13 _smooth->low2z = _smooth->low2; 8000b9a: edc0 7a05 vstr s15, [r0, #20] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 8000b9e: ee77 5a67 vsub.f32 s11, s14, s15 _smooth->bandz = _smooth->low2z - _smooth->low1z; 8000ba2: ed80 6a06 vstr s12, [r0, #24] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 8000ba6: eee5 7aa6 vfma.f32 s15, s11, s13 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8000baa: ed80 7a02 vstr s14, [r0, #8] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 8000bae: eeb0 0a67 vmov.f32 s0, s15 8000bb2: edc0 7a03 vstr s15, [r0, #12] return _smooth->low2; } 8000bb6: 4770 bx lr 08000bb8 : */ #include "loop.h" #include "main.h" void loop(void) { 8000bb8: b538 push {r3, r4, r5, lr} //dac1_ch1(ramp); dac2_ch1(2047); 8000bba: f240 70ff movw r0, #2047 ; 0x7ff 8000bbe: f7ff ff9d bl 8000afc vdd_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(adc_data[6],LL_ADC_RESOLUTION_12B); 8000bc2: 4911 ldr r1, [pc, #68] ; (8000c08 ) vdd_cal = (uint32_t)(*VREFINT_CAL_ADDR); khz_correction = vdd_mv / 3300.0f; khz_in_mv = voct_data[0] * 3300 >> 12; 8000bc4: 4b11 ldr r3, [pc, #68] ; (8000c0c ) vdd_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(adc_data[6],LL_ADC_RESOLUTION_12B); 8000bc6: 880a ldrh r2, [r1, #0] 8000bc8: 4811 ldr r0, [pc, #68] ; (8000c10 ) khz_in_mv = voct_data[0] * 3300 >> 12; 8000bca: 881c ldrh r4, [r3, #0] vdd_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(adc_data[6],LL_ADC_RESOLUTION_12B); 8000bcc: 8985 ldrh r5, [r0, #12] khz_correction = vdd_mv / 3300.0f; 8000bce: ed9f 7a11 vldr s14, [pc, #68] ; 8000c14 vdd_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(adc_data[6],LL_ADC_RESOLUTION_12B); 8000bd2: 4811 ldr r0, [pc, #68] ; (8000c18 ) 8000bd4: f640 43e4 movw r3, #3300 ; 0xce4 8000bd8: fb03 f202 mul.w r2, r3, r2 8000bdc: fbb2 f2f5 udiv r2, r2, r5 khz_correction = vdd_mv / 3300.0f; 8000be0: b295 uxth r5, r2 8000be2: ee07 5a90 vmov s15, r5 8000be6: eef8 7ae7 vcvt.f32.s32 s15, s15 vdd_mv = __LL_ADC_CALC_VREFANALOG_VOLTAGE(adc_data[6],LL_ADC_RESOLUTION_12B); 8000bea: 8002 strh r2, [r0, #0] vdd_cal = (uint32_t)(*VREFINT_CAL_ADDR); 8000bec: 4d0b ldr r5, [pc, #44] ; (8000c1c ) khz_in_mv = voct_data[0] * 3300 >> 12; 8000bee: 480c ldr r0, [pc, #48] ; (8000c20 ) khz_correction = vdd_mv / 3300.0f; 8000bf0: 4a0c ldr r2, [pc, #48] ; (8000c24 ) vdd_cal = (uint32_t)(*VREFINT_CAL_ADDR); 8000bf2: 8809 ldrh r1, [r1, #0] 8000bf4: 6029 str r1, [r5, #0] khz_correction = vdd_mv / 3300.0f; 8000bf6: ee67 7a87 vmul.f32 s15, s15, s14 khz_in_mv = voct_data[0] * 3300 >> 12; 8000bfa: fb03 f304 mul.w r3, r3, r4 8000bfe: 131b asrs r3, r3, #12 8000c00: 8003 strh r3, [r0, #0] khz_correction = vdd_mv / 3300.0f; 8000c02: edc2 7a00 vstr s15, [r2] } 8000c06: bd38 pop {r3, r4, r5, pc} 8000c08: 1ffff7ba .word 0x1ffff7ba 8000c0c: 20000b5c .word 0x20000b5c 8000c10: 200008c4 .word 0x200008c4 8000c14: 399ee00a .word 0x399ee00a 8000c18: 2000088e .word 0x2000088e 8000c1c: 20000afc .word 0x20000afc 8000c20: 20000830 .word 0x20000830 8000c24: 200008a4 .word 0x200008a4 08000c28 : * @arg @ref LL_FLASH_LATENCY_2 * @retval None */ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) { MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 8000c28: 4929 ldr r1, [pc, #164] ; (8000cd0 ) * @rmtoll CR HSION LL_RCC_HSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_HSI_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSION); 8000c2a: 4b2a ldr r3, [pc, #168] ; (8000cd4 ) 8000c2c: 680a ldr r2, [r1, #0] 8000c2e: f022 0207 bic.w r2, r2, #7 8000c32: f042 0202 orr.w r2, r2, #2 /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000c36: b510 push {r4, lr} 8000c38: 600a str r2, [r1, #0] * @arg @ref LL_FLASH_LATENCY_1 * @arg @ref LL_FLASH_LATENCY_2 */ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) { return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); 8000c3a: 680a ldr r2, [r1, #0] 8000c3c: 681a ldr r2, [r3, #0] 8000c3e: f042 0201 orr.w r2, r2, #1 8000c42: 601a str r2, [r3, #0] * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); 8000c44: 681a ldr r2, [r3, #0] Error_Handler(); } LL_RCC_HSI_Enable(); /* Wait till HSI is ready */ while (LL_RCC_HSI_IsReady() != 1) { 8000c46: 0792 lsls r2, r2, #30 8000c48: d5fc bpl.n 8000c44 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F * @retval None */ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) { MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); 8000c4a: 6819 ldr r1, [r3, #0] * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 8000c4c: 4a21 ldr r2, [pc, #132] ; (8000cd4 ) MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); 8000c4e: f021 01f8 bic.w r1, r1, #248 ; 0xf8 8000c52: f041 0180 orr.w r1, r1, #128 ; 0x80 8000c56: 6019 str r1, [r3, #0] * @arg @ref LL_RCC_PLL_MUL_16 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); 8000c58: 6859 ldr r1, [r3, #4] 8000c5a: f421 1174 bic.w r1, r1, #3997696 ; 0x3d0000 8000c5e: f441 1160 orr.w r1, r1, #3670016 ; 0x380000 8000c62: 6059 str r1, [r3, #4] MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); 8000c64: 6ad9 ldr r1, [r3, #44] ; 0x2c 8000c66: f021 010f bic.w r1, r1, #15 8000c6a: 62d9 str r1, [r3, #44] ; 0x2c SET_BIT(RCC->CR, RCC_CR_PLLON); 8000c6c: 6819 ldr r1, [r3, #0] 8000c6e: f041 7180 orr.w r1, r1, #16777216 ; 0x1000000 8000c72: 6019 str r1, [r3, #0] return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 8000c74: 6813 ldr r3, [r2, #0] LL_RCC_HSI_SetCalibTrimming(16); LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_16); LL_RCC_PLL_Enable(); /* Wait till PLL is ready */ while (LL_RCC_PLL_IsReady() != 1) { 8000c76: 019b lsls r3, r3, #6 8000c78: d5fc bpl.n 8000c74 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 8000c7a: 6853 ldr r3, [r2, #4] return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 8000c7c: 4c15 ldr r4, [pc, #84] ; (8000cd4 ) MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 8000c7e: f023 03f0 bic.w r3, r3, #240 ; 0xf0 8000c82: 6053 str r3, [r2, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 8000c84: 6853 ldr r3, [r2, #4] 8000c86: f423 63e0 bic.w r3, r3, #1792 ; 0x700 8000c8a: f443 6380 orr.w r3, r3, #1024 ; 0x400 8000c8e: 6053 str r3, [r2, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 8000c90: 6853 ldr r3, [r2, #4] 8000c92: f423 5360 bic.w r3, r3, #14336 ; 0x3800 8000c96: 6053 str r3, [r2, #4] MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 8000c98: 6853 ldr r3, [r2, #4] 8000c9a: f023 0303 bic.w r3, r3, #3 8000c9e: f043 0302 orr.w r3, r3, #2 8000ca2: 6053 str r3, [r2, #4] return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 8000ca4: 6863 ldr r3, [r4, #4] 8000ca6: f003 030c and.w r3, r3, #12 LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2); LL_RCC_SetAPB2Prescaler(LL_RCC_APB1_DIV_1); LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); /* Wait till System clock is ready */ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) { 8000caa: 2b08 cmp r3, #8 8000cac: d1fa bne.n 8000ca4 } LL_SetSystemCoreClock(64000000); 8000cae: 480a ldr r0, [pc, #40] ; (8000cd8 ) 8000cb0: f001 fbd8 bl 8002464 /* Update the time base */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { 8000cb4: 2000 movs r0, #0 8000cb6: f000 fc19 bl 80014ec MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU)); 8000cba: 6b23 ldr r3, [r4, #48] ; 0x30 8000cbc: f423 7380 bic.w r3, r3, #256 ; 0x100 8000cc0: 6323 str r3, [r4, #48] ; 0x30 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource); 8000cc2: 6ae3 ldr r3, [r4, #44] ; 0x2c 8000cc4: f423 73f8 bic.w r3, r3, #496 ; 0x1f0 8000cc8: f443 7380 orr.w r3, r3, #256 ; 0x100 8000ccc: 62e3 str r3, [r4, #44] ; 0x2c Error_Handler(); }; LL_RCC_SetTIMClockSource(LL_RCC_TIM1_CLKSOURCE_PCLK2); LL_RCC_SetADCClockSource(LL_RCC_ADC12_CLKSRC_PLL_DIV_1); } 8000cce: bd10 pop {r4, pc} 8000cd0: 40022000 .word 0x40022000 8000cd4: 40021000 .word 0x40021000 8000cd8: 03d09000 .word 0x03d09000 08000cdc
: int main(void) { 8000cdc: e92d 4880 stmdb sp!, {r7, fp, lr} * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; 8000ce0: 2400 movs r4, #0 int main(void) { 8000ce2: b095 sub sp, #84 ; 0x54 HAL_Init(); 8000ce4: f000 fc26 bl 8001534 SystemClock_Config(); 8000ce8: f7ff ff9e bl 8000c28 LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; 8000cec: e9cd 4412 strd r4, r4, [sp, #72] ; 0x48 8000cf0: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, Periphs); 8000cf4: 4dc9 ldr r5, [pc, #804] ; (800101c ) hadc1.Init.DiscontinuousConvMode = DISABLE; 8000cf6: 4eca ldr r6, [pc, #808] ; (8001020 ) 8000cf8: 696a ldr r2, [r5, #20] LL_DAC_Init(DAC2, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000cfa: f8df b33c ldr.w fp, [pc, #828] ; 8001038 \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000cfe: f8df a33c ldr.w sl, [pc, #828] ; 800103c 8000d02: f442 3200 orr.w r2, r2, #131072 ; 0x20000 8000d06: 616a str r2, [r5, #20] /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, Periphs); 8000d08: 696a ldr r2, [r5, #20] 8000d0a: f402 3200 and.w r2, r2, #131072 ; 0x20000 8000d0e: 9208 str r2, [sp, #32] (void)tmpreg; 8000d10: 9a08 ldr r2, [sp, #32] SET_BIT(RCC->AHBENR, Periphs); 8000d12: 696a ldr r2, [r5, #20] 8000d14: f442 2280 orr.w r2, r2, #262144 ; 0x40000 8000d18: 616a str r2, [r5, #20] tmpreg = READ_BIT(RCC->AHBENR, Periphs); 8000d1a: 696a ldr r2, [r5, #20] 8000d1c: f402 2280 and.w r2, r2, #262144 ; 0x40000 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOB); /**/ GPIO_InitStruct.Pin = LL_GPIO_PIN_7; GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; 8000d20: 2701 movs r7, #1 8000d22: 9209 str r2, [sp, #36] ; 0x24 LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000d24: a90e add r1, sp, #56 ; 0x38 GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 8000d26: f04f 0880 mov.w r8, #128 ; 0x80 8000d2a: f04f 0900 mov.w r9, #0 LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000d2e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = LL_GPIO_PIN_7; 8000d32: e9cd 890e strd r8, r9, [sp, #56] ; 0x38 (void)tmpreg; 8000d36: 9a09 ldr r2, [sp, #36] ; 0x24 GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; 8000d38: 9712 str r7, [sp, #72] ; 0x48 LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000d3a: f001 fa9b bl 8002274 __HAL_RCC_DMA1_CLK_ENABLE(); 8000d3e: 696a ldr r2, [r5, #20] 8000d40: 433a orrs r2, r7 8000d42: 616a str r2, [r5, #20] 8000d44: 696a ldr r2, [r5, #20] 8000d46: 403a ands r2, r7 8000d48: 9207 str r2, [sp, #28] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8000d4a: 4621 mov r1, r4 8000d4c: 4622 mov r2, r4 8000d4e: 200b movs r0, #11 __HAL_RCC_DMA1_CLK_ENABLE(); 8000d50: f8dd c01c ldr.w ip, [sp, #28] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 8000d54: f001 f85a bl 8001e0c HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8000d58: 200b movs r0, #11 8000d5a: f001 f88f bl 8001e7c HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); 8000d5e: 4622 mov r2, r4 8000d60: 4621 mov r1, r4 8000d62: 200c movs r0, #12 8000d64: f001 f852 bl 8001e0c HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 8000d68: 200c movs r0, #12 8000d6a: f001 f887 bl 8001e7c hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000d6e: f44f 6280 mov.w r2, #1024 ; 0x400 hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 8000d72: f44f 7080 mov.w r0, #256 ; 0x100 hadc1.Init.NbrOfConversion = 7; 8000d76: f04f 0c07 mov.w ip, #7 hadc1.Instance = ADC1; 8000d7a: f04f 41a0 mov.w r1, #1342177280 ; 0x50000000 hadc1.Init.LowPowerAutoWait = DISABLE; 8000d7e: 8334 strh r4, [r6, #24] hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000d80: 62f2 str r2, [r6, #44] ; 0x2c hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T3_TRGO; 8000d82: 62b0 str r0, [r6, #40] ; 0x28 hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000d84: 2208 movs r2, #8 if (HAL_ADC_Init(&hadc1) != HAL_OK) { 8000d86: 4630 mov r0, r6 hadc1.Init.NbrOfConversion = 7; 8000d88: f8c6 c01c str.w ip, [r6, #28] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000d8c: 6172 str r2, [r6, #20] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000d8e: e9c6 4703 strd r4, r7, [r6, #12] hadc1.Init.Resolution = ADC_RESOLUTION_12B; 8000d92: e9c6 4401 strd r4, r4, [r6, #4] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000d96: f886 4020 strb.w r4, [r6, #32] hadc1.Init.DMAContinuousRequests = ENABLE; 8000d9a: f886 7030 strb.w r7, [r6, #48] ; 0x30 hadc1.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; 8000d9e: 6374 str r4, [r6, #52] ; 0x34 hadc1.Instance = ADC1; 8000da0: 6031 str r1, [r6, #0] ADC_ChannelConfTypeDef sConfig = { 0 }; 8000da2: e9cd 440e strd r4, r4, [sp, #56] ; 0x38 8000da6: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 8000daa: e9cd 4412 strd r4, r4, [sp, #72] ; 0x48 ADC_MultiModeTypeDef multimode = { 0 }; 8000dae: e9cd 440b strd r4, r4, [sp, #44] ; 0x2c 8000db2: 940a str r4, [sp, #40] ; 0x28 sConfig.Channel = ADC_CHANNEL_1; 8000db4: f04f 0801 mov.w r8, #1 if (HAL_ADC_Init(&hadc1) != HAL_OK) { 8000db8: f000 fc80 bl 80016bc sConfig.Channel = ADC_CHANNEL_1; 8000dbc: f04f 0901 mov.w r9, #1 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) { 8000dc0: a90a add r1, sp, #40 ; 0x28 8000dc2: 4630 mov r0, r6 multimode.Mode = ADC_MODE_INDEPENDENT; 8000dc4: 940a str r4, [sp, #40] ; 0x28 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) { 8000dc6: f000 ff9b bl 8001d00 sConfig.Channel = ADC_CHANNEL_1; 8000dca: e9cd 890e strd r8, r9, [sp, #56] ; 0x38 8000dce: f04f 0807 mov.w r8, #7 8000dd2: f04f 0900 mov.w r9, #0 8000dd6: e9cd 8910 strd r8, r9, [sp, #64] ; 0x40 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000dda: a90e add r1, sp, #56 ; 0x38 8000ddc: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_1; 8000dde: f04f 0800 mov.w r8, #0 8000de2: f04f 0900 mov.w r9, #0 8000de6: e9cd 8912 strd r8, r9, [sp, #72] ; 0x48 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000dea: f000 fdf1 bl 80019d0 sConfig.Channel = ADC_CHANNEL_2; 8000dee: f04f 0802 mov.w r8, #2 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000df2: a90e add r1, sp, #56 ; 0x38 8000df4: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_2; 8000df6: f04f 0902 mov.w r9, #2 8000dfa: e9cd 890e strd r8, r9, [sp, #56] ; 0x38 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000dfe: f000 fde7 bl 80019d0 sConfig.Channel = ADC_CHANNEL_3; 8000e02: f04f 0803 mov.w r8, #3 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e06: a90e add r1, sp, #56 ; 0x38 8000e08: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_3; 8000e0a: f04f 0903 mov.w r9, #3 8000e0e: e9cd 890e strd r8, r9, [sp, #56] ; 0x38 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e12: f000 fddd bl 80019d0 sConfig.Channel = ADC_CHANNEL_4; 8000e16: f04f 0804 mov.w r8, #4 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e1a: a90e add r1, sp, #56 ; 0x38 8000e1c: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_4; 8000e1e: f04f 0904 mov.w r9, #4 8000e22: e9cd 890e strd r8, r9, [sp, #56] ; 0x38 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e26: f000 fdd3 bl 80019d0 sConfig.Channel = ADC_CHANNEL_11; 8000e2a: f04f 080b mov.w r8, #11 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e2e: a90e add r1, sp, #56 ; 0x38 8000e30: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_11; 8000e32: f04f 0905 mov.w r9, #5 8000e36: e9cd 890e strd r8, r9, [sp, #56] ; 0x38 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e3a: f000 fdc9 bl 80019d0 sConfig.Channel = ADC_CHANNEL_12; 8000e3e: f04f 080c mov.w r8, #12 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e42: a90e add r1, sp, #56 ; 0x38 8000e44: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_12; 8000e46: f04f 0906 mov.w r9, #6 8000e4a: e9cd 890e strd r8, r9, [sp, #56] ; 0x38 sConfig.Channel = ADC_CHANNEL_VREFINT; 8000e4e: 2707 movs r7, #7 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e50: f000 fdbe bl 80019d0 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e54: a90e add r1, sp, #56 ; 0x38 8000e56: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_VREFINT; 8000e58: 2612 movs r6, #18 8000e5a: e9cd 670e strd r6, r7, [sp, #56] ; 0x38 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { 8000e5e: f000 fdb7 bl 80019d0 LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; 8000e62: e9cd 4412 strd r4, r4, [sp, #72] ; 0x48 LL_DAC_InitTypeDef DAC_InitStruct = { 0 }; 8000e66: e9cd 440a strd r4, r4, [sp, #40] ; 0x28 8000e6a: e9cd 440c strd r4, r4, [sp, #48] ; 0x30 LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; 8000e6e: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, Periphs); 8000e72: 69ea ldr r2, [r5, #28] 8000e74: f042 5200 orr.w r2, r2, #536870912 ; 0x20000000 8000e78: 61ea str r2, [r5, #28] /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 8000e7a: 69ea ldr r2, [r5, #28] 8000e7c: f002 5200 and.w r2, r2, #536870912 ; 0x20000000 8000e80: 9205 str r2, [sp, #20] (void)tmpreg; 8000e82: 9a05 ldr r2, [sp, #20] SET_BIT(RCC->AHBENR, Periphs); 8000e84: 696a ldr r2, [r5, #20] 8000e86: f442 3200 orr.w r2, r2, #131072 ; 0x20000 8000e8a: 616a str r2, [r5, #20] tmpreg = READ_BIT(RCC->AHBENR, Periphs); 8000e8c: 696a ldr r2, [r5, #20] GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 8000e8e: 9412 str r4, [sp, #72] ; 0x48 8000e90: f402 3200 and.w r2, r2, #131072 ; 0x20000 8000e94: 9206 str r2, [sp, #24] LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000e96: a90e add r1, sp, #56 ; 0x38 GPIO_InitStruct.Pin = LL_GPIO_PIN_4; 8000e98: 2610 movs r6, #16 8000e9a: 2703 movs r7, #3 LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000e9c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = LL_GPIO_PIN_4; 8000ea0: e9cd 670e strd r6, r7, [sp, #56] ; 0x38 (void)tmpreg; 8000ea4: 9a06 ldr r2, [sp, #24] */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000ea6: 4f5f ldr r7, [pc, #380] ; (8001024 ) LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000ea8: f001 f9e4 bl 8002274 LL_DAC_Init(DAC1, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000eac: 4b5e ldr r3, [pc, #376] ; (8001028 ) 8000eae: 495f ldr r1, [pc, #380] ; (800102c ) DAC_InitStruct.OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE; 8000eb0: 940d str r4, [sp, #52] ; 0x34 DAC_InitStruct.TriggerSource = LL_DAC_TRIG_SOFTWARE; 8000eb2: f04f 0838 mov.w r8, #56 ; 0x38 8000eb6: f04f 0900 mov.w r9, #0 LL_DAC_Init(DAC1, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000eba: aa0a add r2, sp, #40 ; 0x28 8000ebc: 4618 mov r0, r3 DAC_InitStruct.TriggerSource = LL_DAC_TRIG_SOFTWARE; 8000ebe: e9cd 890a strd r8, r9, [sp, #40] ; 0x28 LL_DAC_Init(DAC1, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000ec2: f001 f9a7 bl 8002214 MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U)); 8000ec6: 495a ldr r1, [pc, #360] ; (8001030 ) CLEAR_BIT(DACx->CR, 8000ec8: 4b57 ldr r3, [pc, #348] ; (8001028 ) 8000eca: 680a ldr r2, [r1, #0] 8000ecc: f422 3200 bic.w r2, r2, #131072 ; 0x20000 8000ed0: 600a str r2, [r1, #0] 8000ed2: 681a ldr r2, [r3, #0] 8000ed4: f022 0204 bic.w r2, r2, #4 8000ed8: 601a str r2, [r3, #0] SET_BIT(DACx->CR, 8000eda: 681a ldr r2, [r3, #0] 8000edc: f042 0201 orr.w r2, r2, #1 8000ee0: 601a str r2, [r3, #0] LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; 8000ee2: e9cd 4412 strd r4, r4, [sp, #72] ; 0x48 LL_DAC_InitTypeDef DAC_InitStruct = { 0 }; 8000ee6: e9cd 440a strd r4, r4, [sp, #40] ; 0x28 8000eea: e9cd 440c strd r4, r4, [sp, #48] ; 0x30 LL_GPIO_InitTypeDef GPIO_InitStruct = { 0 }; 8000eee: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 SET_BIT(RCC->APB1ENR, Periphs); 8000ef2: 69eb ldr r3, [r5, #28] 8000ef4: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8000ef8: 61eb str r3, [r5, #28] tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 8000efa: 69eb ldr r3, [r5, #28] 8000efc: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 8000f00: 9303 str r3, [sp, #12] (void)tmpreg; 8000f02: 9b03 ldr r3, [sp, #12] SET_BIT(RCC->AHBENR, Periphs); 8000f04: 696b ldr r3, [r5, #20] 8000f06: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000f0a: 616b str r3, [r5, #20] tmpreg = READ_BIT(RCC->AHBENR, Periphs); 8000f0c: 696b ldr r3, [r5, #20] GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; 8000f0e: 9412 str r4, [sp, #72] ; 0x48 8000f10: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000f14: 9304 str r3, [sp, #16] (void)tmpreg; 8000f16: 9804 ldr r0, [sp, #16] LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f18: a90e add r1, sp, #56 ; 0x38 GPIO_InitStruct.Pin = LL_GPIO_PIN_6; 8000f1a: 2240 movs r2, #64 ; 0x40 8000f1c: 2303 movs r3, #3 LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f1e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = LL_GPIO_PIN_6; 8000f22: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 LL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f26: f001 f9a5 bl 8002274 LL_DAC_Init(DAC2, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000f2a: aa0a add r2, sp, #40 ; 0x28 DAC_InitStruct.OutputBuffer = LL_DAC_OUTPUT_SWITCH_ENABLE; 8000f2c: 2302 movs r3, #2 LL_DAC_Init(DAC2, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000f2e: 493f ldr r1, [pc, #252] ; (800102c ) DAC_InitStruct.OutputBuffer = LL_DAC_OUTPUT_SWITCH_ENABLE; 8000f30: 930d str r3, [sp, #52] ; 0x34 LL_DAC_Init(DAC2, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000f32: 4658 mov r0, fp DAC_InitStruct.TriggerSource = LL_DAC_TRIG_SOFTWARE; 8000f34: e9cd 890a strd r8, r9, [sp, #40] ; 0x28 LL_DAC_Init(DAC2, LL_DAC_CHANNEL_1, &DAC_InitStruct); 8000f38: f001 f96c bl 8002214 CLEAR_BIT(DACx->CR, 8000f3c: f8db 3000 ldr.w r3, [fp] * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 * @retval None */ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) { MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 8000f40: f8df 80fc ldr.w r8, [pc, #252] ; 8001040 8000f44: f023 0304 bic.w r3, r3, #4 8000f48: f8cb 3000 str.w r3, [fp] SET_BIT(DACx->CR, 8000f4c: f8db 3000 ldr.w r3, [fp] 8000f50: f043 0301 orr.w r3, r3, #1 8000f54: f8cb 3000 str.w r3, [fp] LL_TIM_InitTypeDef TIM_InitStruct = { 0 }; 8000f58: e9cd 440e strd r4, r4, [sp, #56] ; 0x38 8000f5c: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 8000f60: 9412 str r4, [sp, #72] ; 0x48 SET_BIT(RCC->APB1ENR, Periphs); 8000f62: 69eb ldr r3, [r5, #28] 8000f64: f043 0301 orr.w r3, r3, #1 8000f68: 61eb str r3, [r5, #28] tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 8000f6a: 69eb ldr r3, [r5, #28] 8000f6c: f003 0301 and.w r3, r3, #1 8000f70: 930a str r3, [sp, #40] ; 0x28 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000f72: f04f 5680 mov.w r6, #268435456 ; 0x10000000 (void)tmpreg; 8000f76: 9b0a ldr r3, [sp, #40] ; 0x28 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000f78: f8da 300c ldr.w r3, [sl, #12] NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000f7c: f887 431c strb.w r4, [r7, #796] ; 0x31c TIM_InitStruct.Autoreload = 1600; 8000f80: f44f 63c8 mov.w r3, #1600 ; 0x640 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000f84: 603e str r6, [r7, #0] LL_TIM_Init(TIM2, &TIM_InitStruct); 8000f86: a90e add r1, sp, #56 ; 0x38 8000f88: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 TIM_InitStruct.Autoreload = 1600; 8000f8c: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 TIM_InitStruct.Prescaler = 0; 8000f90: f8ad 4038 strh.w r4, [sp, #56] ; 0x38 TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 8000f94: 940f str r4, [sp, #60] ; 0x3c LL_TIM_Init(TIM2, &TIM_InitStruct); 8000f96: f001 fa1d bl 80023d4 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 8000f9a: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 8000f9e: 681a ldr r2, [r3, #0] 8000fa0: f042 0280 orr.w r2, r2, #128 ; 0x80 8000fa4: 601a str r2, [r3, #0] MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 8000fa6: 689a ldr r2, [r3, #8] 8000fa8: ea02 0208 and.w r2, r2, r8 8000fac: 609a str r2, [r3, #8] * @arg @ref LL_TIM_TRGO_OC4REF * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) { MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 8000fae: 685a ldr r2, [r3, #4] 8000fb0: f022 0270 bic.w r2, r2, #112 ; 0x70 8000fb4: f042 0220 orr.w r2, r2, #32 8000fb8: 605a str r2, [r3, #4] * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 8000fba: 689a ldr r2, [r3, #8] 8000fbc: f022 0280 bic.w r2, r2, #128 ; 0x80 8000fc0: 609a str r2, [r3, #8] * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_UIE); 8000fc2: 68da ldr r2, [r3, #12] 8000fc4: f042 0201 orr.w r2, r2, #1 8000fc8: 60da str r2, [r3, #12] SET_BIT(TIMx->CR1, TIM_CR1_CEN); 8000fca: 681a ldr r2, [r3, #0] 8000fcc: f042 0201 orr.w r2, r2, #1 8000fd0: 601a str r2, [r3, #0] NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000fd2: f8c7 6080 str.w r6, [r7, #128] ; 0x80 __ASM volatile ("dsb 0xF":::"memory"); 8000fd6: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8000fda: f3bf 8f6f isb sy return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000fde: f8da 300c ldr.w r3, [sl, #12] NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000fe2: f887 431c strb.w r4, [r7, #796] ; 0x31c NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000fe6: 603e str r6, [r7, #0] LL_TIM_InitTypeDef TIM_InitStruct = { 0 }; 8000fe8: e9cd 440e strd r4, r4, [sp, #56] ; 0x38 8000fec: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 8000ff0: 9412 str r4, [sp, #72] ; 0x48 SET_BIT(RCC->APB1ENR, Periphs); 8000ff2: 69eb ldr r3, [r5, #28] LL_TIM_Init(TIM3, &TIM_InitStruct); 8000ff4: 4e0f ldr r6, [pc, #60] ; (8001034 ) 8000ff6: f043 0302 orr.w r3, r3, #2 8000ffa: 61eb str r3, [r5, #28] tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 8000ffc: 69eb ldr r3, [r5, #28] 8000ffe: f003 0302 and.w r3, r3, #2 8001002: 9302 str r3, [sp, #8] 8001004: f04f 5500 mov.w r5, #536870912 ; 0x20000000 (void)tmpreg; 8001008: 9b02 ldr r3, [sp, #8] return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800100a: f8da 300c ldr.w r3, [sl, #12] NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800100e: f887 431d strb.w r4, [r7, #797] ; 0x31d TIM_InitStruct.Autoreload = 12800; 8001012: f44f 5348 mov.w r3, #12800 ; 0x3200 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001016: 603d str r5, [r7, #0] LL_TIM_Init(TIM3, &TIM_InitStruct); 8001018: a90e add r1, sp, #56 ; 0x38 800101a: e013 b.n 8001044 800101c: 40021000 .word 0x40021000 8001020: 20000bb0 .word 0x20000bb0 8001024: e000e100 .word 0xe000e100 8001028: 40007400 .word 0x40007400 800102c: 02100001 .word 0x02100001 8001030: 40010050 .word 0x40010050 8001034: 40000400 .word 0x40000400 8001038: 40009800 .word 0x40009800 800103c: e000ed00 .word 0xe000ed00 8001040: fffebff8 .word 0xfffebff8 8001044: 4630 mov r0, r6 TIM_InitStruct.Autoreload = 12800; 8001046: e9cd 3410 strd r3, r4, [sp, #64] ; 0x40 TIM_InitStruct.Prescaler = 0; 800104a: f8ad 4038 strh.w r4, [sp, #56] ; 0x38 TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 800104e: 940f str r4, [sp, #60] ; 0x3c LL_TIM_Init(TIM3, &TIM_InitStruct); 8001050: f001 f9c0 bl 80023d4 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 8001054: 6833 ldr r3, [r6, #0] 8001056: f043 0380 orr.w r3, r3, #128 ; 0x80 800105a: 6033 str r3, [r6, #0] MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 800105c: 68b3 ldr r3, [r6, #8] 800105e: ea03 0308 and.w r3, r3, r8 8001062: 60b3 str r3, [r6, #8] MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 8001064: 6873 ldr r3, [r6, #4] 8001066: f023 0370 bic.w r3, r3, #112 ; 0x70 800106a: f043 0320 orr.w r3, r3, #32 800106e: 6073 str r3, [r6, #4] CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 8001070: 68b3 ldr r3, [r6, #8] 8001072: f023 0380 bic.w r3, r3, #128 ; 0x80 8001076: 60b3 str r3, [r6, #8] NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001078: f8c7 5080 str.w r5, [r7, #128] ; 0x80 __ASM volatile ("dsb 0xF":::"memory"); 800107c: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8001080: f3bf 8f6f isb sy return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001084: f8da 200c ldr.w r2, [sl, #12] NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001088: f8df 91b0 ldr.w r9, [pc, #432] ; 800123c SET_BIT(TIMx->DIER, TIM_DIER_UIE); 800108c: 4f5f ldr r7, [pc, #380] ; (800120c ) hadc2.Init.DiscontinuousConvMode = DISABLE; 800108e: 4e60 ldr r6, [pc, #384] ; (8001210 ) LL_TIM_Init(TIM1, &TIM_InitStruct); 8001090: 4d60 ldr r5, [pc, #384] ; (8001214 ) return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001092: f3c2 2202 ubfx r2, r2, #8, #3 { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001096: f1c2 0307 rsb r3, r2, #7 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800109a: 1d11 adds r1, r2, #4 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800109c: 2b04 cmp r3, #4 800109e: bf28 it cs 80010a0: 2304 movcs r3, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80010a2: 2906 cmp r1, #6 80010a4: bf88 it hi 80010a6: 1ed4 subhi r4, r2, #3 return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80010a8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80010ac: fa02 f303 lsl.w r3, r2, r3 80010b0: 43db mvns r3, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80010b2: 40a2 lsls r2, r4 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80010b4: f003 0302 and.w r3, r3, #2 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80010b8: 43d2 mvns r2, r2 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80010ba: 40a3 lsls r3, r4 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80010bc: f002 0202 and.w r2, r2, #2 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80010c0: 4313 orrs r3, r2 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80010c2: 011b lsls r3, r3, #4 80010c4: b2db uxtb r3, r3 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80010c6: f04f 5100 mov.w r1, #536870912 ; 0x20000000 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80010ca: f889 331d strb.w r3, [r9, #797] ; 0x31d NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80010ce: f8c9 1000 str.w r1, [r9] 80010d2: 68fb ldr r3, [r7, #12] hadc2.Instance = ADC2; 80010d4: 4a50 ldr r2, [pc, #320] ; (8001218 ) 80010d6: f043 0301 orr.w r3, r3, #1 80010da: 60fb str r3, [r7, #12] SET_BIT(TIMx->CR1, TIM_CR1_CEN); 80010dc: 683b ldr r3, [r7, #0] hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 80010de: f44f 6480 mov.w r4, #1024 ; 0x400 80010e2: f043 0301 orr.w r3, r3, #1 80010e6: 603b str r3, [r7, #0] 80010e8: 62f4 str r4, [r6, #44] ; 0x2c ADC_ChannelConfTypeDef sConfig = { 0 }; 80010ea: 2400 movs r4, #0 hadc2.Init.NbrOfConversion = 1; 80010ec: f04f 0801 mov.w r8, #1 hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_TRGO; 80010f0: f44f 7110 mov.w r1, #576 ; 0x240 hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80010f4: 2304 movs r3, #4 if (HAL_ADC_Init(&hadc2) != HAL_OK) { 80010f6: 4630 mov r0, r6 hadc2.Init.LowPowerAutoWait = DISABLE; 80010f8: 8334 strh r4, [r6, #24] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_TRGO; 80010fa: 62b1 str r1, [r6, #40] ; 0x28 hadc2.Instance = ADC2; 80010fc: 6032 str r2, [r6, #0] hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 80010fe: 6173 str r3, [r6, #20] ADC_ChannelConfTypeDef sConfig = { 0 }; 8001100: e9cd 440e strd r4, r4, [sp, #56] ; 0x38 8001104: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 8001108: e9cd 4412 strd r4, r4, [sp, #72] ; 0x48 hadc2.Init.Resolution = ADC_RESOLUTION_12B; 800110c: e9c6 4401 strd r4, r4, [r6, #4] hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; 8001110: e9c6 4403 strd r4, r4, [r6, #12] hadc2.Init.DiscontinuousConvMode = DISABLE; 8001114: f886 4020 strb.w r4, [r6, #32] hadc2.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; 8001118: 6374 str r4, [r6, #52] ; 0x34 hadc2.Init.NbrOfConversion = 1; 800111a: f8c6 801c str.w r8, [r6, #28] hadc2.Init.DMAContinuousRequests = ENABLE; 800111e: f886 8030 strb.w r8, [r6, #48] ; 0x30 if (HAL_ADC_Init(&hadc2) != HAL_OK) { 8001122: f000 facb bl 80016bc sConfig.Channel = ADC_CHANNEL_2; 8001126: 2202 movs r2, #2 8001128: 2301 movs r3, #1 800112a: e9cd 230e strd r2, r3, [sp, #56] ; 0x38 800112e: 2207 movs r2, #7 8001130: 2300 movs r3, #0 8001132: e9cd 2310 strd r2, r3, [sp, #64] ; 0x40 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { 8001136: a90e add r1, sp, #56 ; 0x38 sConfig.Channel = ADC_CHANNEL_2; 8001138: 2200 movs r2, #0 800113a: 2300 movs r3, #0 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { 800113c: 4630 mov r0, r6 sConfig.Channel = ADC_CHANNEL_2; 800113e: e9cd 2312 strd r2, r3, [sp, #72] ; 0x48 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { 8001142: f000 fc45 bl 80019d0 LL_TIM_InitTypeDef TIM_InitStruct = { 0 }; 8001146: e9cd 440e strd r4, r4, [sp, #56] ; 0x38 800114a: e9cd 4410 strd r4, r4, [sp, #64] ; 0x40 * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, Periphs); 800114e: 4b33 ldr r3, [pc, #204] ; (800121c ) 8001150: 9412 str r4, [sp, #72] ; 0x48 8001152: 699a ldr r2, [r3, #24] return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001154: 4832 ldr r0, [pc, #200] ; (8001220 ) 8001156: f442 6200 orr.w r2, r2, #2048 ; 0x800 800115a: 619a str r2, [r3, #24] /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 800115c: 699b ldr r3, [r3, #24] 800115e: f403 6300 and.w r3, r3, #2048 ; 0x800 8001162: 9301 str r3, [sp, #4] NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001164: f04f 7300 mov.w r3, #33554432 ; 0x2000000 (void)tmpreg; 8001168: 9a01 ldr r2, [sp, #4] return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800116a: 68c2 ldr r2, [r0, #12] NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800116c: f889 4319 strb.w r4, [r9, #793] ; 0x319 LL_TIM_Init(TIM1, &TIM_InitStruct); 8001170: a90e add r1, sp, #56 ; 0x38 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001172: f8c9 3000 str.w r3, [r9] 8001176: 4628 mov r0, r5 TIM_InitStruct.Autoreload = 4800; 8001178: f44f 5396 mov.w r3, #4800 ; 0x12c0 800117c: 9310 str r3, [sp, #64] ; 0x40 TIM_InitStruct.Prescaler = 0; 800117e: f8ad 4038 strh.w r4, [sp, #56] ; 0x38 TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; 8001182: 940f str r4, [sp, #60] ; 0x3c TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 8001184: 9411 str r4, [sp, #68] ; 0x44 TIM_InitStruct.RepetitionCounter = 0; 8001186: f88d 4048 strb.w r4, [sp, #72] ; 0x48 LL_TIM_Init(TIM1, &TIM_InitStruct); 800118a: f001 f923 bl 80023d4 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 800118e: 682b ldr r3, [r5, #0] } /* USER CODE BEGIN 4 */ void start_adc() { HAL_ADC_Start_DMA(&hadc1, (uint32_t*) adc_data, NUM_ADC_CHANNELS); 8001190: 4924 ldr r1, [pc, #144] ; (8001224 ) 8001192: 4825 ldr r0, [pc, #148] ; (8001228 ) 8001194: f023 0380 bic.w r3, r3, #128 ; 0x80 8001198: 602b str r3, [r5, #0] MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 800119a: 68ab ldr r3, [r5, #8] 800119c: f423 33a0 bic.w r3, r3, #81920 ; 0x14000 80011a0: f023 0307 bic.w r3, r3, #7 80011a4: 60ab str r3, [r5, #8] MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 80011a6: 686b ldr r3, [r5, #4] 80011a8: f023 0370 bic.w r3, r3, #112 ; 0x70 80011ac: f043 0320 orr.w r3, r3, #32 80011b0: 606b str r3, [r5, #4] MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 80011b2: 686b ldr r3, [r5, #4] 80011b4: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 80011b8: 606b str r3, [r5, #4] CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 80011ba: 68ab ldr r3, [r5, #8] 80011bc: f023 0380 bic.w r3, r3, #128 ; 0x80 80011c0: 60ab str r3, [r5, #8] SET_BIT(TIMx->DIER, TIM_DIER_UIE); 80011c2: 68eb ldr r3, [r5, #12] 80011c4: ea43 0308 orr.w r3, r3, r8 80011c8: 60eb str r3, [r5, #12] SET_BIT(TIMx->CR1, TIM_CR1_CEN); 80011ca: 682b ldr r3, [r5, #0] 80011cc: ea43 0308 orr.w r3, r3, r8 80011d0: 602b str r3, [r5, #0] 80011d2: 2207 movs r2, #7 80011d4: f000 fb78 bl 80018c8 HAL_ADC_Start_DMA(&hadc2, (uint32_t*) voct_data, 1); 80011d8: 4914 ldr r1, [pc, #80] ; (800122c ) 80011da: 4642 mov r2, r8 80011dc: 4630 mov r0, r6 80011de: f000 fb73 bl 80018c8 80011e2: 683b ldr r3, [r7, #0] dynamic_smooth_init(&dynamic_smooth_a, 0.05f, 0.5f); 80011e4: 4812 ldr r0, [pc, #72] ; (8001230 ) 80011e6: ed9f 0a13 vldr s0, [pc, #76] ; 8001234 80011ea: ea43 0308 orr.w r3, r3, r8 80011ee: 603b str r3, [r7, #0] 80011f0: 682b ldr r3, [r5, #0] 80011f2: ea43 0308 orr.w r3, r3, r8 80011f6: 602b str r3, [r5, #0] 80011f8: eef6 0a00 vmov.f32 s1, #96 ; 0x3f000000 0.5 80011fc: f7ff fc9e bl 8000b3c adsr_structinit(&OP1.ADSR); 8001200: 480d ldr r0, [pc, #52] ; (8001238 ) 8001202: f7ff fa25 bl 8000650 loop(); 8001206: f7ff fcd7 bl 8000bb8 while (1) { 800120a: e7fc b.n 8001206 800120c: 40000400 .word 0x40000400 8001210: 20000b60 .word 0x20000b60 8001214: 40012c00 .word 0x40012c00 8001218: 50000100 .word 0x50000100 800121c: 40021000 .word 0x40021000 8001220: e000ed00 .word 0xe000ed00 8001224: 200008c4 .word 0x200008c4 8001228: 20000bb0 .word 0x20000bb0 800122c: 20000b5c .word 0x20000b5c 8001230: 20000adc .word 0x20000adc 8001234: 3d4ccccd .word 0x3d4ccccd 8001238: 20000854 .word 0x20000854 800123c: e000e100 .word 0xe000e100 08001240 : void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ /* USER CODE END Error_Handler_Debug */ } 8001240: 4770 bx lr 8001242: bf00 nop 08001244 : { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001244: 4b0a ldr r3, [pc, #40] ; (8001270 ) 8001246: 699a ldr r2, [r3, #24] 8001248: f042 0201 orr.w r2, r2, #1 800124c: 619a str r2, [r3, #24] 800124e: 699a ldr r2, [r3, #24] { 8001250: b082 sub sp, #8 __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001252: f002 0201 and.w r2, r2, #1 8001256: 9200 str r2, [sp, #0] 8001258: 9a00 ldr r2, [sp, #0] __HAL_RCC_PWR_CLK_ENABLE(); 800125a: 69da ldr r2, [r3, #28] 800125c: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 8001260: 61da str r2, [r3, #28] 8001262: 69db ldr r3, [r3, #28] 8001264: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001268: 9301 str r3, [sp, #4] 800126a: 9b01 ldr r3, [sp, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 800126c: b002 add sp, #8 800126e: 4770 bx lr 8001270: 40021000 .word 0x40021000 08001274 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8001274: b570 push {r4, r5, r6, lr} GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hadc->Instance==ADC1) 8001276: 6802 ldr r2, [r0, #0] { 8001278: b08c sub sp, #48 ; 0x30 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800127a: 2300 movs r3, #0 if(hadc->Instance==ADC1) 800127c: f1b2 4fa0 cmp.w r2, #1342177280 ; 0x50000000 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001280: e9cd 3306 strd r3, r3, [sp, #24] 8001284: e9cd 3308 strd r3, r3, [sp, #32] { 8001288: 4604 mov r4, r0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800128a: 930a str r3, [sp, #40] ; 0x28 if(hadc->Instance==ADC1) 800128c: d038 beq.n 8001300 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } else if(hadc->Instance==ADC2) 800128e: 4b41 ldr r3, [pc, #260] ; (8001394 ) 8001290: 429a cmp r2, r3 8001292: d001 beq.n 8001298 /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8001294: b00c add sp, #48 ; 0x30 8001296: bd70 pop {r4, r5, r6, pc} HAL_RCC_ADC12_CLK_ENABLED++; 8001298: 4a3f ldr r2, [pc, #252] ; (8001398 ) 800129a: 6813 ldr r3, [r2, #0] 800129c: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 800129e: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 80012a0: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 80012a2: d068 beq.n 8001376 __HAL_RCC_GPIOA_CLK_ENABLE(); 80012a4: 4b3d ldr r3, [pc, #244] ; (800139c ) hdma_adc2.Instance = DMA1_Channel2; 80012a6: 4d3e ldr r5, [pc, #248] ; (80013a0 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 80012a8: 695a ldr r2, [r3, #20] 80012aa: f442 3200 orr.w r2, r2, #131072 ; 0x20000 80012ae: 615a str r2, [r3, #20] 80012b0: 695b ldr r3, [r3, #20] 80012b2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80012b6: 9305 str r3, [sp, #20] 80012b8: 9805 ldr r0, [sp, #20] GPIO_InitStruct.Pin = GPIO_PIN_5; 80012ba: 2303 movs r3, #3 80012bc: 2220 movs r2, #32 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80012be: a906 add r1, sp, #24 GPIO_InitStruct.Pull = GPIO_NOPULL; 80012c0: 2600 movs r6, #0 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80012c2: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_5; 80012c6: e9cd 2306 strd r2, r3, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012ca: 9608 str r6, [sp, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80012cc: f000 febc bl 8002048 hdma_adc2.Instance = DMA1_Channel2; 80012d0: 4b34 ldr r3, [pc, #208] ; (80013a4 ) 80012d2: 602b str r3, [r5, #0] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 80012d4: 2080 movs r0, #128 ; 0x80 hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 80012d6: f44f 7180 mov.w r1, #256 ; 0x100 hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 80012da: f44f 6280 mov.w r2, #1024 ; 0x400 hdma_adc2.Init.Mode = DMA_CIRCULAR; 80012de: 2320 movs r3, #32 hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 80012e0: 60e8 str r0, [r5, #12] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 80012e2: e9c5 1204 strd r1, r2, [r5, #16] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 80012e6: 606e str r6, [r5, #4] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 80012e8: 60ae str r6, [r5, #8] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 80012ea: 61ee str r6, [r5, #28] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 80012ec: 4628 mov r0, r5 hdma_adc2.Init.Mode = DMA_CIRCULAR; 80012ee: 61ab str r3, [r5, #24] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 80012f0: f000 fdec bl 8001ecc 80012f4: 2800 cmp r0, #0 80012f6: d149 bne.n 800138c __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 80012f8: 63a5 str r5, [r4, #56] ; 0x38 80012fa: 626c str r4, [r5, #36] ; 0x24 } 80012fc: b00c add sp, #48 ; 0x30 80012fe: bd70 pop {r4, r5, r6, pc} HAL_RCC_ADC12_CLK_ENABLED++; 8001300: 4a25 ldr r2, [pc, #148] ; (8001398 ) 8001302: 6813 ldr r3, [r2, #0] 8001304: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8001306: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 8001308: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 800130a: d029 beq.n 8001360 __HAL_RCC_GPIOA_CLK_ENABLE(); 800130c: 4b23 ldr r3, [pc, #140] ; (800139c ) hdma_adc1.Instance = DMA1_Channel1; 800130e: 4d26 ldr r5, [pc, #152] ; (80013a8 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8001310: 695a ldr r2, [r3, #20] 8001312: f442 3200 orr.w r2, r2, #131072 ; 0x20000 8001316: 615a str r2, [r3, #20] 8001318: 695a ldr r2, [r3, #20] 800131a: f402 3200 and.w r2, r2, #131072 ; 0x20000 800131e: 9202 str r2, [sp, #8] 8001320: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001322: 695a ldr r2, [r3, #20] 8001324: f442 2280 orr.w r2, r2, #262144 ; 0x40000 8001328: 615a str r2, [r3, #20] 800132a: 695b ldr r3, [r3, #20] 800132c: f403 2380 and.w r3, r3, #262144 ; 0x40000 8001330: 9303 str r3, [sp, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 8001332: 220f movs r2, #15 8001334: 2303 movs r3, #3 __HAL_RCC_GPIOB_CLK_ENABLE(); 8001336: 9903 ldr r1, [sp, #12] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001338: 2600 movs r6, #0 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800133a: a906 add r1, sp, #24 800133c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; 8001340: e9cd 2306 strd r2, r3, [sp, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001344: 9608 str r6, [sp, #32] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001346: f000 fe7f bl 8002048 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 800134a: 2303 movs r3, #3 800134c: 2203 movs r2, #3 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800134e: 4817 ldr r0, [pc, #92] ; (80013ac ) GPIO_InitStruct.Pull = GPIO_NOPULL; 8001350: 9608 str r6, [sp, #32] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001352: a906 add r1, sp, #24 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8001354: e9cd 2306 strd r2, r3, [sp, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001358: f000 fe76 bl 8002048 hdma_adc1.Instance = DMA1_Channel1; 800135c: 4b14 ldr r3, [pc, #80] ; (80013b0 ) 800135e: e7b8 b.n 80012d2 __HAL_RCC_ADC12_CLK_ENABLE(); 8001360: 4b0e ldr r3, [pc, #56] ; (800139c ) 8001362: 695a ldr r2, [r3, #20] 8001364: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 8001368: 615a str r2, [r3, #20] 800136a: 695b ldr r3, [r3, #20] 800136c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001370: 9301 str r3, [sp, #4] 8001372: 9b01 ldr r3, [sp, #4] 8001374: e7ca b.n 800130c __HAL_RCC_ADC12_CLK_ENABLE(); 8001376: 4b09 ldr r3, [pc, #36] ; (800139c ) 8001378: 695a ldr r2, [r3, #20] 800137a: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 800137e: 615a str r2, [r3, #20] 8001380: 695b ldr r3, [r3, #20] 8001382: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001386: 9304 str r3, [sp, #16] 8001388: 9b04 ldr r3, [sp, #16] 800138a: e78b b.n 80012a4 Error_Handler(); 800138c: f7ff ff58 bl 8001240 8001390: e7b2 b.n 80012f8 8001392: bf00 nop 8001394: 50000100 .word 0x50000100 8001398: 20000828 .word 0x20000828 800139c: 40021000 .word 0x40021000 80013a0: 20000c44 .word 0x20000c44 80013a4: 4002001c .word 0x4002001c 80013a8: 20000c00 .word 0x20000c00 80013ac: 48000400 .word 0x48000400 80013b0: 40020008 .word 0x40020008 080013b4 : /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 80013b4: 4770 bx lr 80013b6: bf00 nop 080013b8 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80013b8: e7fe b.n 80013b8 80013ba: bf00 nop 080013bc : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80013bc: e7fe b.n 80013bc 80013be: bf00 nop 080013c0 : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 80013c0: e7fe b.n 80013c0 80013c2: bf00 nop 080013c4 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 80013c4: e7fe b.n 80013c4 80013c6: bf00 nop 080013c8 : 80013c8: 4770 bx lr 80013ca: bf00 nop 080013cc : 80013cc: 4770 bx lr 80013ce: bf00 nop 080013d0 : 80013d0: 4770 bx lr 80013d2: bf00 nop 080013d4 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80013d4: f000 b8c0 b.w 8001558 080013d8 : void DMA1_Channel1_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 80013d8: 4801 ldr r0, [pc, #4] ; (80013e0 ) 80013da: f000 bdeb b.w 8001fb4 80013de: bf00 nop 80013e0: 20000c00 .word 0x20000c00 080013e4 : void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 80013e4: 4801 ldr r0, [pc, #4] ; (80013ec ) 80013e6: f000 bde5 b.w 8001fb4 80013ea: bf00 nop 80013ec: 20000c44 .word 0x20000c44 080013f0 : return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 80013f0: 4b03 ldr r3, [pc, #12] ; (8001400 ) 80013f2: 691a ldr r2, [r3, #16] * @brief This function handles TIM1 update and TIM16 interrupts. */ void TIM1_UP_TIM16_IRQHandler(void) { /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */ if (LL_TIM_IsActiveFlag_UPDATE(TIM1)) { 80013f4: 07d2 lsls r2, r2, #31 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 80013f6: bf44 itt mi 80013f8: f06f 0201 mvnmi.w r2, #1 80013fc: 611a strmi r2, [r3, #16] /* USER CODE END TIM1_UP_TIM16_IRQn 0 */ /* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */ /* USER CODE END TIM1_UP_TIM16_IRQn 1 */ } 80013fe: 4770 bx lr 8001400: 40012c00 .word 0x40012c00 08001404 : return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 8001404: f04f 4380 mov.w r3, #1073741824 ; 0x40000000 8001408: 691a ldr r2, [r3, #16] { /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ /* USER CODE BEGIN TIM2_IRQn 1 */ if (LL_TIM_IsActiveFlag_UPDATE(TIM2)) { 800140a: 07d2 lsls r2, r2, #31 800140c: d400 bmi.n 8001410 main_2OP_loop(); //handle_out_buffer(); } /* USER CODE END TIM2_IRQn 1 */ } 800140e: 4770 bx lr WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 8001410: f06f 0201 mvn.w r2, #1 8001414: 611a str r2, [r3, #16] main_2OP_loop(); 8001416: f7ff ba11 b.w 800083c 800141a: bf00 nop 0800141c : return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 800141c: 4b13 ldr r3, [pc, #76] ; (800146c ) 800141e: 691a ldr r2, [r3, #16] { /* USER CODE BEGIN TIM3_IRQn 0 */ /* USER CODE END TIM3_IRQn 0 */ /* USER CODE BEGIN TIM3_IRQn 1 */ if (LL_TIM_IsActiveFlag_UPDATE(TIM3)) { 8001420: 07d2 lsls r2, r2, #31 8001422: d521 bpl.n 8001468 LL_TIM_ClearFlag_UPDATE(TIM3); for (uint8_t i = 0; i < (NUM_ADC_CHANNELS - 1); i++) { adc_data_10b[i] = adc_data[i] >> 2; 8001424: 4a12 ldr r2, [pc, #72] ; (8001470 ) { 8001426: b570 push {r4, r5, r6, lr} adc_data_10b[i] = adc_data[i] >> 2; 8001428: 8850 ldrh r0, [r2, #2] 800142a: 8816 ldrh r6, [r2, #0] 800142c: 8895 ldrh r5, [r2, #4] 800142e: 88d4 ldrh r4, [r2, #6] WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 8001430: f06f 0101 mvn.w r1, #1 8001434: 6119 str r1, [r3, #16] 8001436: 4b0f ldr r3, [pc, #60] ; (8001474 ) 8001438: 8911 ldrh r1, [r2, #8] 800143a: 8952 ldrh r2, [r2, #10] 800143c: 0880 lsrs r0, r0, #2 800143e: 0889 lsrs r1, r1, #2 8001440: 0892 lsrs r2, r2, #2 8001442: 8058 strh r0, [r3, #2] 8001444: 08b6 lsrs r6, r6, #2 8001446: 08ad lsrs r5, r5, #2 8001448: 08a4 lsrs r4, r4, #2 } #ifdef SMOOTH_ATTACK run_linear_a_expo_r(&OP1.ADSR); 800144a: 480b ldr r0, [pc, #44] ; (8001478 ) adc_data_10b[i] = adc_data[i] >> 2; 800144c: 801e strh r6, [r3, #0] 800144e: 809d strh r5, [r3, #4] 8001450: 80dc strh r4, [r3, #6] 8001452: 8119 strh r1, [r3, #8] 8001454: 815a strh r2, [r3, #10] run_linear_a_expo_r(&OP1.ADSR); 8001456: f7ff f913 bl 8000680 #else run_ar(&OP1.ADSR); #endif check_gate(); 800145a: f7ff f989 bl 8000770 //check_trig(); set_adsr_parameters(&OP1.ADSR); } /* USER CODE END TIM3_IRQn 1 */ } 800145e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} set_adsr_parameters(&OP1.ADSR); 8001462: 4805 ldr r0, [pc, #20] ; (8001478 ) 8001464: f7ff b9a2 b.w 80007ac 8001468: 4770 bx lr 800146a: bf00 nop 800146c: 40000400 .word 0x40000400 8001470: 200008c4 .word 0x200008c4 8001474: 200008b4 .word 0x200008b4 8001478: 20000854 .word 0x20000854 0800147c : */ void SystemInit(void) { /* FPU settings --------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 800147c: 4b05 ldr r3, [pc, #20] ; (8001494 ) 800147e: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 #endif #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 8001482: f04f 6100 mov.w r1, #134217728 ; 0x8000000 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001486: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 800148a: f8c3 2088 str.w r2, [r3, #136] ; 0x88 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 800148e: 6099 str r1, [r3, #8] #endif } 8001490: 4770 bx lr 8001492: bf00 nop 8001494: e000ed00 .word 0xe000ed00 08001498 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ 8001498: f8df d034 ldr.w sp, [pc, #52] ; 80014d0 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 800149c: 2100 movs r1, #0 b LoopCopyDataInit 800149e: e003 b.n 80014a8 080014a0 : CopyDataInit: ldr r3, =_sidata 80014a0: 4b0c ldr r3, [pc, #48] ; (80014d4 ) ldr r3, [r3, r1] 80014a2: 585b ldr r3, [r3, r1] str r3, [r0, r1] 80014a4: 5043 str r3, [r0, r1] adds r1, r1, #4 80014a6: 3104 adds r1, #4 080014a8 : LoopCopyDataInit: ldr r0, =_sdata 80014a8: 480b ldr r0, [pc, #44] ; (80014d8 ) ldr r3, =_edata 80014aa: 4b0c ldr r3, [pc, #48] ; (80014dc ) adds r2, r0, r1 80014ac: 1842 adds r2, r0, r1 cmp r2, r3 80014ae: 429a cmp r2, r3 bcc CopyDataInit 80014b0: d3f6 bcc.n 80014a0 ldr r2, =_sbss 80014b2: 4a0b ldr r2, [pc, #44] ; (80014e0 ) b LoopFillZerobss 80014b4: e002 b.n 80014bc 080014b6 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 80014b6: 2300 movs r3, #0 str r3, [r2], #4 80014b8: f842 3b04 str.w r3, [r2], #4 080014bc : LoopFillZerobss: ldr r3, = _ebss 80014bc: 4b09 ldr r3, [pc, #36] ; (80014e4 ) cmp r2, r3 80014be: 429a cmp r2, r3 bcc FillZerobss 80014c0: d3f9 bcc.n 80014b6 /* Call the clock system intitialization function.*/ bl SystemInit 80014c2: f7ff ffdb bl 800147c /* Call static constructors */ bl __libc_init_array 80014c6: f000 ffd3 bl 8002470 <__libc_init_array> /* Call the application's entry point.*/ bl main 80014ca: f7ff fc07 bl 8000cdc
080014ce : LoopForever: b LoopForever 80014ce: e7fe b.n 80014ce ldr sp, =_estack /* Atollic update: set stack pointer */ 80014d0: 20003000 .word 0x20003000 ldr r3, =_sidata 80014d4: 08002cd8 .word 0x08002cd8 ldr r0, =_sdata 80014d8: 20000000 .word 0x20000000 ldr r3, =_edata 80014dc: 2000080c .word 0x2000080c ldr r2, =_sbss 80014e0: 2000080c .word 0x2000080c ldr r3, = _ebss 80014e4: 20000c8c .word 0x20000c8c 080014e8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80014e8: e7fe b.n 80014e8 ... 080014ec : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80014ec: b538 push {r3, r4, r5, lr} /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80014ee: 4a0e ldr r2, [pc, #56] ; (8001528 ) 80014f0: 4b0e ldr r3, [pc, #56] ; (800152c ) 80014f2: 7812 ldrb r2, [r2, #0] 80014f4: 681b ldr r3, [r3, #0] { 80014f6: 4605 mov r5, r0 if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) 80014f8: f44f 707a mov.w r0, #1000 ; 0x3e8 80014fc: fbb0 f0f2 udiv r0, r0, r2 8001500: fbb3 f0f0 udiv r0, r3, r0 8001504: f000 fcc8 bl 8001e98 8001508: b908 cbnz r0, 800150e { return HAL_ERROR; } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800150a: 2d0f cmp r5, #15 800150c: d901 bls.n 8001512 return HAL_ERROR; 800150e: 2001 movs r0, #1 { return HAL_ERROR; } /* Return function status */ return HAL_OK; } 8001510: bd38 pop {r3, r4, r5, pc} 8001512: 4604 mov r4, r0 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001514: 4602 mov r2, r0 8001516: 4629 mov r1, r5 8001518: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800151c: f000 fc76 bl 8001e0c uwTickPrio = TickPriority; 8001520: 4b03 ldr r3, [pc, #12] ; (8001530 ) 8001522: 4620 mov r0, r4 8001524: 601d str r5, [r3, #0] } 8001526: bd38 pop {r3, r4, r5, pc} 8001528: 20000804 .word 0x20000804 800152c: 20000800 .word 0x20000800 8001530: 20000808 .word 0x20000808 08001534 : __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001534: 4a07 ldr r2, [pc, #28] ; (8001554 ) { 8001536: b508 push {r3, lr} __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001538: 6813 ldr r3, [r2, #0] 800153a: f043 0310 orr.w r3, r3, #16 800153e: 6013 str r3, [r2, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001540: 2003 movs r0, #3 8001542: f000 fc4f bl 8001de4 HAL_InitTick(TICK_INT_PRIORITY); 8001546: 2000 movs r0, #0 8001548: f7ff ffd0 bl 80014ec HAL_MspInit(); 800154c: f7ff fe7a bl 8001244 } 8001550: 2000 movs r0, #0 8001552: bd08 pop {r3, pc} 8001554: 40022000 .word 0x40022000 08001558 : * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; 8001558: 4a03 ldr r2, [pc, #12] ; (8001568 ) 800155a: 4b04 ldr r3, [pc, #16] ; (800156c ) 800155c: 6811 ldr r1, [r2, #0] 800155e: 781b ldrb r3, [r3, #0] 8001560: 440b add r3, r1 8001562: 6013 str r3, [r2, #0] } 8001564: 4770 bx lr 8001566: bf00 nop 8001568: 20000c88 .word 0x20000c88 800156c: 20000804 .word 0x20000804 08001570 : * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; 8001570: 4b01 ldr r3, [pc, #4] ; (8001578 ) 8001572: 6818 ldr r0, [r3, #0] } 8001574: 4770 bx lr 8001576: bf00 nop 8001578: 20000c88 .word 0x20000c88 0800157c : 800157c: 4770 bx lr 800157e: bf00 nop 08001580 : 8001580: 4770 bx lr 8001582: bf00 nop 08001584 : 8001584: 4770 bx lr 8001586: bf00 nop 08001588 : * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 8001588: 6a40 ldr r0, [r0, #36] ; 0x24 /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800158a: 6c03 ldr r3, [r0, #64] ; 0x40 800158c: f043 0340 orr.w r3, r3, #64 ; 0x40 8001590: 6403 str r3, [r0, #64] ; 0x40 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8001592: 6c43 ldr r3, [r0, #68] ; 0x44 8001594: f043 0304 orr.w r3, r3, #4 8001598: 6443 str r3, [r0, #68] ; 0x44 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800159a: f7ff bff3 b.w 8001584 800159e: bf00 nop 080015a0 : HAL_ADC_ConvHalfCpltCallback(hadc); 80015a0: 6a40 ldr r0, [r0, #36] ; 0x24 80015a2: f7ff bfed b.w 8001580 80015a6: bf00 nop 080015a8 : ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 80015a8: 6a43 ldr r3, [r0, #36] ; 0x24 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 80015aa: 6c1a ldr r2, [r3, #64] ; 0x40 80015ac: f012 0f50 tst.w r2, #80 ; 0x50 80015b0: d118 bne.n 80015e4 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80015b2: 6c1a ldr r2, [r3, #64] ; 0x40 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80015b4: 6819 ldr r1, [r3, #0] SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 80015b6: f442 7200 orr.w r2, r2, #512 ; 0x200 80015ba: 641a str r2, [r3, #64] ; 0x40 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 80015bc: 68ca ldr r2, [r1, #12] 80015be: f412 6f40 tst.w r2, #3072 ; 0xc00 80015c2: d10c bne.n 80015de 80015c4: 7e5a ldrb r2, [r3, #25] 80015c6: b952 cbnz r2, 80015de CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80015c8: 6c1a ldr r2, [r3, #64] ; 0x40 80015ca: f422 7280 bic.w r2, r2, #256 ; 0x100 80015ce: 641a str r2, [r3, #64] ; 0x40 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 80015d0: 6c1a ldr r2, [r3, #64] ; 0x40 80015d2: 04d2 lsls r2, r2, #19 80015d4: d403 bmi.n 80015de SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80015d6: 6c1a ldr r2, [r3, #64] ; 0x40 80015d8: f042 0201 orr.w r2, r2, #1 80015dc: 641a str r2, [r3, #64] ; 0x40 HAL_ADC_ConvCpltCallback(hadc); 80015de: 4618 mov r0, r3 80015e0: f7ff bfcc b.w 800157c hadc->DMA_Handle->XferErrorCallback(hdma); 80015e4: 6b9b ldr r3, [r3, #56] ; 0x38 80015e6: 6b1b ldr r3, [r3, #48] ; 0x30 80015e8: 4718 bx r3 80015ea: bf00 nop 080015ec : uint32_t tickstart = 0U; /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET ) 80015ec: 6802 ldr r2, [r0, #0] { 80015ee: b538 push {r3, r4, r5, lr} if (ADC_IS_ENABLE(hadc) != RESET ) 80015f0: 6893 ldr r3, [r2, #8] 80015f2: f003 0303 and.w r3, r3, #3 80015f6: 2b01 cmp r3, #1 80015f8: d001 beq.n 80015fe } } } /* Return HAL status */ return HAL_OK; 80015fa: 2000 movs r0, #0 } 80015fc: bd38 pop {r3, r4, r5, pc} if (ADC_IS_ENABLE(hadc) != RESET ) 80015fe: 6811 ldr r1, [r2, #0] 8001600: 07c9 lsls r1, r1, #31 8001602: d5fa bpl.n 80015fa if (ADC_DISABLING_CONDITIONS(hadc) != RESET) 8001604: 6891 ldr r1, [r2, #8] 8001606: f001 010d and.w r1, r1, #13 800160a: 2901 cmp r1, #1 800160c: 4604 mov r4, r0 800160e: d009 beq.n 8001624 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001610: 6c02 ldr r2, [r0, #64] ; 0x40 8001612: f042 0210 orr.w r2, r2, #16 8001616: 6402 str r2, [r0, #64] ; 0x40 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001618: 6c42 ldr r2, [r0, #68] ; 0x44 800161a: f042 0201 orr.w r2, r2, #1 return HAL_ERROR; 800161e: 4618 mov r0, r3 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001620: 6462 str r2, [r4, #68] ; 0x44 } 8001622: bd38 pop {r3, r4, r5, pc} __HAL_ADC_DISABLE(hadc); 8001624: 6893 ldr r3, [r2, #8] 8001626: 2103 movs r1, #3 8001628: f043 0302 orr.w r3, r3, #2 800162c: 6093 str r3, [r2, #8] 800162e: 6011 str r1, [r2, #0] tickstart = HAL_GetTick(); 8001630: f7ff ff9e bl 8001570 8001634: 4605 mov r5, r0 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 8001636: 6823 ldr r3, [r4, #0] 8001638: 689b ldr r3, [r3, #8] 800163a: 07db lsls r3, r3, #31 800163c: d5dd bpl.n 80015fa if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800163e: f7ff ff97 bl 8001570 8001642: 1b40 subs r0, r0, r5 8001644: 2802 cmp r0, #2 8001646: d9f6 bls.n 8001636 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001648: 6c23 ldr r3, [r4, #64] ; 0x40 800164a: f043 0310 orr.w r3, r3, #16 800164e: 6423 str r3, [r4, #64] ; 0x40 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8001650: 6c63 ldr r3, [r4, #68] ; 0x44 8001652: f043 0301 orr.w r3, r3, #1 8001656: 6463 str r3, [r4, #68] ; 0x44 8001658: 2001 movs r0, #1 } 800165a: bd38 pop {r3, r4, r5, pc} 0800165c : if (ADC_IS_ENABLE(hadc) == RESET) 800165c: 6802 ldr r2, [r0, #0] { 800165e: b538 push {r3, r4, r5, lr} if (ADC_IS_ENABLE(hadc) == RESET) 8001660: 6893 ldr r3, [r2, #8] 8001662: f003 0303 and.w r3, r3, #3 8001666: 2b01 cmp r3, #1 { 8001668: 4604 mov r4, r0 if (ADC_IS_ENABLE(hadc) == RESET) 800166a: d020 beq.n 80016ae if (ADC_ENABLING_CONDITIONS(hadc) == RESET) 800166c: 6891 ldr r1, [r2, #8] 800166e: 4b12 ldr r3, [pc, #72] ; (80016b8 ) 8001670: 4219 tst r1, r3 8001672: d009 beq.n 8001688 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8001674: 6c23 ldr r3, [r4, #64] ; 0x40 8001676: f043 0310 orr.w r3, r3, #16 800167a: 6423 str r3, [r4, #64] ; 0x40 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800167c: 6c63 ldr r3, [r4, #68] ; 0x44 800167e: f043 0301 orr.w r3, r3, #1 8001682: 6463 str r3, [r4, #68] ; 0x44 8001684: 2001 movs r0, #1 } 8001686: bd38 pop {r3, r4, r5, pc} __HAL_ADC_ENABLE(hadc); 8001688: 6893 ldr r3, [r2, #8] 800168a: f043 0301 orr.w r3, r3, #1 800168e: 6093 str r3, [r2, #8] tickstart = HAL_GetTick(); 8001690: f7ff ff6e bl 8001570 8001694: 4605 mov r5, r0 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 8001696: e004 b.n 80016a2 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8001698: f7ff ff6a bl 8001570 800169c: 1b43 subs r3, r0, r5 800169e: 2b02 cmp r3, #2 80016a0: d8e8 bhi.n 8001674 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 80016a2: 6823 ldr r3, [r4, #0] 80016a4: 681b ldr r3, [r3, #0] 80016a6: 07db lsls r3, r3, #31 80016a8: d5f6 bpl.n 8001698 return HAL_OK; 80016aa: 2000 movs r0, #0 } 80016ac: bd38 pop {r3, r4, r5, pc} if (ADC_IS_ENABLE(hadc) == RESET) 80016ae: 6813 ldr r3, [r2, #0] 80016b0: 07d9 lsls r1, r3, #31 80016b2: d5db bpl.n 800166c return HAL_OK; 80016b4: 2000 movs r0, #0 80016b6: e7f9 b.n 80016ac 80016b8: 8000003f .word 0x8000003f 080016bc : { 80016bc: b570 push {r4, r5, r6, lr} 80016be: b082 sub sp, #8 __IO uint32_t wait_loop_index = 0U; 80016c0: 2300 movs r3, #0 80016c2: 9301 str r3, [sp, #4] if(hadc == NULL) 80016c4: 2800 cmp r0, #0 80016c6: f000 808f beq.w 80017e8 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 80016ca: 6c03 ldr r3, [r0, #64] ; 0x40 80016cc: f013 0310 ands.w r3, r3, #16 80016d0: 4604 mov r4, r0 80016d2: d117 bne.n 8001704 if (hadc->State == HAL_ADC_STATE_RESET) 80016d4: 6c05 ldr r5, [r0, #64] ; 0x40 80016d6: 2d00 cmp r5, #0 80016d8: f000 8089 beq.w 80017ee 80016dc: 6822 ldr r2, [r4, #0] if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || 80016de: 6891 ldr r1, [r2, #8] 80016e0: 00ce lsls r6, r1, #3 80016e2: d575 bpl.n 80017d0 HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) ) 80016e4: 6891 ldr r1, [r2, #8] if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || 80016e6: 008d lsls r5, r1, #2 80016e8: d472 bmi.n 80017d0 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 80016ea: 6c21 ldr r1, [r4, #64] ; 0x40 80016ec: 06c8 lsls r0, r1, #27 80016ee: d400 bmi.n 80016f2 80016f0: b163 cbz r3, 800170c ADC_STATE_CLR_SET(hadc->State, 80016f2: 6c23 ldr r3, [r4, #64] ; 0x40 80016f4: f023 0312 bic.w r3, r3, #18 80016f8: f043 0310 orr.w r3, r3, #16 tmp_hal_status = HAL_ERROR; 80016fc: 2001 movs r0, #1 ADC_STATE_CLR_SET(hadc->State, 80016fe: 6423 str r3, [r4, #64] ; 0x40 } 8001700: b002 add sp, #8 8001702: bd70 pop {r4, r5, r6, pc} if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8001704: 6c03 ldr r3, [r0, #64] ; 0x40 8001706: 06d8 lsls r0, r3, #27 8001708: d4f3 bmi.n 80016f2 800170a: 6822 ldr r2, [r4, #0] (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) 800170c: 6890 ldr r0, [r2, #8] (tmp_hal_status == HAL_OK) && 800170e: f010 0004 ands.w r0, r0, #4 8001712: d1ee bne.n 80016f2 ADC_STATE_CLR_SET(hadc->State, 8001714: 6c21 ldr r1, [r4, #64] ; 0x40 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8001716: 4b67 ldr r3, [pc, #412] ; (80018b4 ) ADC_STATE_CLR_SET(hadc->State, 8001718: f421 7181 bic.w r1, r1, #258 ; 0x102 800171c: f041 0102 orr.w r1, r1, #2 8001720: 6421 str r1, [r4, #64] ; 0x40 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001722: 6891 ldr r1, [r2, #8] ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8001724: f1b2 4fa0 cmp.w r2, #1342177280 ; 0x50000000 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001728: f001 0103 and.w r1, r1, #3 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 800172c: bf18 it ne 800172e: f04f 43a0 movne.w r3, #1342177280 ; 0x50000000 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001732: 2901 cmp r1, #1 8001734: f000 80a9 beq.w 800188a (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) 8001738: 6899 ldr r1, [r3, #8] 800173a: f001 0103 and.w r1, r1, #3 800173e: 2901 cmp r1, #1 8001740: f000 80a8 beq.w 8001894 MODIFY_REG(tmpADC_Common->CCR , 8001744: 495c ldr r1, [pc, #368] ; (80018b8 ) 8001746: 6865 ldr r5, [r4, #4] 8001748: 688b ldr r3, [r1, #8] 800174a: f423 3340 bic.w r3, r3, #196608 ; 0x30000 800174e: 432b orrs r3, r5 8001750: 608b str r3, [r1, #8] SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001752: e9d4 3102 ldrd r3, r1, [r4, #8] 8001756: 6b66 ldr r6, [r4, #52] ; 0x34 8001758: 7e65 ldrb r5, [r4, #25] 800175a: 430b orrs r3, r1 if (hadc->Init.DiscontinuousConvMode == ENABLE) 800175c: f894 1020 ldrb.w r1, [r4, #32] SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001760: 2e01 cmp r6, #1 8001762: bf18 it ne 8001764: f44f 5080 movne.w r0, #4096 ; 0x1000 8001768: ea43 3345 orr.w r3, r3, r5, lsl #13 if (hadc->Init.DiscontinuousConvMode == ENABLE) 800176c: 2901 cmp r1, #1 SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800176e: ea43 0300 orr.w r3, r3, r0 if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001772: f000 8082 beq.w 800187a if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8001776: 6aa1 ldr r1, [r4, #40] ; 0x28 8001778: 2901 cmp r1, #1 800177a: d002 beq.n 8001782 SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) | 800177c: 6ae0 ldr r0, [r4, #44] ; 0x2c 800177e: 4301 orrs r1, r0 8001780: 430b orrs r3, r1 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 8001782: 6891 ldr r1, [r2, #8] 8001784: f011 0f0c tst.w r1, #12 8001788: d10c bne.n 80017a4 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY | 800178a: 68d1 ldr r1, [r2, #12] 800178c: f421 4180 bic.w r1, r1, #16384 ; 0x4000 8001790: f021 0102 bic.w r1, r1, #2 8001794: 60d1 str r1, [r2, #12] SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8001796: f894 1030 ldrb.w r1, [r4, #48] ; 0x30 800179a: 7e20 ldrb r0, [r4, #24] 800179c: 0049 lsls r1, r1, #1 800179e: ea41 3180 orr.w r1, r1, r0, lsl #14 80017a2: 430b orrs r3, r1 MODIFY_REG(hadc->Instance->CFGR, 80017a4: 68d5 ldr r5, [r2, #12] 80017a6: 4945 ldr r1, [pc, #276] ; (80018bc ) if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80017a8: 6920 ldr r0, [r4, #16] MODIFY_REG(hadc->Instance->CFGR, 80017aa: 4029 ands r1, r5 80017ac: 430b orrs r3, r1 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80017ae: 2801 cmp r0, #1 MODIFY_REG(hadc->Instance->CFGR, 80017b0: 60d3 str r3, [r2, #12] if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80017b2: d05a beq.n 800186a CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 80017b4: 6b13 ldr r3, [r2, #48] ; 0x30 80017b6: f023 030f bic.w r3, r3, #15 80017ba: 6313 str r3, [r2, #48] ; 0x30 ADC_CLEAR_ERRORCODE(hadc); 80017bc: 2000 movs r0, #0 80017be: 6460 str r0, [r4, #68] ; 0x44 ADC_STATE_CLR_SET(hadc->State, 80017c0: 6c23 ldr r3, [r4, #64] ; 0x40 80017c2: f023 0303 bic.w r3, r3, #3 80017c6: f043 0301 orr.w r3, r3, #1 80017ca: 6423 str r3, [r4, #64] ; 0x40 } 80017cc: b002 add sp, #8 80017ce: bd70 pop {r4, r5, r6, pc} ADC_STATE_CLR_SET(hadc->State, 80017d0: 6c23 ldr r3, [r4, #64] ; 0x40 80017d2: f023 0312 bic.w r3, r3, #18 80017d6: f043 0310 orr.w r3, r3, #16 80017da: 6423 str r3, [r4, #64] ; 0x40 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80017dc: 6c63 ldr r3, [r4, #68] ; 0x44 80017de: f043 0301 orr.w r3, r3, #1 80017e2: 6463 str r3, [r4, #68] ; 0x44 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 80017e4: 6c23 ldr r3, [r4, #64] ; 0x40 80017e6: e784 b.n 80016f2 return HAL_ERROR; 80017e8: 2001 movs r0, #1 } 80017ea: b002 add sp, #8 80017ec: bd70 pop {r4, r5, r6, pc} hadc->InjectionConfig.ContextQueue = 0U; 80017ee: e9c0 5512 strd r5, r5, [r0, #72] ; 0x48 ADC_CLEAR_ERRORCODE(hadc); 80017f2: 6445 str r5, [r0, #68] ; 0x44 hadc->Lock = HAL_UNLOCKED; 80017f4: f880 503c strb.w r5, [r0, #60] ; 0x3c HAL_ADC_MspInit(hadc); 80017f8: f7ff fd3c bl 8001274 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0)) 80017fc: 6822 ldr r2, [r4, #0] 80017fe: 6893 ldr r3, [r2, #8] 8001800: 00d9 lsls r1, r3, #3 8001802: d501 bpl.n 8001808 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001804: 462b mov r3, r5 8001806: e76a b.n 80016de tmp_hal_status = ADC_Disable(hadc); 8001808: 4620 mov r0, r4 800180a: f7ff feef bl 80015ec if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 800180e: 6c22 ldr r2, [r4, #64] ; 0x40 8001810: 06d2 lsls r2, r2, #27 tmp_hal_status = ADC_Disable(hadc); 8001812: 4603 mov r3, r0 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && 8001814: f53f af62 bmi.w 80016dc 8001818: 2800 cmp r0, #0 800181a: f47f af5f bne.w 80016dc ADC_STATE_CLR_SET(hadc->State, 800181e: 6c20 ldr r0, [r4, #64] ; 0x40 CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)); 8001820: 6822 ldr r2, [r4, #0] wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8001822: 4927 ldr r1, [pc, #156] ; (80018c0 ) 8001824: 4d27 ldr r5, [pc, #156] ; (80018c4 ) 8001826: 6809 ldr r1, [r1, #0] ADC_STATE_CLR_SET(hadc->State, 8001828: f420 5088 bic.w r0, r0, #4352 ; 0x1100 800182c: f020 0002 bic.w r0, r0, #2 8001830: f040 0002 orr.w r0, r0, #2 8001834: 6420 str r0, [r4, #64] ; 0x40 CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)); 8001836: 6890 ldr r0, [r2, #8] 8001838: f020 5040 bic.w r0, r0, #805306368 ; 0x30000000 800183c: 6090 str r0, [r2, #8] wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 800183e: fba5 0101 umull r0, r1, r5, r1 8001842: 0c89 lsrs r1, r1, #18 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); 8001844: 6890 ldr r0, [r2, #8] wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8001846: eb01 0181 add.w r1, r1, r1, lsl #2 800184a: 0049 lsls r1, r1, #1 SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); 800184c: f040 5080 orr.w r0, r0, #268435456 ; 0x10000000 8001850: 6090 str r0, [r2, #8] wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 8001852: 9101 str r1, [sp, #4] while(wait_loop_index != 0U) 8001854: 9901 ldr r1, [sp, #4] 8001856: 2900 cmp r1, #0 8001858: f43f af41 beq.w 80016de wait_loop_index--; 800185c: 9901 ldr r1, [sp, #4] 800185e: 3901 subs r1, #1 8001860: 9101 str r1, [sp, #4] while(wait_loop_index != 0U) 8001862: 9901 ldr r1, [sp, #4] 8001864: 2900 cmp r1, #0 8001866: d1f9 bne.n 800185c 8001868: e739 b.n 80016de MODIFY_REG(hadc->Instance->SQR1 , 800186a: 6b11 ldr r1, [r2, #48] ; 0x30 800186c: 69e3 ldr r3, [r4, #28] 800186e: f021 010f bic.w r1, r1, #15 8001872: 3b01 subs r3, #1 8001874: 430b orrs r3, r1 8001876: 6313 str r3, [r2, #48] ; 0x30 8001878: e7a0 b.n 80017bc if (hadc->Init.ContinuousConvMode == DISABLE) 800187a: b985 cbnz r5, 800189e SET_BIT(tmpCFGR, ADC_CFGR_DISCEN | 800187c: 6a61 ldr r1, [r4, #36] ; 0x24 800187e: 3901 subs r1, #1 8001880: ea43 4341 orr.w r3, r3, r1, lsl #17 8001884: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8001888: e775 b.n 8001776 if ((ADC_IS_ENABLE(hadc) == RESET) && 800188a: 6811 ldr r1, [r2, #0] 800188c: 07c9 lsls r1, r1, #31 800188e: f53f af60 bmi.w 8001752 8001892: e751 b.n 8001738 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) 8001894: 681b ldr r3, [r3, #0] 8001896: 07db lsls r3, r3, #31 8001898: f53f af5b bmi.w 8001752 800189c: e752 b.n 8001744 ADC_STATE_CLR_SET(hadc->State, 800189e: 6c21 ldr r1, [r4, #64] ; 0x40 80018a0: f021 0122 bic.w r1, r1, #34 ; 0x22 80018a4: f041 0120 orr.w r1, r1, #32 80018a8: 6421 str r1, [r4, #64] ; 0x40 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80018aa: 6c61 ldr r1, [r4, #68] ; 0x44 80018ac: f041 0101 orr.w r1, r1, #1 80018b0: 6461 str r1, [r4, #68] ; 0x44 80018b2: e760 b.n 8001776 80018b4: 50000100 .word 0x50000100 80018b8: 50000300 .word 0x50000300 80018bc: fff0c007 .word 0xfff0c007 80018c0: 20000800 .word 0x20000800 80018c4: 431bde83 .word 0x431bde83 080018c8 : if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 80018c8: 6803 ldr r3, [r0, #0] { 80018ca: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 80018ce: 689d ldr r5, [r3, #8] 80018d0: f015 0504 ands.w r5, r5, #4 80018d4: d113 bne.n 80018fe __HAL_LOCK(hadc); 80018d6: f890 303c ldrb.w r3, [r0, #60] ; 0x3c 80018da: 2b01 cmp r3, #1 80018dc: 4604 mov r4, r0 80018de: d00e beq.n 80018fe if(ADC_COMMON_CCR_MULTI(hadc) == RESET) 80018e0: f8df a0e8 ldr.w sl, [pc, #232] ; 80019cc __HAL_LOCK(hadc); 80018e4: 2701 movs r7, #1 80018e6: f880 703c strb.w r7, [r0, #60] ; 0x3c if(ADC_COMMON_CCR_MULTI(hadc) == RESET) 80018ea: f8da 6008 ldr.w r6, [sl, #8] 80018ee: f016 061f ands.w r6, r6, #31 80018f2: d008 beq.n 8001906 __HAL_UNLOCK(hadc); 80018f4: f880 503c strb.w r5, [r0, #60] ; 0x3c } 80018f8: 4638 mov r0, r7 80018fa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} tmp_hal_status = HAL_BUSY; 80018fe: 2702 movs r7, #2 } 8001900: 4638 mov r0, r7 8001902: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} tmp_hal_status = ADC_Enable(hadc); 8001906: 4688 mov r8, r1 8001908: 4691 mov r9, r2 800190a: f7ff fea7 bl 800165c if (tmp_hal_status == HAL_OK) 800190e: 4607 mov r7, r0 8001910: 2800 cmp r0, #0 8001912: d150 bne.n 80019b6 ADC_STATE_CLR_SET(hadc->State, 8001914: 6c23 ldr r3, [r4, #64] ; 0x40 8001916: 6821 ldr r1, [r4, #0] 8001918: f423 6370 bic.w r3, r3, #3840 ; 0xf00 800191c: f023 0301 bic.w r3, r3, #1 8001920: f443 7380 orr.w r3, r3, #256 ; 0x100 8001924: 6423 str r3, [r4, #64] ; 0x40 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 8001926: f8da 3008 ldr.w r3, [sl, #8] 800192a: 06d8 lsls r0, r3, #27 800192c: d03b beq.n 80019a6 800192e: f1b1 4fa0 cmp.w r1, #1342177280 ; 0x50000000 8001932: d038 beq.n 80019a6 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001934: 6c23 ldr r3, [r4, #64] ; 0x40 if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8001936: 4a21 ldr r2, [pc, #132] ; (80019bc ) SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001938: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 800193c: 4291 cmp r1, r2 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 800193e: 6423 str r3, [r4, #64] ; 0x40 if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) 8001940: d10a bne.n 8001958 8001942: f04f 43a0 mov.w r3, #1342177280 ; 0x50000000 8001946: 68db ldr r3, [r3, #12] 8001948: 019b lsls r3, r3, #6 800194a: d505 bpl.n 8001958 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 800194c: 6c23 ldr r3, [r4, #64] ; 0x40 800194e: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8001952: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8001956: 6423 str r3, [r4, #64] ; 0x40 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001958: 6c23 ldr r3, [r4, #64] ; 0x40 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800195a: 6ba0 ldr r0, [r4, #56] ; 0x38 800195c: 4a18 ldr r2, [pc, #96] ; (80019c0 ) if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 800195e: f413 5380 ands.w r3, r3, #4096 ; 0x1000 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8001962: bf1c itt ne 8001964: 6c63 ldrne r3, [r4, #68] ; 0x44 8001966: f023 0306 bicne.w r3, r3, #6 ADC_CLEAR_ERRORCODE(hadc); 800196a: 6463 str r3, [r4, #68] ; 0x44 __HAL_UNLOCK(hadc); 800196c: 2600 movs r6, #0 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800196e: 4b15 ldr r3, [pc, #84] ; (80019c4 ) __HAL_UNLOCK(hadc); 8001970: f884 603c strb.w r6, [r4, #60] ; 0x3c hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8001974: 6282 str r2, [r0, #40] ; 0x28 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8001976: 62c3 str r3, [r0, #44] ; 0x2c hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8001978: 4a13 ldr r2, [pc, #76] ; (80019c8 ) 800197a: 6302 str r2, [r0, #48] ; 0x30 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 800197c: 231c movs r3, #28 800197e: 600b str r3, [r1, #0] __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8001980: 684b ldr r3, [r1, #4] 8001982: f043 0310 orr.w r3, r3, #16 8001986: 604b str r3, [r1, #4] SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 8001988: 68ce ldr r6, [r1, #12] 800198a: f046 0601 orr.w r6, r6, #1 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800198e: 464b mov r3, r9 8001990: 4642 mov r2, r8 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 8001992: 60ce str r6, [r1, #12] HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8001994: 3140 adds r1, #64 ; 0x40 8001996: f000 facb bl 8001f30 SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); 800199a: 6822 ldr r2, [r4, #0] 800199c: 6893 ldr r3, [r2, #8] 800199e: f043 0304 orr.w r3, r3, #4 80019a2: 6093 str r3, [r2, #8] 80019a4: e7a8 b.n 80018f8 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 80019a6: 6c23 ldr r3, [r4, #64] ; 0x40 80019a8: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 80019ac: 6423 str r3, [r4, #64] ; 0x40 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) 80019ae: 68cb ldr r3, [r1, #12] 80019b0: 019a lsls r2, r3, #6 80019b2: d5d1 bpl.n 8001958 80019b4: e7ca b.n 800194c __HAL_UNLOCK(hadc); 80019b6: f884 603c strb.w r6, [r4, #60] ; 0x3c 80019ba: e79d b.n 80018f8 80019bc: 50000100 .word 0x50000100 80019c0: 080015a9 .word 0x080015a9 80019c4: 080015a1 .word 0x080015a1 80019c8: 08001589 .word 0x08001589 80019cc: 50000300 .word 0x50000300 080019d0 : { 80019d0: b4f0 push {r4, r5, r6, r7} __HAL_LOCK(hadc); 80019d2: f890 203c ldrb.w r2, [r0, #60] ; 0x3c if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 80019d6: 68cc ldr r4, [r1, #12] { 80019d8: b082 sub sp, #8 80019da: 4603 mov r3, r0 __HAL_LOCK(hadc); 80019dc: 2a01 cmp r2, #1 __IO uint32_t wait_loop_index = 0U; 80019de: f04f 0000 mov.w r0, #0 80019e2: 9001 str r0, [sp, #4] __HAL_LOCK(hadc); 80019e4: f000 80c3 beq.w 8001b6e if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 80019e8: 681a ldr r2, [r3, #0] __HAL_LOCK(hadc); 80019ea: 2001 movs r0, #1 80019ec: f883 003c strb.w r0, [r3, #60] ; 0x3c if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 80019f0: 6895 ldr r5, [r2, #8] 80019f2: 076d lsls r5, r5, #29 80019f4: d436 bmi.n 8001a64 if (sConfig->Rank < 5U) 80019f6: 6848 ldr r0, [r1, #4] 80019f8: 2804 cmp r0, #4 80019fa: d87d bhi.n 8001af8 MODIFY_REG(hadc->Instance->SQR1, 80019fc: eb00 0040 add.w r0, r0, r0, lsl #1 8001a00: 6b16 ldr r6, [r2, #48] ; 0x30 8001a02: 680d ldr r5, [r1, #0] 8001a04: 0040 lsls r0, r0, #1 8001a06: 271f movs r7, #31 8001a08: 4087 lsls r7, r0 8001a0a: ea26 0607 bic.w r6, r6, r7 8001a0e: fa05 f000 lsl.w r0, r5, r0 8001a12: 4330 orrs r0, r6 8001a14: 6310 str r0, [r2, #48] ; 0x30 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 8001a16: 6890 ldr r0, [r2, #8] 8001a18: f010 0f0c tst.w r0, #12 8001a1c: d135 bne.n 8001a8a if (sConfig->Channel >= ADC_CHANNEL_10) 8001a1e: 2d09 cmp r5, #9 8001a20: f240 8093 bls.w 8001b4a MODIFY_REG(hadc->Instance->SMPR2 , 8001a24: eb05 0745 add.w r7, r5, r5, lsl #1 8001a28: 6990 ldr r0, [r2, #24] 8001a2a: 688e ldr r6, [r1, #8] 8001a2c: 3f1e subs r7, #30 8001a2e: f04f 0c07 mov.w ip, #7 8001a32: fa0c fc07 lsl.w ip, ip, r7 8001a36: ea20 000c bic.w r0, r0, ip 8001a3a: 40be lsls r6, r7 8001a3c: 4330 orrs r0, r6 8001a3e: 6190 str r0, [r2, #24] tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); 8001a40: e9d1 6704 ldrd r6, r7, [r1, #16] 8001a44: 68d0 ldr r0, [r2, #12] 8001a46: f3c0 00c1 ubfx r0, r0, #3, #2 8001a4a: 0040 lsls r0, r0, #1 8001a4c: 3e01 subs r6, #1 8001a4e: fa07 f000 lsl.w r0, r7, r0 switch (sConfig->OffsetNumber) 8001a52: 2e03 cmp r6, #3 8001a54: f200 811d bhi.w 8001c92 8001a58: e8df f016 tbh [pc, r6, lsl #1] 8001a5c: 00e4000e .word 0x00e4000e 8001a60: 00d000da .word 0x00d000da SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001a64: 6c1a ldr r2, [r3, #64] ; 0x40 8001a66: f042 0220 orr.w r2, r2, #32 8001a6a: 641a str r2, [r3, #64] ; 0x40 __HAL_UNLOCK(hadc); 8001a6c: 2200 movs r2, #0 8001a6e: f883 203c strb.w r2, [r3, #60] ; 0x3c } 8001a72: b002 add sp, #8 8001a74: bcf0 pop {r4, r5, r6, r7} 8001a76: 4770 bx lr MODIFY_REG(hadc->Instance->OFR1 , 8001a78: 6e17 ldr r7, [r2, #96] ; 0x60 8001a7a: 4e9c ldr r6, [pc, #624] ; (8001cec ) 8001a7c: 403e ands r6, r7 8001a7e: ea46 6685 orr.w r6, r6, r5, lsl #26 8001a82: 4330 orrs r0, r6 8001a84: f040 4000 orr.w r0, r0, #2147483648 ; 0x80000000 8001a88: 6610 str r0, [r2, #96] ; 0x60 if (ADC_IS_ENABLE(hadc) == RESET) 8001a8a: 6890 ldr r0, [r2, #8] 8001a8c: f000 0003 and.w r0, r0, #3 8001a90: 2801 cmp r0, #1 8001a92: d068 beq.n 8001b66 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 8001a94: 2c01 cmp r4, #1 8001a96: d06e beq.n 8001b76 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); 8001a98: f8d2 10b0 ldr.w r1, [r2, #176] ; 0xb0 8001a9c: 2001 movs r0, #1 8001a9e: 40a8 lsls r0, r5 8001aa0: ea21 0100 bic.w r1, r1, r0 8001aa4: f8c2 10b0 str.w r1, [r2, #176] ; 0xb0 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 8001aa8: 2d10 cmp r5, #16 8001aaa: d039 beq.n 8001b20 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || 8001aac: 2d11 cmp r5, #17 8001aae: d179 bne.n 8001ba4 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || 8001ab0: 498f ldr r1, [pc, #572] ; (8001cf0 ) 8001ab2: 6889 ldr r1, [r1, #8] ( (sConfig->Channel == ADC_CHANNEL_VBAT) && 8001ab4: 01ce lsls r6, r1, #7 8001ab6: d437 bmi.n 8001b28 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001ab8: 6890 ldr r0, [r2, #8] ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8001aba: 498e ldr r1, [pc, #568] ; (8001cf4 ) 8001abc: f1b2 4fa0 cmp.w r2, #1342177280 ; 0x50000000 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001ac0: f000 0003 and.w r0, r0, #3 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8001ac4: bf18 it ne 8001ac6: f04f 41a0 movne.w r1, #1342177280 ; 0x50000000 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001aca: 2801 cmp r0, #1 8001acc: f000 808c beq.w 8001be8 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) 8001ad0: 6888 ldr r0, [r1, #8] 8001ad2: f000 0003 and.w r0, r0, #3 8001ad6: 2801 cmp r0, #1 8001ad8: f000 80d7 beq.w 8001c8a if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) 8001adc: 2d10 cmp r5, #16 8001ade: f000 80b6 beq.w 8001c4e else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) 8001ae2: 2d11 cmp r5, #17 8001ae4: f000 80a8 beq.w 8001c38 else if (sConfig->Channel == ADC_CHANNEL_VREFINT) 8001ae8: 2d12 cmp r5, #18 8001aea: d11d bne.n 8001b28 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); 8001aec: 4980 ldr r1, [pc, #512] ; (8001cf0 ) 8001aee: 688a ldr r2, [r1, #8] 8001af0: f442 0280 orr.w r2, r2, #4194304 ; 0x400000 8001af4: 608a str r2, [r1, #8] 8001af6: e017 b.n 8001b28 else if (sConfig->Rank < 10U) 8001af8: 2809 cmp r0, #9 8001afa: d917 bls.n 8001b2c else if (sConfig->Rank < 15U) 8001afc: 280e cmp r0, #14 MODIFY_REG(hadc->Instance->SQR3 , 8001afe: eb00 0040 add.w r0, r0, r0, lsl #1 8001b02: ea4f 0040 mov.w r0, r0, lsl #1 else if (sConfig->Rank < 15U) 8001b06: d863 bhi.n 8001bd0 MODIFY_REG(hadc->Instance->SQR3 , 8001b08: 6b96 ldr r6, [r2, #56] ; 0x38 8001b0a: 680d ldr r5, [r1, #0] 8001b0c: 383c subs r0, #60 ; 0x3c 8001b0e: 271f movs r7, #31 8001b10: 4087 lsls r7, r0 8001b12: ea26 0607 bic.w r6, r6, r7 8001b16: fa05 f000 lsl.w r0, r5, r0 8001b1a: 4330 orrs r0, r6 8001b1c: 6390 str r0, [r2, #56] ; 0x38 8001b1e: e77a b.n 8001a16 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || 8001b20: 4973 ldr r1, [pc, #460] ; (8001cf0 ) 8001b22: 6889 ldr r1, [r1, #8] if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 8001b24: 020f lsls r7, r1, #8 8001b26: d5c7 bpl.n 8001ab8 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001b28: 2000 movs r0, #0 8001b2a: e79f b.n 8001a6c MODIFY_REG(hadc->Instance->SQR2, 8001b2c: eb00 0040 add.w r0, r0, r0, lsl #1 8001b30: 0040 lsls r0, r0, #1 8001b32: 6b56 ldr r6, [r2, #52] ; 0x34 8001b34: 680d ldr r5, [r1, #0] 8001b36: 381e subs r0, #30 8001b38: 271f movs r7, #31 8001b3a: 4087 lsls r7, r0 8001b3c: ea26 0607 bic.w r6, r6, r7 8001b40: fa05 f000 lsl.w r0, r5, r0 8001b44: 4330 orrs r0, r6 8001b46: 6350 str r0, [r2, #52] ; 0x34 8001b48: e765 b.n 8001a16 MODIFY_REG(hadc->Instance->SMPR1 , 8001b4a: 6950 ldr r0, [r2, #20] 8001b4c: 688e ldr r6, [r1, #8] 8001b4e: eb05 0c45 add.w ip, r5, r5, lsl #1 8001b52: 2707 movs r7, #7 8001b54: fa07 f70c lsl.w r7, r7, ip 8001b58: ea20 0007 bic.w r0, r0, r7 8001b5c: fa06 f60c lsl.w r6, r6, ip 8001b60: 4330 orrs r0, r6 8001b62: 6150 str r0, [r2, #20] 8001b64: e76c b.n 8001a40 if (ADC_IS_ENABLE(hadc) == RESET) 8001b66: 6810 ldr r0, [r2, #0] 8001b68: 07c0 lsls r0, r0, #31 8001b6a: d593 bpl.n 8001a94 8001b6c: e7dc b.n 8001b28 __HAL_LOCK(hadc); 8001b6e: 2002 movs r0, #2 } 8001b70: b002 add sp, #8 8001b72: bcf0 pop {r4, r5, r6, r7} 8001b74: 4770 bx lr SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); 8001b76: f8d2 00b0 ldr.w r0, [r2, #176] ; 0xb0 8001b7a: 40ac lsls r4, r5 8001b7c: 4304 orrs r4, r0 if (sConfig->Channel >= ADC_CHANNEL_10) 8001b7e: 2d09 cmp r5, #9 SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); 8001b80: f8c2 40b0 str.w r4, [r2, #176] ; 0xb0 if (sConfig->Channel >= ADC_CHANNEL_10) 8001b84: d915 bls.n 8001bb2 MODIFY_REG(hadc->Instance->SMPR2, 8001b86: eb05 0045 add.w r0, r5, r5, lsl #1 8001b8a: 688e ldr r6, [r1, #8] 8001b8c: 6994 ldr r4, [r2, #24] 8001b8e: f1a0 011b sub.w r1, r0, #27 8001b92: 2707 movs r7, #7 8001b94: 408f lsls r7, r1 8001b96: fa06 f001 lsl.w r0, r6, r1 8001b9a: ea24 0107 bic.w r1, r4, r7 8001b9e: 4301 orrs r1, r0 8001ba0: 6191 str r1, [r2, #24] 8001ba2: e781 b.n 8001aa8 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || 8001ba4: 2d12 cmp r5, #18 8001ba6: d1bf bne.n 8001b28 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) 8001ba8: 4951 ldr r1, [pc, #324] ; (8001cf0 ) 8001baa: 6889 ldr r1, [r1, #8] ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && 8001bac: 024c lsls r4, r1, #9 8001bae: d4bb bmi.n 8001b28 8001bb0: e782 b.n 8001ab8 MODIFY_REG(hadc->Instance->SMPR1, 8001bb2: 3501 adds r5, #1 8001bb4: 6888 ldr r0, [r1, #8] 8001bb6: 6951 ldr r1, [r2, #20] 8001bb8: eb05 0545 add.w r5, r5, r5, lsl #1 8001bbc: 2407 movs r4, #7 8001bbe: 40ac lsls r4, r5 8001bc0: ea21 0104 bic.w r1, r1, r4 8001bc4: fa00 f505 lsl.w r5, r0, r5 8001bc8: 4329 orrs r1, r5 8001bca: 6151 str r1, [r2, #20] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001bcc: 2000 movs r0, #0 8001bce: e74d b.n 8001a6c MODIFY_REG(hadc->Instance->SQR4 , 8001bd0: 6bd6 ldr r6, [r2, #60] ; 0x3c 8001bd2: 680d ldr r5, [r1, #0] 8001bd4: 385a subs r0, #90 ; 0x5a 8001bd6: 271f movs r7, #31 8001bd8: 4087 lsls r7, r0 8001bda: ea26 0607 bic.w r6, r6, r7 8001bde: fa05 f000 lsl.w r0, r5, r0 8001be2: 4330 orrs r0, r6 8001be4: 63d0 str r0, [r2, #60] ; 0x3c 8001be6: e716 b.n 8001a16 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001be8: 6810 ldr r0, [r2, #0] 8001bea: 07c0 lsls r0, r0, #31 8001bec: f57f af70 bpl.w 8001ad0 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001bf0: 6c1a ldr r2, [r3, #64] ; 0x40 8001bf2: f042 0220 orr.w r2, r2, #32 8001bf6: 641a str r2, [r3, #64] ; 0x40 tmp_hal_status = HAL_ERROR; 8001bf8: 2001 movs r0, #1 8001bfa: e737 b.n 8001a6c MODIFY_REG(hadc->Instance->OFR4 , 8001bfc: 6ed7 ldr r7, [r2, #108] ; 0x6c 8001bfe: 4e3b ldr r6, [pc, #236] ; (8001cec ) 8001c00: 403e ands r6, r7 8001c02: ea46 6685 orr.w r6, r6, r5, lsl #26 8001c06: 4330 orrs r0, r6 8001c08: f040 4000 orr.w r0, r0, #2147483648 ; 0x80000000 8001c0c: 66d0 str r0, [r2, #108] ; 0x6c break; 8001c0e: e73c b.n 8001a8a MODIFY_REG(hadc->Instance->OFR3 , 8001c10: 6e97 ldr r7, [r2, #104] ; 0x68 8001c12: 4e36 ldr r6, [pc, #216] ; (8001cec ) 8001c14: 403e ands r6, r7 8001c16: ea46 6685 orr.w r6, r6, r5, lsl #26 8001c1a: 4330 orrs r0, r6 8001c1c: f040 4000 orr.w r0, r0, #2147483648 ; 0x80000000 8001c20: 6690 str r0, [r2, #104] ; 0x68 break; 8001c22: e732 b.n 8001a8a MODIFY_REG(hadc->Instance->OFR2 , 8001c24: 6e57 ldr r7, [r2, #100] ; 0x64 8001c26: 4e31 ldr r6, [pc, #196] ; (8001cec ) 8001c28: 403e ands r6, r7 8001c2a: ea46 6685 orr.w r6, r6, r5, lsl #26 8001c2e: 4330 orrs r0, r6 8001c30: f040 4000 orr.w r0, r0, #2147483648 ; 0x80000000 8001c34: 6650 str r0, [r2, #100] ; 0x64 break; 8001c36: e728 b.n 8001a8a else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) 8001c38: f1b2 4fa0 cmp.w r2, #1342177280 ; 0x50000000 8001c3c: f47f af74 bne.w 8001b28 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); 8001c40: 492b ldr r1, [pc, #172] ; (8001cf0 ) 8001c42: 688a ldr r2, [r1, #8] 8001c44: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000 8001c48: 608a str r2, [r1, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001c4a: 2000 movs r0, #0 SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); 8001c4c: e70e b.n 8001a6c if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) 8001c4e: f1b2 4fa0 cmp.w r2, #1342177280 ; 0x50000000 8001c52: f47f af69 bne.w 8001b28 SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); 8001c56: 4926 ldr r1, [pc, #152] ; (8001cf0 ) wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8001c58: 4c27 ldr r4, [pc, #156] ; (8001cf8 ) SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); 8001c5a: 688a ldr r2, [r1, #8] wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8001c5c: 4827 ldr r0, [pc, #156] ; (8001cfc ) SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); 8001c5e: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 8001c62: 608a str r2, [r1, #8] wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 8001c64: 6822 ldr r2, [r4, #0] 8001c66: fba0 1202 umull r1, r2, r0, r2 8001c6a: 0c92 lsrs r2, r2, #18 8001c6c: eb02 0282 add.w r2, r2, r2, lsl #2 8001c70: 0052 lsls r2, r2, #1 8001c72: 9201 str r2, [sp, #4] while(wait_loop_index != 0U) 8001c74: 9a01 ldr r2, [sp, #4] 8001c76: 2a00 cmp r2, #0 8001c78: f43f af56 beq.w 8001b28 wait_loop_index--; 8001c7c: 9a01 ldr r2, [sp, #4] 8001c7e: 3a01 subs r2, #1 8001c80: 9201 str r2, [sp, #4] while(wait_loop_index != 0U) 8001c82: 9a01 ldr r2, [sp, #4] 8001c84: 2a00 cmp r2, #0 8001c86: d1f9 bne.n 8001c7c 8001c88: e74e b.n 8001b28 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) 8001c8a: 6809 ldr r1, [r1, #0] 8001c8c: 07c9 lsls r1, r1, #31 8001c8e: d4af bmi.n 8001bf0 8001c90: e724 b.n 8001adc if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8001c92: 6e10 ldr r0, [r2, #96] ; 0x60 8001c94: f000 40f8 and.w r0, r0, #2080374784 ; 0x7c000000 8001c98: ebb0 6f85 cmp.w r0, r5, lsl #26 8001c9c: ea4f 6685 mov.w r6, r5, lsl #26 8001ca0: d014 beq.n 8001ccc if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8001ca2: 6e50 ldr r0, [r2, #100] ; 0x64 8001ca4: f000 40f8 and.w r0, r0, #2080374784 ; 0x7c000000 8001ca8: 4286 cmp r6, r0 8001caa: d014 beq.n 8001cd6 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8001cac: 6e90 ldr r0, [r2, #104] ; 0x68 8001cae: f000 40f8 and.w r0, r0, #2080374784 ; 0x7c000000 8001cb2: 4286 cmp r6, r0 8001cb4: d014 beq.n 8001ce0 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8001cb6: 6ed0 ldr r0, [r2, #108] ; 0x6c 8001cb8: f000 40f8 and.w r0, r0, #2080374784 ; 0x7c000000 8001cbc: 4286 cmp r6, r0 8001cbe: f47f aee4 bne.w 8001a8a CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); 8001cc2: 6ed0 ldr r0, [r2, #108] ; 0x6c 8001cc4: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001cc8: 66d0 str r0, [r2, #108] ; 0x6c 8001cca: e6de b.n 8001a8a CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); 8001ccc: 6e10 ldr r0, [r2, #96] ; 0x60 8001cce: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001cd2: 6610 str r0, [r2, #96] ; 0x60 8001cd4: e7e5 b.n 8001ca2 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); 8001cd6: 6e50 ldr r0, [r2, #100] ; 0x64 8001cd8: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001cdc: 6650 str r0, [r2, #100] ; 0x64 8001cde: e7e5 b.n 8001cac CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); 8001ce0: 6e90 ldr r0, [r2, #104] ; 0x68 8001ce2: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8001ce6: 6690 str r0, [r2, #104] ; 0x68 8001ce8: e7e5 b.n 8001cb6 8001cea: bf00 nop 8001cec: 83fff000 .word 0x83fff000 8001cf0: 50000300 .word 0x50000300 8001cf4: 50000100 .word 0x50000100 8001cf8: 20000800 .word 0x20000800 8001cfc: 431bde83 .word 0x431bde83 08001d00 : { 8001d00: b4f0 push {r4, r5, r6, r7} 8001d02: 4603 mov r3, r0 ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8001d04: 4835 ldr r0, [pc, #212] ; (8001ddc ) 8001d06: 681c ldr r4, [r3, #0] __HAL_LOCK(hadc); 8001d08: f893 203c ldrb.w r2, [r3, #60] ; 0x3c ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); 8001d0c: f1b4 4fa0 cmp.w r4, #1342177280 ; 0x50000000 8001d10: bf18 it ne 8001d12: f04f 40a0 movne.w r0, #1342177280 ; 0x50000000 __HAL_LOCK(hadc); 8001d16: 2a01 cmp r2, #1 8001d18: d035 beq.n 8001d86 8001d1a: 2201 movs r2, #1 if(multimode->Mode != ADC_MODE_INDEPENDENT) 8001d1c: 680d ldr r5, [r1, #0] __HAL_LOCK(hadc); 8001d1e: f883 203c strb.w r2, [r3, #60] ; 0x3c if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 8001d22: 68a2 ldr r2, [r4, #8] 8001d24: 0757 lsls r7, r2, #29 8001d26: d509 bpl.n 8001d3c SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001d28: 6c1a ldr r2, [r3, #64] ; 0x40 8001d2a: f042 0220 orr.w r2, r2, #32 8001d2e: 641a str r2, [r3, #64] ; 0x40 tmp_hal_status = HAL_ERROR; 8001d30: 2001 movs r0, #1 __HAL_UNLOCK(hadc); 8001d32: 2200 movs r2, #0 8001d34: f883 203c strb.w r2, [r3, #60] ; 0x3c } 8001d38: bcf0 pop {r4, r5, r6, r7} 8001d3a: 4770 bx lr && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) ) 8001d3c: 6882 ldr r2, [r0, #8] 8001d3e: 0756 lsls r6, r2, #29 8001d40: d4f2 bmi.n 8001d28 if(multimode->Mode != ADC_MODE_INDEPENDENT) 8001d42: b31d cbz r5, 8001d8c MODIFY_REG(tmpADC_Common->CCR , 8001d44: 4f26 ldr r7, [pc, #152] ; (8001de0 ) 8001d46: 684e ldr r6, [r1, #4] 8001d48: 68ba ldr r2, [r7, #8] 8001d4a: f893 c030 ldrb.w ip, [r3, #48] ; 0x30 8001d4e: f422 4260 bic.w r2, r2, #57344 ; 0xe000 8001d52: 4332 orrs r2, r6 8001d54: ea42 324c orr.w r2, r2, ip, lsl #13 8001d58: 60ba str r2, [r7, #8] if ((ADC_IS_ENABLE(hadc) == RESET) && 8001d5a: 68a2 ldr r2, [r4, #8] 8001d5c: f002 0203 and.w r2, r2, #3 8001d60: 2a01 cmp r2, #1 8001d62: d037 beq.n 8001dd4 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) 8001d64: 6882 ldr r2, [r0, #8] 8001d66: f002 0203 and.w r2, r2, #3 8001d6a: 2a01 cmp r2, #1 8001d6c: d02a beq.n 8001dc4 MODIFY_REG(tmpADC_Common->CCR , 8001d6e: 481c ldr r0, [pc, #112] ; (8001de0 ) 8001d70: 6889 ldr r1, [r1, #8] 8001d72: 6882 ldr r2, [r0, #8] 8001d74: f422 6271 bic.w r2, r2, #3856 ; 0xf10 8001d78: 430d orrs r5, r1 8001d7a: f022 020f bic.w r2, r2, #15 8001d7e: 4315 orrs r5, r2 8001d80: 6085 str r5, [r0, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001d82: 2000 movs r0, #0 8001d84: e7d5 b.n 8001d32 __HAL_LOCK(hadc); 8001d86: 2002 movs r0, #2 } 8001d88: bcf0 pop {r4, r5, r6, r7} 8001d8a: 4770 bx lr CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); 8001d8c: 4914 ldr r1, [pc, #80] ; (8001de0 ) 8001d8e: 688a ldr r2, [r1, #8] 8001d90: f422 4260 bic.w r2, r2, #57344 ; 0xe000 8001d94: 608a str r2, [r1, #8] if ((ADC_IS_ENABLE(hadc) == RESET) && 8001d96: 68a2 ldr r2, [r4, #8] 8001d98: f002 0203 and.w r2, r2, #3 8001d9c: 2a01 cmp r2, #1 8001d9e: d015 beq.n 8001dcc (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) 8001da0: 6882 ldr r2, [r0, #8] 8001da2: f002 0203 and.w r2, r2, #3 8001da6: 2a01 cmp r2, #1 8001da8: d008 beq.n 8001dbc CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY); 8001daa: 490d ldr r1, [pc, #52] ; (8001de0 ) 8001dac: 688a ldr r2, [r1, #8] 8001dae: f422 6271 bic.w r2, r2, #3856 ; 0xf10 8001db2: f022 020f bic.w r2, r2, #15 8001db6: 608a str r2, [r1, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001db8: 2000 movs r0, #0 8001dba: e7ba b.n 8001d32 (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) 8001dbc: 6802 ldr r2, [r0, #0] 8001dbe: 07d2 lsls r2, r2, #31 8001dc0: d4df bmi.n 8001d82 8001dc2: e7f2 b.n 8001daa (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) 8001dc4: 6802 ldr r2, [r0, #0] 8001dc6: 07d0 lsls r0, r2, #31 8001dc8: d4db bmi.n 8001d82 8001dca: e7d0 b.n 8001d6e if ((ADC_IS_ENABLE(hadc) == RESET) && 8001dcc: 6822 ldr r2, [r4, #0] 8001dce: 07d1 lsls r1, r2, #31 8001dd0: d4d7 bmi.n 8001d82 8001dd2: e7e5 b.n 8001da0 if ((ADC_IS_ENABLE(hadc) == RESET) && 8001dd4: 6822 ldr r2, [r4, #0] 8001dd6: 07d4 lsls r4, r2, #31 8001dd8: d5c4 bpl.n 8001d64 8001dda: e7d2 b.n 8001d82 8001ddc: 50000100 .word 0x50000100 8001de0: 50000300 .word 0x50000300 08001de4 : reg_value = SCB->AIRCR; /* read old register configuration */ 8001de4: 4908 ldr r1, [pc, #32] ; (8001e08 ) 8001de6: 68ca ldr r2, [r1, #12] * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001de8: b410 push {r4} (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001dea: 0200 lsls r0, r0, #8 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001dec: f64f 04ff movw r4, #63743 ; 0xf8ff 8001df0: 4022 ands r2, r4 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001df2: f400 63e0 and.w r3, r0, #1792 ; 0x700 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001df6: 4313 orrs r3, r2 reg_value = (reg_value | 8001df8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8001dfc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } 8001e00: f85d 4b04 ldr.w r4, [sp], #4 SCB->AIRCR = reg_value; 8001e04: 60cb str r3, [r1, #12] 8001e06: 4770 bx lr 8001e08: e000ed00 .word 0xe000ed00 08001e0c : return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001e0c: 4b19 ldr r3, [pc, #100] ; (8001e74 ) 8001e0e: 68db ldr r3, [r3, #12] 8001e10: f3c3 2302 ubfx r3, r3, #8, #3 * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001e14: b430 push {r4, r5} PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001e16: f1c3 0507 rsb r5, r3, #7 8001e1a: 2d04 cmp r5, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001e1c: f103 0404 add.w r4, r3, #4 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001e20: bf28 it cs 8001e22: 2504 movcs r5, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001e24: 2c06 cmp r4, #6 8001e26: d919 bls.n 8001e5c 8001e28: 3b03 subs r3, #3 8001e2a: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff 8001e2e: 409c lsls r4, r3 8001e30: ea22 0204 bic.w r2, r2, r4 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001e34: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff 8001e38: 40ac lsls r4, r5 8001e3a: ea21 0104 bic.w r1, r1, r4 8001e3e: 4099 lsls r1, r3 if ((int32_t)(IRQn) >= 0) 8001e40: 2800 cmp r0, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001e42: ea41 0102 orr.w r1, r1, r2 if ((int32_t)(IRQn) >= 0) 8001e46: db0c blt.n 8001e62 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001e48: f100 4060 add.w r0, r0, #3758096384 ; 0xe0000000 8001e4c: f500 4061 add.w r0, r0, #57600 ; 0xe100 8001e50: 0109 lsls r1, r1, #4 8001e52: b2c9 uxtb r1, r1 8001e54: f880 1300 strb.w r1, [r0, #768] ; 0x300 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } 8001e58: bc30 pop {r4, r5} 8001e5a: 4770 bx lr 8001e5c: 2200 movs r2, #0 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001e5e: 4613 mov r3, r2 8001e60: e7e8 b.n 8001e34 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001e62: 4b05 ldr r3, [pc, #20] ; (8001e78 ) 8001e64: f000 000f and.w r0, r0, #15 8001e68: 0109 lsls r1, r1, #4 8001e6a: 4403 add r3, r0 8001e6c: b2c9 uxtb r1, r1 8001e6e: 7619 strb r1, [r3, #24] 8001e70: bc30 pop {r4, r5} 8001e72: 4770 bx lr 8001e74: e000ed00 .word 0xe000ed00 8001e78: e000ecfc .word 0xe000ecfc 08001e7c : if ((int32_t)(IRQn) >= 0) 8001e7c: 2800 cmp r0, #0 8001e7e: db07 blt.n 8001e90 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001e80: f000 011f and.w r1, r0, #31 8001e84: 4a03 ldr r2, [pc, #12] ; (8001e94 ) 8001e86: 0940 lsrs r0, r0, #5 8001e88: 2301 movs r3, #1 8001e8a: 408b lsls r3, r1 8001e8c: f842 3020 str.w r3, [r2, r0, lsl #2] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } 8001e90: 4770 bx lr 8001e92: bf00 nop 8001e94: e000e100 .word 0xe000e100 08001e98 : function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001e98: 3801 subs r0, #1 8001e9a: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 8001e9e: d20e bcs.n 8001ebe { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001ea0: 4b08 ldr r3, [pc, #32] ; (8001ec4 ) * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001ea2: b410 push {r4} SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ea4: 4c08 ldr r4, [pc, #32] ; (8001ec8 ) SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001ea6: 6058 str r0, [r3, #4] SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001ea8: 20f0 movs r0, #240 ; 0xf0 8001eaa: f884 0023 strb.w r0, [r4, #35] ; 0x23 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001eae: 2200 movs r2, #0 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001eb0: 2107 movs r1, #7 SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001eb2: 4610 mov r0, r2 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001eb4: 609a str r2, [r3, #8] return SysTick_Config(TicksNumb); } 8001eb6: f85d 4b04 ldr.w r4, [sp], #4 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001eba: 6019 str r1, [r3, #0] 8001ebc: 4770 bx lr return (1UL); /* Reload value impossible */ 8001ebe: 2001 movs r0, #1 8001ec0: 4770 bx lr 8001ec2: bf00 nop 8001ec4: e000e010 .word 0xe000e010 8001ec8: e000ed00 .word 0xe000ed00 08001ecc : HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0U; /* Check the DMA handle allocation */ if(NULL == hdma) 8001ecc: b338 cbz r0, 8001f1e { 8001ece: b470 push {r4, r5, r6} tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 8001ed0: e9d0 2501 ldrd r2, r5, [r0, #4] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001ed4: e9d0 1403 ldrd r1, r4, [r0, #12] 8001ed8: 4603 mov r3, r0 tmp |= hdma->Init.Direction | 8001eda: 432a orrs r2, r5 tmp = hdma->Instance->CCR; 8001edc: 6800 ldr r0, [r0, #0] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001ede: 695e ldr r6, [r3, #20] 8001ee0: 699d ldr r5, [r3, #24] hdma->Init.PeriphInc | hdma->Init.MemInc | 8001ee2: 430a orrs r2, r1 8001ee4: 4322 orrs r2, r4 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001ee6: 4332 orrs r2, r6 tmp = hdma->Instance->CCR; 8001ee8: 6804 ldr r4, [r0, #0] hdma->DmaBaseAddress = DMA2; } #else /* calculation of the channel index */ /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8001eea: 490e ldr r1, [pc, #56] ; (8001f24 ) 8001eec: 4e0e ldr r6, [pc, #56] ; (8001f28 ) hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8001eee: 432a orrs r2, r5 hdma->Init.Mode | hdma->Init.Priority; 8001ef0: 69dd ldr r5, [r3, #28] tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8001ef2: f424 547f bic.w r4, r4, #16320 ; 0x3fc0 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8001ef6: 4401 add r1, r0 hdma->Init.Mode | hdma->Init.Priority; 8001ef8: 432a orrs r2, r5 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8001efa: f024 0430 bic.w r4, r4, #48 ; 0x30 tmp |= hdma->Init.Direction | 8001efe: 4322 orrs r2, r4 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8001f00: fba6 6101 umull r6, r1, r6, r1 hdma->Instance->CCR = tmp; 8001f04: 6002 str r2, [r0, #0] hdma->DmaBaseAddress = DMA1; 8001f06: 4c09 ldr r4, [pc, #36] ; (8001f2c ) hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8001f08: 0909 lsrs r1, r1, #4 hdma->Lock = HAL_UNLOCKED; 8001f0a: f44f 7280 mov.w r2, #256 ; 0x100 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001f0e: 2000 movs r0, #0 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; 8001f10: 0089 lsls r1, r1, #2 hdma->Lock = HAL_UNLOCKED; 8001f12: 841a strh r2, [r3, #32] hdma->DmaBaseAddress = DMA1; 8001f14: e9c3 410f strd r4, r1, [r3, #60] ; 0x3c } 8001f18: bc70 pop {r4, r5, r6} hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001f1a: 6398 str r0, [r3, #56] ; 0x38 } 8001f1c: 4770 bx lr return HAL_ERROR; 8001f1e: 2001 movs r0, #1 } 8001f20: 4770 bx lr 8001f22: bf00 nop 8001f24: bffdfff8 .word 0xbffdfff8 8001f28: cccccccd .word 0xcccccccd 8001f2c: 40020000 .word 0x40020000 08001f30 : { 8001f30: b4f0 push {r4, r5, r6, r7} __HAL_LOCK(hdma); 8001f32: f890 4020 ldrb.w r4, [r0, #32] 8001f36: 2c01 cmp r4, #1 8001f38: d039 beq.n 8001fae if(HAL_DMA_STATE_READY == hdma->State) 8001f3a: f890 5021 ldrb.w r5, [r0, #33] ; 0x21 __HAL_LOCK(hdma); 8001f3e: 2401 movs r4, #1 if(HAL_DMA_STATE_READY == hdma->State) 8001f40: 42a5 cmp r5, r4 __HAL_LOCK(hdma); 8001f42: f880 4020 strb.w r4, [r0, #32] if(HAL_DMA_STATE_READY == hdma->State) 8001f46: d005 beq.n 8001f54 __HAL_UNLOCK(hdma); 8001f48: 2300 movs r3, #0 8001f4a: f880 3020 strb.w r3, [r0, #32] } 8001f4e: bcf0 pop {r4, r5, r6, r7} status = HAL_BUSY; 8001f50: 2002 movs r0, #2 } 8001f52: 4770 bx lr hdma->Instance->CCR &= ~DMA_CCR_EN; 8001f54: 6804 ldr r4, [r0, #0] hdma->State = HAL_DMA_STATE_BUSY; 8001f56: 2702 movs r7, #2 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001f58: 2600 movs r6, #0 hdma->State = HAL_DMA_STATE_BUSY; 8001f5a: f880 7021 strb.w r7, [r0, #33] ; 0x21 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8001f5e: 6386 str r6, [r0, #56] ; 0x38 hdma->Instance->CCR &= ~DMA_CCR_EN; 8001f60: 6826 ldr r6, [r4, #0] hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); 8001f62: 6bc7 ldr r7, [r0, #60] ; 0x3c hdma->Instance->CCR &= ~DMA_CCR_EN; 8001f64: f026 0c01 bic.w ip, r6, #1 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); 8001f68: 6c06 ldr r6, [r0, #64] ; 0x40 hdma->Instance->CCR &= ~DMA_CCR_EN; 8001f6a: f8c4 c000 str.w ip, [r4] hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); 8001f6e: 40b5 lsls r5, r6 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8001f70: 6846 ldr r6, [r0, #4] hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); 8001f72: 607d str r5, [r7, #4] hdma->Instance->CNDTR = DataLength; 8001f74: 6063 str r3, [r4, #4] if(NULL != hdma->XferHalfCpltCallback ) 8001f76: 6ac3 ldr r3, [r0, #44] ; 0x2c if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8001f78: 2e10 cmp r6, #16 hdma->Instance->CPAR = DstAddress; 8001f7a: bf0b itete eq 8001f7c: 60a2 streq r2, [r4, #8] hdma->Instance->CPAR = SrcAddress; 8001f7e: 60a1 strne r1, [r4, #8] hdma->Instance->CMAR = SrcAddress; 8001f80: 60e1 streq r1, [r4, #12] hdma->Instance->CMAR = DstAddress; 8001f82: 60e2 strne r2, [r4, #12] if(NULL != hdma->XferHalfCpltCallback ) 8001f84: b153 cbz r3, 8001f9c hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); 8001f86: 6823 ldr r3, [r4, #0] 8001f88: f043 030e orr.w r3, r3, #14 8001f8c: 6023 str r3, [r4, #0] hdma->Instance->CCR |= DMA_CCR_EN; 8001f8e: 6823 ldr r3, [r4, #0] 8001f90: f043 0301 orr.w r3, r3, #1 8001f94: 6023 str r3, [r4, #0] HAL_StatusTypeDef status = HAL_OK; 8001f96: 2000 movs r0, #0 } 8001f98: bcf0 pop {r4, r5, r6, r7} 8001f9a: 4770 bx lr hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); 8001f9c: 6823 ldr r3, [r4, #0] 8001f9e: f043 030a orr.w r3, r3, #10 8001fa2: 6023 str r3, [r4, #0] hdma->Instance->CCR &= ~DMA_IT_HT; 8001fa4: 6823 ldr r3, [r4, #0] 8001fa6: f023 0304 bic.w r3, r3, #4 8001faa: 6023 str r3, [r4, #0] 8001fac: e7ef b.n 8001f8e __HAL_LOCK(hdma); 8001fae: 2002 movs r0, #2 } 8001fb0: bcf0 pop {r4, r5, r6, r7} 8001fb2: 4770 bx lr 08001fb4 : { 8001fb4: b470 push {r4, r5, r6} if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) 8001fb6: e9d0 620f ldrd r6, r2, [r0, #60] ; 0x3c 8001fba: 2304 movs r3, #4 uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8001fbc: 6831 ldr r1, [r6, #0] uint32_t source_it = hdma->Instance->CCR; 8001fbe: 6804 ldr r4, [r0, #0] if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) 8001fc0: 4093 lsls r3, r2 8001fc2: 420b tst r3, r1 uint32_t source_it = hdma->Instance->CCR; 8001fc4: 6825 ldr r5, [r4, #0] if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) 8001fc6: d00e beq.n 8001fe6 8001fc8: f015 0f04 tst.w r5, #4 8001fcc: d00b beq.n 8001fe6 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8001fce: 6822 ldr r2, [r4, #0] 8001fd0: 0692 lsls r2, r2, #26 8001fd2: d403 bmi.n 8001fdc hdma->Instance->CCR &= ~DMA_IT_HT; 8001fd4: 6822 ldr r2, [r4, #0] 8001fd6: f022 0204 bic.w r2, r2, #4 8001fda: 6022 str r2, [r4, #0] if(hdma->XferHalfCpltCallback != NULL) 8001fdc: 6ac2 ldr r2, [r0, #44] ; 0x2c hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; 8001fde: 6073 str r3, [r6, #4] if(hdma->XferHalfCpltCallback != NULL) 8001fe0: b1ca cbz r2, 8002016 } 8001fe2: bc70 pop {r4, r5, r6} hdma->XferCpltCallback(hdma); 8001fe4: 4710 bx r2 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) 8001fe6: 2302 movs r3, #2 8001fe8: 4093 lsls r3, r2 8001fea: 420b tst r3, r1 8001fec: d015 beq.n 800201a 8001fee: f015 0f02 tst.w r5, #2 8001ff2: d012 beq.n 800201a if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8001ff4: 6822 ldr r2, [r4, #0] 8001ff6: 0692 lsls r2, r2, #26 8001ff8: d406 bmi.n 8002008 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); 8001ffa: 6822 ldr r2, [r4, #0] hdma->State = HAL_DMA_STATE_READY; 8001ffc: 2101 movs r1, #1 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); 8001ffe: f022 020a bic.w r2, r2, #10 8002002: 6022 str r2, [r4, #0] hdma->State = HAL_DMA_STATE_READY; 8002004: f880 1021 strb.w r1, [r0, #33] ; 0x21 if(hdma->XferCpltCallback != NULL) 8002008: 6a82 ldr r2, [r0, #40] ; 0x28 hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; 800200a: 6073 str r3, [r6, #4] __HAL_UNLOCK(hdma); 800200c: 2300 movs r3, #0 800200e: f880 3020 strb.w r3, [r0, #32] if(hdma->XferCpltCallback != NULL) 8002012: 2a00 cmp r2, #0 8002014: d1e5 bne.n 8001fe2 } 8002016: bc70 pop {r4, r5, r6} 8002018: 4770 bx lr else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) 800201a: 2308 movs r3, #8 800201c: 4093 lsls r3, r2 800201e: 420b tst r3, r1 8002020: d0f9 beq.n 8002016 8002022: 072b lsls r3, r5, #28 8002024: d5f7 bpl.n 8002016 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); 8002026: 6823 ldr r3, [r4, #0] if(hdma->XferErrorCallback != NULL) 8002028: 6b01 ldr r1, [r0, #48] ; 0x30 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); 800202a: f023 030e bic.w r3, r3, #14 800202e: 6023 str r3, [r4, #0] hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; 8002030: 2301 movs r3, #1 8002032: fa03 f202 lsl.w r2, r3, r2 __HAL_UNLOCK(hdma); 8002036: f44f 7480 mov.w r4, #256 ; 0x100 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; 800203a: 6072 str r2, [r6, #4] hdma->ErrorCode = HAL_DMA_ERROR_TE; 800203c: 6383 str r3, [r0, #56] ; 0x38 __HAL_UNLOCK(hdma); 800203e: 8404 strh r4, [r0, #32] if(hdma->XferErrorCallback != NULL) 8002040: 2900 cmp r1, #0 8002042: d0e8 beq.n 8002016 } 8002044: bc70 pop {r4, r5, r6} hdma->XferErrorCallback(hdma); 8002046: 4708 bx r1 08002048 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002048: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800204c: 680d ldr r5, [r1, #0] { 800204e: b083 sub sp, #12 while (((GPIO_Init->Pin) >> position) != 0x00u) 8002050: 2d00 cmp r5, #0 8002052: f000 80c2 beq.w 80021da temp &= ~(0x0FuL << (4u * (position & 0x03u))); temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); SYSCFG->EXTICR[position >> 2u] = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR; 8002056: f8df c1ac ldr.w ip, [pc, #428] ; 8002204 uint32_t position = 0x00u; 800205a: 2300 movs r3, #0 iocurrent = (GPIO_Init->Pin) & (1uL << position); 800205c: f04f 0801 mov.w r8, #1 8002060: e076 b.n 8002150 temp = GPIOx->MODER; 8002062: f8d0 b000 ldr.w fp, [r0] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8002066: ea4f 0943 mov.w r9, r3, lsl #1 800206a: 2603 movs r6, #3 800206c: fa06 f609 lsl.w r6, r6, r9 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8002070: f002 0703 and.w r7, r2, #3 temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8002074: ea2b 0b06 bic.w fp, fp, r6 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8002078: fa07 f709 lsl.w r7, r7, r9 if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 800207c: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8002080: ea47 070b orr.w r7, r7, fp if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 8002084: f1ba 0f01 cmp.w sl, #1 temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8002088: ea6f 0606 mvn.w r6, r6 GPIOx->MODER = temp; 800208c: 6007 str r7, [r0, #0] if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 800208e: f240 8091 bls.w 80021b4 temp = GPIOx->PUPDR; 8002092: 68c7 ldr r7, [r0, #12] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8002094: 688c ldr r4, [r1, #8] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); 8002096: 403e ands r6, r7 temp |= ((GPIO_Init->Pull) << (position * 2u)); 8002098: fa04 f409 lsl.w r4, r4, r9 800209c: 4334 orrs r4, r6 GPIOx->PUPDR = temp; 800209e: 60c4 str r4, [r0, #12] if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 80020a0: 00d4 lsls r4, r2, #3 80020a2: d551 bpl.n 8002148 __HAL_RCC_SYSCFG_CLK_ENABLE(); 80020a4: 4e53 ldr r6, [pc, #332] ; (80021f4 ) 80020a6: 69b4 ldr r4, [r6, #24] 80020a8: f044 0401 orr.w r4, r4, #1 80020ac: 61b4 str r4, [r6, #24] 80020ae: 69b4 ldr r4, [r6, #24] 80020b0: f023 0603 bic.w r6, r3, #3 80020b4: f106 4680 add.w r6, r6, #1073741824 ; 0x40000000 80020b8: f004 0401 and.w r4, r4, #1 80020bc: f506 3680 add.w r6, r6, #65536 ; 0x10000 80020c0: 9401 str r4, [sp, #4] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80020c2: f003 0403 and.w r4, r3, #3 80020c6: ea4f 0a84 mov.w sl, r4, lsl #2 __HAL_RCC_SYSCFG_CLK_ENABLE(); 80020ca: 9f01 ldr r7, [sp, #4] temp = SYSCFG->EXTICR[position >> 2u]; 80020cc: 68b7 ldr r7, [r6, #8] temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80020ce: 240f movs r4, #15 80020d0: fa04 f90a lsl.w r9, r4, sl temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 80020d4: f1b0 4f90 cmp.w r0, #1207959552 ; 0x48000000 temp &= ~(0x0FuL << (4u * (position & 0x03u))); 80020d8: ea27 0709 bic.w r7, r7, r9 temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); 80020dc: d00d beq.n 80020fa 80020de: 4c46 ldr r4, [pc, #280] ; (80021f8 ) 80020e0: 42a0 cmp r0, r4 80020e2: d07d beq.n 80021e0 80020e4: 4c45 ldr r4, [pc, #276] ; (80021fc ) 80020e6: 42a0 cmp r0, r4 80020e8: d07e beq.n 80021e8 80020ea: 4c45 ldr r4, [pc, #276] ; (8002200 ) 80020ec: 42a0 cmp r0, r4 80020ee: bf0c ite eq 80020f0: 2403 moveq r4, #3 80020f2: 2405 movne r4, #5 80020f4: fa04 f40a lsl.w r4, r4, sl 80020f8: 4327 orrs r7, r4 SYSCFG->EXTICR[position >> 2u] = temp; 80020fa: 60b7 str r7, [r6, #8] temp = EXTI->IMR; 80020fc: f8dc 4000 ldr.w r4, [ip] temp &= ~(iocurrent); 8002100: ea6f 060e mvn.w r6, lr if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8002104: 03d7 lsls r7, r2, #15 temp &= ~(iocurrent); 8002106: bf54 ite pl 8002108: 4034 andpl r4, r6 { temp |= iocurrent; 800210a: ea4e 0404 orrmi.w r4, lr, r4 } EXTI->IMR = temp; 800210e: f8cc 4000 str.w r4, [ip] temp = EXTI->EMR; 8002112: f8dc 4004 ldr.w r4, [ip, #4] temp &= ~(iocurrent); if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8002116: 0397 lsls r7, r2, #14 temp &= ~(iocurrent); 8002118: bf54 ite pl 800211a: 4034 andpl r4, r6 { temp |= iocurrent; 800211c: ea4e 0404 orrmi.w r4, lr, r4 } EXTI->EMR = temp; 8002120: f8cc 4004 str.w r4, [ip, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8002124: f8dc 4008 ldr.w r4, [ip, #8] temp &= ~(iocurrent); if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8002128: 02d7 lsls r7, r2, #11 temp &= ~(iocurrent); 800212a: bf54 ite pl 800212c: 4034 andpl r4, r6 { temp |= iocurrent; 800212e: ea4e 0404 orrmi.w r4, lr, r4 } EXTI->RTSR = temp; 8002132: f8cc 4008 str.w r4, [ip, #8] temp = EXTI->FTSR; 8002136: f8dc 400c ldr.w r4, [ip, #12] temp &= ~(iocurrent); if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 800213a: 0292 lsls r2, r2, #10 temp &= ~(iocurrent); 800213c: bf54 ite pl 800213e: 4034 andpl r4, r6 { temp |= iocurrent; 8002140: ea4e 0404 orrmi.w r4, lr, r4 } EXTI->FTSR = temp; 8002144: f8cc 400c str.w r4, [ip, #12] } } position++; 8002148: 3301 adds r3, #1 while (((GPIO_Init->Pin) >> position) != 0x00u) 800214a: fa35 f203 lsrs.w r2, r5, r3 800214e: d044 beq.n 80021da iocurrent = (GPIO_Init->Pin) & (1uL << position); 8002150: fa08 f403 lsl.w r4, r8, r3 if (iocurrent != 0x00u) 8002154: ea14 0e05 ands.w lr, r4, r5 8002158: d0f6 beq.n 8002148 if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 800215a: 684a ldr r2, [r1, #4] 800215c: f022 0a10 bic.w sl, r2, #16 8002160: f1ba 0f02 cmp.w sl, #2 8002164: f47f af7d bne.w 8002062 temp = GPIOx->AFR[position >> 3u]; 8002168: ea4f 09d3 mov.w r9, r3, lsr #3 800216c: eb00 0989 add.w r9, r0, r9, lsl #2 temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8002170: f003 0707 and.w r7, r3, #7 temp = GPIOx->AFR[position >> 3u]; 8002174: f8d9 6020 ldr.w r6, [r9, #32] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8002178: 00bf lsls r7, r7, #2 800217a: f04f 0a0f mov.w sl, #15 800217e: fa0a fb07 lsl.w fp, sl, r7 8002182: ea26 0a0b bic.w sl, r6, fp temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8002186: 690e ldr r6, [r1, #16] 8002188: 40be lsls r6, r7 800218a: ea46 060a orr.w r6, r6, sl GPIOx->AFR[position >> 3u] = temp; 800218e: f8c9 6020 str.w r6, [r9, #32] temp = GPIOx->MODER; 8002192: f8d0 a000 ldr.w sl, [r0] temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 8002196: ea4f 0943 mov.w r9, r3, lsl #1 800219a: 2603 movs r6, #3 800219c: fa06 f609 lsl.w r6, r6, r9 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 80021a0: f002 0703 and.w r7, r2, #3 temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 80021a4: ea2a 0a06 bic.w sl, sl, r6 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 80021a8: fa07 f709 lsl.w r7, r7, r9 80021ac: ea47 070a orr.w r7, r7, sl temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); 80021b0: 43f6 mvns r6, r6 GPIOx->MODER = temp; 80021b2: 6007 str r7, [r0, #0] temp = GPIOx->OSPEEDR; 80021b4: 6887 ldr r7, [r0, #8] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); 80021b6: ea07 0a06 and.w sl, r7, r6 temp |= (GPIO_Init->Speed << (position * 2u)); 80021ba: 68cf ldr r7, [r1, #12] 80021bc: fa07 f709 lsl.w r7, r7, r9 80021c0: ea47 070a orr.w r7, r7, sl GPIOx->OSPEEDR = temp; 80021c4: 6087 str r7, [r0, #8] temp = GPIOx->OTYPER; 80021c6: f8d0 a004 ldr.w sl, [r0, #4] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); 80021ca: f3c2 1700 ubfx r7, r2, #4, #1 temp &= ~(GPIO_OTYPER_OT_0 << position) ; 80021ce: ea2a 0404 bic.w r4, sl, r4 temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); 80021d2: 409f lsls r7, r3 80021d4: 4327 orrs r7, r4 GPIOx->OTYPER = temp; 80021d6: 6047 str r7, [r0, #4] 80021d8: e75b b.n 8002092 } } 80021da: b003 add sp, #12 80021dc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80021e0: fa08 f40a lsl.w r4, r8, sl 80021e4: 4327 orrs r7, r4 80021e6: e788 b.n 80020fa 80021e8: f04f 0902 mov.w r9, #2 80021ec: fa09 f40a lsl.w r4, r9, sl 80021f0: 4327 orrs r7, r4 80021f2: e782 b.n 80020fa 80021f4: 40021000 .word 0x40021000 80021f8: 48000400 .word 0x48000400 80021fc: 48000800 .word 0x48000800 8002200: 48000c00 .word 0x48000c00 8002204: 40010400 .word 0x40010400 08002208 : GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8002208: 6903 ldr r3, [r0, #16] 800220a: 4219 tst r1, r3 else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } 800220c: bf14 ite ne 800220e: 2001 movne r0, #1 8002210: 2000 moveq r0, #0 8002212: 4770 bx lr 08002214 : * @retval An ErrorStatus enumeration value: * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) { 8002214: b470 push {r4, r5, r6} return (READ_BIT(DACx->CR, 8002216: f001 0110 and.w r1, r1, #16 800221a: 6805 ldr r5, [r0, #0] 800221c: 2301 movs r3, #1 800221e: 4604 mov r4, r0 8002220: fa03 f001 lsl.w r0, r3, r1 assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); } /* Note: Hardware constraint (refer to description of this function) */ /* DAC instance must be disabled. */ if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) 8002224: 43a8 bics r0, r5 8002226: d022 beq.n 800226e /* - TriggerSource */ /* - WaveAutoGeneration */ /* - OutputBuffer */ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { MODIFY_REG(DACx->CR, 8002228: e9d2 0300 ldrd r0, r3, [r2] if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) 800222c: b96b cbnz r3, 800224a ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } else { MODIFY_REG(DACx->CR, 800222e: 68d2 ldr r2, [r2, #12] 8002230: 6825 ldr r5, [r4, #0] 8002232: 4302 orrs r2, r0 8002234: 20fa movs r0, #250 ; 0xfa 8002236: 4088 lsls r0, r1 8002238: fa02 f101 lsl.w r1, r2, r1 800223c: ea25 0200 bic.w r2, r5, r0 8002240: 4311 orrs r1, r2 ErrorStatus status = SUCCESS; 8002242: 4618 mov r0, r3 MODIFY_REG(DACx->CR, 8002244: 6021 str r1, [r4, #0] { /* Initialization error: DAC instance is not disabled. */ status = ERROR; } return status; } 8002246: bc70 pop {r4, r5, r6} 8002248: 4770 bx lr MODIFY_REG(DACx->CR, 800224a: e9d2 6502 ldrd r6, r5, [r2, #8] 800224e: 4303 orrs r3, r0 8002250: 6822 ldr r2, [r4, #0] 8002252: 4333 orrs r3, r6 8002254: f640 70fa movw r0, #4090 ; 0xffa 8002258: 432b orrs r3, r5 800225a: 4088 lsls r0, r1 800225c: fa03 f101 lsl.w r1, r3, r1 8002260: ea22 0300 bic.w r3, r2, r0 8002264: 4319 orrs r1, r3 8002266: 6021 str r1, [r4, #0] ErrorStatus status = SUCCESS; 8002268: 2000 movs r0, #0 } 800226a: bc70 pop {r4, r5, r6} 800226c: 4770 bx lr status = ERROR; 800226e: 4618 mov r0, r3 } 8002270: bc70 pop {r4, r5, r6} 8002272: 4770 bx lr 08002274 : * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content * - ERROR: Not applicable */ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) { 8002274: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); /* ------------------------- Configure the port pins ---------------- */ /* Initialize pinpos on first pin set */ pinpos = POSITION_VAL(GPIO_InitStruct->Pin); 8002278: 680c ldr r4, [r1, #0] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800227a: fa94 f2a4 rbit r2, r4 800227e: fab2 f282 clz r2, r2 /* Configure the port pins */ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) 8002282: fa34 f302 lsrs.w r3, r4, r2 8002286: f000 80a0 beq.w 80023ca 800228a: 684f ldr r7, [r1, #4] { /* Get current io position */ currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); 800228c: f04f 0c01 mov.w ip, #1 8002290: f107 3eff add.w lr, r7, #4294967295 ; 0xffffffff * @arg @ref LL_GPIO_MODE_ANALOG * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); 8002294: 2603 movs r6, #3 * @arg @ref LL_GPIO_AF_15 * @retval None */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), 8002296: f04f 080f mov.w r8, #15 800229a: e003 b.n 80022a4 { LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } } pinpos++; 800229c: 3201 adds r2, #1 while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) 800229e: fa34 f302 lsrs.w r3, r4, r2 80022a2: d06e beq.n 8002382 currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); 80022a4: fa0c f302 lsl.w r3, ip, r2 if (currentpin != 0x00u) 80022a8: 4023 ands r3, r4 80022aa: d0f7 beq.n 800229c MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); 80022ac: f8d0 9000 ldr.w r9, [r0] 80022b0: fa93 faa3 rbit sl, r3 80022b4: faba fa8a clz sl, sl 80022b8: fa93 f5a3 rbit r5, r3 80022bc: fab5 f585 clz r5, r5 80022c0: ea4f 0a4a mov.w sl, sl, lsl #1 80022c4: 006d lsls r5, r5, #1 80022c6: fa06 fa0a lsl.w sl, r6, sl 80022ca: fa07 f505 lsl.w r5, r7, r5 80022ce: ea29 090a bic.w r9, r9, sl 80022d2: ea49 0505 orr.w r5, r9, r5 if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) 80022d6: f1be 0f01 cmp.w lr, #1 80022da: 6005 str r5, [r0, #0] 80022dc: d816 bhi.n 800230c MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), 80022de: 6885 ldr r5, [r0, #8] 80022e0: fa93 f9a3 rbit r9, r3 80022e4: fab9 f989 clz r9, r9 80022e8: fa93 faa3 rbit sl, r3 80022ec: ea4f 0949 mov.w r9, r9, lsl #1 80022f0: fa06 f909 lsl.w r9, r6, r9 80022f4: ea25 0909 bic.w r9, r5, r9 80022f8: faba fa8a clz sl, sl 80022fc: 688d ldr r5, [r1, #8] 80022fe: ea4f 0a4a mov.w sl, sl, lsl #1 8002302: fa05 f50a lsl.w r5, r5, sl 8002306: ea49 0505 orr.w r5, r9, r5 800230a: 6085 str r5, [r0, #8] MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); 800230c: 68c5 ldr r5, [r0, #12] 800230e: fa93 f9a3 rbit r9, r3 8002312: fab9 f989 clz r9, r9 8002316: fa93 faa3 rbit sl, r3 800231a: ea4f 0949 mov.w r9, r9, lsl #1 800231e: fa06 f909 lsl.w r9, r6, r9 8002322: ea25 0909 bic.w r9, r5, r9 8002326: faba fa8a clz sl, sl 800232a: 690d ldr r5, [r1, #16] 800232c: ea4f 0a4a mov.w sl, sl, lsl #1 8002330: fa05 f50a lsl.w r5, r5, sl 8002334: ea49 0505 orr.w r5, r9, r5 if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) 8002338: 2f02 cmp r7, #2 800233a: 60c5 str r5, [r0, #12] 800233c: d1ae bne.n 800229c 800233e: fa93 f9a3 rbit r9, r3 if (POSITION_VAL(currentpin) < 0x00000008U) 8002342: fab9 f989 clz r9, r9 8002346: f1b9 0f07 cmp.w r9, #7 MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), 800234a: ea4f 2513 mov.w r5, r3, lsr #8 800234e: dc26 bgt.n 800239e MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)), 8002350: 6a05 ldr r5, [r0, #32] 8002352: fa93 faa3 rbit sl, r3 8002356: faba fa8a clz sl, sl 800235a: fa93 f3a3 rbit r3, r3 800235e: ea4f 0a8a mov.w sl, sl, lsl #2 8002362: fa08 fa0a lsl.w sl, r8, sl 8002366: ea25 090a bic.w r9, r5, sl 800236a: fab3 f383 clz r3, r3 800236e: 694d ldr r5, [r1, #20] 8002370: 009b lsls r3, r3, #2 8002372: 409d lsls r5, r3 pinpos++; 8002374: 3201 adds r2, #1 8002376: ea49 0505 orr.w r5, r9, r5 while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) 800237a: fa34 f302 lsrs.w r3, r4, r2 800237e: 6205 str r5, [r0, #32] 8002380: d190 bne.n 80022a4 } if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) 8002382: f1be 0f01 cmp.w lr, #1 8002386: d807 bhi.n 8002398 MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); 8002388: 68ca ldr r2, [r1, #12] 800238a: 6843 ldr r3, [r0, #4] 800238c: fb02 f204 mul.w r2, r2, r4 8002390: ea23 0404 bic.w r4, r3, r4 8002394: 4314 orrs r4, r2 8002396: 6044 str r4, [r0, #4] /* Output mode configuration*/ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); } return (SUCCESS); } 8002398: 2000 movs r0, #0 800239a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), 800239e: 6a43 ldr r3, [r0, #36] ; 0x24 80023a0: fa95 faa5 rbit sl, r5 80023a4: faba fa8a clz sl, sl 80023a8: fa95 f5a5 rbit r5, r5 80023ac: ea4f 0a8a mov.w sl, sl, lsl #2 80023b0: fa08 fa0a lsl.w sl, r8, sl 80023b4: ea23 090a bic.w r9, r3, sl 80023b8: fab5 f585 clz r5, r5 80023bc: 694b ldr r3, [r1, #20] 80023be: 00ad lsls r5, r5, #2 80023c0: 40ab lsls r3, r5 80023c2: ea49 0303 orr.w r3, r9, r3 80023c6: 6243 str r3, [r0, #36] ; 0x24 (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); } 80023c8: e768 b.n 800229c 80023ca: 684b ldr r3, [r1, #4] 80023cc: f103 3eff add.w lr, r3, #4294967295 ; 0xffffffff 80023d0: e7d7 b.n 8002382 80023d2: bf00 nop 080023d4 : assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80023d4: 4a22 ldr r2, [pc, #136] ; (8002460 ) tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); 80023d6: 6803 ldr r3, [r0, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80023d8: 4290 cmp r0, r2 { 80023da: b430 push {r4, r5} if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80023dc: d038 beq.n 8002450 80023de: f1b0 4f80 cmp.w r0, #1073741824 ; 0x40000000 80023e2: d015 beq.n 8002410 80023e4: f5a2 3294 sub.w r2, r2, #75776 ; 0x12800 80023e8: 4290 cmp r0, r2 80023ea: d011 beq.n 8002410 { /* Select the Counter Mode */ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80023ec: f502 329e add.w r2, r2, #80896 ; 0x13c00 80023f0: 4290 cmp r0, r2 80023f2: d021 beq.n 8002438 80023f4: f502 6280 add.w r2, r2, #1024 ; 0x400 80023f8: 4290 cmp r0, r2 80023fa: d01d beq.n 8002438 80023fc: f502 6280 add.w r2, r2, #1024 ; 0x400 8002400: 4290 cmp r0, r2 8002402: d019 beq.n 8002438 /* Write to TIMx CR1 */ LL_TIM_WriteReg(TIMx, CR1, tmpcr1); /* Set the Autoreload value */ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); 8002404: 688c ldr r4, [r1, #8] /* Set the Prescaler value */ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); 8002406: 880a ldrh r2, [r1, #0] LL_TIM_WriteReg(TIMx, CR1, tmpcr1); 8002408: 6003 str r3, [r0, #0] WRITE_REG(TIMx->ARR, AutoReload); 800240a: 62c4 str r4, [r0, #44] ; 0x2c WRITE_REG(TIMx->PSC, Prescaler); 800240c: 6282 str r2, [r0, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800240e: e00c b.n 800242a MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); 8002410: 684a ldr r2, [r1, #4] LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); 8002412: e9d1 4502 ldrd r4, r5, [r1, #8] MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); 8002416: f023 0370 bic.w r3, r3, #112 ; 0x70 800241a: 4313 orrs r3, r2 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); 800241c: f423 7340 bic.w r3, r3, #768 ; 0x300 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); 8002420: 880a ldrh r2, [r1, #0] MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); 8002422: 432b orrs r3, r5 LL_TIM_WriteReg(TIMx, CR1, tmpcr1); 8002424: 6003 str r3, [r0, #0] WRITE_REG(TIMx->ARR, AutoReload); 8002426: 62c4 str r4, [r0, #44] ; 0x2c WRITE_REG(TIMx->PSC, Prescaler); 8002428: 6282 str r2, [r0, #40] ; 0x28 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_UG); 800242a: 6943 ldr r3, [r0, #20] 800242c: f043 0301 orr.w r3, r3, #1 8002430: 6143 str r3, [r0, #20] /* Generate an update event to reload the Prescaler and the repetition counter value (if applicable) immediately */ LL_TIM_GenerateEvent_UPDATE(TIMx); return SUCCESS; } 8002432: bc30 pop {r4, r5} 8002434: 2000 movs r0, #0 8002436: 4770 bx lr MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); 8002438: 68cc ldr r4, [r1, #12] LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); 800243a: 880a ldrh r2, [r1, #0] MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); 800243c: f423 7340 bic.w r3, r3, #768 ; 0x300 8002440: 4323 orrs r3, r4 LL_TIM_WriteReg(TIMx, CR1, tmpcr1); 8002442: 6003 str r3, [r0, #0] LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); 8002444: 688b ldr r3, [r1, #8] WRITE_REG(TIMx->ARR, AutoReload); 8002446: 62c3 str r3, [r0, #44] ; 0x2c WRITE_REG(TIMx->PSC, Prescaler); 8002448: 6282 str r2, [r0, #40] ; 0x28 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); 800244a: 7c0b ldrb r3, [r1, #16] WRITE_REG(TIMx->RCR, RepetitionCounter); 800244c: 6303 str r3, [r0, #48] ; 0x30 } 800244e: e7ec b.n 800242a MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); 8002450: 684d ldr r5, [r1, #4] MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); 8002452: 68cc ldr r4, [r1, #12] LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); 8002454: 880a ldrh r2, [r1, #0] MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); 8002456: f023 0370 bic.w r3, r3, #112 ; 0x70 800245a: 432b orrs r3, r5 800245c: e7ee b.n 800243c 800245e: bf00 nop 8002460: 40012c00 .word 0x40012c00 08002464 : * @retval None */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) { /* HCLK clock frequency */ SystemCoreClock = HCLKFrequency; 8002464: 4b01 ldr r3, [pc, #4] ; (800246c ) 8002466: 6018 str r0, [r3, #0] } 8002468: 4770 bx lr 800246a: bf00 nop 800246c: 20000800 .word 0x20000800 08002470 <__libc_init_array>: 8002470: b570 push {r4, r5, r6, lr} 8002472: 4d0d ldr r5, [pc, #52] ; (80024a8 <__libc_init_array+0x38>) 8002474: 4c0d ldr r4, [pc, #52] ; (80024ac <__libc_init_array+0x3c>) 8002476: 1b64 subs r4, r4, r5 8002478: 10a4 asrs r4, r4, #2 800247a: 2600 movs r6, #0 800247c: 42a6 cmp r6, r4 800247e: d109 bne.n 8002494 <__libc_init_array+0x24> 8002480: 4d0b ldr r5, [pc, #44] ; (80024b0 <__libc_init_array+0x40>) 8002482: 4c0c ldr r4, [pc, #48] ; (80024b4 <__libc_init_array+0x44>) 8002484: f000 f818 bl 80024b8 <_init> 8002488: 1b64 subs r4, r4, r5 800248a: 10a4 asrs r4, r4, #2 800248c: 2600 movs r6, #0 800248e: 42a6 cmp r6, r4 8002490: d105 bne.n 800249e <__libc_init_array+0x2e> 8002492: bd70 pop {r4, r5, r6, pc} 8002494: f855 3b04 ldr.w r3, [r5], #4 8002498: 4798 blx r3 800249a: 3601 adds r6, #1 800249c: e7ee b.n 800247c <__libc_init_array+0xc> 800249e: f855 3b04 ldr.w r3, [r5], #4 80024a2: 4798 blx r3 80024a4: 3601 adds r6, #1 80024a6: e7f2 b.n 800248e <__libc_init_array+0x1e> 80024a8: 08002cd0 .word 0x08002cd0 80024ac: 08002cd0 .word 0x08002cd0 80024b0: 08002cd0 .word 0x08002cd0 80024b4: 08002cd4 .word 0x08002cd4 080024b8 <_init>: 80024b8: b5f8 push {r3, r4, r5, r6, r7, lr} 80024ba: bf00 nop 80024bc: bcf8 pop {r3, r4, r5, r6, r7} 80024be: bc08 pop {r3} 80024c0: 469e mov lr, r3 80024c2: 4770 bx lr 080024c4 <_fini>: 80024c4: b5f8 push {r3, r4, r5, r6, r7, lr} 80024c6: bf00 nop 80024c8: bcf8 pop {r3, r4, r5, r6, r7} 80024ca: bc08 pop {r3} 80024cc: 469e mov lr, r3 80024ce: 4770 bx lr ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/2op_main.d ================================================ Core/Src/2op_main.o: ../Core/Src/2op_main.c ../Core/Inc/2op_main.h \ ../Core/Inc/main.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/big_sine_wave.h ../Core/Inc/dac.h \ ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h \ ../Core/Inc/big_expo.h ../Core/Inc/2op_main.h: ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ../Core/Inc/big_expo.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/2op_main.su ================================================ 2op_main.c:48:6:adsr_structinit 4 static 2op_main.c:62:6:run_adsr 8 static 2op_main.c:106:6:run_ar 8 static 2op_main.c:143:6:run_linear_a_expo_r 8 static 2op_main.c:182:10:operator_run 0 static 2op_main.c:188:6:operator_structinit 0 static 2op_main.c:195:6:check_gate 8 static 2op_main.c:224:6:check_trig 16 static 2op_main.c:251:6:set_adsr_parameters 4 static 2op_main.c:270:6:slow_2op_parameter_loop 16 static 2op_main.c:279:6:main_2OP_loop 24 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/dac.d ================================================ Core/Src/dac.o: ../Core/Src/dac.c ../Core/Inc/dac.h ../Core/Inc/main.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/big_sine_wave.h ../Core/Inc/dac.h \ ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h ../Core/Inc/main.h ../Core/Inc/dac.h: ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ../Core/Inc/main.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/dac.su ================================================ dac.c:12:13:dac2_ch1 0 static,ignoring_inline_asm dac.c:16:13:dac1_ch1 0 static,ignoring_inline_asm ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/dynamic_smooth.d ================================================ Core/Src/dynamic_smooth.o: ../Core/Src/dynamic_smooth.c \ ../Core/Inc/dynamic_smooth.h ../Core/Inc/main.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/big_sine_wave.h ../Core/Inc/dac.h \ ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h ../Core/Inc/dynamic_smooth.h: ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/dynamic_smooth.su ================================================ dynamic_smooth.c:11:7:cm_min 0 static dynamic_smooth.c:15:7:cm_abs 0 static dynamic_smooth.c:23:6:dynamic_smooth_init 0 static dynamic_smooth.c:44:7:dynamic_smooth_tick 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/loop.d ================================================ Core/Src/loop.o: ../Core/Src/loop.c ../Core/Inc/loop.h ../Core/Inc/main.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/main.h ../Core/Inc/big_sine_wave.h \ ../Core/Inc/dac.h ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h ../Core/Inc/loop.h: ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/main.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/loop.su ================================================ loop.c:11:6:loop 16 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/main.d ================================================ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/main.h ../Core/Inc/big_sine_wave.h \ ../Core/Inc/dac.h ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/main.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/main.su ================================================ main.c:116:6:SystemClock_Config 8 static main.c:63:5:main 96 static,ignoring_inline_asm main.c:572:6:Error_Handler 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/noise.d ================================================ Core/Src/noise.o: ../Core/Src/noise.c ../Core/Inc/noise.h \ ../Core/Inc/main.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/big_sine_wave.h ../Core/Inc/dac.h \ ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h ../Core/Inc/main.h ../Core/Inc/noise.h: ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ../Core/Inc/main.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/noise.su ================================================ noise.c:14:10:noise 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/soft_adsr.su ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/stm32f3xx_hal_msp.d ================================================ Core/Src/stm32f3xx_hal_msp.o: ../Core/Src/stm32f3xx_hal_msp.c \ ../Core/Inc/main.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/main.h ../Core/Inc/big_sine_wave.h \ ../Core/Inc/dac.h ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/main.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/stm32f3xx_hal_msp.su ================================================ stm32f3xx_hal_msp.c:67:6:HAL_MspInit 8 static stm32f3xx_hal_msp.c:91:6:HAL_ADC_MspInit 64 static stm32f3xx_hal_msp.c:196:6:HAL_ADC_MspDeInit 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/stm32f3xx_it.d ================================================ Core/Src/stm32f3xx_it.o: ../Core/Src/stm32f3xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Core/Inc/pin_map.h ../Core/Inc/loop.h ../Core/Inc/global_variables.h \ ../Core/Inc/noise.h ../Core/Inc/main.h ../Core/Inc/big_sine_wave.h \ ../Core/Inc/dac.h ../Core/Inc/dynamic_smooth.h ../Core/Inc/2op_main.h \ ../Core/Inc/stm32f3xx_it.h ../Core/Inc/main.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Core/Inc/pin_map.h: ../Core/Inc/loop.h: ../Core/Inc/global_variables.h: ../Core/Inc/noise.h: ../Core/Inc/main.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/dac.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/2op_main.h: ../Core/Inc/stm32f3xx_it.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/stm32f3xx_it.su ================================================ stm32f3xx_it.c:71:6:NMI_Handler 0 static stm32f3xx_it.c:84:6:HardFault_Handler 0 static stm32f3xx_it.c:99:6:MemManage_Handler 0 static stm32f3xx_it.c:114:6:BusFault_Handler 0 static stm32f3xx_it.c:129:6:UsageFault_Handler 0 static stm32f3xx_it.c:144:6:SVC_Handler 0 static stm32f3xx_it.c:157:6:DebugMon_Handler 0 static stm32f3xx_it.c:170:6:PendSV_Handler 0 static stm32f3xx_it.c:183:6:SysTick_Handler 0 static stm32f3xx_it.c:205:6:DMA1_Channel1_IRQHandler 0 static stm32f3xx_it.c:219:6:DMA1_Channel2_IRQHandler 0 static stm32f3xx_it.c:233:6:TIM1_UP_TIM16_IRQHandler 0 static stm32f3xx_it.c:249:6:TIM2_IRQHandler 0 static stm32f3xx_it.c:267:6:TIM3_IRQHandler 16 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../Core/Src/2op_main.c \ ../Core/Src/dac.c \ ../Core/Src/dynamic_smooth.c \ ../Core/Src/loop.c \ ../Core/Src/main.c \ ../Core/Src/noise.c \ ../Core/Src/stm32f3xx_hal_msp.c \ ../Core/Src/stm32f3xx_it.c \ ../Core/Src/syscalls.c \ ../Core/Src/sysmem.c \ ../Core/Src/system_stm32f3xx.c OBJS += \ ./Core/Src/2op_main.o \ ./Core/Src/dac.o \ ./Core/Src/dynamic_smooth.o \ ./Core/Src/loop.o \ ./Core/Src/main.o \ ./Core/Src/noise.o \ ./Core/Src/stm32f3xx_hal_msp.o \ ./Core/Src/stm32f3xx_it.o \ ./Core/Src/syscalls.o \ ./Core/Src/sysmem.o \ ./Core/Src/system_stm32f3xx.o C_DEPS += \ ./Core/Src/2op_main.d \ ./Core/Src/dac.d \ ./Core/Src/dynamic_smooth.d \ ./Core/Src/loop.d \ ./Core/Src/main.d \ ./Core/Src/noise.d \ ./Core/Src/stm32f3xx_hal_msp.d \ ./Core/Src/stm32f3xx_it.d \ ./Core/Src/syscalls.d \ ./Core/Src/sysmem.d \ ./Core/Src/system_stm32f3xx.d # Each subdirectory must supply rules for building sources it contributes Core/Src/%.o: ../Core/Src/%.c Core/Src/subdir.mk arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F334x8 -DUSE_FULL_LL_DRIVER -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/STM32F3xx_HAL_Driver/Inc -I../Core/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F3xx/Include -Ofast -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Core-2f-Src clean-Core-2f-Src: -$(RM) ./Core/Src/2op_main.d ./Core/Src/2op_main.o ./Core/Src/dac.d ./Core/Src/dac.o ./Core/Src/dynamic_smooth.d ./Core/Src/dynamic_smooth.o ./Core/Src/loop.d ./Core/Src/loop.o ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/noise.d ./Core/Src/noise.o ./Core/Src/stm32f3xx_hal_msp.d ./Core/Src/stm32f3xx_hal_msp.o ./Core/Src/stm32f3xx_it.d ./Core/Src/stm32f3xx_it.o ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/system_stm32f3xx.d ./Core/Src/system_stm32f3xx.o .PHONY: clean-Core-2f-Src ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/syscalls.d ================================================ Core/Src/syscalls.o: ../Core/Src/syscalls.c ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/syscalls.su ================================================ syscalls.c:73:6:initialise_monitor_handles 0 static syscalls.c:77:5:_getpid 0 static syscalls.c:82:5:_kill 8 static syscalls.c:88:6:_exit 8 static syscalls.c:94:27:_read 16 static syscalls.c:106:27:_write 16 static syscalls.c:117:5:_close 0 static syscalls.c:123:5:_fstat 0 static syscalls.c:129:5:_isatty 0 static syscalls.c:134:5:_lseek 0 static syscalls.c:139:5:_open 0 static syscalls.c:145:5:_wait 8 static syscalls.c:151:5:_unlink 8 static syscalls.c:157:5:_times 0 static syscalls.c:162:5:_stat 0 static syscalls.c:168:5:_link 8 static syscalls.c:174:5:_fork 8 static syscalls.c:180:5:_execve 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/sysmem.d ================================================ Core/Src/sysmem.o: ../Core/Src/sysmem.c ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/sysmem.su ================================================ sysmem.c:63:9:_sbrk 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/system_stm32f3xx.d ================================================ Core/Src/system_stm32f3xx.o: ../Core/Src/system_stm32f3xx.c \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Src/system_stm32f3xx.su ================================================ system_stm32f3xx.c:151:6:SystemInit 0 static system_stm32f3xx.c:201:6:SystemCoreClockUpdate 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Startup/startup_stm32f334k8tx.d ================================================ Core/Startup/startup_stm32f334k8tx.o: \ ../Core/Startup/startup_stm32f334k8tx.s ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Core/Startup/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables S_SRCS += \ ../Core/Startup/startup_stm32f334k8tx.s OBJS += \ ./Core/Startup/startup_stm32f334k8tx.o S_DEPS += \ ./Core/Startup/startup_stm32f334k8tx.d # Each subdirectory must supply rules for building sources it contributes Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" clean: clean-Core-2f-Startup clean-Core-2f-Startup: -$(RM) ./Core/Startup/startup_stm32f334k8tx.d ./Core/Startup/startup_stm32f334k8tx.o .PHONY: clean-Core-2f-Startup ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.su ================================================ stm32f3xx_hal.c:186:13:HAL_MspInit 0 static stm32f3xx_hal.c:197:13:HAL_MspDeInit 0 static stm32f3xx_hal.c:163:19:HAL_DeInit 8 static stm32f3xx_hal.c:220:26:HAL_InitTick 16 static stm32f3xx_hal.c:138:19:HAL_Init 8 static stm32f3xx_hal.c:278:13:HAL_IncTick 0 static stm32f3xx_hal.c:289:17:HAL_GetTick 0 static stm32f3xx_hal.c:298:10:HAL_GetTickPrio 0 static stm32f3xx_hal.c:307:19:HAL_SetTickFreq 16 static stm32f3xx_hal.c:339:21:HAL_GetTickFreq 0 static stm32f3xx_hal.c:355:13:HAL_Delay 16 static stm32f3xx_hal.c:381:13:HAL_SuspendTick 0 static stm32f3xx_hal.c:399:13:HAL_ResumeTick 0 static stm32f3xx_hal.c:410:10:HAL_GetHalVersion 0 static stm32f3xx_hal.c:419:10:HAL_GetREVID 0 static stm32f3xx_hal.c:428:10:HAL_GetDEVID 0 static stm32f3xx_hal.c:437:10:HAL_GetUIDw0 0 static stm32f3xx_hal.c:446:10:HAL_GetUIDw1 0 static stm32f3xx_hal.c:455:10:HAL_GetUIDw2 0 static stm32f3xx_hal.c:464:6:HAL_DBGMCU_EnableDBGSleepMode 0 static stm32f3xx_hal.c:473:6:HAL_DBGMCU_DisableDBGSleepMode 0 static stm32f3xx_hal.c:482:6:HAL_DBGMCU_EnableDBGStopMode 0 static stm32f3xx_hal.c:491:6:HAL_DBGMCU_DisableDBGStopMode 0 static stm32f3xx_hal.c:500:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static stm32f3xx_hal.c:509:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.su ================================================ stm32f3xx_hal_adc.c:469:26:HAL_ADC_Init 0 static stm32f3xx_hal_adc.c:500:26:HAL_ADC_DeInit 0 static stm32f3xx_hal_adc.c:517:13:HAL_ADC_MspInit 0 static stm32f3xx_hal_adc.c:532:13:HAL_ADC_MspDeInit 0 static stm32f3xx_hal_adc.c:782:26:HAL_ADC_Start 0 static stm32f3xx_hal_adc.c:805:26:HAL_ADC_Stop 0 static stm32f3xx_hal_adc.c:823:26:HAL_ADC_PollForConversion 0 static stm32f3xx_hal_adc.c:849:26:HAL_ADC_PollForEvent 0 static stm32f3xx_hal_adc.c:878:26:HAL_ADC_Start_IT 0 static stm32f3xx_hal_adc.c:905:26:HAL_ADC_Stop_IT 0 static stm32f3xx_hal_adc.c:933:26:HAL_ADC_Start_DMA 0 static stm32f3xx_hal_adc.c:960:26:HAL_ADC_Stop_DMA 0 static stm32f3xx_hal_adc.c:981:17:HAL_ADC_GetValue 0 static stm32f3xx_hal_adc.c:995:13:HAL_ADC_IRQHandler 0 static stm32f3xx_hal_adc.c:1009:13:HAL_ADC_ConvCpltCallback 0 static stm32f3xx_hal_adc.c:1024:13:HAL_ADC_ConvHalfCpltCallback 0 static stm32f3xx_hal_adc.c:1039:13:HAL_ADC_LevelOutOfWindowCallback 0 static stm32f3xx_hal_adc.c:1055:13:HAL_ADC_ErrorCallback 0 static stm32f3xx_hal_adc.c:1107:26:HAL_ADC_ConfigChannel 0 static stm32f3xx_hal_adc.c:1134:26:HAL_ADC_AnalogWDGConfig 0 static stm32f3xx_hal_adc.c:1178:10:HAL_ADC_GetState 0 static stm32f3xx_hal_adc.c:1192:10:HAL_ADC_GetError 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.su ================================================ stm32f3xx_hal_adc_ex.c:7332:26:ADC_ConversionStop 16 static stm32f3xx_hal_adc_ex.c:7189:13:ADC_DMAError 0 static stm32f3xx_hal_adc_ex.c:7171:13:ADC_DMAHalfConvCplt 0 static stm32f3xx_hal_adc_ex.c:7124:13:ADC_DMAConvCplt 0 static stm32f3xx_hal_adc_ex.c:7273:26:ADC_Disable 16 static stm32f3xx_hal_adc_ex.c:7219:26:ADC_Enable 16 static stm32f3xx_hal_adc_ex.c:234:19:HAL_ADC_Init 24 static stm32f3xx_hal_adc_ex.c:807:19:HAL_ADC_DeInit 16 static stm32f3xx_hal_adc_ex.c:1242:19:HAL_ADC_Start 16 static stm32f3xx_hal_adc_ex.c:1448:19:HAL_ADC_Stop 8 static stm32f3xx_hal_adc_ex.c:1553:19:HAL_ADC_PollForConversion 24 static stm32f3xx_hal_adc_ex.c:1856:19:HAL_ADC_PollForEvent 24 static stm32f3xx_hal_adc_ex.c:2034:19:HAL_ADC_Start_IT 16 static stm32f3xx_hal_adc_ex.c:2271:19:HAL_ADC_Stop_IT 8 static stm32f3xx_hal_adc_ex.c:2377:19:HAL_ADC_Start_DMA 32 static stm32f3xx_hal_adc_ex.c:2648:19:HAL_ADC_Stop_DMA 16 static stm32f3xx_hal_adc_ex.c:2798:10:HAL_ADC_GetValue 0 static stm32f3xx_hal_adc_ex.c:3311:19:HAL_ADCEx_Calibration_Start 24 static stm32f3xx_hal_adc_ex.c:3500:10:HAL_ADCEx_Calibration_GetValue 0 static stm32f3xx_hal_adc_ex.c:3535:19:HAL_ADCEx_Calibration_SetValue 4 static stm32f3xx_hal_adc_ex.c:3600:19:HAL_ADCEx_InjectedStart 16 static stm32f3xx_hal_adc_ex.c:3788:19:HAL_ADCEx_InjectedStop 8 static stm32f3xx_hal_adc_ex.c:3931:19:HAL_ADCEx_InjectedPollForConversion 24 static stm32f3xx_hal_adc_ex.c:4158:19:HAL_ADCEx_InjectedStart_IT 16 static stm32f3xx_hal_adc_ex.c:4378:19:HAL_ADCEx_InjectedStop_IT 8 static stm32f3xx_hal_adc_ex.c:4538:19:HAL_ADCEx_MultiModeStart_DMA 104 static stm32f3xx_hal_adc_ex.c:4678:19:HAL_ADCEx_MultiModeStop_DMA 96 static stm32f3xx_hal_adc_ex.c:4798:10:HAL_ADCEx_MultiModeGetValue 0 static stm32f3xx_hal_adc_ex.c:4849:10:HAL_ADCEx_InjectedGetValue 0 static stm32f3xx_hal_adc_ex.c:4963:19:HAL_ADCEx_RegularStop 8 static stm32f3xx_hal_adc_ex.c:5037:19:HAL_ADCEx_RegularStop_IT 8 static stm32f3xx_hal_adc_ex.c:5117:19:HAL_ADCEx_RegularStop_DMA 16 static stm32f3xx_hal_adc_ex.c:5229:19:HAL_ADCEx_RegularMultiModeStop_DMA 96 static stm32f3xx_hal_adc_ex.c:5374:13:HAL_ADCEx_InjectedConvCpltCallback 0 static stm32f3xx_hal_adc_ex.c:5397:13:HAL_ADCEx_InjectedQueueOverflowCallback 0 static stm32f3xx_hal_adc_ex.c:5413:13:HAL_ADCEx_LevelOutOfWindow2Callback 0 static stm32f3xx_hal_adc_ex.c:5428:13:HAL_ADCEx_LevelOutOfWindow3Callback 0 static stm32f3xx_hal_adc_ex.c:2856:6:HAL_ADC_IRQHandler 8 static stm32f3xx_hal_adc_ex.c:5491:19:HAL_ADC_ConfigChannel 24 static stm32f3xx_hal_adc_ex.c:5957:19:HAL_ADCEx_InjectedConfigChannel 32 static stm32f3xx_hal_adc_ex.c:6709:19:HAL_ADC_AnalogWDGConfig 16 static stm32f3xx_hal_adc_ex.c:6994:19:HAL_ADCEx_MultiModeConfigChannel 16 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.su ================================================ stm32f3xx_hal_cortex.c:169:6:HAL_NVIC_SetPriorityGrouping 4 static stm32f3xx_hal_cortex.c:191:6:HAL_NVIC_SetPriority 8 static stm32f3xx_hal_cortex.c:213:6:HAL_NVIC_EnableIRQ 0 static stm32f3xx_hal_cortex.c:229:6:HAL_NVIC_DisableIRQ 0 static,ignoring_inline_asm stm32f3xx_hal_cortex.c:242:6:HAL_NVIC_SystemReset 0 static,ignoring_inline_asm stm32f3xx_hal_cortex.c:255:10:HAL_SYSTICK_Config 4 static stm32f3xx_hal_cortex.c:364:10:HAL_NVIC_GetPriorityGrouping 0 static stm32f3xx_hal_cortex.c:391:6:HAL_NVIC_GetPriority 8 static stm32f3xx_hal_cortex.c:406:6:HAL_NVIC_SetPendingIRQ 0 static stm32f3xx_hal_cortex.c:421:10:HAL_NVIC_GetPendingIRQ 0 static stm32f3xx_hal_cortex.c:434:6:HAL_NVIC_ClearPendingIRQ 0 static stm32f3xx_hal_cortex.c:448:10:HAL_NVIC_GetActive 0 static stm32f3xx_hal_cortex.c:462:6:HAL_SYSTICK_CLKSourceConfig 0 static stm32f3xx_hal_cortex.c:489:13:HAL_SYSTICK_Callback 0 static stm32f3xx_hal_cortex.c:480:6:HAL_SYSTICK_IRQHandler 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.su ================================================ stm32f3xx_hal_dma.c:137:19:HAL_DMA_Init 12 static stm32f3xx_hal_dma.c:199:19:HAL_DMA_DeInit 12 static stm32f3xx_hal_dma.c:281:19:HAL_DMA_Start 20 static stm32f3xx_hal_dma.c:328:19:HAL_DMA_Start_IT 16 static stm32f3xx_hal_dma.c:384:19:HAL_DMA_Abort 8 static stm32f3xx_hal_dma.c:422:19:HAL_DMA_Abort_IT 16 static stm32f3xx_hal_dma.c:468:19:HAL_DMA_PollForTransfer 32 static stm32f3xx_hal_dma.c:569:6:HAL_DMA_IRQHandler 12 static stm32f3xx_hal_dma.c:661:19:HAL_DMA_RegisterCallback 0 static stm32f3xx_hal_dma.c:712:19:HAL_DMA_UnRegisterCallback 0 static stm32f3xx_hal_dma.c:788:22:HAL_DMA_GetState 0 static stm32f3xx_hal_dma.c:799:10:HAL_DMA_GetError 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.su ================================================ stm32f3xx_hal_exti.c:144:19:HAL_EXTI_SetConfigLine 16 static stm32f3xx_hal_exti.c:265:19:HAL_EXTI_GetConfigLine 12 static stm32f3xx_hal_exti.c:368:19:HAL_EXTI_ClearConfigLine 16 static stm32f3xx_hal_exti.c:433:19:HAL_EXTI_RegisterCallback 0 static stm32f3xx_hal_exti.c:458:19:HAL_EXTI_GetHandle 0 static stm32f3xx_hal_exti.c:498:6:HAL_EXTI_IRQHandler 0 static stm32f3xx_hal_exti.c:535:10:HAL_EXTI_GetPending 0 static stm32f3xx_hal_exti.c:569:6:HAL_EXTI_ClearPending 0 static stm32f3xx_hal_exti.c:596:6:HAL_EXTI_GenerateSWI 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.su ================================================ stm32f3xx_hal_flash.c:168:19:HAL_FLASH_Program 40 static stm32f3xx_hal_flash.c:240:19:HAL_FLASH_Program_IT 16 static stm32f3xx_hal_flash.c:429:13:HAL_FLASH_EndOfOperationCallback 0 static stm32f3xx_hal_flash.c:447:13:HAL_FLASH_OperationErrorCallback 0 static stm32f3xx_hal_flash.c:286:6:HAL_FLASH_IRQHandler 24 static stm32f3xx_hal_flash.c:480:19:HAL_FLASH_Unlock 0 static stm32f3xx_hal_flash.c:504:19:HAL_FLASH_Lock 0 static stm32f3xx_hal_flash.c:516:19:HAL_FLASH_OB_Unlock 0 static stm32f3xx_hal_flash.c:536:19:HAL_FLASH_OB_Lock 0 static stm32f3xx_hal_flash.c:549:19:HAL_FLASH_OB_Launch 16 static stm32f3xx_hal_flash.c:581:10:HAL_FLASH_GetError 0 static stm32f3xx_hal_flash.c:621:19:FLASH_WaitForLastOperation 16 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.su ================================================ stm32f3xx_hal_flash_ex.c:159:19:HAL_FLASHEx_Erase 32 static stm32f3xx_hal_flash_ex.c:240:19:HAL_FLASHEx_Erase_IT 8 static stm32f3xx_hal_flash_ex.c:313:19:HAL_FLASHEx_OBErase 16 static stm32f3xx_hal_flash_ex.c:362:19:HAL_FLASHEx_OBProgram 32 static stm32f3xx_hal_flash_ex.c:443:6:HAL_FLASHEx_OBGetConfig 0 static,ignoring_inline_asm stm32f3xx_hal_flash_ex.c:465:10:HAL_FLASHEx_OBGetUserData 0 static,ignoring_inline_asm stm32f3xx_hal_flash_ex.c:959:6:FLASH_PageErase 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.su ================================================ stm32f3xx_hal_gpio.c:179:6:HAL_GPIO_Init 48 static stm32f3xx_hal_gpio.c:304:6:HAL_GPIO_DeInit 48 static stm32f3xx_hal_gpio.c:386:15:HAL_GPIO_ReadPin 0 static stm32f3xx_hal_gpio.c:420:6:HAL_GPIO_WritePin 0 static stm32f3xx_hal_gpio.c:442:6:HAL_GPIO_TogglePin 0 static stm32f3xx_hal_gpio.c:468:19:HAL_GPIO_LockPin 8 static stm32f3xx_hal_gpio.c:518:13:HAL_GPIO_EXTI_Callback 0 static stm32f3xx_hal_gpio.c:503:6:HAL_GPIO_EXTI_IRQHandler 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.su ================================================ stm32f3xx_hal_i2c.c:6181:26:I2C_WaitOnRXNEFlagUntilTimeout 16 static stm32f3xx_hal_i2c.c:6110:26:I2C_WaitOnTXISFlagUntilTimeout 16 static stm32f3xx_hal_i2c.c:6147:26:I2C_WaitOnSTOPFlagUntilTimeout 16 static stm32f3xx_hal_i2c.c:624:13:HAL_I2C_MspInit 0 static stm32f3xx_hal_i2c.c:469:19:HAL_I2C_Init 16 static stm32f3xx_hal_i2c.c:640:13:HAL_I2C_MspDeInit 0 static stm32f3xx_hal_i2c.c:578:19:HAL_I2C_DeInit 8 static stm32f3xx_hal_i2c.c:1060:19:HAL_I2C_Master_Transmit 32 static stm32f3xx_hal_i2c.c:1174:19:HAL_I2C_Master_Receive 32 static stm32f3xx_hal_i2c.c:1287:19:HAL_I2C_Slave_Transmit 24 static stm32f3xx_hal_i2c.c:1424:19:HAL_I2C_Slave_Receive 24 static stm32f3xx_hal_i2c.c:1550:19:HAL_I2C_Master_Transmit_IT 16 static stm32f3xx_hal_i2c.c:1619:19:HAL_I2C_Master_Receive_IT 16 static stm32f3xx_hal_i2c.c:1686:19:HAL_I2C_Slave_Transmit_IT 16 static stm32f3xx_hal_i2c.c:1735:19:HAL_I2C_Slave_Receive_IT 16 static stm32f3xx_hal_i2c.c:1786:19:HAL_I2C_Master_Transmit_DMA 24 static stm32f3xx_hal_i2c.c:1929:19:HAL_I2C_Master_Receive_DMA 24 static stm32f3xx_hal_i2c.c:2070:19:HAL_I2C_Slave_Transmit_DMA 24 static stm32f3xx_hal_i2c.c:2173:19:HAL_I2C_Slave_Receive_DMA 24 static stm32f3xx_hal_i2c.c:2280:19:HAL_I2C_Mem_Write 32 static stm32f3xx_hal_i2c.c:2415:19:HAL_I2C_Mem_Read 32 static stm32f3xx_hal_i2c.c:2548:19:HAL_I2C_Mem_Write_IT 40 static stm32f3xx_hal_i2c.c:2639:19:HAL_I2C_Mem_Read_IT 48 static stm32f3xx_hal_i2c.c:2729:19:HAL_I2C_Mem_Write_DMA 32 static stm32f3xx_hal_i2c.c:2873:19:HAL_I2C_Mem_Read_DMA 32 static stm32f3xx_hal_i2c.c:3014:19:HAL_I2C_IsDeviceReady 40 static stm32f3xx_hal_i2c.c:3156:19:HAL_I2C_Master_Seq_Transmit_IT 16 static stm32f3xx_hal_i2c.c:3240:19:HAL_I2C_Master_Seq_Transmit_DMA 32 static stm32f3xx_hal_i2c.c:3402:19:HAL_I2C_Master_Seq_Receive_IT 16 static stm32f3xx_hal_i2c.c:3486:19:HAL_I2C_Master_Seq_Receive_DMA 32 static stm32f3xx_hal_i2c.c:3646:19:HAL_I2C_Slave_Seq_Transmit_IT 32 static stm32f3xx_hal_i2c.c:3741:19:HAL_I2C_Slave_Seq_Transmit_DMA 40 static stm32f3xx_hal_i2c.c:3920:19:HAL_I2C_Slave_Seq_Receive_IT 32 static stm32f3xx_hal_i2c.c:4015:19:HAL_I2C_Slave_Seq_Receive_DMA 40 static stm32f3xx_hal_i2c.c:4190:19:HAL_I2C_EnableListen_IT 0 static stm32f3xx_hal_i2c.c:4214:19:HAL_I2C_DisableListen_IT 4 static stm32f3xx_hal_i2c.c:4247:19:HAL_I2C_Master_Abort_IT 16 static stm32f3xx_hal_i2c.c:4297:6:HAL_I2C_EV_IRQHandler 0 static stm32f3xx_hal_i2c.c:4365:13:HAL_I2C_MasterTxCpltCallback 0 static stm32f3xx_hal_i2c.c:4381:13:HAL_I2C_MasterRxCpltCallback 0 static stm32f3xx_hal_i2c.c:5317:13:I2C_ITMasterSeqCplt 16 static stm32f3xx_hal_i2c.c:4396:13:HAL_I2C_SlaveTxCpltCallback 0 static stm32f3xx_hal_i2c.c:4412:13:HAL_I2C_SlaveRxCpltCallback 0 static stm32f3xx_hal_i2c.c:5370:13:I2C_ITSlaveSeqCplt 16 static stm32f3xx_hal_i2c.c:5920:13:I2C_DMASlaveTransmitCplt 8 static stm32f3xx_hal_i2c.c:5995:13:I2C_DMASlaveReceiveCplt 16 static stm32f3xx_hal_i2c.c:4430:13:HAL_I2C_AddrCallback 0 static stm32f3xx_hal_i2c.c:5222:13:I2C_ITAddrCplt.isra.0.part.0 24 static stm32f3xx_hal_i2c.c:4448:13:HAL_I2C_ListenCpltCallback 0 static stm32f3xx_hal_i2c.c:5682:13:I2C_ITListenCplt 8 static stm32f3xx_hal_i2c.c:4464:13:HAL_I2C_MemTxCpltCallback 0 static stm32f3xx_hal_i2c.c:4480:13:HAL_I2C_MemRxCpltCallback 0 static stm32f3xx_hal_i2c.c:4496:13:HAL_I2C_ErrorCallback 0 static stm32f3xx_hal_i2c.c:4512:13:HAL_I2C_AbortCpltCallback 0 static stm32f3xx_hal_i2c.c:5733:13:I2C_ITError 16 static stm32f3xx_hal_i2c.c:5545:13:I2C_ITSlaveCplt 16 static stm32f3xx_hal_i2c.c:4732:26:I2C_Slave_ISR_IT 24 static stm32f3xx_hal_i2c.c:5426:13:I2C_ITMasterCplt 16 static stm32f3xx_hal_i2c.c:4595:26:I2C_Master_ISR_IT 24 static stm32f3xx_hal_i2c.c:5000:26:I2C_Slave_ISR_DMA 24 static stm32f3xx_hal_i2c.c:4865:26:I2C_Master_ISR_DMA 24 static stm32f3xx_hal_i2c.c:5872:13:I2C_DMAMasterTransmitCplt 8 static stm32f3xx_hal_i2c.c:5947:13:I2C_DMAMasterReceiveCplt 8 static stm32f3xx_hal_i2c.c:4316:6:HAL_I2C_ER_IRQHandler 4 static stm32f3xx_hal_i2c.c:6039:13:I2C_DMAAbort 8 static stm32f3xx_hal_i2c.c:6022:13:I2C_DMAError 16 static stm32f3xx_hal_i2c.c:4547:22:HAL_I2C_GetState 0 static stm32f3xx_hal_i2c.c:4559:21:HAL_I2C_GetMode 0 static stm32f3xx_hal_i2c.c:4570:10:HAL_I2C_GetError 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.su ================================================ stm32f3xx_hal_i2c_ex.c:97:19:HAL_I2CEx_ConfigAnalogFilter 8 static stm32f3xx_hal_i2c_ex.c:141:19:HAL_I2CEx_ConfigDigitalFilter 8 static stm32f3xx_hal_i2c_ex.c:192:19:HAL_I2CEx_EnableWakeUp 8 static stm32f3xx_hal_i2c_ex.c:231:19:HAL_I2CEx_DisableWakeUp 8 static stm32f3xx_hal_i2c_ex.c:279:6:HAL_I2CEx_EnableFastModePlus 8 static stm32f3xx_hal_i2c_ex.c:306:6:HAL_I2CEx_DisableFastModePlus 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.su ================================================ stm32f3xx_hal_pwr.c:75:6:HAL_PWR_DeInit 0 static stm32f3xx_hal_pwr.c:88:6:HAL_PWR_EnableBkUpAccess 0 static stm32f3xx_hal_pwr.c:100:6:HAL_PWR_DisableBkUpAccess 0 static stm32f3xx_hal_pwr.c:243:6:HAL_PWR_EnableWakeUpPin 0 static stm32f3xx_hal_pwr.c:258:6:HAL_PWR_DisableWakeUpPin 0 static stm32f3xx_hal_pwr.c:283:6:HAL_PWR_EnterSLEEPMode 0 static,ignoring_inline_asm stm32f3xx_hal_pwr.c:325:6:HAL_PWR_EnterSTOPMode 4 static,ignoring_inline_asm stm32f3xx_hal_pwr.c:375:6:HAL_PWR_EnterSTANDBYMode 0 static,ignoring_inline_asm stm32f3xx_hal_pwr.c:399:6:HAL_PWR_EnableSleepOnExit 0 static stm32f3xx_hal_pwr.c:412:6:HAL_PWR_DisableSleepOnExit 0 static stm32f3xx_hal_pwr.c:426:6:HAL_PWR_EnableSEVOnPend 0 static stm32f3xx_hal_pwr.c:439:6:HAL_PWR_DisableSEVOnPend 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.su ================================================ stm32f3xx_hal_pwr_ex.c:129:6:HAL_PWR_ConfigPVD 4 static stm32f3xx_hal_pwr_ex.c:171:6:HAL_PWR_EnablePVD 0 static stm32f3xx_hal_pwr_ex.c:180:6:HAL_PWR_DisablePVD 0 static stm32f3xx_hal_pwr_ex.c:207:13:HAL_PWR_PVDCallback 0 static stm32f3xx_hal_pwr_ex.c:190:6:HAL_PWR_PVD_IRQHandler 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.su ================================================ stm32f3xx_hal_rcc.c:216:19:HAL_RCC_DeInit 16 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:316:19:HAL_RCC_OscConfig 40 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:696:19:HAL_RCC_ClockConfig 24 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:888:6:HAL_RCC_MCOConfig 56 static stm32f3xx_hal_rcc.c:922:6:HAL_RCC_EnableCSS 0 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:931:6:HAL_RCC_DisableCSS 0 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:965:10:HAL_RCC_GetSysClockFreq 4 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:1029:10:HAL_RCC_GetHCLKFreq 0 static stm32f3xx_hal_rcc.c:1040:10:HAL_RCC_GetPCLK1Freq 0 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:1052:10:HAL_RCC_GetPCLK2Freq 0 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:1065:6:HAL_RCC_GetOscConfig 0 static,ignoring_inline_asm stm32f3xx_hal_rcc.c:1153:6:HAL_RCC_GetClockConfig 4 static stm32f3xx_hal_rcc.c:1200:13:HAL_RCC_CSSCallback 0 static stm32f3xx_hal_rcc.c:1183:6:HAL_RCC_NMI_IRQHandler 8 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.su ================================================ stm32f3xx_hal_rcc_ex.c:107:19:HAL_RCCEx_PeriphCLKConfig 40 static,ignoring_inline_asm stm32f3xx_hal_rcc_ex.c:575:6:HAL_RCCEx_GetPeriphCLKConfig 0 static stm32f3xx_hal_rcc_ex.c:946:10:HAL_RCCEx_GetPeriphCLKFreq 48 static,ignoring_inline_asm ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.su ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.su ================================================ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.su ================================================ stm32f3xx_ll_dac.c:195:13:LL_DAC_DeInit 0 static stm32f3xx_ll_dac.c:238:13:LL_DAC_Init 12 static stm32f3xx_ll_dac.c:306:6:LL_DAC_StructInit 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.su ================================================ stm32f3xx_ll_dma.c:150:10:LL_DMA_DeInit 4 static stm32f3xx_ll_dma.c:239:10:LL_DMA_Init 12 static stm32f3xx_ll_dma.c:301:6:LL_DMA_StructInit 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.su ================================================ stm32f3xx_ll_exti.c:83:10:LL_EXTI_DeInit 8 static stm32f3xx_ll_exti.c:127:10:LL_EXTI_Init 8 static stm32f3xx_ll_exti.c:270:6:LL_EXTI_StructInit 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.su ================================================ stm32f3xx_ll_gpio.c:119:13:LL_GPIO_DeInit 0 static stm32f3xx_ll_gpio.c:194:13:LL_GPIO_Init 32 static,ignoring_inline_asm stm32f3xx_ll_gpio.c:270:6:LL_GPIO_StructInit 0 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.su ================================================ stm32f3xx_ll_rcc.c:224:13:LL_RCC_DeInit 16 static stm32f3xx_ll_rcc.c:322:6:LL_RCC_GetSystemClocksFreq 12 static,ignoring_inline_asm stm32f3xx_ll_rcc.c:348:10:LL_RCC_GetUSARTClockFreq 8 static,ignoring_inline_asm stm32f3xx_ll_rcc.c:554:10:LL_RCC_GetI2CClockFreq 8 static,ignoring_inline_asm stm32f3xx_ll_rcc.c:706:10:LL_RCC_GetADCClockFreq 16 static,ignoring_inline_asm stm32f3xx_ll_rcc.c:819:10:LL_RCC_GetTIMClockFreq 8 static,ignoring_inline_asm stm32f3xx_ll_rcc.c:971:10:LL_RCC_GetHRTIMClockFreq 8 static,ignoring_inline_asm stm32f3xx_ll_rcc.c:1010:10:RCC_GetSystemClockFreq 8 static,ignoring_inline_asm stm32f3xx_ll_rcc.c:1042:10:RCC_GetHCLKClockFreq 0 static stm32f3xx_ll_rcc.c:1053:10:RCC_GetPCLK1ClockFreq 0 static stm32f3xx_ll_rcc.c:1064:10:RCC_GetPCLK2ClockFreq 0 static stm32f3xx_ll_rcc.c:1074:10:RCC_PLL_GetFreqDomain_SYS 4 static,ignoring_inline_asm ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.su ================================================ stm32f3xx_ll_tim.c:236:13:LL_TIM_DeInit 0 static stm32f3xx_ll_tim.c:376:6:LL_TIM_StructInit 0 static stm32f3xx_ll_tim.c:394:13:LL_TIM_Init 8 static stm32f3xx_ll_tim.c:445:6:LL_TIM_OC_StructInit 0 static stm32f3xx_ll_tim.c:474:13:LL_TIM_OC_Init 16 static stm32f3xx_ll_tim.c:513:6:LL_TIM_IC_StructInit 0 static stm32f3xx_ll_tim.c:535:13:LL_TIM_IC_Init 12 static stm32f3xx_ll_tim.c:565:6:LL_TIM_ENCODER_StructInit 0 static stm32f3xx_ll_tim.c:587:13:LL_TIM_ENCODER_Init 20 static stm32f3xx_ll_tim.c:650:6:LL_TIM_HALLSENSOR_StructInit 0 static stm32f3xx_ll_tim.c:679:13:LL_TIM_HALLSENSOR_Init 20 static stm32f3xx_ll_tim.c:758:6:LL_TIM_BDTR_StructInit 0 static stm32f3xx_ll_tim.c:794:13:LL_TIM_BDTR_Init 12 static ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.d ================================================ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.o: \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ ../Core/Inc/stm32f3xx_hal_conf.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h \ ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: ../Core/Inc/stm32f3xx_hal_conf.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h: ../Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h: ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.su ================================================ stm32f3xx_ll_utils.c:497:20:UTILS_EnablePLLAndSwitchSystem 16 static,ignoring_inline_asm stm32f3xx_ll_utils.c:151:6:LL_Init1msTick 0 static stm32f3xx_ll_utils.c:167:6:LL_mDelay 8 static stm32f3xx_ll_utils.c:225:6:LL_SetSystemCoreClock 0 static stm32f3xx_ll_utils.c:248:13:LL_PLL_ConfigSystemClock_HSI 12 static,ignoring_inline_asm stm32f3xx_ll_utils.c:317:13:LL_PLL_ConfigSystemClock_HSE 16 static,ignoring_inline_asm ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/Drivers/STM32F3xx_HAL_Driver/Src/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c \ ../Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c OBJS += \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.o \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.o C_DEPS += \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.d \ ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.d # Each subdirectory must supply rules for building sources it contributes Drivers/STM32F3xx_HAL_Driver/Src/%.o: ../Drivers/STM32F3xx_HAL_Driver/Src/%.c Drivers/STM32F3xx_HAL_Driver/Src/subdir.mk arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F334x8 -DUSE_FULL_LL_DRIVER -DDEBUG -c -I../Drivers/CMSIS/Include -I../Drivers/STM32F3xx_HAL_Driver/Inc -I../Core/Inc -I../Drivers/STM32F3xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F3xx/Include -Ofast -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Drivers-2f-STM32F3xx_HAL_Driver-2f-Src clean-Drivers-2f-STM32F3xx_HAL_Driver-2f-Src: -$(RM) ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.o ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.d ./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.o .PHONY: clean-Drivers-2f-STM32F3xx_HAL_Driver-2f-Src ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/makefile ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ -include ../makefile.init RM := rm -rf # All of the sources participating in the build are defined here -include sources.mk -include Drivers/STM32F3xx_HAL_Driver/Src/subdir.mk -include Core/Startup/subdir.mk -include Core/Src/subdir.mk -include objects.mk ifneq ($(MAKECMDGOALS),clean) ifneq ($(strip $(S_DEPS)),) -include $(S_DEPS) endif ifneq ($(strip $(S_UPPER_DEPS)),) -include $(S_UPPER_DEPS) endif ifneq ($(strip $(C_DEPS)),) -include $(C_DEPS) endif endif -include ../makefile.defs OPTIONAL_TOOL_DEPS := \ $(wildcard ../makefile.defs) \ $(wildcard ../makefile.init) \ $(wildcard ../makefile.targets) \ BUILD_ARTIFACT_NAME := 2OPFM_2020 BUILD_ARTIFACT_EXTENSION := elf BUILD_ARTIFACT_PREFIX := BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) # Add inputs and outputs from these tool invocations to the build variables EXECUTABLES += \ 2OPFM_2020.elf \ SIZE_OUTPUT += \ default.size.stdout \ OBJDUMP_LIST += \ 2OPFM_2020.list \ OBJCOPY_BIN += \ 2OPFM_2020.bin \ # All Target all: +@$(MAKE) --no-print-directory main-build && $(MAKE) --no-print-directory post-build # Main-build Target main-build: 2OPFM_2020.elf secondary-outputs # Tool invocations 2OPFM_2020.elf: $(OBJS) $(USER_OBJS) /Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_2020/STM32F334K8TX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-gcc -o "2OPFM_2020.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/Users/chrismcdowell/Desktop/Super/super_fw_2023/2OPFM_2020/STM32F334K8TX_FLASH.ld" --specs=nosys.specs -Wl,-Map="2OPFM_2020.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group @echo 'Finished building target: $@' @echo ' ' default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-size $(EXECUTABLES) @echo 'Finished building: $@' @echo ' ' 2OPFM_2020.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-objdump -h -S $(EXECUTABLES) > "2OPFM_2020.list" @echo 'Finished building: $@' @echo ' ' 2OPFM_2020.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-objcopy -O binary $(EXECUTABLES) "2OPFM_2020.bin" @echo 'Finished building: $@' @echo ' ' # Other Targets clean: -$(RM) 2OPFM_2020.bin 2OPFM_2020.elf 2OPFM_2020.list default.size.stdout -@echo ' ' post-build: arm-none-eabi-objcopy -O ihex 2OPFM_2020.elf 2OPFM_2020.hex -@echo ' ' secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) fail-specified-linker-script-missing: @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' @exit 2 warn-no-linker-script-specified: @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' .PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified post-build -include ../makefile.targets ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/objects.list ================================================ "./Core/Src/2op_main.o" "./Core/Src/dac.o" "./Core/Src/dynamic_smooth.o" "./Core/Src/loop.o" "./Core/Src/main.o" "./Core/Src/noise.o" "./Core/Src/stm32f3xx_hal_msp.o" "./Core/Src/stm32f3xx_it.o" "./Core/Src/syscalls.o" "./Core/Src/sysmem.o" "./Core/Src/system_stm32f3xx.o" "./Core/Startup/startup_stm32f334k8tx.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.o" "./Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.o" ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/objects.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ USER_OBJS := LIBS := ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Debug/sources.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (9-2020-q2-update) ################################################################################ ELF_SRCS := OBJ_SRCS := S_SRCS := C_SRCS := S_UPPER_SRCS := O_SRCS := SIZE_OUTPUT := OBJDUMP_LIST := EXECUTABLES := OBJS := S_DEPS := S_UPPER_DEPS := C_DEPS := OBJCOPY_BIN := # Every subdirectory with source files must be described here SUBDIRS := \ Core/Src \ Core/Startup \ Drivers/STM32F3xx_HAL_Driver/Src \ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h ================================================ /** ****************************************************************************** * @file stm32f334x8.h * @author MCD Application Team * @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32f334x8 * @{ */ #ifndef __STM32F334x8_H #define __STM32F334x8_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ #define __MPU_PRESENT 0U /*!< STM32F334x8 devices do not provide an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /*!< STM32F334x8 devices provide an FPU */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */ HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */ HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32f3xx.h" /* STM32F3xx System Header */ #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ uint32_t RESERVED0; /*!< Reserved, 0x010 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved, 0x01C */ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ uint32_t RESERVED3; /*!< Reserved, 0x044 */ uint32_t RESERVED4; /*!< Reserved, 0x048 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ uint32_t RESERVED9; /*!< Reserved, 0x0AC */ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual AND triple modes, Address offset: ADC1/3 base address + 0x30C */ } ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; /** * @brief Analog Comparators */ typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ } COMP_TypeDef; typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ } COMP_Common_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*!
© Copyright (c) 2016 STMicroelectronics. * All rights reserved.
* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f3xx * @{ */ #ifndef __STM32F3xx_H #define __STM32F3xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Library_configuration_section * @{ */ /** * @brief STM32 Family */ #if !defined (STM32F3) #define STM32F3 #endif /* STM32F3 */ /* Uncomment the line below according to the target STM32 device used in your application */ #if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \ !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \ !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \ !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \ !defined (STM32F373xC) && !defined (STM32F378xx) /* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8, STM32F301R6 and STM32F301R8 Devices */ /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8, STM32F302R6 and STM32F302R8 Devices */ /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */ /* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD, STM32F302VD and STM32F302ZD Devices */ /* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, STM32F303R6 and STM32F303R8 Devices */ /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */ /* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD, STM32F303VD and STM32F303ZD Devices */ /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC, STM32F373V8, STM32F373VB and STM32F373VC Devices */ /* #define STM32F334x8 */ /*!< STM32F334K4, STM32F334K6, STM32F334K8, STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */ /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */ /* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */ /* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */ /* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */ /* #define STM32F398xx */ /*!< STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ #if !defined (USE_HAL_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ /*#define USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */ /** * @brief CMSIS Device version number V2.3.4 */ #define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F3_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ #define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\ |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F3_CMSIS_VERSION_SUB2 << 8 )\ |(__STM32F3_CMSIS_VERSION_RC)) /** * @} */ /** @addtogroup Device_Included * @{ */ #if defined(STM32F301x8) #include "stm32f301x8.h" #elif defined(STM32F302x8) #include "stm32f302x8.h" #elif defined(STM32F302xC) #include "stm32f302xc.h" #elif defined(STM32F302xE) #include "stm32f302xe.h" #elif defined(STM32F303x8) #include "stm32f303x8.h" #elif defined(STM32F303xC) #include "stm32f303xc.h" #elif defined(STM32F303xE) #include "stm32f303xe.h" #elif defined(STM32F373xC) #include "stm32f373xc.h" #elif defined(STM32F334x8) #include "stm32f334x8.h" #elif defined(STM32F318xx) #include "stm32f318xx.h" #elif defined(STM32F328xx) #include "stm32f328xx.h" #elif defined(STM32F358xx) #include "stm32f358xx.h" #elif defined(STM32F378xx) #include "stm32f378xx.h" #elif defined(STM32F398xx) #include "stm32f398xx.h" #else #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)" #endif /** * @} */ /** @addtogroup Exported_types * @{ */ typedef enum { RESET = 0U, SET = !RESET } FlagStatus, ITStatus; typedef enum { DISABLE = 0U, ENABLE = !DISABLE } FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum { SUCCESS = 0U, ERROR = !SUCCESS } ErrorStatus; /** * @} */ /** @addtogroup Exported_macros * @{ */ #define SET_BIT(REG, BIT) ((REG) |= (BIT)) #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT)) #define CLEAR_REG(REG) ((REG) = (0x0)) #define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define READ_REG(REG) ((REG)) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) /** * @} */ #if defined (USE_HAL_DRIVER) #include "stm32f3xx_hal.h" #endif /* USE_HAL_DRIVER */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __STM32F3xx_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h ================================================ /** ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f3xx_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32F3XX_H #define __SYSTEM_STM32F3XX_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F3xx_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32F3xx_System_Exported_types * @{ */ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 3) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) by calling HAL API function HAL_RCC_ClockConfig() Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ /** * @} */ /** @addtogroup STM32F3xx_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32F3xx_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32F3xx_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32F3XX_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/cmsis_armcc.h ================================================ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #error "Please use Arm Compiler Toolchain V4.0.677 or later!" #endif /* CMSIS compiler control architecture macros */ #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) #define __ARM_ARCH_6M__ 1 #endif #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) #define __ARM_ARCH_7M__ 1 #endif #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) #define __ARM_ARCH_7EM__ 1 #endif /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline #endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION __packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif #ifndef __UNALIGNED_UINT16_WRITE #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) #endif #ifndef __UNALIGNED_UINT32_WRITE #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); } /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); } /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xFFU); } /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) { register uint32_t __regBasePriMax __ASM("basepri_max"); __regBasePriMax = (basePri & 0xFFU); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1U); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() do {\ __schedule_barrier();\ __isb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() do {\ __schedule_barrier();\ __dsb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() do {\ __schedule_barrier();\ __dmb(0xF);\ __schedule_barrier();\ } while (0U) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return result; } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/cmsis_armclang.h ================================================ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF); /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF); /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF); /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ (uint8_t)__builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/cmsis_compiler.h ================================================ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* * Arm Compiler 6 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) #include /* * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) #include #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) #include #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #else #error Unknown compiler. #endif #endif /* __CMSIS_COMPILER_H */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/cmsis_gcc.h ================================================ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V5.0.4 * @date 09. April 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #endif #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_set_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #endif #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI() __ASM volatile ("wfi") /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE() __ASM volatile ("wfe") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV() __ASM volatile ("sev") /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); #else int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ (uint8_t)__builtin_clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/cmsis_iccarm.h ================================================ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.0.7 * @date 19. June 2018 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2018 IAR Systems // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // //------------------------------------------------------------------------------ #ifndef __CMSIS_ICCARM_H__ #define __CMSIS_ICCARM_H__ #ifndef __ICCARM__ #error This file should only be compiled by ICCARM #endif #pragma system_include #define __IAR_FT _Pragma("inline=forced") __intrinsic #if (__VER__ >= 8000000) #define __ICCARM_V8 1 #else #define __ICCARM_V8 0 #endif #ifndef __ALIGNED #if __ICCARM_V8 #define __ALIGNED(x) __attribute__((aligned(x))) #elif (__VER__ >= 7080000) /* Needs IAR language extensions */ #define __ALIGNED(x) __attribute__((aligned(x))) #else #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. #define __ALIGNED(x) #endif #endif /* Define compiler macros for CPU architecture, used in CMSIS 5. */ #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ /* Macros already defined */ #else #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' #if __ARM_ARCH == 6 #define __ARM_ARCH_6M__ 1 #elif __ARM_ARCH == 7 #if __ARM_FEATURE_DSP #define __ARM_ARCH_7EM__ 1 #else #define __ARM_ARCH_7M__ 1 #endif #endif /* __ARM_ARCH */ #endif /* __ARM_ARCH_PROFILE == 'M' */ #endif /* Alternativ core deduction for older ICCARM's */ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) #define __ARM_ARCH_6M__ 1 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) #define __ARM_ARCH_7M__ 1 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) #define __ARM_ARCH_7EM__ 1 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #else #error "Unknown target." #endif #endif #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 #define __IAR_M0_FAMILY 1 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 #define __IAR_M0_FAMILY 1 #else #define __IAR_M0_FAMILY 0 #endif #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __NO_RETURN #if __ICCARM_V8 #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif #endif #ifndef __PACKED #if __ICCARM_V8 #define __PACKED __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED __packed #endif #endif #ifndef __PACKED_STRUCT #if __ICCARM_V8 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_STRUCT __packed struct #endif #endif #ifndef __PACKED_UNION #if __ICCARM_V8 #define __PACKED_UNION union __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_UNION __packed union #endif #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma language=save #pragma language=extended __packed struct __iar_u32 { uint32_t v; }; #pragma language=restore #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) #endif #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) #else #define __USED _Pragma("__root") #endif #endif #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) #else #define __WEAK _Pragma("__weak") #endif #endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif #if __ICCARM_INTRINSICS_VERSION__ == 2 #if defined(__CLZ) #undef __CLZ #endif #if defined(__REVSH) #undef __REVSH #endif #if defined(__RBIT) #undef __RBIT #endif #if defined(__SSAT) #undef __SSAT #endif #if defined(__USAT) #undef __USAT #endif #include "iccarm_builtin.h" #define __disable_fault_irq __iar_builtin_disable_fiq #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt #define __arm_rsr __iar_builtin_rsr #define __arm_wsr __iar_builtin_wsr #define __get_APSR() (__arm_rsr("APSR")) #define __get_BASEPRI() (__arm_rsr("BASEPRI")) #define __get_CONTROL() (__arm_rsr("CONTROL")) #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR() (__arm_rsr("FPSCR")) #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) #else #define __get_FPSCR() ( 0 ) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #define __get_IPSR() (__arm_rsr("IPSR")) #define __get_MSP() (__arm_rsr("MSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __get_MSPLIM() (0U) #else #define __get_MSPLIM() (__arm_rsr("MSPLIM")) #endif #define __get_PRIMASK() (__arm_rsr("PRIMASK")) #define __get_PSP() (__arm_rsr("PSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __get_PSPLIM() (0U) #else #define __get_PSPLIM() (__arm_rsr("PSPLIM")) #endif #define __get_xPSR() (__arm_rsr("xPSR")) #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __set_MSPLIM(VALUE) ((void)(VALUE)) #else #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) #endif #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __set_PSPLIM(VALUE) ((void)(VALUE)) #else #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __TZ_get_PSPLIM_NS() (0U) #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) #else #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) #endif #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) #define __NOP __iar_builtin_no_operation #define __CLZ __iar_builtin_CLZ #define __CLREX __iar_builtin_CLREX #define __DMB __iar_builtin_DMB #define __DSB __iar_builtin_DSB #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH #define __LDREXW __iar_builtin_LDREX #define __RBIT __iar_builtin_RBIT #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 __IAR_FT int16_t __REVSH(int16_t val) { return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR #define __RRX __iar_builtin_RRX #define __SEV __iar_builtin_SEV #if !__IAR_M0_FAMILY #define __SSAT __iar_builtin_SSAT #endif #define __STREXB __iar_builtin_STREXB #define __STREXH __iar_builtin_STREXH #define __STREXW __iar_builtin_STREX #if !__IAR_M0_FAMILY #define __USAT __iar_builtin_USAT #endif #define __WFE __iar_builtin_WFE #define __WFI __iar_builtin_WFI #if __ARM_MEDIA__ #define __SADD8 __iar_builtin_SADD8 #define __QADD8 __iar_builtin_QADD8 #define __SHADD8 __iar_builtin_SHADD8 #define __UADD8 __iar_builtin_UADD8 #define __UQADD8 __iar_builtin_UQADD8 #define __UHADD8 __iar_builtin_UHADD8 #define __SSUB8 __iar_builtin_SSUB8 #define __QSUB8 __iar_builtin_QSUB8 #define __SHSUB8 __iar_builtin_SHSUB8 #define __USUB8 __iar_builtin_USUB8 #define __UQSUB8 __iar_builtin_UQSUB8 #define __UHSUB8 __iar_builtin_UHSUB8 #define __SADD16 __iar_builtin_SADD16 #define __QADD16 __iar_builtin_QADD16 #define __SHADD16 __iar_builtin_SHADD16 #define __UADD16 __iar_builtin_UADD16 #define __UQADD16 __iar_builtin_UQADD16 #define __UHADD16 __iar_builtin_UHADD16 #define __SSUB16 __iar_builtin_SSUB16 #define __QSUB16 __iar_builtin_QSUB16 #define __SHSUB16 __iar_builtin_SHSUB16 #define __USUB16 __iar_builtin_USUB16 #define __UQSUB16 __iar_builtin_UQSUB16 #define __UHSUB16 __iar_builtin_UHSUB16 #define __SASX __iar_builtin_SASX #define __QASX __iar_builtin_QASX #define __SHASX __iar_builtin_SHASX #define __UASX __iar_builtin_UASX #define __UQASX __iar_builtin_UQASX #define __UHASX __iar_builtin_UHASX #define __SSAX __iar_builtin_SSAX #define __QSAX __iar_builtin_QSAX #define __SHSAX __iar_builtin_SHSAX #define __USAX __iar_builtin_USAX #define __UQSAX __iar_builtin_UQSAX #define __UHSAX __iar_builtin_UHSAX #define __USAD8 __iar_builtin_USAD8 #define __USADA8 __iar_builtin_USADA8 #define __SSAT16 __iar_builtin_SSAT16 #define __USAT16 __iar_builtin_USAT16 #define __UXTB16 __iar_builtin_UXTB16 #define __UXTAB16 __iar_builtin_UXTAB16 #define __SXTB16 __iar_builtin_SXTB16 #define __SXTAB16 __iar_builtin_SXTAB16 #define __SMUAD __iar_builtin_SMUAD #define __SMUADX __iar_builtin_SMUADX #define __SMMLA __iar_builtin_SMMLA #define __SMLAD __iar_builtin_SMLAD #define __SMLADX __iar_builtin_SMLADX #define __SMLALD __iar_builtin_SMLALD #define __SMLALDX __iar_builtin_SMLALDX #define __SMUSD __iar_builtin_SMUSD #define __SMUSDX __iar_builtin_SMUSDX #define __SMLSD __iar_builtin_SMLSD #define __SMLSDX __iar_builtin_SMLSDX #define __SMLSLD __iar_builtin_SMLSLD #define __SMLSLDX __iar_builtin_SMLSLDX #define __SEL __iar_builtin_SEL #define __QADD __iar_builtin_QADD #define __QSUB __iar_builtin_QSUB #define __PKHBT __iar_builtin_PKHBT #define __PKHTB __iar_builtin_PKHTB #endif #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #define __CLZ __cmsis_iar_clz_not_active #define __SSAT __cmsis_iar_ssat_not_active #define __USAT __cmsis_iar_usat_not_active #define __RBIT __cmsis_iar_rbit_not_active #define __get_APSR __cmsis_iar_get_APSR_not_active #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #define __set_FPSCR __cmsis_iar_set_FPSR_not_active #endif #ifdef __INTRINSICS_INCLUDED #error intrinsics.h is already included previously! #endif #include #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #undef __CLZ #undef __SSAT #undef __USAT #undef __RBIT #undef __get_APSR __STATIC_INLINE uint8_t __CLZ(uint32_t data) { if (data == 0U) { return 32U; } uint32_t count = 0U; uint32_t mask = 0x80000000U; while ((data & mask) == 0U) { count += 1U; mask = mask >> 1U; } return count; } __STATIC_INLINE uint32_t __RBIT(uint32_t v) { uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) { r <<= 1U; r |= v & 1U; sc--; } return (r << sc); } __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t res; __asm("MRS %0,APSR" : "=r" (res)); return res; } #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #undef __get_FPSCR #undef __set_FPSCR #define __get_FPSCR() (0) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #pragma diag_suppress=Pe940 #pragma diag_suppress=Pe177 #define __enable_irq __enable_interrupt #define __disable_irq __disable_interrupt #define __NOP __no_operation #define __get_xPSR __get_PSR #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); } __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); } #endif /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); } #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #endif /* (__CORTEX_M >= 0x03) */ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint32_t __get_MSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,MSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_MSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR MSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __get_PSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_PSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR PSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_MSP_NS(void) { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR MSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_SP_NS(void) { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR SP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); #endif return res; } __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t res; __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t res; __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { uint32_t res; __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #undef __IAR_FT #undef __IAR_M0_FAMILY #undef __ICCARM_V8 #pragma diag_default=Pe940 #pragma diag_default=Pe177 #endif /* __CMSIS_ICCARM_H__ */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/cmsis_version.h ================================================ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions * @version V5.0.2 * @date 19. April 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_VERSION_H #define __CMSIS_VERSION_H /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_armv8mbl.h ================================================ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File * @version V5.0.7 * @date 22. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MBL_H_GENERIC #define __CORE_ARMV8MBL_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MBL @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MBL_H_DEPENDANT #define __CORE_ARMV8MBL_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MBL_REV #define __ARMv8MBL_REV 0x0000U #warning "__ARMv8MBL_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MBL */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_armv8mml.h ================================================ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File * @version V5.0.7 * @date 06. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MML_H_GENERIC #define __CORE_ARMV8MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MML @{ */ #include "cmsis_version.h" /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MML_H_DEPENDANT #define __CORE_ARMV8MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MML_REV #define __ARMv8MML_REV 0x0000U #warning "__ARMv8MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm0.h ================================================ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V5.0.5 * @date 28. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ #include "cmsis_version.h" /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)0x0U; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm0plus.h ================================================ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V5.0.6 * @date 28. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ #include "cmsis_version.h" /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000U #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm1.h ================================================ /**************************************************************************//** * @file core_cm1.h * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File * @version V1.0.0 * @date 23. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM1_H_GENERIC #define __CORE_CM1_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M1 @{ */ #include "cmsis_version.h" /* CMSIS CM1 definitions */ #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (1U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM1_H_DEPENDANT #define __CORE_CM1_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM1_REV #define __CM1_REV 0x0100U #warning "__CM1_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M1 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M1 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)0x0U; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm23.h ================================================ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File * @version V5.0.7 * @date 22. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM23_H_GENERIC #define __CORE_CM23_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M23 @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (23U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM23_H_DEPENDANT #define __CORE_CM23_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM23_REV #define __CM23_REV 0x0000U #warning "__CM23_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M23 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm3.h ================================================ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 04. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ #include "cmsis_version.h" /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm33.h ================================================ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File * @version V5.0.9 * @date 06. July 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM33_H_GENERIC #define __CORE_CM33_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M33 @{ */ #include "cmsis_version.h" /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_PCS_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM33_H_DEPENDANT #define __CORE_CM33_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM33_REV #define __CM33_REV 0x0000U #warning "__CM33_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M33 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm4.h ================================================ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 04. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ #include "cmsis_version.h" /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000U #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_cm7.h ================================================ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 04. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M7 @{ */ #include "cmsis_version.h" /* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (7U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM7_H_DEPENDANT #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM7_REV #define __CM7_REV 0x0000U #warning "__CM7_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M7 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED3[93U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED3[981U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = SCB->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_INLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_INLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_INLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_INLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_INLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_INLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_INLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_INLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t)addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCIMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) int32_t op_size = dsize; uint32_t op_addr = (uint32_t) addr; int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ __DSB(); while (op_size > 0) { SCB->DCCIMVAC = op_addr; op_addr += (uint32_t)linesize; op_size -= linesize; } __DSB(); __ISB(); #endif } /*@} end of CMSIS_Core_CacheFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_sc000.h ================================================ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.5 * @date 28. May 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ #include "cmsis_version.h" /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/core_sc300.h ================================================ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.6 * @date 04. June 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ #include "cmsis_version.h" /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ uint32_t RESERVED1[1U]; } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/mpu_armv7.h ================================================ /****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access /** MPU Region Base Address Register Value * * \param Region The region to be configured, number 0 to 15. * \param BaseAddress The base address for the region. */ #define ARM_MPU_RBAR(Region, BaseAddress) \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \ (MPU_RBAR_VALID_Msk)) /** * MPU Memory Access Attributes * * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. */ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) /** * MPU Memory Access Attribute for strongly ordered memory. * - TEX: 000b * - Shareable * - Non-cacheable * - Non-bufferable */ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** * MPU Memory Access Attribute for device memory. * - TEX: 000b (if non-shareable) or 010b (if shareable) * - Shareable or non-shareable * - Non-cacheable * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** * MPU Memory Access Attribute for normal memory. * - TEX: 1BBb (reflecting outer cacheability rules) * - Shareable or non-shareable * - Cacheable or non-cacheable (reflecting inner cacheability rules) * - Bufferable or non-bufferable (reflecting inner cacheability rules) * * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) /** * MPU Memory Access Attribute non-cacheable policy. */ #define ARM_MPU_CACHEP_NOCACHE 0U /** * MPU Memory Access Attribute write-back, write and read allocate policy. */ #define ARM_MPU_CACHEP_WB_WRA 1U /** * MPU Memory Access Attribute write-through, no write allocate policy. */ #define ARM_MPU_CACHEP_WT_NWA 2U /** * MPU Memory Access Attribute write-back, no write allocate policy. */ #define ARM_MPU_CACHEP_WB_NWA 3U /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { __DSB(); __ISB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DSB(); __ISB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { MPU->RNR = rnr; MPU->RASR = 0U; } /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; MPU->RASR = rasr; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; MPU->RBAR = rbar; MPU->RASR = rasr; } /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); table += MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES; } orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/mpu_armv8.h ================================================ /****************************************************************************** * @file mpu_armv8.h * @brief CMSIS MPU API for Armv8-M MPU * @version V5.0.4 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H /** \brief Attribute for device memory (outer only) */ #define ARM_MPU_ATTR_DEVICE ( 0U ) /** \brief Attribute for non-cacheable, normal memory */ #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) /** \brief Attribute for normal memory (outer and inner) * \param NT Non-Transient: Set to 1 for non-transient data. * \param WB Write-Back: Set to 1 to use write-back update policy. * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. */ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGRE (2U) /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_GRE (3U) /** \brief Memory Attribute * \param O Outer memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes */ #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) /** \brief Normal memory non-shareable */ #define ARM_MPU_SH_NON (0U) /** \brief Normal memory outer shareable */ #define ARM_MPU_SH_OUTER (2U) /** \brief Normal memory inner shareable */ #define ARM_MPU_SH_INNER (3U) /** \brief Memory access permissions * \param RO Read-Only: Set to 1 for read-only memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory. */ #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) /** \brief Region Base Address Register value * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. * \param SH Defines the Shareability domain for this memory region. * \param RO Read-Only: Set to 1 for a read-only memory region. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ ((BASE & MPU_RBAR_BASE_Msk) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) /** \brief Region Limit Address Register value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR(LIMIT, IDX) \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { __DSB(); __ISB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DSB(); __ISB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #ifdef MPU_NS /** Enable the Non-secure MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { __DSB(); __ISB(); MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif } /** Disable the Non-secure MPU. */ __STATIC_INLINE void ARM_MPU_Disable_NS(void) { __DSB(); __ISB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #endif /** Set the memory attribute encoding to the given MPU. * \param mpu Pointer to the MPU to be configured. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) { const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } /** Set the memory attribute encoding. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU, idx, attr); } #ifdef MPU_NS /** Set the memory attribute encoding to the Non-secure MPU. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); } #endif /** Clear and disable the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) { mpu->RNR = rnr; mpu->RLAR = 0U; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU, rnr); } #ifdef MPU_NS /** Clear and disable the given Non-secure MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif /** Configure the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; mpu->RBAR = rbar; mpu->RLAR = rlar; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); } #ifdef MPU_NS /** Configure the given Non-secure MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table to the given MPU. * \param mpu Pointer to the MPU registers to be used. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); table += c; cnt -= c; rnrOffset = 0U; rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } /** Load the given number of MPU regions from a table. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } #ifdef MPU_NS /** Load the given number of MPU regions from a table to the Non-secure MPU. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } #endif #endif ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/CMSIS/Include/tz_context.h ================================================ /****************************************************************************** * @file tz_context.h * @brief Context Management for Armv8-M TrustZone * @version V1.0.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H #include #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); #endif // TZ_CONTEXT_H ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h ================================================ /** ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32_HAL_LEGACY #define STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose * @{ */ #define AES_FLAG_RDERR CRYP_FLAG_RDERR #define AES_FLAG_WRERR CRYP_FLAG_WRERR #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR /** * @} */ /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ #define ADC_RESOLUTION12b ADC_RESOLUTION_12B #define ADC_RESOLUTION10b ADC_RESOLUTION_10B #define ADC_RESOLUTION8b ADC_RESOLUTION_8B #define ADC_RESOLUTION6b ADC_RESOLUTION_6B #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV #define REGULAR_GROUP ADC_REGULAR_GROUP #define INJECTED_GROUP ADC_INJECTED_GROUP #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP #define AWD_EVENT ADC_AWD_EVENT #define AWD1_EVENT ADC_AWD1_EVENT #define AWD2_EVENT ADC_AWD2_EVENT #define AWD3_EVENT ADC_AWD3_EVENT #define OVR_EVENT ADC_OVR_EVENT #define JQOVF_EVENT ADC_JQOVF_EVENT #define ALL_CHANNELS ADC_ALL_CHANNELS #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} */ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32L0) || defined(STM32L4) #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 #if defined(STM32L0) /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ /* to the second dedicated IO (only for COMP2). */ #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 #else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 #endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ #if defined(COMP_CSR_LOCK) #define COMP_FLAG_LOCK COMP_CSR_LOCK #elif defined(COMP_CSR_COMP1LOCK) #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK #elif defined(COMP_CSR_COMPxLOCK) #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK #endif #if defined(STM32L4) #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE #endif #if defined(STM32L0) #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER #else #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER #endif #endif /** * @} */ /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig /** * @} */ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE /** * @} */ /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose * @{ */ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 #define DAC_WAVE_NONE 0x00000000U #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #if defined(STM32G4) #define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) #define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) #endif #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif /** * @} */ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 #define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE #if defined(STM32L4) #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #endif /* STM32L4 */ #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE #define OBEX_PCROP OPTIONBYTE_PCROP #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD #define PAGESIZE FLASH_PAGE_SIZE #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS #define OB_WDG_SW OB_IWDG_SW #define OB_WDG_HW OB_IWDG_HW #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 #if defined(STM32G0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 #if defined(STM32G4) #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ /** * @} */ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 #endif /** * @} */ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** * @} */ /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose * @{ */ #define GET_GPIO_SOURCE GPIO_GET_INDEX #define GET_GPIO_INDEX GPIO_GET_INDEX #if defined(STM32F4) #define GPIO_AF12_SDMMC GPIO_AF12_SDIO #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO #endif #if defined(STM32F7) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32L4) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32H7) #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 #endif #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset #endif /* STM32G4 */ #if defined(STM32H7) #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose * @{ */ #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose * @{ */ #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose * @{ */ #define KR_KEY_RELOAD IWDG_KEY_RELOAD #define KR_KEY_ENABLE IWDG_KEY_ENABLE #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS /** * @} */ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE /** * @} */ /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ #define NOR_StatusTypedef HAL_NOR_StatusTypeDef #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS #define NOR_ONGOING HAL_NOR_STATUS_ONGOING #define NOR_ERROR HAL_NOR_STATUS_ERROR #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT #define __NOR_WRITE NOR_WRITE #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose * @{ */ #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #if defined(STM32L1) || defined(STM32L4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif /** * @} */ /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) #define I2S_IT_TXE I2S_IT_TXP #define I2S_IT_RXNE I2S_IT_RXP #define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} */ /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose * @{ */ /* Compact Flash-ATA registers description */ #define CF_DATA ATA_DATA #define CF_SECTOR_COUNT ATA_SECTOR_COUNT #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER #define CF_CYLINDER_LOW ATA_CYLINDER_LOW #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH #define CF_CARD_HEAD ATA_CARD_HEAD #define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT /** * @} */ /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN /** * @} */ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE #if defined(STM32H7) #define SPI_FLAG_TXE SPI_FLAG_TXP #define SPI_FLAG_RXNE SPI_FLAG_RXP #define SPI_IT_TXE SPI_IT_TXP #define SPI_IT_RXNE SPI_IT_RXP #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR #define TIM_DMABase_DIER TIM_DMABASE_DIER #define TIM_DMABase_SR TIM_DMABASE_SR #define TIM_DMABase_EGR TIM_DMABASE_EGR #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 #define TIM_DMABase_CCER TIM_DMABASE_CCER #define TIM_DMABase_CNT TIM_DMABASE_CNT #define TIM_DMABase_PSC TIM_DMABASE_PSC #define TIM_DMABase_ARR TIM_DMABASE_ARR #define TIM_DMABase_RCR TIM_DMABASE_RCR #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR #define TIM_DMABase_DCR TIM_DMABASE_DCR #define TIM_DMABase_DMAR TIM_DMABASE_DMAR #define TIM_DMABase_OR1 TIM_DMABASE_OR1 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 #define TIM_DMABase_OR TIM_DMABASE_OR #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS #if defined(STM32L0) #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO #endif #if defined(STM32F3) #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #endif #if defined(STM32H7) #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif /** * @} */ /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose * @{ */ #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING /** * @} */ /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose * @{ */ #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 #define __DIV_LPUART UART_DIV_LPUART #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK /** * @} */ /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE #define USARTNACK_ENABLED USART_NACK_ENABLE #define USARTNACK_DISABLED USART_NACK_DISABLE /** * @} */ /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose * @{ */ #define CFR_BASE WWDG_CFR_BASE /** * @} */ /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose * @{ */ #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) #define CAN_TXSTATUS_OK ((uint8_t)0x01U) #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) /** * @} */ /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ #define VLAN_TAG ETH_VLAN_TAG #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK #define ETH_MMCCR 0x00000100U #define ETH_MMCRIR 0x00000104U #define ETH_MMCTIR 0x00000108U #define ETH_MMCRIMR 0x0000010CU #define ETH_MMCTIMR 0x00000110U #define ETH_MMCTGFSCCR 0x0000014CU #define ETH_MMCTGFMSCCR 0x00000150U #define ETH_MMCTGFCR 0x00000168U #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} */ /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR #define DCMI_IT_OVF DCMI_IT_OVR #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop /** * @} */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ || defined(STM32H7) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 #define CM_RGB888 DMA2D_INPUT_RGB888 #define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 #define CM_L8 DMA2D_INPUT_L8 #define CM_AL44 DMA2D_INPUT_AL44 #define CM_AL88 DMA2D_INPUT_AL88 #define CM_L4 DMA2D_INPUT_L4 #define CM_A8 DMA2D_INPUT_A8 #define CM_A4 DMA2D_INPUT_A4 /** * @} */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish /*HASH Algorithm Selection*/ #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY /** * @} */ /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) #else #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) /** * @} */ /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose * @{ */ #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program /** * @} */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB #define PMODE_BIT_NUMBER VOS_BIT_NUMBER #define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER #define PMODE_BitNumber PMODE_BIT_NUMBER #define EWUP_BitNumber EWUP_BIT_NUMBER #define FPDS_BitNumber FPDS_BIT_NUMBER #define ODEN_BitNumber ODEN_BIT_NUMBER #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ */ #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} */ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ /** * @} */ /* Exported macros ------------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose * @{ */ #define AES_IT_CC CRYP_IT_CC #define AES_IT_ERR CRYP_IT_ERR #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} */ /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER /** * @} */ /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ #define __ADC_ENABLE __HAL_ADC_ENABLE #define __ADC_DISABLE __HAL_ADC_DISABLE #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE #define __ADC_IS_ENABLED ADC_IS_ENABLE #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR_RK ADC_JSQR_RK #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER #define __HAL_ADC_SQR1 ADC_SQR1 #define __HAL_ADC_SMPR1 ADC_SMPR1 #define __HAL_ADC_SMPR2 ADC_SMPR2 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK #define __HAL_ADC_SQR2_RK ADC_SQR2_RK #define __HAL_ADC_SQR1_RK ADC_SQR1_RK #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ /** * @} */ /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE /** * @} */ /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 /** * @} */ /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32F3) #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP7_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP7_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ __HAL_COMP_COMP7_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) # endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) #endif #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE #if defined(STM32L0) || defined(STM32L4) /* Note: On these STM32 families, the only argument of this macro */ /* is COMP_FLAG_LOCK. */ /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ /* argument. */ #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) #endif /** * @} */ #if defined(STM32L0) || defined(STM32L4) /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ /** * @} */ #endif /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} */ /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose * @{ */ #define IS_WRPAREA IS_OB_WRPAREA #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM #define IS_TYPEERASE IS_FLASH_TYPEERASE #define IS_NBSECTORS IS_FLASH_NBSECTORS #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE /** * @} */ /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE #else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE #endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST #define __HAL_I2C_SPEED I2C_SPEED #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB #define __HAL_I2C_FREQRANGE I2C_FREQRANGE /** * @} */ /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET /** * @} */ /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET #if defined(STM32WB) #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED #define QSPI_IRQHandler QUADSPI_IRQHandler #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET #if defined(STM32H7) #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE /* alias define maintained for legacy */ #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED #if defined(STM32L1) #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #endif /* STM32L1 */ #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED #define Sdmmc1ClockSelection SdioClockSelection #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE #endif #if defined(STM32F7) || defined(STM32L4) #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif #if defined(STM32H7) #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() #endif #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK #define IS_RCC_HCLK_DIV IS_RCC_PCLK #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK #define RCC_IT_HSI14 RCC_IT_HSI14RDY #define RCC_IT_CSSLSE RCC_IT_LSECSS #define RCC_IT_CSSHSE RCC_IT_CSS #define RCC_PLLMUL_3 RCC_PLL_MUL3 #define RCC_PLLMUL_4 RCC_PLL_MUL4 #define RCC_PLLMUL_6 RCC_PLL_MUL6 #define RCC_PLLMUL_8 RCC_PLL_MUL8 #define RCC_PLLMUL_12 RCC_PLL_MUL12 #define RCC_PLLMUL_16 RCC_PLL_MUL16 #define RCC_PLLMUL_24 RCC_PLL_MUL24 #define RCC_PLLMUL_32 RCC_PLL_MUL32 #define RCC_PLLMUL_48 RCC_PLL_MUL48 #define RCC_PLLDIV_2 RCC_PLL_DIV2 #define RCC_PLLDIV_3 RCC_PLL_DIV3 #define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG #define RCC_MCO_NODIV RCC_MCODIV_1 #define RCC_MCO_DIV1 RCC_MCODIV_1 #define RCC_MCO_DIV2 RCC_MCODIV_2 #define RCC_MCO_DIV4 RCC_MCODIV_4 #define RCC_MCO_DIV8 RCC_MCODIV_8 #define RCC_MCO_DIV16 RCC_MCODIV_16 #define RCC_MCO_DIV32 RCC_MCODIV_32 #define RCC_MCO_DIV64 RCC_MCODIV_64 #define RCC_MCO_DIV128 RCC_MCODIV_128 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 #define HSION_BitNumber RCC_HSION_BIT_NUMBER #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER #define LSION_BitNumber RCC_LSION_BIT_NUMBER #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE #define CR_HSION_BB RCC_CR_HSION_BB #define CR_CSSON_BB RCC_CR_CSSON_BB #define CR_PLLON_BB RCC_CR_PLLON_BB #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB #define CR_MSION_BB RCC_CR_MSION_BB #define CSR_LSION_BB RCC_CSR_LSION_BB #define CSR_LSEON_BB RCC_CSR_LSEON_BB #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB #define CR_HSEON_BB RCC_CR_HSEON_BB #define CSR_RMVF_BB RCC_CSR_RMVF_BB #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 /** * @} */ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT #if defined (STM32F1) #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE /** * @} */ /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn #define SDMMC1_IRQHandler SDIO_IRQHandler #endif #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif #if defined(STM32H7) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback #endif /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose * @{ */ #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED /** * @} */ /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SPI_1LINE_TX SPI_1LINE_TX #define __HAL_SPI_1LINE_RX SPI_1LINE_RX #define __HAL_SPI_RESET_CRC SPI_RESET_CRC /** * @} */ /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose * @{ */ #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT #define __USART_ENABLE __HAL_USART_ENABLE #define __USART_DISABLE __HAL_USART_DISABLE #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE /** * @} */ /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose * @{ */ #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo /** * @} */ /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 /** * @} */ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** * @} */ /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose * @{ */ #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE #define SAI_STREOMODE SAI_STEREOMODE #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA #endif /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose * @{ */ #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} */ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32L4) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE #endif /** * @} */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32_HAL_LEGACY */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal.h * @author MCD Application Team * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_H #define __STM32F3xx_HAL_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_conf.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup HAL * @{ */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup HAL_Private_Macros * @{ */ #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) /** * @} */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ typedef enum { HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ } HAL_TickFreqTypeDef; /** * @} */ /** * @} */ /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region * @brief SYSCFG registers bit address in the alias region * @{ */ /* ------------ SYSCFG registers bit address in the alias region -------------*/ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) /* --- CFGR2 Register ---*/ /* Alias word address of BYP_ADDR_PAR bit */ #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U) #define BYPADDRPAR_BitNumber 0x04U #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U)) /** * @} */ #if defined(SYSCFG_CFGR1_DMA_RMP) /** @defgroup HAL_DMA_Remapping HAL DMA Remapping * Elements values convention: 0xXXYYYYYY * - YYYYYY : Position in the register * - XX : Register index * - 00: CFGR1 register in SYSCFG * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices) * @{ */ #define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */ #define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */ #define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */ #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */ #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices) 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */ #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only) 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */ #if defined(SYSCFG_CFGR3_DMA_RMP) #if !defined(HAL_REMAP_CFGR3_MASK) #define HAL_REMAP_CFGR3_MASK (0x01000000U) #endif #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) 11: Map on DMA1 channel 2 */ #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) 01: Map on DMA1 channel 4 */ #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only) 10: Map on DMA1 channel 6 */ #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) 11: Map on DMA1 channel 3 */ #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) 01: Map on DMA1 channel 5 */ #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only) 10: Map on DMA1 channel 7 */ #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) 11: Map on DMA1 channel 7 */ #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) 01: Map on DMA1 channel 3 */ #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only) 10: Map on DMA1 channel 5 */ #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) 11: Map on DMA1 channel 6 */ #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) 01: Map on DMA1 channel 2 */ #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only) 10: Map on DMA1 channel 4 */ #define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap x0: No remap (ADC2 on DMA2) 10: Map on DMA1 channel 2 */ #define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap 11: Map on DMA1 channel 4 */ #endif /* SYSCFG_CFGR3_DMA_RMP */ #if defined(SYSCFG_CFGR3_DMA_RMP) #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \ (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \ (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \ (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \ (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \ (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \ (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4)) #else #define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \ (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \ (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \ (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \ (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \ (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \ (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5)) #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/ /** * @} */ #endif /* SYSCFG_CFGR1_DMA_RMP */ /** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping * Elements values convention: 0xXXYYYYYY * - YYYYYY : Position in the register * - XX : Register index * - 00: CFGR1 register in SYSCFG * - 01: CFGR3 register in SYSCFG * @{ */ #define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices) 0: No remap (DAC trigger is TIM8_TRGO) 1: Remap (DAC trigger is TIM3_TRGO) */ #define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap 0: No remap 1: Remap (TIM1_TRG3 = TIM17_OC) */ #if defined(SYSCFG_CFGR3_TRIGGER_RMP) #if !defined(HAL_REMAP_CFGR3_MASK) #define HAL_REMAP_CFGR3_MASK (0x01000000U) #endif #define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap 0: Remap (DAC trigger is TIM15_TRGO) 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */ #define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap 0: No remap 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */ #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \ (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \ (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5)) #else #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \ (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3)) #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ /** * @} */ #if defined (STM32F302xE) /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping * @{ */ #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2 0: No remap (TIM1_CC3) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3 0: No remap (TIM2_CC2) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5 0: No remap (TIM4_CC4) 1: Remap (TIM20_CC1) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13 0: No remap (TIM6_TRGO) 1: Remap (TIM20_CC2) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15 0: No remap (TIM3_CC4) 1: Remap (TIM20_CC3) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3 0: No remap (TIM2_CC1) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 0: No remap (EXTI line 15) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 0: No remap (TIM3_CC1) 1: Remap (TIM20_CC4) */ #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13)) /** * @} */ #endif /* STM32F302xE */ #if defined (STM32F303xE) || defined (STM32F398xx) /** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping * @{ */ #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2 0: No remap (TIM1_CC3) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3 0: No remap (TIM2_CC2) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5 0: No remap (TIM4_CC4) 1: Remap (TIM20_CC1) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13 0: No remap (TIM6_TRGO) 1: Remap (TIM20_CC2) */ #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15 0: No remap (TIM3_CC4) 1: Remap (TIM20_CC3) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3 0: No remap (TIM2_CC1) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6 0: No remap (EXTI line 15) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13 0: No remap (TIM3_CC1) 1: Remap (TIM20_CC4) */ #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5 0: No remap (EXTI line 2) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6 0: No remap (TIM4_CC1) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15 0: No remap (TIM2_CC1) 1: Remap (TIM20_CC1) */ #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5 0: No remap (TIM4_CC3) 1: Remap (TIM20_TRGO) */ #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11 0: No remap (TIM1_CC3) 1: Remap (TIM20_TRGO2) */ #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14 0: No remap (TIM7_TRGO) 1: Remap (TIM20_CC2) */ #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \ (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14)) /** * @} */ #endif /* STM32F303xE || STM32F398xx */ /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO * @{ */ /** @brief Fast-mode Plus driving capability on a specific GPIO */ #if defined(SYSCFG_CFGR1_I2C_PB6_FMP) #define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */ #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */ #if defined(SYSCFG_CFGR1_I2C_PB7_FMP) #define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */ #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */ #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) #define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */ #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) #define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */ #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ /** * @} */ #if defined(SYSCFG_RCR_PAGE0) /* CCM-SRAM defined */ /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection * @{ */ #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */ #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */ #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */ #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */ #if defined(SYSCFG_RCR_PAGE4) /* More than 4KB CCM-SRAM defined */ #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */ #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */ #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */ #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */ #endif /* SYSCFG_RCR_PAGE4 */ #if defined(SYSCFG_RCR_PAGE8) #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */ #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */ #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */ #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */ #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */ #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */ #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */ #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */ #endif /* SYSCFG_RCR_PAGE8 */ #if defined(SYSCFG_RCR_PAGE8) #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU)) #elif defined(SYSCFG_RCR_PAGE4) #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU)) #else #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU)) #endif /* SYSCFG_RCR_PAGE8 */ /** * @} */ #endif /* SYSCFG_RCR_PAGE0 */ /** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts * @{ */ #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */ #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */ #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */ #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */ #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */ #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */ #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \ (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5)) /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ */ /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode * @{ */ #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP) #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP) #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP)) #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */ #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */ #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ /** * @} */ /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode * @{ */ #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP) #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP)) #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP) #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP)) #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */ #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP) #define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)) #define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)) #endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */ /** * @} */ /** @defgroup Memory_Mapping_Selection Memory Mapping Selection * @{ */ #if defined(SYSCFG_CFGR1_MEM_MODE) /** @brief Main Flash memory mapped at 0x00000000 */ #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) #endif /* SYSCFG_CFGR1_MEM_MODE */ #if defined(SYSCFG_CFGR1_MEM_MODE_0) /** @brief System Flash memory mapped at 0x00000000 */ #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ }while(0U) #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) /** @brief Embedded SRAM mapped at 0x00000000 */ #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ }while(0U) #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ #if defined(SYSCFG_CFGR1_MEM_MODE_2) #define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \ }while(0U) #endif /* SYSCFG_CFGR1_MEM_MODE_2 */ /** * @} */ /** @defgroup Encoder_Mode Encoder Mode * @{ */ #if defined(SYSCFG_CFGR1_ENCODER_MODE) /** @brief No Encoder mode */ #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE)) #endif /* SYSCFG_CFGR1_ENCODER_MODE */ #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \ }while(0U) #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */ #if defined(SYSCFG_CFGR1_ENCODER_MODE_1) /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \ }while(0U) #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */ #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1) /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices) */ #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \ SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \ }while(0U) #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */ /** * @} */ /** @defgroup DMA_Remap_Enable DMA Remap Enable * @{ */ #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP) /** @brief DMA remapping enable/disable macros * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping */ #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \ }while(0U) #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \ }while(0U) #elif defined(SYSCFG_CFGR1_DMA_RMP) /** @brief DMA remapping enable/disable macros * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping */ #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ SYSCFG->CFGR1 |= (__DMA_REMAP__); \ }while(0U) #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \ SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ }while(0U) #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */ /** * @} */ /** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO * @{ */ /** @brief Fast-mode Plus driving capability enable/disable macros * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values. * That you can find above these macros. */ #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0U) #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0U) /** * @} */ /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable * @{ */ /** @brief SYSCFG interrupt enable/disable macros * @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts */ #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ SYSCFG->CFGR1 |= (__INTERRUPT__); \ }while(0U) #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \ SYSCFG->CFGR1 &= ~(__INTERRUPT__); \ }while(0U) /** * @} */ #if defined(SYSCFG_CFGR1_USB_IT_RMP) /** @defgroup USB_Interrupt_Remap USB Interrupt Remap * @{ */ /** @brief USB interrupt remapping enable/disable macros */ #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP)) #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP)) /** * @} */ #endif /* SYSCFG_CFGR1_USB_IT_RMP */ #if defined(SYSCFG_CFGR1_VBAT) /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable * @{ */ /** @brief SYSCFG interrupt enable/disable macros */ #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT)) #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT)) /** * @} */ #endif /* SYSCFG_CFGR1_VBAT */ #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable * @{ */ /** @brief SYSCFG Break Lockup lock * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input * @note The selected configuration is locked and can be unlocked by system reset */ #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ }while(0U) /** * @} */ #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ #if defined(SYSCFG_CFGR2_PVD_LOCK) /** @defgroup PVD_Lock_Enable PVD Lock * @{ */ /** @brief SYSCFG Break PVD lock * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register * @note The selected configuration is locked and can be unlocked by system reset */ #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ }while(0U) /** * @} */ #endif /* SYSCFG_CFGR2_PVD_LOCK */ #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) /** @defgroup SRAM_Parity_Lock SRAM Parity Lock * @{ */ /** @brief SYSCFG Break SRAM PARITY lock * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 * @note The selected configuration is locked and can be unlocked by system reset */ #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ }while(0U) /** * @} */ #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable * @{ */ #if defined(SYSCFG_CFGR3_TRIGGER_RMP) /** @brief Trigger remapping enable/disable macros * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping */ #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \ }while(0U) #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \ (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \ }while(0U) #else /** @brief Trigger remapping enable/disable macros * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping */ #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \ }while(0U) #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \ (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \ }while(0U) #endif /* SYSCFG_CFGR3_TRIGGER_RMP */ /** * @} */ #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable * @{ */ /** @brief ADC trigger remapping enable/disable macros * @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping */ #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \ }while(0U) #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \ (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \ }while(0U) /** * @} */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR) /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable * @{ */ /** * @brief Parity check on RAM disable macro * @note Disabling the parity check on RAM locks the configuration bit. * To re-enable the parity check on RAM perform a system reset. */ #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U) /** * @} */ #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */ #if defined(SYSCFG_RCR_PAGE0) /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable * @{ */ /** @brief CCM RAM page write protection enable macro * @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection * @note write protection can only be disabled by a system reset */ #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \ SYSCFG->RCR |= (__PAGE_WP__); \ }while(0U) /** * @} */ #endif /* SYSCFG_RCR_PAGE0 */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup HAL_Private_Macros HAL Private Macros * @{ */ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ ((FREQ) == HAL_TICK_FREQ_100HZ) || \ ((FREQ) == HAL_TICK_FREQ_1KHZ)) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions HAL Exported Functions * @{ */ /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); /** * @} */ /* Exported variables ---------------------------------------------------------*/ /** @addtogroup HAL_Exported_Variables * @{ */ extern __IO uint32_t uwTick; extern uint32_t uwTickPrio; extern HAL_TickFreqTypeDef uwTickFreq; /** * @} */ /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @{ */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); HAL_TickFreqTypeDef HAL_GetTickFreq(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); uint32_t HAL_GetUIDw0(void); uint32_t HAL_GetUIDw1(void); uint32_t HAL_GetUIDw2(void); void HAL_DBGMCU_EnableDBGSleepMode(void); void HAL_DBGMCU_DisableDBGSleepMode(void); void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_adc.h * @author MCD Application Team * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_ADC_H #define __STM32F3xx_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /* Include ADC HAL Extended module */ /* (include on top of file since ADC structures are defined in extended file) */ #include "stm32f3xx_hal_adc_ex.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ /** * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. * For example: * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " */ /* States of ADC global scope */ #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ /* States of ADC errors */ #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ /* States of ADC group regular */ #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on, multimode ADC master control) */ #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of analog watchdog 2 */ #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master ( */ /** * @brief ADC handle Structure definition */ typedef struct __ADC_HandleTypeDef { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC required parameters */ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ HAL_LockTypeDef Lock; /*!< ADC locking object */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ }ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief HAL ADC Callback ID enumeration definition */ typedef enum { HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ } HAL_ADC_CallbackIDTypeDef; /** * @brief HAL ADC Callback pointer definition */ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /** @defgroup ADC_Exported_Macro ADC Exported Macros * @{ */ /** @brief Reset ADC handle state * @param __HANDLE__ ADC handle * @retval None */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ do{ \ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) #endif /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_Exported_Functions ADC Exported Functions * @{ */ /** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions **********************************/ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); /* Non-blocking mode: DMA */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); /** * @} */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions * @brief ADC Peripheral State functions * @{ */ /* Peripheral State functions *************************************************/ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /*__STM32F3xx_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_adc_ex.h * @author MCD Application Team * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_ADC_EX_H #define __STM32F3xx_ADC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup ADCEx ADCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADCEx Exported Types * @{ */ struct __ADC_HandleTypeDef; #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Structure definition of ADC initialization and regular group * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign, * ScanConvMode, EOCSelection, LowPowerAutoWait. * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun. * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled * - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group. * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). */ typedef struct { uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler. The clock is common for all the ADCs. This parameter can be a value of @ref ADCEx_ClockPrescaler Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level. Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */ uint32_t Resolution; /*!< Configures the ADC resolution. This parameter can be a value of @ref ADCEx_Resolution */ uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0U) (default setting) or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4U, if offset enabled: MSB on register bit 14 and LSB on register bit 3U). See reference manual for alignments with other resolutions. This parameter can be a value of @ref ADCEx_Data_align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of @ref ADCEx_Scan_mode */ uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. This parameter can be a value of @ref ADCEx_EOCSelection. */ FunctionalState LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary. New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software. This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. This parameter can be a value of @ref ADCEx_External_trigger_source_Regular Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available) */ uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */ FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) or in Continuous mode (DMA transfer unlimited, whatever number of conversions). Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved. This parameter is for regular group only. This parameter can be a value of @ref ADCEx_Overrun Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear). Note: Error reporting in function of conversion mode: - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */ }ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. This parameter can be a value of @ref ADCEx_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. This parameter can be a value of @ref ADCEx_regular_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADCEx_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */ uint32_t SingleDiff; /*!< Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of @ref ADCEx_SingleDifferential Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */ uint32_t OffsetNumber; /*!< Selects the offset number This parameter can be a value of @ref ADCEx_OffsetNumber Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */ uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels. Offset value must be a positive number. Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ }ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC injected group and ADC channel for injected group * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t InjectedChannel; /*!< Configure the ADC injected channel This parameter can be a value of @ref ADCEx_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< The rank in the regular group sequencer This parameter must be a value of @ref ADCEx_injected_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADCEx_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of @ref ADCEx_SingleDifferential Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: Channels 1 to 14 are available in differential mode. Channels 15U, 16U, 17U, 18 can be used only in single-ended mode. Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number This parameter can be a value of @ref ADCEx_OffsetNumber Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. This parameter can be a value of @ref ADCEx_External_trigger_source_Injected Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ }ADC_InjectionConfTypeDef; /** * @brief ADC Injection Configuration */ typedef struct { uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ }ADC_InjectionConfigTypeDef; /** * @brief Structure definition of ADC analog watchdog * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups. */ typedef struct { uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog to apply to the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of @ref ADCEx_analog_watchdog_number. */ uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group. For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter. This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel. Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of @ref ADCEx_channels. */ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ }ADC_AnalogWDGConfTypeDef; /** * @brief Structure definition of ADC multimode * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'DMAAccessMode') * - For parameter 'DMAAccessMode': ADC enabled without conversion on going on regular group. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. This parameter can be a value of @ref ADCEx_Common_mode */ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multi ADC mode: selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun. Therefore, it is recommended to disable multimode DMA access: each ADC uses its own DMA channel. Refer to device errata sheet for more details. */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits */ }ADC_MultiModeTypeDef; #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Structure definition of ADC and regular group initialization * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode. * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0U) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4U, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3U). This parameter can be a value of @ref ADCEx_Data_align */ uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1U). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1U). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of @ref ADCEx_Scan_mode Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1U) or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the the last conversion of the sequence. All previous conversions would be overwritten by the last one. Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */ FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */ }ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. */ typedef struct { uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. This parameter can be a value of @ref ADCEx_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ uint32_t Rank; /*!< Specifies the rank in the regular group sequencer This parameter can be a value of @ref ADCEx_regular_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADCEx_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */ }ADC_ChannelConfTypeDef; /** * @brief ADC Configuration injected Channel structure definition * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv') * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group. */ typedef struct { uint32_t InjectedChannel; /*!< Selection of ADC channel to configure This parameter can be a value of @ref ADCEx_channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Rank in the injected group sequencer This parameter must be a value of @ref ADCEx_injected_rank Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of @ref ADCEx_sampling_times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */ uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12U, 10U, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFU, 0x3FFU, 0xFF or 0x3F respectively. */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of @ref ADCEx_External_trigger_source_Injected Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ }ADC_InjectionConfTypeDef; /** * @brief ADC Configuration analog watchdog definition * @note The setting of these parameters with function is conditioned to ADC state. * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. */ typedef struct { uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */ uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) This parameter can be a value of @ref ADCEx_channels. */ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0U */ }ADC_AnalogWDGConfTypeDef; #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants * @{ */ /** @defgroup ADCEx_Error_Code ADC Extended Error Code * @{ */ #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, enable/disable, erroneous state */ #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler * @{ */ #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated PLL */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */ #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2U */ #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4U */ #endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */ #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) /** * @} */ /** @defgroup ADCEx_Resolution ADC Extended Resolution * @{ */ #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */ #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */ #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */ /** * @} */ /** @defgroup ADCEx_Data_align ADC Extended Data Alignment * @{ */ #define ADC_DATAALIGN_RIGHT (0x00000000U) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN) /** * @} */ /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode * @{ */ #define ADC_SCAN_DISABLE (0x00000000U) #define ADC_SCAN_ENABLE (0x00000001U) /** * @} */ /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /** * @} */ /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group * @{ */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) /*!< List of external triggers with generic trigger name, independently of */ /* ADC target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /*!< External triggers of regular group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 /*!< External triggers of regular group for ADC3&ADC4 only */ #define ADC_EXTERNALTRIGCONV_T2_CC1 ADC3_4_EXTERNALTRIG_T2_CC1 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_4_EXTERNALTRIG_T2_CC3 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_4_EXTERNALTRIG_T3_CC1 #define ADC_EXTERNALTRIGCONV_T4_CC1 ADC3_4_EXTERNALTRIG_T4_CC1 #define ADC_EXTERNALTRIGCONV_T7_TRGO ADC3_4_EXTERNALTRIG_T7_TRGO #define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_4_EXTERNALTRIG_T8_CC1 #define ADC_EXTERNALTRIGCONV_EXT_IT2 ADC3_4_EXTERNALTRIG_EXT_IT2 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 */ /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ /* ADC3_4 by driver when needed. */ #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO #define ADC_SOFTWARE_START (0x00000001U) #if defined(STM32F303xE) || defined(STM32F398xx) /* ADC external triggers specific to device STM303xE: mask to differentiate */ /* standard triggers from specific timer 20U, needed for reallocation of */ /* triggers common to ADC1&2U/ADC3&4 and to avoid mixing with standard */ /* triggers without remap. */ #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000 /*!< List of external triggers specific to device STM303xE: using Timer20 */ /* with ADC trigger input remap. */ /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ /*!< External triggers of regular group for ADC1&ADC2 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ #define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */ #define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */ /*!< External triggers of regular group for ADC3&ADC4 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ /* None */ /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ /* ADC3_4 by driver when needed. */ #define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15U) */ #define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */ #define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) */ #endif /* STM32F303xE || STM32F398xx */ #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) /*!< List of external triggers with generic trigger name, independently of */ /* ADC target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /*!< External triggers of regular group for ADC1&ADC2 */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 #define ADC_SOFTWARE_START (0x00000001U) #if defined(STM32F302xE) /* ADC external triggers specific to device STM302xE: mask to differentiate */ /* standard triggers from specific timer 20U, needed for reallocation of */ /* triggers common to ADC1&2 and to avoind mixing with standard */ /* triggers without remap. */ #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000 /*!< List of external triggers specific to device STM302xE: using Timer20 */ /* with ADC trigger input remap. */ /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ /*!< External triggers of regular group for ADC1&ADC2 only, specific to */ /* device STM302xE: : using Timer20 with ADC trigger input remap */ #define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13U) */ #define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15U) */ #endif /* STM32F302xE */ #endif /* STM32F302xE || */ /* STM32F302xC */ #if defined(STM32F303x8) || defined(STM32F328xx) /*!< List of external triggers with generic trigger name, independently of */ /* ADC target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /*!< External triggers of regular group for ADC1&ADC2 */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 #define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F303x8 || STM32F328xx */ #if defined(STM32F334x8) /*!< List of external triggers with generic trigger name, independently of */ /* ADC target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /*!< External triggers of regular group for ADC1&ADC2 */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO #define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1 #define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11 #define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* List of external triggers with generic trigger name, sorted by trigger */ /* name: */ /* External triggers of regular group for ADC1 */ #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO #define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} */ /** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion * @{ */ #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /** * @} */ /** @defgroup ADCEx_Overrun ADC Extended overrun * @{ */ #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) /*!< Default setting, to be used for compatibility with other STM32 devices */ #define ADC_OVR_DATA_PRESERVED (0x00000001U) /** * @} */ /** @defgroup ADCEx_channels ADC Extended Channels * @{ */ /* Note: Depending on devices, some channels may not be available on package */ /* pins. Refer to device datasheet for channels availability. */ #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1)) #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2)) #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3)) #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1)) #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2)) #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4)) #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0)) #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1)) /* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */ #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_15 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 #define ADC_CHANNEL_VBAT ADC_CHANNEL_17 /* Note: Vopamp2/3U/4 internal channels available on ADC2/3U/4 respectively */ #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17 #define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17 /* Note: VrefInt internal channels available on all ADCs, but only */ /* one ADC is allowed to be connected to VrefInt at the same time. */ #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_18) /** * @} */ /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times * @{ */ #define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */ #define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 19.5 ADC clock cycles */ #define ADC_SAMPLETIME_61CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 61.5 ADC clock cycles */ #define ADC_SAMPLETIME_181CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 181.5 ADC clock cycles */ #define ADC_SAMPLETIME_601CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 601.5 ADC clock cycles */ /** * @} */ /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode * @{ */ #define ADC_SINGLE_ENDED (0x00000000U) #define ADC_DIFFERENTIAL_ENDED (0x00000001U) /** * @} */ /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number * @{ */ #define ADC_OFFSET_NONE (0x00U) #define ADC_OFFSET_1 (0x01U) #define ADC_OFFSET_2 (0x02U) #define ADC_OFFSET_3 (0x03U) #define ADC_OFFSET_4 (0x04U) /** * @} */ /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group * @{ */ #define ADC_REGULAR_RANK_1 (0x00000001U) #define ADC_REGULAR_RANK_2 (0x00000002U) #define ADC_REGULAR_RANK_3 (0x00000003U) #define ADC_REGULAR_RANK_4 (0x00000004U) #define ADC_REGULAR_RANK_5 (0x00000005U) #define ADC_REGULAR_RANK_6 (0x00000006U) #define ADC_REGULAR_RANK_7 (0x00000007U) #define ADC_REGULAR_RANK_8 (0x00000008U) #define ADC_REGULAR_RANK_9 (0x00000009U) #define ADC_REGULAR_RANK_10 (0x0000000AU) #define ADC_REGULAR_RANK_11 (0x0000000BU) #define ADC_REGULAR_RANK_12 (0x0000000CU) #define ADC_REGULAR_RANK_13 (0x0000000DU) #define ADC_REGULAR_RANK_14 (0x0000000EU) #define ADC_REGULAR_RANK_15 (0x0000000FU) #define ADC_REGULAR_RANK_16 (0x00000010U) /** * @} */ /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank * @{ */ #define ADC_INJECTED_RANK_1 (0x00000001U) #define ADC_INJECTED_RANK_2 (0x00000002U) #define ADC_INJECTED_RANK_3 (0x00000003U) #define ADC_INJECTED_RANK_4 (0x00000004U) /** * @} */ /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /** * @} */ /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group * @{ */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) /* List of external triggers with generic trigger name, independently of ADC */ /* target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /* External triggers of injected group for ADC1&ADC2 only */ #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 /* External triggers of injected group for ADC3&ADC4 only */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC3 ADC3_4_EXTERNALTRIGINJEC_T1_CC3 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_4_EXTERNALTRIGINJEC_T4_CC3 #define ADC_EXTERNALTRIGINJECCONV_T4_CC4 ADC3_4_EXTERNALTRIGINJEC_T4_CC4 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC3_4_EXTERNALTRIGINJEC_T7_TRGO #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_4_EXTERNALTRIGINJEC_T8_CC2 /* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */ /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ /* ADC3_4 by driver when needed. */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO #define ADC_INJECTED_SOFTWARE_START (0x00000001U) #if defined(STM32F303xE) || defined(STM32F398xx) /*!< List of external triggers specific to device STM303xE: using Timer20 */ /* with ADC trigger input remap. */ /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ /*!< External triggers of injected group for ADC1&ADC2 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ #define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */ /*!< External triggers of injected group for ADC3&ADC4 only, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ #define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14U) */ /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */ /* device STM303xE: : using Timer20 with ADC trigger input remap */ /* Note: Triggers affected to group ADC1_2 by default, redirected to group */ /* ADC3_4 by driver when needed. */ #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */ #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */ /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11U) */ #endif /* STM32F303xE || STM32F398xx */ #if defined(STM32F303xC) || defined(STM32F358xx) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \ \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F303xE || STM32F398xx */ #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) /*!< List of external triggers with generic trigger name, independently of */ /* ADC target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /* External triggers of injected group for ADC1&ADC2 */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) #if defined(STM32F302xE) /*!< List of external triggers specific to device STM302xE: using Timer20 */ /* with ADC trigger input remap. */ /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */ /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */ /*!< External triggers of injected group for ADC1&ADC2 only, specific to */ /* device STM302xE: : using Timer20 with ADC trigger input remap */ #define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13U) */ #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */ #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */ #endif /* STM32F302xE */ #endif /* STM32F302xE || */ /* STM32F302xC */ #if defined(STM32F303x8) || defined(STM32F328xx) /*!< List of external triggers with generic trigger name, independently of */ /* ADC target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /* External triggers of injected group for ADC1&ADC2 */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) #endif /* STM32F303x8 || STM32F328xx */ #if defined(STM32F334x8) /*!< List of external triggers with generic trigger name, independently of */ /* ADC target (caution: applies to other ADCs sharing the same common group), */ /* sorted by trigger name: */ /* External triggers of injected group for ADC1&ADC2 */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* List of external triggers with generic trigger name, sorted by trigger */ /* name: */ /* External triggers of injected group for ADC1 */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15 #define ADC_INJECTED_SOFTWARE_START (0x00000001U) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} */ /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode * @{ */ #define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000U)) #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0)) #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1)) #define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0)) #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_0)) #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1)) #define ADC_DUALMODE_INTERL ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0)) #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_3 | ADC12_CCR_MULTI_0)) /** * @} */ /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode * @{ */ #define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /*!< DMA multimode disabled: each ADC will use its own DMA channel */ #define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ #define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** * @} */ /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases * @{ */ #define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000U)) #define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0)) #define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1)) #define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0)) #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC12_CCR_DELAY_2)) #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_0)) #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1)) #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0)) #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC12_CCR_DELAY_3)) #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_0)) #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1)) #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0)) /** * @} */ /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection * @{ */ #define ADC_ANALOGWATCHDOG_1 (0x00000001U) #define ADC_ANALOGWATCHDOG_2 (0x00000002U) #define ADC_ANALOGWATCHDOG_3 (0x00000003U) /** * @} */ /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode * @{ */ #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /** * @} */ /** @defgroup ADC_conversion_group ADC Conversion Group * @{ */ #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /** * @} */ /** @defgroup ADCEx_Event_type ADC Extended Event Type * @{ */ #define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) */ #define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) */ #define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) */ #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ #define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ #define ADC_AWD_EVENT ADC_AWD1_EVENT /* ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */ /** * @} */ /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition * @{ */ #define ADC_IT_RDY ADC_IER_RDY /*!< ADC Ready (ADRDY) interrupt source */ #define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of Sampling interrupt source */ #define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of Regular Conversion interrupt source */ #define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of Regular sequence of Conversions interrupt source */ #define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ #define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of Injected Conversion interrupt source */ #define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of Injected sequence of Conversions interrupt source */ #define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) */ #define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) */ #define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) */ #define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ #define ADC_IT_AWD ADC_IT_AWD1 /* ADC Analog watchdog 1 interrupt source: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */ /** * @} */ /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition * @{ */ #define ADC_FLAG_RDY ADC_ISR_ADRD /*!< ADC Ready (ADRDY) flag */ #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) */ #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) */ #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) */ #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ #define ADC_FLAG_AWD ADC_FLAG_AWD1 /* ADC Analog watchdog 1 flag: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */ /** * @} */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup ADCEx_Data_align ADC Extended Data Alignment * @{ */ #define ADC_DATAALIGN_RIGHT (0x00000000U) #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} */ /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode * @{ */ #define ADC_SCAN_DISABLE (0x00000000U) #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /** * @} */ /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) /** * @} */ /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group * @{ */ /* List of external triggers with generic trigger name, sorted by trigger */ /* name: */ /* External triggers of regular group for ADC1 */ #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4 #define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO #define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3 #define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 #define ADC_SOFTWARE_START ADC_SWSTART /** * @} */ /** @defgroup ADCEx_channels ADC Extended Channels * @{ */ /* Note: Depending on devices, some channels may not be available on package */ /* pins. Refer to device datasheet for channels availability. */ #define ADC_CHANNEL_0 (0x00000000U) #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2)) #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3)) #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2)) #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4)) #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1)) #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 #define ADC_CHANNEL_VBAT ADC_CHANNEL_18 /** * @} */ /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times * @{ */ #define ADC_SAMPLETIME_1CYCLE_5 (0x00000000U) /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */ #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */ #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */ #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0) /*!< Sampling time 239.5 ADC clock cycles */ /** * @} */ /** @defgroup ADCEx_regular_rank ADC Extended rank into regular group * @{ */ #define ADC_REGULAR_RANK_1 (0x00000001U) #define ADC_REGULAR_RANK_2 (0x00000002U) #define ADC_REGULAR_RANK_3 (0x00000003U) #define ADC_REGULAR_RANK_4 (0x00000004U) #define ADC_REGULAR_RANK_5 (0x00000005U) #define ADC_REGULAR_RANK_6 (0x00000006U) #define ADC_REGULAR_RANK_7 (0x00000007U) #define ADC_REGULAR_RANK_8 (0x00000008U) #define ADC_REGULAR_RANK_9 (0x00000009U) #define ADC_REGULAR_RANK_10 (0x0000000AU) #define ADC_REGULAR_RANK_11 (0x0000000BU) #define ADC_REGULAR_RANK_12 (0x0000000CU) #define ADC_REGULAR_RANK_13 (0x0000000DU) #define ADC_REGULAR_RANK_14 (0x0000000EU) #define ADC_REGULAR_RANK_15 (0x0000000FU) #define ADC_REGULAR_RANK_16 (0x00000010U) /** * @} */ /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank * @{ */ #define ADC_INJECTED_RANK_1 (0x00000001U) #define ADC_INJECTED_RANK_2 (0x00000002U) #define ADC_INJECTED_RANK_3 (0x00000003U) #define ADC_INJECTED_RANK_4 (0x00000004U) /** * @} */ /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) /** * @} */ /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group * @{ */ /* External triggers for injected groups of ADC1 */ #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO #define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1 #define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 #define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART /** * @} */ /** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode * @{ */ #define ADC_ANALOGWATCHDOG_NONE (0x00000000U) #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) /** * @} */ /** @defgroup ADC_conversion_group ADC Conversion Group * @{ */ #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) /** * @} */ /** @defgroup ADCEx_Event_type ADC Extended Event Type * @{ */ #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ /** * @} */ /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition * @{ */ #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ /** * @} */ /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition * @{ */ #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ /** * @} */ #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group * @{ */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) /* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1 & ADC2 */ #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) /* External triggers of regular group for ADC3 & ADC4 */ #define ADC3_4_EXTERNALTRIG_T3_CC1 (0x00000000U) #define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC3_4_EXTERNALTRIG_T8_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) #define ADC3_4_EXTERNALTRIG_EXT_IT2 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC3_4_EXTERNALTRIG_T4_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC3_4_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC3_4_EXTERNALTRIG_T8_TRGO2 ((uint32_t)ADC_CFGR_EXTSEL_3) #define ADC3_4_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) #define ADC3_4_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) #define ADC3_4_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC3_4_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) #define ADC3_4_EXTERNALTRIG_T7_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC3_4_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC3_4_EXTERNALTRIG_T2_CC1 ((uint32_t)ADC_CFGR_EXTSEL) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) /* List of external triggers of common group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #endif /* STM32F302xE || */ /* STM32F302xC */ #if defined(STM32F303x8) || defined(STM32F328xx) /* List of external triggers of common group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) #endif /* STM32F303x8 || STM32F328xx */ #if defined(STM32F334x8) /* List of external triggers of common group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_2_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_HRTIM_TRG1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_HRTIM_TRG3 ((uint32_t) ADC_CFGR_EXTSEL_3) #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* List of external triggers of regular group for ADC1: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_EXTERNALTRIG_T1_CC1 (0x00000000U) #define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) #define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) #define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) #define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) #define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) #define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) #define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) #define ADC_SOFTWARE_START (0x00000001U) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group * @{ */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) /* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers for injected groups of ADC1 & ADC2 */ #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /* External triggers for injected groups of ADC3 & ADC4 */ /* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event). */ /* JEXT2 is the main trigger, JEXT5 could be redirected to another */ /* in future devices. */ /* However, this channel is implemented with a SW offset of 0x10000 for */ /* differentiation between similar triggers of common groups ADC1&ADC2, */ /* ADC3&ADC4 (Differentiation processed into macro */ /* ADC_JSQR_JEXTSEL_SET) */ #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000U) #define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) #if defined(STM32F303xE) || defined(STM32F398xx) #define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #endif /* STM32F303xE || STM32F398xx */ #define ADC3_4_EXTERNALTRIGINJEC_T4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) #define ADC3_4_EXTERNALTRIGINJEC_T1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) #define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) /* List of external triggers of group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) #endif /* STM32F302xE || */ /* STM32F302xC */ #if defined(STM32F303x8) || defined(STM32F328xx) /* List of external triggers of group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) #endif /* STM32F303x8 || STM32F328xx */ #if defined(STM32F334x8) /* List of external triggers of group ADC1&ADC2: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* List of external triggers of injected group for ADC1: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ #define ADC1_EXTERNALTRIGINJEC_T1_TRGO (0x00000000U) #define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) #define ADC1_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) #define ADC1_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) #define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) #define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) #define ADC1_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} */ #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ ADC_FLAG_JQOVF) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group * @{ */ /* List of external triggers of regular group for ADC1: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1 */ #define ADC_EXTERNALTRIG_T19_TRGO (0x00000000U) #define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0) #define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1) #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2) #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) #define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) /** * @} */ /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group * @{ */ /* List of external triggers of injected group for ADC1: */ /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of injected group for ADC1 */ #define ADC_EXTERNALTRIGINJEC_T19_CC1 ( 0x00000000U) #define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0) #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1) #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2) #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) #define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) /** * @} */ /** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels * @{ */ #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \ ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \ ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \ ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 ) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \ ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \ ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \ ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 ) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \ ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \ ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0) #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS (0x00000000U) #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS (0x00000000U) #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD ) /** * @} */ #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros * @{ */ /* Macro for internal HAL driver usage, and possibly can be used into code of */ /* final user. */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Enable the ADC peripheral * @param __HANDLE__ ADC handle * @note ADC enable requires a delay for ADC stabilization time * (refer to device datasheet, parameter tSTAB) * @note On STM32F3 devices, some hardware constraints must be strictly * respected before using this macro: * - ADC internal voltage regulator must be preliminarily enabled. * This is performed by function HAL_ADC_Init(). * - ADC state requirements: ADC must be disabled, no conversion on * going, no calibration on going. * These checks are performed by functions HAL_ADC_start_xxx(). * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) \ (SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADEN)) /** * @brief Disable the ADC peripheral * @param __HANDLE__ ADC handle * @note On STM32F3 devices, some hardware constraints must be strictly * respected before using this macro: * - ADC state requirements: ADC must be enabled, no conversion on * going. * These checks are performed by functions HAL_ADC_start_xxx(). * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \ __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ } while(0U) /** * @brief Enable the ADC end of conversion interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source * @arg ADC_IT_OVR: ADC overrun interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ (SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))) /** * @brief Disable the ADC end of conversion interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source * @arg ADC_IT_OVR: ADC overrun interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC interrupt source to check * This parameter can be any combination of the following values: * @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source * @arg ADC_IT_OVR: ADC overrun interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Get the selected ADC's flag status. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag * @arg ADC_FLAG_OVR: ADC overrun flag * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) /** * @brief Clear the ADC's pending flags * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag * @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag * @arg ADC_FLAG_OVR: ADC overrun flag * @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag * @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of */ /* register ISR). */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ (WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__))) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enable the ADC peripheral * @note ADC enable requires a delay for ADC stabilization time * (refer to device datasheet, parameter tSTAB) * @note On STM32F37x devices, if ADC is already enabled this macro trigs * a conversion SW start on regular group. * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) \ (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** * @brief Disable the ADC peripheral * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) \ (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON))) /** @brief Enable the ADC end of conversion interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Disable the ADC end of conversion interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC interrupt source to check * This parameter can be any combination of the following values: * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected ADC's flag status. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the ADC's pending flags * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be any combination of the following values: * @arg ADC_FLAG_STRT: ADC Regular group start flag * @arg ADC_FLAG_JSTRT: ADC Injected group start flag * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag * @arg ADC_FLAG_AWD: ADC Analog watchdog flag * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__))) #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Private macro ------------------------------------------------------------*/ /** @addtogroup ADCEx_Private_Macro ADCEx Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Verification of hardware constraints before ADC can be enabled * @param __HANDLE__ ADC handle * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) */ #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ (( HAL_IS_BIT_CLR((__HANDLE__)->Instance->CR , \ (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | \ ADC_CR_JADSTART |ADC_CR_ADSTART | ADC_CR_ADDIS | \ ADC_CR_ADEN ) ) \ ) ? SET : RESET) /** * @brief Verification of ADC state: enabled or disabled * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ ) ? SET : RESET) /** * @brief Test if conversion trigger of regular group is software start * or external trigger. * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) /** * @brief Test if conversion trigger of injected group is software start * or external trigger. * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) /** * @brief Check if no conversion on going on regular and/or injected groups * @param __HANDLE__ ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ ) ? RESET : SET) /** * @brief Check if no conversion on going on regular group * @param __HANDLE__ ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ ) ? RESET : SET) /** * @brief Check if no conversion on going on injected group * @param __HANDLE__ ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \ ) ? RESET : SET) /** * @brief Returns resolution bits in CFGR1 register: RES[1:0]. * Returned value is among parameters to @ref ADCEx_Resolution. * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES) /** * @brief Simultaneously clears and sets specific bits of the handle State * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Clear ADC error code (set it to error code: "no error") * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Set the ADC's sample time for Channels numbers between 0 and 9. * @param _SAMPLETIME_ Sample time parameter. * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_))) /** * @brief Set the ADC's sample time for Channels numbers between 10 and 18. * @param _SAMPLETIME_ Sample time parameter. * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U))) /** * @brief Set the selected regular Channel rank for rank between 1 and 4. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_))) /** * @brief Set the selected regular Channel rank for rank between 5 and 9. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U))) /** * @brief Set the selected regular Channel rank for rank between 10 and 14. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U))) /** * @brief Set the selected regular Channel rank for rank between 15 and 16. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U))) /** * @brief Set the selected injected Channel rank. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U)) /** * @brief Set the Analog Watchdog 1 channel. * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. * @retval None */ #define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U) /** * @brief Configure the channel number into Analog Watchdog 2 or 3. * @param _CHANNEL_ ADC Channel * @retval None */ #define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_)) /** * @brief Enable automatic conversion of injected group * @param _INJECT_AUTO_CONVERSION_ Injected automatic conversion. * @retval None */ #define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U) /** * @brief Enable ADC injected context queue * @param _INJECT_CONTEXT_QUEUE_MODE_ Injected context queue mode. * @retval None */ #define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U) /** * @brief Enable ADC discontinuous conversion mode for injected group * @param _INJECT_DISCONTINUOUS_MODE_ Injected discontinuous mode. * @retval None */ #define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U) /** * @brief Enable ADC discontinuous conversion mode for regular group * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. * @retval None */ #define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U) /** * @brief Configures the number of discontinuous conversions for regular group. * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions. * @retval None */ #define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U) /** * @brief Enable the ADC auto delay mode. * @param _AUTOWAIT_ Auto delay bit enable or disable. * @retval None */ #define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U) /** * @brief Enable ADC continuous conversion mode. * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U) /** * @brief Enable ADC overrun mode. * @param _OVERRUN_MODE_ Overrun mode. * @retval Overrun bit setting to be programmed into CFGR register */ /* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */ /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00U, to set it */ /* as the default case to be compliant with other STM32 devices. */ #define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \ ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ )? (ADC_CFGR_OVRMOD) : (0x00000000U) \ ) /** * @brief Enable the ADC DMA continuous request. * @param _DMACONTREQ_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U) /** * @brief For devices with 3 ADCs or more: Defines the external trigger source * for regular group according to ADC into common group ADC1&ADC2 or * ADC3&ADC4 (some triggers with same source have different value to * be programmed into ADC EXTSEL bits of CFGR register). * Note: No risk of trigger bits value of common group ADC1&ADC2 * misleading to another trigger at same bits value, because the 3 * exceptions below are circular and do not point to any other trigger * with direct treatment. * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__ ADC handle * @param __EXT_TRIG_CONV__ External trigger selected for regular group. * @retval External trigger to be programmed into EXTSEL bits of CFGR register */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #if defined(STM32F303xC) || defined(STM32F358xx) #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ )? \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \ )? \ (ADC3_4_EXTERNALTRIG_T2_TRGO) \ : \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \ )? \ (ADC3_4_EXTERNALTRIG_T3_TRGO) \ : \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \ )? \ (ADC3_4_EXTERNALTRIG_T8_TRGO) \ : \ (__EXT_TRIG_CONV__) \ ) \ ) \ ) \ : \ (__EXT_TRIG_CONV__) \ ) #endif /* STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx) /* Note: Macro including external triggers specific to device STM303xE: using */ /* Timer20 with ADC trigger input remap. */ #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ )? \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \ )? \ (ADC3_4_EXTERNALTRIG_T2_TRGO) \ : \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \ )? \ (ADC3_4_EXTERNALTRIG_T3_TRGO) \ : \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \ )? \ (ADC3_4_EXTERNALTRIG_T8_TRGO) \ : \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1 \ )? \ (ADC3_4_EXTERNALTRIG_T2_CC1) \ : \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO \ )? \ (ADC3_4_EXTERNALTRIG_EXT_IT2) \ : \ ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2 \ )? \ (ADC3_4_EXTERNALTRIG_T4_CC1) \ : \ (__EXT_TRIG_CONV__) \ ) \ ) \ ) \ ) \ ) \ ) \ : \ (__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \ ) #endif /* STM32F303xE || STM32F398xx */ #else #define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \ (__EXT_TRIG_CONV__) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ /** * @brief For devices with 3 ADCs or more: Defines the external trigger source * for injected group according to ADC into common group ADC1&ADC2 or * ADC3&ADC4 (some triggers with same source have different value to * be programmed into ADC JEXTSEL bits of JSQR register). * Note: No risk of trigger bits value of common group ADC1&ADC2 * misleading to another trigger at same bits value, because the 3 * exceptions below are circular and do not point to any other trigger * with direct treatment, except trigger * ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset. * For devices with 2 ADCs or less: this macro makes no change. * @param __HANDLE__ ADC handle * @param __EXT_TRIG_INJECTCONV__ External trigger selected for injected group * @retval External trigger to be programmed into JEXTSEL bits of JSQR register */ #if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx) #if defined(STM32F303xC) || defined(STM32F358xx) #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ )? \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \ : \ (__EXT_TRIG_INJECTCONV__) \ ) \ ) \ ) \ ) \ : \ (__EXT_TRIG_INJECTCONV__) \ ) #endif /* STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx) /* Note: Macro including external triggers specific to device STM303xE: using */ /* Timer20 with ADC trigger input remap. */ #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \ )? \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) \ == ADC_EXTERNALTRIGINJECCONV_T20_TRGO \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T20_TRGO) \ : \ ( ( (__EXT_TRIG_INJECTCONV__) \ == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 \ )? \ (ADC3_4_EXTERNALTRIGINJEC_T1_CC3) \ : \ (__EXT_TRIG_INJECTCONV__) \ ) \ ) \ ) \ ) \ ) \ ) \ : \ (__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \ ) #endif /* STM32F303xE || STM32F398xx */ #else #define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \ (__EXT_TRIG_INJECTCONV__) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ /** * @brief Configure the channel number into offset OFRx register * @param _CHANNEL_ ADC Channel * @retval None */ #define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U) /** * @brief Configure the channel number into differential mode selection register * @param _CHANNEL_ ADC Channel * @retval None */ #define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_)) /** * @brief Calibration factor in differential mode to be set into calibration register * @param _Calibration_Factor_ Calibration factor value * @retval None */ #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U) /** * @brief Calibration factor in differential mode to be retrieved from calibration register * @param _Calibration_Factor_ Calibration factor value * @retval None */ #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U) /** * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. * @param _Threshold_ Threshold value * @retval None */ #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U) /** * @brief Enable the ADC DMA continuous request for ADC multimode. * @param _DMAContReq_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U) /** * @brief Verification of hardware constraints before ADC can be disabled * @param __HANDLE__ ADC handle * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) */ #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ (( ( ((__HANDLE__)->Instance->CR) & \ (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ ) ? SET : RESET) /** * @brief Shift the offset in function of the selected ADC resolution. * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) * @param __HANDLE__ ADC handle * @param _Offset_ Value to be shifted * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U)) /** * @brief Shift the AWD1 threshold in function of the selected ADC resolution. * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) * @param __HANDLE__ ADC handle * @param _Threshold_ Value to be shifted * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U)) /** * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. * Thresholds have to be left-aligned on bit 7. * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded) * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded) * If resolution 8 bits, no shift. * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0) * @param __HANDLE__ ADC handle * @param _Threshold_ Value to be shifted * @retval None */ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \ ((_Threshold_) >> (4U- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3U)*2U))) : \ (_Threshold_) << 2U ) /** * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) * @param __HANDLE__ ADC handle * @retval Common control register ADC1_2 or ADC3_4 */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #define ADC_MASTER_INSTANCE(__HANDLE__) \ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ )? (ADC1) : (ADC3) \ ) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_MASTER_INSTANCE(__HANDLE__) \ (ADC1) #endif /* STM32F302xE || */ /* STM32F302xC || */ /* STM32F303x8 || STM32F328xx || STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_MASTER_INSTANCE(__HANDLE__) \ (ADC1) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) * @param __HANDLE__ ADC handle * @retval Common control register ADC1_2 or ADC3_4 */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #define ADC_COMMON_REGISTER(__HANDLE__) \ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ )? (ADC1_2_COMMON) : (ADC3_4_COMMON) \ ) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_COMMON_REGISTER(__HANDLE__) \ (ADC1_2_COMMON) #endif /* STM32F302xE || */ /* STM32F302xC || */ /* STM32F303x8 || STM32F328xx || STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_COMMON_REGISTER(__HANDLE__) \ (ADC1_COMMON) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs) * @param __HANDLE__ ADC handle * @retval None */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #define ADC_COMMON_CCR_MULTI(__HANDLE__) \ ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ )? \ (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) \ : \ (ADC3_4_COMMON->CCR & ADC34_CCR_MULTI) \ ) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_COMMON_CCR_MULTI(__HANDLE__) \ (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) #endif /* STM32F302xE || */ /* STM32F302xC || */ /* STM32F303x8 || STM32F328xx || STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_COMMON_CCR_MULTI(__HANDLE__) \ (RESET) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) * @param __HANDLE__ ADC handle * @retval None */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) ) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ (!RESET) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs) * @param __HANDLE__ ADC handle. * @retval None */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INJECSIMULT) || \ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_ALTERTRIG) || \ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) ) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \ (!RESET) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs) * @param __HANDLE__ ADC handle. * @retval None */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \ ((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) || \ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_REGSIMULT) || \ (ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INTERL) || \ (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) ) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \ (!RESET) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) * @param __HANDLE__ ADC handle * @retval None */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ )? \ (ADC1->CFGR & ADC_CFGR_JAUTO) \ : \ (ADC3->CFGR & ADC_CFGR_JAUTO) \ ) #elif defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ )? \ (ADC1->CFGR & ADC_CFGR_JAUTO) \ : \ (RESET) \ ) #else #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (RESET) #endif /** * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) * @param __HANDLE__ ADC handle * @param __HANDLE_OTHER_ADC__ other ADC handle * @retval None */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ ( ( ((__HANDLE__)->Instance == ADC1) \ )? \ ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \ : \ ( ( ((__HANDLE__)->Instance == ADC2) \ )? \ ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \ : \ ( ( ((__HANDLE__)->Instance == ADC3) \ )? \ ((__HANDLE_OTHER_ADC__)->Instance = ADC4) \ : \ ( ( ((__HANDLE__)->Instance == ADC4) \ )? \ ((__HANDLE_OTHER_ADC__)->Instance = ADC3) \ : \ ((__HANDLE_OTHER_ADC__)->Instance = NULL) \ ) \ ) \ ) \ ) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ ( ( ((__HANDLE__)->Instance == ADC1) \ )? \ ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \ : \ ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \ ) #endif /* STM32F302xE || */ /* STM32F302xC || */ /* STM32F303x8 || STM32F328xx || STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \ ((__HANDLE_OTHER_ADC__)->Instance = NULL) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Set handle of the ADC slave associated to the ADC master * if available (ADC2, ADC3, ADC4 availability depends on STM32 product) * @param __HANDLE_MASTER__ ADC master handle * @param __HANDLE_SLAVE__ ADC slave handle * @retval None */ #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \ )? \ ((__HANDLE_SLAVE__)->Instance = ADC2) \ : \ ( ( ((__HANDLE_MASTER__)->Instance == ADC3) \ )? \ ((__HANDLE_SLAVE__)->Instance = ADC4) \ : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) \ ) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \ )? \ ((__HANDLE_SLAVE__)->Instance = ADC2) \ : \ ( NULL ) \ ) #endif /* STM32F302xE || */ /* STM32F302xC || */ /* STM32F303x8 || STM32F328xx || STM32F334x8 */ #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ ((RESOLUTION) == ADC_RESOLUTION_10B) || \ ((RESOLUTION) == ADC_RESOLUTION_8B) || \ ((RESOLUTION) == ADC_RESOLUTION_6B) ) #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ ((RESOLUTION) == ADC_RESOLUTION_6B) ) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ ((ALIGN) == ADC_DATAALIGN_LEFT) ) #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ ((SCAN_MODE) == ADC_SCAN_ENABLE) ) #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \ ((CHANNEL) == ADC_CHANNEL_2) || \ ((CHANNEL) == ADC_CHANNEL_3) || \ ((CHANNEL) == ADC_CHANNEL_4) || \ ((CHANNEL) == ADC_CHANNEL_5) || \ ((CHANNEL) == ADC_CHANNEL_6) || \ ((CHANNEL) == ADC_CHANNEL_7) || \ ((CHANNEL) == ADC_CHANNEL_8) || \ ((CHANNEL) == ADC_CHANNEL_9) || \ ((CHANNEL) == ADC_CHANNEL_10) || \ ((CHANNEL) == ADC_CHANNEL_11) || \ ((CHANNEL) == ADC_CHANNEL_12) || \ ((CHANNEL) == ADC_CHANNEL_13) || \ ((CHANNEL) == ADC_CHANNEL_14) || \ ((CHANNEL) == ADC_CHANNEL_15) || \ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ ((CHANNEL) == ADC_CHANNEL_VBAT) || \ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ ((CHANNEL) == ADC_CHANNEL_VOPAMP1) || \ ((CHANNEL) == ADC_CHANNEL_VOPAMP2) || \ ((CHANNEL) == ADC_CHANNEL_VOPAMP3) || \ ((CHANNEL) == ADC_CHANNEL_VOPAMP4) ) #define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \ ((CHANNEL) == ADC_CHANNEL_2) || \ ((CHANNEL) == ADC_CHANNEL_3) || \ ((CHANNEL) == ADC_CHANNEL_4) || \ ((CHANNEL) == ADC_CHANNEL_5) || \ ((CHANNEL) == ADC_CHANNEL_6) || \ ((CHANNEL) == ADC_CHANNEL_7) || \ ((CHANNEL) == ADC_CHANNEL_8) || \ ((CHANNEL) == ADC_CHANNEL_9) || \ ((CHANNEL) == ADC_CHANNEL_10) || \ ((CHANNEL) == ADC_CHANNEL_11) || \ ((CHANNEL) == ADC_CHANNEL_12) || \ ((CHANNEL) == ADC_CHANNEL_13) || \ ((CHANNEL) == ADC_CHANNEL_14) ) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ ((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_4CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_61CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_181CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_601CYCLES_5) ) #define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \ ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) ) #define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \ ((OFFSET_NUMBER) == ADC_OFFSET_1) || \ ((OFFSET_NUMBER) == ADC_OFFSET_2) || \ ((OFFSET_NUMBER) == ADC_OFFSET_3) || \ ((OFFSET_NUMBER) == ADC_OFFSET_4) ) #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_10) || \ ((CHANNEL) == ADC_REGULAR_RANK_11) || \ ((CHANNEL) == ADC_REGULAR_RANK_12) || \ ((CHANNEL) == ADC_REGULAR_RANK_13) || \ ((CHANNEL) == ADC_REGULAR_RANK_14) || \ ((CHANNEL) == ADC_REGULAR_RANK_15) || \ ((CHANNEL) == ADC_REGULAR_RANK_16) ) #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #if defined(STM32F303xC) || defined(STM32F358xx) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \ \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ \ ((REGTRIG) == ADC_SOFTWARE_START) ) #endif /* STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \ \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) || \ \ ((REGTRIG) == ADC_SOFTWARE_START) ) #endif /* STM32F303xE || STM32F398xx */ #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) #if defined(STM32F302xE) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \ \ ((REGTRIG) == ADC_SOFTWARE_START) ) #endif /* STM32F302xE */ #if defined(STM32F302xC) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ \ ((REGTRIG) == ADC_SOFTWARE_START) ) #endif /* STM32F302xC */ #endif /* STM32F302xE || */ /* STM32F302xC */ #if defined(STM32F303x8) || defined(STM32F328xx) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ \ ((REGTRIG) == ADC_SOFTWARE_START) ) #endif /* STM32F303x8 || STM32F328xx */ #if defined(STM32F334x8) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ \ ((REGTRIG) == ADC_SOFTWARE_START) ) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ ((REGTRIG) == ADC_SOFTWARE_START) ) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) #if defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F303xC) || defined(STM32F358xx) #if defined(STM32F303xC) || defined(STM32F358xx) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \ \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F303xE || STM32F398xx */ #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ #if defined(STM32F302xE) || \ defined(STM32F302xC) #if defined(STM32F302xE) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F302xE */ #if defined(STM32F302xC) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F302xC */ #endif /* STM32F302xE || */ /* STM32F302xC */ #if defined(STM32F303x8) || defined(STM32F328xx) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F303x8 || STM32F328xx */ #if defined(STM32F334x8) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F334x8 */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ ((CHANNEL) == ADC_INJECTED_RANK_2) || \ ((CHANNEL) == ADC_INJECTED_RANK_3) || \ ((CHANNEL) == ADC_INJECTED_RANK_4) ) #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ ((MODE) == ADC_DUALMODE_INJECSIMULT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT) || \ ((MODE) == ADC_DUALMODE_INTERL) || \ ((MODE) == ADC_DUALMODE_ALTERTRIG) ) #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \ ((MODE) == ADC_DMAACCESSMODE_8_6_BITS) ) #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ ((CONVERSION) == ADC_INJECTED_GROUP) || \ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ ((EVENT) == ADC_AWD2_EVENT) || \ ((EVENT) == ADC_AWD3_EVENT) || \ ((EVENT) == ADC_OVR_EVENT) || \ ((EVENT) == ADC_JQOVF_EVENT) ) /** @defgroup ADCEx_range_verification ADC Extended Range Verification * in function of ADC resolution selected (12, 10, 8 or 6 bits) * @{ */ #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) /** * @} */ /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification * @{ */ #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) /** * @} */ /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification * @{ */ #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U))) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification * @{ */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) /** * @} */ /** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification * @{ */ /** * @brief Calibration factor length verification (7 bits maximum) * @param _Calibration_Factor_ Calibration factor value * @retval None */ #define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU)) /** * @} */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Verification of ADC state: enabled or disabled * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \ ) ? SET : RESET) /** * @brief Test if conversion trigger of regular group is software start * or external trigger. * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START) /** * @brief Test if conversion trigger of injected group is software start * or external trigger. * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START) /** * @brief Simultaneously clears and sets specific bits of the handle State * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Clear ADC error code (set it to error code: "no error") * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Set ADC number of conversions into regular channel sequence length. * @param _NbrOfConversion_ Regular channel sequence length * @retval None */ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ (((_NbrOfConversion_) - (uint8_t)1U) << 20U) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. * @param _SAMPLETIME_ Sample time parameter. * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. * @param _SAMPLETIME_ Sample time parameter. * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ ((_SAMPLETIME_) << (3U * (_CHANNELNB_))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 1U))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 7U))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ ((_CHANNELNB_) << (5U * ((_RANKNB_) - 13U))) /** * @brief Set the injected sequence length. * @param _JSQR_JL_ Sequence length. * @retval None */ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ (((_JSQR_JL_) -1U) << 20U) /** * @brief Set the selected injected channel rank * Note: on STM32F37x devices, channel rank position in JSQR register * is depending on total number of ranks selected into * injected sequencer (ranks sequence starting from 4-JL) * @param _CHANNELNB_ Channel number. * @param _RANKNB_ Rank number. * @param _JSQR_JL_ Sequence length. * @retval None */ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ ((_CHANNELNB_) << (5U * ((4U - ((_JSQR_JL_) - (_RANKNB_))) - 1U))) /** * @brief Enable ADC continuous conversion mode. * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ ((_CONTINUOUS_MODE_) << 1U) /** * @brief Configures the number of discontinuous conversions for the regular group channels. * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions. * @retval None */ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 13U) /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. * @param _SCAN_MODE_ Scan conversion mode. * @retval None */ /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ /* is equivalent to ADC_SCAN_ENABLE. */ #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ ) /** * @brief Calibration factor in differential mode to be set into calibration register * @param _Calibration_Factor_ Calibration factor value * @retval None */ #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \ ((_Calibration_Factor_) << 16U) /** * @brief Calibration factor in differential mode to be retrieved from calibration register * @param _Calibration_Factor_ Calibration factor value * @retval None */ #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \ ((_Calibration_Factor_) >> 16U) /** * @brief Get the maximum ADC conversion cycles on all channels. * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) * Approximation of sampling time within 4 ranges, returns the highest value: * below 7.5 cycles {1.5 cycle; 7.5 cycles}, * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} * equal to 239.5 cycles * Unit: ADC clock cycles * @param __HANDLE__ ADC handle * @retval ADC conversion cycles on all channels */ #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ \ (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \ : \ ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \ ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \ (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \ ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \ ) /** * @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler) * from system clock configuration register. * Approximation within 3 ranges, returns the higher value: * total prescaler minimum: 2 (ADC presc 2, APB2 presc 0) * total prescaler 32 (ADC presc 0 and APB2 presc all, or * ADC presc {4, 6, 8} and APB2 presc {0, 2, 4}) * total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16}) * Unit: none (prescaler factor) * @retval ADC and APB2 prescaler factor */ #define ADC_CLOCK_PRESCALER_RANGE() \ (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \ (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32U ) \ : \ (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128U ) \ ) /** * @brief Get the ADC clock prescaler from system clock configuration register. * @retval None */ #define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14U) +1U) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ ((ALIGN) == ADC_DATAALIGN_LEFT) ) #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ ((SCAN_MODE) == ADC_SCAN_ENABLE) ) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ ((CHANNEL) == ADC_CHANNEL_1) || \ ((CHANNEL) == ADC_CHANNEL_2) || \ ((CHANNEL) == ADC_CHANNEL_3) || \ ((CHANNEL) == ADC_CHANNEL_4) || \ ((CHANNEL) == ADC_CHANNEL_5) || \ ((CHANNEL) == ADC_CHANNEL_6) || \ ((CHANNEL) == ADC_CHANNEL_7) || \ ((CHANNEL) == ADC_CHANNEL_8) || \ ((CHANNEL) == ADC_CHANNEL_9) || \ ((CHANNEL) == ADC_CHANNEL_10) || \ ((CHANNEL) == ADC_CHANNEL_11) || \ ((CHANNEL) == ADC_CHANNEL_12) || \ ((CHANNEL) == ADC_CHANNEL_13) || \ ((CHANNEL) == ADC_CHANNEL_14) || \ ((CHANNEL) == ADC_CHANNEL_15) || \ ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ ((CHANNEL) == ADC_CHANNEL_VBAT) ) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ ((CHANNEL) == ADC_REGULAR_RANK_10) || \ ((CHANNEL) == ADC_REGULAR_RANK_11) || \ ((CHANNEL) == ADC_REGULAR_RANK_12) || \ ((CHANNEL) == ADC_REGULAR_RANK_13) || \ ((CHANNEL) == ADC_REGULAR_RANK_14) || \ ((CHANNEL) == ADC_REGULAR_RANK_15) || \ ((CHANNEL) == ADC_REGULAR_RANK_16) ) #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) ) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_SOFTWARE_START) ) #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) ) #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2) || \ ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) ) #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ ((CHANNEL) == ADC_INJECTED_RANK_2) || \ ((CHANNEL) == ADC_INJECTED_RANK_3) || \ ((CHANNEL) == ADC_INJECTED_RANK_4) ) #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ ((CONVERSION) == ADC_INJECTED_GROUP) || \ ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT) /** @defgroup ADCEx_range_verification ADC Extended Range Verification * For a unique ADC resolution: 12 bits * @{ */ #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= (0x0FFFU)) /** * @} */ /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification * @{ */ #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) /** * @} */ /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification * @{ */ #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (16U))) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification * @{ */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) /** * @} */ #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions * @{ */ /* Initialization/de-initialization functions *********************************/ /** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions * @{ */ /* I/O operation functions ****************************************************/ /* ADC calibration */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc); #endif /* STM32F373xC || STM32F378xx */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc); #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /* ADC group regular stop conversion without impacting group injected */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(struct __ADC_HandleTypeDef* hadc); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(struct __ADC_HandleTypeDef* hadc); /* Non-blocking mode: DMA */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(struct __ADC_HandleTypeDef* hadc); #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc); #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) void HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc); void HAL_ADCEx_LevelOutOfWindow2Callback(struct __ADC_HandleTypeDef* hadc); void HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleTypeDef* hadc); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} */ /** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /*__STM32F3xx_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_cortex.h * @author MCD Application Team * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_CORTEX_H #define __STM32F3xx_HAL_CORTEX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup CORTEX * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types CORTEX Exported Types * @{ */ #if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @brief MPU Region initialization structure * @{ */ typedef struct { uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ #define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ /** * @} */ /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) #define SYSTICK_CLKSOURCE_HCLK (0x00000004U) /** * @} */ #if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ #define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) #define MPU_HARDFAULT_NMI (0x00000002U) #define MPU_PRIVILEGED_DEFAULT (0x00000004U) #define MPU_HFNMI_PRIVDEF (0x00000006U) /** * @} */ /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ #define MPU_REGION_ENABLE ((uint8_t)0x01U) #define MPU_REGION_DISABLE ((uint8_t)0x00U) /** * @} */ /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) /** * @} */ /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) /** * @} */ /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) /** * @} */ /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) /** * @} */ /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels * @{ */ #define MPU_TEX_LEVEL0 ((uint8_t)0x00U) #define MPU_TEX_LEVEL1 ((uint8_t)0x01U) #define MPU_TEX_LEVEL2 ((uint8_t)0x02U) /** * @} */ /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04U) #define MPU_REGION_SIZE_64B ((uint8_t)0x05U) #define MPU_REGION_SIZE_128B ((uint8_t)0x06U) #define MPU_REGION_SIZE_256B ((uint8_t)0x07U) #define MPU_REGION_SIZE_512B ((uint8_t)0x08U) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /** * @} */ /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) #define MPU_REGION_PRIV_RW ((uint8_t)0x01U) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) #define MPU_REGION_PRIV_RO ((uint8_t)0x05U) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) /** * @} */ /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ #define MPU_REGION_NUMBER0 ((uint8_t)0x00U) #define MPU_REGION_NUMBER1 ((uint8_t)0x01U) #define MPU_REGION_NUMBER2 ((uint8_t)0x02U) #define MPU_REGION_NUMBER3 ((uint8_t)0x03U) #define MPU_REGION_NUMBER4 ((uint8_t)0x04U) #define MPU_REGION_NUMBER5 ((uint8_t)0x05U) #define MPU_REGION_NUMBER6 ((uint8_t)0x06U) #define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported Macros -----------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions * @{ */ /** @addtogroup CORTEX_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** * @} */ /** @addtogroup CORTEX_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ #if (__MPU_PRESENT == 1U) void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ ((GROUP) == NVIC_PRIORITYGROUP_1) || \ ((GROUP) == NVIC_PRIORITYGROUP_2) || \ ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) /** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source * @{ */ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) /** * @} */ #if (__MPU_PRESENT == 1U) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ ((TYPE) == MPU_TEX_LEVEL1) || \ ((TYPE) == MPU_TEX_LEVEL2)) #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ ((TYPE) == MPU_REGION_FULL_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RO) || \ ((TYPE) == MPU_REGION_PRIV_RO_URO)) #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ ((NUMBER) == MPU_REGION_NUMBER1) || \ ((NUMBER) == MPU_REGION_NUMBER2) || \ ((NUMBER) == MPU_REGION_NUMBER3) || \ ((NUMBER) == MPU_REGION_NUMBER4) || \ ((NUMBER) == MPU_REGION_NUMBER5) || \ ((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER7)) #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ ((SIZE) == MPU_REGION_SIZE_64B) || \ ((SIZE) == MPU_REGION_SIZE_128B) || \ ((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \ ((SIZE) == MPU_REGION_SIZE_1KB) || \ ((SIZE) == MPU_REGION_SIZE_2KB) || \ ((SIZE) == MPU_REGION_SIZE_4KB) || \ ((SIZE) == MPU_REGION_SIZE_8KB) || \ ((SIZE) == MPU_REGION_SIZE_16KB) || \ ((SIZE) == MPU_REGION_SIZE_32KB) || \ ((SIZE) == MPU_REGION_SIZE_64KB) || \ ((SIZE) == MPU_REGION_SIZE_128KB) || \ ((SIZE) == MPU_REGION_SIZE_256KB) || \ ((SIZE) == MPU_REGION_SIZE_512KB) || \ ((SIZE) == MPU_REGION_SIZE_1MB) || \ ((SIZE) == MPU_REGION_SIZE_2MB) || \ ((SIZE) == MPU_REGION_SIZE_4MB) || \ ((SIZE) == MPU_REGION_SIZE_8MB) || \ ((SIZE) == MPU_REGION_SIZE_16MB) || \ ((SIZE) == MPU_REGION_SIZE_32MB) || \ ((SIZE) == MPU_REGION_SIZE_64MB) || \ ((SIZE) == MPU_REGION_SIZE_128MB) || \ ((SIZE) == MPU_REGION_SIZE_256MB) || \ ((SIZE) == MPU_REGION_SIZE_512MB) || \ ((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) #endif /* __MPU_PRESENT */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CORTEX_Private_Functions CORTEX Private Functions * @brief CORTEX private functions * @{ */ #if (__MPU_PRESENT == 1U) void HAL_MPU_Disable(void); void HAL_MPU_Enable(uint32_t MPU_Control); #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_CORTEX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_def.h * @author MCD Application Team * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_DEF #define __STM32F3xx_HAL_DEF #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" #if defined USE_LEGACY #include "Legacy/stm32_hal_legacy.h" #endif #include /* Exported types ------------------------------------------------------------*/ /** * @brief HAL Status structures definition */ typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03 } HAL_StatusTypeDef; /** * @brief HAL Lock structures definition */ typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01 } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == BIT) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ do{ \ (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ (__DMA_HANDLE_).Parent = (__HANDLE__); \ } while(0U) /** @brief Reset the Handle's State field. * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * In this later function, when the Handle's "State" field is set to 0, it will execute the function * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #if (USE_RTOS == 1U) #error " USE_RTOS should be 0 in the current HAL release " #else #define __HAL_LOCK(__HANDLE__) \ do{ \ if((__HANDLE__)->Lock == HAL_LOCKED) \ { \ return HAL_BUSY; \ } \ else \ { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ }while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do{ \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ }while (0U) #endif /* USE_RTOS */ #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ #ifndef __packed #define __packed __attribute__((__packed__)) #endif /* __packed */ #endif /* __GNUC__ */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler */ #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ /** * @brief __NOINLINE definition */ #if defined ( __CC_ARM ) || defined ( __GNUC__ ) /* ARM & GNUCompiler ---------------- */ #define __NOINLINE __attribute__ ( (noinline) ) #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- */ #define __NOINLINE _Pragma("optimize = no_inline") #endif #ifdef __cplusplus } #endif #endif /* ___STM32F3xx_HAL_DEF */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_dma.h * @author MCD Application Team * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_DMA_H #define __STM32F3xx_HAL_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ /** * @brief DMA Configuration Structure definition */ typedef struct { uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; /** * @brief HAL DMA State structures definition */ typedef enum { HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */ }HAL_DMA_StateTypeDef; /** * @brief HAL DMA Error Code structure definition */ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; /** * @brief HAL DMA Callback ID structure definition */ typedef enum { HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ }HAL_DMA_CallbackIDTypeDef; /** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_InitTypeDef Init; /*!< DMA communication parameters */ HAL_LockTypeDef Lock; /*!< DMA locking object */ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ void *Parent; /*!< Parent object state */ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ uint32_t ChannelIndex; /*!< DMA Channel Index */ } DMA_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ /** @defgroup DMA_Error_Code DMA Error Code * @{ */ #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */ #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ /** * @} */ /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ /** * @} */ /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */ /** * @} */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */ /** * @} */ /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ /** * @} */ /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ /** * @} */ /** @defgroup DMA_mode DMA mode * @{ */ #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */ /** * @} */ /** @defgroup DMA_Priority_level DMA Priority level * @{ */ #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ /** * @} */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) /** * @} */ /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ #define DMA_FLAG_GL1 (0x00000001U) #define DMA_FLAG_TC1 (0x00000002U) #define DMA_FLAG_HT1 (0x00000004U) #define DMA_FLAG_TE1 (0x00000008U) #define DMA_FLAG_GL2 (0x00000010U) #define DMA_FLAG_TC2 (0x00000020U) #define DMA_FLAG_HT2 (0x00000040U) #define DMA_FLAG_TE2 (0x00000080U) #define DMA_FLAG_GL3 (0x00000100U) #define DMA_FLAG_TC3 (0x00000200U) #define DMA_FLAG_HT3 (0x00000400U) #define DMA_FLAG_TE3 (0x00000800U) #define DMA_FLAG_GL4 (0x00001000U) #define DMA_FLAG_TC4 (0x00002000U) #define DMA_FLAG_HT4 (0x00004000U) #define DMA_FLAG_TE4 (0x00008000U) #define DMA_FLAG_GL5 (0x00010000U) #define DMA_FLAG_TC5 (0x00020000U) #define DMA_FLAG_HT5 (0x00040000U) #define DMA_FLAG_TE5 (0x00080000U) #define DMA_FLAG_GL6 (0x00100000U) #define DMA_FLAG_TC6 (0x00200000U) #define DMA_FLAG_HT6 (0x00400000U) #define DMA_FLAG_TE6 (0x00800000U) #define DMA_FLAG_GL7 (0x01000000U) #define DMA_FLAG_TC7 (0x02000000U) #define DMA_FLAG_HT7 (0x04000000U) #define DMA_FLAG_TE7 (0x08000000U) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ /** @brief Reset DMA handle state * @param __HANDLE__ DMA handle. * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) /* Interrupt & Flag management */ /** * @brief Enables the specified DMA Channel interrupts. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) /** * @brief Disables the specified DMA Channel interrupts. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval None */ #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) /** * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @retval The state of DMA_IT (SET or RESET). */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) /** * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. * @param __HANDLE__ DMA handle * * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) /** * @} */ /* Include DMA HAL Extended module */ #include "stm32f3xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions * @{ */ /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* Input and Output operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros * @brief DMA private macros * @{ */ #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ ((STATE) == DMA_MINC_DISABLE)) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_PDATAALIGN_WORD)) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_MDATAALIGN_WORD )) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_dma_ex.h * @author MCD Application Team * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_DMA_EX_H #define __STM32F3xx_HAL_DMA_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup DMAEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros * @{ */ /* Interrupt & Flag management */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Returns the current DMA Channel transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ DMA_FLAG_TC5) /** * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ DMA_FLAG_HT5) /** * @brief Returns the current DMA Channel transfer error flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ DMA_FLAG_TE5) /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ DMA_FLAG_GL5) /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ (DMA1->ISR & (__FLAG__))) /** * @brief Clears the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ (DMA1->IFCR = (__FLAG__))) /** * @} */ #else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */ /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices * @{ */ /** * @brief Returns the current DMA Channel transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ DMA_FLAG_TC7) /** * @brief Returns the current DMA Channel half transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ DMA_FLAG_HT7) /** * @brief Returns the current DMA Channel transfer error flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ DMA_FLAG_TE7) /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ DMA_FLAG_GL7) /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) /** * @brief Clears the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag * Where x can be 1_7 to select the DMA Channel flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) /** * @} */ #endif /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ #endif /* __STM32F3xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_exti.h * @author MCD Application Team * @brief Header file of EXTI HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F3xx_HAL_EXTI_H #define STM32F3xx_HAL_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup EXTI EXTI * @brief EXTI HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Types EXTI Exported Types * @{ */ /** * @brief HAL EXTI common Callback ID enumeration definition */ typedef enum { HAL_EXTI_COMMON_CB_ID = 0x00U } EXTI_CallbackIDTypeDef; /** * @brief EXTI Handle structure definition */ typedef struct { uint32_t Line; /*!< Exti line number */ void (* PendingCallback)(void); /*!< Exti pending callback */ } EXTI_HandleTypeDef; /** * @brief EXTI Configuration structure definition */ typedef struct { uint32_t Line; /*!< The Exti line to be configured. This parameter can be a value of @ref EXTI_Line */ uint32_t Mode; /*!< The Exit Mode to be configured for a core. This parameter can be a combination of @ref EXTI_Mode */ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter can be a value of @ref EXTI_Trigger */ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of @ref EXTI_GPIOSel */ } EXTI_ConfigTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Constants EXTI Exported Constants * @{ */ /** @defgroup EXTI_Line EXTI Line * @{ */ #define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) /*!< External interrupt line 0 */ #define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) /*!< External interrupt line 1 */ #define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) /*!< External interrupt line 2 */ #define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) /*!< External interrupt line 3 */ #define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) /*!< External interrupt line 4 */ #define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) /*!< External interrupt line 5 */ #define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) /*!< External interrupt line 6 */ #define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) /*!< External interrupt line 7 */ #define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) /*!< External interrupt line 8 */ #define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) /*!< External interrupt line 9 */ #define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) /*!< External interrupt line 10 */ #define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) /*!< External interrupt line 11 */ #define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) /*!< External interrupt line 12 */ #define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) /*!< External interrupt line 13 */ #define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) /*!< External interrupt line 14 */ #define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) /*!< External interrupt line 15 */ #define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #if defined(EXTI_IMR_MR18) #define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ #else #define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u) #endif /* EXTI_IMR_MR18 */ #define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u) /*!< External interrupt line 19 Connected to the RTC tamper and Timestamps */ #define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) /*!< External interrupt line 20 Connected to the RTC wakeup timer */ #if defined(EXTI_IMR_MR21) #define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */ #else #define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u) #endif /* EXTI_IMR_MR21 */ #define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */ #define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */ #if defined(EXTI_IMR_MR24) #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) /*!< External interrupt line 24 Connected to the internal I2C2 wakeup event */ #else #define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u) #endif /* EXTI_IMR_MR24 */ #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */ #if defined(EXTI_IMR_MR26) #define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */ #else #define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au) #endif /* EXTI_IMR_MR26 */ #if defined(EXTI_IMR_MR27) #define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) /*!< External interrupt line 27 Connected to the internal I2C3 wakeup event */ #else #define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu) #endif /* EXTI_IMR_MR27 */ #if defined(EXTI_IMR_MR28) #define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) /*!< External interrupt line 28 Connected to the internal USART3 wakeup event */ #else #define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) #endif /* EXTI_IMR_MR28 */ #if defined(EXTI_32_63_SUPPORT) #if defined(EXTI_IMR_MR29) #define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du) /*!< External interrupt line 29 Connected to the Comparator 3 output */ #else #define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) #endif /* EXTI_IMR_MR29 */ #if defined(EXTI_IMR_MR30) #define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu) /*!< External interrupt line 30 Connected to the Comparator 4 output */ #else #define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) #endif /* EXTI_IMR_MR30 */ #if defined(EXTI_IMR_MR31) #define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) /*!< External interrupt line 31 Connected to the Comparator 5 output */ #else #define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu) #endif /* EXTI_IMR_MR31 */ #define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u) /*!< External interrupt line 32 Connected to the Comparator 6 output */ #if defined(EXTI_IMR2_MR33) #define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) /*!< External interrupt line 33 Connected to the Comparator 7 output */ #else #define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u) #endif /* EXTI_IMR2_MR33 */ #if defined(EXTI_IMR2_MR34) #define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u) /*!< External interrupt line 34 Connected to the USART4 output */ #else #define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) #endif /* EXTI_IMR2_MR34 */ #if defined(EXTI_IMR2_MR35) #define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) /*!< External interrupt line 35 Connected to the USART5 output */ #else #define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) #endif /* EXTI_IMR2_MR35 */ #endif /* EXTI_32_63_SUPPORT */ /** * @} */ /** @defgroup EXTI_Mode EXTI Mode * @{ */ #define EXTI_MODE_NONE 0x00000000u #define EXTI_MODE_INTERRUPT 0x00000001u #define EXTI_MODE_EVENT 0x00000002u /** * @} */ /** @defgroup EXTI_Trigger EXTI Trigger * @{ */ #define EXTI_TRIGGER_NONE 0x00000000u #define EXTI_TRIGGER_RISING 0x00000001u #define EXTI_TRIGGER_FALLING 0x00000002u #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @} */ /** @defgroup EXTI_GPIOSel EXTI GPIOSel * @brief * @{ */ #define EXTI_GPIOA 0x00000000u #define EXTI_GPIOB 0x00000001u #define EXTI_GPIOC 0x00000002u #define EXTI_GPIOD 0x00000003u #if defined(GPIOE) #define EXTI_GPIOE 0x00000004u #endif /* GPIOE */ #define EXTI_GPIOF 0x00000005u #if defined(GPIOG) #define EXTI_GPIOG 0x00000006u #endif /* GPIOG */ #if defined(GPIOH) #define EXTI_GPIOH 0x00000007u #endif /* GPIOH */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Macros EXTI Exported Macros * @{ */ /** * @} */ /* Private constants --------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ /** * @brief EXTI Line property definition */ #define EXTI_PROPERTY_SHIFT 24u #define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) #define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) #define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI Register and bit usage */ #define EXTI_REG_SHIFT 16u #define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) #define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) #define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) #define EXTI_PIN_MASK 0x0000001Fu /** * @brief EXTI Mask for interrupt & event mode */ #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) /** * @brief EXTI Mask for trigger possibilities */ #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @brief EXTI Line number */ #if defined(EXTI_32_63_SUPPORT) #define EXTI_LINE_NB 36uL #else #define EXTI_LINE_NB 29uL #endif /* EXTI_32_63_SUPPORT */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ #define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) #define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) #define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) #define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) #if defined(GPIOH) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOF) || \ ((__PORT__) == EXTI_GPIOG) || \ ((__PORT__) == EXTI_GPIOH)) #elif defined(GPIOE) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOF)) #else #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOF)) #endif /* GPIOE */ #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Functions EXTI Exported Functions * @brief EXTI Exported Functions * @{ */ /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions * @brief Configuration functions * @{ */ /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); /** * @} */ /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F3xx_HAL_EXTI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_flash.h * @author MCD Application Team * @brief Header file of Flash HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_FLASH_H #define __STM32F3xx_HAL_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Constants * @{ */ #define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ /** * @} */ /** @addtogroup FLASH_Private_Macros * @{ */ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ ((__LATENCY__) == FLASH_LATENCY_1) || \ ((__LATENCY__) == FLASH_LATENCY_2)) /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ /** * @brief FLASH Procedure structure definition */ typedef enum { FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_MASSERASE = 2U, FLASH_PROC_PROGRAMHALFWORD = 3U, FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMDOUBLEWORD = 5U } FLASH_ProcedureTypeDef; /** * @brief FLASH handle Structure definition */ typedef struct { __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ HAL_LockTypeDef Lock; /*!< FLASH locking object */ __IO uint32_t ErrorCode; /*!< FLASH error code This parameter can be a value of @ref FLASH_Error_Codes */ } FLASH_ProcessTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ */ /** @defgroup FLASH_Error_Codes FLASH Error Codes * @{ */ #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ /** * @} */ /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ #define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR |= FLASH_ACR_HLFCYA) /** * @brief Disable the FLASH half cycle access. * @retval None */ #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) /** * @} */ /** @defgroup FLASH_EM_Latency FLASH Latency * @brief macros to handle FLASH Latency * @{ */ /** * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency * This parameter can be one of the following values: * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) /** * @brief Get the FLASH Latency. * @retval FLASH Latency * This parameter can be one of the following values: * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles */ #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) /** * @} */ /** @defgroup FLASH_Prefetch FLASH Prefetch * @brief macros to handle FLASH Prefetch buffer * @{ */ /** * @brief Enable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) /** * @brief Disable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) /** * @} */ /** @defgroup FLASH_Interrupt FLASH Interrupts * @brief macros to handle FLASH interrupts * @{ */ /** * @brief Enable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) /** * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt * @arg @ref FLASH_IT_ERR Error Interrupt * @retval none */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) /** * @brief Get the specified FLASH flag status. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg @ref FLASH_FLAG_BSY FLASH Busy flag * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @retval The new state of __FLAG__ (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) /** * @brief Clear the specified FLASH flag. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag * @retval none */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) /** * @} */ /** * @} */ /* Include FLASH HAL Extended module */ #include "stm32f3xx_hal_flash_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler function */ void HAL_FLASH_IRQHandler(void); /* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** * @} */ /** @addtogroup FLASH_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); /** * @} */ /** @addtogroup FLASH_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ uint32_t HAL_FLASH_GetError(void); /** * @} */ /** * @} */ /* Private function -------------------------------------------------*/ /** @addtogroup FLASH_Private_Functions * @{ */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_FLASH_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_flash_ex.h * @author MCD Application Team * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_FLASH_EX_H #define __STM32F3xx_HAL_FLASH_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup FLASHEx * @{ */ /** @addtogroup FLASHEx_Private_Constants * @{ */ #define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU) /** * @} */ /** @addtogroup FLASHEx_Private_Macros * @{ */ #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)) #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ ((VALUE) == OB_WRPSTATE_ENABLE)) #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ ((LEVEL) == OB_RDP_LEVEL_1))/*||\ ((LEVEL) == OB_RDP_LEVEL_2))*/ #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET)) #define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF)) #define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET)) #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) #define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \ ((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET)) #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */ #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \ || defined(STM32F373xC) || defined(STM32F378xx) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ ((ADDRESS) <= 0x0803FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ ((ADDRESS) <= 0x0800FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ ((ADDRESS) <= 0x08007FFFU) : ((ADDRESS) <= 0x08003FFFU)))) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \ || defined(STM32F373xC) || defined(STM32F378xx) #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU))) #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU))) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types * @{ */ /** * @brief FLASH Erase structure definition */ typedef struct { uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase. This parameter can be a value of @ref FLASHEx_Type_Erase */ uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */ uint32_t NbPages; /*!< NbPages: Number of pagess to be erased. This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/ } FLASH_EraseInitTypeDef; /** * @brief FLASH Options bytes program structure definition */ typedef struct { uint32_t OptionType; /*!< OptionType: Option byte to be configured. This parameter can be a value of @ref FLASHEx_OB_Type */ uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. This parameter can be a value of @ref FLASHEx_OB_WRP_State */ uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected This parameter can be a value of @ref FLASHEx_OB_Write_Protection */ uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.. This parameter can be a value of @ref FLASHEx_OB_Read_Protection */ uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP, @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring, @ref FLASHEx_OB_RAM_Parity_Check_Enable. @if STM32F373xC And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices) @endif @if STM32F378xx And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices) @endif */ uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed This parameter can be a value of @ref FLASHEx_OB_Data_Address */ uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ } FLASH_OBProgramInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants * @{ */ /** @defgroup FLASHEx_Page_Size FLASHEx Page Size * @{ */ #define FLASH_PAGE_SIZE 0x800 /** * @} */ /** @defgroup FLASHEx_Type_Erase FLASH Type Erase * @{ */ #define FLASH_TYPEERASE_PAGES (0x00U) /*!
© Copyright (c) 2016 STMicroelectronics. * All rights reserved.
* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_GPIO_H #define __STM32F3xx_HAL_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup GPIO * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ */ /** * @brief GPIO Init structure definition */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode */ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull */ uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed */ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ }GPIO_InitTypeDef; /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }GPIO_PinState; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ */ /** @defgroup GPIO_pins GPIO pins * @{ */ #define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ #define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ #define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ #define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ #define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ #define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ #define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ #define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ #define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ #define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ #define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ #define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ #define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ #define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ /** * @} */ /** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ * - X : GPIO mode or EXTI Mode * - y : External IT or Event trigger detection * - z : IO configuration on External IT or Event * - Y : Output type (Push Pull or Open Drain) * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ #define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ #define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ #define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup GPIO_speed GPIO speed * @brief GPIO Output Maximum frequency * @{ */ #define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */ /** * @} */ /** @defgroup GPIO_pull GPIO pull * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ #define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ #define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ /** * @brief Check whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** * @brief Clear the EXTI's line pending flags. * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** * @brief Check whether the specified EXTI line is asserted or not. * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** * @brief Clear the EXTI's line pending bits. * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** * @brief Generate a Software interrupt on selected EXTI line. * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup GPIO_Private_Macros GPIO Private Macros * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ ((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ ((__MODE__) == GPIO_MODE_AF_PP) ||\ ((__MODE__) == GPIO_MODE_AF_OD) ||\ ((__MODE__) == GPIO_MODE_IT_RISING) ||\ ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ ((__MODE__) == GPIO_MODE_ANALOG)) #define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) #define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ ((__PULL__) == GPIO_PULLUP) || \ ((__PULL__) == GPIO_PULLDOWN)) /** * @} */ /* Include GPIO HAL Extended module */ #include "stm32f3xx_hal_gpio_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions * @{ */ /** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} */ /** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions * @{ */ /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_GPIO_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_gpio_ex.h * @author MCD Application Team * @brief Header file of GPIO HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_GPIO_EX_H #define __STM32F3xx_HAL_GPIO_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup GPIOEx GPIOEx * @brief GPIO Extended HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection * @{ */ #if defined (STM32F302xC) /*---------------------------------- STM32F302xC ------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ #define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ #define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F302xC */ #if defined (STM32F303xC) /*---------------------------------- STM32F303xC ------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ #define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ #define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ #define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ #define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ #define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ #define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ #define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F303xC */ #if defined (STM32F303xE) /*---------------------------------- STM32F303xE ------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ #define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ #define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ #define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ #define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ #define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ #define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ #define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ #define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ #define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ #define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ #define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ #define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ #define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ #define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F303xE */ #if defined (STM32F302xE) /*---------------------------------- STM32F302xE ------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ #define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ #define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ #define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ #define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ #define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ #define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F302xE */ #if defined (STM32F398xx) /*---------------------------------- STM32F398xx ------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ #define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ #define GPIO_AF2_TIM20 ((uint8_t)0x02U) /* TIM20 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ #define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ #define GPIO_AF3_TIM20 ((uint8_t)0x03U) /* TIM20 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ #define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ #define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ #define GPIO_AF6_TIM20 ((uint8_t)0x06U) /* TIM20 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ #define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ #define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ #define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ #define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ #define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ #define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ #define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0xCU) /* SDIO Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F398xx */ #if defined (STM32F358xx) /*---------------------------------- STM32F358xx -------------------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM8 ((uint8_t)0x02U) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02U) /* COMP1 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_COMP7 ((uint8_t)0x03U) /* COMP7 Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM8 ((uint8_t)0x04U) /* TIM8 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_I2S ((uint8_t)0x05U) /* I2S Alternate Function mapping */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05U) /* I2S2ext Alternate Function mapping */ #define GPIO_AF5_TIM8 ((uint8_t)0x05U) /* TIM8 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05U) /* UART4 Alternate Function mapping */ #define GPIO_AF5_UART5 ((uint8_t)0x05U) /* UART5 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06U) /* I2S3ext Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_TIM8 ((uint8_t)0x06U) /* TIM8 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_COMP3 ((uint8_t)0x07U) /* COMP3 Alternate Function mapping */ #define GPIO_AF7_COMP5 ((uint8_t)0x07U) /* COMP5 Alternate Function mapping */ #define GPIO_AF7_COMP6 ((uint8_t)0x07U) /* COMP6 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP3 ((uint8_t)0x08U) /* COMP3 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08U) /* COMP4 Alternate Function mapping */ #define GPIO_AF8_COMP5 ((uint8_t)0x08U) /* COMP5 Alternate Function mapping */ #define GPIO_AF8_COMP6 ((uint8_t)0x08U) /* COMP6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM8 ((uint8_t)0x09U) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM8 ((uint8_t)0xAU) /* TIM8 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ #define GPIO_AF11_TIM8 ((uint8_t)0x0BU) /* TIM8 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0xCU) /* TIM1 Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F358xx */ #if defined (STM32F373xC) /*---------------------------------- STM32F373xC--------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ #define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */ #define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ #define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ #define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_USB ((uint8_t)0x0EU) /* USB Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0EU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F373xC */ #if defined (STM32F378xx) /*---------------------------------------- STM32F378xx--------------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ #define GPIO_AF2_TIM13 ((uint8_t)0x02U) /* TIM13 Alternate Function mapping */ #define GPIO_AF2_TIM14 ((uint8_t)0x02U) /* TIM14 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM19 ((uint8_t)0x02U) /* TIM19 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI1 ((uint8_t)0x06U) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ #define GPIO_AF6_CEC ((uint8_t)0x06U) /* CEC Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ #define GPIO_AF7_CEC ((uint8_t)0x07U) /* CEC Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08U) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08U) /* COMP2 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0xAU) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM12 ((uint8_t)0xAU) /* TIM12 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM19 ((uint8_t)0x0BU) /* TIM19 Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0BU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F378xx */ #if defined (STM32F303x8) /*---------------------------------- STM32F303x8--------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ #define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ #define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ /** * @brief AF 13 selection */ #define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F303x8 */ #if defined (STM32F334x8) || defined (STM32F328xx) /*---------------------------------- STM32F334x8/STM32F328xx -------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM16 ((uint8_t)0x02U) /* TIM16 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_HRTIM1 ((uint8_t)0x03U) /* HRTIM1 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ #define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ #define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0xAU) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ #define GPIO_AF12_HRTIM1 ((uint8_t)0x0CU) /* HRTIM1 Alternate Function mapping */ /** * @brief AF 13 selection */ #define GPIO_AF13_OPAMP2 ((uint8_t)0x0DU) /* OPAMP2 Alternate Function mapping */ #define GPIO_AF13_HRTIM1 ((uint8_t)0x0DU) /* HRTIM1 Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0DU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F334x8 || STM32F328xx */ #if defined (STM32F301x8) || defined (STM32F318xx) /*---------------------------------- STM32F301x8 / STM32F318xx ------------------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ #define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ #define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ #define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F301x8 || STM32F318xx */ #if defined (STM32F302x8) /*---------------------------------- STM32F302x8------------------------------------------*/ /** * @brief AF 0 selection */ #define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00U) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01U) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_TIM16 ((uint8_t)0x01U) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01U) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_EVENTOUT ((uint8_t)0x01U) /* EVENTOUT Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_I2C3 ((uint8_t)0x02U) /* I2C3 Alternate Function mapping */ #define GPIO_AF2_TIM1 ((uint8_t)0x02U) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02U) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02U) /* TIM2 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TSC ((uint8_t)0x03U) /* TSC Alternate Function mapping */ #define GPIO_AF3_I2C3 ((uint8_t)0x03U) /* I2C3 Alternate Function mapping */ #define GPIO_AF3_TIM15 ((uint8_t)0x03U) /* TIM15 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_TIM1 ((uint8_t)0x04U) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04U) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04U) /* TIM17 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_IR ((uint8_t)0x05U) /* IR Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_TIM1 ((uint8_t)0x06U) /* TIM1 Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06U) /* IR Alternate Function mapping */ #define GPIO_AF6_SPI2 ((uint8_t)0x06U) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ #define GPIO_AF7_GPCOMP6 ((uint8_t)0x07U) /* GPCOMP6 Alternate Function mapping */ #define GPIO_AF7_CAN ((uint8_t)0x07U) /* CAN Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF8_I2C3 ((uint8_t)0x08U) /* I2C3 Alternate Function mapping */ #define GPIO_AF8_GPCOMP2 ((uint8_t)0x08U) /* GPCOMP2 Alternate Function mapping */ #define GPIO_AF8_GPCOMP4 ((uint8_t)0x08U) /* GPCOMP4 Alternate Function mapping */ #define GPIO_AF8_GPCOMP6 ((uint8_t)0x08U) /* GPCOMP6 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF9_TIM1 ((uint8_t)0x09U) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09U) /* TIM15 Alternate Function mapping */ #define GPIO_AF9_CAN ((uint8_t)0x09U) /* CAN Alternate Function mapping */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0xAU) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0xAU) /* TIM17 Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF11_TIM1 ((uint8_t)0x0BU) /* TIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_TIM1 ((uint8_t)0x0CU) /* TIM1 Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0CU) || ((AF) == (uint8_t)0x0FU)) /*------------------------------------------------------------------------------------------*/ #endif /* STM32F302x8 */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros * @{ */ /** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index * @{ */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOD))? 3U : 5U) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F373xC) || defined(STM32F378xx) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOD))? 3U :\ ((__GPIOx__) == (GPIOE))? 4U : 5U) #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOD))? 3U :\ ((__GPIOx__) == (GPIOE))? 4U :\ ((__GPIOx__) == (GPIOF))? 5U :\ ((__GPIOx__) == (GPIOG))? 6U : 7U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_GPIO_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_i2c.h * @author MCD Application Team * @brief Header file of I2C HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F3xx_HAL_I2C_H #define STM32F3xx_HAL_I2C_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup I2C * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types * @{ */ /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition * @brief I2C Configuration Structure definition * @{ */ typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. This parameter calculated by referring to I2C initialization section in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ } I2C_InitTypeDef; /** * @} */ /** @defgroup HAL_state_structure_definition HAL state structure definition * @brief HAL State structure definition * @note HAL I2C State value coding follow below described bitmap :\n * b7-b6 Error information\n * 00 : No Error\n * 01 : Abort (Abort user request on going)\n * 10 : Timeout\n * 11 : Error\n * b5 Peripheral initialization status\n * 0 : Reset (peripheral not initialized)\n * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n * b4 (not used)\n * x : Should be set to 0\n * b3\n * 0 : Ready or Busy (No Listen mode ongoing)\n * 1 : Listen (peripheral in Address Listen Mode)\n * b2 Intrinsic process state\n * 0 : Ready\n * 1 : Busy (peripheral busy with some configuration or internal operations)\n * b1 Rx state\n * 0 : Ready (no Rx operation ongoing)\n * 1 : Busy (Rx operation ongoing)\n * b0 Tx state\n * 0 : Ready (no Tx operation ongoing)\n * 1 : Busy (Tx operation ongoing) * @{ */ typedef enum { HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission process is ongoing */ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; /** * @} */ /** @defgroup HAL_mode_structure_definition HAL mode structure definition * @brief HAL Mode structure definition * @note HAL I2C Mode value coding follow below described bitmap :\n * b7 (not used)\n * x : Should be set to 0\n * b6\n * 0 : None\n * 1 : Memory (HAL I2C communication is in Memory Mode)\n * b5\n * 0 : None\n * 1 : Slave (HAL I2C communication is in Slave Mode)\n * b4\n * 0 : None\n * 1 : Master (HAL I2C communication is in Master Mode)\n * b3-b2-b1-b0 (not used)\n * xxxx : Should be set to 0000 * @{ */ typedef enum { HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ } HAL_I2C_ModeTypeDef; /** * @} */ /** @defgroup I2C_Error_Code_definition I2C Error Code definition * @brief I2C Error Code definition * @{ */ #define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ #define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ #define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ #define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ #define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ #define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ #define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) #define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ #define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** * @} */ /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition * @brief I2C handle Structure definition * @{ */ typedef struct __I2C_HandleTypeDef { I2C_TypeDef *Instance; /*!< I2C registers base address */ I2C_InitTypeDef Init; /*!< I2C communication parameters */ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ uint16_t XferSize; /*!< I2C transfer size */ __IO uint16_t XferCount; /*!< I2C transfer counter */ __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can be a value of @ref I2C_XFEROPTIONS */ __IO uint32_t PreviousState; /*!< I2C communication Previous state */ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ HAL_LockTypeDef Lock; /*!< I2C locking object */ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ __IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) /** * @brief HAL I2C Callback ID enumeration definition */ typedef enum { HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ } HAL_I2C_CallbackIDTypeDef; /** * @brief HAL I2C Callback pointer definition */ typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup I2C_Exported_Constants I2C Exported Constants * @{ */ /** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options * @{ */ #define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) #define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) /* List of XferOptions in usage of : * 1- Restart condition in all use cases (direction change or not) */ #define I2C_OTHER_FRAME (0x000000AAU) #define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) /** * @} */ /** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode * @{ */ #define I2C_ADDRESSINGMODE_7BIT (0x00000001U) #define I2C_ADDRESSINGMODE_10BIT (0x00000002U) /** * @} */ /** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode * @{ */ #define I2C_DUALADDRESS_DISABLE (0x00000000U) #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ /** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks * @{ */ #define I2C_OA2_NOMASK ((uint8_t)0x00U) #define I2C_OA2_MASK01 ((uint8_t)0x01U) #define I2C_OA2_MASK02 ((uint8_t)0x02U) #define I2C_OA2_MASK03 ((uint8_t)0x03U) #define I2C_OA2_MASK04 ((uint8_t)0x04U) #define I2C_OA2_MASK05 ((uint8_t)0x05U) #define I2C_OA2_MASK06 ((uint8_t)0x06U) #define I2C_OA2_MASK07 ((uint8_t)0x07U) /** * @} */ /** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode * @{ */ #define I2C_GENERALCALL_DISABLE (0x00000000U) #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ /** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode * @{ */ #define I2C_NOSTRETCH_DISABLE (0x00000000U) #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ /** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size * @{ */ #define I2C_MEMADD_SIZE_8BIT (0x00000001U) #define I2C_MEMADD_SIZE_16BIT (0x00000002U) /** * @} */ /** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View * @{ */ #define I2C_DIRECTION_TRANSMIT (0x00000000U) #define I2C_DIRECTION_RECEIVE (0x00000001U) /** * @} */ /** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode * @{ */ #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND #define I2C_SOFTEND_MODE (0x00000000U) /** * @} */ /** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode * @{ */ #define I2C_NO_STARTSTOP (0x00000000U) #define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) #define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /** * @} */ /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition * @brief I2C Interrupt definition * Elements values convention: 0xXXXXXXXX * - XXXXXXXX : Interrupt control mask * @{ */ #define I2C_IT_ERRI I2C_CR1_ERRIE #define I2C_IT_TCI I2C_CR1_TCIE #define I2C_IT_STOPI I2C_CR1_STOPIE #define I2C_IT_NACKI I2C_CR1_NACKIE #define I2C_IT_ADDRI I2C_CR1_ADDRIE #define I2C_IT_RXI I2C_CR1_RXIE #define I2C_IT_TXI I2C_CR1_TXIE /** * @} */ /** @defgroup I2C_Flag_definition I2C Flag definition * @{ */ #define I2C_FLAG_TXE I2C_ISR_TXE #define I2C_FLAG_TXIS I2C_ISR_TXIS #define I2C_FLAG_RXNE I2C_ISR_RXNE #define I2C_FLAG_ADDR I2C_ISR_ADDR #define I2C_FLAG_AF I2C_ISR_NACKF #define I2C_FLAG_STOPF I2C_ISR_STOPF #define I2C_FLAG_TC I2C_ISR_TC #define I2C_FLAG_TCR I2C_ISR_TCR #define I2C_FLAG_BERR I2C_ISR_BERR #define I2C_FLAG_ARLO I2C_ISR_ARLO #define I2C_FLAG_OVR I2C_ISR_OVR #define I2C_FLAG_PECERR I2C_ISR_PECERR #define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT #define I2C_FLAG_ALERT I2C_ISR_ALERT #define I2C_FLAG_BUSY I2C_ISR_BUSY #define I2C_FLAG_DIR I2C_ISR_DIR /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup I2C_Exported_Macros I2C Exported Macros * @{ */ /** @brief Reset I2C handle state. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) #endif /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg @ref I2C_IT_ERRI Errors interrupt enable * @arg @ref I2C_IT_TCI Transfer complete interrupt enable * @arg @ref I2C_IT_STOPI STOP detection interrupt enable * @arg @ref I2C_IT_NACKI NACK received interrupt enable * @arg @ref I2C_IT_ADDRI Address match interrupt enable * @arg @ref I2C_IT_RXI RX interrupt enable * @arg @ref I2C_IT_TXI TX interrupt enable * * @retval None */ #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) /** @brief Disable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the interrupt source to disable. * This parameter can be one of the following values: * @arg @ref I2C_IT_ERRI Errors interrupt enable * @arg @ref I2C_IT_TCI Transfer complete interrupt enable * @arg @ref I2C_IT_STOPI STOP detection interrupt enable * @arg @ref I2C_IT_NACKI NACK received interrupt enable * @arg @ref I2C_IT_ADDRI Address match interrupt enable * @arg @ref I2C_IT_RXI RX interrupt enable * @arg @ref I2C_IT_TXI TX interrupt enable * * @retval None */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) /** @brief Check whether the specified I2C interrupt source is enabled or not. * @param __HANDLE__ specifies the I2C Handle. * @param __INTERRUPT__ specifies the I2C interrupt source to check. * This parameter can be one of the following values: * @arg @ref I2C_IT_ERRI Errors interrupt enable * @arg @ref I2C_IT_TCI Transfer complete interrupt enable * @arg @ref I2C_IT_STOPI STOP detection interrupt enable * @arg @ref I2C_IT_NACKI NACK received interrupt enable * @arg @ref I2C_IT_ADDRI Address match interrupt enable * @arg @ref I2C_IT_RXI RX interrupt enable * @arg @ref I2C_IT_TXI TX interrupt enable * * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2C flag is set or not. * @param __HANDLE__ specifies the I2C Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref I2C_FLAG_TXE Transmit data register empty * @arg @ref I2C_FLAG_TXIS Transmit interrupt status * @arg @ref I2C_FLAG_RXNE Receive data register not empty * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) * @arg @ref I2C_FLAG_AF Acknowledge failure received flag * @arg @ref I2C_FLAG_STOPF STOP detection flag * @arg @ref I2C_FLAG_TC Transfer complete (master mode) * @arg @ref I2C_FLAG_TCR Transfer complete reload * @arg @ref I2C_FLAG_BERR Bus error * @arg @ref I2C_FLAG_ARLO Arbitration lost * @arg @ref I2C_FLAG_OVR Overrun/Underrun * @arg @ref I2C_FLAG_PECERR PEC error in reception * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref I2C_FLAG_ALERT SMBus alert * @arg @ref I2C_FLAG_BUSY Bus busy * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) * * @retval The new state of __FLAG__ (SET or RESET). */ #define I2C_FLAG_MASK (0x0001FFFFU) #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the I2C Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg @ref I2C_FLAG_TXE Transmit data register empty * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) * @arg @ref I2C_FLAG_AF Acknowledge failure received flag * @arg @ref I2C_FLAG_STOPF STOP detection flag * @arg @ref I2C_FLAG_BERR Bus error * @arg @ref I2C_FLAG_ARLO Arbitration lost * @arg @ref I2C_FLAG_OVR Overrun/Underrun * @arg @ref I2C_FLAG_PECERR PEC error in reception * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag * @arg @ref I2C_FLAG_ALERT SMBus alert * * @retval None */ #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ : ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} */ /* Include I2C HAL Extended module */ #include "stm32f3xx_hal_i2c_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup I2C_Exported_Functions * @{ */ /** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); /** * @} */ /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); /** * @} */ /** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions * @{ */ /* Peripheral State, Mode and Error functions *********************************/ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants * @{ */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2C_Private_Macro I2C Private Macros * @{ */ #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ ((MODE) == I2C_ADDRESSINGMODE_10BIT)) #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ ((MASK) == I2C_OA2_MASK01) || \ ((MASK) == I2C_OA2_MASK02) || \ ((MASK) == I2C_OA2_MASK03) || \ ((MASK) == I2C_OA2_MASK04) || \ ((MASK) == I2C_OA2_MASK05) || \ ((MASK) == I2C_OA2_MASK06) || \ ((MASK) == I2C_OA2_MASK07)) #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ ((CALL) == I2C_GENERALCALL_ENABLE)) #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ ((STRETCH) == I2C_NOSTRETCH_ENABLE)) #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ ((SIZE) == I2C_MEMADD_SIZE_16BIT)) #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ ((MODE) == I2C_AUTOEND_MODE) || \ ((MODE) == I2C_SOFTEND_MODE)) #define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ ((REQUEST) == I2C_GENERATE_START_READ) || \ ((REQUEST) == I2C_GENERATE_START_WRITE) || \ ((REQUEST) == I2C_NO_STARTSTOP)) #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ ((REQUEST) == I2C_LAST_FRAME) || \ ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) #define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ /* Private functions are defined in stm32f3xx_hal_i2c.c file */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F3xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_i2c_ex.h * @author MCD Application Team * @brief Header file of I2C HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F3xx_HAL_I2C_EX_H #define STM32F3xx_HAL_I2C_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup I2CEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter * @{ */ #define I2C_ANALOGFILTER_ENABLE 0x00000000U #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus * @{ */ #define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ #define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ #define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ #define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ #if defined(SYSCFG_CFGR1_I2C2_FMP) #define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ #else #define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ #endif #if defined(SYSCFG_CFGR1_I2C3_FMP) #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ #else #define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ #endif /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions * @{ */ /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants * @{ */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ ((FILTER) == I2C_ANALOGFILTER_DISABLE)) #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) /** * @} */ /* Private Functions ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions * @{ */ /* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F3xx_HAL_I2C_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_pwr.h * @author MCD Application Team * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_PWR_H #define __STM32F3xx_HAL_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup PWR PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins * @{ */ #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */ #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */ #define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */ /** * @} */ /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode * @{ */ #define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */ #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */ /** * @} */ /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */ #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */ /** * @} */ /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */ #define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */ /** * @} */ /** @defgroup PWR_Flag PWR Flag * @{ */ #define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */ #define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */ #define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */ #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Macro PWR Exported Macro * @{ */ /** @brief Check PWR flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. * An additional wakeup event is detected if the WKUP pin is enabled * (by setting the EWUP bit) when the WKUP pin level is already high. * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * resumed from StandBy mode. * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode * For this reason, this bit is equal to 0 after Standby or reset * until the PVDE bit is set. * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference * voltage VREFINT is ready. * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) /** * @} */ /* Private macros --------------------------------------------------------*/ /** @addtogroup PWR_Private_Macros PWR Private Macros * @{ */ #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ ((PIN) == PWR_WAKEUP_PIN2) || \ ((PIN) == PWR_WAKEUP_PIN3)) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) /** * @} */ /* Include PWR HAL Extended module */ #include "stm32f3xx_hal_pwr_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_PWR_DeInit(void); /** * @} */ /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ /* Peripheral Control functions **********************************************/ void HAL_PWR_EnableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void); /* WakeUp pins configuration functions ****************************************/ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); /* Low Power modes configuration functions ************************************/ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSTANDBYMode(void); void HAL_PWR_EnableSleepOnExit(void); void HAL_PWR_DisableSleepOnExit(void); void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_PWR_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_pwr_ex.h * @author MCD Application Team * @brief Header file of PWR HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_PWR_EX_H #define __STM32F3xx_HAL_PWR_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup PWREx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWREx_Exported_Types PWR Extended Exported Types * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || \ defined(STM32F302xC) || defined(STM32F303xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || \ defined(STM32F373xC) /** * @brief PWR PVD configuration structure definition */ typedef struct { uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level This parameter can be a value of @ref PWREx_PVD_detection_level */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWREx_PVD_Mode */ }PWR_PVDTypeDef; #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F303x8 || STM32F334x8 || */ /* STM32F301x8 || STM32F302x8 || */ /* STM32F373xC */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || \ defined(STM32F302xC) || defined(STM32F303xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || \ defined(STM32F373xC) /** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level * @{ */ #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */ #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */ #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */ #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */ #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */ #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */ #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */ #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */ /** * @} */ /** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode * @{ */ #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ #define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F303x8 || STM32F334x8 || */ /* STM32F301x8 || STM32F302x8 || */ /* STM32F373xC */ #if defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx * @{ */ #define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */ #define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */ #define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */ /** * @} */ #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || \ defined(STM32F302xC) || defined(STM32F303xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || \ defined(STM32F373xC) /** * @brief Enable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) /** * @brief Disable interrupt on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None. */ #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) /** * @brief Enable event on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) /** * @brief Disable event on PVD Exti Line 16. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) /** * @brief Disable the PVD Extended Interrupt Rising Trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Falling Trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); /** * @brief PVD EXTI line configuration: set falling edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) /** * @brief PVD EXTI line configuration: set rising edge trigger. * @retval None. */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) /** * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); /** * @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @retval EXTI PVD Line Status. */ #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) /** * @brief Clear the PVD EXTI flag. * @retval None. */ #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F303x8 || STM32F334x8 || */ /* STM32F301x8 || STM32F302x8 || */ /* STM32F373xC */ /** * @} */ /* Private macros --------------------------------------------------------*/ /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || \ defined(STM32F302xC) || defined(STM32F303xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || \ defined(STM32F373xC) #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ ((MODE) == PWR_PVD_MODE_NORMAL)) #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F303x8 || STM32F334x8 || */ /* STM32F301x8 || STM32F302x8 || */ /* STM32F373xC */ #if defined(STM32F373xC) || defined(STM32F378xx) #define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \ ((SDADC) == PWR_SDADC_ANALOG2) || \ ((SDADC) == PWR_SDADC_ANALOG3)) #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ /** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions * @{ */ /* Peripheral Extended control functions **************************************/ #if defined(STM32F302xE) || defined(STM32F303xE) || \ defined(STM32F302xC) || defined(STM32F303xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || \ defined(STM32F373xC) void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVDCallback(void); #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F303x8 || STM32F334x8 || */ /* STM32F301x8 || STM32F302x8 || */ /* STM32F373xC */ #if defined(STM32F373xC) || defined(STM32F378xx) void HAL_PWREx_EnableSDADC(uint32_t Analogx); void HAL_PWREx_DisableSDADC(uint32_t Analogx); #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_PWR_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_rcc.h * @author MCD Application Team * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_RCC_H #define __STM32F3xx_HAL_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup RCC * @{ */ /** @addtogroup RCC_Private_Constants * @{ */ /** @defgroup RCC_Timeout RCC Timeout * @{ */ /* Disable Backup domain write protection state change timeout */ #define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ /* LSE state change timeout */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ /** * @} */ /** @defgroup RCC_Register_Offset Register offsets * @{ */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) #define RCC_CR_OFFSET 0x00 #define RCC_CFGR_OFFSET 0x04 #define RCC_CIR_OFFSET 0x08 #define RCC_BDCR_OFFSET 0x20 #define RCC_CSR_OFFSET 0x24 /** * @} */ /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion * @brief RCC registers bit address in the alias region * @{ */ #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) /* Alias word address of HSEON bit */ #define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) /* Alias word address of CSSON bit */ #define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) /* Alias word address of PLLON bit */ #define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) /* Alias word address of RMVF bit */ #define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) /* --- BDCR Registers ---*/ /* Alias word address of LSEON bit */ #define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) /* Alias word address of LSEON bit */ #define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) /* Alias word address of RTCEN bit */ #define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) /* Alias word address of BDRST bit */ #define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) /** * @} */ /* CR register byte 2 (Bits[23:16]) base address */ #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) /* CIR register byte 1 (Bits[15:8]) base address */ #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) /* CIR register byte 2 (Bits[23:16]) base address */ #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) /* Defines used for Flags */ #define CR_REG_INDEX ((uint8_t)1U) #define BDCR_REG_INDEX ((uint8_t)2U) #define CSR_REG_INDEX ((uint8_t)3U) #define CFGR_REG_INDEX ((uint8_t)4U) #define RCC_FLAG_MASK ((uint8_t)0x1FU) /** * @} */ /** @addtogroup RCC_Private_Macros * @{ */ #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ ((__HSE__) == RCC_HSE_BYPASS)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ ((__PLL__) == RCC_PLL_ON)) #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) #define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \ ((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \ ((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \ ((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \ ((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \ ((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \ ((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \ ((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16)) #else #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) #endif #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \ ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \ ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \ ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \ ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \ ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \ ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \ ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16)) #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ ((__MUL__) == RCC_PLL_MUL16)) #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ ((__HCLK__) == RCC_SYSCLK_DIV512)) #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) #if defined(RCC_CFGR3_USART2SW) #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) #define IS_RCC_USART3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) #endif /* RCC_CFGR3_USART3SW */ #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)) /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ /** * @brief RCC PLL configuration structure definition */ typedef struct { uint32_t PLLState; /*!< PLLState: The new state of the PLL. This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock This parameter must be a value of @ref RCC_PLL_Prediv_Factor */ #endif } RCC_PLLInitTypeDef; /** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { uint32_t OscillatorType; /*!< The oscillators to be configured. This parameter can be a value of @ref RCC_Oscillator_Type */ uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) uint32_t HSEPredivValue; /*!< The HSE predivision factor value. This parameter can be a value of @ref RCC_PLL_HSE_Prediv_Factor */ #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ } RCC_OscInitTypeDef; /** * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { uint32_t ClockType; /*!< The clock to be configured. This parameter can be a value of @ref RCC_System_Clock_Type */ uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. This parameter can be a value of @ref RCC_System_Clock_Source */ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of @ref RCC_AHB_Clock_Source */ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ } RCC_ClkInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants RCC Exported Constants * @{ */ /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI clock selected as PLL entry clock source */ #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE clock selected as PLL entry clock source */ /** * @} */ /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE (0x00000000U) #define RCC_OSCILLATORTYPE_HSE (0x00000001U) #define RCC_OSCILLATORTYPE_HSI (0x00000002U) #define RCC_OSCILLATORTYPE_LSE (0x00000004U) #define RCC_OSCILLATORTYPE_LSI (0x00000008U) /** * @} */ /** @defgroup RCC_HSE_Config HSE Config * @{ */ #define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ /** * @} */ /** @defgroup RCC_LSE_Config LSE Config * @{ */ #define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ /** * @} */ /** @defgroup RCC_HSI_Config HSI Config * @{ */ #define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ /** * @} */ /** @defgroup RCC_LSI_Config LSI Config * @{ */ #define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ /** @defgroup RCC_PLL_Config PLL Config * @{ */ #define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ #define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ #define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ /** * @} */ /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ #define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ #define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ #define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ /** * @} */ /** @defgroup RCC_System_Clock_Source System Clock Source * @{ */ #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ /** * @} */ /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status * @{ */ #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ /** * @} */ /** @defgroup RCC_AHB_Clock_Source AHB Clock Source * @{ */ #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ #define RCC_RTCCLKSOURCE_NO_CLK RCC_BDCR_RTCSEL_NOCLOCK /*!< No clock */ #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} */ /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor * @{ */ #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 /** * @} */ #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor * @{ */ #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 /** * @} */ #endif #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) /** @defgroup RCC_PLL_HSE_Prediv_Factor RCC PLL HSE Prediv Factor * @{ */ #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 /** * @} */ #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ #if defined(RCC_CFGR3_USART2SW) /** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source * @{ */ #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI /** * @} */ #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source * @{ */ #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI /** * @} */ #endif /* RCC_CFGR3_USART3SW */ /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source * @{ */ #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK /** * @} */ /** @defgroup RCC_MCO_Index MCO Index * @{ */ #define RCC_MCO1 (0x00000000U) #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ /** @defgroup RCC_Interrupt Interrupts * @{ */ #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ /** * @} */ /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register * - XXX : Register index * - 001: CR register * - 010: BDCR register * - 011: CSR register * - 100: CFGR register * @{ */ /* Flags in the CR register */ #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ /* Flags in the CSR register */ #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ #if defined(RCC_CSR_V18PWRRSTF) #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_V18PWRRSTF))) #endif #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */ #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ /* Flags in the CFGR register */ #if defined(RCC_CFGR_MCOF) #define RCC_FLAG_MCO ((uint8_t)((CFGR_REG_INDEX << 5U) | POSITION_VAL(RCC_CFGR_MCOF))) /*!< Microcontroller Clock Output Flag */ #endif /* RCC_CFGR_MCOF */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Macros RCC Exported Macros * @{ */ /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable * @brief Enable or disable the AHB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TSC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN)) /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) #define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN)) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) /** * @} */ /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET) #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET) #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET) #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) #define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET) #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET) #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET) #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) #define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET) /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) #define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET) #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) #define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status * @brief EGet the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) /** * @} */ /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset * @brief Force or release AHB peripheral reset. * @{ */ #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST)) /** * @} */ /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) #define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC1RST)) #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) #define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST)) /** * @} */ /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) /** * @} */ /** @defgroup RCC_HSI_Configuration HSI Configuration * @{ */ /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. */ #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) /** * @} */ /** @defgroup RCC_LSI_Configuration LSI Configuration * @{ */ /** @brief Macro to enable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. */ #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) /** @brief Macro to disable the Internal Low Speed oscillator (LSI). * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. */ #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) /** * @} */ /** @defgroup RCC_HSE_Configuration HSE Configuration * @{ */ /** * @brief Macro to configure the External High Speed oscillator (HSE). * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg @ref RCC_HSE_ON turn ON the HSE oscillator * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ do{ \ if ((__STATE__) == RCC_HSE_ON) \ { \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } \ else if ((__STATE__) == RCC_HSE_OFF) \ { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ else if ((__STATE__) == RCC_HSE_BYPASS) \ { \ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } \ else \ { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ }while(0U) /** * @} */ /** @defgroup RCC_LSE_Configuration LSE Configuration * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do{ \ if ((__STATE__) == RCC_LSE_ON) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ else if ((__STATE__) == RCC_LSE_OFF) \ { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ else if ((__STATE__) == RCC_LSE_BYPASS) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ else \ { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ }while(0U) /** * @} */ /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config * @{ */ /** @brief Macro to configure the USART1 clock (USART1CLK). * @param __USART1CLKSOURCE__ specifies the USART1 clock source. * This parameter can be one of the following values: @if STM32F302xC * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F303xC * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F358xx * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F302xE * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F303xE * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F398xx * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F373xC * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F378xx * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F301x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F302x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F318xx * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F303x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F334x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F328xx * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ #define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: @if STM32F302xC * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F303xC * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F358xx * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F302xE * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F303xE * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F398xx * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F373xC * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F378xx * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock @endif @if STM32F301x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F302x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F318xx * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F303x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F334x8 * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif @if STM32F328xx * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock @endif * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW))) #if defined(RCC_CFGR3_USART2SW) /** @brief Macro to configure the USART2 clock (USART2CLK). * @param __USART2CLKSOURCE__ specifies the USART2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ #define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW))) #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /** @brief Macro to configure the USART3 clock (USART3CLK). * @param __USART3CLKSOURCE__ specifies the USART3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ #define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW))) #endif /* RCC_CFGR3_USART2SW */ /** * @} */ /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config * @{ */ /** @brief Macro to configure the I2C1 clock (I2C1CLK). * @param __I2C1CLKSOURCE__ specifies the I2C1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW))) /** * @} */ /** @defgroup RCC_PLL_Configuration PLL Configuration * @{ */ /** @brief Macro to enable the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. */ #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) /** @brief Macro to disable the main PLL. * @note The main PLL can not be disabled if it is used as system clock source */ #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) /** @brief Get oscillator clock selected as PLL input clock * @retval The clock source used for PLL entry. The returned value can be one * of the following: * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock */ #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) /** * @} */ /** @defgroup RCC_Get_Clock_source Get Clock source * @{ */ /** * @brief Macro to configure the system clock source. * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. */ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) /** @brief Macro to get the clock source used as system clock. * @retval The clock source used as system clock. The returned value can be one * of the following: * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock */ #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) /** * @} */ /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config * @{ */ #if defined(RCC_CFGR_MCOPRE) /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 */ #else /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source */ #endif #if defined(RCC_CFGR_MCOPRE) #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) #else #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) #endif /** * @} */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration * @{ */ /** @brief Macro to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it cannot be changed unless the * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source, * the RTC cannot be used in STOP and STANDBY modes. * @note The system must always be configured so as to get a PCLK frequency greater than or * equal to the RTCCLK frequency for a proper operation of the RTC. */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) /** @brief Macro to get the RTC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 */ #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macro to enable the the RTC clock. * @note These macros must be used only after the RTC clock source was selected. */ #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) /** @brief Macro to disable the the RTC clock. * @note These macros must be used only after the RTC clock source was selected. */ #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) /** @brief Macro to force the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_BDCR register. */ #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) /** @brief Macros to release the Backup domain reset. */ #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) /** * @} */ /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ /** @brief Enable RCC interrupt. * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) /** @brief Disable RCC interrupt. * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) /** @brief Clear the RCC's interrupt pending bits. * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. * @arg @ref RCC_IT_LSERDY LSE ready interrupt. * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. * @arg @ref RCC_IT_HSERDY HSE ready interrupt. * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. * @arg @ref RCC_IT_CSS Clock Security System interrupt */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) /** @brief Check the RCC's interrupt has occurred or not. * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. * @arg @ref RCC_IT_LSERDY LSE ready interrupt. * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. * @arg @ref RCC_IT_HSERDY HSE ready interrupt. * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. * @arg @ref RCC_IT_CSS Clock Security System interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, * RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) /** @brief Check RCC flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset * @arg @ref RCC_FLAG_PINRST Pin reset. * @arg @ref RCC_FLAG_PORRST POR/PDR reset. * @arg @ref RCC_FLAG_SFTRST Software reset. * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. * @arg @ref RCC_FLAG_LPWRRST Low Power reset. @if defined(STM32F301x8) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain @endif @if defined(STM32F302x8) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain @endif @if defined(STM32F302xC) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output @endif @if defined(STM32F302xE) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain @endif @if defined(STM32F303x8) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain @endif @if defined(STM32F303xC) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output @endif @if defined(STM32F303xE) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain @endif @if defined(STM32F334x8) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain @endif @if defined(STM32F358xx) * @arg @ref RCC_FLAG_MCO Microcontroller Clock Output @endif @if defined(STM32F373xC) * @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain @endif * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ (((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ (((__FLAG__) >> 5U) == CFGR_REG_INDEX)? RCC->CFGR : \ RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) /** * @} */ /** * @} */ /* Include RCC HAL Extension module */ #include "stm32f3xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_Exported_Functions * @{ */ /** @addtogroup RCC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} */ /** @addtogroup RCC_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ************************************************/ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); void HAL_RCC_EnableCSS(void); /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); void HAL_RCC_DisableCSS(void); uint32_t HAL_RCC_GetSysClockFreq(void); uint32_t HAL_RCC_GetHCLKFreq(void); uint32_t HAL_RCC_GetPCLK1Freq(void); uint32_t HAL_RCC_GetPCLK2Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_RCC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_rcc_ex.h * @author MCD Application Team * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_HAL_RCC_EX_H #define __STM32F3xx_HAL_RCC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup RCCEx * @{ */ /** @addtogroup RCCEx_Private_Macros * @{ */ #if defined(RCC_CFGR_PLLNODIV) #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2)) #else #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \ ((SOURCE) == RCC_MCO1SOURCE_LSI) || \ ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ ((SOURCE) == RCC_MCO1SOURCE_HSI) || \ ((SOURCE) == RCC_MCO1SOURCE_HSE) || \ ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2)) #endif /* RCC_CFGR_PLLNODIV */ #if defined(STM32F301x8) || defined(STM32F318xx) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC)) #endif /* STM32F301x8 || STM32F318xx */ #if defined(STM32F302x8) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ RCC_PERIPHCLK_TIM17)) #endif /* STM32F302x8 */ #if defined(STM32F302xC) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_USB)) #endif /* STM32F302xC */ #if defined(STM32F303xC) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_USB)) #endif /* STM32F303xC */ #if defined(STM32F302xE) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ RCC_PERIPHCLK_TIM17)) #endif /* STM32F302xE */ #if defined(STM32F303xE) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20)) #endif /* STM32F303xE */ #if defined(STM32F398xx) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \ RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \ RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \ RCC_PERIPHCLK_TIM20)) #endif /* STM32F398xx */ #if defined(STM32F358xx) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC)) #endif /* STM32F358xx */ #if defined(STM32F303x8) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) #endif /* STM32F303x8 */ #if defined(STM32F334x8) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \ RCC_PERIPHCLK_RTC)) #endif /* STM32F334x8 */ #if defined(STM32F328xx) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) #endif /* STM32F328xx */ #if defined(STM32F373xC) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_USB)) #endif /* STM32F373xC */ #if defined(STM32F378xx) #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) #endif /* STM32F378xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \ ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \ ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \ ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \ ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \ ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \ ((ADCCLK) == RCC_ADC1PLLCLK_DIV256)) #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ ((SOURCE) == RCC_TIM1CLK_PLLCLK)) #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ ((SOURCE) == RCC_TIM15CLK_PLLCLK)) #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ ((SOURCE) == RCC_TIM16CLK_PLLCLK)) #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ ((SOURCE) == RCC_TIM17CLK_PLLCLK)) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ ((SOURCE) == RCC_TIM1CLK_PLLCLK)) #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) #endif /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ ((SOURCE) == RCC_TIM1CLK_PLLCLK)) #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \ ((SOURCE) == RCC_TIM2CLK_PLLCLK)) #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \ ((SOURCE) == RCC_TIM34CLK_PLLCLK)) #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ ((SOURCE) == RCC_TIM15CLK_PLLCLK)) #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ ((SOURCE) == RCC_TIM16CLK_PLLCLK)) #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ ((SOURCE) == RCC_TIM17CLK_PLLCLK)) #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx) #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \ ((SOURCE) == RCC_TIM20CLK_PLLCLK)) #endif /* STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \ ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \ ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \ ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \ ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \ ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \ ((ADCCLK) == RCC_ADC34PLLCLK_DIV256)) #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \ ((SOURCE) == RCC_TIM8CLK_PLLCLK)) #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ ((SOURCE) == RCC_TIM1CLK_PLLCLK)) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F334x8) #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \ ((SOURCE) == RCC_HRTIM1CLK_PLLCLK)) #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \ ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8)) #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ ((SOURCE) == RCC_CECCLKSOURCE_LSE)) #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \ ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \ ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \ ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \ ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \ ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \ ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \ ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \ ((DIV) == RCC_SDADCSYSCLK_DIV48)) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5)) #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ #if defined(RCC_CFGR_MCOPRE) #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \ ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \ ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128)) #else #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)) #endif /* RCC_CFGR_MCOPRE */ #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ /** * @brief RCC extended clocks structure definition */ #if defined(STM32F301x8) || defined(STM32F318xx) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t I2c3ClockSelection; /*!< I2C3 clock source This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ uint32_t Adc1ClockSelection; /*!< ADC1 clock source This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Tim15ClockSelection; /*!< TIM15 clock source This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ uint32_t Tim16ClockSelection; /*!< TIM16 clock source This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ uint32_t Tim17ClockSelection; /*!< TIM17 clock source This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F301x8 || STM32F318xx */ #if defined(STM32F302x8) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t I2c3ClockSelection; /*!< I2C3 clock source This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ uint32_t Adc1ClockSelection; /*!< ADC1 clock source This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Tim15ClockSelection; /*!< TIM15 clock source This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ uint32_t Tim16ClockSelection; /*!< TIM16 clock source This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ uint32_t Tim17ClockSelection; /*!< TIM17 clock source This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ uint32_t USBClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F302x8 */ #if defined(STM32F302xC) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t USBClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F302xC */ #if defined(STM32F303xC) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Tim8ClockSelection; /*!< TIM8 clock source This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ uint32_t USBClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F303xC */ #if defined(STM32F302xE) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t I2c3ClockSelection; /*!< I2C3 clock source This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Tim2ClockSelection; /*!< TIM2 clock source This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ uint32_t Tim15ClockSelection; /*!< TIM15 clock source This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ uint32_t Tim16ClockSelection; /*!< TIM16 clock source This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ uint32_t Tim17ClockSelection; /*!< TIM17 clock source This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ uint32_t USBClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F302xE */ #if defined(STM32F303xE) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t I2c3ClockSelection; /*!< I2C3 clock source This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Tim2ClockSelection; /*!< TIM2 clock source This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ uint32_t Tim8ClockSelection; /*!< TIM8 clock source This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ uint32_t Tim15ClockSelection; /*!< TIM15 clock source This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ uint32_t Tim16ClockSelection; /*!< TIM16 clock source This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ uint32_t Tim17ClockSelection; /*!< TIM17 clock source This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ uint32_t Tim20ClockSelection; /*!< TIM20 clock source This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ uint32_t USBClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F303xE */ #if defined(STM32F398xx) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t I2c3ClockSelection; /*!< I2C3 clock source This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Tim2ClockSelection; /*!< TIM2 clock source This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ uint32_t Tim8ClockSelection; /*!< TIM8 clock source This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ uint32_t Tim15ClockSelection; /*!< TIM15 clock source This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ uint32_t Tim16ClockSelection; /*!< TIM16 clock source This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ uint32_t Tim17ClockSelection; /*!< TIM17 clock source This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ uint32_t Tim20ClockSelection; /*!< TIM20 clock source This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F398xx */ #if defined(STM32F358xx) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t Uart4ClockSelection; /*!< UART4 clock source This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ uint32_t Uart5ClockSelection; /*!< UART5 clock source This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ uint32_t I2sClockSelection; /*!< I2S clock source This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Tim8ClockSelection; /*!< TIM8 clock source This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F358xx */ #if defined(STM32F303x8) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F303x8 */ #if defined(STM32F334x8) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F334x8 */ #if defined(STM32F328xx) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ uint32_t Tim1ClockSelection; /*!< TIM1 clock source This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F328xx */ #if defined(STM32F373xC) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t Adc1ClockSelection; /*!< ADC1 clock source This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ uint32_t SdadcClockSelection; /*!< SDADC clock prescaler This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ uint32_t CecClockSelection; /*!< HDMI CEC clock source This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ uint32_t USBClockSelection; /*!< USB clock source This parameter can be a value of @ref RCCEx_USB_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F373xC */ #if defined(STM32F378xx) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCC_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< USART3 clock source This parameter can be a value of @ref RCC_USART3_Clock_Source */ uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCC_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< I2C2 clock source This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t Adc1ClockSelection; /*!< ADC1 clock source This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ uint32_t SdadcClockSelection; /*!< SDADC clock prescaler This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ uint32_t CecClockSelection; /*!< HDMI CEC clock source This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ }RCC_PeriphCLKInitTypeDef; #endif /* STM32F378xx */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants * @{ */ /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source * @{ */ #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE #if defined(RCC_CFGR_PLLNODIV) #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL) #endif /* RCC_CFGR_PLLNODIV */ #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL /** * @} */ /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection * @{ */ #if defined(STM32F301x8) || defined(STM32F318xx) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC1 (0x00000080U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_I2C3 (0x00008000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_TIM15 (0x00040000U) #define RCC_PERIPHCLK_TIM16 (0x00080000U) #define RCC_PERIPHCLK_TIM17 (0x00100000U) #endif /* STM32F301x8 || STM32F318xx */ #if defined(STM32F302x8) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC1 (0x00000080U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_I2C3 (0x00008000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_USB (0x00020000U) #define RCC_PERIPHCLK_TIM15 (0x00040000U) #define RCC_PERIPHCLK_TIM16 (0x00080000U) #define RCC_PERIPHCLK_TIM17 (0x00100000U) #endif /* STM32F302x8 */ #if defined(STM32F302xC) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_UART4 (0x00000008U) #define RCC_PERIPHCLK_UART5 (0x00000010U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_USB (0x00020000U) #endif /* STM32F302xC */ #if defined(STM32F303xC) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_UART4 (0x00000008U) #define RCC_PERIPHCLK_UART5 (0x00000010U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_ADC34 (0x00000100U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_TIM8 (0x00002000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_USB (0x00020000U) #endif /* STM32F303xC */ #if defined(STM32F302xE) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_UART4 (0x00000008U) #define RCC_PERIPHCLK_UART5 (0x00000010U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_USB (0x00020000U) #define RCC_PERIPHCLK_I2C3 (0x00040000U) #define RCC_PERIPHCLK_TIM2 (0x00100000U) #define RCC_PERIPHCLK_TIM34 (0x00200000U) #define RCC_PERIPHCLK_TIM15 (0x00400000U) #define RCC_PERIPHCLK_TIM16 (0x00800000U) #define RCC_PERIPHCLK_TIM17 (0x01000000U) #endif /* STM32F302xE */ #if defined(STM32F303xE) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_UART4 (0x00000008U) #define RCC_PERIPHCLK_UART5 (0x00000010U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_ADC34 (0x00000100U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_TIM8 (0x00002000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_USB (0x00020000U) #define RCC_PERIPHCLK_I2C3 (0x00040000U) #define RCC_PERIPHCLK_TIM2 (0x00100000U) #define RCC_PERIPHCLK_TIM34 (0x00200000U) #define RCC_PERIPHCLK_TIM15 (0x00400000U) #define RCC_PERIPHCLK_TIM16 (0x00800000U) #define RCC_PERIPHCLK_TIM17 (0x01000000U) #define RCC_PERIPHCLK_TIM20 (0x02000000U) #endif /* STM32F303xE */ #if defined(STM32F398xx) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_UART4 (0x00000008U) #define RCC_PERIPHCLK_UART5 (0x00000010U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_ADC34 (0x00000100U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_TIM8 (0x00002000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_I2C3 (0x00040000U) #define RCC_PERIPHCLK_TIM2 (0x00100000U) #define RCC_PERIPHCLK_TIM34 (0x00200000U) #define RCC_PERIPHCLK_TIM15 (0x00400000U) #define RCC_PERIPHCLK_TIM16 (0x00800000U) #define RCC_PERIPHCLK_TIM17 (0x01000000U) #define RCC_PERIPHCLK_TIM20 (0x02000000U) #endif /* STM32F398xx */ #if defined(STM32F358xx) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_UART4 (0x00000008U) #define RCC_PERIPHCLK_UART5 (0x00000010U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_ADC34 (0x00000100U) #define RCC_PERIPHCLK_I2S (0x00000200U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_TIM8 (0x00002000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F358xx */ #if defined(STM32F303x8) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F303x8 */ #if defined(STM32F334x8) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_HRTIM1 (0x00004000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F334x8 */ #if defined(STM32F328xx) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_ADC12 (0x00000080U) #define RCC_PERIPHCLK_TIM1 (0x00001000U) #define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F328xx */ #if defined(STM32F373xC) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC1 (0x00000080U) #define RCC_PERIPHCLK_CEC (0x00000400U) #define RCC_PERIPHCLK_SDADC (0x00000800U) #define RCC_PERIPHCLK_RTC (0x00010000U) #define RCC_PERIPHCLK_USB (0x00020000U) #endif /* STM32F373xC */ #if defined(STM32F378xx) #define RCC_PERIPHCLK_USART1 (0x00000001U) #define RCC_PERIPHCLK_USART2 (0x00000002U) #define RCC_PERIPHCLK_USART3 (0x00000004U) #define RCC_PERIPHCLK_I2C1 (0x00000020U) #define RCC_PERIPHCLK_I2C2 (0x00000040U) #define RCC_PERIPHCLK_ADC1 (0x00000080U) #define RCC_PERIPHCLK_CEC (0x00000400U) #define RCC_PERIPHCLK_SDADC (0x00000800U) #define RCC_PERIPHCLK_RTC (0x00010000U) #endif /* STM32F378xx */ /** * @} */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source * @{ */ #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI /** * @} */ /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source * @{ */ #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK /** * @} */ /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source * @{ */ #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK /** * @} */ /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source * @{ */ #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1 #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2 #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4 #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6 #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8 #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10 #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12 #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16 #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32 #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64 #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128 #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256 /** * @} */ /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source * @{ */ #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT /** * @} */ /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source * @{ */ #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL /** * @} */ /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source * @{ */ #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL /** * @} */ /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source * @{ */ #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL /** * @} */ /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source * @{ */ #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL /** * @} */ #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source * @{ */ #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI /** * @} */ /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source * @{ */ #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK /** * @} */ /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source * @{ */ /* ADC1 & ADC2 */ #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 /** * @} */ /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source * @{ */ #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT /** * @} */ /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source * @{ */ #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL /** * @} */ /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source * @{ */ #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI /** * @} */ /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source * @{ */ #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI /** * @} */ #endif /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source * @{ */ #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI /** * @} */ /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source * @{ */ #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK /** * @} */ /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source * @{ */ #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK /** * @} */ /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source * @{ */ /* ADC1 & ADC2 */ #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 /** * @} */ /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source * @{ */ #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT /** * @} */ /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source * @{ */ #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL /** * @} */ /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source * @{ */ #define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK #define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL /** * @} */ /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source * @{ */ #define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK #define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL /** * @} */ /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source * @{ */ #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL /** * @} */ /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source * @{ */ #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL /** * @} */ /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source * @{ */ #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL /** * @} */ /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source * @{ */ #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI /** * @} */ /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source * @{ */ #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI /** * @} */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx) /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source * @{ */ #define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK #define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL /** * @} */ #endif /* STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source * @{ */ /* ADC3 & ADC4 */ #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1 #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2 #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4 #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6 #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8 #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10 #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12 #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16 #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32 #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64 #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128 #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256 /** * @} */ /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source * @{ */ #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL /** * @} */ #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source * @{ */ #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI /** * @} */ /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source * @{ */ /* ADC1 & ADC2 */ #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 /** * @} */ /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source * @{ */ #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL /** * @} */ #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F334x8) /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source * @{ */ #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL /** * @} */ #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source * @{ */ #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI /** * @} */ /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source * @{ */ #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK /** * @} */ /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source * @{ */ /* ADC1 */ #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 /** * @} */ /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source * @{ */ #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /** * @} */ /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler * @{ */ #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDPRE_DIV1 #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDPRE_DIV2 #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDPRE_DIV4 #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDPRE_DIV6 #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDPRE_DIV8 #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDPRE_DIV10 #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDPRE_DIV12 #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDPRE_DIV14 #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDPRE_DIV16 #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDPRE_DIV20 #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDPRE_DIV24 #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDPRE_DIV28 #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDPRE_DIV32 #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDPRE_DIV36 #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDPRE_DIV40 #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDPRE_DIV44 #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDPRE_DIV48 /** * @} */ #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) /** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source * @{ */ #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 #define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5 /** * @} */ #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler * @{ */ #if defined(RCC_CFGR_MCOPRE) #define RCC_MCODIV_1 (0x00000000U) #define RCC_MCODIV_2 (0x10000000U) #define RCC_MCODIV_4 (0x20000000U) #define RCC_MCODIV_8 (0x30000000U) #define RCC_MCODIV_16 (0x40000000U) #define RCC_MCODIV_32 (0x50000000U) #define RCC_MCODIV_64 (0x60000000U) #define RCC_MCODIV_128 (0x70000000U) #else #define RCC_MCODIV_1 (0x00000000U) #endif /* RCC_CFGR_MCOPRE */ /** * @} */ /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration * @{ */ #define RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros * @{ */ /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) /** @brief Macro to configure the PLL clock source, multiplication and division factors. * @note This macro must be used only when the PLL is disabled. * * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. * */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ do { \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ } while(0U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) /** @brief Macro to configure the PLL clock source and multiplication factor. * @note This macro must be used only when the PLL is disabled. * * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. * */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))) #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /* STM32F373xC || STM32F378xx */ /** * @} */ #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration * @{ */ /** * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. * @note Predivision factor can not be changed if PLL is used as system clock * In this case, you have to select another source of the system clock, disable the PLL and * then change the HSE predivision factor. * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. */ #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__)) /** * @brief Macro to get prediv1 factor for PLL. */ #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV) /** * @} */ #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /* STM32F373xC || STM32F378xx */ /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable * @brief Enable or disable the AHB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN)) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ UNUSED(tmpreg); \ } while(0U) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_ADC34_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN)) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\ UNUSED(tmpreg); \ } while(0U) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE() #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE() #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM18_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_CEC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) #define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN)) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F303xE) || defined(STM32F398xx) \ || defined(STM32F303xC) || defined(STM32F358xx) \ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) #define __HAL_RCC_USB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ #if !defined(STM32F301x8) #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) #endif /* STM32F301x8*/ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F334x8) #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN)) #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM19_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SDADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SDADC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SDADC3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) #define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN)) #define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN)) #define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN)) #define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN)) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_TIM20_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\ UNUSED(tmpreg); \ } while(0U) #define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN)) #endif /* STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the AHB peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET) #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET) #define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET) #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET) #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET) #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET) #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) #define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET) #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) #define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET) #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F303xE) || defined(STM32F398xx) \ || defined(STM32F303xC) || defined(STM32F358xx) \ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ #if !defined(STM32F301x8) #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET) #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET) #endif /* STM32F301x8*/ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status * @brief Get the enable or disable status of the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F334x8) #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET) #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET) #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET) #define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET) #define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET) #define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET) #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) #define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET) #define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET) #define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET) #define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET) #define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET) #endif /* STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset * @brief Force or release AHB peripheral reset. * @{ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST)) #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST)) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST)) #define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST)) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET() #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) /* Aliases for STM32 F3 compatibility */ #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET() #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST)) #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST)) #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) #define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ #if !defined(STM32F301x8) #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) #endif /* STM32F301x8*/ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ /** * @} */ /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F334x8) #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST)) #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST)) #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST)) #define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST)) #define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST)) #define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST)) #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) #define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST)) #define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST)) #define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST)) #define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST)) #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx) #define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST)) #define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST)) #endif /* STM32F303xE || STM32F398xx */ /** * @} */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config * @{ */ /** @brief Macro to configure the I2C2 clock (I2C2CLK). * @param __I2C2CLKSource__ specifies the I2C2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) /** @brief Macro to configure the I2C3 clock (I2C3CLK). * @param __I2C3CLKSource__ specifies the I2C3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) /** * @} */ /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config * @{ */ /** @brief Macro to configure the TIM1 clock (TIM1CLK). * @param __TIM1CLKSource__ specifies the TIM1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock */ #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) /** @brief Macro to get the TIM1 clock (TIM1CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock */ #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) /** @brief Macro to configure the TIM15 clock (TIM15CLK). * @param __TIM15CLKSource__ specifies the TIM15 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock */ #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) /** @brief Macro to get the TIM15 clock (TIM15CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock */ #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) /** @brief Macro to configure the TIM16 clock (TIM16CLK). * @param __TIM16CLKSource__ specifies the TIM16 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock */ #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) /** @brief Macro to get the TIM16 clock (TIM16CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock */ #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) /** @brief Macro to configure the TIM17 clock (TIM17CLK). * @param __TIM17CLKSource__ specifies the TIM17 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock */ #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) /** @brief Macro to get the TIM17 clock (TIM17CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock */ #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) /** * @} */ /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config * @{ */ /** @brief Macro to configure the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. * @param __I2SCLKSource__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin * used as I2S clock source */ #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) /** @brief Macro to get the I2S clock source (I2SCLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin * used as I2S clock source */ #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) /** * @} */ /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config * @{ */ /** @brief Macro to configure the ADC1 clock (ADC1CLK). * @param __ADC1CLKSource__ specifies the ADC1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock */ #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__)) /** @brief Macro to get the ADC1 clock * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock */ #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES))) /** * @} */ #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config * @{ */ /** @brief Macro to configure the I2C2 clock (I2C2CLK). * @param __I2C2CLKSource__ specifies the I2C2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) /** * @} */ /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config * @{ */ /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock */ #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) /** @brief Macro to get the ADC1 & ADC2 clock * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock */ #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) /** * @} */ /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config * @{ */ /** @brief Macro to configure the TIM1 clock (TIM1CLK). * @param __TIM1CLKSource__ specifies the TIM1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock */ #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) /** @brief Macro to get the TIM1 clock (TIM1CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock */ #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) /** * @} */ /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config * @{ */ /** @brief Macro to configure the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. * @param __I2SCLKSource__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin * used as I2S clock source */ #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) /** @brief Macro to get the I2S clock source (I2SCLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin * used as I2S clock source */ #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) /** * @} */ /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config * @{ */ /** @brief Macro to configure the UART4 clock (UART4CLK). * @param __UART4CLKSource__ specifies the UART4 clock source. * This parameter can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock */ #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__)) /** @brief Macro to get the UART4 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock */ #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW))) /** @brief Macro to configure the UART5 clock (UART5CLK). * @param __UART5CLKSource__ specifies the UART5 clock source. * This parameter can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock */ #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__)) /** @brief Macro to get the UART5 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock */ #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW))) /** * @} */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config * @{ */ /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK). * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock */ #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__)) /** @brief Macro to get the ADC3 & ADC4 clock * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock */ #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34))) /** * @} */ /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config * @{ */ /** @brief Macro to configure the TIM8 clock (TIM8CLK). * @param __TIM8CLKSource__ specifies the TIM8 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock */ #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__)) /** @brief Macro to get the TIM8 clock (TIM8CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock */ #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW))) /** * @} */ #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config * @{ */ /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock */ #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) /** @brief Macro to get the ADC1 & ADC2 clock * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock */ #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) /** * @} */ /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config * @{ */ /** @brief Macro to configure the TIM1 clock (TIM1CLK). * @param __TIM1CLKSource__ specifies the TIM1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock */ #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) /** @brief Macro to get the TIM1 clock (TIM1CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock */ #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) /** * @} */ #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F334x8) /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config * @{ */ /** @brief Macro to configure the HRTIM1 clock. * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock */ #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__)) /** @brief Macro to get the HRTIM1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock */ #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW))) /** * @} */ #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config * @{ */ /** @brief Macro to configure the I2C2 clock (I2C2CLK). * @param __I2C2CLKSource__ specifies the I2C2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) /** * @} */ /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config * @{ */ /** @brief Macro to configure the ADC1 clock (ADC1CLK). * @param __ADC1CLKSource__ specifies the ADC1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock */ #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__)) /** @brief Macro to get the ADC1 clock (ADC1CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock */ #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) /** * @} */ /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config * @{ */ /** @brief Macro to configure the SDADCx clock (SDADCxCLK). * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock */ #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, (uint32_t)(__SDADCPrescaler__)) /** @brief Macro to get the SDADCx clock prescaler. * @retval The clock source can be one of the following values: * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock */ #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDPRE))) /** * @} */ /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config * @{ */ /** @brief Macro to configure the CEC clock. * @param __CECCLKSource__ specifies the CEC clock source. * This parameter can be one of the following values: * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock */ #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__)) /** @brief Macro to get the HDMI CEC clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock */ #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) /** * @} */ #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config * @{ */ /** @brief Macro to configure the USB clock (USBCLK). * @param __USBCLKSource__ specifies the USB clock source. * This parameter can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock */ #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) /** * @} */ #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config * @{ */ /** @brief Macro to configure the I2C3 clock (I2C3CLK). * @param __I2C3CLKSource__ specifies the I2C3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) /** * @} */ /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config * @{ */ /** @brief Macro to configure the TIM2 clock (TIM2CLK). * @param __TIM2CLKSource__ specifies the TIM2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock */ #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__)) /** @brief Macro to get the TIM2 clock (TIM2CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock */ #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW))) /** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK). * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock */ #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__)) /** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock */ #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW))) /** @brief Macro to configure the TIM15 clock (TIM15CLK). * @param __TIM15CLKSource__ specifies the TIM15 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock */ #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) /** @brief Macro to get the TIM15 clock (TIM15CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock */ #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) /** @brief Macro to configure the TIM16 clock (TIM16CLK). * @param __TIM16CLKSource__ specifies the TIM16 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock */ #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) /** @brief Macro to get the TIM16 clock (TIM16CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock */ #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) /** @brief Macro to configure the TIM17 clock (TIM17CLK). * @param __TIM17CLKSource__ specifies the TIM17 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock */ #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) /** @brief Macro to get the TIM17 clock (TIM17CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock */ #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) /** * @} */ #endif /* STM32f302xE || STM32f303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx) /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config * @{ */ /** @brief Macro to configure the TIM20 clock (TIM20CLK). * @param __TIM20CLKSource__ specifies the TIM20 clock source. * This parameter can be one of the following values: * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock */ #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__)) /** @brief Macro to get the TIM20 clock (TIM20CLK). * @retval The clock source can be one of the following values: * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock */ #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW))) /** * @} */ #endif /* STM32f303xE || STM32F398xx */ /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. * @retval None */ #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\ RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCCEx_Exported_Functions * @{ */ /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_HAL_RCC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_tim.h * @author MCD Application Team * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F3xx_HAL_TIM_H #define STM32F3xx_HAL_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIM_Exported_Types TIM Exported Types * @{ */ /** * @brief TIM Time base Configuration Structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** * @brief TIM Output Compare Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ } TIM_OC_InitTypeDef; /** * @brief TIM One Pulse Mode Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; /** * @brief TIM Input Capture Configuration Structure definition */ typedef struct { uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_IC_InitTypeDef; /** * @brief TIM Encoder Configuration Structure definition */ typedef struct { uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; /** * @brief Clock Configuration Handle Structure definition */ typedef struct { uint32_t ClockSource; /*!< TIM clock sources This parameter can be a value of @ref TIM_Clock_Source */ uint32_t ClockPolarity; /*!< TIM clock polarity This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ uint32_t ClockFilter; /*!< TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClockConfigTypeDef; /** * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { uint32_t ClearInputState; /*!< TIM clear Input state This parameter can be ENABLE or DISABLE */ uint32_t ClearInputSource; /*!< TIM clear Input sources This parameter can be a value of @ref TIM_ClearInput_Source */ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; /** * @brief TIM Master configuration Structure definition * @note Advanced timers provide TRGO2 internal line which is redirected * to the ADC */ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection This parameter can be a value of @ref TIM_Master_Mode_Selection */ #if defined(TIM_CR2_MMS2) uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ #endif /* TIM_CR2_MMS2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode @note When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode. */ } TIM_MasterConfigTypeDef; /** * @brief TIM Slave configuration Structure definition */ typedef struct { uint32_t SlaveMode; /*!< Slave mode selection This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_SlaveConfigTypeDef; /** * @brief TIM Break input(s) and Dead time configuration Structure definition * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable * filter and polarity. */ typedef struct { uint32_t OffStateRunMode; /*!< TIM off state in run mode This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t BreakState; /*!< TIM Break State This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint32_t BreakPolarity; /*!< TIM Break input polarity This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t BreakFilter; /*!< Specifies the break input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ #if defined(TIM_BDTR_BK2E) uint32_t Break2State; /*!< TIM Break2 State This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ uint32_t Break2Polarity; /*!< TIM Break2 input polarity This parameter can be a value of @ref TIM_Break2_Polarity */ uint32_t Break2Filter; /*!< TIM break2 input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ #endif /*TIM_BDTR_BK2E */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** * @brief HAL State structures definition */ typedef enum { HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; /** * @brief HAL Active channel structures definition */ typedef enum { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ #if defined(TIM_CCER_CC5E) HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ #endif /* TIM_CCER_CC6E */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; /** * @brief TIM Time Base Handle Structure definition */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) typedef struct __TIM_HandleTypeDef #else typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { TIM_TypeDef *Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ #if defined(TIM_BDTR_BK2E) void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ #endif /* */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } TIM_HandleTypeDef; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief HAL TIM Callback ID enumeration definition */ typedef enum { HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ #if defined(TIM_BDTR_BK2E) ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ #endif /* TIM_BDTR_BK2E */ } HAL_TIM_CallbackIDTypeDef; /** * @brief HAL TIM Callback pointer definition */ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_Constants TIM Exported Constants * @{ */ /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ #if defined(TIM_SMCR_OCCS) #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ #endif /* TIM_SMCR_OCCS */ /** * @} */ /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ #define TIM_DMABASE_CR1 0x00000000U #define TIM_DMABASE_CR2 0x00000001U #define TIM_DMABASE_SMCR 0x00000002U #define TIM_DMABASE_DIER 0x00000003U #define TIM_DMABASE_SR 0x00000004U #define TIM_DMABASE_EGR 0x00000005U #define TIM_DMABASE_CCMR1 0x00000006U #define TIM_DMABASE_CCMR2 0x00000007U #define TIM_DMABASE_CCER 0x00000008U #define TIM_DMABASE_CNT 0x00000009U #define TIM_DMABASE_PSC 0x0000000AU #define TIM_DMABASE_ARR 0x0000000BU #define TIM_DMABASE_RCR 0x0000000CU #define TIM_DMABASE_CCR1 0x0000000DU #define TIM_DMABASE_CCR2 0x0000000EU #define TIM_DMABASE_CCR3 0x0000000FU #define TIM_DMABASE_CCR4 0x00000010U #define TIM_DMABASE_BDTR 0x00000011U #define TIM_DMABASE_DCR 0x00000012U #define TIM_DMABASE_DMAR 0x00000013U #define TIM_DMABASE_OR 0x00000014U #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define TIM_DMABASE_CCMR3 0x00000015U #define TIM_DMABASE_CCR5 0x00000016U #define TIM_DMABASE_CCR6 0x00000017U #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @} */ /** @defgroup TIM_Event_Source TIM Event Source * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ #if defined(TIM_EGR_B2G) #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ #endif /* TIM_EGR_B2G */ /** * @} */ /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** * @} */ /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ /** * @} */ /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ /** * @} */ /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ /** * @} */ /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ /** * @} */ /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ /** * @} */ /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ /** * @} */ /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ /** * @} */ /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ /** * @} */ /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity * @{ */ #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ /** * @} */ /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ /** * @} */ /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ /** * @} */ /** @defgroup TIM_Interrupt_definition TIM interrupt Definition * @{ */ #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ /** * @} */ /** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** * @} */ /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ /** * @} */ /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ #if defined(TIM_SR_CC5IF) #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ #endif /* TIM_SR_CC5IF */ #if defined(TIM_SR_CC6IF) #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ #endif /* TIM_SR_CC6IF */ #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ #if defined(TIM_SR_B2IF) #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ #endif /* TIM_SR_B2IF */ #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ /** * @} */ /** @defgroup TIM_Channel TIM Channel * @{ */ #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ #if defined(TIM_CCER_CC5E) #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ #endif /* TIM_CCER_CC6E */ #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} */ /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** * @} */ /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ */ #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state * @{ */ #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state * @{ */ #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_Lock_level TIM Lock level * @{ */ #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ /** * @} */ /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable * @{ */ #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ /** * @} */ /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ /** * @} */ #if defined(TIM_BDTR_BK2E) /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ /** * @} */ /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity * @{ */ #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ /** * @} */ #endif /* TIM_BDTR_BK2E */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ #if defined(TIM_CCR5_CCR5) /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 * @{ */ #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ #endif /* TIM_CCR5_CCR5 */ /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ /** * @} */ #if defined(TIM_CR2_MMS2) /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ /** * @} */ #endif /* TIM_CR2_MMS2 */ /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ /** * @} */ /** @defgroup TIM_Slave_Mode TIM Slave mode * @{ */ #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ #if defined (TIM_SMCR_SMS_3) #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ #endif /* TIM_SMCR_SMS_3 */ /** * @} */ /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes * @{ */ #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ #if defined(TIM_CCMR1_OC1M_3) #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #endif /* TIM_CCMR1_OC1M_3 */ /** * @} */ /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} */ /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ /** * @} */ /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ /** * @} */ /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ /** @defgroup DMA_Handle_index TIM DMA Handle Index * @{ */ #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ /** @defgroup Channel_CC_State TIM Capture/Compare Channel State * @{ */ #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /** @defgroup TIM_Exported_Macros TIM Exported Macros * @{ */ /** @brief Reset TIM handle state. * @param __HANDLE__ TIM handle. * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->Base_MspInitCallback = NULL; \ (__HANDLE__)->Base_MspDeInitCallback = NULL; \ (__HANDLE__)->IC_MspInitCallback = NULL; \ (__HANDLE__)->IC_MspDeInitCallback = NULL; \ (__HANDLE__)->OC_MspInitCallback = NULL; \ (__HANDLE__)->OC_MspDeInitCallback = NULL; \ (__HANDLE__)->PWM_MspInitCallback = NULL; \ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ (__HANDLE__)->Encoder_MspInitCallback = NULL; \ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ } while(0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ } while(0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) /** @brief Disable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * (*) Value not defined for all devices * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Capture/Compare 5 interrupt flag (*) * @arg TIM_FLAG_CC5: Capture/Compare 6 interrupt flag (*) * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag (*) * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * (*) Value not defined for all devices * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** * @brief Check whether the specified TIM interrupt source is enabled or not. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval The state of TIM_IT (SET or RESET). */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) /** * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while(0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do{ \ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while(0) /** * @brief Get the TIM Clock Division value on runtime. * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do{ \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ } while(0) /** * @brief Get the TIM Input Capture prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval The input capture prescaler can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) #else #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Get the TIM Capture Compare Register value on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @arg TIM_CHANNEL_5: get capture/compare 5 register value (*) * @arg TIM_CHANNEL_6: get capture/compare 6 register value (*) * (*) Value not defined for all devices * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) #else #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ ((__HANDLE__)->Instance->CCR4)) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Set the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval None */ #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) #else #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Reset the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval None */ #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) #else #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Enable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @note When fast mode is enabled an active edge on the trigger input acts * like a compare match on CCx output. Delay to sample the trigger * input and to activate CCx output is reduced to 3 clock cycles. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. * @retval None */ #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) #else #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Disable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @note When fast mode is disabled CCx output behaves normally depending * on counter and CCRx values even when the trigger is ON. The minimum * delay to activate CCx output when an active edge occurs on the * trigger input is 5 clock cycles. * @retval None */ #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) #else #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit * _ Update generation through the slave mode controller * @retval None */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ do{ \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) /** * @} */ /* End of exported macros ----------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_Private_Constants TIM Private Constants * @{ */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} */ /* End of private constants --------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ #if defined(TIM_SMCR_OCCS) #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) #else #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) #endif /* TIM_SMCR_OCCS */ #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ ((__BASE__) == TIM_DMABASE_SMCR) || \ ((__BASE__) == TIM_DMABASE_DIER) || \ ((__BASE__) == TIM_DMABASE_SR) || \ ((__BASE__) == TIM_DMABASE_EGR) || \ ((__BASE__) == TIM_DMABASE_CCMR1) || \ ((__BASE__) == TIM_DMABASE_CCMR2) || \ ((__BASE__) == TIM_DMABASE_CCER) || \ ((__BASE__) == TIM_DMABASE_CNT) || \ ((__BASE__) == TIM_DMABASE_PSC) || \ ((__BASE__) == TIM_DMABASE_ARR) || \ ((__BASE__) == TIM_DMABASE_RCR) || \ ((__BASE__) == TIM_DMABASE_CCR1) || \ ((__BASE__) == TIM_DMABASE_CCR2) || \ ((__BASE__) == TIM_DMABASE_CCR3) || \ ((__BASE__) == TIM_DMABASE_CCR4) || \ ((__BASE__) == TIM_DMABASE_BDTR) || \ ((__BASE__) == TIM_DMABASE_CCMR3) || \ ((__BASE__) == TIM_DMABASE_CCR5) || \ ((__BASE__) == TIM_DMABASE_CCR6) || \ ((__BASE__) == TIM_DMABASE_OR)) #else #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ ((__BASE__) == TIM_DMABASE_SMCR) || \ ((__BASE__) == TIM_DMABASE_DIER) || \ ((__BASE__) == TIM_DMABASE_SR) || \ ((__BASE__) == TIM_DMABASE_EGR) || \ ((__BASE__) == TIM_DMABASE_CCMR1) || \ ((__BASE__) == TIM_DMABASE_CCMR2) || \ ((__BASE__) == TIM_DMABASE_CCER) || \ ((__BASE__) == TIM_DMABASE_CNT) || \ ((__BASE__) == TIM_DMABASE_PSC) || \ ((__BASE__) == TIM_DMABASE_ARR) || \ ((__BASE__) == TIM_DMABASE_RCR) || \ ((__BASE__) == TIM_DMABASE_CCR1) || \ ((__BASE__) == TIM_DMABASE_CCR2) || \ ((__BASE__) == TIM_DMABASE_CCR3) || \ ((__BASE__) == TIM_DMABASE_CCR4) || \ ((__BASE__) == TIM_DMABASE_BDTR) || \ ((__BASE__) == TIM_DMABASE_OR)) #endif /* TIM_CCER_CC5E && TIM_CCER_CC6E */ #if defined(TIM_EGR_B2G) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #else #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #endif /* TIM_EGR_B2G */ #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ ((__STATE__) == TIM_OCFAST_ENABLE)) #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ ((__POLARITY__) == TIM_OCPOLARITY_LOW)) #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ ((__STATE__) == TIM_OCIDLESTATE_RESET)) #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ ((__SELECTION__) == TIM_ICSELECTION_TRC)) #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12)) #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #if defined(TIM_CCER_CC5E) && defined(TIM_CCER_CC6E) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4) || \ ((__CHANNEL__) == TIM_CHANNEL_5) || \ ((__CHANNEL__) == TIM_CHANNEL_6) || \ ((__CHANNEL__) == TIM_CHANNEL_ALL)) #else #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4) || \ ((__CHANNEL__) == TIM_CHANNEL_ALL)) #endif /* TIM_CCER_CC5E &&TIM_CCER_CC6E */ #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ ((__STATE__) == TIM_OSSR_DISABLE)) #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ ((__STATE__) == TIM_OSSI_DISABLE)) #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ ((__LEVEL__) == TIM_LOCKLEVEL_3)) #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) #if defined(TIM_BDTR_BK2E) #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ ((__STATE__) == TIM_BREAK2_DISABLE)) #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) #endif /* TIM_BDTR_BK2E */ #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) #if defined(TIM_CCR5_CCR5) #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) #endif /* TIM_CCR5_CCR5 */ #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ ((__SOURCE__) == TIM_TRGO_ENABLE) || \ ((__SOURCE__) == TIM_TRGO_UPDATE) || \ ((__SOURCE__) == TIM_TRGO_OC1) || \ ((__SOURCE__) == TIM_TRGO_OC1REF) || \ ((__SOURCE__) == TIM_TRGO_OC2REF) || \ ((__SOURCE__) == TIM_TRGO_OC3REF) || \ ((__SOURCE__) == TIM_TRGO_OC4REF)) #if defined(TIM_CR2_MMS2) #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ ((__SOURCE__) == TIM_TRGO2_OC1) || \ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) #endif /* TIM_CR2_MMS2 */ #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) #if defined (TIM_SMCR_SMS_3) #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ ((__MODE__) == TIM_SLAVEMODE_RESET) || \ ((__MODE__) == TIM_SLAVEMODE_GATED) || \ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #else #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ ((__MODE__) == TIM_SLAVEMODE_RESET) || \ ((__MODE__) == TIM_SLAVEMODE_GATED) || \ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) #endif /* TIM_SMCR_SMS_3 */ #if defined(TIM_CCMR1_OC1M_3) #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) #else #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ ((__MODE__) == TIM_OCMODE_PWM2)) #endif /* TIM_CCMR1_OC1M_3 */ #if defined(TIM_CCMR1_OC1M_3) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_INACTIVE) || \ ((__MODE__) == TIM_OCMODE_TOGGLE) || \ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) #else #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_INACTIVE) || \ ((__MODE__) == TIM_OCMODE_TOGGLE) || \ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) #endif /* TIM_CCMR1_OC1M_3 */ #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_NONE)) #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) #if defined (TIM_SMCR_SMS_3) #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #else #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) #endif /* TIM_SMCR_SMS_3 */ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) /** * @} */ /* End of private macros -----------------------------------------------------*/ /* Include TIM HAL Extended module */ #include "stm32f3xx_hal_tim_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @{ */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @{ */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @{ */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @{ */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @{ */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @{ */ /* Timer Encoder functions ****************************************************/ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief IRQ handler management * @{ */ /* Interrupt Handler functions ***********************************************/ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief Peripheral State functions * @{ */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F3xx_HAL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_tim_ex.h * @author MCD Application Team * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32F3xx_HAL_TIM_EX_H #define STM32F3xx_HAL_TIM_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal_def.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup TIMEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types * @{ */ /** * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants * @{ */ /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ #if defined(TIM1) #define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */ #define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */ #if defined(ADC4) #define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */ #define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */ #define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */ #elif defined(ADC2) #define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/ #define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */ #define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */ #define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */ #endif /* ADC4 */ #endif /* TIM1 */ #if defined(TIM8) #define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ #define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */ #define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */ #define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */ #define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */ #define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */ #define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */ #endif /* TIM8 */ #if defined(TIM14) #define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */ #define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */ #define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */ #define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */ #endif /* TIM14 */ #if defined(TIM16) #define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */ #define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */ #define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32 */ #define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */ #endif /* TIM16 */ #if defined(TIM20) #define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ #define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */ #define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */ #define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */ #define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */ #define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */ #define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */ #define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */ #endif /* TIM20 */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros * @{ */ /** * @} */ /* End of exported macro -----------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros * @{ */ #if defined(TIM1) && defined(TIM8) && defined(TIM20) && defined(TIM16) #define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ || (((__INSTANCE__) == TIM20) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) #elif defined(TIM1) && defined(TIM8) && defined(TIM16) #define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) #elif defined(TIM1) && defined(TIM16) #define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \ || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)))) #elif defined(TIM14) #define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ (((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)) #endif /* TIM1 && TIM8 && TIM20 && TIM16 */ /** * @} */ /* End of private macro ------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ /* Timer Hall Sensor functions **********************************************/ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @{ */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @{ */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @{ */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Extended Control functions ************************************************/ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); #if defined(TIM_CCR5_CCR5) HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); #endif /* TIM_CCR5_CCR5 */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ /* Extended Callback **********************************************************/ void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); #if defined(TIM_BDTR_BK2E) void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); #endif /* TIM_BDTR_BK2E */ /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32F3xx_HAL_TIM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_bus.h * @author MCD Application Team * @brief Header file of BUS LL module. @verbatim ##### RCC Limitations ##### ============================================================================== [..] A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each LL_{BUS}_GRP{x}_EnableClock() function. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_BUS_H #define __STM32F3xx_LL_BUS_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined(RCC) /** @defgroup BUS_LL BUS * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants * @{ */ /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH * @{ */ #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN #if defined(DMA2) #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN #endif /*DMA2*/ #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN #if defined(FMC_Bank1) #define LL_AHB1_GRP1_PERIPH_FMC RCC_AHBENR_FMCEN #endif /*FMC_Bank1*/ #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN #if defined(GPIOH) #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN #endif /*GPIOH*/ #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN #if defined(GPIOE) #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN #endif /*GPIOE*/ #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN #if defined(GPIOG) #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN #endif /*GPIOH*/ #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN #if defined(RCC_AHBENR_ADC1EN) #define LL_AHB1_GRP1_PERIPH_ADC1 RCC_AHBENR_ADC1EN #endif /*RCC_AHBENR_ADC1EN*/ #if defined(ADC1_2_COMMON) #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHBENR_ADC12EN #endif /*ADC1_2_COMMON*/ #if defined(ADC3_4_COMMON) #define LL_AHB1_GRP1_PERIPH_ADC34 RCC_AHBENR_ADC34EN #endif /*ADC3_4_COMMON*/ /** * @} */ /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH * @{ */ #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN #if defined(TIM3) #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN #endif /*TIM3*/ #if defined(TIM4) #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN #endif /*TIM4*/ #if defined(TIM5) #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN #endif /*TIM5*/ #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN #if defined(TIM7) #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN #endif /*TIM7*/ #if defined(TIM12) #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN #endif /*TIM12*/ #if defined(TIM13) #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN #endif /*TIM13*/ #if defined(TIM14) #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN #endif /*TIM14*/ #if defined(TIM18) #define LL_APB1_GRP1_PERIPH_TIM18 RCC_APB1ENR_TIM18EN #endif /*TIM18*/ #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN #if defined(SPI2) #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN #endif /*SPI2*/ #if defined(SPI3) #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN #endif /*SPI3*/ #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN #if defined(UART4) #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN #endif /*UART4*/ #if defined(UART5) #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN #endif /*UART5*/ #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN #if defined(I2C2) #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN #endif /*I2C2*/ #if defined(USB) #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN #endif /*USB*/ #if defined(CAN) #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN #endif /*CAN*/ #if defined(DAC2) #define LL_APB1_GRP1_PERIPH_DAC2 RCC_APB1ENR_DAC2EN #endif /*DAC2*/ #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DAC1EN #if defined(CEC) #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN #endif /*CEC*/ #if defined(I2C3) #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN #endif /*I2C3*/ /** * @} */ /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH * @{ */ #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN #if defined(RCC_APB2ENR_ADC1EN) #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN #endif /*RCC_APB2ENR_ADC1EN*/ #if defined(TIM1) #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN #endif /*TIM1*/ #if defined(SPI1) #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN #endif /*SPI1*/ #if defined(TIM8) #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN #endif /*TIM8*/ #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN #if defined(SPI4) #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN #endif /*SPI4*/ #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN #if defined(TIM19) #define LL_APB2_GRP1_PERIPH_TIM19 RCC_APB2ENR_TIM19EN #endif /*TIM19*/ #if defined(TIM20) #define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN #endif /*TIM20*/ #if defined(HRTIM1) #define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN #endif /*HRTIM1*/ #if defined(SDADC1) #define LL_APB2_GRP1_PERIPH_SDADC1 RCC_APB2ENR_SDADC1EN #endif /*SDADC1*/ #if defined(SDADC2) #define LL_APB2_GRP1_PERIPH_SDADC2 RCC_APB2ENR_SDADC2EN #endif /*SDADC2*/ #if defined(SDADC3) #define LL_APB2_GRP1_PERIPH_SDADC3 RCC_APB2ENR_SDADC3EN #endif /*SDADC3*/ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions * @{ */ /** @defgroup BUS_LL_EF_AHB1 AHB1 * @{ */ /** * @brief Enable AHB1 peripherals clock. * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n * AHBENR FMCEN LL_AHB1_GRP1_EnableClock\n * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n * AHBENR ADC1EN LL_AHB1_GRP1_EnableClock\n * AHBENR ADC12EN LL_AHB1_GRP1_EnableClock\n * AHBENR ADC34EN LL_AHB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; SET_BIT(RCC->AHBENR, Periphs); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, Periphs); (void)tmpreg; } /** * @brief Check if AHB1 peripheral clock is enabled or not * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR FMCEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR ADC1EN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n * AHBENR ADC34EN LL_AHB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); } /** * @brief Disable AHB1 peripherals clock. * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n * AHBENR FMCEN LL_AHB1_GRP1_DisableClock\n * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n * AHBENR ADC1EN LL_AHB1_GRP1_DisableClock\n * AHBENR ADC12EN LL_AHB1_GRP1_DisableClock\n * AHBENR ADC34EN LL_AHB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->AHBENR, Periphs); } /** * @brief Force AHB1 peripherals reset. * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR ADC1RST LL_AHB1_GRP1_ForceReset\n * AHBRSTR ADC12RST LL_AHB1_GRP1_ForceReset\n * AHBRSTR ADC34RST LL_AHB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->AHBRSTR, Periphs); } /** * @brief Release AHB1 peripherals reset. * @rmtoll AHBRSTR FMCRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR ADC1RST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n * AHBRSTR ADC34RST LL_AHB1_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_FMC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ADC34 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->AHBRSTR, Periphs); } /** * @} */ /** @defgroup BUS_LL_EF_APB1 APB1 * @{ */ /** * @brief Enable APB1 peripherals clock. * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n * APB1ENR TIM18EN LL_APB1_GRP1_EnableClock\n * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n * APB1ENR DAC2EN LL_APB1_GRP1_EnableClock\n * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n * APB1ENR DAC1EN LL_APB1_GRP1_EnableClock\n * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_PWR * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; SET_BIT(RCC->APB1ENR, Periphs); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB1ENR, Periphs); (void)tmpreg; } /** * @brief Check if APB1 peripheral clock is enabled or not * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR TIM18EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR DAC2EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR DAC1EN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_PWR * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); } /** * @brief Disable APB1 peripherals clock. * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n * APB1ENR TIM18EN LL_APB1_GRP1_DisableClock\n * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n * APB1ENR DAC2EN LL_APB1_GRP1_DisableClock\n * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n * APB1ENR DAC1EN LL_APB1_GRP1_DisableClock\n * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_PWR * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB1ENR, Periphs); } /** * @brief Force APB1 peripherals reset. * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n * APB1RSTR TIM18RST LL_APB1_GRP1_ForceReset\n * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n * APB1RSTR DAC2RST LL_APB1_GRP1_ForceReset\n * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n * APB1RSTR DAC1RST LL_APB1_GRP1_ForceReset\n * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_PWR * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB1RSTR, Periphs); } /** * @brief Release APB1 peripherals reset. * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR TIM18RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR DAC2RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR DAC1RST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB1_GRP1_PERIPH_ALL * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) * @arg @ref LL_APB1_GRP1_PERIPH_TIM18 (*) * @arg @ref LL_APB1_GRP1_PERIPH_WWDG * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USART2 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) * @arg @ref LL_APB1_GRP1_PERIPH_DAC2 (*) * @arg @ref LL_APB1_GRP1_PERIPH_PWR * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB1RSTR, Periphs); } /** * @} */ /** @defgroup BUS_LL_EF_APB2 APB2 * @{ */ /** * @brief Enable APB2 peripherals clock. * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM19EN LL_APB2_GRP1_EnableClock\n * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SDADC1EN LL_APB2_GRP1_EnableClock\n * APB2ENR SDADC2EN LL_APB2_GRP1_EnableClock\n * APB2ENR SDADC3EN LL_APB2_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USART1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; SET_BIT(RCC->APB2ENR, Periphs); /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, Periphs); (void)tmpreg; } /** * @brief Check if APB2 peripheral clock is enabled or not * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM19EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SDADC1EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SDADC2EN LL_APB2_GRP1_IsEnabledClock\n * APB2ENR SDADC3EN LL_APB2_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USART1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); } /** * @brief Disable APB2 peripherals clock. * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM19EN LL_APB2_GRP1_DisableClock\n * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SDADC1EN LL_APB2_GRP1_DisableClock\n * APB2ENR SDADC2EN LL_APB2_GRP1_DisableClock\n * APB2ENR SDADC3EN LL_APB2_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USART1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB2ENR, Periphs); } /** * @brief Force APB2 peripherals reset. * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM19RST LL_APB2_GRP1_ForceReset\n * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SDADC1RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SDADC2RST LL_APB2_GRP1_ForceReset\n * APB2RSTR SDADC3RST LL_APB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USART1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB2RSTR, Periphs); } /** * @brief Release APB2 peripherals reset. * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM19RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR TIM20RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR HRTIM1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SDADC1RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SDADC2RST LL_APB2_GRP1_ReleaseReset\n * APB2RSTR SDADC3RST LL_APB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_APB2_GRP1_PERIPH_ALL * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) * @arg @ref LL_APB2_GRP1_PERIPH_USART1 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 * @arg @ref LL_APB2_GRP1_PERIPH_TIM19 (*) * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*) * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC1 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC2 (*) * @arg @ref LL_APB2_GRP1_PERIPH_SDADC3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB2RSTR, Periphs); } /** * @} */ /** * @} */ /** * @} */ #endif /* defined(RCC) */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_BUS_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_cortex.h * @author MCD Application Team * @brief Header file of CORTEX LL module. @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick functions (+) Low power mode configuration (SCB register of Cortex-MCU) (+) MPU API to configure and enable regions (MPU services provided only on some devices) (+) API to access to MCU info (CPUID register) (+) API to enable fault handler (SHCSR accesses) @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_CORTEX_H #define __STM32F3xx_LL_CORTEX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ /** @defgroup CORTEX_LL CORTEX * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants * @{ */ /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source * @{ */ #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ /** * @} */ /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type * @{ */ #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ /** * @} */ #if __MPU_PRESENT /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control * @{ */ #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ /** * @} */ /** @defgroup CORTEX_LL_EC_REGION MPU Region Number * @{ */ #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ /** * @} */ /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size * @{ */ #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ /** * @} */ /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges * @{ */ #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ /** * @} */ /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level * @{ */ #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ /** * @} */ /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access * @{ */ #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ /** * @} */ /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access * @{ */ #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ /** * @} */ /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access * @{ */ #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ /** * @} */ /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access * @{ */ #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions * @{ */ /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK * @{ */ /** * @brief This function checks if the Systick counter flag is active or not. * @note It can be used in timeout function on application side. * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) { return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); } /** * @brief Configures the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK * @retval None */ __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) { if (Source == LL_SYSTICK_CLKSOURCE_HCLK) { SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); } else { CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); } } /** * @brief Get the SysTick clock source * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource * @retval Returned value can be one of the following values: * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK */ __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) { return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); } /** * @brief Enable SysTick exception request * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT * @retval None */ __STATIC_INLINE void LL_SYSTICK_EnableIT(void) { SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Disable SysTick exception request * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT * @retval None */ __STATIC_INLINE void LL_SYSTICK_DisableIT(void) { CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Checks if the SYSTICK interrupt is enabled or disabled. * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) { return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); } /** * @} */ /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE * @{ */ /** * @brief Processor uses sleep as its low power mode * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep * @retval None */ __STATIC_INLINE void LL_LPM_EnableSleep(void) { /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Processor uses deep sleep as its low power mode * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep * @retval None */ __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) { /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an * empty main application. * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit * @retval None */ __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) { /* Set SLEEPONEXIT bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Do not sleep when returning to Thread mode. * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit * @retval None */ __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) { /* Clear SLEEPONEXIT bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the * processor. * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend * @retval None */ __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) { /* Set SEVEONPEND bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are * excluded * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend * @retval None */ __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) { /* Clear SEVEONPEND bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @} */ /** @defgroup CORTEX_LL_EF_HANDLER HANDLER * @{ */ /** * @brief Enable a fault in System handler control register (SHCSR) * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault * @param Fault This parameter can be a combination of the following values: * @arg @ref LL_HANDLER_FAULT_USG * @arg @ref LL_HANDLER_FAULT_BUS * @arg @ref LL_HANDLER_FAULT_MEM * @retval None */ __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) { /* Enable the system handler fault */ SET_BIT(SCB->SHCSR, Fault); } /** * @brief Disable a fault in System handler control register (SHCSR) * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault * @param Fault This parameter can be a combination of the following values: * @arg @ref LL_HANDLER_FAULT_USG * @arg @ref LL_HANDLER_FAULT_BUS * @arg @ref LL_HANDLER_FAULT_MEM * @retval None */ __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) { /* Disable the system handler fault */ CLEAR_BIT(SCB->SHCSR, Fault); } /** * @} */ /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO * @{ */ /** * @brief Get Implementer code * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer * @retval Value should be equal to 0x41 for ARM */ __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) { return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); } /** * @brief Get Variant number (The r value in the rnpn product revision identifier) * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant * @retval Value between 0 and 255 (0x0: revision 0) */ __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) { return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); } /** * @brief Get Constant number * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant * @retval Value should be equal to 0xF for Cortex-M4 devices */ __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) { return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); } /** * @brief Get Part number * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo * @retval Value should be equal to 0xC24 for Cortex-M4 */ __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) { return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); } /** * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision * @retval Value between 0 and 255 (0x1: patch 1) */ __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) { return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); } /** * @} */ #if __MPU_PRESENT /** @defgroup CORTEX_LL_EF_MPU MPU * @{ */ /** * @brief Enable MPU with input options * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable * @param Options This parameter can be one of the following values: * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF * @retval None */ __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) { /* Enable the MPU*/ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); /* Ensure MPU settings take effects */ __DSB(); /* Sequence instruction fetches using update settings */ __ISB(); } /** * @brief Disable MPU * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable * @retval None */ __STATIC_INLINE void LL_MPU_Disable(void) { /* Make sure outstanding transfers are done */ __DMB(); /* Disable MPU*/ WRITE_REG(MPU->CTRL, 0U); } /** * @brief Check if MPU is enabled or not * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) { return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); } /** * @brief Enable a MPU region * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion * @param Region This parameter can be one of the following values: * @arg @ref LL_MPU_REGION_NUMBER0 * @arg @ref LL_MPU_REGION_NUMBER1 * @arg @ref LL_MPU_REGION_NUMBER2 * @arg @ref LL_MPU_REGION_NUMBER3 * @arg @ref LL_MPU_REGION_NUMBER4 * @arg @ref LL_MPU_REGION_NUMBER5 * @arg @ref LL_MPU_REGION_NUMBER6 * @arg @ref LL_MPU_REGION_NUMBER7 * @retval None */ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU->RNR, Region); /* Enable the MPU region */ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); } /** * @brief Configure and enable a region * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n * MPU_RBAR REGION LL_MPU_ConfigRegion\n * MPU_RBAR ADDR LL_MPU_ConfigRegion\n * MPU_RASR XN LL_MPU_ConfigRegion\n * MPU_RASR AP LL_MPU_ConfigRegion\n * MPU_RASR S LL_MPU_ConfigRegion\n * MPU_RASR C LL_MPU_ConfigRegion\n * MPU_RASR B LL_MPU_ConfigRegion\n * MPU_RASR SIZE LL_MPU_ConfigRegion * @param Region This parameter can be one of the following values: * @arg @ref LL_MPU_REGION_NUMBER0 * @arg @ref LL_MPU_REGION_NUMBER1 * @arg @ref LL_MPU_REGION_NUMBER2 * @arg @ref LL_MPU_REGION_NUMBER3 * @arg @ref LL_MPU_REGION_NUMBER4 * @arg @ref LL_MPU_REGION_NUMBER5 * @arg @ref LL_MPU_REGION_NUMBER6 * @arg @ref LL_MPU_REGION_NUMBER7 * @param Address Value of region base address * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF * @param Attributes This parameter can be a combination of the following values: * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE * @retval None */ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) { /* Set Region number */ WRITE_REG(MPU->RNR, Region); /* Set base address */ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); /* Configure MPU */ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); } /** * @brief Disable a region * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n * MPU_RASR ENABLE LL_MPU_DisableRegion * @param Region This parameter can be one of the following values: * @arg @ref LL_MPU_REGION_NUMBER0 * @arg @ref LL_MPU_REGION_NUMBER1 * @arg @ref LL_MPU_REGION_NUMBER2 * @arg @ref LL_MPU_REGION_NUMBER3 * @arg @ref LL_MPU_REGION_NUMBER4 * @arg @ref LL_MPU_REGION_NUMBER5 * @arg @ref LL_MPU_REGION_NUMBER6 * @arg @ref LL_MPU_REGION_NUMBER7 * @retval None */ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) { /* Set Region number */ WRITE_REG(MPU->RNR, Region); /* Disable the MPU region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); } /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_CORTEX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dac.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_dac.h * @author MCD Application Team * @brief Header file of DAC LL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_DAC_H #define __STM32F3xx_LL_DAC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (DAC1) || defined (DAC2) /** @defgroup DAC_LL DAC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup DAC_LL_Private_Constants DAC Private Constants * @{ */ /* Internal masks for DAC channels definition */ /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ /* - channel bits position into register CR */ /* - channel bits position into register SWTRIG */ /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ #if defined(DAC_CHANNEL2_SUPPORT) #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) #else #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) #endif /* DAC_CHANNEL2_SUPPORT */ #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #if defined(DAC_CHANNEL2_SUPPORT) #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ #endif /* DAC_CHANNEL2_SUPPORT */ #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ #if defined(DAC_CHANNEL2_SUPPORT) #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) #else #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) #endif /* DAC_CHANNEL2_SUPPORT */ /* DAC registers bits positions */ #if defined(DAC_CHANNEL2_SUPPORT) #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ #endif /* DAC_CHANNEL2_SUPPORT */ /* Miscellaneous data */ #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DAC_LL_Private_Macros DAC Private Macros * @{ */ /** * @brief Driver macro reserved for internal use: isolate bits with the * selected mask and shift them to the register LSB * (shift mask on register position bit 0). * @param __BITS__ Bits in register 32 bits * @param __MASK__ Mask in register 32 bits * @retval Bits in register 32 bits */ #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). * @retval Pointer to register address */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) /** * @} */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure * @{ */ /** * @brief Structure definition of some features of DAC instance. */ typedef struct { uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE @note If waveform automatic generation mode is disabled, this parameter is discarded. This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ } LL_DAC_InitTypeDef; /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants * @{ */ /** @defgroup DAC_LL_EC_GET_FLAG DAC flags * @brief Flags defines which can be used with LL_DAC_ReadReg function * @{ */ /* DAC channel 1 flags */ #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ #if defined(DAC_CHANNEL2_SUPPORT) /* DAC channel 2 flags */ #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ #endif /* DAC_CHANNEL2_SUPPORT */ /** * @} */ /** @defgroup DAC_LL_EC_IT DAC interruptions * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions * @{ */ #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ #if defined(DAC_CHANNEL2_SUPPORT) #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ #endif /* DAC_CHANNEL2_SUPPORT */ /** * @} */ /** @defgroup DAC_LL_EC_CHANNEL DAC channels * @{ */ #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ #if defined(DAC_CHANNEL2_SUPPORT) #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ #endif /* DAC_CHANNEL2_SUPPORT */ /** * @} */ /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source * @{ */ #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ #define LL_DAC_TRIG_EXT_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM3_TRGO) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM8_TRGO for TIM8 selection. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F303x8) || defined(STM32F328xx) #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8) #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F301x8) || defined(STM32F318xx) #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F373xC) || defined(STM32F378xx) #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ #define LL_DAC_TRIG_EXT_TIM18_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) /*!< DAC channel conversion trigger from external IP: TIM18 TRGO. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #elif defined(STM32F334x8) #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG1_REMAP_TIM3_TRGO for TIM3 selection. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. Trigger remap: by default, default trigger. If needed to restore trigger, use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_TIM15_TRGO for TIM15 selection. */ #define LL_DAC_TRIGGER_HRTIM1_DACTRG1 (LL_DAC_TRIG_EXT_TIM15_TRGO) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG1. Available only on DAC instance: DAC1. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG3_REMAP_HRTIM1_DAC1_TRIG1 for HRTIM1 TRIG1 selection. */ #define LL_DAC_TRIGGER_HRTIM1_DACTRG2 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG2. Available only on DAC instance: DAC2. Trigger remap: use @ref LL_SYSCFG_DAC1_TRIG5_REMAP_HRTIM1_DAC1_TRIG2 for HRTIM1 TRIG2 selection. */ #define LL_DAC_TRIGGER_HRTIM1_DACTRG3 (LL_DAC_TRIGGER_HRTIM1_DACTRG2) /*!< DAC channel conversion trigger from external IP: HRTIM1 DACTRG3. */ #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ #endif /** * @} */ /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode * @{ */ #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ /** * @} */ /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits * @{ */ #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ /** * @} */ /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude * @{ */ #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ /** * @} */ /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer * @{ */ #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ #if defined(DAC_CR_OUTEN1) || defined(DAC_CR_OUTEN2) #define LL_DAC_OUTPUT_SWITCH_DISABLE (LL_DAC_OUTPUT_BUFFER_ENABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. Selection of switch disabled: DAC channel output not connected to GPIO. */ #define LL_DAC_OUTPUT_SWITCH_ENABLE (LL_DAC_OUTPUT_BUFFER_DISABLE) /*!< Feature specific to STM32F303x6/8 and STM32F328: On DAC1 channel 2, output buffer is replaced by a switch to connect DAC channel output to pin PA5. On DAC2 channel 1, output buffer is replaced by a switch to connect DAC channel output to pin PA6. */ #endif /** * @} */ /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ /** * @} */ /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose * @{ */ /* List of DAC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ /** * @} */ /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays * @note Only DAC IP HW delays are defined in DAC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. * @{ */ /* Delay for DAC channel voltage settling time from DAC channel startup */ /* (transition from disable to enable). */ /* Note: DAC channel startup time depends on board application environment: */ /* impedance connected to DAC channel output. */ /* The delay below is specified under conditions: */ /* - voltage maximum transition (lowest to highest value) */ /* - until voltage reaches final value +-1LSB */ /* - DAC channel output buffer enabled */ /* - load impedance of 5kOhm (min), 50pF (max) */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ /* impedance connected to DAC channel output. */ /* The delay below is specified under conditions: */ /* - voltage maximum transition (lowest to highest value) */ /* - until voltage reaches final value +-1LSB */ /* - DAC channel output buffer enabled */ /* - load impedance of 5kOhm min, 50pF max */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros * @{ */ /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros * @{ */ /** * @brief Write a value in DAC register * @param __INSTANCE__ DAC Instance * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) /** * @brief Read a value in DAC register * @param __INSTANCE__ DAC Instance * @param __REG__ Register to be read * @retval Register value */ #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) /** * @} */ /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro * @{ */ /** * @brief Helper macro to get DAC channel number in decimal format * from literals LL_DAC_CHANNEL_x. * Example: * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) * will return decimal number "1". * @note The input can be a value from functions where a channel * number is returned. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval 1...2 (value "2" depending on DAC channel 2 availability) */ #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((__CHANNEL__) & DAC_SWTR_CHX_MASK) /** * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x * from number in decimal format. * Example: * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) * will return a data equivalent to "LL_DAC_CHANNEL_1". * @note If the input parameter does not correspond to a DAC channel, * this macro returns value '0'. * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. */ #if defined(DAC_CHANNEL2_SUPPORT) #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) == 1U) \ ? ( \ LL_DAC_CHANNEL_1 \ ) \ : \ (((__DECIMAL_NB__) == 2U) \ ? ( \ LL_DAC_CHANNEL_2 \ ) \ : \ ( \ 0 \ ) \ ) \ ) #else #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) == 1U) \ ? ( \ LL_DAC_CHANNEL_1 \ ) \ : \ ( \ 0 \ ) \ ) #endif /* DAC_CHANNEL2_SUPPORT */ /** * @brief Helper macro to define the DAC conversion data full-scale digital * value corresponding to the selected DAC resolution. * @note DAC conversion data full-scale corresponds to voltage range * determined by analog voltage references Vref+ and Vref- * (refer to reference manual). * @param __DAC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_DAC_RESOLUTION_12B * @arg @ref LL_DAC_RESOLUTION_8B * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) /** * @brief Helper macro to calculate the DAC conversion data (unit: digital * value) corresponding to a voltage (unit: mVolt). * @note This helper macro is intended to provide input data in voltage * rather than digital value, * to be used with LL DAC functions such as * @ref LL_DAC_ConvertData12RightAligned(). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). * @param __DAC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_DAC_RESOLUTION_12B * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ __DAC_VOLTAGE__,\ __DAC_RESOLUTION__) \ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ / (__VREFANALOG_VOLTAGE__) \ ) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels * @{ */ /** * @brief Set the conversion trigger source for the selected DAC channel. * @note For conversion trigger source to be effective, DAC trigger * must be enabled using function @ref LL_DAC_EnableTrigger(). * @note To set conversion trigger source, DAC channel must be disabled. * Otherwise, the setting is discarded. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n * CR TSEL2 LL_DAC_SetTriggerSource * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1) * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2) * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3) * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 * * (1) On STM32F3, parameter not available on all devices * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device). * @retval None */ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) { MODIFY_REG(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Get the conversion trigger source for the selected DAC channel. * @note For conversion trigger source to be effective, DAC trigger * must be enabled using function @ref LL_DAC_EnableTrigger(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n * CR TSEL2 LL_DAC_GetTriggerSource * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_TIM18_TRGO (1) * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG1 (1) * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG2 (1)(2) * @arg @ref LL_DAC_TRIG_EXT_HRTIM1_DACTRG3 (1) (3) * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 * * (1) On STM32F3, parameter not available on all devices * (2) On STM32F3, parameter not available on all DAC instances: DAC1 (for DAC instances DACx available on the selected device).\n * (3) On STM32F3, parameter not available on all DAC instances: DAC2 (for DAC instances DACx available on the selected device). */ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } /** * @brief Set the waveform automatic generation mode * for the selected DAC channel. * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n * CR WAVE2 LL_DAC_SetWaveAutoGeneration * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param WaveAutoGeneration This parameter can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE * @retval None */ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) { MODIFY_REG(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Get the waveform automatic generation mode * for the selected DAC channel. * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n * CR WAVE2 LL_DAC_GetWaveAutoGeneration * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE */ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } /** * @brief Set the noise waveform generation for the selected DAC channel: * Noise mode and parameters LFSR (linear feedback shift register). * @note For wave generation to be effective, DAC channel * wave generation mode must be enabled using * function @ref LL_DAC_SetWaveAutoGeneration(). * @note This setting can be set when the selected DAC channel is disabled * (otherwise, the setting operation is ignored). * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n * CR MAMP2 LL_DAC_SetWaveNoiseLFSR * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param NoiseLFSRMask This parameter can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 * @retval None */ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) { MODIFY_REG(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Set the noise waveform generation for the selected DAC channel: * Noise mode and parameters LFSR (linear feedback shift register). * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n * CR MAMP2 LL_DAC_GetWaveNoiseLFSR * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 */ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } /** * @brief Set the triangle waveform generation for the selected DAC channel: * triangle mode and amplitude. * @note For wave generation to be effective, DAC channel * wave generation mode must be enabled using * function @ref LL_DAC_SetWaveAutoGeneration(). * @note This setting can be set when the selected DAC channel is disabled * (otherwise, the setting operation is ignored). * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param TriangleAmplitude This parameter can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 * @retval None */ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) { MODIFY_REG(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Set the triangle waveform generation for the selected DAC channel: * triangle mode and amplitude. * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 */ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } /** * @brief Set the output buffer for the selected DAC channel. * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n * CR BOFF2 LL_DAC_SetOutputBuffer * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param OutputBuffer This parameter can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1) * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1) * * (1) Feature specific to STM32F303x6/8 and STM32F328: * On DAC1 channel 2, output buffer is replaced by a switch * to connect DAC channel output to pin PA5. * On DAC2 channel 1, output buffer is replaced by a switch * to connect DAC channel output to pin PA6. * @retval None */ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) { MODIFY_REG(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Get the output buffer state for the selected DAC channel. * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n * CR BOFF2 LL_DAC_GetOutputBuffer * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE * @arg @ref LL_DAC_OUTPUT_SWITCH_DISABLE (1) * @arg @ref LL_DAC_OUTPUT_SWITCH_ENABLE (1) * * (1) Feature specific to STM32F303x6/8 and STM32F328: * On DAC1 channel 2, output buffer is replaced by a switch * to connect DAC channel output to pin PA5. * On DAC2 channel 1, output buffer is replaced by a switch * to connect DAC channel output to pin PA6. */ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } /** * @} */ /** @defgroup DAC_LL_EF_DMA_Management DMA Management * @{ */ /** * @brief Enable DAC DMA transfer request of the selected channel. * @note To configure DMA source address (peripheral address), * use function @ref LL_DAC_DMA_GetRegAddr(). * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n * CR DMAEN2 LL_DAC_EnableDMAReq * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) { SET_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Disable DAC DMA transfer request of the selected channel. * @note To configure DMA source address (peripheral address), * use function @ref LL_DAC_DMA_GetRegAddr(). * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n * CR DMAEN2 LL_DAC_DisableDMAReq * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) { CLEAR_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Get DAC DMA transfer request state of the selected channel. * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n * CR DMAEN2 LL_DAC_IsDMAReqEnabled * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (READ_BIT(DACx->CR, DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); } /** * @brief Function to help to configure DMA transfer to DAC: retrieve the * DAC register address from DAC instance and a list of DAC registers * intended to be used (most commonly) with DMA transfer. * @note These DAC registers are data holding registers: * when DAC conversion is requested, DAC generates a DMA transfer * request to have data available in DAC data holding registers. * @note This macro is intended to be used with LL DMA driver, refer to * function "LL_DMA_ConfigAddresses()". * Example: * LL_DMA_ConfigAddresses(DMA1, * LL_DMA_CHANNEL_1, * (uint32_t)&< array or variable >, * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Register This parameter can be one of the following values: * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED * @retval DAC register address */ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); } /** * @} */ /** @defgroup DAC_LL_EF_Operation Operation on DAC channels * @{ */ /** * @brief Enable DAC selected channel. * @rmtoll CR EN1 LL_DAC_Enable\n * CR EN2 LL_DAC_Enable * @note After enable from off state, DAC channel requires a delay * for output voltage to reach accuracy +/- 1 LSB. * Refer to device datasheet, parameter "tWAKEUP". * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) { SET_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Disable DAC selected channel. * @rmtoll CR EN1 LL_DAC_Disable\n * CR EN2 LL_DAC_Disable * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) { CLEAR_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Get DAC enable state of the selected channel. * (0: DAC channel is disabled, 1: DAC channel is enabled) * @rmtoll CR EN1 LL_DAC_IsEnabled\n * CR EN2 LL_DAC_IsEnabled * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (READ_BIT(DACx->CR, DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); } /** * @brief Enable DAC trigger of the selected channel. * @note - If DAC trigger is disabled, DAC conversion is performed * automatically once the data holding register is updated, * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": * @ref LL_DAC_ConvertData12RightAligned(), ... * - If DAC trigger is enabled, DAC conversion is performed * only when a hardware of software trigger event is occurring. * Select trigger source using * function @ref LL_DAC_SetTriggerSource(). * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n * CR TEN2 LL_DAC_EnableTrigger * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) { SET_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Disable DAC trigger of the selected channel. * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n * CR TEN2 LL_DAC_DisableTrigger * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) { CLEAR_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); } /** * @brief Get DAC trigger state of the selected channel. * (0: DAC trigger is disabled, 1: DAC trigger is enabled) * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n * CR TEN2 LL_DAC_IsTriggerEnabled * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { return (READ_BIT(DACx->CR, DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); } /** * @brief Trig DAC conversion by software for the selected DAC channel. * @note Preliminarily, DAC trigger must be set to software trigger * using function @ref LL_DAC_SetTriggerSource() * with parameter "LL_DAC_TRIGGER_SOFTWARE". * and DAC trigger must be enabled using * function @ref LL_DAC_EnableTrigger(). * @note For devices featuring DAC with 2 channels: this function * can perform a SW start of both DAC channels simultaneously. * Two channels can be selected as parameter. * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion * @param DACx DAC instance * @param DAC_Channel This parameter can a combination of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval None */ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) { SET_BIT(DACx->SWTRIGR, (DAC_Channel & DAC_SWTR_CHX_MASK)); } /** * @brief Set the data to be loaded in the data holding register * in format 12 bits left alignment (LSB aligned on bit 0), * for the selected DAC channel. * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); } /** * @brief Set the data to be loaded in the data holding register * in format 12 bits left alignment (MSB aligned on bit 15), * for the selected DAC channel. * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); } /** * @brief Set the data to be loaded in the data holding register * in format 8 bits left alignment (LSB aligned on bit 0), * for the selected DAC channel. * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF * @retval None */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); } #if defined(DAC_CHANNEL2_SUPPORT) /** * @brief Set the data to be loaded in the data holding register * in format 12 bits left alignment (LSB aligned on bit 0), * for both DAC channels. * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned * @param DACx DAC instance * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) { MODIFY_REG(DACx->DHR12RD, (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); } /** * @brief Set the data to be loaded in the data holding register * in format 12 bits left alignment (MSB aligned on bit 15), * for both DAC channels. * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned * @param DACx DAC instance * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) { /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ /* the 4 LSB must be taken into account for the shift value. */ MODIFY_REG(DACx->DHR12LD, (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); } /** * @brief Set the data to be loaded in the data holding register * in format 8 bits left alignment (LSB aligned on bit 0), * for both DAC channels. * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned * @param DACx DAC instance * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF * @retval None */ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) { MODIFY_REG(DACx->DHR8RD, (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); } #endif /* DAC_CHANNEL2_SUPPORT */ /** * @brief Retrieve output data currently generated for the selected DAC channel. * @note Whatever alignment and resolution settings * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": * @ref LL_DAC_ConvertData12RightAligned(), ...), * output data format is 12 bits right aligned (LSB aligned on bit 0). * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n * DOR2 DACC2DOR LL_DAC_RetrieveOutputData * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { register __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } /** * @} */ /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management * @{ */ /** * @brief Get DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 * @param DACx DAC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) { return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); } #if defined(DAC_CHANNEL2_SUPPORT) /** * @brief Get DAC underrun flag for DAC channel 2 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 * @param DACx DAC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) { return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); } #endif /* DAC_CHANNEL2_SUPPORT */ /** * @brief Clear DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 * @param DACx DAC instance * @retval None */ __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) { WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); } #if defined(DAC_CHANNEL2_SUPPORT) /** * @brief Clear DAC underrun flag for DAC channel 2 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 * @param DACx DAC instance * @retval None */ __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) { WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); } #endif /* DAC_CHANNEL2_SUPPORT */ /** * @} */ /** @defgroup DAC_LL_EF_IT_Management IT management * @{ */ /** * @brief Enable DMA underrun interrupt for DAC channel 1 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 * @param DACx DAC instance * @retval None */ __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) { SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); } #if defined(DAC_CHANNEL2_SUPPORT) /** * @brief Enable DMA underrun interrupt for DAC channel 2 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 * @param DACx DAC instance * @retval None */ __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) { SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); } #endif /* DAC_CHANNEL2_SUPPORT */ /** * @brief Disable DMA underrun interrupt for DAC channel 1 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 * @param DACx DAC instance * @retval None */ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) { CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); } #if defined(DAC_CHANNEL2_SUPPORT) /** * @brief Disable DMA underrun interrupt for DAC channel 2 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 * @param DACx DAC instance * @retval None */ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) { CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); } #endif /* DAC_CHANNEL2_SUPPORT */ /** * @brief Get DMA underrun interrupt for DAC channel 1 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 * @param DACx DAC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) { return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); } #if defined(DAC_CHANNEL2_SUPPORT) /** * @brief Get DMA underrun interrupt for DAC channel 2 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 * @param DACx DAC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) { return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); } #endif /* DAC_CHANNEL2_SUPPORT */ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions * @{ */ ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_dma.h * @author MCD Application Team * @brief Header file of DMA LL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_DMA_H #define __STM32F3xx_LL_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (DMA1) || defined (DMA2) /** @defgroup DMA_LL DMA * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup DMA_LL_Private_Variables DMA Private Variables * @{ */ /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ static const uint8_t CHANNEL_OFFSET_TAB[] = { (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) }; /** * @} */ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup DMA_LL_Private_Macros DMA Private Macros * @{ */ /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure * @{ */ typedef struct { uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_LL_EC_DIRECTION This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ uint32_t Mode; /*!< Specifies the normal or circular operation mode. This parameter can be a value of @ref DMA_LL_EC_MODE @note: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of @ref DMA_LL_EC_PERIPH This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of @ref DMA_LL_EC_MEMORY This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ uint32_t Priority; /*!< Specifies the channel priority level. This parameter can be a value of @ref DMA_LL_EC_PRIORITY This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ } LL_DMA_InitTypeDef; /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants * @{ */ /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines * @brief Flags defines which can be used with LL_DMA_WriteReg function * @{ */ #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ /** * @} */ /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_DMA_ReadReg function * @{ */ #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ /** * @} */ /** @defgroup DMA_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions * @{ */ #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ /** * @} */ /** @defgroup DMA_LL_EC_CHANNEL CHANNEL * @{ */ #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ #if defined(USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} */ /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction * @{ */ #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** * @} */ /** @defgroup DMA_LL_EC_MODE Transfer mode * @{ */ #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ /** * @} */ /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode * @{ */ #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ /** @defgroup DMA_LL_EC_MEMORY Memory increment mode * @{ */ #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment * @{ */ #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** * @} */ /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment * @{ */ #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** * @} */ /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level * @{ */ #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros * @{ */ /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros * @{ */ /** * @brief Write a value in DMA register * @param __INSTANCE__ DMA Instance * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) /** * @brief Read a value in DMA register * @param __INSTANCE__ DMA Instance * @param __REG__ Register to be read * @retval Register value */ #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) /** * @} */ /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely * @{ */ /** * @brief Convert DMAx_Channely into DMAx * @param __CHANNEL_INSTANCE__ DMAx_Channely * @retval DMAx */ #if defined(DMA2) #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) #else #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) #endif /** * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y * @param __CHANNEL_INSTANCE__ DMAx_Channely * @retval LL_DMA_CHANNEL_y */ #if defined (DMA2) #if defined (DMA2_Channel6) && defined (DMA2_Channel7) #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ LL_DMA_CHANNEL_7) #else #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ LL_DMA_CHANNEL_7) #endif #else #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ LL_DMA_CHANNEL_7) #endif /** * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely * @param __DMA_INSTANCE__ DMAx * @param __CHANNEL__ LL_DMA_CHANNEL_y * @retval DMAx_Channely */ #if defined (DMA2) #if defined (DMA2_Channel6) && defined (DMA2_Channel7) #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ DMA2_Channel7) #else #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ DMA1_Channel7) #endif #else #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ DMA1_Channel7) #endif /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions * @{ */ /** @defgroup DMA_LL_EF_Configuration Configuration * @{ */ /** * @brief Enable DMA channel. * @rmtoll CCR EN LL_DMA_EnableChannel * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); } /** * @brief Disable DMA channel. * @rmtoll CCR EN LL_DMA_DisableChannel * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) { CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); } /** * @brief Check if DMA channel is enabled or disabled. * @rmtoll CCR EN LL_DMA_IsEnabledChannel * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN) == (DMA_CCR_EN)); } /** * @brief Configure all parameters link to DMA transfer. * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n * CCR MEM2MEM LL_DMA_ConfigTransfer\n * CCR CIRC LL_DMA_ConfigTransfer\n * CCR PINC LL_DMA_ConfigTransfer\n * CCR MINC LL_DMA_ConfigTransfer\n * CCR PSIZE LL_DMA_ConfigTransfer\n * CCR MSIZE LL_DMA_ConfigTransfer\n * CCR PL LL_DMA_ConfigTransfer * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param Configuration This parameter must be a combination of all the following values: * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, Configuration); } /** * @brief Set Data transfer direction (read from peripheral or from memory). * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n * CCR MEM2MEM LL_DMA_SetDataTransferDirection * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param Direction This parameter can be one of the following values: * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); } /** * @brief Get Data transfer direction (read from peripheral or from memory). * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n * CCR MEM2MEM LL_DMA_GetDataTransferDirection * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_DIR | DMA_CCR_MEM2MEM)); } /** * @brief Set DMA mode circular or normal. * @note The circular buffer mode cannot be used if the memory-to-memory * data transfer is configured on the selected Channel. * @rmtoll CCR CIRC LL_DMA_SetMode * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param Mode This parameter can be one of the following values: * @arg @ref LL_DMA_MODE_NORMAL * @arg @ref LL_DMA_MODE_CIRCULAR * @retval None */ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, Mode); } /** * @brief Get DMA mode circular or normal. * @rmtoll CCR CIRC LL_DMA_GetMode * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_MODE_NORMAL * @arg @ref LL_DMA_MODE_CIRCULAR */ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC)); } /** * @brief Set Peripheral increment mode. * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: * @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @retval None */ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, PeriphOrM2MSrcIncMode); } /** * @brief Get Peripheral increment mode. * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_NOINCREMENT */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC)); } /** * @brief Set Memory increment mode. * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: * @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @retval None */ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, MemoryOrM2MDstIncMode); } /** * @brief Get Memory increment mode. * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_NOINCREMENT */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC)); } /** * @brief Set Peripheral size. * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: * @arg @ref LL_DMA_PDATAALIGN_BYTE * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, PeriphOrM2MSrcDataSize); } /** * @brief Get Peripheral size. * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_PDATAALIGN_BYTE * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE)); } /** * @brief Set Memory size. * @rmtoll CCR MSIZE LL_DMA_SetMemorySize * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: * @arg @ref LL_DMA_MDATAALIGN_BYTE * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, MemoryOrM2MDstDataSize); } /** * @brief Get Memory size. * @rmtoll CCR MSIZE LL_DMA_GetMemorySize * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_MDATAALIGN_BYTE * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE)); } /** * @brief Set Channel priority level. * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param Priority This parameter can be one of the following values: * @arg @ref LL_DMA_PRIORITY_LOW * @arg @ref LL_DMA_PRIORITY_MEDIUM * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, Priority); } /** * @brief Get Channel priority level. * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Returned value can be one of the following values: * @arg @ref LL_DMA_PRIORITY_LOW * @arg @ref LL_DMA_PRIORITY_MEDIUM * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL)); } /** * @brief Set Number of data to transfer. * @note This action has no effect if * channel is enabled. * @rmtoll CNDTR NDT LL_DMA_SetDataLength * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, DMA_CNDTR_NDT, NbData); } /** * @brief Get Number of data to transfer. * @note Once the channel is enabled, the return value indicate the * remaining bytes to be transmitted. * @rmtoll CNDTR NDT LL_DMA_GetDataLength * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, DMA_CNDTR_NDT)); } /** * @brief Configure the Source and Destination addresses. * @note This API must not be called when the DMA channel is enabled. * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @param Direction This parameter can be one of the following values: * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { /* Direction Memory to Periph */ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); } /* Direction Periph to Memory and Memory to Memory */ else { WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); } } /** * @brief Set the Memory address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetMemoryAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** * @brief Set the Peripheral address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetPeriphAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); } /** * @brief Get Memory address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. * @rmtoll CMAR MA LL_DMA_GetMemoryAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } /** * @brief Get Peripheral address. * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. * @rmtoll CPAR PA LL_DMA_GetPeriphAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** * @brief Set the Memory to Memory Source address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. * @note This API must not be called when the DMA channel is enabled. * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); } /** * @brief Set the Memory to Memory Destination address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. * @note This API must not be called when the DMA channel is enabled. * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); } /** * @brief Get the Memory to Memory Source address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); } /** * @brief Get the Memory to Memory Destination address. * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); } /** * @} */ /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management * @{ */ /** * @brief Get Channel 1 global interrupt flag. * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); } /** * @brief Get Channel 2 global interrupt flag. * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); } /** * @brief Get Channel 3 global interrupt flag. * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); } /** * @brief Get Channel 4 global interrupt flag. * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); } /** * @brief Get Channel 5 global interrupt flag. * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); } /** * @brief Get Channel 6 global interrupt flag. * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); } /** * @brief Get Channel 7 global interrupt flag. * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); } /** * @brief Get Channel 1 transfer complete flag. * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); } /** * @brief Get Channel 2 transfer complete flag. * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); } /** * @brief Get Channel 3 transfer complete flag. * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); } /** * @brief Get Channel 4 transfer complete flag. * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); } /** * @brief Get Channel 5 transfer complete flag. * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); } /** * @brief Get Channel 6 transfer complete flag. * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); } /** * @brief Get Channel 7 transfer complete flag. * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); } /** * @brief Get Channel 1 half transfer flag. * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); } /** * @brief Get Channel 2 half transfer flag. * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); } /** * @brief Get Channel 3 half transfer flag. * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); } /** * @brief Get Channel 4 half transfer flag. * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); } /** * @brief Get Channel 5 half transfer flag. * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); } /** * @brief Get Channel 6 half transfer flag. * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); } /** * @brief Get Channel 7 half transfer flag. * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); } /** * @brief Get Channel 1 transfer error flag. * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); } /** * @brief Get Channel 2 transfer error flag. * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); } /** * @brief Get Channel 3 transfer error flag. * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); } /** * @brief Get Channel 4 transfer error flag. * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); } /** * @brief Get Channel 5 transfer error flag. * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); } /** * @brief Get Channel 6 transfer error flag. * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); } /** * @brief Get Channel 7 transfer error flag. * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); } /** * @brief Clear Channel 1 global interrupt flag. * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); } /** * @brief Clear Channel 2 global interrupt flag. * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); } /** * @brief Clear Channel 3 global interrupt flag. * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); } /** * @brief Clear Channel 4 global interrupt flag. * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); } /** * @brief Clear Channel 5 global interrupt flag. * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); } /** * @brief Clear Channel 6 global interrupt flag. * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } /** * @brief Clear Channel 7 global interrupt flag. * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } /** * @brief Clear Channel 1 transfer complete flag. * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); } /** * @brief Clear Channel 2 transfer complete flag. * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); } /** * @brief Clear Channel 3 transfer complete flag. * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); } /** * @brief Clear Channel 4 transfer complete flag. * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); } /** * @brief Clear Channel 5 transfer complete flag. * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); } /** * @brief Clear Channel 6 transfer complete flag. * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } /** * @brief Clear Channel 7 transfer complete flag. * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } /** * @brief Clear Channel 1 half transfer flag. * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); } /** * @brief Clear Channel 2 half transfer flag. * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); } /** * @brief Clear Channel 3 half transfer flag. * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); } /** * @brief Clear Channel 4 half transfer flag. * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); } /** * @brief Clear Channel 5 half transfer flag. * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); } /** * @brief Clear Channel 6 half transfer flag. * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } /** * @brief Clear Channel 7 half transfer flag. * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } /** * @brief Clear Channel 1 transfer error flag. * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); } /** * @brief Clear Channel 2 transfer error flag. * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); } /** * @brief Clear Channel 3 transfer error flag. * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); } /** * @brief Clear Channel 4 transfer error flag. * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); } /** * @brief Clear Channel 5 transfer error flag. * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); } /** * @brief Clear Channel 6 transfer error flag. * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } /** * @brief Clear Channel 7 transfer error flag. * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 * @param DMAx DMAx Instance * @retval None */ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) { WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } /** * @} */ /** @defgroup DMA_LL_EF_IT_Management IT_Management * @{ */ /** * @brief Enable Transfer complete interrupt. * @rmtoll CCR TCIE LL_DMA_EnableIT_TC * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); } /** * @brief Enable Half transfer interrupt. * @rmtoll CCR HTIE LL_DMA_EnableIT_HT * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); } /** * @brief Enable Transfer error interrupt. * @rmtoll CCR TEIE LL_DMA_EnableIT_TE * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); } /** * @brief Disable Transfer complete interrupt. * @rmtoll CCR TCIE LL_DMA_DisableIT_TC * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); } /** * @brief Disable Half transfer interrupt. * @rmtoll CCR HTIE LL_DMA_DisableIT_HT * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); } /** * @brief Disable Transfer error interrupt. * @rmtoll CCR TEIE LL_DMA_DisableIT_TE * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); } /** * @brief Check if Transfer complete Interrupt is enabled. * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE) == (DMA_CCR_TCIE)); } /** * @brief Check if Half transfer Interrupt is enabled. * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE) == (DMA_CCR_HTIE)); } /** * @brief Check if Transfer error Interrupt is enabled. * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) { return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE) == (DMA_CCR_TEIE)); } /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions * @{ */ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* DMA1 || DMA2 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_exti.h * @author MCD Application Team * @brief Header file of EXTI LL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_EXTI_H #define __STM32F3xx_LL_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (EXTI) /** @defgroup EXTI_LL EXTI * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private Macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros * @{ */ /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure * @{ */ typedef struct { uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of @ref EXTI_LL_EC_LINE */ #if defined(EXTI_32_63_SUPPORT) uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 This parameter can be any combination of @ref EXTI_LL_EC_LINE */ #endif FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE */ uint8_t Mode; /*!< Specifies the mode for the EXTI lines. This parameter can be a value of @ref EXTI_LL_EC_MODE. */ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ } LL_EXTI_InitTypeDef; /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants * @{ */ /** @defgroup EXTI_LL_EC_LINE LINE * @{ */ #define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ #define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ #define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ #define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ #define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ #define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ #define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ #define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ #define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ #define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ #define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ #define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ #define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ #define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ #define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ #define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ #if defined(EXTI_IMR_IM16) #define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ #endif #define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ #if defined(EXTI_IMR_IM18) #define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ #endif #define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ #if defined(EXTI_IMR_IM20) #define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ #endif #if defined(EXTI_IMR_IM21) #define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ #endif #if defined(EXTI_IMR_IM22) #define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ #endif #define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ #if defined(EXTI_IMR_IM24) #define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ #endif #if defined(EXTI_IMR_IM25) #define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ #endif #if defined(EXTI_IMR_IM26) #define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ #endif #if defined(EXTI_IMR_IM27) #define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ #endif #if defined(EXTI_IMR_IM28) #define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ #endif #if defined(EXTI_IMR_IM29) #define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ #endif #if defined(EXTI_IMR_IM30) #define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ #endif #if defined(EXTI_IMR_IM31) #define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ #endif #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ #if defined(EXTI_32_63_SUPPORT) #define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ #if defined(EXTI_IMR2_IM33) #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ #endif #if defined(EXTI_IMR2_IM34) #define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ #endif #if defined(EXTI_IMR2_IM35) #define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ #endif #if defined(EXTI_IMR2_IM36) #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ #endif #if defined(EXTI_IMR2_IM37) #define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ #endif #if defined(EXTI_IMR2_IM38) #define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ #endif #if defined(EXTI_IMR2_IM39) #define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ #endif #if defined(EXTI_IMR2_IM40) #define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ #endif #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ #endif #define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ #if defined(USE_FULL_LL_DRIVER) #define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup EXTI_LL_EC_MODE Mode * @{ */ #define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ #define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ #define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ /** * @} */ /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger * @{ */ #define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ #define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ #define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ #define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros * @{ */ /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros * @{ */ /** * @brief Write a value in EXTI register * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) /** * @brief Read a value in EXTI register * @param __REG__ Register to be read * @retval Register value */ #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions * @{ */ /** @defgroup EXTI_LL_EF_IT_Management IT_Management * @{ */ /** * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 * @note The reset value for the direct or internal lines (see RM) * is set to 1 in order to enable the interrupt by default. * Bits are set automatically at Power on. * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 * @arg @ref LL_EXTI_LINE_26 * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) { SET_BIT(EXTI->IMR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 * @note The reset value for the direct lines (lines from 32 to 34, line * 39) is set to 1 in order to enable the interrupt by default. * Bits are set automatically at Power on. * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_34 * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->IMR2, ExtiLine); } #endif /** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 * @note The reset value for the direct or internal lines (see RM) * is set to 1 in order to enable the interrupt by default. * Bits are set automatically at Power on. * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 * @arg @ref LL_EXTI_LINE_26 * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) { CLEAR_BIT(EXTI->IMR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 * @note The reset value for the direct lines (lines from 32 to 34, line * 39) is set to 1 in order to enable the interrupt by default. * Bits are set automatically at Power on. * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_34 * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->IMR2, ExtiLine); } #endif /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 * @note The reset value for the direct or internal lines (see RM) * is set to 1 in order to enable the interrupt by default. * Bits are set automatically at Power on. * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 * @arg @ref LL_EXTI_LINE_26 * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) { return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 * @note The reset value for the direct lines (lines from 32 to 34, line * 39) is set to 1 in order to enable the interrupt by default. * Bits are set automatically at Power on. * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_34 * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) { return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)); } #endif /** * @} */ /** @defgroup EXTI_LL_EF_Event_Management Event_Management * @{ */ /** * @brief Enable ExtiLine Event request for Lines in range 0 to 31 * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 * @arg @ref LL_EXTI_LINE_26 * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) { SET_BIT(EXTI->EMR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Enable ExtiLine Event request for Lines in range 32 to 63 * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_34 * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->EMR2, ExtiLine); } #endif /** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 * @arg @ref LL_EXTI_LINE_26 * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) { CLEAR_BIT(EXTI->EMR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Disable ExtiLine Event request for Lines in range 32 to 63 * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_34 * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval None */ __STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->EMR2, ExtiLine); } #endif /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 * @param ExtiLine This parameter can be one of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_17 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_23 * @arg @ref LL_EXTI_LINE_24 * @arg @ref LL_EXTI_LINE_25 * @arg @ref LL_EXTI_LINE_26 * @arg @ref LL_EXTI_LINE_27 * @arg @ref LL_EXTI_LINE_28 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @arg @ref LL_EXTI_LINE_ALL_0_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) { return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_32 * @arg @ref LL_EXTI_LINE_33 * @arg @ref LL_EXTI_LINE_34 * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @arg @ref LL_EXTI_LINE_39 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) { return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)); } #endif /** * @} */ /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management * @{ */ /** * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a rising edge on a configurable interrupt * line occurs during a write operation in the EXTI_RTSR register, the * pending bit is not set. * Rising and falling edge triggers can be set for * the same interrupt line. In this case, both generate a trigger * condition. * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) { SET_BIT(EXTI->RTSR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a rising edge on a configurable interrupt * line occurs during a write operation in the EXTI_RTSR register, the * pending bit is not set.Rising and falling edge triggers can be set for * the same interrupt line. In this case, both generate a trigger * condition. * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval None */ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->RTSR2, ExtiLine); } #endif /** * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a rising edge on a configurable interrupt * line occurs during a write operation in the EXTI_RTSR register, the * pending bit is not set. * Rising and falling edge triggers can be set for * the same interrupt line. In this case, both generate a trigger * condition. * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) { CLEAR_BIT(EXTI->RTSR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a rising edge on a configurable interrupt * line occurs during a write operation in the EXTI_RTSR register, the * pending bit is not set. * Rising and falling edge triggers can be set for * the same interrupt line. In this case, both generate a trigger * condition. * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval None */ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->RTSR2, ExtiLine); } #endif /** * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) { return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) { return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)); } #endif /** * @} */ /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management * @{ */ /** * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a falling edge on a configurable interrupt * line occurs during a write operation in the EXTI_FTSR register, the * pending bit is not set. * Rising and falling edge triggers can be set for * the same interrupt line. In this case, both generate a trigger * condition. * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) { SET_BIT(EXTI->FTSR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a Falling edge on a configurable interrupt * line occurs during a write operation in the EXTI_FTSR register, the * pending bit is not set. * Rising and falling edge triggers can be set for * the same interrupt line. In this case, both generate a trigger * condition. * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval None */ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->FTSR2, ExtiLine); } #endif /** * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a Falling edge on a configurable interrupt * line occurs during a write operation in the EXTI_FTSR register, the * pending bit is not set. * Rising and falling edge triggers can be set for the same interrupt line. * In this case, both generate a trigger condition. * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) { CLEAR_BIT(EXTI->FTSR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 * @note The configurable wakeup lines are edge-triggered. No glitch must be * generated on these lines. If a Falling edge on a configurable interrupt * line occurs during a write operation in the EXTI_FTSR register, the * pending bit is not set. * Rising and falling edge triggers can be set for the same interrupt line. * In this case, both generate a trigger condition. * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval None */ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->FTSR2, ExtiLine); } #endif /** * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) { return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) { return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)); } #endif /** * @} */ /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management * @{ */ /** * @brief Generate a software Interrupt Event for Lines in range 0 to 31 * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR * resulting in an interrupt request generation. * This bit is cleared by clearing the corresponding bit in the EXTI_PR * register (by writing a 1 into the bit) * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) { SET_BIT(EXTI->SWIER, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Generate a software Interrupt Event for Lines in range 32 to 63 * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 * resulting in an interrupt request generation. * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 * register (by writing a 1 into the bit) * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval None */ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->SWIER2, ExtiLine); } #endif /** * @} */ /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management * @{ */ /** * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 * @note This bit is set when the selected edge event arrives on the interrupt * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) { return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 * @note This bit is set when the selected edge event arrives on the interrupt * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) { return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)); } #endif /** * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 * @note This bit is set when the selected edge event arrives on the interrupt * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval @note This bit is set when the selected edge event arrives on the interrupt */ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) { return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 * @note This bit is set when the selected edge event arrives on the interrupt * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval @note This bit is set when the selected edge event arrives on the interrupt */ __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) { return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); } #endif /** * @brief Clear ExtLine Flags for Lines in range 0 to 31 * @note This bit is set when the selected edge event arrives on the interrupt * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_0 * @arg @ref LL_EXTI_LINE_1 * @arg @ref LL_EXTI_LINE_2 * @arg @ref LL_EXTI_LINE_3 * @arg @ref LL_EXTI_LINE_4 * @arg @ref LL_EXTI_LINE_5 * @arg @ref LL_EXTI_LINE_6 * @arg @ref LL_EXTI_LINE_7 * @arg @ref LL_EXTI_LINE_8 * @arg @ref LL_EXTI_LINE_9 * @arg @ref LL_EXTI_LINE_10 * @arg @ref LL_EXTI_LINE_11 * @arg @ref LL_EXTI_LINE_12 * @arg @ref LL_EXTI_LINE_13 * @arg @ref LL_EXTI_LINE_14 * @arg @ref LL_EXTI_LINE_15 * @arg @ref LL_EXTI_LINE_16 * @arg @ref LL_EXTI_LINE_18 * @arg @ref LL_EXTI_LINE_19 * @arg @ref LL_EXTI_LINE_20 * @arg @ref LL_EXTI_LINE_21 * @arg @ref LL_EXTI_LINE_22 * @arg @ref LL_EXTI_LINE_29 * @arg @ref LL_EXTI_LINE_30 * @arg @ref LL_EXTI_LINE_31 * @note Please check each device line mapping for EXTI Line availability * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) { WRITE_REG(EXTI->PR, ExtiLine); } #if defined(EXTI_32_63_SUPPORT) /** * @brief Clear ExtLine Flags for Lines in range 32 to 63 * @note This bit is set when the selected edge event arrives on the interrupt * line. This bit is cleared by writing a 1 to the bit. * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_35 * @arg @ref LL_EXTI_LINE_36 * @arg @ref LL_EXTI_LINE_37 * @arg @ref LL_EXTI_LINE_38 * @retval None */ __STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) { WRITE_REG(EXTI->PR2, ExtiLine); } #endif /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions * @{ */ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); uint32_t LL_EXTI_DeInit(void); void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* EXTI */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_EXTI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_gpio.h * @author MCD Application Team * @brief Header file of GPIO LL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_GPIO_H #define __STM32F3xx_LL_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) /** @defgroup GPIO_LL GPIO * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros * @{ */ /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures * @{ */ /** * @brief LL GPIO Init Structure definition */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_LL_EC_PIN */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_LL_EC_MODE. GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_LL_EC_SPEED. GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of @ref GPIO_LL_EC_PULL. GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. This parameter can be a value of @ref GPIO_LL_EC_AF. GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ } LL_GPIO_InitTypeDef; /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants * @{ */ /** @defgroup GPIO_LL_EC_PIN PIN * @{ */ #define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ #define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ #define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ #define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ #define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ #define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ #define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ #define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ #define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ #define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ #define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ #define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ #define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ #define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ #define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ #define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ #define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ GPIO_BSRR_BS_15) /*!< Select all pins */ /** * @} */ /** @defgroup GPIO_LL_EC_MODE Mode * @{ */ #define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ #define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ #define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ #define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ /** * @} */ /** @defgroup GPIO_LL_EC_OUTPUT Output Type * @{ */ #define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ /** * @} */ /** @defgroup GPIO_LL_EC_SPEED Output Speed * @{ */ #define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ #define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ #define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ /** * @} */ /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down * @{ */ #define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ #define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ #define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ /** * @} */ /** @defgroup GPIO_LL_EC_AF Alternate Function * @{ */ #define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ #define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ #define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ #define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ #define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ #define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ #define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ #define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ #define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ #define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ #define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ #define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ #define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ #define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ #define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ #define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros * @{ */ /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros * @{ */ /** * @brief Write a value in GPIO register * @param __INSTANCE__ GPIO Instance * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) /** * @brief Read a value in GPIO register * @param __INSTANCE__ GPIO Instance * @param __REG__ Register to be read * @retval Register value */ #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions * @{ */ /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration * @{ */ /** * @brief Configure gpio mode for a dedicated pin on dedicated port. * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. * @note Warning: only one pin can be passed as parameter. * @rmtoll MODER MODEy LL_GPIO_SetPinMode * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @param Mode This parameter can be one of the following values: * @arg @ref LL_GPIO_MODE_INPUT * @arg @ref LL_GPIO_MODE_OUTPUT * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) { MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); } /** * @brief Return gpio mode for a dedicated pin on dedicated port. * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. * @note Warning: only one pin can be passed as parameter. * @rmtoll MODER MODEy LL_GPIO_GetPinMode * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @retval Returned value can be one of the following values: * @arg @ref LL_GPIO_MODE_INPUT * @arg @ref LL_GPIO_MODE_OUTPUT * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); } /** * @brief Configure gpio output type for several pins on dedicated port. * @note Output type as to be set when gpio pin is in output or * alternate modes. Possible type are Push-pull or Open-drain. * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @param OutputType This parameter can be one of the following values: * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); } /** * @brief Return gpio output type for several pins on dedicated port. * @note Output type as to be set when gpio pin is in output or * alternate modes. Possible type are Push-pull or Open-drain. * @note Warning: only one pin can be passed as parameter. * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval Returned value can be one of the following values: * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); } /** * @brief Configure gpio speed for a dedicated pin on dedicated port. * @note I/O speed can be Low, Medium, Fast or High speed. * @note Warning: only one pin can be passed as parameter. * @note Refer to datasheet for frequency specifications and the power * supply and load conditions for each speed. * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @param Speed This parameter can be one of the following values: * @arg @ref LL_GPIO_SPEED_FREQ_LOW * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) { MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), (Speed << (POSITION_VAL(Pin) * 2U))); } /** * @brief Return gpio speed for a dedicated pin on dedicated port. * @note I/O speed can be Low, Medium, Fast or High speed. * @note Warning: only one pin can be passed as parameter. * @note Refer to datasheet for frequency specifications and the power * supply and load conditions for each speed. * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @retval Returned value can be one of the following values: * @arg @ref LL_GPIO_SPEED_FREQ_LOW * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM * @arg @ref LL_GPIO_SPEED_FREQ_HIGH */ __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); } /** * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. * @note Warning: only one pin can be passed as parameter. * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @param Pull This parameter can be one of the following values: * @arg @ref LL_GPIO_PULL_NO * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN * @retval None */ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) { MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); } /** * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port * @note Warning: only one pin can be passed as parameter. * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @retval Returned value can be one of the following values: * @arg @ref LL_GPIO_PULL_NO * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); } /** * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. * @note Possible values are from AF0 to AF15 depending on target. * @note Warning: only one pin can be passed as parameter. * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @param Alternate This parameter can be one of the following values: * @arg @ref LL_GPIO_AF_0 * @arg @ref LL_GPIO_AF_1 * @arg @ref LL_GPIO_AF_2 * @arg @ref LL_GPIO_AF_3 * @arg @ref LL_GPIO_AF_4 * @arg @ref LL_GPIO_AF_5 * @arg @ref LL_GPIO_AF_6 * @arg @ref LL_GPIO_AF_7 * @arg @ref LL_GPIO_AF_8 * @arg @ref LL_GPIO_AF_9 * @arg @ref LL_GPIO_AF_10 * @arg @ref LL_GPIO_AF_11 * @arg @ref LL_GPIO_AF_12 * @arg @ref LL_GPIO_AF_13 * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 * @retval None */ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)), (Alternate << (POSITION_VAL(Pin) * 4U))); } /** * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @retval Returned value can be one of the following values: * @arg @ref LL_GPIO_AF_0 * @arg @ref LL_GPIO_AF_1 * @arg @ref LL_GPIO_AF_2 * @arg @ref LL_GPIO_AF_3 * @arg @ref LL_GPIO_AF_4 * @arg @ref LL_GPIO_AF_5 * @arg @ref LL_GPIO_AF_6 * @arg @ref LL_GPIO_AF_7 * @arg @ref LL_GPIO_AF_8 * @arg @ref LL_GPIO_AF_9 * @arg @ref LL_GPIO_AF_10 * @arg @ref LL_GPIO_AF_11 * @arg @ref LL_GPIO_AF_12 * @arg @ref LL_GPIO_AF_13 * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); } /** * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. * @note Possible values are from AF0 to AF15 depending on target. * @note Warning: only one pin can be passed as parameter. * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @param Alternate This parameter can be one of the following values: * @arg @ref LL_GPIO_AF_0 * @arg @ref LL_GPIO_AF_1 * @arg @ref LL_GPIO_AF_2 * @arg @ref LL_GPIO_AF_3 * @arg @ref LL_GPIO_AF_4 * @arg @ref LL_GPIO_AF_5 * @arg @ref LL_GPIO_AF_6 * @arg @ref LL_GPIO_AF_7 * @arg @ref LL_GPIO_AF_8 * @arg @ref LL_GPIO_AF_9 * @arg @ref LL_GPIO_AF_10 * @arg @ref LL_GPIO_AF_11 * @arg @ref LL_GPIO_AF_12 * @arg @ref LL_GPIO_AF_13 * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 * @retval None */ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) { MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); } /** * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. * @note Possible values are from AF0 to AF15 depending on target. * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 * @param GPIOx GPIO Port * @param Pin This parameter can be one of the following values: * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @retval Returned value can be one of the following values: * @arg @ref LL_GPIO_AF_0 * @arg @ref LL_GPIO_AF_1 * @arg @ref LL_GPIO_AF_2 * @arg @ref LL_GPIO_AF_3 * @arg @ref LL_GPIO_AF_4 * @arg @ref LL_GPIO_AF_5 * @arg @ref LL_GPIO_AF_6 * @arg @ref LL_GPIO_AF_7 * @arg @ref LL_GPIO_AF_8 * @arg @ref LL_GPIO_AF_9 * @arg @ref LL_GPIO_AF_10 * @arg @ref LL_GPIO_AF_11 * @arg @ref LL_GPIO_AF_12 * @arg @ref LL_GPIO_AF_13 * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); } /** * @brief Lock configuration of several pins for a dedicated port. * @note When the lock sequence has been applied on a port bit, the * value of this port bit can no longer be modified until the * next reset. * @note Each lock bit freezes a specific configuration register * (control and alternate function registers). * @rmtoll LCKR LCKK LL_GPIO_LockPin * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { __IO uint32_t temp; WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); WRITE_REG(GPIOx->LCKR, PinMask); WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); temp = READ_REG(GPIOx->LCKR); (void) temp; } /** * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) { return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); } /** * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) { return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); } /** * @} */ /** @defgroup GPIO_LL_EF_Data_Access Data Access * @{ */ /** * @brief Return full input data register value for a dedicated port. * @rmtoll IDR IDy LL_GPIO_ReadInputPort * @param GPIOx GPIO Port * @retval Input data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } /** * @brief Return if input data level for several pins of dedicated port is high or low. * @rmtoll IDR IDy LL_GPIO_IsInputPinSet * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); } /** * @brief Write output data register for the port. * @rmtoll ODR ODy LL_GPIO_WriteOutputPort * @param GPIOx GPIO Port * @param PortValue Level value for each pin of the port * @retval None */ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) { WRITE_REG(GPIOx->ODR, PortValue); } /** * @brief Return full output data register value for a dedicated port. * @rmtoll ODR ODy LL_GPIO_ReadOutputPort * @param GPIOx GPIO Port * @retval Output data register value of port */ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } /** * @brief Return if input data level for several pins of dedicated port is high or low. * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) { return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); } /** * @brief Set several pins to high level on dedicated gpio port. * @rmtoll BSRR BSy LL_GPIO_SetOutputPin * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { WRITE_REG(GPIOx->BSRR, PinMask); } /** * @brief Set several pins to low level on dedicated gpio port. * @rmtoll BRR BRy LL_GPIO_ResetOutputPin * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { WRITE_REG(GPIOx->BRR, PinMask); } /** * @brief Toggle data value for several pin of dedicated port. * @rmtoll ODR ODy LL_GPIO_TogglePin * @param GPIOx GPIO Port * @param PinMask This parameter can be a combination of the following values: * @arg @ref LL_GPIO_PIN_0 * @arg @ref LL_GPIO_PIN_1 * @arg @ref LL_GPIO_PIN_2 * @arg @ref LL_GPIO_PIN_3 * @arg @ref LL_GPIO_PIN_4 * @arg @ref LL_GPIO_PIN_5 * @arg @ref LL_GPIO_PIN_6 * @arg @ref LL_GPIO_PIN_7 * @arg @ref LL_GPIO_PIN_8 * @arg @ref LL_GPIO_PIN_9 * @arg @ref LL_GPIO_PIN_10 * @arg @ref LL_GPIO_PIN_11 * @arg @ref LL_GPIO_PIN_12 * @arg @ref LL_GPIO_PIN_13 * @arg @ref LL_GPIO_PIN_14 * @arg @ref LL_GPIO_PIN_15 * @arg @ref LL_GPIO_PIN_ALL * @retval None */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); } /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions * @{ */ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_GPIO_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_pwr.h * @author MCD Application Team * @brief Header file of PWR LL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_PWR_H #define __STM32F3xx_LL_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined(PWR) /** @defgroup PWR_LL PWR * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants * @{ */ /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines * @brief Flags defines which can be used with LL_PWR_WriteReg function * @{ */ #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ /** * @} */ /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_PWR_ReadReg function * @{ */ #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ #if defined(PWR_PVD_SUPPORT) #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ #endif /* PWR_PVD_SUPPORT */ #if defined(PWR_CSR_VREFINTRDYF) #define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ #endif /* PWR_CSR_VREFINTRDYF */ #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ #if defined(PWR_CSR_EWUP3) #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ #endif /* PWR_CSR_EWUP3 */ /** * @} */ /** @defgroup PWR_LL_EC_MODE_PWR Mode Power * @{ */ #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ /** * @} */ #if defined(PWR_CR_LPDS) /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode * @{ */ #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ /** * @} */ #endif /* PWR_CR_LPDS */ #if defined(PWR_PVD_SUPPORT) /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level * @{ */ #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ /** * @} */ #endif /* PWR_PVD_SUPPORT */ /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins * @{ */ #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ #if defined(PWR_CSR_EWUP3) #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ #endif /* PWR_CSR_EWUP3 */ /** * @} */ /** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx * @{ */ #if defined(SDADC1) #define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */ #endif /* SDADC1 */ #if defined(SDADC2) #define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */ #endif /* SDADC2 */ #if defined(SDADC3) #define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */ #endif /* SDADC3 */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros * @{ */ /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros * @{ */ /** * @brief Write a value in PWR register * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) /** * @brief Read a value in PWR register * @param __REG__ Register to be read * @retval Register value */ #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions * @{ */ /** @defgroup PWR_LL_EF_Configuration Configuration * @{ */ /** * @brief Enables the SDADC peripheral functionality * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n * CR ENSD2 LL_PWR_EnableSDADC\n * CR ENSD3 LL_PWR_EnableSDADC * @param Analogx This parameter can be a combination of the following values: * @arg @ref LL_PWR_SDADC_ANALOG1 * @arg @ref LL_PWR_SDADC_ANALOG2 * @arg @ref LL_PWR_SDADC_ANALOG3 * @retval None */ __STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx) { SET_BIT(PWR->CR, Analogx); } /** * @brief Disables the SDADC peripheral functionality * @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n * CR ENSD2 LL_PWR_EnableSDADC\n * CR ENSD3 LL_PWR_EnableSDADC * @param Analogx This parameter can be a combination of the following values: * @arg @ref LL_PWR_SDADC_ANALOG1 * @arg @ref LL_PWR_SDADC_ANALOG2 * @arg @ref LL_PWR_SDADC_ANALOG3 * @retval None */ __STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx) { CLEAR_BIT(PWR->CR, Analogx); } /** * @brief Check if SDADCx has been enabled or not * @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n * CR ENSD2 LL_PWR_IsEnabledSDADC\n * CR ENSD3 LL_PWR_IsEnabledSDADC * @param Analogx This parameter can be a combination of the following values: * @arg @ref LL_PWR_SDADC_ANALOG1 * @arg @ref LL_PWR_SDADC_ANALOG2 * @arg @ref LL_PWR_SDADC_ANALOG3 * @retval None */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx) { return (READ_BIT(PWR->CR, Analogx) == (Analogx)); } /** * @brief Enable access to the backup domain * @rmtoll CR DBP LL_PWR_EnableBkUpAccess * @retval None */ __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) { SET_BIT(PWR->CR, PWR_CR_DBP); } /** * @brief Disable access to the backup domain * @rmtoll CR DBP LL_PWR_DisableBkUpAccess * @retval None */ __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) { CLEAR_BIT(PWR->CR, PWR_CR_DBP); } /** * @brief Check if the backup domain is enabled * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) { return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); } #if defined(PWR_CR_LPDS) /** * @brief Set voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_SetRegulModeDS * @param RegulMode This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER * @retval None */ __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) { MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); } /** * @brief Get voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_GetRegulModeDS * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER */ __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) { return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); } #endif /* PWR_CR_LPDS */ /** * @brief Set Power Down mode when CPU enters deepsleep * @rmtoll CR PDDS LL_PWR_SetPowerMode\n * @rmtoll CR LPDS LL_PWR_SetPowerMode * @param PDMode This parameter can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU * @arg @ref LL_PWR_MODE_STANDBY * @retval None */ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) { MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); } /** * @brief Get Power Down mode when CPU enters deepsleep * @rmtoll CR PDDS LL_PWR_GetPowerMode\n * @rmtoll CR LPDS LL_PWR_GetPowerMode * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_MODE_STOP_MAINREGU * @arg @ref LL_PWR_MODE_STOP_LPREGU * @arg @ref LL_PWR_MODE_STANDBY */ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) { return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); } #if defined(PWR_PVD_SUPPORT) /** * @brief Configure the voltage threshold detected by the Power Voltage Detector * @rmtoll CR PLS LL_PWR_SetPVDLevel * @param PVDLevel This parameter can be one of the following values: * @arg @ref LL_PWR_PVDLEVEL_0 * @arg @ref LL_PWR_PVDLEVEL_1 * @arg @ref LL_PWR_PVDLEVEL_2 * @arg @ref LL_PWR_PVDLEVEL_3 * @arg @ref LL_PWR_PVDLEVEL_4 * @arg @ref LL_PWR_PVDLEVEL_5 * @arg @ref LL_PWR_PVDLEVEL_6 * @arg @ref LL_PWR_PVDLEVEL_7 * @retval None */ __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) { MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); } /** * @brief Get the voltage threshold detection * @rmtoll CR PLS LL_PWR_GetPVDLevel * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_PVDLEVEL_0 * @arg @ref LL_PWR_PVDLEVEL_1 * @arg @ref LL_PWR_PVDLEVEL_2 * @arg @ref LL_PWR_PVDLEVEL_3 * @arg @ref LL_PWR_PVDLEVEL_4 * @arg @ref LL_PWR_PVDLEVEL_5 * @arg @ref LL_PWR_PVDLEVEL_6 * @arg @ref LL_PWR_PVDLEVEL_7 */ __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) { return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); } /** * @brief Enable Power Voltage Detector * @rmtoll CR PVDE LL_PWR_EnablePVD * @retval None */ __STATIC_INLINE void LL_PWR_EnablePVD(void) { SET_BIT(PWR->CR, PWR_CR_PVDE); } /** * @brief Disable Power Voltage Detector * @rmtoll CR PVDE LL_PWR_DisablePVD * @retval None */ __STATIC_INLINE void LL_PWR_DisablePVD(void) { CLEAR_BIT(PWR->CR, PWR_CR_PVDE); } /** * @brief Check if Power Voltage Detector is enabled * @rmtoll CR PVDE LL_PWR_IsEnabledPVD * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) { return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); } #endif /* PWR_PVD_SUPPORT */ /** * @brief Enable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * * (*) not available on all devices * @retval None */ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) { SET_BIT(PWR->CSR, WakeUpPin); } /** * @brief Disable the WakeUp PINx functionality * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * * (*) not available on all devices * @retval None */ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) { CLEAR_BIT(PWR->CSR, WakeUpPin); } /** * @brief Check if the WakeUp PINx functionality is enabled * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin * @param WakeUpPin This parameter can be one of the following values: * @arg @ref LL_PWR_WAKEUP_PIN1 * @arg @ref LL_PWR_WAKEUP_PIN2 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) * * (*) not available on all devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) { return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); } /** * @} */ /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management * @{ */ /** * @brief Get Wake-up Flag * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) { return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); } /** * @brief Get Standby Flag * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) { return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); } #if defined(PWR_PVD_SUPPORT) /** * @brief Indicate whether VDD voltage is below the selected PVD threshold * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) { return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); } #endif /* PWR_PVD_SUPPORT */ #if defined(PWR_CSR_VREFINTRDYF) /** * @brief Get Internal Reference VrefInt Flag * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) { return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); } #endif /* PWR_CSR_VREFINTRDYF */ /** * @brief Clear Standby Flag * @rmtoll CR CSBF LL_PWR_ClearFlag_SB * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) { SET_BIT(PWR->CR, PWR_CR_CSBF); } /** * @brief Clear Wake-up Flags * @rmtoll CR CWUF LL_PWR_ClearFlag_WU * @retval None */ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) { SET_BIT(PWR->CR, PWR_CR_CWUF); } /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function * @{ */ ErrorStatus LL_PWR_DeInit(void); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* defined(PWR) */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_PWR_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_rcc.h * @author MCD Application Team * @brief Header file of RCC LL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_RCC_H #define __STM32F3xx_LL_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined(RCC) /** @defgroup RCC_LL RCC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup RCC_LL_Private_Constants RCC Private Constants * @{ */ /* Defines used for the bit position in the register and perform offsets*/ #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */ #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */ #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */ #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */ #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */ #define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */ #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */ #define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */ /** * @} */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Private_Macros RCC Private Macros * @{ */ /** * @} */ #endif /*USE_FULL_LL_DRIVER*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Exported_Types RCC Exported Types * @{ */ /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure * @{ */ /** * @brief RCC Clocks Frequency Structure */ typedef struct { uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ } LL_RCC_ClocksTypeDef; /** * @} */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants * @{ */ /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation * @brief Defines used to adapt values of different oscillators * @note These values could be modified in the user environment according to * HW set-up. * @{ */ #if !defined (HSE_VALUE) #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ #endif /* HSI_VALUE */ #if !defined (LSE_VALUE) #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ /** * @} */ /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines * @brief Flags defines which can be used with LL_RCC_WriteReg function * @{ */ #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ /** * @} */ /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_RCC_ReadReg function * @{ */ #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ #define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */ #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ #if defined(RCC_CSR_V18PWRRSTF) #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */ #endif /* RCC_CSR_V18PWRRSTF */ /** * @} */ /** @defgroup RCC_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions * @{ */ #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ /** * @} */ /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability * @{ */ #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */ #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ /** * @} */ /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch * @{ */ #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ /** * @} */ /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status * @{ */ #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ /** * @} */ /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler * @{ */ #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ /** * @} */ /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) * @{ */ #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) * @{ */ #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection * @{ */ #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ #if defined(RCC_CFGR_PLLNODIV) #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/ #endif /* RCC_CFGR_PLLNODIV */ /** * @} */ /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler * @{ */ #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */ #if defined(RCC_CFGR_MCOPRE) #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */ #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */ #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */ #endif /* RCC_CFGR_MCOPRE */ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency * @{ */ #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection * @{ */ #if defined(RCC_CFGR3_USART1SW_PCLK1) #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */ #else #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */ #endif /*RCC_CFGR3_USART1SW_PCLK1*/ #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */ #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */ #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */ #if defined(RCC_CFGR3_USART2SW) #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */ #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */ #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */ #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */ #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */ #endif /* RCC_CFGR3_USART3SW */ /** * @} */ #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection * @{ */ #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */ #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */ #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */ #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */ #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */ #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */ #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */ #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */ /** * @} */ #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection * @{ */ #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */ #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */ #if defined(RCC_CFGR3_I2C2SW) #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */ #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */ #endif /*RCC_CFGR3_I2C2SW*/ #if defined(RCC_CFGR3_I2C3SW) #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */ #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */ #endif /*RCC_CFGR3_I2C3SW*/ /** * @} */ #if defined(RCC_CFGR_I2SSRC) /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection * @{ */ #define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */ #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */ /** * @} */ #endif /* RCC_CFGR_I2SSRC */ #if defined(RCC_CFGR3_TIMSW) /** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection * @{ */ #define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */ #define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */ #if defined(RCC_CFGR3_TIM8SW) #define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */ #define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */ #endif /*RCC_CFGR3_TIM8SW*/ #if defined(RCC_CFGR3_TIM15SW) #define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */ #define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */ #endif /*RCC_CFGR3_TIM15SW*/ #if defined(RCC_CFGR3_TIM16SW) #define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */ #define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */ #endif /*RCC_CFGR3_TIM16SW*/ #if defined(RCC_CFGR3_TIM17SW) #define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */ #define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */ #endif /*RCC_CFGR3_TIM17SW*/ #if defined(RCC_CFGR3_TIM20SW) #define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */ #define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */ #endif /*RCC_CFGR3_TIM20SW*/ #if defined(RCC_CFGR3_TIM2SW) #define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */ #define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */ #endif /*RCC_CFGR3_TIM2SW*/ #if defined(RCC_CFGR3_TIM34SW) #define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */ #define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */ #endif /*RCC_CFGR3_TIM34SW*/ /** * @} */ #endif /* RCC_CFGR3_TIMSW */ #if defined(HRTIM1) /** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection * @{ */ #define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */ #define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */ /** * @} */ #endif /* HRTIM1 */ #if defined(CEC) /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection * @{ */ #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */ #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */ /** * @} */ #endif /* CEC */ #if defined(USB) /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection * @{ */ #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */ #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */ /** * @} */ #endif /* USB */ #if defined(RCC_CFGR_ADCPRE) /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection * @{ */ #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */ #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */ #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */ #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */ /** * @} */ #elif defined(RCC_CFGR2_ADC1PRES) /** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection * @{ */ #define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */ #define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */ /** * @} */ #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) #if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34) /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection * @{ */ #define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */ /** * @} */ /** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection * @{ */ #define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */ #define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */ /** * @} */ #else /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection * @{ */ #define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */ #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */ /** * @} */ #endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */ #endif /* RCC_CFGR_ADCPRE */ #if defined(RCC_CFGR_SDPRE) /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection * @{ */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */ #define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */ /** * @} */ #endif /* RCC_CFGR_SDPRE */ /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source * @{ */ #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */ #if defined(RCC_CFGR3_USART2SW) #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */ #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */ #endif /* RCC_CFGR3_USART3SW */ /** * @} */ #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source * @{ */ #define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */ #define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */ /** * @} */ #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source * @{ */ #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */ #if defined(RCC_CFGR3_I2C2SW) #define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */ #endif /*RCC_CFGR3_I2C2SW*/ #if defined(RCC_CFGR3_I2C3SW) #define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */ #endif /*RCC_CFGR3_I2C3SW*/ /** * @} */ #if defined(RCC_CFGR_I2SSRC) /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source * @{ */ #define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ /** * @} */ #endif /* RCC_CFGR_I2SSRC */ #if defined(RCC_CFGR3_TIMSW) /** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source * @{ */ #define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */ #if defined(RCC_CFGR3_TIM2SW) #define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */ #endif /*RCC_CFGR3_TIM2SW*/ #if defined(RCC_CFGR3_TIM8SW) #define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */ #endif /*RCC_CFGR3_TIM8SW*/ #if defined(RCC_CFGR3_TIM15SW) #define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */ #endif /*RCC_CFGR3_TIM15SW*/ #if defined(RCC_CFGR3_TIM16SW) #define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */ #endif /*RCC_CFGR3_TIM16SW*/ #if defined(RCC_CFGR3_TIM17SW) #define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */ #endif /*RCC_CFGR3_TIM17SW*/ #if defined(RCC_CFGR3_TIM20SW) #define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */ #endif /*RCC_CFGR3_TIM20SW*/ #if defined(RCC_CFGR3_TIM34SW) #define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */ #endif /*RCC_CFGR3_TIM34SW*/ /** * @} */ #endif /* RCC_CFGR3_TIMSW */ #if defined(HRTIM1) /** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source * @{ */ #define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */ /** * @} */ #endif /* HRTIM1 */ #if defined(CEC) /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source * @{ */ #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */ /** * @} */ #endif /* CEC */ #if defined(USB) /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source * @{ */ #define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */ /** * @} */ #endif /* USB */ #if defined(RCC_CFGR_ADCPRE) /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source * @{ */ #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ /** * @} */ #endif /* RCC_CFGR_ADCPRE */ #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) /** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source * @{ */ #if defined(RCC_CFGR2_ADC1PRES) #define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */ #else #define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */ #if defined(RCC_CFGR2_ADCPRE34) #define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */ #endif /*RCC_CFGR2_ADCPRE34*/ #endif /*RCC_CFGR2_ADC1PRES*/ /** * @} */ #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ #if defined(RCC_CFGR_SDPRE) /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source * @{ */ #define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */ /** * @} */ #endif /* RCC_CFGR_SDPRE */ /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} */ /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor * @{ */ #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */ #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ /** * @} */ /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE * @{ */ #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ #else #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ /** * @} */ /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor * @{ */ #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */ #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */ #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */ #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */ #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */ #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */ #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */ #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */ #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */ #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */ #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */ #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */ #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */ #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */ #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */ #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros * @{ */ /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros * @{ */ /** * @brief Write a value in RCC register * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) /** * @brief Read a value in RCC register * @param __REG__ Register to be read * @retval Register value */ #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) /** * @} */ /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies * @{ */ #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) /** * @brief Helper macro to calculate the PLLCLK frequency * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator() * , @ref LL_RCC_PLL_GetPrediv()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) * @param __PLLMUL__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 * @arg @ref LL_RCC_PLL_MUL_5 * @arg @ref LL_RCC_PLL_MUL_6 * @arg @ref LL_RCC_PLL_MUL_7 * @arg @ref LL_RCC_PLL_MUL_8 * @arg @ref LL_RCC_PLL_MUL_9 * @arg @ref LL_RCC_PLL_MUL_10 * @arg @ref LL_RCC_PLL_MUL_11 * @arg @ref LL_RCC_PLL_MUL_12 * @arg @ref LL_RCC_PLL_MUL_13 * @arg @ref LL_RCC_PLL_MUL_14 * @arg @ref LL_RCC_PLL_MUL_15 * @arg @ref LL_RCC_PLL_MUL_16 * @param __PLLPREDIV__ This parameter can be one of the following values: * @arg @ref LL_RCC_PREDIV_DIV_1 * @arg @ref LL_RCC_PREDIV_DIV_2 * @arg @ref LL_RCC_PREDIV_DIV_3 * @arg @ref LL_RCC_PREDIV_DIV_4 * @arg @ref LL_RCC_PREDIV_DIV_5 * @arg @ref LL_RCC_PREDIV_DIV_6 * @arg @ref LL_RCC_PREDIV_DIV_7 * @arg @ref LL_RCC_PREDIV_DIV_8 * @arg @ref LL_RCC_PREDIV_DIV_9 * @arg @ref LL_RCC_PREDIV_DIV_10 * @arg @ref LL_RCC_PREDIV_DIV_11 * @arg @ref LL_RCC_PREDIV_DIV_12 * @arg @ref LL_RCC_PREDIV_DIV_13 * @arg @ref LL_RCC_PREDIV_DIV_14 * @arg @ref LL_RCC_PREDIV_DIV_15 * @arg @ref LL_RCC_PREDIV_DIV_16 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \ (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) #else /** * @brief Helper macro to calculate the PLLCLK frequency * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2) * @param __PLLMUL__ This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 * @arg @ref LL_RCC_PLL_MUL_5 * @arg @ref LL_RCC_PLL_MUL_6 * @arg @ref LL_RCC_PLL_MUL_7 * @arg @ref LL_RCC_PLL_MUL_8 * @arg @ref LL_RCC_PLL_MUL_9 * @arg @ref LL_RCC_PLL_MUL_10 * @arg @ref LL_RCC_PLL_MUL_11 * @arg @ref LL_RCC_PLL_MUL_12 * @arg @ref LL_RCC_PLL_MUL_13 * @arg @ref LL_RCC_PLL_MUL_14 * @arg @ref LL_RCC_PLL_MUL_15 * @arg @ref LL_RCC_PLL_MUL_16 * @retval PLL clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U)) #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ /** * @brief Helper macro to calculate the HCLK frequency * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) * @param __AHBPRESCALER__ This parameter can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 * @arg @ref LL_RCC_SYSCLK_DIV_8 * @arg @ref LL_RCC_SYSCLK_DIV_16 * @arg @ref LL_RCC_SYSCLK_DIV_64 * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval HCLK clock frequency (in Hz) */ #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) /** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) * @param __HCLKFREQ__ HCLK frequency * @param __APB1PRESCALER__: This parameter can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 * @retval PCLK1 clock frequency (in Hz) */ #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) /** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) * @param __HCLKFREQ__ HCLK frequency * @param __APB2PRESCALER__: This parameter can be one of the following values: * @arg @ref LL_RCC_APB2_DIV_1 * @arg @ref LL_RCC_APB2_DIV_2 * @arg @ref LL_RCC_APB2_DIV_4 * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 * @retval PCLK2 clock frequency (in Hz) */ #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions * @{ */ /** @defgroup RCC_LL_EF_HSE HSE * @{ */ /** * @brief Enable the Clock Security System. * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS * @retval None */ __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) { SET_BIT(RCC->CR, RCC_CR_CSSON); } /** * @brief Disable the Clock Security System. * @note Cannot be disabled in HSE is ready (only by hardware) * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS * @retval None */ __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void) { CLEAR_BIT(RCC->CR, RCC_CR_CSSON); } /** * @brief Enable HSE external oscillator (HSE Bypass) * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass * @retval None */ __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) { SET_BIT(RCC->CR, RCC_CR_HSEBYP); } /** * @brief Disable HSE external oscillator (HSE Bypass) * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass * @retval None */ __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) { CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); } /** * @brief Enable HSE crystal oscillator (HSE ON) * @rmtoll CR HSEON LL_RCC_HSE_Enable * @retval None */ __STATIC_INLINE void LL_RCC_HSE_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSEON); } /** * @brief Disable HSE crystal oscillator (HSE ON) * @rmtoll CR HSEON LL_RCC_HSE_Disable * @retval None */ __STATIC_INLINE void LL_RCC_HSE_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_HSEON); } /** * @brief Check if HSE oscillator Ready * @rmtoll CR HSERDY LL_RCC_HSE_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); } /** * @} */ /** @defgroup RCC_LL_EF_HSI HSI * @{ */ /** * @brief Enable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_HSI_Enable(void) { SET_BIT(RCC->CR, RCC_CR_HSION); } /** * @brief Disable HSI oscillator * @rmtoll CR HSION LL_RCC_HSI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_HSI_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_HSION); } /** * @brief Check if HSI clock is ready * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); } /** * @brief Get HSI Calibration value * @note When HSITRIM is written, HSICAL is updated with the sum of * HSITRIM and the factory trim value * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration * @retval Between Min_Data = 0x00 and Max_Data = 0xFF */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) { return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); } /** * @brief Set HSI Calibration trimming * @note user-programmable trimming value that is added to the HSICAL * @note Default value is 16, which, when added to the HSICAL value, * should trim the HSI to 16 MHz +/- 1 % * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming * @param Value between Min_Data = 0x00 and Max_Data = 0x1F * @retval None */ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) { MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); } /** * @brief Get HSI Calibration trimming * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming * @retval Between Min_Data = 0x00 and Max_Data = 0x1F */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) { return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); } /** * @} */ /** @defgroup RCC_LL_EF_LSE LSE * @{ */ /** * @brief Enable Low Speed External (LSE) crystal. * @rmtoll BDCR LSEON LL_RCC_LSE_Enable * @retval None */ __STATIC_INLINE void LL_RCC_LSE_Enable(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); } /** * @brief Disable Low Speed External (LSE) crystal. * @rmtoll BDCR LSEON LL_RCC_LSE_Disable * @retval None */ __STATIC_INLINE void LL_RCC_LSE_Disable(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); } /** * @brief Enable external clock source (LSE bypass). * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass * @retval None */ __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } /** * @brief Disable external clock source (LSE bypass). * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass * @retval None */ __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); } /** * @brief Set LSE oscillator drive capability * @note The oscillator is in Xtal mode when it is not in bypass mode. * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability * @param LSEDrive This parameter can be one of the following values: * @arg @ref LL_RCC_LSEDRIVE_LOW * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH * @arg @ref LL_RCC_LSEDRIVE_HIGH * @retval None */ __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) { MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); } /** * @brief Get LSE oscillator drive capability * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_LSEDRIVE_LOW * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH * @arg @ref LL_RCC_LSEDRIVE_HIGH */ __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) { return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); } /** * @brief Check if LSE oscillator Ready * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) { return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); } /** * @} */ /** @defgroup RCC_LL_EF_LSI LSI * @{ */ /** * @brief Enable LSI Oscillator * @rmtoll CSR LSION LL_RCC_LSI_Enable * @retval None */ __STATIC_INLINE void LL_RCC_LSI_Enable(void) { SET_BIT(RCC->CSR, RCC_CSR_LSION); } /** * @brief Disable LSI Oscillator * @rmtoll CSR LSION LL_RCC_LSI_Disable * @retval None */ __STATIC_INLINE void LL_RCC_LSI_Disable(void) { CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); } /** * @brief Check if LSI is Ready * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) { return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); } /** * @} */ /** @defgroup RCC_LL_EF_System System * @{ */ /** * @brief Configure the system clock source * @rmtoll CFGR SW LL_RCC_SetSysClkSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL * @retval None */ __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) { MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); } /** * @brief Get the system clock source * @rmtoll CFGR SWS LL_RCC_GetSysClkSource * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL */ __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); } /** * @brief Set AHB prescaler * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 * @arg @ref LL_RCC_SYSCLK_DIV_8 * @arg @ref LL_RCC_SYSCLK_DIV_16 * @arg @ref LL_RCC_SYSCLK_DIV_64 * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval None */ __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); } /** * @brief Set APB1 prescaler * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); } /** * @brief Set APB2 prescaler * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler * @param Prescaler This parameter can be one of the following values: * @arg @ref LL_RCC_APB2_DIV_1 * @arg @ref LL_RCC_APB2_DIV_2 * @arg @ref LL_RCC_APB2_DIV_4 * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); } /** * @brief Get AHB prescaler * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SYSCLK_DIV_1 * @arg @ref LL_RCC_SYSCLK_DIV_2 * @arg @ref LL_RCC_SYSCLK_DIV_4 * @arg @ref LL_RCC_SYSCLK_DIV_8 * @arg @ref LL_RCC_SYSCLK_DIV_16 * @arg @ref LL_RCC_SYSCLK_DIV_64 * @arg @ref LL_RCC_SYSCLK_DIV_128 * @arg @ref LL_RCC_SYSCLK_DIV_256 * @arg @ref LL_RCC_SYSCLK_DIV_512 */ __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); } /** * @brief Get APB1 prescaler * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_APB1_DIV_1 * @arg @ref LL_RCC_APB1_DIV_2 * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); } /** * @brief Get APB2 prescaler * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_APB2_DIV_1 * @arg @ref LL_RCC_APB2_DIV_2 * @arg @ref LL_RCC_APB2_DIV_4 * @arg @ref LL_RCC_APB2_DIV_8 * @arg @ref LL_RCC_APB2_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); } /** * @} */ /** @defgroup RCC_LL_EF_MCO MCO * @{ */ /** * @brief Configure MCOx * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n * CFGR MCOPRE LL_RCC_ConfigMCO\n * CFGR PLLNODIV LL_RCC_ConfigMCO * @param MCOxSource This parameter can be one of the following values: * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK * @arg @ref LL_RCC_MCO1SOURCE_HSI * @arg @ref LL_RCC_MCO1SOURCE_HSE * @arg @ref LL_RCC_MCO1SOURCE_LSI * @arg @ref LL_RCC_MCO1SOURCE_LSE * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*) * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 * * (*) value not defined in all devices * @param MCOxPrescaler This parameter can be one of the following values: * @arg @ref LL_RCC_MCO1_DIV_1 * @arg @ref LL_RCC_MCO1_DIV_2 (*) * @arg @ref LL_RCC_MCO1_DIV_4 (*) * @arg @ref LL_RCC_MCO1_DIV_8 (*) * @arg @ref LL_RCC_MCO1_DIV_16 (*) * @arg @ref LL_RCC_MCO1_DIV_32 (*) * @arg @ref LL_RCC_MCO1_DIV_64 (*) * @arg @ref LL_RCC_MCO1_DIV_128 (*) * * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) { #if defined(RCC_CFGR_MCOPRE) #if defined(RCC_CFGR_PLLNODIV) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler); #else MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); #endif /* RCC_CFGR_PLLNODIV */ #else MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); #endif /* RCC_CFGR_MCOPRE */ } /** * @} */ /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source * @{ */ /** * @brief Configure USARTx clock source * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n * CFGR3 USART3SW LL_RCC_SetUSARTClockSource * @param USARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) { MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU)); } #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) /** * @brief Configure UARTx clock source * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n * CFGR3 UART5SW LL_RCC_SetUARTClockSource * @param UARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI * @retval None */ __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) { MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW))); } #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ /** * @brief Configure I2Cx clock source * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n * CFGR3 I2C3SW LL_RCC_SetI2CClockSource * @param I2CxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU)); } #if defined(RCC_CFGR_I2SSRC) /** * @brief Configure I2Sx clock source * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource * @param I2SxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN * @retval None */ __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) { MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource); } #endif /* RCC_CFGR_I2SSRC */ #if defined(RCC_CFGR3_TIMSW) /** * @brief Configure TIMx clock source * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n * CFGR3 TIM34SW LL_RCC_SetTIMClockSource * @param TIMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource) { MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU)); } #endif /* RCC_CFGR3_TIMSW */ #if defined(HRTIM1) /** * @brief Configure HRTIMx clock source * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource * @param HRTIMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL * @retval None */ __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource) { MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource); } #endif /* HRTIM1 */ #if defined(CEC) /** * @brief Configure CEC clock source * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource * @param CECxSource This parameter can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE * @retval None */ __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) { MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource); } #endif /* CEC */ #if defined(USB) /** * @brief Configure USB clock source * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 * @retval None */ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) { MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); } #endif /* USB */ #if defined(RCC_CFGR_ADCPRE) /** * @brief Configure ADC clock source * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 * @retval None */ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) { MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); } #elif defined(RCC_CFGR2_ADC1PRES) /** * @brief Configure ADC clock source * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 * @retval None */ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) { MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource); } #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) /** * @brief Configure ADC clock source * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) { #if defined(RCC_CFGR2_ADCPRE34) MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU)); #else MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource); #endif /* RCC_CFGR2_ADCPRE34 */ } #endif /* RCC_CFGR_ADCPRE */ #if defined(RCC_CFGR_SDPRE) /** * @brief Configure SDADCx clock source * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource * @param SDADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 * @retval None */ __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource) { MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource); } #endif /* RCC_CFGR_SDPRE */ /** * @brief Get USARTx clock source * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n * CFGR3 USART3SW LL_RCC_GetUSARTClockSource * @param USARTx This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE * @arg @ref LL_RCC_USART2_CLKSOURCE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE (*) * * (*) value not defined in all devices. * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) { return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U)); } #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW) /** * @brief Get UARTx clock source * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n * CFGR3 UART5SW LL_RCC_GetUARTClockSource * @param UARTx This parameter can be one of the following values: * @arg @ref LL_RCC_UART4_CLKSOURCE * @arg @ref LL_RCC_UART5_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI */ __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) { return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U)); } #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */ /** * @brief Get I2Cx clock source * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n * CFGR3 I2C3SW LL_RCC_GetI2CClockSource * @param I2Cx This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) * * (*) value not defined in all devices. * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) { return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U)); } #if defined(RCC_CFGR_I2SSRC) /** * @brief Get I2Sx clock source * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource * @param I2Sx This parameter can be one of the following values: * @arg @ref LL_RCC_I2S_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN */ __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) { return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); } #endif /* RCC_CFGR_I2SSRC */ #if defined(RCC_CFGR3_TIMSW) /** * @brief Get TIMx clock source * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n * CFGR3 TIM34SW LL_RCC_GetTIMClockSource * @param TIMx This parameter can be one of the following values: * @arg @ref LL_RCC_TIM1_CLKSOURCE * @arg @ref LL_RCC_TIM2_CLKSOURCE (*) * @arg @ref LL_RCC_TIM8_CLKSOURCE (*) * @arg @ref LL_RCC_TIM15_CLKSOURCE (*) * @arg @ref LL_RCC_TIM16_CLKSOURCE (*) * @arg @ref LL_RCC_TIM17_CLKSOURCE (*) * @arg @ref LL_RCC_TIM20_CLKSOURCE (*) * @arg @ref LL_RCC_TIM34_CLKSOURCE (*) * * (*) value not defined in all devices. * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*) * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*) * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx) { return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U)); } #endif /* RCC_CFGR3_TIMSW */ #if defined(HRTIM1) /** * @brief Get HRTIMx clock source * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource * @param HRTIMx This parameter can be one of the following values: * @arg @ref LL_RCC_HRTIM1_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL */ __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx) { return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx)); } #endif /* HRTIM1 */ #if defined(CEC) /** * @brief Get CEC clock source * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource * @param CECx This parameter can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE */ __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) { return (uint32_t)(READ_BIT(RCC->CFGR3, CECx)); } #endif /* CEC */ #if defined(USB) /** * @brief Get USBx clock source * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource * @param USBx This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE_PLL * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 */ __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) { return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); } #endif /* USB */ #if defined(RCC_CFGR_ADCPRE) /** * @brief Get ADCx clock source * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource * @param ADCx This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 */ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) { return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); } #elif defined(RCC_CFGR2_ADC1PRES) /** * @brief Get ADCx clock source * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource * @param ADCx This parameter can be one of the following values: * @arg @ref LL_RCC_ADC1_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256 */ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) { return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); } #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) /** * @brief Get ADCx clock source * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource * @param ADCx This parameter can be one of the following values: * @arg @ref LL_RCC_ADC12_CLKSOURCE * @arg @ref LL_RCC_ADC34_CLKSOURCE (*) * * (*) value not defined in all devices. * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*) * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) { #if defined(RCC_CFGR2_ADCPRE34) return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U)); #else return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx)); #endif /*RCC_CFGR2_ADCPRE34*/ } #endif /* RCC_CFGR_ADCPRE */ #if defined(RCC_CFGR_SDPRE) /** * @brief Get SDADCx clock source * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource * @param SDADCx This parameter can be one of the following values: * @arg @ref LL_RCC_SDADC_CLKSOURCE * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48 */ __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx) { return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx)); } #endif /* RCC_CFGR_SDPRE */ /** * @} */ /** @defgroup RCC_LL_EF_RTC RTC * @{ */ /** * @brief Set RTC Clock Source * @note Once the RTC clock source has been selected, it cannot be changed any more unless * the Backup domain is reset. The BDRST bit can be used to reset them. * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 * @retval None */ __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) { MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); } /** * @brief Get RTC Clock Source * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 */ __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) { return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); } /** * @brief Enable RTC * @rmtoll BDCR RTCEN LL_RCC_EnableRTC * @retval None */ __STATIC_INLINE void LL_RCC_EnableRTC(void) { SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); } /** * @brief Disable RTC * @rmtoll BDCR RTCEN LL_RCC_DisableRTC * @retval None */ __STATIC_INLINE void LL_RCC_DisableRTC(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); } /** * @brief Check if RTC has been enabled or not * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) { return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); } /** * @brief Force the Backup domain reset * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset * @retval None */ __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) { SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); } /** * @brief Release the Backup domain reset * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset * @retval None */ __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); } /** * @} */ /** @defgroup RCC_LL_EF_PLL PLL * @{ */ /** * @brief Enable PLL * @rmtoll CR PLLON LL_RCC_PLL_Enable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Enable(void) { SET_BIT(RCC->CR, RCC_CR_PLLON); } /** * @brief Disable PLL * @note Cannot be disabled if the PLL clock is used as the system clock * @rmtoll CR PLLON LL_RCC_PLL_Disable * @retval None */ __STATIC_INLINE void LL_RCC_PLL_Disable(void) { CLEAR_BIT(RCC->CR, RCC_CR_PLLON); } /** * @brief Check if PLL Ready * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) { return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); } #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) /** * @brief Configure PLL used for SYSCLK Domain * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI * @arg @ref LL_RCC_PLLSOURCE_HSE * @param PLLMul This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 * @arg @ref LL_RCC_PLL_MUL_5 * @arg @ref LL_RCC_PLL_MUL_6 * @arg @ref LL_RCC_PLL_MUL_7 * @arg @ref LL_RCC_PLL_MUL_8 * @arg @ref LL_RCC_PLL_MUL_9 * @arg @ref LL_RCC_PLL_MUL_10 * @arg @ref LL_RCC_PLL_MUL_11 * @arg @ref LL_RCC_PLL_MUL_12 * @arg @ref LL_RCC_PLL_MUL_13 * @arg @ref LL_RCC_PLL_MUL_14 * @arg @ref LL_RCC_PLL_MUL_15 * @arg @ref LL_RCC_PLL_MUL_16 * @param PLLDiv This parameter can be one of the following values: * @arg @ref LL_RCC_PREDIV_DIV_1 * @arg @ref LL_RCC_PREDIV_DIV_2 * @arg @ref LL_RCC_PREDIV_DIV_3 * @arg @ref LL_RCC_PREDIV_DIV_4 * @arg @ref LL_RCC_PREDIV_DIV_5 * @arg @ref LL_RCC_PREDIV_DIV_6 * @arg @ref LL_RCC_PREDIV_DIV_7 * @arg @ref LL_RCC_PREDIV_DIV_8 * @arg @ref LL_RCC_PREDIV_DIV_9 * @arg @ref LL_RCC_PREDIV_DIV_10 * @arg @ref LL_RCC_PREDIV_DIV_11 * @arg @ref LL_RCC_PREDIV_DIV_12 * @arg @ref LL_RCC_PREDIV_DIV_13 * @arg @ref LL_RCC_PREDIV_DIV_14 * @arg @ref LL_RCC_PREDIV_DIV_15 * @arg @ref LL_RCC_PREDIV_DIV_16 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul); MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); } #else /** * @brief Configure PLL used for SYSCLK Domain * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS * @param Source This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 * @param PLLMul This parameter can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 * @arg @ref LL_RCC_PLL_MUL_5 * @arg @ref LL_RCC_PLL_MUL_6 * @arg @ref LL_RCC_PLL_MUL_7 * @arg @ref LL_RCC_PLL_MUL_8 * @arg @ref LL_RCC_PLL_MUL_9 * @arg @ref LL_RCC_PLL_MUL_10 * @arg @ref LL_RCC_PLL_MUL_11 * @arg @ref LL_RCC_PLL_MUL_12 * @arg @ref LL_RCC_PLL_MUL_13 * @arg @ref LL_RCC_PLL_MUL_14 * @arg @ref LL_RCC_PLL_MUL_15 * @arg @ref LL_RCC_PLL_MUL_16 * @retval None */ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); } #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ /** * @brief Configure PLL clock source * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource * @param PLLSource This parameter can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_NONE * @arg @ref LL_RCC_PLLSOURCE_HSI (*) * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) * @arg @ref LL_RCC_PLLSOURCE_HSE * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*) * * (*) value not defined in all devices * @retval None */ __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); } /** * @brief Get the oscillator used as PLL clock source. * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLLSOURCE_NONE * @arg @ref LL_RCC_PLLSOURCE_HSI (*) * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) * @arg @ref LL_RCC_PLLSOURCE_HSE * * (*) value not defined in all devices */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); } /** * @brief Get PLL multiplication Factor * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PLL_MUL_2 * @arg @ref LL_RCC_PLL_MUL_3 * @arg @ref LL_RCC_PLL_MUL_4 * @arg @ref LL_RCC_PLL_MUL_5 * @arg @ref LL_RCC_PLL_MUL_6 * @arg @ref LL_RCC_PLL_MUL_7 * @arg @ref LL_RCC_PLL_MUL_8 * @arg @ref LL_RCC_PLL_MUL_9 * @arg @ref LL_RCC_PLL_MUL_10 * @arg @ref LL_RCC_PLL_MUL_11 * @arg @ref LL_RCC_PLL_MUL_12 * @arg @ref LL_RCC_PLL_MUL_13 * @arg @ref LL_RCC_PLL_MUL_14 * @arg @ref LL_RCC_PLL_MUL_15 * @arg @ref LL_RCC_PLL_MUL_16 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) { return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); } /** * @brief Get PREDIV division factor for the main PLL * @note They can be written only when the PLL is disabled * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv * @retval Returned value can be one of the following values: * @arg @ref LL_RCC_PREDIV_DIV_1 * @arg @ref LL_RCC_PREDIV_DIV_2 * @arg @ref LL_RCC_PREDIV_DIV_3 * @arg @ref LL_RCC_PREDIV_DIV_4 * @arg @ref LL_RCC_PREDIV_DIV_5 * @arg @ref LL_RCC_PREDIV_DIV_6 * @arg @ref LL_RCC_PREDIV_DIV_7 * @arg @ref LL_RCC_PREDIV_DIV_8 * @arg @ref LL_RCC_PREDIV_DIV_9 * @arg @ref LL_RCC_PREDIV_DIV_10 * @arg @ref LL_RCC_PREDIV_DIV_11 * @arg @ref LL_RCC_PREDIV_DIV_12 * @arg @ref LL_RCC_PREDIV_DIV_13 * @arg @ref LL_RCC_PREDIV_DIV_14 * @arg @ref LL_RCC_PREDIV_DIV_15 * @arg @ref LL_RCC_PREDIV_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) { return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)); } /** * @} */ /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management * @{ */ /** * @brief Clear LSI ready interrupt flag * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); } /** * @brief Clear LSE ready interrupt flag * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); } /** * @brief Clear HSI ready interrupt flag * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); } /** * @brief Clear HSE ready interrupt flag * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); } /** * @brief Clear PLL ready interrupt flag * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); } /** * @brief Clear Clock security system interrupt flag * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS * @retval None */ __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) { SET_BIT(RCC->CIR, RCC_CIR_CSSC); } /** * @brief Check if LSI ready interrupt occurred or not * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); } /** * @brief Check if LSE ready interrupt occurred or not * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); } /** * @brief Check if HSI ready interrupt occurred or not * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); } /** * @brief Check if HSE ready interrupt occurred or not * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); } #if defined(RCC_CFGR_MCOF) /** * @brief Check if switch to new MCO source is effective or not * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1 * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void) { return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF)); } #endif /* RCC_CFGR_MCOF */ /** * @brief Check if PLL ready interrupt occurred or not * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); } /** * @brief Check if Clock security system interrupt occurred or not * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) { return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); } /** * @brief Check if RCC flag Independent Watchdog reset is set or not. * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); } /** * @brief Check if RCC flag Low Power reset is set or not. * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); } /** * @brief Check if RCC flag is set or not. * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)); } /** * @brief Check if RCC flag Pin reset is set or not. * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); } /** * @brief Check if RCC flag POR/PDR reset is set or not. * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); } /** * @brief Check if RCC flag Software reset is set or not. * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); } /** * @brief Check if RCC flag Window Watchdog reset is set or not. * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); } #if defined(RCC_CSR_V18PWRRSTF) /** * @brief Check if RCC Reset flag of the 1.8 V domain is set or not. * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void) { return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF)); } #endif /* RCC_CSR_V18PWRRSTF */ /** * @brief Set RMVF bit to clear the reset flags. * @rmtoll CSR RMVF LL_RCC_ClearResetFlags * @retval None */ __STATIC_INLINE void LL_RCC_ClearResetFlags(void) { SET_BIT(RCC->CSR, RCC_CSR_RMVF); } /** * @} */ /** @defgroup RCC_LL_EF_IT_Management IT Management * @{ */ /** * @brief Enable LSI ready interrupt * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); } /** * @brief Enable LSE ready interrupt * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); } /** * @brief Enable HSI ready interrupt * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); } /** * @brief Enable HSE ready interrupt * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) { SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); } /** * @brief Enable PLL ready interrupt * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY * @retval None */ __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) { SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); } /** * @brief Disable LSI ready interrupt * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); } /** * @brief Disable LSE ready interrupt * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); } /** * @brief Disable HSI ready interrupt * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); } /** * @brief Disable HSE ready interrupt * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); } /** * @brief Disable PLL ready interrupt * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY * @retval None */ __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) { CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); } /** * @brief Checks if LSI ready interrupt source is enabled or disabled. * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); } /** * @brief Checks if LSE ready interrupt source is enabled or disabled. * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); } /** * @brief Checks if HSI ready interrupt source is enabled or disabled. * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); } /** * @brief Checks if HSE ready interrupt source is enabled or disabled. * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); } /** * @brief Checks if PLL ready interrupt source is enabled or disabled. * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) { return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); } /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_EF_Init De-initialization function * @{ */ ErrorStatus LL_RCC_DeInit(void); /** * @} */ /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions * @{ */ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); #if defined(UART4) || defined(UART5) uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); #endif /* UART4 || UART5 */ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); #if defined(RCC_CFGR_I2SSRC) uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); #endif /* RCC_CFGR_I2SSRC */ #if defined(USB_OTG_FS) || defined(USB) uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); #endif /* USB_OTG_FS || USB */ #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)) uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ #if defined(RCC_CFGR_SDPRE) uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource); #endif /*RCC_CFGR_SDPRE */ #if defined(CEC) uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); #endif /* CEC */ #if defined(RCC_CFGR3_TIMSW) uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource); #endif /*RCC_CFGR3_TIMSW*/ uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* RCC */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_RCC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_system.h * @author MCD Application Team * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The LL SYSTEM driver contains a set of generic APIs that can be used by user: (+) Some of the FLASH features need to be handled in the SYSTEM file. (+) Access to DBGCMU registers (+) Access to SYSCFG registers @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_SYSTEM_H #define __STM32F3xx_LL_SYSTEM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) /** @defgroup SYSTEM_LL SYSTEM * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants * @{ */ /* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */ #define SYSCFG_OFFSET_CFGR1 0x00000000U #define SYSCFG_OFFSET_CFGR3 0x00000050U /* Mask used for TIM breaks functions */ #if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK) #elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK) #elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK) #else #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK) #endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants * @{ */ /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP * @{ */ #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */ #if defined(FMC_BANK1) #define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); } /** * @brief Get memory mapping at address 0x00000000 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_REMAP_FLASH * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH * @arg @ref LL_SYSCFG_REMAP_SRAM * @arg @ref LL_SYSCFG_REMAP_FMC (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) { return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); } #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP) /** * @brief Set DMA request remapping bits for SPI * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI * @param Remap This parameter can be one of the following values: * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap) { MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF)); } #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */ #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP) /** * @brief Set DMA request remapping bits for I2C * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C * @param Remap This parameter can be one of the following values: * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap) { MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF)); } #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */ #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP) /** * @brief Set DMA request remapping bits for ADC * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC * @param Remap This parameter can be one of the following values: * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*) * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*) * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*) * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*) * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*) * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U)); MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU)); } #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */ /** * @brief Set DMA request remapping bits for DAC * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC * @param Remap This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*) * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*) * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*) * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*) * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*) * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap) { MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U)); } /** * @brief Set DMA request remapping bits for TIM * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM * @param Remap This parameter can be a combination of the following values: * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3 * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*) * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap) { MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U)); } #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE) /** * @brief Set Timer input remap * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM * @param Remap This parameter can be one of the following values: * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*) * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*) * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*) * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*) * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*) * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap) { MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU)); } #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */ #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP) /** * @brief Set ADC Trigger remap * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC * @param Remap This parameter can be one of the following values: * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap) { MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU)); } #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */ #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP) /** * @brief Set DAC Trigger remap * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC * @param Remap This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*) * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*) * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*) * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*) * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*) * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*) * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U)); MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U)); } #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */ #if defined(SYSCFG_CFGR1_USB_IT_RMP) /** * @brief Enable USB interrupt remap * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76 * respectively * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP); } /** * @brief Disable USB interrupt remap * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP); } #endif /* SYSCFG_CFGR1_USB_IT_RMP */ #if defined(SYSCFG_CFGR1_VBAT) /** * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input) * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT); } /** * @brief Disable VBAT monitoring * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT); } #endif /* SYSCFG_CFGR1_VBAT */ /** * @brief Enable the I2C fast mode plus driving capability. * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus * @param ConfigFastModePlus This parameter can be a combination of the following values: * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) { SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); } /** * @brief Disable the I2C fast mode plus driving capability. * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus * @param ConfigFastModePlus This parameter can be a combination of the following values: * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) { CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); } /** * @brief Enable Floating Point Unit Invalid operation Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); } /** * @brief Enable Floating Point Unit Divide-by-zero Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); } /** * @brief Enable Floating Point Unit Underflow Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); } /** * @brief Enable Floating Point Unit Overflow Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); } /** * @brief Enable Floating Point Unit Input denormal Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); } /** * @brief Enable Floating Point Unit Inexact Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); } /** * @brief Disable Floating Point Unit Invalid operation Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); } /** * @brief Disable Floating Point Unit Divide-by-zero Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); } /** * @brief Disable Floating Point Unit Underflow Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); } /** * @brief Disable Floating Point Unit Overflow Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); } /** * @brief Disable Floating Point Unit Input denormal Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); } /** * @brief Disable Floating Point Unit Inexact Interrupt * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); } /** * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) { return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)); } /** * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) { return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)); } /** * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) { return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)); } /** * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) { return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)); } /** * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) { return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)); } /** * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) { return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)); } /** * @brief Configure source input for the EXTI external interrupt. * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource * @param Port This parameter can be one of the following values: * @arg @ref LL_SYSCFG_EXTI_PORTA * @arg @ref LL_SYSCFG_EXTI_PORTB * @arg @ref LL_SYSCFG_EXTI_PORTC * @arg @ref LL_SYSCFG_EXTI_PORTD * @arg @ref LL_SYSCFG_EXTI_PORTE (*) * @arg @ref LL_SYSCFG_EXTI_PORTF * @arg @ref LL_SYSCFG_EXTI_PORTG (*) * @arg @ref LL_SYSCFG_EXTI_PORTH (*) * * (*) value not defined in all devices. * @param Line This parameter can be one of the following values: * @arg @ref LL_SYSCFG_EXTI_LINE0 * @arg @ref LL_SYSCFG_EXTI_LINE1 * @arg @ref LL_SYSCFG_EXTI_LINE2 * @arg @ref LL_SYSCFG_EXTI_LINE3 * @arg @ref LL_SYSCFG_EXTI_LINE4 * @arg @ref LL_SYSCFG_EXTI_LINE5 * @arg @ref LL_SYSCFG_EXTI_LINE6 * @arg @ref LL_SYSCFG_EXTI_LINE7 * @arg @ref LL_SYSCFG_EXTI_LINE8 * @arg @ref LL_SYSCFG_EXTI_LINE9 * @arg @ref LL_SYSCFG_EXTI_LINE10 * @arg @ref LL_SYSCFG_EXTI_LINE11 * @arg @ref LL_SYSCFG_EXTI_LINE12 * @arg @ref LL_SYSCFG_EXTI_LINE13 * @arg @ref LL_SYSCFG_EXTI_LINE14 * @arg @ref LL_SYSCFG_EXTI_LINE15 * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) { MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); } /** * @brief Get the configured defined for specific EXTI Line * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource * @param Line This parameter can be one of the following values: * @arg @ref LL_SYSCFG_EXTI_LINE0 * @arg @ref LL_SYSCFG_EXTI_LINE1 * @arg @ref LL_SYSCFG_EXTI_LINE2 * @arg @ref LL_SYSCFG_EXTI_LINE3 * @arg @ref LL_SYSCFG_EXTI_LINE4 * @arg @ref LL_SYSCFG_EXTI_LINE5 * @arg @ref LL_SYSCFG_EXTI_LINE6 * @arg @ref LL_SYSCFG_EXTI_LINE7 * @arg @ref LL_SYSCFG_EXTI_LINE8 * @arg @ref LL_SYSCFG_EXTI_LINE9 * @arg @ref LL_SYSCFG_EXTI_LINE10 * @arg @ref LL_SYSCFG_EXTI_LINE11 * @arg @ref LL_SYSCFG_EXTI_LINE12 * @arg @ref LL_SYSCFG_EXTI_LINE13 * @arg @ref LL_SYSCFG_EXTI_LINE14 * @arg @ref LL_SYSCFG_EXTI_LINE15 * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_EXTI_PORTA * @arg @ref LL_SYSCFG_EXTI_PORTB * @arg @ref LL_SYSCFG_EXTI_PORTC * @arg @ref LL_SYSCFG_EXTI_PORTD * @arg @ref LL_SYSCFG_EXTI_PORTE (*) * @arg @ref LL_SYSCFG_EXTI_PORTF * @arg @ref LL_SYSCFG_EXTI_PORTG (*) * @arg @ref LL_SYSCFG_EXTI_PORTH (*) * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) { return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); } /** * @brief Set connections to TIMx Break inputs * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs * @param Break This parameter can be a combination of the following values: * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*) * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) { MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break); } /** * @brief Get connections to TIMx Break inputs * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs * @retval Returned value can be can be a combination of the following values: * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*) * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*) * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) { return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK)); } #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR) /** * @brief Disable RAM Parity Check Disable * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void) { SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR); } #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */ #if defined(SYSCFG_CFGR2_SRAM_PE) /** * @brief Check if SRAM parity error detected * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void) { return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE)); } /** * @brief Clear SRAM parity error flag * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP * @retval None */ __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) { SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE); } #endif /* SYSCFG_CFGR2_SRAM_PE */ #if defined(SYSCFG_RCR_PAGE0) /** * @brief Enable CCM SRAM page write protection * @note Write protection is cleared only by a system reset * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP * @param PageWRP This parameter can be a combination of the following values: * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*) * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP) { SET_BIT(SYSCFG->RCR, PageWRP); } #endif /* SYSCFG_RCR_PAGE0 */ /** * @} */ /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU * @{ */ /** * @brief Return the device identifier * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422 * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432 * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438. * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439 * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID * @retval Values between Min_Data=0x00 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) { return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); } /** * @brief Return the device revision identifier * @note This field indicates the revision of the device. * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** * @brief Enable the Debug Module during SLEEP mode * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Disable the Debug Module during SLEEP mode * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Enable the Debug Module during STOP mode * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Disable the Debug Module during STOP mode * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Enable the Debug Module during STANDBY mode * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Disable the Debug Module during STANDBY mode * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode * @retval None */ __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Set Trace pin assignment control * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment * @param PinAssignment This parameter can be one of the following values: * @arg @ref LL_DBGMCU_TRACE_NONE * @arg @ref LL_DBGMCU_TRACE_ASYNCH * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 * @retval None */ __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) { MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); } /** * @brief Get Trace pin assignment control * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment * @retval Returned value can be one of the following values: * @arg @ref LL_DBGMCU_TRACE_NONE * @arg @ref LL_DBGMCU_TRACE_ASYNCH * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 */ __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) { return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); } /** * @brief Freeze APB1 peripherals (group1 peripherals) * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) { SET_BIT(DBGMCU->APB1FZ, Periphs); } /** * @brief Unfreeze APB1 peripherals (group1 peripherals) * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) { CLEAR_BIT(DBGMCU->APB1FZ, Periphs); } /** * @brief Freeze APB2 peripherals * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) { SET_BIT(DBGMCU->APB2FZ, Periphs); } /** * @brief Unfreeze APB2 peripherals * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*) * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*) * * (*) value not defined in all devices. * @retval None */ __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) { CLEAR_BIT(DBGMCU->APB2FZ, Periphs); } /** * @} */ /** @defgroup SYSTEM_LL_EF_FLASH FLASH * @{ */ /** * @brief Set FLASH Latency * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency * @param Latency This parameter can be one of the following values: * @arg @ref LL_FLASH_LATENCY_0 * @arg @ref LL_FLASH_LATENCY_1 * @arg @ref LL_FLASH_LATENCY_2 * @retval None */ __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) { MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); } /** * @brief Get FLASH Latency * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency * @retval Returned value can be one of the following values: * @arg @ref LL_FLASH_LATENCY_0 * @arg @ref LL_FLASH_LATENCY_1 * @arg @ref LL_FLASH_LATENCY_2 */ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) { return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); } /** * @brief Enable Prefetch * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch * @retval None */ __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) { SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE ); } /** * @brief Disable Prefetch * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch * @retval None */ __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) { CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE ); } /** * @brief Check if Prefetch buffer is enabled * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) { return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); } #if defined(FLASH_ACR_HLFCYA) /** * @brief Enable Flash Half Cycle Access * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess * @retval None */ __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) { SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); } /** * @brief Disable Flash Half Cycle Access * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess * @retval None */ __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) { CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); } /** * @brief Check if Flash Half Cycle Access is enabled or not * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) { return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); } #endif /* FLASH_ACR_HLFCYA */ /** * @} */ /** * @} */ /** * @} */ #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_SYSTEM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_tim.h * @author MCD Application Team * @brief Header file of TIM LL module. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_TIM_H #define __STM32F3xx_LL_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20) /** @defgroup TIM_LL TIM * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup TIM_LL_Private_Variables TIM Private Variables * @{ */ static const uint8_t OFFSET_TAB_CCMRx[] = { 0x00U, /* 0: TIMx_CH1 */ 0x00U, /* 1: TIMx_CH1N */ 0x00U, /* 2: TIMx_CH2 */ 0x00U, /* 3: TIMx_CH2N */ 0x04U, /* 4: TIMx_CH3 */ 0x04U, /* 5: TIMx_CH3N */ 0x04U, /* 6: TIMx_CH4 */ 0x3CU, /* 7: TIMx_CH5 */ 0x3CU /* 8: TIMx_CH6 */ }; static const uint8_t SHIFT_TAB_OCxx[] = { 0U, /* 0: OC1M, OC1FE, OC1PE */ 0U, /* 1: - NA */ 8U, /* 2: OC2M, OC2FE, OC2PE */ 0U, /* 3: - NA */ 0U, /* 4: OC3M, OC3FE, OC3PE */ 0U, /* 5: - NA */ 8U, /* 6: OC4M, OC4FE, OC4PE */ 0U, /* 7: OC5M, OC5FE, OC5PE */ 8U /* 8: OC6M, OC6FE, OC6PE */ }; static const uint8_t SHIFT_TAB_ICxx[] = { 0U, /* 0: CC1S, IC1PSC, IC1F */ 0U, /* 1: - NA */ 8U, /* 2: CC2S, IC2PSC, IC2F */ 0U, /* 3: - NA */ 0U, /* 4: CC3S, IC3PSC, IC3F */ 0U, /* 5: - NA */ 8U, /* 6: CC4S, IC4PSC, IC4F */ 0U, /* 7: - NA */ 0U /* 8: - NA */ }; static const uint8_t SHIFT_TAB_CCxP[] = { 0U, /* 0: CC1P */ 2U, /* 1: CC1NP */ 4U, /* 2: CC2P */ 6U, /* 3: CC2NP */ 8U, /* 4: CC3P */ 10U, /* 5: CC3NP */ 12U, /* 6: CC4P */ 16U, /* 7: CC5P */ 20U /* 8: CC6P */ }; static const uint8_t SHIFT_TAB_OISx[] = { 0U, /* 0: OIS1 */ 1U, /* 1: OIS1N */ 2U, /* 2: OIS2 */ 3U, /* 3: OIS2N */ 4U, /* 4: OIS3 */ 5U, /* 5: OIS3N */ 6U, /* 6: OIS4 */ 8U, /* 7: OIS5 */ 10U /* 8: OIS6 */ }; /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_LL_Private_Constants TIM Private Constants * @{ */ #define TIMx_OR_RMP_SHIFT 16U #define TIMx_OR_RMP_MASK 0x0000FFFFU #if defined(TIM1) #define TIM1_OR_RMP_MASK (TIM1_OR_ETR_RMP << TIMx_OR_RMP_SHIFT) #endif /* TIM1 */ #if defined (TIM8) #define TIM8_OR_RMP_MASK (TIM8_OR_ETR_RMP << TIMx_OR_RMP_SHIFT) #endif /* TIM8 */ #if defined(TIM14) #define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) #endif /* TIM14 */ #if defined(TIM16) #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) #endif /* TIM16 */ #if defined(TIM20) #define TIM20_OR_RMP_MASK (TIM20_OR_ETR_RMP << TIMx_OR_RMP_SHIFT) #endif /* TIM20 */ /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ #define DT_DELAY_1 ((uint8_t)0x7F) #define DT_DELAY_2 ((uint8_t)0x3F) #define DT_DELAY_3 ((uint8_t)0x1F) #define DT_DELAY_4 ((uint8_t)0x1F) /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ #define DT_RANGE_1 ((uint8_t)0x00) #define DT_RANGE_2 ((uint8_t)0x80) #define DT_RANGE_3 ((uint8_t)0xC0) #define DT_RANGE_4 ((uint8_t)0xE0) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_LL_Private_Macros TIM Private Macros * @{ */ /** @brief Convert channel id into channel index. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note CH5 and CH6 channels are not available for all F3 devices * @retval none */ #if defined(TIM_CCR5_CCR5) #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) #else #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) #endif /** @brief Calculate the deadtime sampling period(in ps). * @param __TIMCLK__ timer input clock frequency (in Hz). * @param __CKD__ This parameter can be one of the following values: * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 * @retval none */ #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) /** * @} */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure * @{ */ /** * @brief TIM Time Base configuration structure definition. */ typedef struct { uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; /** * @brief TIM Output Compare configuration structure definition. */ typedef struct { uint32_t OCMode; /*!< Specifies the output mode. This parameter can be a value of @ref TIM_LL_EC_OCMODE. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ uint32_t OCState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ } LL_TIM_OC_InitTypeDef; /** * @brief TIM Input Capture configuration structure definition. */ typedef struct { uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ uint32_t ICActiveInput; /*!< Specifies the input. This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_LL_EC_ICPSC. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_IC_InitTypeDef; /** * @brief TIM Encoder interface configuration structure definition. */ typedef struct { uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC2Filter; /*!< Specifies the TI2 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_ENCODER_InitTypeDef; /** * @brief TIM Hall sensor interface configuration structure definition. */ typedef struct { uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of @ref TIM_LL_EC_ICPSC. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; /** * @brief BDTR (Break and Dead Time) structure definition */ typedef struct { uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_LL_EC_OSSR This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ #if defined(TIM_BDTR_BKF) uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ #endif /* TIM_BDTR_BKF */ #if defined(TIM_BDTR_BK2E) uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ #endif /* TIM_BDTR_BK2E */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ } LL_TIM_BDTR_InitTypeDef; /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants * @{ */ /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_TIM_ReadReg function. * @{ */ #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ #if defined(TIM_CCMR1_OC1M_3) #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ #endif /* TIM_CCMR1_OC1M_3 */ #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable * @{ */ #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ /** * @} */ #if defined(TIM_BDTR_BK2E) /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable * @{ */ #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ /** * @} */ #endif /* TIM_BDTR_BK2E */ /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable * @{ */ #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** @defgroup TIM_LL_EC_IT IT Defines * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. * @{ */ #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ /** * @} */ /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source * @{ */ #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ /** * @} */ /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ /** * @} */ /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ #if defined(TIM_CCMR1_OC1M_3) #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) /** * @brief Read a value in TIM register. * @param __INSTANCE__ TIM Instance * @param __REG__ Register to be read * @retval Register value */ #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros * @{ */ /** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied * to TIMx_CNT register bit 31) * @param __CNT__ Counter value * @retval UIF status bit */ #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) /** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __CKD__ This parameter can be one of the following values: * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 * @param __DT__ deadtime duration (in ns) * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __CNTCLK__ counter clock frequency (in Hz) * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __FREQ__ output signal frequency (in Hz) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @retval Compare value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @param __PULSE__ pulse duration (in us) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @brief HELPER macro retrieving the ratio of the input capture prescaler * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); * @param __ICPSC__ This parameter can be one of the following values: * @arg @ref LL_TIM_ICPSC_DIV1 * @arg @ref LL_TIM_ICPSC_DIV2 * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 * @retval Input capture prescaler ratio (1, 2, 4 or 8) */ #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions * @{ */ /** @defgroup TIM_LL_EF_Time_Base Time Base configuration * @{ */ /** * @brief Enable timer counter. * @rmtoll CR1 CEN LL_TIM_EnableCounter * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) { SET_BIT(TIMx->CR1, TIM_CR1_CEN); } /** * @brief Disable timer counter. * @rmtoll CR1 CEN LL_TIM_DisableCounter * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); } /** * @brief Indicates whether the timer counter is enabled. * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } /** * @brief Enable update event generation. * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** * @brief Disable update event generation. * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) { SET_BIT(TIMx->CR1, TIM_CR1_UDIS); } /** * @brief Indicates whether update event generation is enabled. * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } /** * @brief Set update event source * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events * generate an update interrupt or DMA request if enabled: * - Counter overflow/underflow * - Setting the UG bit * - Update generation through the slave mode controller * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter * overflow/underflow generates an update interrupt or DMA request if enabled. * @rmtoll CR1 URS LL_TIM_SetUpdateSource * @param TIMx Timer instance * @param UpdateSource This parameter can be one of the following values: * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER * @retval None */ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) { MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); } /** * @brief Get actual event update source * @rmtoll CR1 URS LL_TIM_GetUpdateSource * @param TIMx Timer instance * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } /** * @brief Set one pulse mode (one shot v.s. repetitive). * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode * @param TIMx Timer instance * @param OnePulseMode This parameter can be one of the following values: * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE * @retval None */ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) { MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); } /** * @brief Get actual one pulse mode. * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode * @param TIMx Timer instance * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } /** * @brief Set the timer counter counting mode. * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n * CR1 CMS LL_TIM_SetCounterMode * @param TIMx Timer instance * @param CounterMode This parameter can be one of the following values: * @arg @ref LL_TIM_COUNTERMODE_UP * @arg @ref LL_TIM_COUNTERMODE_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN * @retval None */ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) { MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); } /** * @brief Get actual counter mode. * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n * CR1 CMS LL_TIM_GetCounterMode * @param TIMx Timer instance * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_COUNTERMODE_UP * @arg @ref LL_TIM_COUNTERMODE_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); } /** * @brief Enable auto-reload (ARR) preload. * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) { SET_BIT(TIMx->CR1, TIM_CR1_ARPE); } /** * @brief Disable auto-reload (ARR) preload. * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); } /** * @brief Indicates whether auto-reload (ARR) preload is enabled. * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } /** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_SetClockDivision * @param TIMx Timer instance * @param ClockDivision This parameter can be one of the following values: * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 * @retval None */ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) { MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); } /** * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_GetClockDivision * @param TIMx Timer instance * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } /** * @brief Set the counter value. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_SetCounter * @param TIMx Timer instance * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) * @retval None */ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) { WRITE_REG(TIMx->CNT, Counter); } /** * @brief Get the counter value. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_GetCounter * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } /** * @brief Get the current direction of the counter * @rmtoll CR1 DIR LL_TIM_GetDirection * @param TIMx Timer instance * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } /** * @brief Set the prescaler value. * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). * @note The prescaler can be changed on the fly as this control register is buffered. The new * prescaler ratio is taken into account at the next update event. * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter * @rmtoll PSC PSC LL_TIM_SetPrescaler * @param TIMx Timer instance * @param Prescaler between Min_Data=0 and Max_Data=65535 * @retval None */ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) { WRITE_REG(TIMx->PSC, Prescaler); } /** * @brief Get the prescaler value. * @rmtoll PSC PSC LL_TIM_GetPrescaler * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } /** * @brief Set the auto-reload value. * @note The counter is blocked while the auto-reload value is null. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter * @rmtoll ARR ARR LL_TIM_SetAutoReload * @param TIMx Timer instance * @param AutoReload between Min_Data=0 and Max_Data=65535 * @retval None */ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) { WRITE_REG(TIMx->ARR, AutoReload); } /** * @brief Get the auto-reload value. * @rmtoll ARR ARR LL_TIM_GetAutoReload * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @param TIMx Timer instance * @retval Auto-reload value */ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } /** * @brief Set the repetition counter value. * @note For advanced timer instances RepetitionCounter can be up to 65535 except for STM32F373xC and STM32F378xx devices. * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance * @param RepetitionCounter between Min_Data=0 and Max_Data=255 * @retval None */ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) { WRITE_REG(TIMx->RCR, RepetitionCounter); } /** * @brief Get the repetition counter value. * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_GetRepetitionCounter * @param TIMx Timer instance * @retval Repetition counter value */ __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } #if defined(TIM_CR1_UIFREMAP) /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) { SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); } /** * @brief Disable update interrupt flag (UIF) remapping. * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); } #endif /* TIM_CR1_UIFREMAP */ /** * @} */ /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration * @{ */ /** * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, * they are updated only when a commutation event (COM) occurs. * @note Only on channels that have a complementary output. * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) { SET_BIT(TIMx->CR2, TIM_CR2_CCPC); } /** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); } /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate * @param TIMx Timer instance * @param CCUpdateSource This parameter can be one of the following values: * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI * @retval None */ __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) { MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); } /** * @brief Set the trigger of the capture/compare DMA request. * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger * @param TIMx Timer instance * @param DMAReqTrigger This parameter can be one of the following values: * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE * @retval None */ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) { MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); } /** * @brief Get actual trigger of the capture/compare DMA request. * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger * @param TIMx Timer instance * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } /** * @brief Set the lock level to freeze the * configuration of several capture/compare parameters. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * the lock mechanism is supported by a timer instance. * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel * @param TIMx Timer instance * @param LockLevel This parameter can be one of the following values: * @arg @ref LL_TIM_LOCKLEVEL_OFF * @arg @ref LL_TIM_LOCKLEVEL_1 * @arg @ref LL_TIM_LOCKLEVEL_2 * @arg @ref LL_TIM_LOCKLEVEL_3 * @retval None */ __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) { MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); } /** * @brief Enable capture/compare channels. * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n * CCER CC1NE LL_TIM_CC_EnableChannel\n * CCER CC2E LL_TIM_CC_EnableChannel\n * CCER CC2NE LL_TIM_CC_EnableChannel\n * CCER CC3E LL_TIM_CC_EnableChannel\n * CCER CC3NE LL_TIM_CC_EnableChannel\n * CCER CC4E LL_TIM_CC_EnableChannel\n * CCER CC5E LL_TIM_CC_EnableChannel\n * CCER CC6E LL_TIM_CC_EnableChannel * @param TIMx Timer instance * @param Channels This parameter can be a combination of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) { SET_BIT(TIMx->CCER, Channels); } /** * @brief Disable capture/compare channels. * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n * CCER CC1NE LL_TIM_CC_DisableChannel\n * CCER CC2E LL_TIM_CC_DisableChannel\n * CCER CC2NE LL_TIM_CC_DisableChannel\n * CCER CC3E LL_TIM_CC_DisableChannel\n * CCER CC3NE LL_TIM_CC_DisableChannel\n * CCER CC4E LL_TIM_CC_DisableChannel\n * CCER CC5E LL_TIM_CC_DisableChannel\n * CCER CC6E LL_TIM_CC_DisableChannel * @param TIMx Timer instance * @param Channels This parameter can be a combination of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) { CLEAR_BIT(TIMx->CCER, Channels); } /** * @brief Indicate whether channel(s) is(are) enabled. * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n * CCER CC2E LL_TIM_CC_IsEnabledChannel\n * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n * CCER CC3E LL_TIM_CC_IsEnabledChannel\n * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n * CCER CC4E LL_TIM_CC_IsEnabledChannel\n * CCER CC5E LL_TIM_CC_IsEnabledChannel\n * CCER CC6E LL_TIM_CC_IsEnabledChannel * @param TIMx Timer instance * @param Channels This parameter can be a combination of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note CH5 and CH6 channels are not available for all F3 devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } /** * @} */ /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration * @{ */ /** * @brief Configure an output channel. * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n * @if STM32F334x8 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n * @elseif STM32F303xC * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n * @elseif STM32F302x8 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n * @endif * CCER CC1P LL_TIM_OC_ConfigOutput\n * CCER CC2P LL_TIM_OC_ConfigOutput\n * CCER CC3P LL_TIM_OC_ConfigOutput\n * CCER CC4P LL_TIM_OC_ConfigOutput\n * CCER CC5P LL_TIM_OC_ConfigOutput\n * CCER CC6P LL_TIM_OC_ConfigOutput\n * CR2 OIS1 LL_TIM_OC_ConfigOutput\n * CR2 OIS2 LL_TIM_OC_ConfigOutput\n * CR2 OIS3 LL_TIM_OC_ConfigOutput\n * CR2 OIS4 LL_TIM_OC_ConfigOutput\n * CR2 OIS5 LL_TIM_OC_ConfigOutput\n * CR2 OIS6 LL_TIM_OC_ConfigOutput * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @param Configuration This parameter must be a combination of all the following values: * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH * @note CH3 CH4 CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); } /** * @brief Define the behavior of the output reference signal OCxREF from which * OCx and OCxN (when relevant) are derived. * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n * CCMR1 OC2M LL_TIM_OC_SetMode\n * CCMR2 OC3M LL_TIM_OC_SetMode\n * CCMR2 OC4M LL_TIM_OC_SetMode\n * @if STM32F334x8 * CCMR3 OC5M LL_TIM_OC_SetMode\n * CCMR3 OC6M LL_TIM_OC_SetMode * @elseif STM32F303xC * CCMR3 OC5M LL_TIM_OC_SetMode\n * CCMR3 OC6M LL_TIM_OC_SetMode * @elseif STM32F302x8 * CCMR3 OC5M LL_TIM_OC_SetMode\n * CCMR3 OC6M LL_TIM_OC_SetMode * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @param Mode This parameter can be one of the following values: * @arg @ref LL_TIM_OCMODE_FROZEN * @arg @ref LL_TIM_OCMODE_ACTIVE * @arg @ref LL_TIM_OCMODE_INACTIVE * @arg @ref LL_TIM_OCMODE_TOGGLE * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE * @arg @ref LL_TIM_OCMODE_PWM1 * @arg @ref LL_TIM_OCMODE_PWM2 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 * @note The following OC modes are not available on all F3 devices : * - LL_TIM_OCMODE_RETRIG_OPM1 * - LL_TIM_OCMODE_RETRIG_OPM2 * - LL_TIM_OCMODE_COMBINED_PWM1 * - LL_TIM_OCMODE_COMBINED_PWM2 * - LL_TIM_OCMODE_ASSYMETRIC_PWM1 * - LL_TIM_OCMODE_ASSYMETRIC_PWM2 * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } /** * @brief Get the output compare mode of an output channel. * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n * CCMR1 OC2M LL_TIM_OC_GetMode\n * CCMR2 OC3M LL_TIM_OC_GetMode\n * CCMR2 OC4M LL_TIM_OC_GetMode\n * @if STM32F334x8 * CCMR3 OC5M LL_TIM_OC_GetMode\n * CCMR3 OC6M LL_TIM_OC_GetMode * @elseif STM32F303xC * CCMR3 OC5M LL_TIM_OC_GetMode\n * CCMR3 OC6M LL_TIM_OC_GetMode * @elseif STM32F302x8 * CCMR3 OC5M LL_TIM_OC_GetMode\n * CCMR3 OC6M LL_TIM_OC_GetMode * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note The following OC modes are not available on all F3 devices : * - LL_TIM_OCMODE_RETRIG_OPM1 * - LL_TIM_OCMODE_RETRIG_OPM2 * - LL_TIM_OCMODE_COMBINED_PWM1 * - LL_TIM_OCMODE_COMBINED_PWM2 * - LL_TIM_OCMODE_ASSYMETRIC_PWM1 * - LL_TIM_OCMODE_ASSYMETRIC_PWM2 * @note CH5 and CH6 channels are not available for all F3 devices * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_OCMODE_FROZEN * @arg @ref LL_TIM_OCMODE_ACTIVE * @arg @ref LL_TIM_OCMODE_INACTIVE * @arg @ref LL_TIM_OCMODE_TOGGLE * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE * @arg @ref LL_TIM_OCMODE_PWM1 * @arg @ref LL_TIM_OCMODE_PWM2 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } /** * @brief Set the polarity of an output channel. * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n * CCER CC1NP LL_TIM_OC_SetPolarity\n * CCER CC2P LL_TIM_OC_SetPolarity\n * CCER CC2NP LL_TIM_OC_SetPolarity\n * CCER CC3P LL_TIM_OC_SetPolarity\n * CCER CC3NP LL_TIM_OC_SetPolarity\n * CCER CC4P LL_TIM_OC_SetPolarity\n * CCER CC5P LL_TIM_OC_SetPolarity\n * CCER CC6P LL_TIM_OC_SetPolarity * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @param Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } /** * @brief Get the polarity of an output channel. * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n * CCER CC1NP LL_TIM_OC_GetPolarity\n * CCER CC2P LL_TIM_OC_GetPolarity\n * CCER CC2NP LL_TIM_OC_GetPolarity\n * CCER CC3P LL_TIM_OC_GetPolarity\n * CCER CC3NP LL_TIM_OC_GetPolarity\n * CCER CC4P LL_TIM_OC_GetPolarity\n * CCER CC5P LL_TIM_OC_GetPolarity\n * CCER CC6P LL_TIM_OC_GetPolarity * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note CH5 and CH6 channels are not available for all F3 devices * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } /** * @brief Set the IDLE state of an output channel * @note This function is significant only for the timer instances * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) * can be used to check whether or not a timer instance provides * a break input. * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n * CR2 OIS2N LL_TIM_OC_SetIdleState\n * CR2 OIS2 LL_TIM_OC_SetIdleState\n * CR2 OIS2N LL_TIM_OC_SetIdleState\n * CR2 OIS3 LL_TIM_OC_SetIdleState\n * CR2 OIS3N LL_TIM_OC_SetIdleState\n * CR2 OIS4 LL_TIM_OC_SetIdleState\n * CR2 OIS5 LL_TIM_OC_SetIdleState\n * CR2 OIS6 LL_TIM_OC_SetIdleState * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @param IdleState This parameter can be one of the following values: * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } /** * @brief Get the IDLE state of an output channel * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n * CR2 OIS2N LL_TIM_OC_GetIdleState\n * CR2 OIS2 LL_TIM_OC_GetIdleState\n * CR2 OIS2N LL_TIM_OC_GetIdleState\n * CR2 OIS3 LL_TIM_OC_GetIdleState\n * CR2 OIS3N LL_TIM_OC_GetIdleState\n * CR2 OIS4 LL_TIM_OC_GetIdleState\n * CR2 OIS5 LL_TIM_OC_GetIdleState\n * CR2 OIS6 LL_TIM_OC_GetIdleState * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH1N * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH2N * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH3N * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note CH5 and CH6 channels are not available for all F3 devices * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } /** * @brief Enable fast mode for the output channel. * @note Acts only if the channel is configured in PWM1 or PWM2 mode. * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n * CCMR1 OC2FE LL_TIM_OC_EnableFast\n * CCMR2 OC3FE LL_TIM_OC_EnableFast\n * CCMR2 OC4FE LL_TIM_OC_EnableFast\n * @if STM32F334x8 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n * CCMR3 OC6FE LL_TIM_OC_EnableFast * @elseif STM32F303xC * CCMR3 OC5FE LL_TIM_OC_EnableFast\n * CCMR3 OC6FE LL_TIM_OC_EnableFast * @elseif STM32F302x8 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n * CCMR3 OC6FE LL_TIM_OC_EnableFast * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5FE and OC6FE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } /** * @brief Disable fast mode for the output channel. * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n * CCMR1 OC2FE LL_TIM_OC_DisableFast\n * CCMR2 OC3FE LL_TIM_OC_DisableFast\n * CCMR2 OC4FE LL_TIM_OC_DisableFast\n * @if STM32F334x8 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n * CCMR3 OC6FE LL_TIM_OC_DisableFast * @elseif STM32F303xC * CCMR3 OC5FE LL_TIM_OC_DisableFast\n * CCMR3 OC6FE LL_TIM_OC_DisableFast * @elseif STM32F302x8 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n * CCMR3 OC6FE LL_TIM_OC_DisableFast * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5FE and OC6FE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } /** * @brief Indicates whether fast mode is enabled for the output channel. * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n * @if STM32F334x8 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast * @elseif STM32F303xC * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast * @elseif STM32F302x8 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n * CCMR3 OC6FE LL_TIM_OC_DisableFast * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5FE and OC6FE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** * @brief Enable compare register (TIMx_CCRx) preload for the output channel. * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n * @if STM32F334x8 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n * CCMR3 OC6PE LL_TIM_OC_EnablePreload * @elseif STM32F303xC * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n * CCMR3 OC6PE LL_TIM_OC_EnablePreload * @elseif STM32F302x8 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n * CCMR3 OC6PE LL_TIM_OC_EnablePreload * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5PE and OC6PE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } /** * @brief Disable compare register (TIMx_CCRx) preload for the output channel. * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n * @if STM32F334x8 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n * CCMR3 OC6PE LL_TIM_OC_DisablePreload * @elseif STM32F303xC * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n * CCMR3 OC6PE LL_TIM_OC_DisablePreload * @elseif STM32F302x8 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n * CCMR3 OC6PE LL_TIM_OC_DisablePreload * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5PE and OC6PE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } /** * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n * @if STM32F334x8 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload * @elseif STM32F303xC * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload * @elseif STM32F302x8 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5PE and OC6PE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** * @brief Enable clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n * CCMR1 OC2CE LL_TIM_OC_EnableClear\n * CCMR2 OC3CE LL_TIM_OC_EnableClear\n * CCMR2 OC4CE LL_TIM_OC_EnableClear\n * @if STM32F334x8 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n * CCMR3 OC6CE LL_TIM_OC_EnableClear * @elseif STM32F303xC * CCMR3 OC5CE LL_TIM_OC_EnableClear\n * CCMR3 OC6CE LL_TIM_OC_EnableClear * @elseif STM32F302x8 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n * CCMR3 OC6CE LL_TIM_OC_EnableClear * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5CE and OC6CE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } /** * @brief Disable clearing the output channel on an external event. * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n * CCMR1 OC2CE LL_TIM_OC_DisableClear\n * CCMR2 OC3CE LL_TIM_OC_DisableClear\n * CCMR2 OC4CE LL_TIM_OC_DisableClear\n * @if STM32F334x8 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n * CCMR3 OC6CE LL_TIM_OC_DisableClear * @elseif STM32F303xC * CCMR3 OC5CE LL_TIM_OC_DisableClear\n * CCMR3 OC6CE LL_TIM_OC_DisableClear * @elseif STM32F302x8 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n * CCMR3 OC6CE LL_TIM_OC_DisableClear * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5CE and OC6CE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } /** * @brief Indicates clearing the output channel on an external event is enabled for the output channel. * @note This function enables clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n * @if STM32F334x8 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear * @elseif STM32F303xC * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear * @elseif STM32F302x8 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear * @endif * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @note OC5CE and OC6CE are not available for all F3 devices * @note CH5 and CH6 channels are not available for all F3 devices * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } /** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime * @param TIMx Timer instance * @param DeadTime between Min_Data=0 and Max_Data=255 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) { MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); } /** * @brief Set compare value for output channel 1 (TIMx_CCR1). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 * @param TIMx Timer instance * @param CompareValue between Min_Data=0 and Max_Data=65535 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) { WRITE_REG(TIMx->CCR1, CompareValue); } /** * @brief Set compare value for output channel 2 (TIMx_CCR2). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 * @param TIMx Timer instance * @param CompareValue between Min_Data=0 and Max_Data=65535 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) { WRITE_REG(TIMx->CCR2, CompareValue); } /** * @brief Set compare value for output channel 3 (TIMx_CCR3). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 * @param TIMx Timer instance * @param CompareValue between Min_Data=0 and Max_Data=65535 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) { WRITE_REG(TIMx->CCR3, CompareValue); } /** * @brief Set compare value for output channel 4 (TIMx_CCR4). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 * @param TIMx Timer instance * @param CompareValue between Min_Data=0 and Max_Data=65535 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) { WRITE_REG(TIMx->CCR4, CompareValue); } #if defined(TIM_CCR5_CCR5) /** * @brief Set compare value for output channel 5 (TIMx_CCR5). * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @if STM32F334x8 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 * @elseif STM32F303xC * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 * @elseif STM32F302x8 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 * @endif * @param TIMx Timer instance * @param CompareValue between Min_Data=0 and Max_Data=65535 * @note CH5 channel is not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) { MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); } #endif /* TIM_CCR5_CCR5 */ #if defined(TIM_CCR6_CCR6) /** * @brief Set compare value for output channel 6 (TIMx_CCR6). * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @if STM32F344x8 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 * @elseif STM32F303xC * CCR6 CCR6 LL_TIM_OC_SetCompareCH6 * @elseif STM32F302x8 * CCR6 CCR6 LL_TIM_OC_SetCompareCH6 * @endif * @param TIMx Timer instance * @param CompareValue between Min_Data=0 and Max_Data=65535 * @note CH6 channel is not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) { WRITE_REG(TIMx->CCR6, CompareValue); } #endif /* TIM_CCR6_CCR6 */ /** * @brief Get compare value (TIMx_CCR1) set for output channel 1. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } /** * @brief Get compare value (TIMx_CCR2) set for output channel 2. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } /** * @brief Get compare value (TIMx_CCR3) set for output channel 3. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } /** * @brief Get compare value (TIMx_CCR4) set for output channel 4. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } #if defined(TIM_CCR5_CCR5) /** * @brief Get compare value (TIMx_CCR5) set for output channel 5. * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @if STM32F334x8 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 * @elseif STM32F303xC * CCR5 CCR5 LL_TIM_OC_GetCompareCH5 * @elseif STM32F302x8 * CCR5 CCR5 LL_TIM_OC_GetCompareCH5 * @endif * @param TIMx Timer instance * @note CH5 channel is not available for all F3 devices * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } #endif /* TIM_CCR5_CCR5 */ #if defined(TIM_CCR6_CCR6) /** * @brief Get compare value (TIMx_CCR6) set for output channel 6. * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @if STM32F334x8 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 * @elseif STM32F303xC * CCR6 CCR6 LL_TIM_OC_GetCompareCH6 * @elseif STM32F302x8 * CCR6 CCR6 LL_TIM_OC_GetCompareCH6 * @endif * @param TIMx Timer instance * @note CH6 channel is not available for all F3 devices * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR6)); } #endif /* TIM_CCR6_CCR6 */ #if defined(TIM_CCR5_CCR5) /** * @brief Select on which reference signal the OC5REF is combined to. * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the combined 3-phase PWM mode. * @if STM32F334x8 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels * @elseif STM32F303xC * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels * @elseif STM32F302x8 * CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels * @endif * @param TIMx Timer instance * @param GroupCH5 This parameter can be a combination of the following values: * @arg @ref LL_TIM_GROUPCH5_NONE * @arg @ref LL_TIM_GROUPCH5_OC1REFC * @arg @ref LL_TIM_GROUPCH5_OC2REFC * @arg @ref LL_TIM_GROUPCH5_OC3REFC * @note CH5 channel is not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) { MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); } #endif /* TIM_CCR5_CCR5 */ /** * @} */ /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration * @{ */ /** * @brief Configure input channel. * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n * CCMR1 IC1PSC LL_TIM_IC_Config\n * CCMR1 IC1F LL_TIM_IC_Config\n * CCMR1 CC2S LL_TIM_IC_Config\n * CCMR1 IC2PSC LL_TIM_IC_Config\n * CCMR1 IC2F LL_TIM_IC_Config\n * CCMR2 CC3S LL_TIM_IC_Config\n * CCMR2 IC3PSC LL_TIM_IC_Config\n * CCMR2 IC3F LL_TIM_IC_Config\n * CCMR2 CC4S LL_TIM_IC_Config\n * CCMR2 IC4PSC LL_TIM_IC_Config\n * CCMR2 IC4F LL_TIM_IC_Config\n * CCER CC1P LL_TIM_IC_Config\n * CCER CC1NP LL_TIM_IC_Config\n * CCER CC2P LL_TIM_IC_Config\n * CCER CC2NP LL_TIM_IC_Config\n * CCER CC3P LL_TIM_IC_Config\n * CCER CC3NP LL_TIM_IC_Config\n * CCER CC4P LL_TIM_IC_Config\n * CCER CC4NP LL_TIM_IC_Config * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @param Configuration This parameter must be a combination of all the following values: * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE * @retval None */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); } /** * @brief Set the active input. * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n * CCMR2 CC4S LL_TIM_IC_SetActiveInput * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @param ICActiveInput This parameter can be one of the following values: * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC * @retval None */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } /** * @brief Get the current active input. * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n * CCMR2 CC4S LL_TIM_IC_GetActiveInput * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } /** * @brief Set the prescaler of input channel. * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @param ICPrescaler This parameter can be one of the following values: * @arg @ref LL_TIM_ICPSC_DIV1 * @arg @ref LL_TIM_ICPSC_DIV2 * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 * @retval None */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } /** * @brief Get the current prescaler value acting on an input channel. * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_ICPSC_DIV1 * @arg @ref LL_TIM_ICPSC_DIV2 * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } /** * @brief Set the input filter duration. * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n * CCMR1 IC2F LL_TIM_IC_SetFilter\n * CCMR2 IC3F LL_TIM_IC_SetFilter\n * CCMR2 IC4F LL_TIM_IC_SetFilter * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @param ICFilter This parameter can be one of the following values: * @arg @ref LL_TIM_IC_FILTER_FDIV1 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 * @retval None */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } /** * @brief Get the input filter duration. * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n * CCMR1 IC2F LL_TIM_IC_GetFilter\n * CCMR2 IC3F LL_TIM_IC_GetFilter\n * CCMR2 IC4F LL_TIM_IC_GetFilter * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_IC_FILTER_FDIV1 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } /** * @brief Set the input channel polarity. * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n * CCER CC1NP LL_TIM_IC_SetPolarity\n * CCER CC2P LL_TIM_IC_SetPolarity\n * CCER CC2NP LL_TIM_IC_SetPolarity\n * CCER CC3P LL_TIM_IC_SetPolarity\n * CCER CC3NP LL_TIM_IC_SetPolarity\n * CCER CC4P LL_TIM_IC_SetPolarity\n * CCER CC4NP LL_TIM_IC_SetPolarity * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @param ICPolarity This parameter can be one of the following values: * @arg @ref LL_TIM_IC_POLARITY_RISING * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE * @retval None */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } /** * @brief Get the current input channel polarity. * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n * CCER CC1NP LL_TIM_IC_GetPolarity\n * CCER CC2P LL_TIM_IC_GetPolarity\n * CCER CC2NP LL_TIM_IC_GetPolarity\n * CCER CC3P LL_TIM_IC_GetPolarity\n * CCER CC3NP LL_TIM_IC_GetPolarity\n * CCER CC4P LL_TIM_IC_GetPolarity\n * CCER CC4NP LL_TIM_IC_GetPolarity * @param TIMx Timer instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @retval Returned value can be one of the following values: * @arg @ref LL_TIM_IC_POLARITY_RISING * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } /** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) { SET_BIT(TIMx->CR2, TIM_CR2_TI1S); } /** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); } /** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } /** * @brief Get captured value for input channel 1. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * input channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } /** * @brief Get captured value for input channel 2. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * input channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } /** * @brief Get captured value for input channel 3. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * input channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } /** * @brief Get captured value for input channel 4. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * input channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } /** * @} */ /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection * @{ */ /** * @brief Enable external clock mode 2. * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_EnableExternalClock * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) { SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); } /** * @brief Disable external clock mode 2. * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_DisableExternalClock * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); } /** * @brief Indicate whether external clock mode 2 is enabled. * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } /** * @brief Set the clock source of the counter clock. * @note when selected clock source is external clock mode 1, the timer input * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() * function. This timer input must be configured by calling * the @ref LL_TIM_IC_Config() function. * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode1. * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR SMS LL_TIM_SetClockSource\n * SMCR ECE LL_TIM_SetClockSource * @param TIMx Timer instance * @param ClockSource This parameter can be one of the following values: * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 * @retval None */ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) { MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); } /** * @brief Set the encoder interface mode. * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the encoder mode. * @rmtoll SMCR SMS LL_TIM_SetEncoderMode * @param TIMx Timer instance * @param EncoderMode This parameter can be one of the following values: * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 * @retval None */ __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) { MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); } /** * @} */ /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration * @{ */ /** * @brief Set the trigger output (TRGO) used for timer synchronization . * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance can operate as a master timer. * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput * @param TIMx Timer instance * @param TimerSynchronization This parameter can be one of the following values: * @arg @ref LL_TIM_TRGO_RESET * @arg @ref LL_TIM_TRGO_ENABLE * @arg @ref LL_TIM_TRGO_UPDATE * @arg @ref LL_TIM_TRGO_CC1IF * @arg @ref LL_TIM_TRGO_OC1REF * @arg @ref LL_TIM_TRGO_OC2REF * @arg @ref LL_TIM_TRGO_OC3REF * @arg @ref LL_TIM_TRGO_OC4REF * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) { MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); } #if defined(TIM_CR2_MMS2) /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check * whether or not a timer instance can be used for ADC synchronization. * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 * @param TIMx Timer Instance * @param ADCSynchronization This parameter can be one of the following values: * @arg @ref LL_TIM_TRGO2_RESET * @arg @ref LL_TIM_TRGO2_ENABLE * @arg @ref LL_TIM_TRGO2_UPDATE * @arg @ref LL_TIM_TRGO2_CC1F * @arg @ref LL_TIM_TRGO2_OC1 * @arg @ref LL_TIM_TRGO2_OC2 * @arg @ref LL_TIM_TRGO2_OC3 * @arg @ref LL_TIM_TRGO2_OC4 * @arg @ref LL_TIM_TRGO2_OC5 * @arg @ref LL_TIM_TRGO2_OC6 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING * @note OC5 and OC6 are not available for all F3 devices * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) { MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); } #endif /* TIM_CR2_MMS2 */ /** * @brief Set the synchronization mode of a slave timer. * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR SMS LL_TIM_SetSlaveMode * @param TIMx Timer instance * @param SlaveMode This parameter can be one of the following values: * @arg @ref LL_TIM_SLAVEMODE_DISABLED * @arg @ref LL_TIM_SLAVEMODE_RESET * @arg @ref LL_TIM_SLAVEMODE_GATED * @arg @ref LL_TIM_SLAVEMODE_TRIGGER * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER * @retval None */ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) { MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); } /** * @brief Set the selects the trigger input to be used to synchronize the counter. * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR TS LL_TIM_SetTriggerInput * @param TIMx Timer instance * @param TriggerInput This parameter can be one of the following values: * @arg @ref LL_TIM_TS_ITR0 * @arg @ref LL_TIM_TS_ITR1 * @arg @ref LL_TIM_TS_ITR2 * @arg @ref LL_TIM_TS_ITR3 * @arg @ref LL_TIM_TS_TI1F_ED * @arg @ref LL_TIM_TS_TI1FP1 * @arg @ref LL_TIM_TS_TI2FP2 * @arg @ref LL_TIM_TS_ETRF * @retval None */ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) { MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); } /** * @brief Enable the Master/Slave mode. * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) { SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); } /** * @brief Disable the Master/Slave mode. * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); } /** * @brief Indicates whether the Master/Slave mode is enabled. * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } /** * @brief Configure the external trigger (ETR) input. * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an external trigger input. * @rmtoll SMCR ETP LL_TIM_ConfigETR\n * SMCR ETPS LL_TIM_ConfigETR\n * SMCR ETF LL_TIM_ConfigETR * @param TIMx Timer instance * @param ETRPolarity This parameter can be one of the following values: * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED * @arg @ref LL_TIM_ETR_POLARITY_INVERTED * @param ETRPrescaler This parameter can be one of the following values: * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 * @param ETRFilter This parameter can be one of the following values: * @arg @ref LL_TIM_ETR_FILTER_FDIV1 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 * @retval None */ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter) { MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); } /** * @} */ /** @defgroup TIM_LL_EF_Break_Function Break function configuration * @{ */ /** * @brief Enable the break function. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKE LL_TIM_EnableBRK * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) { #if defined(TIM_IP_V2_1) __IO uint32_t tmpreg; #endif /* TIM_IP_V2_1 */ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); #if defined(TIM_IP_V2_1) /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ tmpreg = READ_REG(TIMx->BDTR); (void)(tmpreg); #endif /* TIM_IP_V2_1 */ } /** * @brief Disable the break function. * @rmtoll BDTR BKE LL_TIM_DisableBRK * @param TIMx Timer instance * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @retval None */ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) { #if defined(TIM_IP_V2_1) __IO uint32_t tmpreg; #endif /* TIM_IP_V2_1 */ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); #if defined(TIM_IP_V2_1) /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ tmpreg = READ_REG(TIMx->BDTR); (void)(tmpreg); #endif /* TIM_IP_V2_1 */ } #if defined(TIM_BDTR_BKF) /** * @brief Configure the break input. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n * BDTR BKF LL_TIM_ConfigBRK * @param TIMx Timer instance * @param BreakPolarity This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_POLARITY_LOW * @arg @ref LL_TIM_BREAK_POLARITY_HIGH * @param BreakFilter This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 * @retval None */ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) { #if defined(TIM_IP_V2_1) __IO uint32_t tmpreg; #endif /* TIM_IP_V2_1 */ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); #if defined(TIM_IP_V2_1) /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ tmpreg = READ_REG(TIMx->BDTR); (void)(tmpreg); #endif /* TIM_IP_V2_1 */ } #else /** * @brief Configure the break input. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKP LL_TIM_ConfigBRK * @param TIMx Timer instance * @param BreakPolarity This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK_POLARITY_LOW * @arg @ref LL_TIM_BREAK_POLARITY_HIGH * @retval None */ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) { #if defined(TIM_IP_V2_1) __IO uint32_t tmpreg; #endif /* TIM_IP_V2_1 */ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); #if defined(TIM_IP_V2_1) /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ tmpreg = READ_REG(TIMx->BDTR); (void)(tmpreg); #endif /* TIM_IP_V2_1 */ } #endif /* TIM_BDTR_BKF */ #if defined(TIM_BDTR_BK2E) /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) { #if defined(TIM_IP_V2_1) __IO uint32_t tmpreg; #endif /* TIM_IP_V2_1 */ SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); #if defined(TIM_IP_V2_1) /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ tmpreg = READ_REG(TIMx->BDTR); (void)(tmpreg); #endif /* TIM_IP_V2_1 */ } /** * @brief Disable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) { #if defined(TIM_IP_V2_1) __IO uint32_t tmpreg; #endif /* TIM_IP_V2_1 */ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); #if defined(TIM_IP_V2_1) /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ tmpreg = READ_REG(TIMx->BDTR); (void)(tmpreg); #endif /* TIM_IP_V2_1 */ } /** * @brief Configure the break 2 input. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n * BDTR BK2F LL_TIM_ConfigBRK2 * @param TIMx Timer instance * @param Break2Polarity This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK2_POLARITY_LOW * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH * @param Break2Filter This parameter can be one of the following values: * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 * @retval None */ __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) { MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); } #endif /* TIM_BDTR_BK2E */ /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n * BDTR OSSR LL_TIM_SetOffStates * @param TIMx Timer instance * @param OffStateIdle This parameter can be one of the following values: * @arg @ref LL_TIM_OSSI_DISABLE * @arg @ref LL_TIM_OSSI_ENABLE * @param OffStateRun This parameter can be one of the following values: * @arg @ref LL_TIM_OSSR_DISABLE * @arg @ref LL_TIM_OSSR_ENABLE * @retval None */ __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) { MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); } /** * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) { SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); } /** * @brief Disable automatic output (MOE can be set only by software). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); } /** * @brief Indicate whether automatic output is enabled. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } /** * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) { SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); } /** * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); } /** * @brief Indicates whether outputs are enabled. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } /** * @} */ /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration * @{ */ /** * @brief Configures the timer DMA burst feature. * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports the DMA burst mode. * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n * DCR DBA LL_TIM_ConfigDMABurst * @param TIMx Timer instance * @param DMABurstBaseAddress This parameter can be one of the following values: * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER * @arg @ref LL_TIM_DMABURST_BASEADDR_SR * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR * @arg @ref LL_TIM_DMABURST_BASEADDR_OR * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 (*) * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 (*) * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 (*) * (*) value not defined in all devices * @param DMABurstLength This parameter can be one of the following values: * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS * @retval None */ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) { MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); } /** * @} */ /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping * @{ */ /** * @brief Remap TIM inputs (input channel, internal/external triggers). * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not * a some timer inputs can be remapped. * @if STM32F334x8 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n * TIM16_OR TI1_RMP LL_TIM_SetRemap\n * @elseif STM32F302x8 * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n * TIM16_OR TI1_RMP LL_TIM_SetRemap\n * @elseif STM32F303xC * @rmtoll TIM1_OR ETR_RMP LL_TIM_SetRemap\n * TIM8_OR ETR_RMP LL_TIM_SetRemap\n * TIM20_OR ETR_RMP LL_TIM_SetRemap\n * @elseif STM32F373xC * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap * @endif * @param TIMx Timer instance * @param Remap Remap params depends on the TIMx. Description available only * in CHM version of the User Manual (not in .pdf). * Otherwise see Reference Manual description of OR registers. * * Below description summarizes "Timer Instance" and "Remap" param combinations: * * TIM1: any combination of ETR_RMP where (**) * * . . ETR_RMP can be one of the following values * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_NC (*) * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD1 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD2 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC2_RMP_AWD3 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC (*) * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (*) * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (*) * * TIM8: any combination of ETR_RMP where (**) * * . . ETR_RMP can be one of the following values * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC (*) * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (*) * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (*) * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (*) * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC (*) * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (*) * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (*) * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (*) * * TIM14: any combination of TI1_RMP where (**) * * . . TI1_RMP can be one of the following values * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO (*) * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK (*) * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE (*) * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO (*) * * TIM16: any combination of TI1_RMP where (**) * * . . TI1_RMP can be one of the following values * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO (*) * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI (*) * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE (*) * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC (*) * * TIM20: any combination of ETR_RMP where (**) * * . . ETR_RMP can be one of the following values * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_NC (*) * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD1 (*) * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD2 (*) * @arg @ref LL_TIM_TIM20_ETR_ADC3_RMP_AWD3 (*) * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_NC (*) * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD1 (*) * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD2 (*) * @arg @ref LL_TIM_TIM20_ETR_ADC4_RMP_AWD3 (*) * * (*) Value not defined in all devices. \n * (**) Register not available in all devices. * @retval None */ __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) { MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); } /** * @} */ #if defined(TIM_SMCR_OCCS) /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management * @{ */ /** * @brief Set the OCREF clear input source * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT * @note This function can only be used in Output compare and PWM modes. * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource * @param TIMx Timer instance * @param OCRefClearInputSource This parameter can be one of the following values: * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR * @arg @ref LL_TIM_OCREF_CLR_INT_ETR * @retval None */ __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) { MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); } /** * @} */ #endif /* TIM_SMCR_OCCS */ /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management * @{ */ /** * @brief Clear the update interrupt flag (UIF). * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); } /** * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } /** * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); } /** * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } /** * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); } /** * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } /** * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); } /** * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } /** * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); } /** * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } #if defined (TIM_SR_CC5IF) /** * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); } /** * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } #endif /* TIM_SR_CC5IF */ #if defined (TIM_SR_CC6IF) /** * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); } /** * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } #endif /* TIM_SR_CC6IF */ /** * @brief Clear the commutation interrupt flag (COMIF). * @rmtoll SR COMIF LL_TIM_ClearFlag_COM * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); } /** * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } /** * @brief Clear the trigger interrupt flag (TIF). * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); } /** * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } /** * @brief Clear the break interrupt flag (BIF). * @rmtoll SR BIF LL_TIM_ClearFlag_BRK * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); } /** * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } #if defined(TIM_SR_B2IF) /** * @brief Clear the break 2 interrupt flag (B2IF). * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); } /** * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } #endif /* TIM_SR_B2IF */ /** * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); } /** * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } /** * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); } /** * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } /** * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); } /** * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } /** * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) { WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); } /** * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } /** * @} */ /** @defgroup TIM_LL_EF_IT_Management IT-Management * @{ */ /** * @brief Enable update interrupt (UIE). * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_UIE); } /** * @brief Disable update interrupt (UIE). * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); } /** * @brief Indicates whether the update interrupt (UIE) is enabled. * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 1 interrupt (CC1IE). * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); } /** * @brief Disable capture/compare 1 interrupt (CC1IE). * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); } /** * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 2 interrupt (CC2IE). * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); } /** * @brief Disable capture/compare 2 interrupt (CC2IE). * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); } /** * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 3 interrupt (CC3IE). * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); } /** * @brief Disable capture/compare 3 interrupt (CC3IE). * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); } /** * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 4 interrupt (CC4IE). * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); } /** * @brief Disable capture/compare 4 interrupt (CC4IE). * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); } /** * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } /** * @brief Enable commutation interrupt (COMIE). * @rmtoll DIER COMIE LL_TIM_EnableIT_COM * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_COMIE); } /** * @brief Disable commutation interrupt (COMIE). * @rmtoll DIER COMIE LL_TIM_DisableIT_COM * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); } /** * @brief Indicates whether the commutation interrupt (COMIE) is enabled. * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } /** * @brief Enable trigger interrupt (TIE). * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_TIE); } /** * @brief Disable trigger interrupt (TIE). * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); } /** * @brief Indicates whether the trigger interrupt (TIE) is enabled. * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } /** * @brief Enable break interrupt (BIE). * @rmtoll DIER BIE LL_TIM_EnableIT_BRK * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_BIE); } /** * @brief Disable break interrupt (BIE). * @rmtoll DIER BIE LL_TIM_DisableIT_BRK * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); } /** * @brief Indicates whether the break interrupt (BIE) is enabled. * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } /** * @} */ /** @defgroup TIM_LL_EF_DMA_Management DMA-Management * @{ */ /** * @brief Enable update DMA request (UDE). * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_UDE); } /** * @brief Disable update DMA request (UDE). * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); } /** * @brief Indicates whether the update DMA request (UDE) is enabled. * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 1 DMA request (CC1DE). * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); } /** * @brief Disable capture/compare 1 DMA request (CC1DE). * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); } /** * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 2 DMA request (CC2DE). * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); } /** * @brief Disable capture/compare 2 DMA request (CC2DE). * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); } /** * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 3 DMA request (CC3DE). * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); } /** * @brief Disable capture/compare 3 DMA request (CC3DE). * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); } /** * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } /** * @brief Enable capture/compare 4 DMA request (CC4DE). * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); } /** * @brief Disable capture/compare 4 DMA request (CC4DE). * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); } /** * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } /** * @brief Enable commutation DMA request (COMDE). * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_COMDE); } /** * @brief Disable commutation DMA request (COMDE). * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); } /** * @brief Indicates whether the commutation DMA request (COMDE) is enabled. * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } /** * @brief Enable trigger interrupt (TDE). * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) { SET_BIT(TIMx->DIER, TIM_DIER_TDE); } /** * @brief Disable trigger interrupt (TDE). * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) { CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); } /** * @brief Indicates whether the trigger interrupt (TDE) is enabled. * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG * @param TIMx Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } /** * @} */ /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management * @{ */ /** * @brief Generate an update event. * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_UG); } /** * @brief Generate Capture/Compare 1 event. * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_CC1G); } /** * @brief Generate Capture/Compare 2 event. * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_CC2G); } /** * @brief Generate Capture/Compare 3 event. * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_CC3G); } /** * @brief Generate Capture/Compare 4 event. * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_CC4G); } /** * @brief Generate commutation event. * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_COMG); } /** * @brief Generate trigger event. * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_TG); } /** * @brief Generate break event. * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_BG); } #if defined(TIM_EGR_B2G) /** * @brief Generate break 2 event. * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 * @param TIMx Timer instance * @retval None */ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) { SET_BIT(TIMx->EGR, TIM_EGR_B2G); } #endif /* TIM_EGR_B2G */ /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions * @{ */ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_utils.h * @author MCD Application Team * @brief Header file of UTILS LL module. @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The LL UTILS driver contains a set of generic APIs that can be used by user: (+) Device electronic signature (+) Timing functions (+) PLL configuration functions @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F3xx_LL_UTILS_H #define __STM32F3xx_LL_UTILS_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" /** @addtogroup STM32F3xx_LL_Driver * @{ */ /** @defgroup UTILS_LL UTILS * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants * @{ */ /* Max delay can be used in LL_mDelay */ #define LL_MAX_DELAY 0xFFFFFFFFU /** * @brief Unique device ID register base address */ #define UID_BASE_ADDRESS UID_BASE /** * @brief Flash size data register base address */ #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE /** * @brief Package data register base address */ #define PACKAGE_BASE_ADDRESS PACKAGE_BASE /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros * @{ */ /** * @} */ /* Exported types ------------------------------------------------------------*/ /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures * @{ */ /** * @brief UTILS PLL structure definition */ typedef struct { uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. This parameter can be a value of @ref RCC_LL_EC_PLL_MUL This feature can be modified afterwards using unitary function @ref LL_RCC_PLL_ConfigDomain_SYS(). */ #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV This feature can be modified afterwards using unitary function @ref LL_RCC_PLL_ConfigDomain_SYS(). */ #else uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV This feature can be modified afterwards using unitary function @ref LL_RCC_PLL_ConfigDomain_SYS(). */ #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ } LL_UTILS_PLLInitTypeDef; /** * @brief UTILS System, AHB and APB buses clock configuration structure definition */ typedef struct { uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV This feature can be modified afterwards using unitary function @ref LL_RCC_SetAHBPrescaler(). */ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_LL_EC_APB1_DIV This feature can be modified afterwards using unitary function @ref LL_RCC_SetAPB1Prescaler(). */ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_LL_EC_APB2_DIV This feature can be modified afterwards using unitary function @ref LL_RCC_SetAPB2Prescaler(). */ } LL_UTILS_ClkInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants * @{ */ /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation * @{ */ #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions * @{ */ /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE * @{ */ /** * @brief Get Word0 of the unique device identifier (UID based on 96 bits) * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format */ __STATIC_INLINE uint32_t LL_GetUID_Word0(void) { return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); } /** * @brief Get Word1 of the unique device identifier (UID based on 96 bits) * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) */ __STATIC_INLINE uint32_t LL_GetUID_Word1(void) { return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); } /** * @brief Get Word2 of the unique device identifier (UID based on 96 bits) * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] */ __STATIC_INLINE uint32_t LL_GetUID_Word2(void) { return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); } /** * @brief Get Flash memory size * @note This bitfield indicates the size of the device Flash memory expressed in * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. * @retval FLASH_SIZE[15:0]: Flash memory size */ __STATIC_INLINE uint32_t LL_GetFlashSize(void) { return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); } /** * @} */ /** @defgroup UTILS_LL_EF_DELAY DELAY * @{ */ /** * @brief This function configures the Cortex-M SysTick source of the time base. * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param Ticks Number of ticks * @retval None */ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) { /* Configure the SysTick to have interrupt in 1ms time base */ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ } void LL_Init1msTick(uint32_t HCLKFrequency); void LL_mDelay(uint32_t Delay); /** * @} */ /** @defgroup UTILS_EF_SYSTEM SYSTEM * @{ */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32F3xx_LL_UTILS_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal.c * @author MCD Application Team * @brief HAL module driver. * This is the common part of the HAL initialization * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be used by the PPP peripheral drivers and the user to start using the HAL. [..] The HAL contains two APIs categories: (+) HAL Initialization and de-initialization functions (+) HAL Control functions @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup HAL HAL * @brief HAL module driver. * @{ */ #ifdef HAL_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup HAL_Private Constants * @{ */ /** * @brief STM32F3xx HAL Driver version number V1.5.3 */ #define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32F3xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\ |(__STM32F3xx_HAL_VERSION_RC)) #define IDCODE_DEVID_MASK (0x00000FFFU) /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Exported variables --------------------------------------------------------*/ /** @defgroup HAL_Exported_Variables HAL Exported Variables * @{ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions * @{ */ /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface, the NVIC allocation and initial clock configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. (+) de-Initializes common part of the HAL. (+) Configure The time base source to have 1ms time base with a dedicated Tick interrupt priority. (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. (++) Time base configuration function (HAL_InitTick ()) is called automatically at the beginning of the program after reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). (++) Source of time base is configured to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. (++) functions affecting time base configurations are declared as __Weak to make override possible in case of other implementations in user file. @endverbatim * @{ */ /** * @brief This function configures the Flash prefetch, * Configures time base source, NVIC and Low level hardware * @note This function is called at the beginning of program after reset and before * the clock configuration * * @note The Systick configuration is based on HSI clock, as HSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4 * * @note The time base configuration is based on MSI clock when exting from Reset. * Once done, time base tick start incrementing. * In the default implementation,Systick is used as source of time base. * The tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { /* Configure Flash prefetch */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); /* Init the low level hardware */ HAL_MspInit(); /* Return function status */ return HAL_OK; } /** * @brief This function de-Initializes common part of the HAL and stops the systick. * @note This function is optional. * @retval HAL status */ HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ __HAL_RCC_APB1_FORCE_RESET(); __HAL_RCC_APB1_RELEASE_RESET(); __HAL_RCC_APB2_FORCE_RESET(); __HAL_RCC_APB2_RELEASE_RESET(); __HAL_RCC_AHB_FORCE_RESET(); __HAL_RCC_AHB_RELEASE_RESET(); /* De-Init the low level hardware */ HAL_MspDeInit(); /* Return function status */ return HAL_OK; } /** * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } /** * @brief DeInitialize the MSP. * @retval None */ __weak void HAL_MspDeInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } /** * @brief This function configures the source of the time base. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __Weak to be overwritten in case of other * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) { return HAL_ERROR; } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); uwTickPrio = TickPriority; } else { return HAL_ERROR; } /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim =============================================================================== ##### HAL Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Provide a tick value in millisecond (+) Provide a blocking delay in millisecond (+) Suspend the time base source interrupt (+) Resume the time base source interrupt (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier (+) Enable/Disable Debug module during Sleep mode (+) Enable/Disable Debug module during STOP mode (+) Enable/Disable Debug module during STANDBY mode @endverbatim * @{ */ /** * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; } /** * @brief Povides a tick value in millisecond. * @note The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; } /** * @brief This function returns a tick priority. * @retval tick priority */ uint32_t HAL_GetTickPrio(void) { return uwTickPrio; } /** * @brief Set new tick Freq. * @retval status */ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; HAL_TickFreqTypeDef prevTickFreq; assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { /* Back up uwTickFreq frequency */ prevTickFreq = uwTickFreq; /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); if (status != HAL_OK) { /* Restore previous tick frequency */ uwTickFreq = prevTickFreq; } } return status; } /** * @brief Return tick frequency. * @retval tick period in Hz */ HAL_TickFreqTypeDef HAL_GetTickFreq(void) { return uwTickFreq; } /** * @brief This function provides accurate delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. * The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; /* Add freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { wait += (uint32_t)(uwTickFreq); } while((HAL_GetTick() - tickstart) < wait) { } } /** * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() * is called, the the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_SuspendTick(void) { /* Disable SysTick Interrupt */ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; } /** * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() * is called, the the SysTick interrupt will be enabled and so Tick increment * is resumed. * The function is declared as __Weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_ResumeTick(void) { /* Enable SysTick Interrupt */ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; } /** * @brief This function returns the HAL revision * @retval version 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) { return __STM32F3xx_HAL_VERSION; } /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { return((DBGMCU->IDCODE) >> 16U); } /** * @brief Returns the device identifier. * @retval Device identifier */ uint32_t HAL_GetDEVID(void) { return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } /** * @brief Returns first word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw0(void) { return(READ_REG(*((uint32_t *)UID_BASE))); } /** * @brief Returns second word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw1(void) { return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); } /** * @brief Returns third word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw2(void) { return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** * @brief Enable the Debug Module during SLEEP mode * @retval None */ void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Disable the Debug Module during SLEEP mode * @retval None */ void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Enable the Debug Module during STOP mode * @retval None */ void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Disable the Debug Module during STOP mode * @retval None */ void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Enable the Debug Module during STANDBY mode * @retval None */ void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Disable the Debug Module during STANDBY mode * @retval None */ void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @} */ /** * @} */ #endif /* HAL_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC * + Operation functions * ++ Start, stop, get result of conversions of regular * group, using 3 possible modes: polling, interruption or DMA. * + Control functions * ++ Channels configuration on regular group * ++ Channels configuration on injected group * ++ Analog Watchdog configuration * + State functions * ++ ADC state machine management * ++ Interrupts and flags management * Other functions (extended functions) are available in file * "stm32f3xx_hal_adc_ex.c". * @verbatim ============================================================================== ##### ADC peripheral features ##### ============================================================================== [..] (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on STM32F30xxC devices). (+) Interrupt generation at the end of regular conversion, end of injected conversion, and in case of analog watchdog or overrun events. (+) Single and continuous conversion modes. (+) Scan mode for conversion of several channels sequentially. (+) Data alignment with in-built data coherency. (+) Programmable sampling time (channel wise) (+) ADC conversion of regular group and injected group. (+) External trigger (timer or EXTI) with configurable polarity for both regular and injected groups. (+) DMA request generation for transfer of conversions data of regular group. (+) Multimode dual mode (available on devices with 2 ADCs or more). (+) Configurable DMA data storage in Multimode Dual mode (available on devices with 2 DCs or more). (+) Configurable delay between conversions in Dual interleaved mode (available on devices with 2 DCs or more). (+) ADC calibration (+) ADC channels selectable single/differential input (available only on STM32F30xxC devices) (+) ADC Injected sequencer&channels configuration context queue (available only on STM32F30xxC devices) (+) ADC offset on injected and regular groups (offset on regular group available only on STM32F30xxC devices) (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed. (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). ##### How to use this driver ##### ============================================================================== [..] *** Configuration of top level parameters related to ADC *** ============================================================ [..] (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. (++) For STM32F30x/STM32F33x devices: Two possible clock sources: synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz. - Synchronous clock is mandatory since used as ADC core clock. Synchronous clock can be used optionally as ADC conversion clock, depending on ADC init structure clock setting. Synchronous clock is configured using macro __ADCx_CLK_ENABLE(). - Asynchronous can be used optionally as ADC conversion clock, depending on ADC init structure clock setting. Asynchronous clock is configured using function HAL_RCCEx_PeriphCLKConfig(). (+++) For example, in case of device with a single ADC: Into HAL_ADC_MspInit() (recommended code location) or with other device clock parameters configuration: (+++) __HAL_RCC_ADC1_CLK_ENABLE() (mandatory) (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock) (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock) (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock) (+++) For example, in case of device with 4 ADCs: (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) (+++) { (+++) __HAL_RCC_ADC12_CLK_ENABLE() (mandatory) (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if ADC conversion from asynchronous clock) (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_DIV1 (optional, if ADC conversion from asynchronous clock) (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if ADC conversion from asynchronous clock) (+++) } (+++) else (+++) { (+++) __HAL_RCC_ADC34_CLK_ENABLE() (mandatory) (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_DIV1; (optional, if ADC conversion from asynchronous clock) (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure); (optional, if ADC conversion from asynchronous clock) (+++) } (++) For STM32F37x devices: One clock setting is mandatory: ADC clock (core and conversion clock) from APB2 clock. (+++) Example: Into HAL_ADC_MspInit() (recommended code location) or with other device clock parameters configuration: (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_DIV2 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_ENABLE() (++) Configure these ADC pins in analog mode using function HAL_GPIO_Init() (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: (++) Configure the DMA (DMA channel, mode normal or circular, ...) using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, groups regular/injected, channels parameters *** ========================================================================== [..] (#) Configure the ADC parameters (resolution, data alignment, ...) and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). (#) Optionally, configure the injected group parameters (conversion trigger, sequencer, ..., of injected group) and the channels for injected group parameters (channel number, channel rank into sequencer, ..., into injected group) using function HAL_ADCEx_InjectedConfigChannel(). (#) Optionally, configure the analog watchdog parameters (channels monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). (#) Optionally, for devices with several ADC instances: configure the multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). *** Execution of ADC conversions *** ==================================== [..] (#) Optionally, perform an automatic ADC calibration to improve the conversion accuracy using function HAL_ADCEx_Calibration_Start(). (#) ADC driver can be used among three modes: polling, interruption, transfer by DMA. (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (or for injected group: HAL_ADCEx_InjectedGetValue() ) (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() (++) For devices with several ADCs: ADC multimode conversion with transfer by DMA: (+++) Activate the ADC peripheral (slave) using function HAL_ADC_Start() (conversion start pending ADC master) (+++) Activate the ADC peripheral (master) and start conversions using function HAL_ADCEx_MultiModeStart_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral (master) using function HAL_ADCEx_MultiModeStop_DMA() (+++) Stop conversion and disable the ADC peripheral (slave) using function HAL_ADC_Stop_IT() [..] (@) Callback functions must be implemented in user program: (+@) HAL_ADC_ErrorCallback() (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) (+@) HAL_ADC_ConvCpltCallback() (+@) HAL_ADC_ConvHalfCpltCallback (+@) HAL_ADCEx_InjectedConvCpltCallback() (+@) HAL_ADCEx_InjectedQueueOverflowCallback() (for STM32F30x/STM32F33x devices) *** Deinitialization of ADC *** ============================================================ [..] (#) Disable the ADC interface (++) ADC clock can be hard reset and disabled at RCC top level. (++) Hard reset of ADC peripherals using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). (++) ADC clock disable using the equivalent macro/functions as configuration step. (++) For STM32F30x/STM32F33x devices: Caution: For devices with several ADCs: These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4 if available (ADC2, ADC3, ADC4 availability depends on STM32 product) (+++) For example, in case of device with a single ADC: Into HAL_ADC_MspDeInit() (recommended code location) or with other device clock parameters configuration: (+++) __HAL_RCC_ADC1_FORCE_RESET() (optional) (+++) __HAL_RCC_ADC1_RELEASE_RESET() (optional) (+++) __HAL_RCC_ADC1_CLK_DISABLE() (mandatory) (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before) (+++) PeriphClkInit.Adc1ClockSelection = RCC_ADC1PLLCLK_OFF (optional, if configured before) (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before) (+++) For example, in case of device with 4 ADCs: (+++) if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) (+++) { (+++) __HAL_RCC_ADC12_FORCE_RESET() (optional) (+++) __HAL_RCC_ADC12_RELEASE_RESET() (optional) (+++) __HAL_RCC_ADC12_CLK_DISABLE() (mandatory) (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (optional, if configured before) (+++) PeriphClkInit.Adc12ClockSelection = RCC_ADC12PLLCLK_OFF (optional, if configured before) (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before) (+++) } (+++) else (+++) { (+++) __HAL_RCC_ADC32_FORCE_RESET() (optional) (+++) __HAL_RCC_ADC32_RELEASE_RESET() (optional) (+++) __HAL_RCC_ADC34_CLK_DISABLE() (mandatory) (+++) PeriphClkInit.Adc34ClockSelection = RCC_ADC34PLLCLK_OFF (optional, if configured before) (+++) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStructure) (optional, if configured before) (+++) } (++) For STM32F37x devices: (+++) Example: Into HAL_ADC_MspDeInit() (recommended code location) or with other device clock parameters configuration: (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK_OFF (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) (#) ADC pins configuration (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() (#) Optionally, in case of usage of ADC with interruptions: (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA using function HAL_DMA_DeInit(). (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) [..] *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_ADC_RegisterCallback() to register an interrupt callback. [..] Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback [..] By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() or @ref HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup ADC ADC * @brief ADC HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** * @brief Initializes the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * depending on both possible clock sources: PLL clock or AHB clock. * See commented example code below that can be copied and uncommented * into HAL_ADC_MspInit(). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @note For devices with several ADCs: parameters related to common ADC * registers (ADC clock mode) are set only if all ADCs sharing the * same common group are disabled. * If this is not the case, these common parameters setting are * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs sharing the same common group. * @param hadc ADC handle * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * If this is not the case, reset of these common parameters reset is * bypassed without error reporting: it can be the intended behaviour in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @note For devices with several ADCs: Global reset of all ADCs sharing a * common group is possible. * As this function is intended to reset a single ADC, to not impact * other ADCs, instructions for global reset of multiple ADCs have been * let commented below. * If needed, the example code can be copied and uncommented into * function HAL_ADC_MspDeInit(). * @param hadc ADC handle * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Initializes the ADC MSP. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. */ } /** * @brief DeInitializes the ADC MSP. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. */ } #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief Register a User ADC Callback * To be used instead of the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; return HAL_ERROR; } if ((hadc->State & HAL_ADC_STATE_READY) != 0) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = pCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = pCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = pCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = pCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } /** * @brief Unregister a ADC Callback * ADC callback is redirected to the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; if ((hadc->State & HAL_ADC_STATE_READY) != 0) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions * @brief IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular group. (+) Stop conversion of regular group. (+) Poll for conversion complete on regular group. (+) Poll for conversion event. (+) Get result of regular channel conversion. (+) Start conversion of regular group and enable interruptions. (+) Stop conversion of regular group and disable interruptions. (+) Handle ADC interrupt request (+) Start conversion of regular group and enable DMA transfer. (+) Stop conversion of regular group and disable ADC DMA transfer. @endverbatim * @{ */ /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. * @note: Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC slave first, then ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Return function status */ return HAL_ERROR; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note: Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC master first, then ADC slave. * For ADC master, converson is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @param hadc ADC handle * @retval HAL status. */ __weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Wait for regular group conversion to be completed. * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); UNUSED(Timeout); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Poll for conversion event. * @param hadc ADC handle * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices) * @arg ADC_OVR_EVENT: ADC Overrun event * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); UNUSED(EventType); UNUSED(Timeout); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Enables ADC, starts conversion of regular group with interruption. * Interruptions enabled in this function: * - EOC (end of conversion of regular group) or EOS (end of * sequence of regular group) depending on ADC initialization * parameter "EOCSelection" (if available) * - overrun (if available) * Each of these interruptions has its dedicated callback function. * @note: Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC slave first, then ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interruption of * end-of-conversion, disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note: Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC master first, then ADC slave. * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @param hadc ADC handle * @retval HAL status. */ __weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * - overrun (if available) * Each of these interruptions has its dedicated callback function. * @note: Case of multimode enabled (for devices with several ADCs): This * function is for single-ADC mode only. For multimode, use the * dedicated MultimodeStart function. * @param hadc ADC handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ __weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); UNUSED(pData); UNUSED(Length); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note: Case of multimode enabled (for devices with several ADCs): This * function is for single-ADC mode only. For multimode, use the * dedicated MultimodeStop function. * @param hadc ADC handle * @retval HAL status. */ __weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Get ADC regular group conversion result. * @note Reading DR register automatically clears EOC (end of conversion of * regular group) flag. * Additionally, this functions clears EOS (end of sequence of * regular group) flag, in case of the end of the sequence is reached. * @param hadc ADC handle * @retval Converted value */ __weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return ADC converted value */ return hadc->Instance->DR; } /** * @brief Handles ADC interrupt request. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ } /** * @brief Conversion complete callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } /** * @brief Conversion DMA half-transfer callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } /** * @brief Analog watchdog callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file. */ } /** * @brief ADC error callback in non blocking mode * (ADC conversion with interruption or transfer by DMA) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } /** * @} */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog @endverbatim * @{ */ /** * @brief Configures the the selected channel to be linked to the regular * group. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * The recommended sampling time is at least: * - For devices STM32F37x: 17.1us for temperature sensor * - For the other STM32F3 devices: 2.2us for each of channels * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into regular group, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". * @param hadc ADC handle * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); UNUSED(sConfig); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @brief Configures the analog watchdog. * @note Possibility to update parameters on the fly: * This function initializes the selected analog watchdog, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". * @param hadc ADC handle * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ __weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); UNUSED(AnalogWDGConfig); /* Note : This function is defined into this file for library reference. */ /* Function content is located into file stm32f3xx_hal_adc_ex.c */ /* Return function status */ return HAL_ERROR; } /** * @} */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions * @brief ADC Peripheral State functions * @verbatim =============================================================================== ##### Peripheral state and errors functions ##### =============================================================================== [..] This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @endverbatim * @{ */ /** * @brief return the ADC state * @note ADC state machine is managed by bitfield, state must be compared * with bit by bit. * For example: * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " * @param hadc ADC handle * @retval HAL state */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Return ADC state */ return hadc->State; } /** * @brief Return the ADC error code * @param hadc ADC handle * @retval ADC Error Code */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { return hadc->ErrorCode; } /** * @} */ /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Operation functions * ++ Start, stop, get result of conversions of injected * group, using 2 possible modes: polling, interruption. * ++ Multimode feature (available on devices with 2 ADCs or more) * ++ Calibration (ADC automatic self-calibration) * + Control functions * ++ Channels configuration on injected group * Other functions (generic functions) are available in file * "stm32f3xx_hal_adc.c". * @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32f3xx_hal_adc.c". [..] @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup ADCEx ADCEx * @brief ADC Extended HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Constants ADCEx Private Constants * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /* Fixed timeout values for ADC calibration, enable settling time, disable */ /* settling time. */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */ /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */ /* resolution 12 bits. */ /* Unit: ms */ #define ADC_CALIBRATION_TIMEOUT ( 10U) #define ADC_ENABLE_TIMEOUT ( 2U) #define ADC_DISABLE_TIMEOUT ( 2U) #define ADC_STOP_CONVERSION_TIMEOUT ( 11U) /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to worst case, for 1 channel. */ /* - maximum sampling time (601.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */ /* Unit: cycles of CPU clock. */ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ( 156928U) /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */ /* Unit: us */ #define ADC_STAB_DELAY_US ( 10U) /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US ( 10U) #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /* Timeout values for ADC enable and disable settling time. */ /* Values defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_ENABLE_TIMEOUT ( 2U) #define ADC_DISABLE_TIMEOUT ( 2U) /* Delay for ADC calibration: */ /* Hardware prerequisite before starting a calibration: the ADC must have */ /* been in power-on state for at least two ADC clock cycles. */ /* Unit: ADC clock cycles */ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ( 2U) /* Timeout value for ADC calibration */ /* Value defined to be higher than worst cases: low clocks freq, */ /* maximum prescaler. */ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4U, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ #define ADC_CALIBRATION_TIMEOUT ( 10U) /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ #define ADC_STAB_DELAY_US ( 1U) /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US ( 10U) /* Maximum number of CPU cycles corresponding to 1 ADC cycle */ /* Value fixed to worst case: clock prescalers slowing down ADC clock to */ /* minimum frequency */ /* - AHB prescaler: 16 */ /* - ADC prescaler: 8 */ /* Unit: cycles of CPU clock. */ #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ( 128U) /* ADC conversion cycles (unit: ADC clock cycles) */ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ /* resolution 12 bits) */ #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ( 14U) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ( 20U) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ( 26U) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ( 41U) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ( 54U) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ( 68U) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ( 84U) #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 (252U) #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); #endif /* STM32F373xC || STM32F378xx */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAError(DMA_HandleTypeDef *hdma); /* Exported functions --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions * @{ */ /** @defgroup ADCEx_Exported_Functions_Group1 ADCEx Initialization and de-initialization functions * @brief ADC Extended Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Initializes the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * depending on possible clock sources: AHB clock or PLL clock. * See commented example code below that can be copied and uncommented * into HAL_ADC_MspInit(). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned by ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @note For devices with several ADCs: parameters related to common ADC * registers (ADC clock mode) are set only if all ADCs sharing the * same common group are disabled. * If this is not the case, these common parameters setting are * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs sharing the same common group. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpCFGR = 0U; __IO uint32_t wait_loop_index = 0U; /* Check ADC handle */ if(hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if(hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* Configuration of ADC core parameters and ADC MSP related parameters */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ /* at RCC top level. */ /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ /* - ADC voltage regulator enable */ if (hadc->State == HAL_ADC_STATE_RESET) { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); /* Initialize HAL ADC API internal variables */ hadc->InjectionConfig.ChannelCount = 0U; hadc->InjectionConfig.ContextQueue = 0U; /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Enable voltage regulator (if disabled at this step) */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0)) { /* Note: The software must wait for the startup time of the ADC */ /* voltage regulator before launching a calibration or */ /* enabling the ADC. This temporization must be implemented by */ /* software and is equal to 10 us in the worst case */ /* process/temperature/power supply. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ /* Configuration of ADC parameters if previous preliminary actions */ /* are correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set the intermediate state before moving the ADC voltage */ /* regulator to state enable. */ CLEAR_BIT(hadc->Instance->CR, (ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0)); /* Set ADVREGEN bits to 0x01U */ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_0); /* Delay for ADC stabilization time. */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } } } } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0) || HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADVREGEN_1) ) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } } /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (tmp_hal_status == HAL_OK) && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode clock configuration */ if ((ADC_IS_ENABLE(hadc) == RESET) && ((tmphadcSharingSameCommonRegister.Instance == NULL) || (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) { /* Reset configuration of ADC common register CCR: */ /* - ADC clock mode: CKMODE */ /* Some parameters of this register are not reset, since they are set */ /* by other functions and must be kept in case of usage of this */ /* function on the fly (update of a parameter of ADC_InitTypeDef */ /* without needing to reconfigure all other ADC groups/channels */ /* parameters): */ /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */ /* into HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ MODIFY_REG(tmpADC_Common->CCR , ADC_CCR_CKMODE , hadc->Init.ClockPrescaler ); } /* Configuration of ADC: */ /* - resolution */ /* - data alignment */ /* - external trigger to start conversion */ /* - external trigger polarity */ /* - continuous conversion mode */ /* - overrun */ /* - discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | ADC_CFGR_OVERRUN(hadc->Init.Overrun) | hadc->Init.DataAlign | hadc->Init.Resolution ); /* Enable discontinuous mode only if continuous mode is disabled */ if (hadc->Init.DiscontinuousConvMode == ENABLE) { if (hadc->Init.ContinuousConvMode == DISABLE) { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ SET_BIT(tmpCFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); } else { /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { SET_BIT(tmpCFGR, ADC_CFGR_EXTSEL_SET(hadc, hadc->Init.ExternalTrigConv) | hadc->Init.ExternalTrigConvEdge ); } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - DMA continuous request */ /* - LowPowerAutoWait feature */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY | ADC_CFGR_DMACFG ); SET_BIT(tmpCFGR, ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); } /* Update ADC configuration register with previous settings */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_ALIGN | ADC_CFGR_RES , tmpCFGR ); /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1U) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1 , ADC_SQR1_L , (hadc->Init.NbrOfConversion - (uint8_t)1U) ); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Initializes the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (clock source APB2). * See commented example code below that can be copied and uncommented * into HAL_ADC_MspInit(). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_cr1 = 0U; uint32_t tmp_cr2 = 0U; uint32_t tmp_sqr1 = 0U; /* Check ADC handle */ if(hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if(hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ /* at RCC top level. */ /* Refer to header of this file for more details on clock enabling */ /* procedure. */ /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) { /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ /* Note: In case of ADC already enabled, precaution to not launch an */ /* unwanted conversion while modifying register CR2 by writing 1 to */ /* bit ADON. */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && (tmp_hal_status == HAL_OK) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Set ADC parameters */ /* Configuration of ADC: */ /* - data alignment */ /* - external trigger to start conversion */ /* - external trigger polarity (always set to 1U, because needed for all */ /* triggers: external trigger of SW start) */ /* - continuous conversion mode */ /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ /* HAL_ADC_Start_xxx functions because if set in this function, */ /* a conversion on injected group would start a conversion also on */ /* regular group after ADC enabling. */ tmp_cr2 |= (hadc->Init.DataAlign | hadc->Init.ExternalTrigConv | ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) ); /* Configuration of ADC: */ /* - scan mode */ /* - discontinuous mode disable/enable */ /* - discontinuous mode number of conversions */ tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); /* Enable discontinuous mode only if continuous mode is disabled */ /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ /* discontinuous is set anyway, but will have no effect on ADC HW. */ if (hadc->Init.DiscontinuousConvMode == ENABLE) { if (hadc->Init.ContinuousConvMode == DISABLE) { /* Enable the selected ADC regular discontinuous mode */ /* Set the number of channels to be converted in discontinuous mode */ tmp_cr1 |= (ADC_CR1_DISCEN | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); } else { /* ADC regular group discontinuous was intended to be enabled, */ /* but ADC regular group modes continuous and sequencer discontinuous */ /* cannot be enabled simultaneously. */ /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } /* Update ADC configuration register CR1 with previous settings */ MODIFY_REG(hadc->Instance->CR1, ADC_CR1_SCAN | ADC_CR1_DISCEN | ADC_CR1_DISCNUM , tmp_cr1 ); /* Update ADC configuration register CR2 with previous settings */ MODIFY_REG(hadc->Instance->CR2, ADC_CR2_ALIGN | ADC_CR2_EXTSEL | ADC_CR2_EXTTRIG | ADC_CR2_CONT , tmp_cr2 ); /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1U) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion" */ if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) { tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); } MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L , tmp_sqr1 ); /* Check back that ADC registers have effectively been configured to */ /* ensure of no potential problem of ADC core IP clocking. */ /* Check through register CR2 (excluding bits set in other functions: */ /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ /* measurement path bit (TSVREFE). */ if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_TSVREFE )) == tmp_cr2) { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * If this is not the case, reset of these common parameters reset is * bypassed without error reporting: it can be the intended behaviour in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @note For devices with several ADCs: Global reset of all ADCs sharing a * common group is possible. * As this function is intended to reset a single ADC, to not impact * other ADCs, instructions for global reset of multiple ADCs have been * let commented below. * If needed, the example code can be copied and uncommented into * function HAL_ADC_MspDeInit(). * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; /* Check ADC handle */ if(hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Flush register JSQR: queue sequencer reset when injected queue */ /* sequencer is enabled and ADC disabled. */ /* Enable injected queue sequencer after injected conversion stop */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); /* Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; } else { tmp_hal_status = HAL_ERROR; } } /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (tmp_hal_status == HAL_OK) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF | ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC | ADC_IT_EOSMP | ADC_IT_RDY ) ); /* Reset register ISR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF | ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); /* Reset register CR */ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */ /* in access mode "read-set": no direct reset applicable. */ /* Reset Calibration mode to default setting (single ended): */ /* Disable voltage regulator: */ /* Note: Voltage regulator disable is conditioned to ADC state disabled: */ /* already done above. */ /* Note: Voltage regulator disable is intended for power saving. */ /* Sequence to disable voltage regulator: */ /* 1. Set the intermediate state before moving the ADC voltage regulator */ /* to disable state. */ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF); /* 2. Set ADVREGEN bits to 0x10U */ SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN_1); /* Reset register CFGR */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 ); /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 ); /* Reset register TR1 */ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); /* Reset register TR2 */ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); /* Reset register TR3 */ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L); /* Reset register SQR2 */ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5); /* Reset register SQR3 */ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10); /* Reset register SQR4 */ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ /* Reset register OFR1 */ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); /* Reset register OFR3 */ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); /* Reset register OFR4 */ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ /* Reset register AWD2CR */ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); /* Reset register AWD3CR */ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); /* Reset register DIFSEL */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); /* Reset register CALFACT */ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); /* ========== Reset common ADC registers ========== */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); /* Software is allowed to change common parameters only when all ADCs of */ /* the common group are disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && ( (tmphadcSharingSameCommonRegister.Instance == NULL) || (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) { /* Reset configuration of ADC common register CCR: - clock mode: CKMODE - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into HAL_ADCEx_MultiModeConfigChannel() ) - internal measurement paths: Vbat, temperature sensor, Vref (set into HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_CKMODE | ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_MDMA | ADC_CCR_DMACFG | ADC_CCR_DELAY | ADC_CCR_MULTI ); /* Other ADC common registers (CSR, CDR) are in access mode read only, no direct reset applicable */ } /* ========== Hard reset and clock disable of ADC peripheral ========== */ /* Into HAL_ADC_MspDeInit(), ADC clock can be hard reset and disabled */ /* at RCC top level. */ /* Refer to header of this file for more details on clock disabling */ /* procedure. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } /* DeInit the low level hardware */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Deinitialize the ADC peripheral registers to its default reset values. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check ADC handle */ if(hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (tmp_hal_status == HAL_OK) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); /* Reset register CR1 */ CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )); /* Reset register CR2 */ CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | ADC_CR2_ADON )); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 )); /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0 )); /* Reset register JOFR1 */ CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); /* Reset register JOFR2 */ CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); /* Reset register JOFR3 */ CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); /* Reset register JOFR4 */ CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); /* Reset register HTR */ CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); /* Reset register LTR */ CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); /* Reset register SQR2 */ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 ); /* Reset register SQR3 */ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 ); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); /* Reset register JSQR */ CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ /* Reset VBAT measurement path, in case of enabled before by selecting */ /* channel ADC_CHANNEL_VBAT. */ SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT); /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripheral: ADC state is */ /* forced to a similar state after device power-on. */ /* If needed, copy-paste and uncomment the following reset code into */ /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ /* */ /* __HAL_RCC_ADC1_FORCE_RESET() */ /* __HAL_RCC_ADC1_RELEASE_RESET() */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } /* DeInit the low level hardware */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /** @defgroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions * @brief ADC Extended IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular group. (+) Stop conversion of regular group. (+) Poll for conversion complete on regular group. (+) Poll for conversion event. (+) Get result of regular channel conversion. (+) Start conversion of regular group and enable interruptions. (+) Stop conversion of regular group and disable interruptions. (+) Handle ADC interrupt request (+) Start conversion of regular group and enable DMA transfer. (+) Stop conversion of regular group and disable ADC DMA transfer. (+) Start conversion of injected group. (+) Stop conversion of injected group. (+) Poll for conversion complete on injected group. (+) Get result of injected channel conversion. (+) Start conversion of injected group and enable interruptions. (+) Stop conversion of injected group and disable interruptions. (+) Start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. @endverbatim * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. * @note Case of multimode enabled (for devices with several ADCs): * if ADC is slave, ADC is enabled only (conversion is not started). * if ADC is master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular*/ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (for devices with several ADCs): */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) { SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enables ADC, starts conversion of regular group. * Interruptions enabled in this function: None. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) */ /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Stop ADC conversion of both groups regular and injected, * disable ADC peripheral. * @note ADC peripheral disable is forcing interruption of potential * conversion on injected group. If injected group is under use, * it should be preliminarily stopped using function * @ref HAL_ADCEx_InjectedStop(). * To stop ADC conversion only on ADC group regular * while letting ADC group injected conversions running, * use function @ref HAL_ADCEx_RegularStop(). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. * @note ADC peripheral disable is forcing interruption of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Wait for regular group conversion to be completed. * @note ADC conversion flags EOS (end of sequence) and EOC (end of * conversion) are cleared by this function, with an exception: * if low power feature "LowPowerAutoWait" is enabled, flags are * not cleared to not interfere with this feature until data register * is read using function HAL_ADC_GetValue(). * @note This function cannot be used in a particular setup: ADC configured * in DMA mode and polling for end of each conversion (ADC init * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @note Depending on init parameter "EOCSelection", flags EOS or EOC is * checked and cleared depending on autodelay status (bit AUTDLY). * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_EOC; ADC_Common_TypeDef *tmpADC_Common; uint32_t tmp_cfgr = 0x0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_Flag_EOC = ADC_FLAG_EOS; } /* If end of conversion selected to end of each conversion */ else /* ADC_EOC_SINGLE_CONV */ { /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check DMA configuration, depending on MultiMode set or not */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT) { if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } else { /* MultiMode is enabled, Common Control Register MDMA bits must be checked */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if(ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait until End of Conversion or End of Sequence flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) { /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } /* Clear end of conversion flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) { /* Clear regular group conversion flag */ /* (EOC or EOS depending on HAL ADC initialization parameter) */ __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC); } /* Return ADC state */ return HAL_OK; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Wait for regular group conversion to be completed. * @note This function cannot be used in a particular setup: ADC configured * in DMA mode. * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. * @note On STM32F37x devices, limitation in case of sequencer enabled * (several ranks selected): polling cannot be done on each * conversion inside the sequence. In this case, polling is replaced by * wait for maximum conversion time. * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { uint32_t tickstart; /* Variables for polling in case of scan mode enabled */ uint32_t Conversion_Timeout_CPU_cycles_max = 0U; uint32_t Conversion_Timeout_CPU_cycles = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Get tick count */ tickstart = HAL_GetTick(); /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* - If single conversion for regular group (Scan mode disabled or enabled */ /* with NbrOfConversion =1U), flag EOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for regular group (scan mode enabled and */ /* NbrOfConversion >=2U), flag EOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag EOC is not set after each conversion, no timeout status can */ /* be set. */ if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } else { /* Replace polling by wait for maximum conversion time */ /* Calculation of CPU cycles corresponding to ADC conversion cycles. */ /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ /* channels. */ Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE() ; Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc); /* Poll with maximum conversion time */ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } Conversion_Timeout_CPU_cycles ++; } } /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F37x devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Poll for conversion event. * @param hadc ADC handle * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) * @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) * @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) * @arg ADC_OVR_EVENT: ADC Overrun event * @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get start tick count */ tickstart = HAL_GetTick(); /* Check selected event flag */ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } switch(EventType) { /* Analog watchdog (level out of window) event */ /* Note: In case of several analog watchdog enabled, if needed to know */ /* which one triggered and on which ADCx, test ADC state of analog watchdog */ /* flags HAL_ADC_STATE_AWD1/2U/3 using function "HAL_ADC_GetState()". */ /* For example: */ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */ /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */ /* Check analog watchdog 1 flag */ case ADC_AWD_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); break; /* Check analog watchdog 2 flag */ case ADC_AWD2_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); break; /* Check analog watchdog 3 flag */ case ADC_AWD3_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); break; /* Injected context queue overflow event */ case ADC_JQOVF_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); /* Clear ADC Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); break; /* Overrun event */ default: /* Case ADC_OVR_EVENT */ /* If overrun is set to overwrite previous data, overrun event is not */ /* considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and without */ /* overrun ") */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); } /* Clear ADC Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); break; } /* Return ADC state */ return HAL_OK; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Poll for conversion event. * @param hadc ADC handle * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watchdog event. * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); tickstart = HAL_GetTick(); /* Check selected event flag */ while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } /* Analog watchdog (level out of window) event */ /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); /* Return ADC state */ return HAL_OK; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Enables ADC, starts conversion of regular group with interruption. * Interruptions enabled in this function: * - EOC (end of conversion of regular group) or EOS (end of * sequence of regular group) depending on ADC initialization * parameter "EOCSelection" * - overrun, depending on ADC initialization parameter "Overrun" * Each of these interruptions has its dedicated callback function. * @note Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC slave first, then ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular*/ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Enable ADC end of conversion interrupt */ /* Enable ADC overrun interrupt */ switch(hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS)); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS)); break; } /* If overrun is set to overwrite previous data (default setting), */ /* overrun interrupt is not activated (overrun event is not considered */ /* as an error). */ /* (cf ref manual "Managing conversions without using the DMA and */ /* without overrun ") */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); } /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (for devices with several ADCs): */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) { SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enables ADC, starts conversion of regular group with interruption. * Interruptions enabled in this function: * - EOC (end of conversion of regular group) * Each of these interruptions has its dedicated callback function. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) */ /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Stop ADC conversion of both groups regular and injected, * disable ADC peripheral. * Interruptions disabled in this function: * - EOC (end of conversion of regular group) and EOS (end of * sequence of regular group) * - overrun * @note ADC peripheral disable is forcing interruption of potential * conversion on injected group. If injected group is under use, * it should be preliminarily stopped using function * @ref HAL_ADCEx_InjectedStop(). * To stop ADC conversion only on ADC group regular * while letting ADC group injected conversions running, * use function @ref HAL_ADCEx_RegularStop_IT(). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * - overrun * Each of these interruptions has its dedicated callback function. * @note Case of multimode enabled (for devices with several ADCs): This * function is for single-ADC mode only. For multimode, use the * dedicated MultimodeStart function. * @param hadc ADC handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Verification if multimode is disabled (for devices with several ADC) */ /* If multimode is enabled, dedicated function multimode conversion */ /* start DMA must be used. */ if(ADC_COMMON_CCR_MULTI(hadc) == RESET) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) and multimode state */ /* for all cases of multimode: independent mode, multimode ADC master */ /* or multimode ADC slave (for devices with several ADCs): */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { /* Set ADC state (ADC independent or master) */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } else { /* Set ADC state (ADC slave) */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* If conversions on group regular are also triggering group injected,*/ /* update ADC state. */ if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular*/ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately.*/ /* If external trigger has been selected, conversion will start at */ /* next trigger event. */ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStart function. * @param hadc ADC handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_BUSY); /* Set group injected state (from auto-injection) */ /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode */ hadc->Instance->CR2 |= ADC_CR2_DMA; /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Stop ADC conversion of both groups regular and injected, * disable ADC DMA transfer, disable ADC peripheral. * Interruptions disabled in this function: * - DMA transfer complete * - DMA half transfer * - overrun * @note ADC peripheral disable is forcing interruption of potential * conversion on injected group. If injected group is under use, * it should be preliminarily stopped using function * @ref HAL_ADCEx_InjectedStop(). * To stop ADC conversion only on ADC group regular * while letting ADC group injected conversions running, * use function @ref HAL_ADCEx_RegularStop_DMA(). * @note Case of multimode enabled (for devices with several ADCs): This * function is for single-ADC mode only. For multimode, use the * dedicated MultimodeStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to retain a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note ADC peripheral disable is forcing interruption of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note For devices with several ADCs: This function is for single-ADC mode * only. For multimode, use the dedicated MultimodeStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA mode */ hadc->Instance->CR2 &= ~ADC_CR2_DMA; /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent * to flag EOC. * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: ADC flag EOC is not cleared here by software because */ /* automatically cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent * to flag EOC. * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Handles ADC interrupt request. * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { uint32_t overrun_error = 0U; /* flag set if overrun occurrence has to be considered as an error */ ADC_Common_TypeDef *tmpADC_Common; uint32_t tmp_cfgr = 0x0U; uint32_t tmp_cfgr_jqm = 0x0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); /* ========== Check End of Conversion flag for regular group ========== */ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) || (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) ) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); } /* Disable interruption if no further conversion upcoming by regular */ /* external trigger or by continuous mode, */ /* and if scan sequence if completed. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == RESET) ) { /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } /* Conversion complete callback */ /* Note: into callback, to determine if conversion has been triggered */ /* from EOC or EOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved */ /* data. */ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); } /* ========== Check End of Conversion flag for injected group ========== */ if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) || (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS)) ) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(hadc)) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); } /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) { /* If End of Sequence is reached, disable interrupts */ if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc)) { tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); } else { tmp_cfgr_jqm = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); } /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if(READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) == RESET) { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } /* Conversion complete callback */ /* Note: into callback, to determine if conversion has been triggered */ /* from JEOC or JEOS, possibility to use: */ /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } /* ========== Check analog watchdog 1 flag ========== */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); } /* ========== Check analog watchdog 2 flag ========== */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Level out of window 2 callback */ HAL_ADCEx_LevelOutOfWindow2Callback(hadc); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); } /* ========== Check analog watchdog 3 flag ========== */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Level out of window 3 callback */ HAL_ADCEx_LevelOutOfWindow3Callback(hadc); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); } /* ========== Check Overrun flag ========== */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR)) { /* If overrun is set to overwrite previous data (default setting), */ /* overrun event is not considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and */ /* without overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { overrun_error = 1U; } else { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check DMA configuration, depending on MultiMode set or not */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI) == ADC_MODE_INDEPENDENT) { if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) { overrun_error = 1U; } } else { /* MultiMode is enabled, Common Control Register MDMA bits must be checked */ if (READ_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA) != RESET) { overrun_error = 1U; } } } if (overrun_error == 1U) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear the Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } /* ========== Check Injected context queue overflow flag ========== */ if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); /* Error callback */ HAL_ADCEx_InjectedQueueOverflowCallback(hadc); } } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Handles ADC interrupt request * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); /* ========== Check End of Conversion flag for regular group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F37x devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Disable ADC end of single conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } } /* ========== Check End of Conversion flag for injected group ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } /* Determine whether any further conversion upcoming on group injected */ /* by external trigger, scan sequence on going or by automatic injected */ /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ /* Note: On STM32F37x devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) { /* Disable ADC end of single conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); } } /* ========== Check Analog watchdog flags ========== */ if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) { if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); } } } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @param hadc ADC handle * @param SingleDiff Selection of single-ended or differential input * This parameter can be one of the following values: * @arg ADC_SINGLE_ENDED: Channel in mode input single ended * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; /* Select calibration mode single ended or differential ended */ hadc->Instance->CR &= (~ADC_CR_ADCALDIF); if (SingleDiff == ADC_DIFFERENTIAL_ENDED) { hadc->Instance->CR |= ADC_CR_ADCALDIF; } /* Start ADC calibration */ hadc->Instance->CR |= ADC_CR_ADCAL; tickstart = HAL_GetTick(); /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL)) { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * During calibration process, ADC is enabled. ADC is let enabled at * the completion of this function. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Wait two ADC clock cycles */ while(wait_loop_index < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2U) { wait_loop_index++; } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); tickstart = HAL_GetTick(); /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); tickstart = HAL_GetTick(); /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Get the calibration factor from automatic conversion result * @param hadc ADC handle * @param SingleDiff Selection of single-ended or differential input * This parameter can be one of the following values: * @arg ADC_SINGLE_ENDED: Channel in mode input single ended * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended * @retval Converted value */ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Return the selected ADC calibration value */ if (SingleDiff == ADC_DIFFERENTIAL_ENDED) { return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT); } else { return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S); } } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going. * @param hadc ADC handle * @param SingleDiff Selection of single-ended or differential input * This parameter can be one of the following values: * @arg ADC_SINGLE_ENDED: Channel in mode input single ended * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); /* Process locked */ __HAL_LOCK(hadc); /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ if ( (ADC_IS_ENABLE(hadc) != RESET) && (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) ) { /* Set the selected ADC calibration value */ if (SingleDiff == ADC_DIFFERENTIAL_ENDED) { MODIFY_REG(hadc->Instance->CALFACT , ADC_CALFACT_CALFACT_D , ADC_CALFACT_DIFF_SET(CalibrationFactor) ); } else { MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S , CalibrationFactor ); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Enables ADC, starts conversion of injected group. * Interruptions enabled in this function: None. * @note Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC slave first, then ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode(for devices with several ADCs):*/ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); /* Enable conversion of injected group, if automatic injected */ /* conversion is disabled. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (for devices with several ADCs): */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) && ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) ) { SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enables ADC, starts conversion of injected group. * Interruptions enabled in this function: None. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable conversion of injected group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Stop ADC group injected conversion (potential conversion on going * on ADC group regular is not impacted), disable ADC peripheral * if no conversion is on going on group regular. * @note To stop ADC conversion of both groups regular and injected and to * to disable ADC peripheral, instead of using 2 functions * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(), * use function @ref HAL_ADC_Stop(). * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC master first, then ADC slave. * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @note In case of auto-injection mode, HAL_ADC_Stop must be used. * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential ADC conversion on going and disable ADC peripheral */ /* conditioned to: */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ /* - For ADC injected group conversion stop: */ /* On this STM32 family, conversion on the other group */ /* (group regular) can continue (groups regular and injected */ /* conversion stop commands are independent) */ /* - For ADC disable: */ /* No conversion on the other group (group regular) must be intended to */ /* continue (groups regular and injected are both impacted by */ /* ADC disable) */ if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) { /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); /* Disable ADC peripheral if conversion on ADC group injected is */ /* effectively stopped and if no conversion on the other group */ /* (ADC group regular) is intended to continue. */ if (tmp_hal_status == HAL_OK) { if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) && ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) ) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on ADC group injected group is stopped, but ADC is not */ /* disabled since conversion on ADC group regular is still on going. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Wait for injected group conversion to be completed. * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_EOC; uint32_t tmp_cfgr = 0x00000000U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_Flag_EOC = ADC_FLAG_JEOS; } /* If end of conversion selected to end of each conversion */ else /* ADC_EOC_SINGLE_CONV */ { tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS); } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmp_cfgr = READ_REG(ADC_MASTER_INSTANCE(hadc)->CFGR); } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Clear end of conversion flag of injected group if low power feature */ /* "Auto Wait" is disabled, to not interfere with this feature until data */ /* register is read using function HAL_ADC_GetValue(). */ if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) { /* Clear injected group conversion flag */ /* (JEOC or JEOS depending on HAL ADC initialization parameter) */ __HAL_ADC_CLEAR_FLAG(hadc, tmp_Flag_EOC); } /* Return ADC state */ return HAL_OK; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Wait for injected group conversion to be completed. * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { uint32_t tickstart = 0U; /* Variables for polling in case of scan mode enabled */ uint32_t Conversion_Timeout_CPU_cycles_max =0U; uint32_t Conversion_Timeout_CPU_cycles =0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get tick count */ tickstart = HAL_GetTick(); /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* For injected group, flag JEOC is set only at the end of the sequence, */ /* not for each conversion within the sequence. */ /* - If single conversion for injected group (scan mode disabled or */ /* InjectedNbrOfConversion ==1U), flag JEOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for injected group (scan mode enabled and */ /* InjectedNbrOfConversion >=2U), flag JEOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ /* As flag JEOC is not set after each conversion, no timeout status can */ /* be set. */ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } else { /* Replace polling by wait for maximum conversion time */ /* Calculation of CPU cycles corresponding to ADC conversion cycles. */ /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */ /* channels. */ Conversion_Timeout_CPU_cycles_max = ADC_CLOCK_PRESCALER_RANGE(); Conversion_Timeout_CPU_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc); /* Poll with maximum conversion time */ while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } Conversion_Timeout_CPU_cycles ++; } } /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && (ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Return ADC state */ return HAL_OK; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Enables ADC, starts conversion of injected group with interruption. * Interruptions enabled in this function: * - JEOC (end of conversion of injected group) or JEOS (end of * sequence of injected group) depending on ADC initialization * parameter "EOCSelection" * Each of these interruptions has its dedicated callback function. * @note Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC slave first, then ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Case of independent mode or multimode(for devices with several ADCs):*/ /* Set multimode state. */ if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } else { SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET) { __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); } /* Enable ADC end of conversion interrupt */ switch(hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); break; } /* Enable conversion of injected group, if automatic injected */ /* conversion is disabled. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (for devices with several ADCs): */ /* - if ADC is slave, ADC is enabled only (conversion is not started). */ /* - if ADC is master, ADC is enabled and conversion is started. */ if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) && ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(hadc) ) { SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enables ADC, starts conversion of injected group with interruption. * Interruptions enabled in this function: * - JEOC (end of conversion of injected group) * Each of these interruptions has its dedicated callback function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ /* going on group regular, no error code is reset. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); /* Enable end of conversion interrupt for injected channels */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); /* Enable conversion of injected group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* If automatic injected conversion is enabled, conversion will start */ /* after next regular group conversion. */ if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Start ADC conversion on injected group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); } else { /* Start ADC conversion on injected group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); } } /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Stop ADC group injected conversion (potential conversion on going * on ADC group regular is not impacted), disable ADC peripheral * if no conversion is on going on group regular. * Interruptions disabled in this function: * - JEOC (end of conversion of injected group) and JEOS (end of * sequence of injected group) * @note To stop ADC conversion of both groups regular and injected and to * to disable ADC peripheral, instead of using 2 functions * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(), * use function @ref HAL_ADC_Stop(). * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note Case of multimode enabled (for devices with several ADCs): This * function must be called for ADC master first, then ADC slave. * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @note In case of auto-injection mode, HAL_ADC_Stop must be used. * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential ADC conversion on going and disable ADC peripheral */ /* conditioned to: */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ /* - For ADC injected group conversion stop: */ /* On this STM32 family, conversion on the other group */ /* (group regular) can continue (groups regular and injected */ /* conversion stop commands are independent) */ /* - For ADC disable: */ /* No conversion on the other group (group regular) must be intended to */ /* continue (groups regular and injected are both impacted by */ /* ADC disable) */ if(HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) { /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); /* Disable ADC peripheral if conversion on ADC group injected is */ /* effectively stopped and if no conversion on the other group */ /* (ADC group regular) is intended to continue. */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_IT_JQOVF)); if((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) && ((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) ) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on ADC group injected group is stopped, but ADC is not */ /* disabled since conversion on ADC group regular is still on going. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /** * @brief With ADC configured in multimode, for ADC master: * Enables ADC, starts conversion of regular group and transfers result * through DMA. * Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * - overrun * Each of these interruptions has its dedicated callback function. * @note ADC slave must be preliminarily enabled using single-mode * HAL_ADC_Start() function. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @param pData The destination Buffer address. * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave = {0}; ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); /* Process locked */ __HAL_LOCK(hadc); /* Perform ADC enable and conversion start if no conversion is on going */ /* (check on ADC master only) */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Set a temporary handle of the ADC slave associated to the ADC master */ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Enable(&tmphadcSlave); } /* Start conversion all ADCs of multimode are effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state (ADC master) */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP | HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_REG_BUSY); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART); } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } /** * @brief With ADC configured in multimode, for ADC master: * Stop ADC group regular conversion (potential conversion on going * on ADC group injected is not impacted), * disable ADC DMA transfer, disable ADC peripheral * if no conversion is on going on group injected. * Interruptions disabled in this function: * - DMA transfer complete * - DMA half transfer * - overrun * @note In case of auto-injection mode, this function also stop conversion * on ADC group injected. * @note Multimode is kept enabled after this function. To disable multimode * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA must be called after this function with handle of * ADC slave, to properly disable the DMA channel of ADC slave. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave = {0}; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential multimode conversion on going, on regular and */ /* injected groups. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Set a temporary handle of the ADC slave associated to the ADC master */ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ /* 1. Wait until ADSTP=0 for ADC master and ADC slave */ tickstart = HAL_GetTick(); while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) { if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ /* Note: In case of ADC slave using its own DMA channel (multimode */ /* parameter "DMAAccessMode" set to disabled): */ /* DMA channel of ADC slave should stopped after this function with */ /* function HAL_ADC_Stop_DMA. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripherals: master and slave */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to retain a potential failing status. */ if (tmp_hal_status == HAL_OK) { /* Check if ADC are effectively disabled */ if ((ADC_Disable(hadc) != HAL_ERROR) && (ADC_Disable(&tmphadcSlave) != HAL_ERROR) ) { tmp_hal_status = HAL_OK; /* Change ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* In case of error, attempt to disable ADC instances anyway */ ADC_Disable(hadc); ADC_Disable(&tmphadcSlave); /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Returns the last ADC Master&Slave regular conversions results data * in the selected multi mode. * @note Reading register CDR does not clear flag ADC flag EOC * (ADC group regular end of unitary conversion), * as it is the case for independent mode data register. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval The converted data value. */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) { ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Return the multi mode conversion value */ return tmpADC_Common->CDR; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent * to flag JEOC. * - If sequencer is composed of several ranks, during the scan * sequence flag JEOC only is raised, at the end of the scan sequence * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc ADC handle * @param InjectedRank the converted ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); /* Note: ADC flag JEOC is not cleared here by software because */ /* automatically cleared by hardware when reading register JDRx. */ /* Get ADC converted value */ switch(InjectedRank) { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: default: tmp_jdr = hadc->Instance->JDR1; break; } /* Return ADC converted value */ return tmp_jdr; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent * to flag JEOC. * - If sequencer is composed of several ranks, during the scan * sequence flag JEOC only is raised, at the end of the scan sequence * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc ADC handle * @param InjectedRank the converted ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); /* Get ADC converted value */ switch(InjectedRank) { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: default: tmp_jdr = hadc->Instance->JDR1; break; } /* Return ADC converted value */ return tmp_jdr; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Stop ADC group regular conversion (potential conversion on going * on ADC group injected is not impacted), disable ADC peripheral * if no conversion is on going on group injected. * @note To stop ADC conversion of both groups regular and injected and to * to disable ADC peripheral, instead of using 2 functions * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(), * use function @ref HAL_ADC_Stop(). * @note In case of auto-injection mode, this function also stop conversion * on ADC group injected. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential ADC conversion on going and disable ADC peripheral */ /* conditioned to: */ /* - For ADC regular group conversion stop: */ /* On this STM32 family, conversion on the other group */ /* (group injected) can continue (groups regular and injected */ /* conversion stop commands are independent) */ /* - For ADC disable: */ /* No conversion on the other group (group injected) must be intended to */ /* continue (groups regular and injected are both impacted by */ /* ADC disable) */ /* 1. Stop potential conversion on going, on regular group only */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversion on ADC group regular is */ /* effectively stopped and if no conversion on the other group */ /* (ADC group injected) is intended to continue. */ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) && ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) ) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on ADC group regular group is stopped, but ADC is not */ /* disabled since conversion on ADC group injected is still on going. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC group regular conversion (potential conversion on going * on ADC group injected is not impacted), disable ADC peripheral * if no conversion is on going on group injected. * Interruptions disabled in this function: * - EOC (end of conversion of regular group) and EOS (end of * sequence of regular group) * - overrun * @note To stop ADC conversion of both groups regular and injected and to * to disable ADC peripheral, instead of using 2 functions * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(), * use function @ref HAL_ADC_Stop(). * @note In case of auto-injection mode, this function also stop conversion * on ADC group injected. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential ADC conversion on going and disable ADC peripheral */ /* conditioned to: */ /* - For ADC regular group conversion stop: */ /* On this STM32 family, conversion on the other group */ /* (group injected) can continue (groups regular and injected */ /* conversion stop commands are independent) */ /* - For ADC disable: */ /* No conversion on the other group (group injected) must be intended to */ /* continue (groups regular and injected are both impacted by */ /* ADC disable) */ /* 1. Stop potential conversion on going, on regular group only */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversion on ADC group regular is */ /* effectively stopped and if no conversion on the other group */ /* (ADC group injected) is intended to continue. */ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) && ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) ) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on ADC group regular group is stopped, but ADC is not */ /* disabled since conversion on ADC group injected is still on going. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC group regular conversion (potential conversion on going * on ADC group injected is not impacted), * disable ADC DMA transfer, disable ADC peripheral * if no conversion is on going on group injected. * Interruptions disabled in this function: * - DMA transfer complete * - DMA half transfer * - overrun * @note To stop ADC conversion of both groups regular and injected and to * to disable ADC peripheral, instead of using 2 functions * @ref HAL_ADCEx_RegularStop() and @ref HAL_ADCEx_InjectedStop(), * use function @ref HAL_ADC_Stop(). * @note Case of multimode enabled (for devices with several ADCs): This * function is for single-ADC mode only. For multimode, use the * dedicated MultimodeStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential ADC conversion on going and disable ADC peripheral */ /* conditioned to: */ /* - For ADC regular group conversion stop: */ /* On this STM32 family, conversion on the other group */ /* (group injected) can continue (groups regular and injected */ /* conversion stop commands are independent) */ /* - For ADC disable: */ /* No conversion on the other group (group injected) must be intended to */ /* continue (groups regular and injected are both impacted by */ /* ADC disable) */ /* 1. Stop potential conversion on going, on regular group only */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversion on ADC group regular is */ /* effectively stopped and if no conversion on the other group */ /* (ADC group injected) is intended to continue. */ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) && ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) ) { /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to retain a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on ADC group regular group is stopped, but ADC is not */ /* disabled since conversion on ADC group injected is still on going. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /** * @brief With ADC configured in multimode, for ADC master: * Stop ADC group regular conversion (potential conversion on going * on ADC group injected is not impacted), * disable ADC DMA transfer, disable ADC peripheral * if no conversion is on going on group injected. * Interruptions disabled in this function: * - DMA transfer complete * - DMA half transfer * - overrun * @note To stop ADC conversion of both groups regular and injected and to * to disable ADC peripheral, instead of using 2 functions * @ref HAL_ADCEx_RegularMultiModeStop_DMA() and * @ref HAL_ADCEx_InjectedStop(), use function * @ref HAL_ADCEx_MultiModeStop_DMA. * @note In case of auto-injection mode, this function also stop conversion * on ADC group injected. * @note Multimode is kept enabled after this function. To disable multimode * (set with HAL_ADCEx_MultiModeConfigChannel() ), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA must be called after this function with handle of * ADC slave, to properly disable the DMA channel of ADC slave. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval None */ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave = {0}; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* Stop potential ADC conversion on going and disable ADC peripheral */ /* conditioned to: */ /* - For ADC regular group conversion stop: */ /* On this STM32 family, conversion on the other group */ /* (group injected) can continue (groups regular and injected */ /* conversion stop commands are independent) */ /* - For ADC disable: */ /* No conversion on the other group (group injected) must be intended to */ /* continue (groups regular and injected are both impacted by */ /* ADC disable) */ /* 1. Stop potential conversion on going, on regular group only */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversion on ADC group regular is */ /* effectively stopped and if no conversion on the other group */ /* (ADC group injected) is intended to continue. */ if((ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) && ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == RESET) ) { /* Set a temporary handle of the ADC slave associated to the ADC master */ /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/ tickstart = HAL_GetTick(); while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) || ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) ) { if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ /* Note: In case of ADC slave using its own DMA channel (multimode */ /* parameter "DMAAccessMode" set to disabled): */ /* DMA channel of ADC slave should stopped after this function with */ /* function HAL_ADC_Stop_DMA. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripherals: master and slave */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to retain a potential failing status. */ if (tmp_hal_status == HAL_OK) { /* Check if ADC are effectively disabled */ if ((ADC_Disable(hadc) != HAL_ERROR) && (ADC_Disable(&tmphadcSlave) != HAL_ERROR) ) { tmp_hal_status = HAL_OK; /* Change ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { /* In case of error, attempt to disable ADC instances anyway */ ADC_Disable(hadc); ADC_Disable(&tmphadcSlave); /* Update ADC state machine (ADC master) to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); } } /* Conversion on ADC group regular group is stopped, but ADC is not */ /* disabled since conversion on ADC group injected is still on going. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @brief Injected conversion complete callback in non blocking mode * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file */ } #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Injected context queue overflow flag callback. * @note This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts). * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } /** * @brief Analog watchdog 2 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow2Callback must be implemented in the user file. */ } /** * @brief Analog watchdog 3 callback in non blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOoutOfWindow3Callback must be implemented in the user file. */ } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ /** * @} */ /** @defgroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions * @brief ADC Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure channels on injected group (+) Configure multimode (+) Configure the analog watchdog @endverbatim * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Configures the the selected channel to be linked to the regular * group. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * The recommended sampling time is at least: * - For devices STM32F37x: 17.1us for temperature sensor * - For the other STM32F3 devices: 2.2us for each of channels * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into regular group, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". * @param hadc ADC handle * @param sConfig Structure ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpOffsetShifted; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); /* Verification of channel number: Channels 1 to 14 are available in */ /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */ /* single-ended mode. */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { assert_param(IS_ADC_CHANNEL(sConfig->Channel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) { /* Regular sequence configuration */ /* For Rank 1 to 4U */ if (sConfig->Rank < 5U) { MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 5 to 9U */ else if (sConfig->Rank < 10U) { MODIFY_REG(hadc->Instance->SQR2, ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 10 to 14U */ else if (sConfig->Rank < 15U) { MODIFY_REG(hadc->Instance->SQR3 , ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 15 to 16U */ else { MODIFY_REG(hadc->Instance->SQR4 , ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank) , ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) ); } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { /* Channel sampling time configuration */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset in function of the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */ /* to 0. */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); /* Configure the selected offset register: */ /* - Enable offset */ /* - Set channel number */ /* - Set offset value */ switch (sConfig->OffsetNumber) { case ADC_OFFSET_1: /* Configure offset register 1U */ MODIFY_REG(hadc->Instance->OFR1 , ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 , ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; case ADC_OFFSET_2: /* Configure offset register 2U */ MODIFY_REG(hadc->Instance->OFR2 , ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 , ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; case ADC_OFFSET_3: /* Configure offset register 3U */ MODIFY_REG(hadc->Instance->OFR3 , ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 , ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; case ADC_OFFSET_4: /* Configure offset register 4U */ MODIFY_REG(hadc->Instance->OFR4 , ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 , ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted ); break; /* Case ADC_OFFSET_NONE */ default : /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */ /* enabled. If this is the case, offset OFRx is disabled. */ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) { /* Disable offset OFR1*/ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) { /* Disable offset OFR2*/ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) { /* Disable offset OFR3*/ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) { /* Disable offset OFR4*/ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); } break; } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Configuration of differential mode */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { /* Disable differential mode (default mode: single-ended) */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); } else { /* Enable differential mode */ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel)); /* Channel sampling time configuration (channel ADC_INx +1 */ /* corresponding to differential negative input). */ /* For channels 10 to 18U */ if (sConfig->Channel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel +1U) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel +1U) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP0, sConfig->Channel +1U) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel +1U) ); } } /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || ( (sConfig->Channel == ADC_CHANNEL_VBAT) && (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) ) { /* Configuration of common ADC parameters (continuation) */ /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && ( (tmphadcSharingSameCommonRegister.Instance == NULL) || (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) { /* If Channel_16 is selected, enable Temp. sensor measurement path */ /* Note: Temp. sensor internal channels available on ADC1 only */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) { SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } } /* If Channel_17 is selected, enable VBAT measurement path */ /* Note: VBAT internal channels available on ADC1 only */ else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); } /* If Channel_18 is selected, enable VREFINT measurement path */ /* Note: VrefInt internal channels available on all ADCs, but only */ /* one ADC is allowed to be connected to VrefInt at the same */ /* time. */ else if (sConfig->Channel == ADC_CHANNEL_VREFINT) { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); } } /* If the requested internal measurement path has already been */ /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } } } /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Configures the the selected channel to be linked to the regular * group. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * The recommended sampling time is at least: * - For devices STM32F37x: 17.1us for temperature sensor * - For the other STM32F3 devices: 2.2us for each of channels * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into regular group, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_ChannelConfTypeDef". * @param hadc ADC handle * @param sConfig Structure of ADC channel for regular group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); /* Process locked */ __HAL_LOCK(hadc); /* Regular sequence configuration */ /* For Rank 1 to 6U */ if (sConfig->Rank < 7U) { MODIFY_REG(hadc->Instance->SQR3 , ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12U */ else if (sConfig->Rank < 13U) { MODIFY_REG(hadc->Instance->SQR2 , ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 13 to 16U */ else { MODIFY_REG(hadc->Instance->SQR1 , ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) , ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); } /* Channel sampling time configuration */ /* For channels 10 to 18U */ if (sConfig->Channel > ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); } else /* For channels 0 to 9U */ { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) , ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT) ) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } } } /* if ADC1 Channel_18 is selected, enable VBAT measurement path */ else if (sConfig->Channel == ADC_CHANNEL_VBAT) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Configures the ADC injected group and the selected channel to be * linked to the injected group. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InjectionConfTypeDef". * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * The recommended sampling time is at least: * - For devices STM32F37x: 17.1us for temperature sensor * - For the other STM32F3 devices: 2.2us for each of channels * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can * be used. * @note Caution: For Injected Context Queue use: a context must be fully * defined before start of injected conversion: all channels configured * consecutively for the same ADC instance. Therefore, Number of calls of * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter * InjectedNbrOfConversion for each context. * - Example 1: If 1 context intended to be used (or not use of this feature: * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be * called once for each channel (3 times) before launching a conversion. * This function must not be called to configure the 4th injected channel: * it would start a new context into context queue. * - Example 2: If 2 contexts intended to be used and usage of the 3 first * injected ranks (InjectedNbrOfConversion=3), * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and * for each context (3 channels x 2 contexts = 6 calls). Conversion can * start once the 1st context is set. The 2nd context can be set on the fly. * @param hadc ADC handle * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; uint32_t tmpOffsetShifted; __IO uint32_t wait_loop_index = 0U; /* Injected context queue feature: temporary JSQR variables defined in */ /* static to be passed over calls of this function */ uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } /* Verification of channel number: Channels 1 to 14 are available in */ /* differential mode. Channels 15U, 16U, 17U, 18 can be used only in */ /* single-ended mode. */ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of Injected group sequencer. */ /* Hardware constraint: Must fully define injected context register JSQR */ /* before make it entering into injected sequencer queue. */ /* */ /* - if scan mode is disabled: */ /* * Injected channels sequence length is set to 0x00: 1 channel */ /* converted (channel on injected rank 1U) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* * Injected context register JSQR setting is simple: register is fully */ /* defined on one call of this function (for injected rank 1U) and can */ /* be entered into queue directly. */ /* - if scan mode is enabled: */ /* * Injected channels sequence length is set to parameter */ /* "InjectedNbrOfConversion". */ /* * Injected context register JSQR setting more complex: register is */ /* fully defined over successive calls of this function, for each */ /* injected channel rank. It is entered into queue only when all */ /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || (sConfigInjected->InjectedNbrOfConversion == 1U) ) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ /* (scan mode disabled, only rank 1 used) */ /* - external trigger to start conversion */ /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) | ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) | sConfigInjected->ExternalTrigInjecConvEdge ); } else { SET_BIT(tmp_JSQR_ContextQueueBeingBuilt, ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); } /* Update ADC register JSQR */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | ADC_JSQR_JEXTEN | ADC_JSQR_JEXTSEL | ADC_JSQR_JL , tmp_JSQR_ContextQueueBeingBuilt ); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } else { /* Case of scan mode enabled, several channels to set into injected group */ /* sequencer. */ /* Procedure to define injected context register JSQR over successive */ /* calls of this function, for each injected channel rank: */ /* 1. Start new context and set parameters related to all injected */ /* channels: injected sequence length and trigger */ if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion; /* Initialize value that will be set into register JSQR */ hadc->InjectionConfig.ContextQueue = 0x00000000U; /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ /* - external trigger to start conversion */ /* - external trigger polarity */ /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) | ADC_JSQR_JEXTSEL_SET(hadc, sConfigInjected->ExternalTrigInjecConv) | sConfigInjected->ExternalTrigInjecConvEdge ); } else { SET_BIT(hadc->InjectionConfig.ContextQueue, (sConfigInjected->InjectedNbrOfConversion - 1U) ); } } /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Set the JSQx bits for the selected rank */ MODIFY_REG(hadc->InjectionConfig.ContextQueue , ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank) , ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank) ); /* Decrease channel count after setting into temporary JSQR variable */ hadc->InjectionConfig.ChannelCount --; /* 3. End of context setting: If last channel set, then write context */ /* into register JSQR and make it enter into queue */ if (hadc->InjectionConfig.ChannelCount == 0U) { /* Update ADC register JSQR */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | ADC_JSQR_JEXTEN | ADC_JSQR_JEXTSEL | ADC_JSQR_JL , hadc->InjectionConfig.ContextQueue ); } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on injected group: */ /* - Injected context queue: Queue disable (active context is kept) or */ /* enable (context decremented, up to 2 contexts queued) */ /* - Injected discontinuous mode: can be enabled only if auto-injected */ /* mode is disabled. */ if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) { /* If auto-injected mode is disabled: no constraint */ if (sConfigInjected->AutoInjectedConv == DISABLE) { MODIFY_REG(hadc->Instance->CFGR , ADC_CFGR_JQM | ADC_CFGR_JDISCEN , ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode) ); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { MODIFY_REG(hadc->Instance->CFGR , ADC_CFGR_JQM | ADC_CFGR_JDISCEN , ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) ); /* If injected discontinuous mode was intended to be set and could not */ /* due to auto-injected enabled, error is reported. */ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Automatic injected conversion: can be enabled if injected group */ /* external triggers are disabled. */ /* - Channel sampling time */ /* - Channel offset */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) { MODIFY_REG(hadc->Instance->CFGR , ADC_CFGR_JAUTO , ADC_CFGR_INJECT_AUTO_CONVERSION((uint32_t)sConfigInjected->AutoInjectedConv) ); } /* If Automatic injected conversion was intended to be set and could not */ /* due to injected group external triggers enabled, error is reported. */ else { /* Disable Automatic injected conversion */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); if (sConfigInjected->AutoInjectedConv == ENABLE) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Channel sampling time configuration */ /* For channels 10 to 18U */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel) , ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel) , ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset in function of the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11U, the LSB (right bits) are set */ /* to 0. */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); /* Configure the selected offset register: */ /* - Enable offset */ /* - Set channel number */ /* - Set offset value */ switch (sConfigInjected->InjectedOffsetNumber) { case ADC_OFFSET_1: /* Configure offset register 1U */ MODIFY_REG(hadc->Instance->OFR1 , ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 , ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted ); break; case ADC_OFFSET_2: /* Configure offset register 2U */ MODIFY_REG(hadc->Instance->OFR2 , ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 , ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted ); break; case ADC_OFFSET_3: /* Configure offset register 3U */ MODIFY_REG(hadc->Instance->OFR3 , ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 , ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted ); break; case ADC_OFFSET_4: /* Configure offset register 4U */ MODIFY_REG(hadc->Instance->OFR4 , ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 , ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted ); break; /* Case ADC_OFFSET_NONE */ default : /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is */ /* enabled. If this is the case, offset OFRx is disabled. */ if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) { /* Disable offset OFR1*/ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN); } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) { /* Disable offset OFR2*/ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) { /* Disable offset OFR3*/ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel)) { /* Disable offset OFR4*/ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); } break; } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Configuration of differential mode */ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { /* Disable differential mode (default mode: single-ended) */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel)); } else { /* Enable differential mode */ SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel)); /* Channel sampling time configuration (channel ADC_INx +1 */ /* corresponding to differential negative input). */ /* For channels 10 to 18U */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel +1U), ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) ); } else /* For channels 1 to 9U */ { MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel +1U), ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel +1U) ); } } /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_deInit(). */ /* Configuration of common ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) || ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) || ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN))) ) { /* Configuration of common ADC parameters (continuation) */ /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if ((ADC_IS_ENABLE(hadc) == RESET) && ( (tmphadcSharingSameCommonRegister.Instance == NULL) || (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) ) { /* If Channel_16 is selected, enable Temp. sensor measurement path */ /* Note: Temp. sensor internal channels available on ADC1 only */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1)) { SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN); /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } } /* If Channel_17 is selected, enable VBAT measurement path */ /* Note: VBAT internal channels available on ADC1 only */ else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1)) { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN); } /* If Channel_18 is selected, enable VREFINT measurement path */ /* Note: VrefInt internal channels available on all ADCs, but only */ /* one ADC is allowed to be connected to VrefInt at the same */ /* time. */ else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) { SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN); } } /* If the requested internal measurement path has already been enabled */ /* and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Configures the ADC injected group and the selected channel to be * linked to the injected group. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. * The setting of these parameters is conditioned to ADC state: * this function must be called when ADC is not under conversion. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * The recommended sampling time is at least: * - For devices STM32F37x: 17.1us for temperature sensor * - For the other STM32F3 devices: 2.2us for each of channels * Vbat/VrefInt/TempSensor. * These internal paths can be be disabled using function * HAL_ADC_DeInit(). * @param hadc ADC handle * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* - if scan mode is disabled, injected channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1U) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, injected channels sequence length is set to */ /* parameter "InjectedNbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) { if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Clear the old SQx bits for all injected ranks */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 , ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1, 0x01U) ); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } else { /* Since injected channels rank conv. order depends on total number of */ /* injected conversions, selected rank must be below or equal to total */ /* number of injected conversions to be updated. */ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) { /* Clear the old SQx bits for the selected rank */ /* Set the SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) ); } else { /* Clear the old SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , 0x00000000 ); } } /* Configuration of injected group */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - external trigger to start conversion */ /* Parameters update not conditioned to ADC state: */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Note: In case of ADC already enabled, caution to not launch an unwanted */ /* conversion while modifying register CR2 by writing 1 to bit ADON. */ if (ADC_IS_ENABLE(hadc) == RESET) { MODIFY_REG(hadc->Instance->CR2 , ADC_CR2_JEXTSEL | ADC_CR2_ADON , sConfigInjected->ExternalTrigInjecConv ); } /* Configuration of injected group */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Automatic injected conversion can be enabled if injected group */ /* external triggers are disabled. */ if (sConfigInjected->AutoInjectedConv == ENABLE) { if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* Injected discontinuous can be enabled only if auto-injected mode is */ /* disabled. */ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) { if (sConfigInjected->AutoInjectedConv == DISABLE) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } } /* InjectedChannel sampling time configuration */ /* For channels 10 to 18 */ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1, ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel), ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } else /* For channels 1 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2, ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel), ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ switch(sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset); break; case 2: /* Set injected channel 2 offset */ MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset); break; case 3: /* Set injected channel 3 offset */ MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset); break; case 4: default: MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset); break; } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } } } } /* if ADC1 Channel_18 is selected, enable VBAT measurement path */ else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Configures the analog watchdog. * @note Possibility to update parameters on the fly: * This function initializes the selected analog watchdog, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". * @param hadc ADC handle * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpAWDHighThresholdShifted; uint32_t tmpAWDLowThresholdShifted; uint32_t tmpADCFlagAWD2orAWD3; uint32_t tmpADCITAWD2orAWD3; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); /* Verify if threshold is within the selected ADC resolution */ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) { assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Analog watchdog channels */ /* - Analog watchdog thresholds */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) { /* Analog watchdogs configuration */ if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: regular and/or injected */ /* groups, one or overall group of channels. */ /* - Set the Analog watchdog channel (is not used if watchdog */ /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */ MODIFY_REG(hadc->Instance->CFGR , ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH , AnalogWDGConfig->WatchdogMode | ADC_CFGR_AWD1CH_SHIFT(AnalogWDGConfig->Channel) ); /* Shift the offset in function of the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11U, the LSB (right bits) */ /* are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); /* Set the high and low thresholds */ MODIFY_REG(hadc->Instance->TR1 , ADC_TR1_HT1 | ADC_TR1_LT1 , ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); /* Clear the ADC Analog watchdog flag (in case of left enabled by */ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ /* or HAL_ADC_PollForEvent(). */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1); /* Configure ADC Analog watchdog interrupt */ if(AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1); } else { /* Disable the ADC Analog watchdog interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1); } } /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ else { /* Shift the threshold in function of the selected ADC resolution */ /* have to be left-aligned on bit 7U, the LSB (right bits) are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Set the Analog watchdog channel or group of channels. This also */ /* enables the watchdog. */ /* Note: Conditional register reset, because several channels can be */ /* set by successive calls of this function. */ if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) { /* Set the high and low thresholds */ MODIFY_REG(hadc->Instance->TR2 , ADC_TR2_HT2 | ADC_TR2_LT2 , ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel)); } else { CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); } /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ /* settings. */ tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2; tmpADCITAWD2orAWD3 = ADC_IT_AWD2; } /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { /* Set the Analog watchdog channel or group of channels. This also */ /* enables the watchdog. */ /* Note: Conditionnal register reset, because several channels can be */ /* set by successive calls of this function. */ if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) { /* Set the high and low thresholds */ MODIFY_REG(hadc->Instance->TR3 , ADC_TR3_HT3 | ADC_TR3_LT3 , ADC_TRX_HIGHTHRESHOLD(tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted ); SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel)); } else { CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); } /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */ /* settings. */ tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3; tmpADCITAWD2orAWD3 = ADC_IT_AWD3; } /* Clear the ADC Analog watchdog flag (in case of left enabled by */ /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */ /* or HAL_ADC_PollForEvent(). */ __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3); /* Configure ADC Analog watchdog interrupt */ if(AnalogWDGConfig->ITMode == ENABLE) { __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3); } else { __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3); } } } /* If a conversion is on going on regular or injected groups, no update */ /* could be done on neither of the AWD configuration structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Configures the analog watchdog. * @note Analog watchdog thresholds can be modified while ADC conversion * is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next * ADC EOC (end of unitary conversion). * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc ADC handle * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) { assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Analog watchdog configuration */ /* Configure ADC Analog watchdog interrupt */ if(AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); } else { /* Disable the ADC Analog watchdog interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); } /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: regular and/or injected groups, */ /* one or all channels. */ /* - Set the Analog watchdog channel (is not used if watchdog */ /* mode "all channels": ADC_CFGR_AWD1SGL=0U). */ MODIFY_REG(hadc->Instance->CR1 , ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDCH , AnalogWDGConfig->WatchdogMode | AnalogWDGConfig->Channel ); /* Set the high threshold */ WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); /* Set the low threshold */ WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: * This function initializes multimode parameters, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_MultiModeTypeDef" on the fly, without reseting * the ADCs (both ADCs of the common group). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To change back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSharingSameCommonRegister; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MODE(multimode->Mode)); if(multimode->Mode != ADC_MODE_INDEPENDENT) { assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Set handle of the other ADC sharing the same common register */ ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister); if (tmphadcSharingSameCommonRegister.Instance == NULL) { /* Return function status */ return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSharingSameCommonRegister) == RESET) ) { /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */ /* control registers) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* If multimode is selected, configure all multimode paramaters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if(multimode->Mode != ADC_MODE_INDEPENDENT) { /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */ /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */ /* - DMA access mode */ MODIFY_REG(tmpADC_Common->CCR , ADC_CCR_MDMA | ADC_CCR_DMACFG , multimode->DMAAccessMode | ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) ); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Set delay between two sampling phases */ /* Note: Delay range depends on selected resolution: */ /* from 1 to 12 clock cycles for 12 bits */ /* from 1 to 10 clock cycles for 10 bits, */ /* from 1 to 8 clock cycles for 8 bits */ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clamped to maximum delay */ /* range */ /* Note: If ADC is not in the appropriate state to modify these */ /* parameters, their setting is bypassed without error reporting */ /* (as it can be the expected behaviour in case of intended action */ /* to update parameter above (which fulfills the ADC state */ /* condition: no conversion on going on group regular) */ /* on the fly). */ if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) { MODIFY_REG(tmpADC_Common->CCR , ADC_CCR_MULTI | ADC_CCR_DELAY , multimode->Mode | multimode->TwoSamplingDelay ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if ((ADC_IS_ENABLE(hadc) == RESET) && (ADC_IS_ENABLE(&tmphadcSharingSameCommonRegister) == RESET) ) { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MULTI | ADC_CCR_DELAY); } } } /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F328xx || STM32F334x8 */ /** * @} */ /** * @} */ /** @defgroup ADCEx_Private_Functions ADCEx Private Functions * @{ */ /** * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F3 devices, in case of sequencer enabled */ /* (several ranks selected), end of conversion flag is raised */ /* at the end of the sequence. */ if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } /** * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback * @param hdma pointer to DMA handle. * @retval None */ static void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Check if conditions to enable the ADC are fulfilled */ if (ADC_ENABLING_CONDITIONS(hadc) == RESET) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } /** * @brief Disable the selected ADC. * @note Prerequisite condition to use this function: ADC conversions must be * stopped. * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0U; /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if (ADC_IS_ENABLE(hadc) != RESET ) { /* Check if conditions to disable the ADC are fulfilled */ if (ADC_DISABLING_CONDITIONS(hadc) != RESET) { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } /* Wait for ADC effectively disabled */ tickstart = HAL_GetTick(); while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } /** * @brief Stop ADC conversion. * @param hadc ADC handle * @param ConversionGroup ADC group regular and/or injected. * This parameter can be one of the following values: * @arg ADC_REGULAR_GROUP: ADC regular conversion type. * @arg ADC_INJECTED_GROUP: ADC injected conversion type. * @arg ADC_REGULAR_INJECTED_GROUP: ADC regular and injected conversion type. * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) { uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0U; uint32_t tickstart = 0U; uint32_t Conversion_Timeout_CPU_cycles = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) { /* Particular case of continuous auto-injection mode combined with */ /* auto-delay mode. */ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1U, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) && (hadc->Init.ContinuousConvMode==ENABLE) && (hadc->Init.LowPowerAutoWait==ENABLE) ) { /* Use stop of regular group */ ConversionGroup = ADC_REGULAR_GROUP; /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET) { if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4U)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } Conversion_Timeout_CPU_cycles ++; } /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); } /* Stop potential conversion on going on regular group */ if (ConversionGroup != ADC_INJECTED_GROUP) { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0U */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) { /* Stop conversions on regular group */ hadc->Instance->CR |= ADC_CR_ADSTP; } } /* Stop potential conversion on going on injected group */ if (ConversionGroup != ADC_REGULAR_GROUP) { /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0U */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) { /* Stop conversions on injected group */ hadc->Instance->CR |= ADC_CR_JADSTP; } } /* Selection of start and stop bits in function of regular or injected group */ switch(ConversionGroup) { case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); break; case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; break; /* Case ADC_REGULAR_GROUP */ default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; break; } /* Wait for conversion effectively stopped */ tickstart = HAL_GetTick(); while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET) { if((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0U; __IO uint32_t wait_loop_index = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); while(wait_loop_index != 0U) { wait_loop_index--; } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively enabled */ while(ADC_IS_ENABLE(hadc) == RESET) { if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } /** * @brief Stop ADC conversion and disable the selected ADC * @param hadc ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0U; /* Verification if ADC is not already disabled: */ if (ADC_IS_ENABLE(hadc) != RESET) { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); /* Get tick count */ tickstart = HAL_GetTick(); /* Wait for ADC effectively disabled */ while(ADC_IS_ENABLE(hadc) != RESET) { if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } /* Return HAL status */ return HAL_OK; } #endif /* STM32F373xC || STM32F378xx */ /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_cortex.c * @author MCD Application Team * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: * + Initialization and de-initialization functions * + Peripheral Control functions * * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== [..] This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the sub priority. -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest pre-emption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) [..] *** How to configure Systick using CORTEX HAL driver *** ======================================================== [..] Setup SysTick Timer for time base (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. (++) Configures the SysTick IRQ priority to the lowest value (0x0FU). (++) Resets the SysTick Counter register. (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined inside the stm32f3xx_hal_cortex.h file. (+) You can change the SysTick IRQ priority by calling the HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Additional Tables: CORTEX_NVIC_Priority_Table The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function ========================================================================================================================== NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ========================================================================================================================== NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | 0 bits for pre-emption priority | | | 4 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | 1 bits for pre-emption priority | | | 3 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | 3 bits for pre-emption priority | | | 1 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | 4 bits for pre-emption priority | | | 0 bits for subpriority ========================================================================================================================== */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup CORTEX CORTEX * @brief CORTEX CORTEX HAL module driver * @{ */ #ifdef HAL_CORTEX_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions * @{ */ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides the CORTEX HAL driver functions allowing to configure Interrupts Systick functionalities @endverbatim * @{ */ /** * @brief Sets the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority * 0 bits for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } /** * @brief Sets the priority of an interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @param PreemptPriority The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table * A lower priority value indicates a higher priority * @param SubPriority the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t prioritygroup = 0x00U; /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } /** * @brief Disables a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } /** * @brief Initiates a system reset request to reset the MCU. * @retval None */ void HAL_NVIC_SystemReset(void) { /* System Reset */ NVIC_SystemReset(); } /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } /** * @} */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions * @brief Cortex control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX (NVIC, SYSTICK, MPU) functionalities. @endverbatim * @{ */ #if (__MPU_PRESENT == 1U) /** * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation) * @retval None */ void HAL_MPU_Disable(void) { /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable the MPU */ MPU->CTRL = 0U; } /** * @brief Enables the MPU * @param MPU_Control Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; } /** * @brief Initializes and configures the Region and the memory to be protected. * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; if ((MPU_Init->Enable) != RESET) { /* Check the parameters */ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); MPU->RBAR = MPU_Init->BaseAddress; MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } else { MPU->RBAR = 0x00U; MPU->RASR = 0x00U; } } #endif /* __MPU_PRESENT */ /** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) */ uint32_t HAL_NVIC_GetPriorityGrouping(void) { /* Get the PRIGROUP[10:8] field value */ return NVIC_GetPriorityGrouping(); } /** * @brief Gets the priority of an interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority * 0 bits for subpriority * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). * @param pSubPriority Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Get priority for Cortex-M system or device specific interrupts */ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); } /** * @brief Sets Pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { /* Return 1 if pending else 0U */ return NVIC_GetPendingIRQ(IRQn); } /** * @brief Clears the pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } /** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) { /* Return 1 if active else 0U */ return NVIC_GetActive(IRQn); } /** * @brief Configures the SysTick clock source. * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); if (CLKSource == SYSTICK_CLKSOURCE_HCLK) { SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; } else { SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; } } /** * @brief This function handles SYSTICK interrupt request. * @retval None */ void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); } /** * @brief SYSTICK callback. * @retval None */ __weak void HAL_SYSTICK_Callback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SYSTICK_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_CORTEX_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_dma.c * @author MCD Application Team * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is necessary). Please refer to Reference manual for connection between peripherals and DMA requests . (#) For a given Channel, program the required configuration through the following parameters: Transfer Direction, Source and Destination data formats, Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, using HAL_DMA_Init() function. (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. (#) Use HAL_DMA_Abort() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** ================================= [..] (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. *** Interrupt mode IO operation *** =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. In this case the DMA interrupt is configured (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function by customization of function pointer XferCpltCallback and XferErrorCallback (i.e a member of DMA handle structure). *** DMA HAL driver macros list *** ============================================= [..] Below the list of most used macros in DMA HAL driver. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup DMA DMA * @brief DMA HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup DMA_Exported_Functions DMA Exported Functions * @{ */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in reference manual. @endverbatim * @{ */ /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0U; /* Check the DMA handle allocation */ if(NULL == hdma) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; /* Initialize DmaBaseAddress and ChannelIndex parameters used by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ DMA_CalcBaseAndBitshift(hdma); /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; return HAL_OK; } /** * @brief DeInitialize the DMA peripheral * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if(NULL == hdma) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ hdma->Instance->CCR &= ~DMA_CCR_EN; /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0U; /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0U; /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0U; /* Get DMA Base Address */ DMA_CalcBaseAndBitshift(hdma); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; /* Clean callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; /* Reset the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Reset the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions * @brief I/O operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete (+) Handle DMA interrupt request @endverbatim * @{ */ /** * @brief Start the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ hdma->Instance->CCR &= ~DMA_CCR_EN; /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ hdma->Instance->CCR |= DMA_CCR_EN; } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; } return status; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ hdma->Instance->CCR &= ~DMA_CCR_EN; /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete, & transfer error interrupts */ /* Half transfer interrupt is optional: enable it only if associated callback is available */ if(NULL != hdma->XferHalfCpltCallback ) { hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); } else { hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); hdma->Instance->CCR &= ~DMA_IT_HT; } /* Enable the Peripheral */ hdma->Instance->CCR |= DMA_CCR_EN; } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; } return status; } /** * @brief Abort the DMA Transfer. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { if(hdma->State != HAL_DMA_STATE_BUSY) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } else { /* Disable DMA IT */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); /* Disable the channel */ hdma->Instance->CCR &= ~DMA_CCR_EN; /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); } /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @brief Abort the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); /* Disable the channel */ hdma->Instance->CCR &= ~DMA_CCR_EN; /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } } return status; } /** * @brief Polling for transfer complete. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CompleteLevel Specifies the DMA level complete. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart = 0U; if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Polling mode not supported in circular mode */ if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } /* Get the level transfer complete flag */ if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Transfer Complete flag */ temp = DMA_FLAG_TC1 << hdma->ChannelIndex; } else { /* Half Transfer Complete flag */ temp = DMA_FLAG_HT1 << hdma->ChannelIndex; } /* Get tick */ tickstart = HAL_GetTick(); while(RESET == (hdma->DmaBaseAddress->ISR & temp)) { if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State= HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } } } if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; } /* Process unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @brief Handle DMA interrupt request. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the half transfer interrupt */ hdma->Instance->CCR &= ~DMA_IT_HT; } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; /* DMA peripheral state is not updated in Half Transfer */ /* State is updated only in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); } } /* Transfer Complete Interrupt management ***********************************/ else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) { if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the transfer complete & transfer error interrupts */ /* if the DMA mode is not CIRCULAR */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; /* Process Unlocked */ __HAL_UNLOCK(hdma); if(hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } } /* Transfer Error Interrupt management ***************************************/ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Then, disable all DMA interrupts */ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); if(hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } } /** * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if(HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = pCallback; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = pCallback; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = pCallback; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = pCallback; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if(HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; break; case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions * @brief Peripheral State functions * @verbatim =============================================================================== ##### State and Errors functions ##### =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state (+) Get error code @endverbatim * @{ */ /** * @brief Returns the DMA state. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { return hdma->State; } /** * @brief Return the DMA error code * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup DMA_Private_Functions * @{ */ /** * @brief Set the DMA Transfer parameters. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } /* Memory to Peripheral */ else { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } /** * @brief Set the DMA base address and channel index depending on DMA instance * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { #if defined (DMA2) /* calculation of the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; hdma->DmaBaseAddress = DMA2; } #else /* calculation of the channel index */ /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; hdma->DmaBaseAddress = DMA1; #endif } /** * @} */ /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_exti.c * @author MCD Application Team * @brief EXTI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: * + Initialization and de-initialization functions * + IO operation functions * @verbatim ============================================================================== ##### EXTI Peripheral features ##### ============================================================================== [..] (+) Each Exti line can be configured within this driver. (+) Exti line can be configured in 3 different modes (++) Interrupt (++) Event (++) Both of them (+) Configurable Exti lines can be configured with 3 different triggers (++) Rising (++) Falling (++) Both of them (+) When set in interrupt mode, configurable Exti lines have two different interrupts pending registers which allow to distinguish which transition occurs: (++) Rising edge pending interrupt (++) Falling (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can be selected through multiplexer. ##### How to use this driver ##### ============================================================================== [..] (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). (++) Choose the interrupt line number by setting "Line" member from EXTI_ConfigTypeDef structure. (++) Configure the interrupt and/or event mode using "Mode" member from EXTI_ConfigTypeDef structure. (++) For configurable lines, configure rising and/or falling trigger "Trigger" member from EXTI_ConfigTypeDef structure. (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" member from GPIO_InitTypeDef structure. (#) Get current Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). (++) Provide exiting handle as first parameter. (++) Provide which callback will be registered using one value from EXTI_CallbackIDTypeDef. (++) Provide callback function pointer. (#) Get interrupt pending bit using HAL_EXTI_GetPending(). (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @addtogroup EXTI * @{ */ /** MISRA C:2012 deviation rule has been granted for following rule: * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out * of bounds [0,3] in following API : * HAL_EXTI_SetConfigLine * HAL_EXTI_GetConfigLine * HAL_EXTI_ClearConfigLine */ #ifdef HAL_EXTI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ #define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between CPU IMR/EMR registers */ #define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup EXTI_Exported_Functions * @{ */ /** @addtogroup EXTI_Exported_Functions_Group1 * @brief Configuration functions * @verbatim =============================================================================== ##### Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Set configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on EXTI configuration to be set. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_EXTI_LINE(pExtiConfig->Line)); assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); /* Assign line number to handle */ hexti->Line = pExtiConfig->Line; /* Compute line register offset and line mask */ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); linepos = (pExtiConfig->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* Configure triggers for configurable lines */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); /* Configure rising trigger */ regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store rising trigger mode */ *regaddr = regval; /* Configure falling trigger */ regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store falling trigger mode */ *regaddr = regval; /* Configure gpio port selection in case of gpio exti line */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); SYSCFG->EXTICR[linepos >> 2u] = regval; } } /* Configure interrupt mode : read current mode */ regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store interrupt mode */ *regaddr = regval; /* Configure event mode : read current mode */ regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store event mode */ *regaddr = regval; return HAL_OK; } /** * @brief Get configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on structure to store Exti configuration. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* Store handle line number to configuration structure */ pExtiConfig->Line = hexti->Line; /* compute line register offset and line mask */ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); linepos = (pExtiConfig->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* 1] Get core mode : interrupt */ regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Check if selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Mode = EXTI_MODE_INTERRUPT; } else { pExtiConfig->Mode = EXTI_MODE_NONE; } /* Get event mode */ regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Check if selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Mode |= EXTI_MODE_EVENT; } /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } else { pExtiConfig->Trigger = EXTI_TRIGGER_NONE; } /* Get falling configuration */ regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; } /* Get Gpio port selection for gpio lines */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); } else { pExtiConfig->GPIOSel = 0x00u; } } else { /* No Trigger selected */ pExtiConfig->Trigger = EXTI_TRIGGER_NONE; pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; } /** * @brief Clear whole configuration of a dedicated Exti line. * @param hexti Exti handle. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* compute line register offset and line mask */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); linepos = (hexti->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* 1] Clear interrupt mode */ regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* 2] Clear event mode */ regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* 3] Clear triggers in case of configurable lines */ if ((hexti->Line & EXTI_CONFIG) != 0x00u) { regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* Get Gpio port selection for gpio lines */ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); SYSCFG->EXTICR[linepos >> 2u] = regval; } } return HAL_OK; } /** * @brief Register callback for a dedicated Exti line. * @param hexti Exti handle. * @param CallbackID User callback identifier. * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. * @param pPendingCbfn function pointer to be stored as callback. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) { HAL_StatusTypeDef status = HAL_OK; switch (CallbackID) { case HAL_EXTI_COMMON_CB_ID: hexti->PendingCallback = pPendingCbfn; break; default: status = HAL_ERROR; break; } return status; } /** * @brief Store line number as handle private field. * @param hexti Exti handle. * @param ExtiLine Exti line number. * This parameter can be from 0 to @ref EXTI_LINE_NB. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) { /* Check the parameters */ assert_param(IS_EXTI_LINE(ExtiLine)); /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } else { /* Store line number as handle private field */ hexti->Line = ExtiLine; return HAL_OK; } } /** * @} */ /** @addtogroup EXTI_Exported_Functions_Group2 * @brief EXTI IO functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Handle EXTI interrupt request. * @param hexti Exti handle. * @retval none. */ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; uint32_t maskline; uint32_t offset; /* Compute line register offset and line mask */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Get pending bit */ regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & maskline); if (regval != 0x00u) { /* Clear pending bit */ EXTI->PR = maskline; /* Call callback */ if (hexti->PendingCallback != NULL) { hexti->PendingCallback(); } } } /** * @brief Get interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge Specify which pending edge as to be checked. * This parameter can be one of the following values: * @arg @ref EXTI_TRIGGER_RISING_FALLING * This parameter is kept for compatibility with other series. * @retval 1 if interrupt is pending else 0. */ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); assert_param(IS_EXTI_PENDING_EDGE(Edge)); /* compute line register offset and line mask */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); linepos = (hexti->Line & EXTI_PIN_MASK); maskline = (1uL << linepos); /* Get pending bit */ regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); /* return 1 if bit is set else 0 */ regval = ((*regaddr & maskline) >> linepos); return regval; } /** * @brief Clear interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge Specify which pending edge as to be clear. * This parameter can be one of the following values: * @arg @ref EXTI_TRIGGER_RISING_FALLING * This parameter is kept for compatibility with other series. * @retval None. */ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; uint32_t offset; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); assert_param(IS_EXTI_PENDING_EDGE(Edge)); /* compute line register offset and line mask */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Get pending bit */ regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); /* Clear Pending bit */ *regaddr = maskline; } /** * @brief Generate a software interrupt for a dedicated line. * @param hexti Exti handle. * @retval None. */ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; uint32_t offset; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); /* compute line register offset and line mask */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); regaddr = (&EXTI->SWIER + (EXTI_CONFIG_OFFSET * offset)); *regaddr = maskline; } /** * @} */ /** * @} */ #endif /* HAL_EXTI_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_flash.c * @author MCD Application Team * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions * + Memory Control functions * + Peripheral State functions * @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. [..] The FLASH main features are: (+) Flash memory read operations (+) Flash memory program/erase operations (+) Read / write protections (+) Prefetch on I-Code (+) Option Bytes programming ##### How to use this driver ##### ============================================================================== [..] This driver provides functions and macros to configure and program the FLASH memory of all STM32F3xx devices. (#) FLASH Memory I/O Programming functions: this group includes all needed functions to erase and program the main memory: (++) Lock and Unlock the FLASH interface (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes (++) Set/Reset the write protection (++) Set the Read protection Level (++) Program the user Option Bytes (++) Launch the Option Bytes loader (++) Erase Option Bytes (++) Program the data Option Bytes (++) Get the Write protection. (++) Get the user option bytes. (#) Interrupts and flags management functions : this group includes all needed functions to: (++) Handle FLASH interrupts (++) Wait for last FLASH operation according to its status (++) Get error flag status [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: (+) Set/Get the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the half cycle access (+) Enable/Disable the FLASH interrupts (+) Monitor the FLASH flags status @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /** @defgroup FLASH FLASH * @brief FLASH HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ /** * @} */ /* Private macro ---------------------------- ---------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables * @{ */ /* Variables used for Erase pages under interruption*/ FLASH_ProcessTypeDef pFlash; /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions * @{ */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); static void FLASH_SetErrorCode(void); extern void FLASH_PageErase(uint32_t PageAddress); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions * @brief Programming operation functions * @verbatim @endverbatim * @{ */ /** * @brief Program halfword, word or double word at a specified address * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @note FLASH should be previously erased before new programming (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address Specifie the address to be programmed. * @param Data Specifie the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_ERROR; uint8_t index = 0U; uint8_t nbiterations = 0U; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { /* Program halfword (16-bit) at a specified address. */ nbiterations = 1U; } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { /* Program word (32-bit = 2*16-bit) at a specified address. */ nbiterations = 2U; } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ nbiterations = 4U; } for (index = 0U; index < nbiterations; index++) { FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); /* In case of error, stop programming procedure */ if (status != HAL_OK) { break; } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Program halfword, word or double word at a specified address with interrupt enabled. * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address Specifie the address to be programmed. * @param Data Specifie the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); pFlash.Address = Address; pFlash.Data = Data; if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; /* Program halfword (16-bit) at a specified address. */ pFlash.DataRemaining = 1U; } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; /* Program word (32-bit : 2*16-bit) at a specified address. */ pFlash.DataRemaining = 2U; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; /* Program double word (64-bit : 4*16-bit) at a specified address. */ pFlash.DataRemaining = 4U; } /* Program halfword (16-bit) at a specified address. */ FLASH_Program_HalfWord(Address, (uint16_t)Data); return status; } /** * @brief This function handles FLASH interrupt request. * @retval None */ void HAL_FLASH_IRQHandler(void) { uint32_t addresstmp = 0U; /* Check FLASH operation error flags */ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { /* Return the faulty address */ addresstmp = pFlash.Address; /* Reset address */ pFlash.Address = 0xFFFFFFFFU; /* Save the Error code */ FLASH_SetErrorCode(); /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(addresstmp); /* Stop the procedure ongoing */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } /* Check FLASH End of Operation flag */ if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); /* Process can continue only if no error detected */ if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) { /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; /* Check if there are still pages to erase */ if(pFlash.DataRemaining != 0U) { addresstmp = pFlash.Address; /*Indicate user which sector has been erased */ HAL_FLASH_EndOfOperationCallback(addresstmp); /*Increment sector number*/ addresstmp = pFlash.Address + FLASH_PAGE_SIZE; pFlash.Address = addresstmp; /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); FLASH_PageErase(addresstmp); } else { /* No more pages to Erase, user callback can be called. */ /* Reset Sector and stop Erase pages procedure */ pFlash.Address = addresstmp = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(addresstmp); } } else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) { /* Operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(0U); /* Stop Mass Erase procedure*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } else { /* Nb of 16-bit data to program can be decreased */ pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ if(pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); /*Program halfword (16-bit) at a specified address.*/ FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); } else { /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address); } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); } else { HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); } /* Reset Address and stop Program procedure */ pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } } } if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { /* Operation is completed, disable the PG, PER and MER Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); /* Disable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } } /** * @brief FLASH end of operation interrupt callback * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file */ } /** * @brief FLASH operation error interrupt callback * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * - Mass Erase: No return value expected * - Pages Erase: Address of the page which returned an error * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions * @brief management functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim * @{ */ /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* Verify Flash is unlocked */ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { status = HAL_ERROR; } } return status; } /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); return HAL_OK; } /** * @brief Unlock the FLASH Option Control Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); } else { return HAL_ERROR; } return HAL_OK; } /** * @brief Lock the FLASH Option Control Registers access. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); return HAL_OK; } /** * @brief Launch the option byte loading. * @note This function will reset automatically the MCU. * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { /* Set the OBL_Launch bit to launch the option byte loading */ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); /* Wait for last operation to be completed */ return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions * @brief Peripheral errors functions * @verbatim =============================================================================== ##### Peripheral Errors functions ##### =============================================================================== [..] This subsection permit to get in run-time errors of the FLASH peripheral. @endverbatim * @{ */ /** * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode The returned value can be: * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Program a half-word (16-bit) at a specified address. * @param Address specify the address to be programmed. * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Proceed to program the new data */ SET_BIT(FLASH->CR, FLASH_CR_PG); /* Write data in the address */ *(__IO uint16_t*)Address = Data; } /** * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { if (Timeout != HAL_MAX_DELAY) { if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { return HAL_TIMEOUT; } } } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { /*Save the error code*/ FLASH_SetErrorCode(); return HAL_ERROR; } /* There is no error flag set */ return HAL_OK; } /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { uint32_t flags = 0U; if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; flags |= FLASH_FLAG_WRPERR; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) { pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; flags |= FLASH_FLAG_PGERR; } /* Clear FLASH error pending bits */ __HAL_FLASH_CLEAR_FLAG(flags); } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_flash_ex.c * @author MCD Application Team * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + Extended Initialization/de-initialization functions * + Extended I/O operation functions * + Extended Peripheral Control functions * @verbatim ============================================================================== ##### Flash peripheral extended features ##### ============================================================================== ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the FLASH memory of all STM32F3xxx devices. It includes (++) Set/Reset the write protection (++) Program the user Option Bytes (++) Get the Read protection Level @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Variables * @{ */ /* Variables used for Erase pages under interruption*/ extern FLASH_ProcessTypeDef pFlash; /** * @} */ /** * @} */ /** @defgroup FLASHEx FLASHEx * @brief FLASH HAL Extension module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants * @{ */ #define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW) #define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0) #define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1) /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ /* Erase operations */ static void FLASH_MassErase(void); void FLASH_PageErase(uint32_t PageAddress); /* Option bytes control */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); static uint32_t FLASH_OB_GetWRP(void); static uint32_t FLASH_OB_GetRDP(void); static uint8_t FLASH_OB_GetUser(void); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions * @brief FLASH Memory Erasing functions * @verbatim ============================================================================== ##### FLASH Erasing Programming functions ##### ============================================================================== [..] The FLASH Memory Erasing functions, includes the following functions: (+) @ref HAL_FLASHEx_Erase: return only when erase has been done (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter 0xFFFFFFFF [..] Any operation of erase should follow these steps: (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and program memory access. (#) Call the desired function to erase page. (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access (recommended to protect the FLASH memory against possible unwanted operation). @endverbatim * @{ */ /** * @brief Perform a mass erase or erase the specified FLASH memory pages * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @param[out] PageError pointer to variable that * contains the configuration information on faulty page in case of error * (0xFFFFFFFF means that all the pages have been correctly erased) * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status = HAL_ERROR; uint32_t address = 0U; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /* Mass Erase requested for Bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Mass erase to be done*/ FLASH_MassErase(); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the MER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_MER); } } else { /* Page Erase is requested */ /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); /* Page Erase requested on address located on bank1 */ /* Wait for last operation to be completed */ if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); address += FLASH_PAGE_SIZE) { FLASH_PageErase(address); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PER); if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty address */ *PageError = address; break; } } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function * must be called before. * Call the @ref HAL_FLASH_Lock() to disable the flash memory access * (recommended to protect the FLASH memory against possible unwanted operation) * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* If procedure already ongoing, reject the next one */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; FLASH_MassErase(); } else { /* Erase by page to be done*/ /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; pFlash.DataRemaining = pEraseInit->NbPages; pFlash.Address = pEraseInit->PageAddress; /*Erase 1st page and wait for IT*/ FLASH_PageErase(pEraseInit->PageAddress); } return status; } /** * @} */ /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions * @brief Option Bytes Programming functions * @verbatim ============================================================================== ##### Option Bytes Programming functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH option bytes operations. @endverbatim * @{ */ /** * @brief Erases the FLASH option bytes. * @note This functions erases all option bytes except the Read protection (RDP). * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * @retval HAL status */ HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) { uint8_t rdptmp = OB_RDP_LEVEL_0; HAL_StatusTypeDef status = HAL_ERROR; /* Get the actual read protection Option Byte value */ rdptmp = FLASH_OB_GetRDP(); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the OPTER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); if(status == HAL_OK) { /* Restore the last read protection Option Byte value */ status = FLASH_OB_RDP_LevelConfig(rdptmp); } } /* Return the erase status */ return status; } /** * @brief Program option bytes * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /* Write protection configuration */ if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) { assert_param(IS_WRPSTATE(pOBInit->WRPState)); if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) { /* Enable of Write protection on the selected page */ status = FLASH_OB_EnableWRP(pOBInit->WRPPage); } else { /* Disable of Write protection on the selected page */ status = FLASH_OB_DisableWRP(pOBInit->WRPPage); } if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* Read protection configuration */ if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) { status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* USER configuration */ if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) { status = FLASH_OB_UserConfig(pOBInit->USERConfig); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* DATA configuration*/ if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) { status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Get the Option byte configuration * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; /*Get WRP*/ pOBInit->WRPPage = FLASH_OB_GetWRP(); /*Get RDP Level*/ pOBInit->RDPLevel = FLASH_OB_GetRDP(); /*Get USER*/ pOBInit->USERConfig = FLASH_OB_GetUser(); } /** * @brief Get the Option byte user data * @param DATAAdress Address of the option byte DATA * This parameter can be one of the following values: * @arg @ref OB_DATA_ADDRESS_DATA0 * @arg @ref OB_DATA_ADDRESS_DATA1 * @retval Value programmed in USER data */ uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) { uint32_t value = 0U; if (DATAAdress == OB_DATA_ADDRESS_DATA0) { /* Get value programmed in OB USER Data0 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; } else { /* Get value programmed in OB USER Data1 */ value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; } return value; } /** * @} */ /** * @} */ /** @addtogroup FLASHEx_Private_Functions * @{ */ /** * @brief Full erase of FLASH memory Bank * * @retval None */ static void FLASH_MassErase(void) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); SET_BIT(FLASH->CR, FLASH_CR_STRT); } /** * @brief Enable the write protection of the desired pages * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage specifies the page(s) to be write protected. * The value of this parameter depend on device used within the same series * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; uint16_t WRP0_Data = 0xFFFFU; #if defined(OB_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFFU; #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) uint16_t WRP2_Data = 0xFFFFU; #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFFU; #endif /* OB_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); /* Get current write protected pages and the new pages to be protected ******/ WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES48TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #endif /* OB_WRP_PAGES48TO63MASK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); if (status == HAL_OK) { /* Enable write protection */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(OB_WRP0_WRP0) if(WRP0_Data != 0xFFU) { OB->WRP0 &= WRP0_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP0_WRP0 */ #if defined(OB_WRP1_WRP1) if((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 &= WRP1_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) if((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 &= WRP2_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) if((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 &= WRP3_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP3_WRP3 */ /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Disable the write protection of the desired pages * @note An option byte erase is done automatically in this function. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash page i if * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * * @param WriteProtectPage specifies the page(s) to be write unprotected. * The value of this parameter depend on device used within the same series * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) { HAL_StatusTypeDef status = HAL_OK; uint16_t WRP0_Data = 0xFFFFU; #if defined(OB_WRP1_WRP1) uint16_t WRP1_Data = 0xFFFFU; #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) uint16_t WRP2_Data = 0xFFFFU; #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) uint16_t WRP3_Data = 0xFFFFU; #endif /* OB_WRP3_WRP3 */ /* Check the parameters */ assert_param(IS_OB_WRP(WriteProtectPage)); /* Get current write protected pages and the new pages to be unprotected ******/ WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); #if defined(OB_WRP_PAGES0TO15MASK) WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES32TO47MASK) WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES48TO127MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #endif /* OB_WRP_PAGES48TO63MASK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* To be able to write again option byte, need to perform a option byte erase */ status = HAL_FLASHEx_OBErase(); if (status == HAL_OK) { SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(OB_WRP0_WRP0) if(WRP0_Data != 0xFFU) { OB->WRP0 |= WRP0_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP0_WRP0 */ #if defined(OB_WRP1_WRP1) if((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 |= WRP1_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP1_WRP1 */ #if defined(OB_WRP2_WRP2) if((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 |= WRP2_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP2_WRP2 */ #if defined(OB_WRP3_WRP3) if((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 |= WRP3_Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } #endif /* OB_WRP3_WRP3 */ /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Set the read protection level. * @param ReadProtectLevel specifies the read protection level. * This parameter can be one of the following values: * @arg @ref OB_RDP_LEVEL_0 No protection * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory * @arg @ref OB_RDP_LEVEL_2 Full chip protection * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* If the previous operation is completed, proceed to erase the option bytes */ SET_BIT(FLASH->CR, FLASH_CR_OPTER); SET_BIT(FLASH->CR, FLASH_CR_STRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the OPTER Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); if(status == HAL_OK) { /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); WRITE_REG(OB->RDP, ReadProtectLevel); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } } return status; } /** * @brief Program the FLASH User Option Byte. * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET))); #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enable the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) OB->USER = (UserConfig | 0x08U); #else OB->USER = (UserConfig | 0x88U); #endif /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* if the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } return status; } /** * @brief Programs a half word at a specified Option Byte Data address. * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes * (system reset will occur) * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) * @param Address specifies the address to be programmed. * This parameter can be 0x1FFFF804 or 0x1FFFF806. * @param Data specifies the data to be programmed. * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) { HAL_StatusTypeDef status = HAL_ERROR; /* Check the parameters */ assert_param(IS_OB_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Enables the Option Bytes Programming operation */ SET_BIT(FLASH->CR, FLASH_CR_OPTPG); *(__IO uint16_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the OPTPG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); } /* Return the Option Byte Data Program Status */ return status; } /** * @brief Return the FLASH Write Protection Option Bytes value. * @retval The FLASH Write Protection Option Bytes value */ static uint32_t FLASH_OB_GetWRP(void) { /* Return the FLASH write protection Register value */ return (uint32_t)(READ_REG(FLASH->WRPR)); } /** * @brief Returns the FLASH Read Protection level. * @retval FLASH RDP level * This parameter can be one of the following values: * @arg @ref OB_RDP_LEVEL_0 No protection * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory * @arg @ref OB_RDP_LEVEL_2 Full chip protection */ static uint32_t FLASH_OB_GetRDP(void) { uint32_t tmp_reg = 0U; /* Read RDP level bits */ #if defined(FLASH_OBR_RDPRT) tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); #elif defined(FLASH_OBR_LEVEL1_PROT) tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT)); #endif /* FLASH_OBR_RDPRT */ #if defined(FLASH_OBR_RDPRT) if (tmp_reg == FLASH_OBR_RDPRT_2) #elif defined(FLASH_OBR_LEVEL1_PROT) if (tmp_reg == FLASH_OBR_LEVEL2_PROT) #endif /* FLASH_OBR_RDPRT */ { return OB_RDP_LEVEL_2; } else if (tmp_reg == 0U) { return OB_RDP_LEVEL_0; } else { return OB_RDP_LEVEL_1; } } /** * @brief Return the FLASH User Option Byte value. * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nBOOT1(Bit4), * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . */ static uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); } /** * @} */ /** * @} */ /** @addtogroup FLASH * @{ */ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Erase the specified FLASH memory page * @param PageAddress FLASH page to erase * The value of this parameter depend on device used within the same series * * @retval None */ void FLASH_PageErase(uint32_t PageAddress) { /* Clean the error context */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Proceed to erase the page */ SET_BIT(FLASH->CR, FLASH_CR_PER); WRITE_REG(FLASH->AR, PageAddress); SET_BIT(FLASH->CR, FLASH_CR_STRT); } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_gpio.c * @author MCD Application Team * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions * @verbatim ============================================================================== ##### GPIO Peripheral features ##### ============================================================================== [..] (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: (++) Input mode (++) Analog mode (++) Output mode (++) Alternate function mode (++) External interrupt/event lines (+) During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. (+) The microcontroller IO pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an IO pin at a time. In this way, there can be no conflict between peripherals sharing the same IO pin. (+) All ports have external interrupt/event capability. To use external interrupt lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. (+) The external interrupt/event controller consists of up to 23 edge detectors (16 lines are connected to GPIO) for generating event/interrupt requests (each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also be masked independently. ##### How to use this driver ##### ============================================================================== [..] (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure. (++) In alternate mode is selection, the alternate function connected to the IO is configured through "Alternate" member from GPIO_InitTypeDef structure. (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. (++) In case of external interrupt/event selection the "Mode" member from GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general purpose PF0 and PF1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup GPIO GPIO * @brief GPIO HAL module driver * @{ */ /** MISRA C:2012 deviation rule has been granted for following rules: * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] * which may be out of array bounds [..,UNKNOWN] in following APIs: * HAL_GPIO_Init * HAL_GPIO_DeInit */ #ifdef HAL_GPIO_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup GPIO_Private_Defines GPIO Private Defines * @{ */ #define GPIO_MODE (0x00000003U) #define EXTI_MODE (0x10000000U) #define GPIO_MODE_IT (0x00010000U) #define GPIO_MODE_EVT (0x00020000U) #define RISING_EDGE (0x00100000U) #define FALLING_EDGE (0x00200000U) #define GPIO_OUTPUT_TYPE (0x00000010U) #define GPIO_NUMBER (16U) /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Functions GPIO Exported Functions * @{ */ /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0x00u; uint32_t iocurrent; uint32_t temp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; temp &= ~(0xFu << ((position & 0x07u) * 4u)); temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); GPIOx->AFR[position >> 3u] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); GPIOx->MODER = temp; /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); temp |= (GPIO_Init->Speed << (position * 2u)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT_0 << position) ; temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); GPIOx->OTYPER = temp; } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); temp |= ((GPIO_Init->Pull) << (position * 2u)); GPIOx->PUPDR = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2u]; temp &= ~(0x0FuL << (4u * (position & 0x03u))); temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); SYSCFG->EXTICR[position >> 2u] = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR; temp &= ~(iocurrent); if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) { temp |= iocurrent; } EXTI->IMR = temp; temp = EXTI->EMR; temp &= ~(iocurrent); if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) { temp |= iocurrent; } EXTI->EMR = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; temp &= ~(iocurrent); if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) { temp |= iocurrent; } EXTI->RTSR = temp; temp = EXTI->FTSR; temp &= ~(iocurrent); if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) { temp |= iocurrent; } EXTI->FTSR = temp; } } position++; } } /** * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { uint32_t position = 0x00u; uint32_t iocurrent; uint32_t tmp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0x00u) { /* Get current io position */ iocurrent = (GPIO_Pin) & (1uL << position); if (iocurrent != 0x00u) { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = SYSCFG->EXTICR[position >> 2u]; tmp &= (0x0FuL << (4u * (position & 0x03u))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) { /* Clear EXTI line configuration */ EXTI->IMR &= ~((uint32_t)iocurrent); EXTI->EMR &= ~((uint32_t)iocurrent); /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~((uint32_t)iocurrent); EXTI->FTSR &= ~((uint32_t)iocurrent); /* Configure the External Interrupt or event for the current IO */ tmp = 0x0FuL << (4u * (position & 0x03u)); SYSCFG->EXTICR[position >> 2u] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO Direction in Input Floating Mode */ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ; /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); } position++; } } /** * @} */ /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Read the specified input port pin. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) { bitstatus = GPIO_PIN_SET; } else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } /** * @brief Set or clear the selected data port bit. * * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) { GPIOx->BSRR = (uint32_t)GPIO_Pin; } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } /** * @brief Toggle the specified GPIO pin. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family * @param GPIO_Pin specifies the pin to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->ODR & GPIO_Pin) != 0X00u) { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } else { GPIOx->BSRR = (uint32_t)GPIO_Pin; } } /** * @brief Lock GPIO Pins configuration registers. * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family * @param GPIO_Pin specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { __IO uint32_t tmp = GPIO_LCKR_LCKK; /* Check the parameters */ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Apply lock key write sequence */ tmp |= GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ GPIOx->LCKR = tmp; /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */ GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ GPIOx->LCKR = tmp; /* Read LCKK register. This read is mandatory to complete key lock sequence */ tmp = GPIOx->LCKR; /* read again in order to confirm lock is active */ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) { return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } } /** * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* Prevent unused argument(s) compilation warning */ UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_GPIO_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_i2c.c * @author MCD Application Team * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The I2C HAL driver can be used as follows: (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs (+++) Configure I2C pins as alternate function open-drain (##) NVIC configuration if you need to use interrupt process (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel (##) DMA Configuration if you need to use DMA process (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx channel (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode or DMA mode IO sequential operation *** ========================================================== [..] (@) These interfaces allow to manage a sequential transfer with a repeated start condition when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call the same master sequential interface several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and without a final stop condition in both cases (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and with a final stop condition in both cases (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit without stopping the communication and so generate a restart condition. (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential interface. Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. (+) Differents sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() or using @ref HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() or using @ref HAL_I2C_Slave_Seq_Receive_DMA() (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using @ref HAL_I2C_Mem_Write_IT() (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using @ref HAL_I2C_Mem_Read_IT() (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Master_Transmit_DMA() (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Master_Receive_DMA() (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Slave_Transmit_DMA() (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Slave_Receive_DMA() (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using @ref HAL_I2C_Mem_Write_DMA() (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using @ref HAL_I2C_Mem_Read_DMA() (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** ================================== [..] Below the list of most used macros in I2C HAL driver. (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() to register an interrupt callback. [..] Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. (+) ListenCpltCallback : callback for end of listen mode. (+) MemTxCpltCallback : callback for Memory transmission end of transfer. (+) MemRxCpltCallback : callback for Memory reception end of transfer. (+) ErrorCallback : callback for error detection. (+) AbortCpltCallback : callback for abort completion process. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). [..] Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. (+) ListenCpltCallback : callback for end of listen mode. (+) MemTxCpltCallback : callback for Memory transmission end of transfer. (+) MemRxCpltCallback : callback for Memory reception end of transfer. (+) ErrorCallback : callback for error detection. (+) AbortCpltCallback : callback for abort completion process. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). [..] By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when these callbacks are null (not registered beforehand). If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() or @ref HAL_I2C_Init() function. [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. [..] (@) You can refer to the I2C HAL driver header file for more useful macros @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup I2C I2C * @brief I2C HAL module driver * @{ */ #ifdef HAL_I2C_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup I2C_Private_Define I2C Private Define * @{ */ #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U #define SlaveAddr_SHIFT 7U #define SlaveAddr_MSK 0x06U /* Private define for @ref PreviousState usage */ #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ #define I2C_XFER_TX_IT (0x00000001U) #define I2C_XFER_RX_IT (0x00000002U) #define I2C_XFER_LISTEN_IT (0x00000004U) #define I2C_XFER_ERROR_IT (0x00000011U) #define I2C_XFER_CPLT_IT (0x00000012U) #define I2C_XFER_RELOAD_IT (0x00000012U) /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ /* Private functions to handle DMA transfer */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); /* Private functions to handle IT transfer */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); /* Private function to handle start, restart or stop a transfer */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup I2C_Exported_Functions I2C Exported Functions * @{ */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize and deinitialize the I2Cx peripheral: (+) User must Implement HAL_I2C_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). (+) Call the function HAL_I2C_Init() to configure the selected device with the selected configuration: (++) Clock Timing (++) Own Address 1 (++) Addressing mode (Master, Slave) (++) Dual Addressing mode (++) Own Address 2 (++) Own Address 2 Mask (++) General call mode (++) Nostretch mode (+) Call the function HAL_I2C_DeInit() to restore the default configuration of the selected I2Cx peripheral. @endverbatim * @{ */ /** * @brief Initializes the I2C according to the specified parameters * in the I2C_InitTypeDef and initialize the associated handle. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ if (hi2c == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) /* Init the I2C Callback settings */ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ if (hi2c->MspInitCallback == NULL) { hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { hi2c->Instance->CR2 = (I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; return HAL_OK; } /** * @brief DeInitialize the I2C peripheral. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) { /* Check the I2C handle allocation */ if (hi2c == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); hi2c->State = HAL_I2C_STATE_BUSY; /* Disable the I2C Peripheral Clock */ __HAL_I2C_DISABLE(hi2c); #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) if (hi2c->MspDeInitCallback == NULL) { hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ } /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ hi2c->MspDeInitCallback(hi2c); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_I2C_MspDeInit(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_RESET; hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; /* Release Lock */ __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Initialize the I2C MSP. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspInit could be implemented in the user file */ } /** * @brief DeInitialize the I2C MSP. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MspDeInit could be implemented in the user file */ } #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) /** * @brief Register a User I2C Callback * To be used instead of the weak predefined callback * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { switch (CallbackID) { case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : hi2c->MasterTxCpltCallback = pCallback; break; case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : hi2c->MasterRxCpltCallback = pCallback; break; case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : hi2c->SlaveTxCpltCallback = pCallback; break; case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : hi2c->SlaveRxCpltCallback = pCallback; break; case HAL_I2C_LISTEN_COMPLETE_CB_ID : hi2c->ListenCpltCallback = pCallback; break; case HAL_I2C_MEM_TX_COMPLETE_CB_ID : hi2c->MemTxCpltCallback = pCallback; break; case HAL_I2C_MEM_RX_COMPLETE_CB_ID : hi2c->MemRxCpltCallback = pCallback; break; case HAL_I2C_ERROR_CB_ID : hi2c->ErrorCallback = pCallback; break; case HAL_I2C_ABORT_CB_ID : hi2c->AbortCpltCallback = pCallback; break; case HAL_I2C_MSPINIT_CB_ID : hi2c->MspInitCallback = pCallback; break; case HAL_I2C_MSPDEINIT_CB_ID : hi2c->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_I2C_STATE_RESET == hi2c->State) { switch (CallbackID) { case HAL_I2C_MSPINIT_CB_ID : hi2c->MspInitCallback = pCallback; break; case HAL_I2C_MSPDEINIT_CB_ID : hi2c->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hi2c); return status; } /** * @brief Unregister an I2C Callback * I2C callback is redirected to the weak predefined callback * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * This parameter can be one of the following values: * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { switch (CallbackID) { case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ break; case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ break; case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ break; case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ break; case HAL_I2C_LISTEN_COMPLETE_CB_ID : hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ break; case HAL_I2C_MEM_TX_COMPLETE_CB_ID : hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ break; case HAL_I2C_MEM_RX_COMPLETE_CB_ID : hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ break; case HAL_I2C_ERROR_CB_ID : hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_I2C_ABORT_CB_ID : hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_I2C_MSPINIT_CB_ID : hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ break; case HAL_I2C_MSPDEINIT_CB_ID : hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_I2C_STATE_RESET == hi2c->State) { switch (CallbackID) { case HAL_I2C_MSPINIT_CB_ID : hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ break; case HAL_I2C_MSPDEINIT_CB_ID : hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hi2c); return status; } /** * @brief Register the Slave Address Match I2C Callback * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pCallback pointer to the Address Match Callback function * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { hi2c->AddrCallback = pCallback; } else { /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hi2c); return status; } /** * @brief UnRegister the Slave Address Match I2C Callback * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ } else { /* Update the error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hi2c); return status; } #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions * @brief Data transfers functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the I2C data transfers. (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. The end of the data processing will be indicated through the dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. (#) Blocking mode functions are : (++) HAL_I2C_Master_Transmit() (++) HAL_I2C_Master_Receive() (++) HAL_I2C_Slave_Transmit() (++) HAL_I2C_Slave_Receive() (++) HAL_I2C_Mem_Write() (++) HAL_I2C_Mem_Read() (++) HAL_I2C_IsDeviceReady() (#) No-Blocking mode functions with Interrupt are : (++) HAL_I2C_Master_Transmit_IT() (++) HAL_I2C_Master_Receive_IT() (++) HAL_I2C_Slave_Transmit_IT() (++) HAL_I2C_Slave_Receive_IT() (++) HAL_I2C_Mem_Write_IT() (++) HAL_I2C_Mem_Read_IT() (++) HAL_I2C_Master_Seq_Transmit_IT() (++) HAL_I2C_Master_Seq_Receive_IT() (++) HAL_I2C_Slave_Seq_Transmit_IT() (++) HAL_I2C_Slave_Seq_Receive_IT() (++) HAL_I2C_EnableListen_IT() (++) HAL_I2C_DisableListen_IT() (++) HAL_I2C_Master_Abort_IT() (#) No-Blocking mode functions with DMA are : (++) HAL_I2C_Master_Transmit_DMA() (++) HAL_I2C_Master_Receive_DMA() (++) HAL_I2C_Slave_Transmit_DMA() (++) HAL_I2C_Slave_Receive_DMA() (++) HAL_I2C_Mem_Write_DMA() (++) HAL_I2C_Mem_Read_DMA() (++) HAL_I2C_Master_Seq_Transmit_DMA() (++) HAL_I2C_Master_Seq_Receive_DMA() (++) HAL_I2C_Slave_Seq_Transmit_DMA() (++) HAL_I2C_Slave_Seq_Receive_DMA() (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_I2C_MasterTxCpltCallback() (++) HAL_I2C_MasterRxCpltCallback() (++) HAL_I2C_SlaveTxCpltCallback() (++) HAL_I2C_SlaveRxCpltCallback() (++) HAL_I2C_MemTxCpltCallback() (++) HAL_I2C_MemRxCpltCallback() (++) HAL_I2C_AddrCallback() (++) HAL_I2C_ListenCpltCallback() (++) HAL_I2C_ErrorCallback() (++) HAL_I2C_AbortCpltCallback() @endverbatim * @{ */ /** * @brief Transmits in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferCount--; hi2c->XferSize--; if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receives in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferSize--; hi2c->XferCount--; if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Transmits in slave mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* If 10bit addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Wait until DIR flag is set Transmitter mode */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } while (hi2c->XferCount > 0U) { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferCount--; } /* Wait until STOP flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Normal use case for Transmitter mode */ /* A NACK is generated to confirm the end of transfer */ hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } else { return HAL_ERROR; } } /* Clear STOP flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive in slave mode an amount of data in blocking mode * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Wait until ADDR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Wait until DIR flag is reset Receiver mode */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } while (hi2c->XferCount > 0U) { /* Wait until RXNE flag is set */ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Store Last receive data if any */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferCount--; } return HAL_ERROR; } /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferCount--; } /* Wait until STOP flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } /* Clear STOP flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; return HAL_ERROR; } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } if (hi2c->XferSize > 0U) { if (hi2c->hdmatx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } else { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive in master mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } if (hi2c->XferSize > 0U) { if (hi2c->hdmarx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Send Slave Address */ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } else { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; if (hi2c->hdmatx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef dmaxferstatus; if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; if (hi2c->hdmarx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } do { /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferCount--; hi2c->XferSize--; if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Read an amount of data in blocking mode from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) { return HAL_ERROR; } hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferISR = NULL; /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); } do { /* Wait until RXNE flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferSize--; hi2c->XferCount--; if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_IT; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (hi2c->hdmatx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param pData Pointer to data buffer * @param Size Amount of data to be read * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if (hi2c->State == HAL_I2C_STATE_READY) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Master_ISR_DMA; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = I2C_AUTOEND_MODE; } /* Send Slave Address and Memory Address */ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (hi2c->hdmarx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Checks if target device is ready for communication. * @note This function is used with Memory devices * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param Trials Number of trials * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { uint32_t tickstart; __IO uint32_t I2C_Trials = 0UL; FlagStatus tmp1; FlagStatus tmp2; if (hi2c->State == HAL_I2C_STATE_READY) { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; do { /* Generate Start */ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ tickstart = HAL_GetTick(); tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); while ((tmp1 == RESET) && (tmp2 == RESET)) { if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); } /* Check if the NACKF flag has not been set */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) { /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Device is ready */ hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Clear STOP Flag, auto generated with autoend*/ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } /* Check if the maximum allowed number of trials has been reached */ if (I2C_Trials == Trials) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_ERROR; } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } else { return HAL_BUSY; } } /** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; } /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } else { /* Convert OTHER_xxx XferOptions if any */ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ if (hi2c->XferCount < MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } } /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Master_ISR_DMA; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; } /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } else { /* Convert OTHER_xxx XferOptions if any */ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ if (hi2c->XferCount < MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } } if (hi2c->XferSize > 0U) { if (hi2c->hdmatx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } else { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Master_ISR_IT; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; } /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } else { /* Convert OTHER_xxx XferOptions if any */ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ if (hi2c->XferCount < MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } } /* Send Slave Address and set NBYTES to read */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Master_ISR_DMA; /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; xfermode = hi2c->XferOptions; } /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } else { /* Convert OTHER_xxx XferOptions if any */ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ if (hi2c->XferCount < MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } } if (hi2c->XferSize > 0U) { if (hi2c->hdmarx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to read */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR and NACK interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } else { /* Update Transfer ISR function pointer */ hi2c->XferISR = I2C_Master_ISR_IT; /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); /* Process Locked */ __HAL_LOCK(hi2c); /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); /* Abort DMA Xfer if any */ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; if (hi2c->hdmarx != NULL) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } } } hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hi2c); /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { /* Abort DMA Xfer if any */ if (hi2c->hdmarx != NULL) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } } } else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* Abort DMA Xfer if any */ if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } } } else { /* Nothing to do */ } hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_DMA; if (hi2c->hdmatx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; /* Set the DMA error callback */ hi2c->hdmatx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmatx->XferHalfCpltCallback = NULL; hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Reset XferSize */ hi2c->XferSize = 0; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); /* Process Locked */ __HAL_LOCK(hi2c); /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* Abort DMA Xfer if any */ if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } } } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { if ((pData == NULL) || (Size == 0U)) { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; return HAL_ERROR; } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); /* Process Locked */ __HAL_LOCK(hi2c); /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { /* Abort DMA Xfer if any */ if (hi2c->hdmatx != NULL) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } } } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Abort DMA Xfer if any */ if (hi2c->hdmarx != NULL) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } } } else { /* Nothing to do */ } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_DMA; if (hi2c->hdmarx != NULL) { /* Set the I2C DMA transfer complete callback */ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; /* Set the DMA error callback */ hi2c->hdmarx->XferErrorCallback = I2C_DMAError; /* Set the unused DMA callbacks to NULL */ hi2c->hdmarx->XferHalfCpltCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (dmaxferstatus == HAL_OK) { /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Reset XferSize */ hi2c->XferSize = 0; } else { /* Update I2C state */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->Mode = HAL_I2C_MODE_NONE; /* Update I2C error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); /* Enable DMA Request */ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Enable the Address listen mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { if (hi2c->State == HAL_I2C_STATE_READY) { hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->XferISR = I2C_Slave_ISR_IT; /* Enable the Address Match interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Disable the Address listen mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) { /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp; /* Disable Address listen mode only if a transfer is not ongoing */ if (hi2c->State == HAL_I2C_STATE_LISTEN) { tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; /* Disable the Address Match interrupt */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Abort a master I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { if (hi2c->Mode == HAL_I2C_MODE_MASTER) { /* Process Locked */ __HAL_LOCK(hi2c); /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); return HAL_OK; } else { /* Wrong usage of abort function */ /* This function should be used only in case of abort monitored by master device */ return HAL_ERROR; } } /** * @} */ /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ */ /** * @brief This function handles I2C event interrupt request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) { /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); uint32_t itsources = READ_REG(hi2c->Instance->CR1); /* I2C events treatment -------------------------------------*/ if (hi2c->XferISR != NULL) { hi2c->XferISR(hi2c, itflags, itsources); } } /** * @brief This function handles I2C error interrupt request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { uint32_t itflags = READ_REG(hi2c->Instance->ISR); uint32_t itsources = READ_REG(hi2c->Instance->CR1); uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); } /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; /* Call the Error Callback in case of Error detected */ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) { I2C_ITError(hi2c, tmperror); } } /** * @brief Master Tx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ } /** * @brief Master Rx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } /** @brief Slave Tx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ } /** * @brief Slave Rx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file */ } /** * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); UNUSED(TransferDirection); UNUSED(AddrMatchCode); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AddrCallback() could be implemented in the user file */ } /** * @brief Listen Complete callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ListenCpltCallback() could be implemented in the user file */ } /** * @brief Memory Tx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemTxCpltCallback could be implemented in the user file */ } /** * @brief Memory Rx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemRxCpltCallback could be implemented in the user file */ } /** * @brief I2C error callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file */ } /** * @brief I2C abort callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AbortCpltCallback could be implemented in the user file */ } /** * @} */ /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions * @brief Peripheral State, Mode and Error functions * @verbatim =============================================================================== ##### Peripheral State, Mode and Error functions ##### =============================================================================== [..] This subsection permit to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the I2C handle state. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) { /* Return I2C handle state */ return hi2c->State; } /** * @brief Returns the I2C Master, Slave, Memory or no mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for I2C module * @retval HAL mode */ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) { return hi2c->Mode; } /** * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup I2C_Private_Functions * @{ */ /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param ITFlags Interrupt flags to handle. * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; /* Process Locked */ __HAL_LOCK(hi2c); if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set corresponding Error Code */ /* No need to generate STOP, it is automatically done */ /* Error callback will be send during stop flag treatment */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; /* Flush TX register */ I2C_Flush_TXDR(hi2c); } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferSize--; hi2c->XferCount--; } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferSize--; hi2c->XferCount--; } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); } else { I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } else { /* Call TxCpltCallback() if no stop mode is set */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Generate a stop condition in case of no transfer option */ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; } else { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); } } } else { /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } else { /* Nothing to do */ } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, tmpITFlags); } /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param ITFlags Interrupt flags to handle. * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t tmpITFlags = ITFlags; /* Process locked */ __HAL_LOCK(hi2c); /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferSize--; hi2c->XferCount--; } if ((hi2c->XferCount == 0U) && \ (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, tmpITFlags); } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Datas have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; /* Increment Buffer pointer */ hi2c->pBuffPtr++; hi2c->XferCount--; hi2c->XferSize--; } else { if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); } } } else { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param ITFlags Interrupt flags to handle. * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; /* Process Locked */ __HAL_LOCK(hi2c); if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); /* Flush TX register */ I2C_Flush_TXDR(hi2c); } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); if (hi2c->XferCount != 0U) { /* Recover Slave address */ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { xfermode = hi2c->XferOptions; } else { xfermode = I2C_AUTOEND_MODE; } } /* Set the new XferSize in Nbytes register */ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; } } else { /* Call TxCpltCallback() if no stop mode is set */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) { /* Generate a stop condition in case of no transfer option */ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; } else { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); } } } else { /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); } else { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param ITFlags Interrupt flags to handle. * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; /* Process locked */ __HAL_LOCK(hi2c); /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) { /* Split check of hdmarx, for MISRA compliance */ if (hi2c->hdmarx != NULL) { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) { if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) { treatdmanack = 1U; } } } /* Split check of hdmatx, for MISRA compliance */ if (hi2c->hdmatx != NULL) { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) { if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) { treatdmanack = 1U; } } } if (treatdmanack == 1U) { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } } } else { /* Only Clear NACK Flag, no DMA treatment is pending */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } else { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } /** * @brief Master sends target device address followed by internal memory address for write request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } return HAL_OK; } /** * @brief Master sends target device address followed by internal memory address for read request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value * in datasheet must be shifted to the left before calling the interface * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* If Memory address size is 8Bit */ if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Send LSB of Memory Address */ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } return HAL_OK; } /** * @brief I2C Address complete process callback. * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint8_t transferdirection; uint16_t slaveaddrcode; uint16_t ownadd1code; uint16_t ownadd2code; /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) { transferdirection = I2C_GET_DIR(hi2c); slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; if (hi2c->AddrEventCount == 2U) { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } else { slaveaddrcode = ownadd2code; /* Disable ADDR Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* else 7 bits addressing mode is selected */ else { /* Disable ADDR Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* Else clear address flag only */ else { /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); } } /** * @brief I2C Master sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; hi2c->XferISR = NULL; /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterTxCpltCallback(hi2c); #else HAL_I2C_MasterTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ else { hi2c->State = HAL_I2C_STATE_READY; hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; hi2c->XferISR = NULL; /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); #else HAL_I2C_MasterRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /** * @brief I2C Slave sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveRxCpltCallback(hi2c); #else HAL_I2C_SlaveRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { /* Nothing to do */ } } /** * @brief I2C Master complete process. * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Set acknowledge error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; /* Call the corresponding callback to inform upper layer of End of Transfer */ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; if (hi2c->Mode == HAL_I2C_MODE_MEM) { hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MemTxCpltCallback(hi2c); #else HAL_I2C_MemTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterTxCpltCallback(hi2c); #else HAL_I2C_MasterTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; if (hi2c->Mode == HAL_I2C_MODE_MEM) { hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MemRxCpltCallback(hi2c); #else HAL_I2C_MemRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterRxCpltCallback(hi2c); #else HAL_I2C_MasterRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } else { /* Nothing to do */ } } /** * @brief I2C Slave complete process. * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); } } else { /* Do nothing */ } /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; } } /* All data are not transferred, so set error code accordingly */ if (hi2c->XferCount != 0U) { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ if (hi2c->State == HAL_I2C_STATE_LISTEN) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); } } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ I2C_ITSlaveSeqCplt(hi2c); hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ListenCpltCallback(hi2c); #else HAL_I2C_ListenCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /* Call the corresponding callback to inform upper layer of End of Transfer */ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveRxCpltCallback(hi2c); #else HAL_I2C_SlaveRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /** * @brief I2C Listen complete process. * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { /* Reset handle parameters */ hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->PreviousState = I2C_STATE_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; /* Store Last receive data if any */ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; /* Increment Buffer pointer */ hi2c->pBuffPtr++; if ((hi2c->XferSize > 0U)) { hi2c->XferSize--; hi2c->XferCount--; /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } } /* Disable all Interrupts*/ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ListenCpltCallback(hi2c); #else HAL_I2C_ListenCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } /** * @brief I2C interrupts error process. * @param hi2c I2C handle. * @param ErrorCode Error code to handle. * @retval None */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferCount = 0U; /* Set new error code */ hi2c->ErrorCode |= ErrorCode; /* Disable Interrupts */ if ((tmpstate == HAL_I2C_STATE_LISTEN) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } } /* Abort DMA RX transfer if any */ else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; if (hi2c->hdmarx != NULL) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } } else if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AbortCpltCallback(hi2c); #else HAL_I2C_AbortCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ErrorCallback(hi2c); #else HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /** * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) { hi2c->Instance->TXDR = 0x00U; } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); } } /** * @brief DMA I2C master transmit process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* If last transfer, enable STOP interrupt */ if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); } /* else prepare a new DMA transfer and enable TCReload interrupt */ else { /* Update Buffer pointer */ hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } else { hi2c->XferSize = hi2c->XferCount; } /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } else { /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } } /** * @brief DMA I2C slave transmit process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tmpoptions = hi2c->XferOptions; if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); } else { /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ } } /** * @brief DMA I2C master receive process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* If last transfer, enable STOP interrupt */ if (hi2c->XferCount == 0U) { /* Enable STOP interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); } /* else prepare a new DMA transfer and enable TCReload interrupt */ else { /* Update Buffer pointer */ hi2c->pBuffPtr += hi2c->XferSize; /* Set the XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; } else { hi2c->XferSize = hi2c->XferCount; } /* Enable the DMA channel */ if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } else { /* Enable TC interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); } } } /** * @brief DMA I2C slave receive process complete callback. * @param hdma DMA handle * @retval None */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tmpoptions = hi2c->XferOptions; if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); } else { /* No specific action, Master fully manage the generation of STOP condition */ /* Mean that this generation can arrive at any time, at the end or during DMA process */ /* So STOP condition should be manage through Interrupt treatment */ } } /** * @brief DMA I2C communication error callback. * @param hdma DMA handle * @retval None */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); } /** * @brief DMA I2C communication abort callback * (To be called at end of DMA Abort procedure). * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ hi2c->hdmatx->XferAbortCallback = NULL; hi2c->hdmarx->XferAbortCallback = NULL; /* Check if come from abort from user */ if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AbortCpltCallback(hi2c); #else HAL_I2C_AbortCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } else { /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ErrorCallback(hi2c); #else HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } /** * @brief This function handles I2C Communication Timeout. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Flag Specifies the I2C flag to check. * @param Status The new Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } } return HAL_OK; } /** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } } return HAL_OK; } /** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } return HAL_OK; } /** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a NACK is detected */ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ return HAL_OK; } else { /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } return HAL_OK; } /** * @brief This function handles Acknowledge failed detection during an I2C Communication. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } } } /* Clear NACKF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); hi2c->ErrorCode |= HAL_I2C_ERROR_AF; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_ERROR; } return HAL_OK; } /** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hi2c I2C handle. * @param DevAddress Specifies the slave address to be programmed. * @param Size Specifies the number of bytes to be programmed. * This parameter must be a value between 0 and 255. * @param Mode New state of the I2C START condition generation. * This parameter can be one of the following values: * @arg @ref I2C_RELOAD_MODE Enable Reload mode . * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. * @param Request New state of the I2C START condition generation. * This parameter can be one of the following values: * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** * @brief Manage the enabling of Interrupts. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ (hi2c->XferISR == I2C_Slave_ISR_DMA)) { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; } } else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Enable ERR, STOP, NACK, and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } } /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); } /** * @brief Manage the disabling of Interrupts. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { uint32_t tmpisr = 0U; if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } } if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; } /* Disable interrupts only at the end */ /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); } /** * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. * @param hi2c I2C handle. * @retval None */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) { /* if user set XferOptions to I2C_OTHER_FRAME */ /* it request implicitly to generate a restart condition */ /* set XferOptions to I2C_FIRST_FRAME */ if (hi2c->XferOptions == I2C_OTHER_FRAME) { hi2c->XferOptions = I2C_FIRST_FRAME; } /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ /* it request implicitly to generate a restart condition */ /* then generate a stop condition at the end of transfer */ /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) { hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; } else { /* Nothing to do */ } } /** * @} */ #endif /* HAL_I2C_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_i2c_ex.c * @author MCD Application Team * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: * + Extended features functions * @verbatim ============================================================================== ##### I2C peripheral Extended features ##### ============================================================================== [..] Comparing to other previous devices, the I2C interface for STM32F3xx devices contains the following additional features (+) Possibility to disable or enable Analog Noise Filter (+) Use of a configured Digital Noise Filter (+) Disable or enable wakeup from Stop mode(s) (+) Disable or enable Fast Mode Plus ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure Noise Filter and Wake Up Feature (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() (#) Configure the enable or disable of I2C Wake Up Mode using the functions : (++) HAL_I2CEx_EnableWakeUp() (++) HAL_I2CEx_DisableWakeUp() (#) Configure the enable or disable of fast mode plus driving capability using the functions : (++) HAL_I2CEx_EnableFastModePlus() (++) HAL_I2CEx_DisableFastModePlus() @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup I2CEx I2CEx * @brief I2C Extended HAL module driver * @{ */ #ifdef HAL_I2C_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions * @verbatim =============================================================================== ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters (+) Configure Wake Up Feature (+) Configure Fast Mode Plus @endverbatim * @{ */ /** * @brief Configure I2C Analog noise filter. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY; /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Configure I2C Digital noise filter. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { uint32_t tmpreg; /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY; /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); /* Get the old register value */ tmpreg = hi2c->Instance->CR1; /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Enable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY; /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); /* Enable wakeup from stop mode */ hi2c->Instance->CR1 |= I2C_CR1_WUPEN; __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Disable I2C wakeup from Stop mode(s). * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) { /* Check the parameters */ assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); if (hi2c->State == HAL_I2C_STATE_READY) { /* Process Locked */ __HAL_LOCK(hi2c); hi2c->State = HAL_I2C_STATE_BUSY; /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); /* Enable wakeup from stop mode */ hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); __HAL_I2C_ENABLE(hi2c); hi2c->State = HAL_I2C_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2c); return HAL_OK; } else { return HAL_BUSY; } } /** * @brief Enable the I2C fast mode plus driving capability. * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values * @note For I2C1, fast mode plus driving capability can be enabled on all selected * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. * @note For all I2C2 pins fast mode plus driving capability can be enabled * only by using I2C_FASTMODEPLUS_I2C2 parameter. * @note For all I2C3 pins fast mode plus driving capability can be enabled * only by using I2C_FASTMODEPLUS_I2C3 parameter. * @retval None */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) { /* Check the parameter */ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); /* Enable fast mode plus driving capability for selected pin */ SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); } /** * @brief Disable the I2C fast mode plus driving capability. * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref I2CEx_FastModePlus values * @note For I2C1, fast mode plus driving capability can be disabled on all selected * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. * @note For all I2C2 pins fast mode plus driving capability can be disabled * only by using I2C_FASTMODEPLUS_I2C2 parameter. * @note For all I2C3 pins fast mode plus driving capability can be disabled * only by using I2C_FASTMODEPLUS_I2C3 parameter. * @retval None */ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) { /* Check the parameter */ assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); /* Enable SYSCFG clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); } /** * @} */ /** * @} */ #endif /* HAL_I2C_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_pwr.c * @author MCD Application Team * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization/de-initialization functions * + Peripheral Control functions * @verbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup PWR PWR * @brief PWR HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] After reset, the backup domain (RTC registers, RTC backup data registers and backup SRAM) is protected against possible unwanted write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. @endverbatim * @{ */ /** * @brief Deinitializes the PWR peripheral registers to their default reset values. * @retval None */ void HAL_PWR_DeInit(void) { __HAL_RCC_PWR_FORCE_RESET(); __HAL_RCC_PWR_RELEASE_RESET(); } /** * @brief Enables access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). * @note If the HSE divided by 32 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { SET_BIT(PWR->CR, PWR_CR_DBP); } /** * @brief Disables access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). * @note If the HSE divided by 32 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @retval None */ void HAL_PWR_DisableBkUpAccess(void) { CLEAR_BIT(PWR->CR, PWR_CR_DBP); } /** * @} */ /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== *** WakeUp pin configuration *** ================================ [..] (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is forced in input pull down configuration and is active on rising edges. (+) There are up to three WakeUp pins: (++)WakeUp Pin 1 on PA.00. (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only). (++)WakeUp Pin 3 on PE.06. *** Main and Backup Regulators configuration *** ================================================ [..] (+) When the backup domain is supplied by VDD (analog switch connected to VDD) the backup SRAM is powered from VDD which replaces the VBAT power supply to save battery life. (+) The backup SRAM is not mass erased by a tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through the Flash interface when a protection level change from level 1 to level 0 is requested. -@- Refer to the description of Read protection (RDP) in the Flash programming manual. Refer to the datasheets for more details. *** Low Power modes configuration *** ===================================== [..] The devices feature 3 low-power modes: (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices). *** Sleep mode *** ================== [..] (+) Entry: The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) functions with (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction (+) Exit: (++) Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. *** Stop mode *** ================= [..] In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. The voltage regulator can be configured either in normal or low-power mode to minimize the consumption. (+) Entry: The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) function with: (++) Main regulator ON or (++) Low Power regulator ON. (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction (+) Exit: (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, when programmed in wakeup mode (the peripheral must be programmed in wakeup mode and the corresponding interrupt vector must be enabled in the NVIC). *** Standby mode *** ==================== [..] The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for the RTC registers, RTC backup registers, backup SRAM and Standby circuitry. The voltage regulator is OFF. (+) Entry: (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. (+) Exit: (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event, a time-stamp event, or a comparator event, without depending on an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop and Standby modes (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to configure the RTC to detect the tamper or time stamp event using the HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. (+) Comparator auto-wakeup (AWU) from the Stop mode (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U) to be sensitive to to the selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using the EXTI_Init() function. (+++) Configure the comparator to generate the event. @endverbatim * @{ */ /** * @brief Enables the WakeUp PINx functionality. * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. * This parameter can be value of : * @ref PWR_WakeUp_Pins * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameters */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Enable the EWUPx pin */ SET_BIT(PWR->CSR, WakeUpPinx); } /** * @brief Disables the WakeUp PINx functionality. * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. * This parameter can be values of : * @ref PWR_WakeUp_Pins * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameters */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Disable the EWUPx pin */ CLEAR_BIT(PWR->CSR, WakeUpPinx); } /** * @brief Enters Sleep mode. * @note In Sleep mode, all I/O pins keep the same state as in Run mode. * @param Regulator Specifies the regulator state in SLEEP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON * @note This parameter has no effect in F3 family and is just maintained to * offer full portability of other STM32 families softwares. * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. * When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Check the parameters */ assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Clear SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } } /** * @brief Enters STOP mode. * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * @param Regulator Specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); /* Select the regulator state in STOP mode ---------------------------------*/ tmpreg = PWR->CR; /* Clear PDDS and LPDS bits */ tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); /* Set LPDS bit according to Regulator value */ tmpreg |= Regulator; /* Store the new value */ PWR->CR = tmpreg; /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Select STOP mode entry --------------------------------------------------*/ if(STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } /** * @brief Enters STANDBY mode. * @note In Standby mode, all I/O pins are high impedance except for: * - Reset pad (still available), * - RTC alternate function pins if configured for tamper, time-stamp, RTC * Alarm out, or RTC clock calibration out, * - WKUP pins if enabled. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) { /* Select STANDBY mode */ PWR->CR |= PWR_CR_PDDS; /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) { /* Set SLEEPONEXIT bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) { /* Clear SLEEPONEXIT bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Enables CORTEX M4 SEVONPEND bit. * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_EnableSEVOnPend(void) { /* Set SEVONPEND bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief Disables CORTEX M4 SEVONPEND bit. * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) { /* Clear SEVONPEND bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_pwr_ex.c * @author MCD Application Team * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions * ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup PWREx PWREx * @brief PWREx HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup PWREx_Private_Constants PWR Extended Private Constants * @{ */ #define PVD_MODE_IT (0x00010000U) #define PVD_MODE_EVT (0x00020000U) #define PVD_RISING_EDGE (0x00000001U) #define PVD_FALLING_EDGE (0x00000002U) /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Extended control functions ##### =============================================================================== *** PVD configuration (present on all other devices than STM32F3x8 devices) *** ========================= [..] (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro (+) The PVD is stopped in Standby mode. -@- PVD is not available on STM32F3x8 Product Line *** Voltage regulator *** ========================= [..] (+) The voltage regulator is always enabled after Reset. It works in three different modes. In Run mode, the regulator supplies full power to the 1.8V domain (core, memories and digital peripherals). In Stop mode, the regulator supplies low power to the 1.8V domain, preserving contents of registers and SRAM. In Stop mode, the regulator is powered off. The contents of the registers and SRAM are lost except for the Standby circuitry and the Backup Domain. Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage. (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro (+) The PVD is stopped in Standby mode. *** SDADC power configuration *** ================================ [..] (+) On STM32F373xC/STM32F378xx devices, there are up to 3 SDADC instances that can be enabled/disabled. @endverbatim * @{ */ #if defined(STM32F302xE) || defined(STM32F303xE) || \ defined(STM32F302xC) || defined(STM32F303xC) || \ defined(STM32F303x8) || defined(STM32F334x8) || \ defined(STM32F301x8) || defined(STM32F302x8) || \ defined(STM32F373xC) /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each * detection level. * @retval None */ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); /* Configure interrupt mode */ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } } /** * @brief Enables the Power Voltage Detector(PVD). * @retval None */ void HAL_PWR_EnablePVD(void) { SET_BIT(PWR->CR, PWR_CR_PVDE); } /** * @brief Disables the Power Voltage Detector(PVD). * @retval None */ void HAL_PWR_DisablePVD(void) { CLEAR_BIT(PWR->CR, PWR_CR_PVDE); } /** * @brief This function handles the PWR PVD interrupt request. * @note This API should be called under the PVD_IRQHandler(). * @retval None */ void HAL_PWR_PVD_IRQHandler(void) { /* Check PWR exti flag */ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); /* Clear PWR Exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } } /** * @brief PWR PVD interrupt callback * @retval None */ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PWR_PVDCallback could be implemented in the user file */ } #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F303x8 || STM32F334x8 || */ /* STM32F301x8 || STM32F302x8 || */ /* STM32F373xC */ #if defined(STM32F373xC) || defined(STM32F378xx) /** * @brief Enables the SDADC peripheral functionaliy * @param Analogx specifies the SDADC peripheral instance. * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. * @retval None */ void HAL_PWREx_EnableSDADC(uint32_t Analogx) { /* Check the parameters */ assert_param(IS_PWR_SDADC_ANALOG(Analogx)); /* Enable PWR clock interface for SDADC use */ __HAL_RCC_PWR_CLK_ENABLE(); PWR->CR |= Analogx; } /** * @brief Disables the SDADC peripheral functionaliy * @param Analogx specifies the SDADC peripheral instance. * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. * @retval None */ void HAL_PWREx_DisableSDADC(uint32_t Analogx) { /* Check the parameters */ assert_param(IS_PWR_SDADC_ANALOG(Analogx)); PWR->CR &= ~Analogx; } #endif /* STM32F373xC || STM32F378xx */ /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_rcc.c * @author MCD Application Team * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== [..] After reset the device is running from Internal High Speed oscillator (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals whose clocks are not derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS) ##### RCC Limitations ##### ============================================================================== [..] A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (++) AHB & APB peripherals, 1 dummy read is necessary [..] Workarounds: (#) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup RCC RCC * @brief RCC HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ /* Bits position in in the CFGR register */ #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE) #define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1) #define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2) /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO1_GPIO_PORT GPIOA #define MCO1_PIN GPIO_PIN_8 /** * @} */ /* Private variables ---------------------------------------------------------*/ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ */ const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ /** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ */ /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through the PLL as System clock source. The HSI clock can be used also to clock the USART and I2C peripherals. (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC clock source. (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring different output clocks: (++) The first output is used to generate the high speed system clock (up to 72 MHz) (++) The second output is used to generate the clock for the USB FS (48 MHz) (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz) (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz) (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clocks automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL clock (divided by 2) output on pin (such as PA8 pin). [..] System, AHB and APB buses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these buses. You can use "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: (++) The FLASH program/erase clock which is always HSI 8MHz clock. (++) The USB 48 MHz clock which is derived from the PLL VCO clock. (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. (++) The I2C clock which can be derived as well from HSI 8MHz clock. (++) The ADC clock which is derived from PLL output. (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE divided by a programmable prescaler). The System clock (SYSCLK) frequency must be higher or equal to the RTC clock frequency. (++) IWDG clock which is always the LSI clock. (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz, Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and prefetch is disabled. @endverbatim * @{ */ /* Additional consideration on the SYSCLK based on Latency settings: +-----------------------------------------------+ | Latency | SYSCLK clock frequency (MHz) | |---------------|-------------------------------| |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | |---------------|-------------------------------| |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | |---------------|-------------------------------| |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | +-----------------------------------------------+ */ /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO1 OFF * - All interrupts disabled * @note This function does not modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart = 0; /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); /* Insure HSIRDY bit is set before writing default HSITRIM value */ /* Get start tick */ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Set HSITRIM default value */ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4); /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO); /* Insure HSI selected as system clock source */ /* Get start tick */ tickstart = HAL_GetTick(); /* Wait till system clock source is ready */ while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) { if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Update the SystemCoreClock global variable for HSI as system clock source */ SystemCoreClock = HSI_VALUE; /* Configure the source of time base considering new system clock settings */ if(HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } /* Reset HSEON, CSSON, PLLON bits */ CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); /* Insure PLLRDY is reset */ /* Get start tick */ tickstart = HAL_GetTick(); while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); /* Reset CFGR3 register */ CLEAR_REG(RCC->CFGR3); /* Clear all interrupt flags */ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); /* Disable all interrupts */ CLEAR_REG(RCC->CIR); /* Reset all CSR flags */ __HAL_RCC_CLEAR_RESET_FLAGS(); return HAL_OK; } /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not * supported by this macro. User should request a transition to LSE Off * first and then LSE On or LSE Bypass. * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; uint32_t pll_config; #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) uint32_t pll_config2; #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Check Null pointer */ if(RCC_OscInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) /* Configure the HSE predivision factor --------------------------------*/ __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) { return HAL_ERROR; } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { FlagStatus pwrclkchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) /* Configure the main PLL clock source, predivider and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PREDIV, RCC_OscInitStruct->PLL.PLLMUL); #else /* Configure the main PLL clock source and multiplication factor. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLMUL); #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) { return HAL_ERROR; } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) pll_config2 = RCC->CFGR2; if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) #else if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) #endif { return HAL_ERROR; } } } } return HAL_OK; } /** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. * @param FLatency FLASH Latency * The value of this parameter depend on device used within the same series * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * start-up from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after start-up delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source will be ready. * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart = 0U; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; } } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick */ tickstart = HAL_GetTick(); while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (uwTickPrio); return HAL_OK; } /** * @} */ /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. @endverbatim * @{ */ #if defined(RCC_CFGR_MCOPRE) /** * @brief Selects the clock source to output on MCO pin. * @note MCO pin should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock * @param RCC_MCODiv specifies the MCO DIV. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 no division applied to MCO clock * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock * @retval None */ #else /** * @brief Selects the clock source to output on MCO pin. * @note MCO pin should be configured in alternate function mode. * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock * @param RCC_MCODiv specifies the MCO DIV. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 no division applied to MCO clock * @retval None */ #endif void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); /* Configure the MCO1 pin in alternate function mode */ gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_FREQ_HIGH; gpio.Pull = GPIO_NOPULL; gpio.Pin = MCO1_PIN; gpio.Alternate = GPIO_AF0_MCO; /* MCO1 Clock Enable */ MCO1_CLK_ENABLE(); HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); /* Configure the MCO clock source */ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); } /** * @brief Enables the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) { *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; } /** * @brief Disables the Clock Security System. * @retval None */ void HAL_RCC_DisableCSS(void) { *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; } /** * @brief Returns the SYSCLK frequency * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value * 8 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @note This function can be used by the user application to compute the * baud-rate for the communication peripherals or configure other parameters. * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; uint32_t sysclockfreq = 0U; tmpreg = RCC->CFGR; /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) { case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; break; } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)]; prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)]; #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); } else { /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); } #else if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV) { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); } else { /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); } #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ sysclockfreq = pllclk; break; } case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ default: /* HSI used as system clock */ { sysclockfreq = HSI_VALUE; break; } } return sysclockfreq; } /** * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; } /** * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); } /** * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); } /** * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } else { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); #endif /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } else { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } else { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } else { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } else { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ } /** * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * contains the current clock configuration. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); assert_param(pFLatency != NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); } /** * @brief This function handles the RCC CSS interrupt request. * @note This API should be called under the NMI_Handler(). * @retval None */ void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF flag */ if(__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } } /** * @brief RCC Clock Security System interrupt callback * @retval none */ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_rcc_ex.c * @author MCD Application Team * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions * ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /** @defgroup RCCEx RCCEx * @brief RCC Extension HAL module driver. * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCCEx_Private_Macros RCCEx Private Macros * @{ */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \ || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \ || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \ || defined(RCC_CFGR3_HRTIM1SW) /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ static uint32_t RCC_GetPLLCLKFreq(void); /** * @} */ #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values. @endverbatim * @{ */ /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB). * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source; in this case the Backup domain will be reset in * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @note When the TIMx clock source is APB clock, so the TIMx clock is APB clock or * APB clock x 2 depending on the APB prescaler. * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0U; uint32_t temp_reg = 0U; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); FlagStatus pwrclkchanged = RESET; /* As soon as function is called to change RTC clock source, activation of the power domain is done. */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { /* Store the content of BDCR register before the reset of Backup Domain */ temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = temp_reg; /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) { /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } #if defined(RCC_CFGR3_USART2SW) /*----------------------------- USART2 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); } #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /*------------------------------ USART3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } #endif /* RCC_CFGR3_USART3SW */ /*------------------------------ I2C1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) /*------------------------------ USB Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { /* Check the parameters */ assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); /* Configure the USB clock source */ __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); } #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) /*------------------------------ I2C2 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ I2C3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) /*------------------------------ UART4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); } /*------------------------------ UART5 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ I2S Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ ADC1 clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) { /* Check the parameters */ assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection)); /* Configure the ADC1 clock source */ __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); } #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) { /* Check the parameters */ assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34) { /* Check the parameters */ assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection)); /* Configure the ADC34 clock source */ __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection); } #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F373xC) || defined(STM32F378xx) /*------------------------------ ADC1 clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) { /* Check the parameters */ assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection)); /* Configure the ADC1 clock source */ __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ TIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) { /* Check the parameters */ assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); /* Configure the TIM1 clock source */ __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); } #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) /*------------------------------ TIM8 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8) { /* Check the parameters */ assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection)); /* Configure the TIM8 clock source */ __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection); } #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) /*------------------------------ TIM15 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) { /* Check the parameters */ assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); /* Configure the TIM15 clock source */ __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); } /*------------------------------ TIM16 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) { /* Check the parameters */ assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); /* Configure the TIM16 clock source */ __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); } /*------------------------------ TIM17 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) { /* Check the parameters */ assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); /* Configure the TIM17 clock source */ __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); } #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F334x8) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); } #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) /*------------------------------ SDADC clock Configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC) { /* Check the parameters */ assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection)); /* Configure the SDADC clock prescaler */ __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection); } /*------------------------------ CEC clock Configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) /*------------------------------ TIM2 clock Configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2) { /* Check the parameters */ assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection); } /*------------------------------ TIM3 clock Configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34) { /* Check the parameters */ assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection); } /*------------------------------ TIM15 clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) { /* Check the parameters */ assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); } /*------------------------------ TIM16 clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) { /* Check the parameters */ assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); } /*------------------------------ TIM17 clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) { /* Check the parameters */ assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); } #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined(STM32F303xE) || defined(STM32F398xx) /*------------------------------ TIM20 clock Configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20) { /* Check the parameters */ assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); } #endif /* STM32F303xE || STM32F398xx */ return HAL_OK; } /** * @brief Get the RCC_ClkInitStruct according to the internal * RCC configuration registers. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals clocks * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ /* Common part first */ #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; #else PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \ RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ /* Get the RTC configuration --------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); /* Get the USART1 clock configuration --------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); #if defined(RCC_CFGR3_USART2SW) /* Get the USART2 clock configuration -----------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) /* Get the USART3 clock configuration -----------------------------------------*/ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); #endif /* RCC_CFGR3_USART3SW */ /* Get the I2C1 clock configuration -----------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); #if defined(STM32F302xE) || defined(STM32F303xE)\ || defined(STM32F302xC) || defined(STM32F303xC)\ || defined(STM32F302x8) \ || defined(STM32F373xC) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; /* Get the USB clock configuration -----------------------------------------*/ PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE(); #endif /* STM32F302xE || STM32F303xE || */ /* STM32F302xC || STM32F303xC || */ /* STM32F302x8 || */ /* STM32F373xC */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2; /* Get the I2C2 clock configuration -----------------------------------------*/ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3; /* Get the I2C3 clock configuration -----------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5); /* Get the UART4 clock configuration -----------------------------------------*/ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); /* Get the UART5 clock configuration -----------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S; /* Get the I2S clock configuration -----------------------------------------*/ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ || defined(STM32F373xC) || defined(STM32F378xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1; /* Get the ADC1 clock configuration -----------------------------------------*/ PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE(); #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12; /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/ PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE(); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34; /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/ PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE(); #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1; /* Get the TIM1 clock configuration -----------------------------------------*/ PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE(); #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ /* STM32F302xC || STM32F303xC || STM32F358xx || */ /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F303xE) || defined(STM32F398xx)\ || defined(STM32F303xC) || defined(STM32F358xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8; /* Get the TIM8 clock configuration -----------------------------------------*/ PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE(); #endif /* STM32F303xE || STM32F398xx || */ /* STM32F303xC || STM32F358xx */ #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17); /* Get the TIM15 clock configuration -----------------------------------------*/ PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); /* Get the TIM16 clock configuration -----------------------------------------*/ PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); /* Get the TIM17 clock configuration -----------------------------------------*/ PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ #if defined(STM32F334x8) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; /* Get the HRTIM1 clock configuration -----------------------------------------*/ PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); #endif /* STM32F334x8 */ #if defined(STM32F373xC) || defined(STM32F378xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC; /* Get the SDADC clock configuration -----------------------------------------*/ PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE(); PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; /* Get the CEC clock configuration -----------------------------------------*/ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2; /* Get the TIM2 clock configuration -----------------------------------------*/ PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE(); PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34; /* Get the TIM3 clock configuration -----------------------------------------*/ PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE(); PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15; /* Get the TIM15 clock configuration -----------------------------------------*/ PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16; /* Get the TIM16 clock configuration -----------------------------------------*/ PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17; /* Get the TIM17 clock configuration -----------------------------------------*/ PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #if defined (STM32F303xE) || defined(STM32F398xx) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20; /* Get the TIM20 clock configuration -----------------------------------------*/ PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE(); #endif /* STM32F303xE || STM32F398xx */ } /** * @brief Returns the peripheral clock frequency * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable. * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock @if STM32F301x8 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock @endif @if STM32F302x8 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock @endif @if STM32F302xC * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock @endif @if STM32F302xE * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock @endif @if STM32F303x8 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock @endif @if STM32F303xC * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock @endif @if STM32F303xE * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock @endif @if STM32F318xx * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock @endif @if STM32F328xx * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock @endif @if STM32F334x8 * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock @endif @if STM32F358xx * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock @endif @if STM32F373xC * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock @endif @if STM32F378xx * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock @endif @if STM32F398xx * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock @endif * @retval Frequency in Hz (0: means that no available frequency for the peripheral) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* frequency == 0 : means that no available frequency for the peripheral */ uint32_t frequency = 0U; uint32_t srcclk = 0U; #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) uint16_t adc_pll_prediv_table[16] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U}; #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ #if defined(RCC_CFGR_SDPRE) uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}; #endif /* RCC_CFGR_SDPRE */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); switch (PeriphClk) { case RCC_PERIPHCLK_RTC: { /* Get the current RTC source */ srcclk = __HAL_RCC_GET_RTC_SOURCE(); /* Check if LSE is ready and if RTC clock selection is LSE */ if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } /* Check if LSI is ready and if RTC clock selection is LSI */ else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) { frequency = LSI_VALUE; } /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { frequency = HSE_VALUE / 32U; } break; } case RCC_PERIPHCLK_USART1: { /* Get the current USART1 source */ srcclk = __HAL_RCC_GET_USART1_SOURCE(); /* Check if USART1 clock selection is PCLK1 */ #if defined(RCC_USART1CLKSOURCE_PCLK2) if (srcclk == RCC_USART1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); } #else if (srcclk == RCC_USART1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } #endif /* RCC_USART1CLKSOURCE_PCLK2 */ /* Check if HSI is ready and if USART1 clock selection is HSI */ else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if USART1 clock selection is SYSCLK */ else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Check if LSE is ready and if USART1 clock selection is LSE */ else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } break; } #if defined(RCC_CFGR3_USART2SW) case RCC_PERIPHCLK_USART2: { /* Get the current USART2 source */ srcclk = __HAL_RCC_GET_USART2_SOURCE(); /* Check if USART2 clock selection is PCLK1 */ if (srcclk == RCC_USART2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } /* Check if HSI is ready and if USART2 clock selection is HSI */ else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if USART2 clock selection is SYSCLK */ else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Check if LSE is ready and if USART2 clock selection is LSE */ else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } break; } #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) case RCC_PERIPHCLK_USART3: { /* Get the current USART3 source */ srcclk = __HAL_RCC_GET_USART3_SOURCE(); /* Check if USART3 clock selection is PCLK1 */ if (srcclk == RCC_USART3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } /* Check if HSI is ready and if USART3 clock selection is HSI */ else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if USART3 clock selection is SYSCLK */ else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Check if LSE is ready and if USART3 clock selection is LSE */ else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } break; } #endif /* RCC_CFGR3_USART3SW */ #if defined(RCC_CFGR3_UART4SW) case RCC_PERIPHCLK_UART4: { /* Get the current UART4 source */ srcclk = __HAL_RCC_GET_UART4_SOURCE(); /* Check if UART4 clock selection is PCLK1 */ if (srcclk == RCC_UART4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } /* Check if HSI is ready and if UART4 clock selection is HSI */ else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if UART4 clock selection is SYSCLK */ else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Check if LSE is ready and if UART4 clock selection is LSE */ else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } break; } #endif /* RCC_CFGR3_UART4SW */ #if defined(RCC_CFGR3_UART5SW) case RCC_PERIPHCLK_UART5: { /* Get the current UART5 source */ srcclk = __HAL_RCC_GET_UART5_SOURCE(); /* Check if UART5 clock selection is PCLK1 */ if (srcclk == RCC_UART5CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } /* Check if HSI is ready and if UART5 clock selection is HSI */ else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if UART5 clock selection is SYSCLK */ else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Check if LSE is ready and if UART5 clock selection is LSE */ else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } break; } #endif /* RCC_CFGR3_UART5SW */ case RCC_PERIPHCLK_I2C1: { /* Get the current I2C1 source */ srcclk = __HAL_RCC_GET_I2C1_SOURCE(); /* Check if HSI is ready and if I2C1 clock selection is HSI */ if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if I2C1 clock selection is SYSCLK */ else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } break; } #if defined(RCC_CFGR3_I2C2SW) case RCC_PERIPHCLK_I2C2: { /* Get the current I2C2 source */ srcclk = __HAL_RCC_GET_I2C2_SOURCE(); /* Check if HSI is ready and if I2C2 clock selection is HSI */ if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if I2C2 clock selection is SYSCLK */ else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } break; } #endif /* RCC_CFGR3_I2C2SW */ #if defined(RCC_CFGR3_I2C3SW) case RCC_PERIPHCLK_I2C3: { /* Get the current I2C3 source */ srcclk = __HAL_RCC_GET_I2C3_SOURCE(); /* Check if HSI is ready and if I2C3 clock selection is HSI */ if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if I2C3 clock selection is SYSCLK */ else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } break; } #endif /* RCC_CFGR3_I2C3SW */ #if defined(RCC_CFGR_I2SSRC) case RCC_PERIPHCLK_I2S: { /* Get the current I2S source */ srcclk = __HAL_RCC_GET_I2S_SOURCE(); /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */ if (srcclk == RCC_I2SCLKSOURCE_EXT) { /* External clock used. Frequency cannot be returned.*/ frequency = 0xDEADDEADU; } /* Check if I2S clock selection is SYSCLK */ else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } break; } #endif /* RCC_CFGR_I2SSRC */ #if defined(RCC_CFGR_USBPRE) case RCC_PERIPHCLK_USB: { /* Check if PLL is ready */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { /* Get the current USB source */ srcclk = __HAL_RCC_GET_USB_SOURCE(); /* Check if USB clock selection is not divided */ if (srcclk == RCC_USBCLKSOURCE_PLL) { frequency = RCC_GetPLLCLKFreq(); } /* Check if USB clock selection is divided by 1.5 */ else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */ { frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U; } } break; } #endif /* RCC_CFGR_USBPRE */ #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE) case RCC_PERIPHCLK_ADC1: { /* Get the current ADC1 source */ srcclk = __HAL_RCC_GET_ADC1_SOURCE(); #if defined(RCC_CFGR2_ADC1PRES) /* Check if ADC1 clock selection is AHB */ if (srcclk == RCC_ADC1PLLCLK_OFF) { frequency = SystemCoreClock; } /* PLL clock has been selected */ else { /* Check if PLL is ready */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU]; } } #else /* RCC_CFGR_ADCPRE */ /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */ frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U); #endif /* RCC_CFGR2_ADC1PRES */ break; } #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */ #if defined(RCC_CFGR2_ADCPRE12) case RCC_PERIPHCLK_ADC12: { /* Get the current ADC12 source */ srcclk = __HAL_RCC_GET_ADC12_SOURCE(); /* Check if ADC12 clock selection is AHB */ if (srcclk == RCC_ADC12PLLCLK_OFF) { frequency = SystemCoreClock; } /* PLL clock has been selected */ else { /* Check if PLL is ready */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF]; } } break; } #endif /* RCC_CFGR2_ADCPRE12 */ #if defined(RCC_CFGR2_ADCPRE34) case RCC_PERIPHCLK_ADC34: { /* Get the current ADC34 source */ srcclk = __HAL_RCC_GET_ADC34_SOURCE(); /* Check if ADC34 clock selection is AHB */ if (srcclk == RCC_ADC34PLLCLK_OFF) { frequency = SystemCoreClock; } /* PLL clock has been selected */ else { /* Check if PLL is ready */ if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) { /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */ frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF]; } } break; } #endif /* RCC_CFGR2_ADCPRE34 */ #if defined(RCC_CFGR3_TIM1SW) case RCC_PERIPHCLK_TIM1: { /* Get the current TIM1 source */ srcclk = __HAL_RCC_GET_TIM1_SOURCE(); /* Check if PLL is ready and if TIM1 clock selection is PLL */ if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM1 clock selection is SYSCLK */ else if (srcclk == RCC_TIM1CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM1SW */ #if defined(RCC_CFGR3_TIM2SW) case RCC_PERIPHCLK_TIM2: { /* Get the current TIM2 source */ srcclk = __HAL_RCC_GET_TIM2_SOURCE(); /* Check if PLL is ready and if TIM2 clock selection is PLL */ if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM2 clock selection is SYSCLK */ else if (srcclk == RCC_TIM2CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM2SW */ #if defined(RCC_CFGR3_TIM8SW) case RCC_PERIPHCLK_TIM8: { /* Get the current TIM8 source */ srcclk = __HAL_RCC_GET_TIM8_SOURCE(); /* Check if PLL is ready and if TIM8 clock selection is PLL */ if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM8 clock selection is SYSCLK */ else if (srcclk == RCC_TIM8CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM8SW */ #if defined(RCC_CFGR3_TIM15SW) case RCC_PERIPHCLK_TIM15: { /* Get the current TIM15 source */ srcclk = __HAL_RCC_GET_TIM15_SOURCE(); /* Check if PLL is ready and if TIM15 clock selection is PLL */ if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM15 clock selection is SYSCLK */ else if (srcclk == RCC_TIM15CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM15SW */ #if defined(RCC_CFGR3_TIM16SW) case RCC_PERIPHCLK_TIM16: { /* Get the current TIM16 source */ srcclk = __HAL_RCC_GET_TIM16_SOURCE(); /* Check if PLL is ready and if TIM16 clock selection is PLL */ if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM16 clock selection is SYSCLK */ else if (srcclk == RCC_TIM16CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM16SW */ #if defined(RCC_CFGR3_TIM17SW) case RCC_PERIPHCLK_TIM17: { /* Get the current TIM17 source */ srcclk = __HAL_RCC_GET_TIM17_SOURCE(); /* Check if PLL is ready and if TIM17 clock selection is PLL */ if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM17 clock selection is SYSCLK */ else if (srcclk == RCC_TIM17CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM17SW */ #if defined(RCC_CFGR3_TIM20SW) case RCC_PERIPHCLK_TIM20: { /* Get the current TIM20 source */ srcclk = __HAL_RCC_GET_TIM20_SOURCE(); /* Check if PLL is ready and if TIM20 clock selection is PLL */ if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM20 clock selection is SYSCLK */ else if (srcclk == RCC_TIM20CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM20SW */ #if defined(RCC_CFGR3_TIM34SW) case RCC_PERIPHCLK_TIM34: { /* Get the current TIM34 source */ srcclk = __HAL_RCC_GET_TIM34_SOURCE(); /* Check if PLL is ready and if TIM34 clock selection is PLL */ if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if TIM34 clock selection is SYSCLK */ else if (srcclk == RCC_TIM34CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_TIM34SW */ #if defined(RCC_CFGR3_HRTIM1SW) case RCC_PERIPHCLK_HRTIM1: { /* Get the current HRTIM1 source */ srcclk = __HAL_RCC_GET_HRTIM1_SOURCE(); /* Check if PLL is ready and if HRTIM1 clock selection is PLL */ if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) { frequency = RCC_GetPLLCLKFreq(); } /* Check if HRTIM1 clock selection is SYSCLK */ else if (srcclk == RCC_HRTIM1CLK_HCLK) { frequency = SystemCoreClock; } break; } #endif /* RCC_CFGR3_HRTIM1SW */ #if defined(RCC_CFGR_SDPRE) case RCC_PERIPHCLK_SDADC: { /* Get the current SDADC source */ srcclk = __HAL_RCC_GET_SDADC_SOURCE(); /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/20U/24U/28U/32U/36U/40U/44U/48U) */ frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) & 0xF]; break; } #endif /* RCC_CFGR_SDPRE */ #if defined(RCC_CFGR3_CECSW) case RCC_PERIPHCLK_CEC: { /* Get the current CEC source */ srcclk = __HAL_RCC_GET_CEC_SOURCE(); /* Check if HSI is ready and if CEC clock selection is HSI */ if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) { frequency = HSI_VALUE; } /* Check if LSE is ready and if CEC clock selection is LSE */ else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) { frequency = LSE_VALUE; } break; } #endif /* RCC_CFGR3_CECSW */ default: { break; } } return(frequency); } /** * @} */ /** * @} */ #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || defined(RCC_CFGR_USBPRE) \ || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined(RCC_CFGR3_TIM15SW) \ || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defined(RCC_CFGR3_TIM34SW) \ || defined(RCC_CFGR3_HRTIM1SW) /** @addtogroup RCCEx_Private_Functions * @{ */ static uint32_t RCC_GetPLLCLKFreq(void) { uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U; pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; pllmul = ( pllmul >> 18U) + 2U; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) if (pllsource != RCC_PLLSOURCE_HSI) { prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (HSE_VALUE/prediv) * pllmul; } else { /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */ pllclk = (HSI_VALUE >> 1U) * pllmul; } #else prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) { /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ pllclk = (HSE_VALUE/prediv) * pllmul; } else { /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ pllclk = (HSI_VALUE/prediv) * pllmul; } #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ return pllclk; } /** * @} */ #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC_CFGR_USBPRE */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_tim.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + TIM Time Base Initialization * + TIM Time Base Start * + TIM Time Base Start Interruption * + TIM Time Base Start DMA * + TIM Output Compare/PWM Initialization * + TIM Output Compare/PWM Channel Configuration * + TIM Output Compare/PWM Start * + TIM Output Compare/PWM Start Interruption * + TIM Output Compare/PWM Start DMA * + TIM Input Capture Initialization * + TIM Input Capture Channel Configuration * + TIM Input Capture Start * + TIM Input Capture Start Interruption * + TIM Input Capture Start DMA * + TIM One Pulse Initialization * + TIM One Pulse Channel Configuration * + TIM One Pulse Start * + TIM Encoder Interface Initialization * + TIM Encoder Interface Start * + TIM Encoder Interface Start Interruption * + TIM Encoder Interface Start DMA * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration @verbatim ============================================================================== ##### TIMER Generic features ##### ============================================================================== [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. (#) Up to 4 independent channels for: (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Supports incremental encoder for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() (++) Output Compare : HAL_TIM_OC_MspInit() (++) PWM generation : HAL_TIM_PWM_MspInit() (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() (++) Encoder mode output : HAL_TIM_Encoder_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an Output Compare signal. (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). (#) The DMA Burst is managed with the two following functions: HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() *** Callback registration *** ============================================= [..] The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] Use Function @ref HAL_TIM_RegisterCallback() to register a callback. @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: (+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. (+) IC_MspInitCallback : TIM IC Msp Init Callback. (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. (+) OC_MspInitCallback : TIM OC Msp Init Callback. (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. (+) PeriodElapsedCallback : TIM Period Elapsed Callback. (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. (+) TriggerCallback : TIM Trigger Callback. (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. (+) IC_CaptureCallback : TIM Input Capture Callback. (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. (+) ErrorCallback : TIM Error Callback. (+) CommutationCallback : TIM Commutation Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. (+) BreakCallback : TIM Break Callback. (+) Break2Callback : TIM Break2 Callback (when supported). [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init / DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered beforehand) [..] Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Exception done MspInit / MspDeInit that can be registered / unregistered in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup TIM TIM * @brief TIM HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions * @{ */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); #if defined(TIM_CCER_CC5E) static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); #endif /* TIM_CCER_CC6E */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM base. (+) De-initialize the TIM base. (+) Start the Time Base. (+) Stop the Time Base. (+) Start the Time Base and enable interrupt. (+) Stop the Time Base and disable interrupt. (+) Start the Time Base and enable DMA transfer. (+) Stop the Time Base and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Base_MspInitCallback == NULL) { htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Base peripheral * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Base_MspDeInitCallback == NULL) { htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; } /* DeInit the low level hardware */ htim->Base_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Change the TIM state*/ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the TIM state*/ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in DMA mode. * @param htim TIM Base handle * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in DMA mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @verbatim ============================================================================== ##### TIM Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. (+) Start the TIM Output Compare. (+) Stop the TIM Output Compare. (+) Start the TIM Output Compare and enable interrupt. (+) Stop the TIM Output Compare and disable interrupt. (+) Start the TIM Output Compare and enable DMA transfer. (+) Stop the TIM Output Compare and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OC_MspInitCallback == NULL) { htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OC_MspDeInitCallback == NULL) { htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; } /* DeInit the low level hardware */ htim->OC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @verbatim ============================================================================== ##### TIM PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. (+) Start the TIM PWM. (+) Stop the TIM PWM. (+) Start the TIM PWM and enable interrupt. (+) Stop the TIM PWM and disable interrupt. (+) Start the TIM PWM and enable DMA transfer. (+) Stop the TIM PWM and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->PWM_MspInitCallback == NULL) { htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->PWM_MspDeInitCallback == NULL) { htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; } /* DeInit the low level hardware */ htim->PWM_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspDeInit could be implemented in the user file */ } /** * @brief Starts the PWM signal generation. * @param htim TIM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @verbatim ============================================================================== ##### TIM Input Capture functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. (+) Start the TIM Input Capture. (+) Stop the TIM Input Capture. (+) Start the TIM Input Capture and enable interrupt. (+) Stop the TIM Input Capture and disable interrupt. (+) Start the TIM Input Capture and enable DMA transfer. (+) Stop the TIM Input Capture and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->IC_MspInitCallback == NULL) { htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->IC_MspDeInitCallback == NULL) { htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; } /* DeInit the low level hardware */ htim->IC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Input Capture MSP. * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: break; } /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: break; } /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @verbatim ============================================================================== ##### TIM One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. (+) Start the TIM One Pulse. (+) Stop the TIM One Pulse. (+) Start the TIM One Pulse and enable interrupt. (+) Stop the TIM One Pulse and disable interrupt. (+) Start the TIM One Pulse and enable DMA transfer. (+) Stop the TIM One Pulse and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OnePulse_MspInitCallback == NULL) { htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OnePulse_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM One Pulse * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OnePulse_MspDeInitCallback == NULL) { htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; } /* DeInit the low level hardware */ htim->OnePulse_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM One Pulse signal generation. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @verbatim ============================================================================== ##### TIM Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. (+) Start the TIM Encoder. (+) Stop the TIM Encoder. (+) Start the TIM Encoder and enable interrupt. (+) Stop the TIM Encoder and disable interrupt. (+) Start the TIM Encoder and enable DMA transfer. (+) Stop the TIM Encoder and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Encoder_MspInitCallback == NULL) { htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Encoder interface * @param htim TIM Encoder Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Encoder_MspDeInitCallback == NULL) { htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; } /* DeInit the low level hardware */ htim->Encoder_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 and 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @param pData1 The destination Buffer address for IC1. * @param pData2 The destination Buffer address for IC2. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_ALL: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { return HAL_ERROR; } /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } default: break; } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 and 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief TIM IRQ handler management * @verbatim ============================================================================== ##### IRQ handler management ##### ============================================================================== [..] This section provides Timer IRQ handler function. @endverbatim * @{ */ /** * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #if defined(TIM_BDTR_BK2E) /* TIM Break2 input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } #endif /* TIM_BDTR_BK2E */ /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief TIM Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. (+) Configure External Clock source. (+) Configure Complementary channels, break features and dead time. (+) Configure Master and the Slave synchronization. (+) Configure the DMA Burst Mode. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM Output Compare handle * @param sConfig TIM Output Compare configuration structure * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); break; } #if defined(TIM_CCER_CC5E) case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the TIM Channel 5 in Output Compare */ TIM_OC5_SetConfig(htim->Instance, sConfig); break; } #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the TIM Channel 6 in Output Compare */ TIM_OC6_SetConfig(htim->Instance, sConfig); break; } #endif /* TIM_CCER_CC6E */ default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. * @param htim TIM IC handle * @param sConfig TIM Input Capture configuration structure * @param Channel TIM Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; } else if (Channel == TIM_CHANNEL_2) { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } else { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM PWM handle * @param sConfig TIM PWM configuration structure * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; htim->Instance->CCMR2 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; break; } #if defined(TIM_CCER_CC5E) case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; htim->Instance->CCMR3 |= sConfig->OCFastMode; break; } #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; break; } #endif /* TIM_CCER_CC6E */ default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. * @param htim TIM One Pulse handle * @param sConfig TIM One Pulse configuration structure * @param OutputChannel TIM output channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @param InputChannel TIM input Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @note To output a waveform with a minimum delay user can enable the fast * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx * output is forced in response to the edge detection on TIx input, * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; /* Check the parameters */ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Extract the Output compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; temp1.OCNPolarity = sConfig->OCNPolarity; temp1.OCIdleState = sConfig->OCIdleState; temp1.OCNIdleState = sConfig->OCNIdleState; switch (OutputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_OC1_SetConfig(htim->Instance, &temp1); break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_OC2_SetConfig(htim->Instance, &temp1); break; } default: break; } switch (InputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1FP1; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI2FP2; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR * @arg TIM_DMABASE_CCMR3 (*) * @arg TIM_DMABASE_CCR5 (*) * @arg TIM_DMABASE_CCR6 (*) * (*) value not defined in all devices * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); } /** * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR * @arg TIM_DMABASE_CCMR3 (*) * @arg TIM_DMABASE_CCR5 (*) * @arg TIM_DMABASE_CCR6 (*) * (*) value not defined in all devices * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { return HAL_ERROR; } break; } default: break; } /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM DMA Burst mode * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } if (HAL_OK == status) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ return status; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR * @arg TIM_DMABASE_CCMR3 (*) * @arg TIM_DMABASE_CCR5 (*) * @arg TIM_DMABASE_CCR6 (*) * (*) value not defined in all devices * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_OR * @arg TIM_DMABASE_CCMR3 (*) * @arg TIM_DMABASE_CCR5 (*) * @arg TIM_DMABASE_CCR6 (*) * (*) value not defined in all devices * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { return HAL_ERROR; } break; } default: break; } /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Stop the DMA burst reading * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } if (HAL_OK == status) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ return status; } /** * @brief Generate a software event * @param htim TIM handle * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source * @arg TIM_EVENTSOURCE_COM: Timer COM event source * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source * @note Basic timers can only generate an update event. * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances * supporting a break input. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_EVENT_SOURCE(EventSource)); /* Process Locked */ __HAL_LOCK(htim); /* Change the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the event sources */ htim->Instance->EGR = EventSource; /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); /* Return function status */ return HAL_OK; } /** * @brief Configures the OCRef clear feature * @param htim TIM handle * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 (*) * @arg TIM_CHANNEL_6: TIM Channel 6 (*) * (*) Value not defined for all devices * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { /* Clear the OCREF clear selection bit and the the ETR Bits */ #if defined(TIM_SMCR_OCCS) CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); #else CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); #endif /* TIM_SMCR_OCCS */ break; } #if defined(TIM_SMCR_OCCS) case TIM_CLEARINPUTSOURCE_OCREFCLR: { /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); } break; #endif /* TIM_SMCR_OCCS */ case TIM_CLEARINPUTSOURCE_ETR: { /* Check the parameters */ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); #if defined(TIM_SMCR_OCCS) /* Set the OCREF clear selection bit */ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); #endif /* TIM_SMCR_OCCS */ break; } default: break; } switch (Channel) { case TIM_CHANNEL_1: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 1 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } else { /* Disable the OCREF clear feature for Channel 1 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } break; } case TIM_CHANNEL_2: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 2 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } else { /* Disable the OCREF clear feature for Channel 2 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } break; } case TIM_CHANNEL_3: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 3 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } else { /* Disable the OCREF clear feature for Channel 3 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } break; } case TIM_CHANNEL_4: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 4 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } else { /* Disable the OCREF clear feature for Channel 4 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } break; } #if defined(TIM_CCER_CC5E) case TIM_CHANNEL_5: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 5 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } else { /* Disable the OCREF clear feature for Channel 5 */ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } break; } #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) case TIM_CHANNEL_6: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 6 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } else { /* Disable the OCREF clear feature for Channel 6 */ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } break; } #endif /* TIM_CCER_CC6E */ default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the clock source to be used * @param htim TIM handle * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); htim->Instance->SMCR = tmpsmcr; switch (sClockSourceConfig->ClockSource) { case TIM_CLOCKSOURCE_INTERNAL: { assert_param(IS_TIM_INSTANCE(htim->Instance)); break; } case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; break; } case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; break; } case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); break; } case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); break; } case TIM_CLOCKSOURCE_TI1ED: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); break; } case TIM_CLOCKSOURCE_ITR0: case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); break; } default: break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input * @param htim TIM handle. * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 * pins are connected to the TI1 input (XOR combination) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Reset the TI1 selection */ tmpcr2 &= ~TIM_CR2_TI1S; /* Set the TI1 selection */ tmpcr2 |= TI1_Selection; /* Write to TIMxCR2 */ htim->Instance->CR2 = tmpcr2; return HAL_OK; } /** * @brief Configures the TIM in Slave mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Enable Trigger Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Read the captured value from Capture Compare unit * @param htim TIM handle. * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; break; } default: break; } return tmpreg; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== [..] This section provides TIM callback functions: (+) TIM Period elapsed callback (+) TIM Output Compare callback (+) TIM Input capture callback (+) TIM Trigger callback (+) TIM Error callback @endverbatim * @{ */ /** * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } /** * @brief Period elapsed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file */ } /** * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } /** * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } /** * @brief Input Capture half complete callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file */ } /** * @brief Timer error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Register a User TIM callback to be used instead of the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID #if defined(TIM_BDTR_BK2E) * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID #endif * @param pCallback pointer to the callback function * @retval status */ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : htim->PeriodElapsedCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : htim->PeriodElapsedHalfCpltCallback = pCallback; break; case HAL_TIM_TRIGGER_CB_ID : htim->TriggerCallback = pCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : htim->TriggerHalfCpltCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : htim->IC_CaptureCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : htim->IC_CaptureHalfCpltCallback = pCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : htim->OC_DelayElapsedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : htim->PWM_PulseFinishedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : htim->PWM_PulseFinishedHalfCpltCallback = pCallback; break; case HAL_TIM_ERROR_CB_ID : htim->ErrorCallback = pCallback; break; case HAL_TIM_COMMUTATION_CB_ID : htim->CommutationCallback = pCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : htim->CommutationHalfCpltCallback = pCallback; break; case HAL_TIM_BREAK_CB_ID : htim->BreakCallback = pCallback; break; #if defined(TIM_BDTR_BK2E) case HAL_TIM_BREAK2_CB_ID : htim->Break2Callback = pCallback; break; #endif /* TIM_BDTR_BK2E */ default : /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = pCallback; break; default : /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } /** * @brief Unregister a TIM callback * TIM callback is redirected to the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID #if defined(TIM_BDTR_BK2E) * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID #endif * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ break; case HAL_TIM_TRIGGER_CB_ID : htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ break; case HAL_TIM_TRIGGER_HALF_CB_ID : htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ break; case HAL_TIM_IC_CAPTURE_CB_ID : htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ break; case HAL_TIM_ERROR_CB_ID : htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ break; case HAL_TIM_COMMUTATION_CB_ID : htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ break; case HAL_TIM_COMMUTATION_HALF_CB_ID : htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ break; case HAL_TIM_BREAK_CB_ID : htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ break; #if defined(TIM_BDTR_BK2E) case HAL_TIM_BREAK2_CB_ID : htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ break; #endif /* TIM_BDTR_BK2E */ default : /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ break; default : /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief TIM Peripheral State functions * @verbatim ============================================================================== ##### Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Base handle state. * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM OC handle state. * @param htim TIM Output Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM PWM handle state. * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Input Capture handle state. * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM One Pulse Mode handle state. * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM Encoder Interface handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @} */ /** * @} */ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ /** * @brief TIM DMA error callback * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Delay Pulse complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedHalfCpltCallback(htim); #else HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureHalfCpltCallback(htim); #else HAL_TIM_IC_CaptureHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Period Elapse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Period Elapse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else HAL_TIM_PeriodElapsedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else HAL_TIM_TriggerHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief Time Base configuration * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; } /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; #if defined(TIM_CR2_OIS2N) tmpcr2 &= ~TIM_CR2_OIS2N; #endif /* TIM_CR2_OIS2N */ /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } #if defined(TIM_CR2_OIS3) if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); } #endif /* TIM_CR2_OIS3 */ /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); #if defined(TIM_CR2_OIS4) if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); } #endif /* TIM_CR2_OIS4 */ /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } #if defined(TIM_CCER_CC5E) /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The ouput configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } #endif /* TIM_CCER_CC6E */ /** * @brief Slave Timer configuration function * @param htim TIM handle * @param sSlaveConfig Slave timer configuration * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Reset the Trigger Selection Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source */ tmpsmcr |= sSlaveConfig->InputTrigger; /* Reset the slave mode Bits */ tmpsmcr &= ~TIM_SMCR_SMS; /* Set the slave mode */ tmpsmcr |= sSlaveConfig->SlaveMode; /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { case TIM_TS_ETRF: { /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; } /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = htim->Instance->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; htim->Instance->CCER = tmpccer; break; } case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_ITR0: case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: { /* Check the parameter */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); break; } default: break; } return HAL_OK; } /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= TIM_ICPolarity; /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; tmpccmr2 |= TIM_ICSelection; /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer ; } /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { uint32_t tmp; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Reset interrupt callbacks to the legacy weak callbacks. * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ #if defined(TIM_BDTR_BK2E) htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ #endif /* TIM_BDTR_BK2E */ } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c ================================================ /** ****************************************************************************** * @file stm32f3xx_hal_tim_ex.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: * + Time Hall Sensor Interface Initialization * + Time Hall Sensor Interface Start * + Time Complementary signal break and dead time configuration * + Time Master and Slave synchronization configuration * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) * + Time OCRef clear configuration * + Timer remapping capabilities configuration @verbatim ============================================================================== ##### TIMER Extended features ##### ============================================================================== [..] The Timer Extended features include: (#) Complementary outputs with programmable dead-time for : (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Break input to put the timer output signals in reset state or in a known state. (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the Timer Hall Sensor Interface and the commutation event with the corresponding Interrupt and DMA request if needed (Note that One Timer is used to interface with the Hall sensor Interface and another Timer should be used to use the commutation event). (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_hal.h" /** @addtogroup STM32F3xx_HAL_Driver * @{ */ /** @defgroup TIMEx TIMEx * @brief TIM Extended HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @verbatim ============================================================================== ##### Timer Hall Sensor functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure TIM HAL Sensor. (+) De-initialize TIM HAL Sensor. (+) Start the Hall Sensor Interface. (+) Stop the Hall Sensor Interface. (+) Start the Hall Sensor Interface and enable interrupts. (+) Stop the Hall Sensor Interface and disable interrupts. (+) Start the Hall Sensor Interface and enable DMA transfers. (+) Stop the Hall Sensor Interface and disable DMA transfers. @endverbatim * @{ */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy week callbacks */ TIM_ResetCallback(htim); if (htim->HallSensor_MspInitCallback == NULL) { htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->HallSensor_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->IC1Prescaler; /* Enable the Hall sensor interface (XOR function of the three inputs) */ htim->Instance->CR2 |= TIM_CR2_TI1S; /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1F_ED; /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ OC_Config.OCFastMode = TIM_OCFAST_DISABLE; OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; OC_Config.OCMode = TIM_OCMODE_PWM2; OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; OC_Config.Pulse = sConfig->Commutation_Delay; TIM_OC2_SetConfig(htim->Instance, &OC_Config); /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to 101 */ htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Hall Sensor interface * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->HallSensor_MspDeInitCallback == NULL) { htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; } /* DeInit the low level hardware */ htim->HallSensor_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Hall Sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 event */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @verbatim ============================================================================== ##### Timer Complementary Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary Output Compare/PWM. (+) Stop the Complementary Output Compare/PWM. (+) Start the Complementary Output Compare/PWM and enable interrupts. (+) Stop the Complementary Output Compare/PWM and disable interrupts. (+) Start the Complementary Output Compare/PWM and enable DMA transfers. (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. @endverbatim * @{ */ /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM OC handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } default: break; } /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } default: break; } /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @verbatim ============================================================================== ##### Timer Complementary PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary PWM. (+) Stop the Complementary PWM. (+) Start the Complementary PWM and enable interrupts. (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. (+) Start the Complementary Input Capture measurement. (+) Stop the Complementary Input Capture. (+) Start the Complementary Input Capture and enable interrupts. (+) Stop the Complementary Input Capture and disable interrupts. (+) Start the Complementary Input Capture and enable DMA transfers. (+) Stop the Complementary Input Capture and disable DMA transfers. (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } default: break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { /* nothing to do */ } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } default: break; } /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } default: break; } /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @verbatim ============================================================================== ##### Timer Complementary One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Enable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); /* Enable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @param htim TIM One Pulse handle * @param OutputChannel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the complementary One Pulse output */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. (+) Enable or disable channel grouping. @endverbatim * @{ */ /** * @brief Configure the TIM commutation event sequence. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with interrupt. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); /* Enable the Commutation Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with DMA. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); __HAL_LOCK(htim); if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Enable the Commutation DMA Request */ /* Set the DMA Commutation Callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Enable the Commutation DMA Request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in master mode. * @param htim TIM handle. * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; #if defined(TIM_CR2_MMS2) /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; } #endif /* TIM_CR2_MMS2 */ /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @note Interrupts can be generated when an active level is detected on the * break input, the break 2 input or the system break input. Break * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); #if defined(TIM_BDTR_BKF) assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); #endif /* TIM_BDTR_BKF */ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); /* Check input state */ __HAL_LOCK(htim); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); #if defined(TIM_BDTR_BKF) MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); #endif /* TIM_BDTR_BKF */ #if defined(TIM_BDTR_BK2E) if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); } #endif /* TIM_BDTR_BK2E */ /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. * @param Remap specifies the TIM remapping source. @if STM32F301x8 * For TIM1, the parameter can have the following values: * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 @elseif STM32F303xE * For TIM1, the parameter is a combination of 2 fields (field1 | field2): * * field1 can have the following values: * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 * * field2 can have the following values: * @arg TIM_TIM1_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 @elseif STM32F334x8 * For TIM1, the parameter is a combination of 2 fields (field1 | field2): * * field1 can have the following values: * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 * * field2 can have the following values: * @arg TIM_TIM1_ADC2_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3 @endif @if STM32F303xE * For TIM8, the parameter is a combination of 2 fields (field1 | field2): * * field1 can have the following values: * @arg TIM_TIM8_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM8_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 * @arg TIM_TIM8_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 * @arg TIM_TIM8_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD2 * * field2 can have the following values: * @arg TIM_TIM8_ADC3_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM8_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 * @arg TIM_TIM8_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 * @arg TIM_TIM8_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 @endif @if STM32F373xC * For TIM14, the parameter can have the following values: * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO @else * For TIM16, the parameter can have the following values: * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32 * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO @endif @if STM32F303xE * For TIM20, the parameter is a combination of 2 fields (field1 | field2): * * field1 can have the following values: * @arg TIM_TIM20_ADC3_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM20_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 * @arg TIM_TIM20_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 * @arg TIM_TIM20_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD2 * * field2 can have the following values: * @arg TIM_TIM20_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) * @arg TIM_TIM20_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 * @arg TIM_TIM20_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 * @arg TIM_TIM20_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 @endif * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { __HAL_LOCK(htim); /* Check parameters */ assert_param(IS_TIM_REMAP(htim->Instance, Remap)); /* Set the Timer remapping configuration */ WRITE_REG(htim->Instance->OR, Remap); __HAL_UNLOCK(htim); return HAL_OK; } #if defined(TIM_CCR5_CCR5) /** * @brief Group channel 5 and channel 1, 2 or 3 * @param htim TIM handle. * @param Channels specifies the reference signal(s) the OC5REF is combined with. * This parameter can be any combination of the following values: * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) { /* Check parameters */ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); assert_param(IS_TIM_GROUPCH5(Channels)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Clear GC5Cx bit fields */ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); /* Set GC5Cx bit fields */ htim->Instance->CCR5 |= Channels; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } #endif /* TIM_CCR5_CCR5 */ /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @verbatim ============================================================================== ##### Extended Callbacks functions ##### ============================================================================== [..] This section provides Extended TIM callback functions: (+) Timer Commutation callback (+) Timer Break callback @endverbatim * @{ */ /** * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } /** * @brief Hall commutation changed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } #if defined(TIM_BDTR_BK2E) /** * @brief Hall Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } #endif /* TIM_BDTR_BK2E */ /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @verbatim ============================================================================== ##### Extended Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Hall Sensor interface handle state. * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ /** * @brief TIM DMA Commutation callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Commutation half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationHalfCpltCallback(htim); #else HAL_TIMEx_CommutHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { uint32_t tmp; tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_dac.c * @author MCD Application Team * @brief DAC LL module driver ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_ll_dac.h" #include "stm32f3xx_ll_bus.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (DAC1) || defined (DAC2) /** @addtogroup DAC_LL DAC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup DAC_LL_Private_Macros * @{ */ #if defined(DAC_CHANNEL2_SUPPORT) #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ ( \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #else #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ ( \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ ) #endif /* DAC_CHANNEL2_SUPPORT */ #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) #elif defined(STM32F303x8) || defined(STM32F328xx) #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) #elif defined(STM32F302xE) || defined(STM32F302xC) || defined(STM32F302x8) #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) #elif defined(STM32F301x8) || defined(STM32F318xx) #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) #elif defined(STM32F373xC) || defined(STM32F378xx) #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) #elif defined(STM32F334x8) #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG2) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIGGER_HRTIM1_DACTRG3) \ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) #endif #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \ ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup DAC_LL_Exported_Functions * @{ */ /** @addtogroup DAC_LL_EF_Init * @{ */ /** * @brief De-initialize registers of the selected DAC instance * to their default reset values. * @param DACx DAC instance * @retval An ErrorStatus enumeration value: * - SUCCESS: DAC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); if(DACx == DAC1) { /* Force reset of DAC clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); /* Release reset of DAC clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); } #if defined(DAC2) else { /* Force reset of DAC clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC2); /* Release reset of DAC clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC2); } #endif return SUCCESS; } /** * @brief Initialize some features of DAC instance. * @note The setting of these parameters by function @ref LL_DAC_Init() * is conditioned to DAC state: * DAC instance must be disabled. * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * * (1) On this STM32 serie, parameter not available on all devices. * Refer to device datasheet for channels availability. * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: DAC registers are initialized * - ERROR: DAC registers are not initialized */ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource)); assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer)); assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); } /* Note: Hardware constraint (refer to description of this function) */ /* DAC instance must be disabled. */ if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) { /* Configuration of DAC channel: */ /* - TriggerSource */ /* - WaveAutoGeneration */ /* - OutputBuffer */ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { MODIFY_REG(DACx->CR, ( DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1 | DAC_CR_BOFF1 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) , ( DAC_InitStruct->TriggerSource | DAC_InitStruct->WaveAutoGeneration | DAC_InitStruct->WaveAutoGenerationConfig | DAC_InitStruct->OutputBuffer ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } else { MODIFY_REG(DACx->CR, ( DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_BOFF1 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) , ( DAC_InitStruct->TriggerSource | LL_DAC_WAVE_AUTO_GENERATION_NONE | DAC_InitStruct->OutputBuffer ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ); } } else { /* Initialization error: DAC instance is not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_DAC_InitTypeDef field to default value. * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) { /* Set DAC_InitStruct fields to default values */ DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE; DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; /* Note: Parameter discarded if wave auto generation is disabled, */ /* set anyway to its default value. */ DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0; DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE; } /** * @} */ /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_dma.c * @author MCD Application Team * @brief DMA LL module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_ll_dma.h" #include "stm32f3xx_ll_bus.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (DMA1) || defined (DMA2) /** @defgroup DMA_LL DMA * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup DMA_LL_Private_Macros * @{ */ #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) #if defined (DMA2) #if defined (DMA2_Channel6) && defined (DMA2_Channel7) #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ (((CHANNEL) == LL_DMA_CHANNEL_1) || \ ((CHANNEL) == LL_DMA_CHANNEL_2) || \ ((CHANNEL) == LL_DMA_CHANNEL_3) || \ ((CHANNEL) == LL_DMA_CHANNEL_4) || \ ((CHANNEL) == LL_DMA_CHANNEL_5) || \ ((CHANNEL) == LL_DMA_CHANNEL_6) || \ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ (((INSTANCE) == DMA2) && \ (((CHANNEL) == LL_DMA_CHANNEL_1) || \ ((CHANNEL) == LL_DMA_CHANNEL_2) || \ ((CHANNEL) == LL_DMA_CHANNEL_3) || \ ((CHANNEL) == LL_DMA_CHANNEL_4) || \ ((CHANNEL) == LL_DMA_CHANNEL_5) || \ ((CHANNEL) == LL_DMA_CHANNEL_6) || \ ((CHANNEL) == LL_DMA_CHANNEL_7)))) #else #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ (((CHANNEL) == LL_DMA_CHANNEL_1) || \ ((CHANNEL) == LL_DMA_CHANNEL_2) || \ ((CHANNEL) == LL_DMA_CHANNEL_3) || \ ((CHANNEL) == LL_DMA_CHANNEL_4) || \ ((CHANNEL) == LL_DMA_CHANNEL_5) || \ ((CHANNEL) == LL_DMA_CHANNEL_6) || \ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ (((INSTANCE) == DMA2) && \ (((CHANNEL) == LL_DMA_CHANNEL_1) || \ ((CHANNEL) == LL_DMA_CHANNEL_2) || \ ((CHANNEL) == LL_DMA_CHANNEL_3) || \ ((CHANNEL) == LL_DMA_CHANNEL_4) || \ ((CHANNEL) == LL_DMA_CHANNEL_5)))) #endif #else #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ ((CHANNEL) == LL_DMA_CHANNEL_2) || \ ((CHANNEL) == LL_DMA_CHANNEL_3) || \ ((CHANNEL) == LL_DMA_CHANNEL_4) || \ ((CHANNEL) == LL_DMA_CHANNEL_5) || \ ((CHANNEL) == LL_DMA_CHANNEL_6) || \ ((CHANNEL) == LL_DMA_CHANNEL_7)))) #endif /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_LL_Exported_Functions * @{ */ /** @addtogroup DMA_LL_EF_Init * @{ */ /** * @brief De-initialize the DMA registers to their default reset values. * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA registers are de-initialized * - ERROR: DMA registers are not de-initialized */ uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) { DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; ErrorStatus status = SUCCESS; /* Check the DMA Instance DMAx and Channel parameters*/ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); /* Disable the selected DMAx_Channely */ CLEAR_BIT(tmp->CCR, DMA_CCR_EN); /* Reset DMAx_Channely control register */ LL_DMA_WriteReg(tmp, CCR, 0U); /* Reset DMAx_Channely remaining bytes register */ LL_DMA_WriteReg(tmp, CNDTR, 0U); /* Reset DMAx_Channely peripheral address register */ LL_DMA_WriteReg(tmp, CPAR, 0U); /* Reset DMAx_Channely memory address register */ LL_DMA_WriteReg(tmp, CMAR, 0U); if (Channel == LL_DMA_CHANNEL_1) { /* Reset interrupt pending bits for DMAx Channel1 */ LL_DMA_ClearFlag_GI1(DMAx); } else if (Channel == LL_DMA_CHANNEL_2) { /* Reset interrupt pending bits for DMAx Channel2 */ LL_DMA_ClearFlag_GI2(DMAx); } else if (Channel == LL_DMA_CHANNEL_3) { /* Reset interrupt pending bits for DMAx Channel3 */ LL_DMA_ClearFlag_GI3(DMAx); } else if (Channel == LL_DMA_CHANNEL_4) { /* Reset interrupt pending bits for DMAx Channel4 */ LL_DMA_ClearFlag_GI4(DMAx); } else if (Channel == LL_DMA_CHANNEL_5) { /* Reset interrupt pending bits for DMAx Channel5 */ LL_DMA_ClearFlag_GI5(DMAx); } else if (Channel == LL_DMA_CHANNEL_6) { /* Reset interrupt pending bits for DMAx Channel6 */ LL_DMA_ClearFlag_GI6(DMAx); } else if (Channel == LL_DMA_CHANNEL_7) { /* Reset interrupt pending bits for DMAx Channel7 */ LL_DMA_ClearFlag_GI7(DMAx); } else { status = ERROR; } return status; } /** * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : * @arg @ref __LL_DMA_GET_INSTANCE * @arg @ref __LL_DMA_GET_CHANNEL * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_1 * @arg @ref LL_DMA_CHANNEL_2 * @arg @ref LL_DMA_CHANNEL_3 * @arg @ref LL_DMA_CHANNEL_4 * @arg @ref LL_DMA_CHANNEL_5 * @arg @ref LL_DMA_CHANNEL_6 * @arg @ref LL_DMA_CHANNEL_7 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA registers are initialized * - ERROR: Not applicable */ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) { /* Check the DMA Instance DMAx and Channel parameters*/ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); /* Check the DMA parameters from DMA_InitStruct */ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); /*---------------------------- DMAx CCR Configuration ------------------------ * Configure DMAx_Channely: data transfer direction, data transfer mode, * peripheral and memory increment mode, * data size alignment and priority level with parameters : * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits * - Mode: DMA_CCR_CIRC bit * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits * - Priority: DMA_CCR_PL[1:0] bits */ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ DMA_InitStruct->Mode | \ DMA_InitStruct->PeriphOrM2MSrcIncMode | \ DMA_InitStruct->MemoryOrM2MDstIncMode | \ DMA_InitStruct->PeriphOrM2MSrcDataSize | \ DMA_InitStruct->MemoryOrM2MDstDataSize | \ DMA_InitStruct->Priority); /*-------------------------- DMAx CMAR Configuration ------------------------- * Configure the memory or destination base address with parameter : * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits */ LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); /*-------------------------- DMAx CPAR Configuration ------------------------- * Configure the peripheral or source base address with parameter : * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits */ LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); /*--------------------------- DMAx CNDTR Configuration ----------------------- * Configure the peripheral base address with parameter : * - NbData: DMA_CNDTR_NDT[15:0] bits */ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); return SUCCESS; } /** * @brief Set each @ref LL_DMA_InitTypeDef field to default value. * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. * @retval None */ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) { /* Set DMA_InitStruct fields to default values */ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; DMA_InitStruct->NbData = 0x00000000U; DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; } /** * @} */ /** * @} */ /** * @} */ #endif /* DMA1 || DMA2 */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_exti.c * @author MCD Application Team * @brief EXTI LL module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_ll_exti.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (EXTI) /** @defgroup EXTI_LL EXTI * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup EXTI_LL_Private_Macros * @{ */ #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) #if defined(EXTI_32_63_SUPPORT) #define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) #endif #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) #define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup EXTI_LL_Exported_Functions * @{ */ /** @addtogroup EXTI_LL_EF_Init * @{ */ /** * @brief De-initialize the EXTI registers to their default reset values. * @retval An ErrorStatus enumeration value: * - SUCCESS: EXTI registers are de-initialized * - ERROR: not applicable */ uint32_t LL_EXTI_DeInit(void) { /* Interrupt mask register set to default reset values */ LL_EXTI_WriteReg(IMR, 0x1F800000U); /* Event mask register set to default reset values */ LL_EXTI_WriteReg(EMR, 0x00000000U); /* Rising Trigger selection register set to default reset values */ LL_EXTI_WriteReg(RTSR, 0x00000000U); /* Falling Trigger selection register set to default reset values */ LL_EXTI_WriteReg(FTSR, 0x00000000U); /* Software interrupt event register set to default reset values */ LL_EXTI_WriteReg(SWIER, 0x00000000U); /* Pending register clear */ LL_EXTI_WriteReg(PR, 0x007FFFFFU); #if defined(EXTI_32_63_SUPPORT) /* Interrupt mask register 2 set to default reset values */ #if defined(STM32F334x8) LL_EXTI_WriteReg(IMR2, 0xFFFFFFFEU); #else LL_EXTI_WriteReg(IMR2, 0xFFFFFFFCU); #endif /* Event mask register 2 set to default reset values */ LL_EXTI_WriteReg(EMR2, 0x00000000U); /* Rising Trigger selection register 2 set to default reset values */ LL_EXTI_WriteReg(RTSR2, 0x00000000U); /* Falling Trigger selection register 2 set to default reset values */ LL_EXTI_WriteReg(FTSR2, 0x00000000U); /* Software interrupt event register 2 set to default reset values */ LL_EXTI_WriteReg(SWIER2, 0x00000000U); /* Pending register 2 clear */ LL_EXTI_WriteReg(PR2, 0x00000003U); #endif return SUCCESS; } /** * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. * @retval An ErrorStatus enumeration value: * - SUCCESS: EXTI registers are initialized * - ERROR: not applicable */ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); #if defined(EXTI_32_63_SUPPORT) assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); #endif assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); /* ENABLE LineCommand */ if (EXTI_InitStruct->LineCommand != DISABLE) { assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); /* Configure EXTI Lines in range from 0 to 31 */ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) { switch (EXTI_InitStruct->Mode) { case LL_EXTI_MODE_IT: /* First Disable Event on provided Lines */ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable IT on provided Lines */ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_MODE_EVENT: /* First Disable IT on provided Lines */ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable Event on provided Lines */ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_MODE_IT_EVENT: /* Directly Enable IT & Event on provided Lines */ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); break; default: status = ERROR; break; } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) { switch (EXTI_InitStruct->Trigger) { case LL_EXTI_TRIGGER_RISING: /* First Disable Falling Trigger on provided Lines */ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable Rising Trigger on provided Lines */ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_TRIGGER_FALLING: /* First Disable Rising Trigger on provided Lines */ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable Falling Trigger on provided Lines */ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_TRIGGER_RISING_FALLING: LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); break; default: status = ERROR; break; } } } #if defined(EXTI_32_63_SUPPORT) /* Configure EXTI Lines in range from 32 to 63 */ if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE) { switch (EXTI_InitStruct->Mode) { case LL_EXTI_MODE_IT: /* First Disable Event on provided Lines */ LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); /* Then Enable IT on provided Lines */ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); break; case LL_EXTI_MODE_EVENT: /* First Disable IT on provided Lines */ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); /* Then Enable Event on provided Lines */ LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); break; case LL_EXTI_MODE_IT_EVENT: /* Directly Enable IT & Event on provided Lines */ LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); break; default: status = ERROR; break; } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) { switch (EXTI_InitStruct->Trigger) { case LL_EXTI_TRIGGER_RISING: /* First Disable Falling Trigger on provided Lines */ LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); /* Then Enable IT on provided Lines */ LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); break; case LL_EXTI_TRIGGER_FALLING: /* First Disable Rising Trigger on provided Lines */ LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); /* Then Enable Falling Trigger on provided Lines */ LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); break; case LL_EXTI_TRIGGER_RISING_FALLING: LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); break; default: status = ERROR; break; } } } #endif } /* DISABLE LineCommand */ else { /* De-configure EXTI Lines in range from 0 to 31 */ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); #if defined(EXTI_32_63_SUPPORT) /* De-configure EXTI Lines in range from 32 to 63 */ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); #endif } return status; } /** * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. * @retval None */ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) { EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; #if defined(EXTI_32_63_SUPPORT) EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE; #endif EXTI_InitStruct->LineCommand = DISABLE; EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; } /** * @} */ /** * @} */ /** * @} */ #endif /* defined (EXTI) */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_gpio.c * @author MCD Application Team * @brief GPIO LL module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_ll_gpio.h" #include "stm32f3xx_ll_bus.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) /** @addtogroup GPIO_LL * @{ */ /** MISRA C:2012 deviation rule has been granted for following rules: * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of * range of the shift operator in following API : * LL_GPIO_Init * LL_GPIO_DeInit * LL_GPIO_SetPinMode * LL_GPIO_GetPinMode * LL_GPIO_SetPinSpeed * LL_GPIO_GetPinSpeed * LL_GPIO_SetPinPull * LL_GPIO_GetPinPull * LL_GPIO_GetAFPin_0_7 * LL_GPIO_SetAFPin_0_7 * LL_GPIO_SetAFPin_8_15 * LL_GPIO_GetAFPin_8_15 */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup GPIO_LL_Private_Macros * @{ */ #define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ ((__VALUE__) == LL_GPIO_MODE_ANALOG)) #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) #define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) #define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ ((__VALUE__) == LL_GPIO_PULL_UP) ||\ ((__VALUE__) == LL_GPIO_PULL_DOWN)) #define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ ((__VALUE__) == LL_GPIO_AF_1 ) ||\ ((__VALUE__) == LL_GPIO_AF_2 ) ||\ ((__VALUE__) == LL_GPIO_AF_3 ) ||\ ((__VALUE__) == LL_GPIO_AF_4 ) ||\ ((__VALUE__) == LL_GPIO_AF_5 ) ||\ ((__VALUE__) == LL_GPIO_AF_6 ) ||\ ((__VALUE__) == LL_GPIO_AF_7 ) ||\ ((__VALUE__) == LL_GPIO_AF_8 ) ||\ ((__VALUE__) == LL_GPIO_AF_9 ) ||\ ((__VALUE__) == LL_GPIO_AF_10 ) ||\ ((__VALUE__) == LL_GPIO_AF_11 ) ||\ ((__VALUE__) == LL_GPIO_AF_12 ) ||\ ((__VALUE__) == LL_GPIO_AF_13 ) ||\ ((__VALUE__) == LL_GPIO_AF_14 ) ||\ ((__VALUE__) == LL_GPIO_AF_15 )) /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_LL_Exported_Functions * @{ */ /** @addtogroup GPIO_LL_EF_Init * @{ */ /** * @brief De-initialize GPIO registers (Registers restored to their default values). * @param GPIOx GPIO Port * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); /* Force and Release reset on clock of GPIOx Port */ if (GPIOx == GPIOA) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); } else if (GPIOx == GPIOB) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); } else if (GPIOx == GPIOC) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); } #if defined(GPIOD) else if (GPIOx == GPIOD) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); } #endif /* GPIOD */ #if defined(GPIOE) else if (GPIOx == GPIOE) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); } #endif /* GPIOE */ #if defined(GPIOF) else if (GPIOx == GPIOF) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); } #endif /* GPIOF */ #if defined(GPIOG) else if (GPIOx == GPIOG) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG); } #endif /* GPIOG */ #if defined(GPIOH) else if (GPIOx == GPIOH) { LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH); LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH); } #endif /* GPIOH */ else { status = ERROR; } return (status); } /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content * - ERROR: Not applicable */ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) { uint32_t pinpos; uint32_t currentpin; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); /* ------------------------- Configure the port pins ---------------- */ /* Initialize pinpos on first pin set */ pinpos = POSITION_VAL(GPIO_InitStruct->Pin); /* Configure the port pins */ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) { /* Get current io position */ currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); if (currentpin != 0x00u) { /* Pin Mode configuration */ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); } /* Pull-up Pull down resistor configuration*/ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) { /* Check Alternate parameter */ assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); /* Speed mode configuration */ if (POSITION_VAL(currentpin) < 0x00000008U) { LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); } else { LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } } pinpos++; } if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Output mode parameters */ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); /* Output mode configuration*/ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); } return (SUCCESS); } /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) { /* Reset GPIO init structure parameters values */ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; GPIO_InitStruct->Alternate = LL_GPIO_AF_0; } /** * @} */ /** * @} */ /** * @} */ #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_rcc.c * @author MCD Application Team * @brief RCC LL module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_ll_rcc.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined(RCC) /** @defgroup RCC_LL RCC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @addtogroup RCC_LL_Private_Variables * @{ */ #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) const uint16_t aADCPrescTable[16] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U}; #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ #if defined(RCC_CFGR_SDPRE) const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U}; #endif /* RCC_CFGR_SDPRE */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCC_LL_Private_Macros * @{ */ #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) #elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) #elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) #else #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ #if defined(UART4) && defined(UART5) #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)) #elif defined(UART4) #define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE) #elif defined(UART5) #define IS_LL_RCC_UART_INSTANCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) #endif /* UART4 && UART5*/ #if defined(RCC_CFGR3_I2C2SW) && defined(RCC_CFGR3_I2C3SW) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) #elif defined(RCC_CFGR3_I2C2SW) && !defined(RCC_CFGR3_I2C3SW) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE)) #elif defined(RCC_CFGR3_I2C3SW) && !defined(RCC_CFGR3_I2C2SW) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) #else #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) #endif /* RCC_CFGR3_I2C2SW && RCC_CFGR3_I2C3SW */ #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE) #if defined(USB) #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) #endif /* USB */ #if defined(RCC_CFGR_ADCPRE) #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) #else #if defined(RCC_CFGR2_ADC1PRES) #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC1_CLKSOURCE)) #elif defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34) #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_ADC34_CLKSOURCE)) #else /* RCC_CFGR2_ADCPRE12 */ #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE)) #endif /* RCC_CFGR2_ADC1PRES */ #endif /* RCC_CFGR_ADCPRE */ #if defined(RCC_CFGR_SDPRE) #define IS_LL_RCC_SDADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDADC_CLKSOURCE)) #endif /* RCC_CFGR_SDPRE */ #if defined(CEC) #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) #endif /* CEC */ #if defined(RCC_CFGR3_TIMSW) #if defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \ && defined(RCC_CFGR3_TIM17SW) && defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \ && defined(RCC_CFGR3_TIM34SW) #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM20_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE)) #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \ && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && defined(RCC_CFGR3_TIM2SW) \ && defined(RCC_CFGR3_TIM34SW) #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM2_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM34_CLKSOURCE)) #elif defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \ && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \ && !defined(RCC_CFGR3_TIM34SW) #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM8_CLKSOURCE)) #elif !defined(RCC_CFGR3_TIM8SW) && defined(RCC_CFGR3_TIM15SW) && defined(RCC_CFGR3_TIM16SW) \ && defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \ && !defined(RCC_CFGR3_TIM34SW) #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM16_CLKSOURCE) \ || ((__VALUE__) == LL_RCC_TIM17_CLKSOURCE)) #elif !defined(RCC_CFGR3_TIM8SW) && !defined(RCC_CFGR3_TIM15SW) && !defined(RCC_CFGR3_TIM16SW) \ && !defined(RCC_CFGR3_TIM17SW) && !defined(RCC_CFGR3_TIM20SW) && !defined(RCC_CFGR3_TIM2SW) \ && !defined(RCC_CFGR3_TIM34SW) #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)) #else #error "Miss macro" #endif /* RCC_CFGR3_TIMxSW */ #endif /* RCC_CFGR3_TIMSW */ #if defined(HRTIM1) #define IS_LL_RCC_HRTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_HRTIM1_CLKSOURCE)) #endif /* HRTIM1 */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCC_LL_Private_Functions RCC Private functions * @{ */ uint32_t RCC_GetSystemClockFreq(void); uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); uint32_t RCC_PLL_GetFreqDomain_SYS(void); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_LL_Exported_Functions * @{ */ /** @addtogroup RCC_LL_EF_Init * @{ */ /** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE and PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval An ErrorStatus enumeration value: * - SUCCESS: RCC registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_RCC_DeInit(void) { __IO uint32_t vl_mask; /* Set HSION bit */ LL_RCC_HSI_Enable(); /* Wait for HSI READY bit */ while(LL_RCC_HSI_IsReady() != 1U) {} /* Set HSITRIM bits to the reset value*/ LL_RCC_HSI_SetCalibTrimming(0x10U); /* Reset SW, HPRE, PPRE and MCOSEL bits */ vl_mask = 0xFFFFFFFFU; CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 |\ RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL)); /* Write new value in CFGR register */ LL_RCC_WriteReg(CFGR, vl_mask); /* Wait till system clock source is ready */ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {} /* Read CR register */ vl_mask = LL_RCC_ReadReg(CR); /* Reset HSEON, CSSON, PLLON bits */ CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); /* Write new value in CR register */ LL_RCC_WriteReg(CR, vl_mask); /* Wait for PLL READY bit to be reset */ while(LL_RCC_PLL_IsReady() != 0U) {} /* Reset HSEBYP bit */ LL_RCC_HSE_DisableBypass(); /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); /* Reset CFGR2 register */ LL_RCC_WriteReg(CFGR2, 0x00000000U); /* Reset CFGR3 register */ LL_RCC_WriteReg(CFGR3, 0x00000000U); /* Clear pending flags */ vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC |\ LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC); /* Write new value in CIR register */ LL_RCC_WriteReg(CIR, vl_mask); /* Disable all interrupts */ LL_RCC_WriteReg(CIR, 0x00000000U); /* Clear reset flags */ LL_RCC_ClearResetFlags(); return SUCCESS; } /** * @} */ /** @addtogroup RCC_LL_EF_Get_Freq * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks * and different peripheral clocks available on the device. * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) * @note If SYSCLK source is PLL, function returns values based on * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. * @note (**) HSI_VALUE is a defined constant but the real value may vary * depending on the variations in voltage and temperature. * @note (***) HSE_VALUE is a defined constant, user has to ensure that * HSE_VALUE is same as the real frequency of the crystal used. * Otherwise, this function may have wrong result. * @note The result of this function could be incorrect when using fractional * value for HSE crystal. * @note This function can be used by the user application to compute the * baud-rate for the communication peripherals or configure other parameters. * @{ */ /** * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function * must be called to update structure fields. Otherwise, any * configuration based on this function will be incorrect. * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies * @retval None */ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) { /* Get SYSCLK frequency */ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); /* HCLK clock frequency */ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); /* PCLK1 clock frequency */ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); /* PCLK2 clock frequency */ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); } /** * @brief Return USARTx clock frequency * @param USARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USART1_CLKSOURCE * @arg @ref LL_RCC_USART2_CLKSOURCE (*) * @arg @ref LL_RCC_USART3_CLKSOURCE (*) * * (*) value not defined in all devices. * @retval USART clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready */ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) { uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); #if defined(RCC_CFGR3_USART1SW) if (USARTxSource == LL_RCC_USART1_CLKSOURCE) { /* USART1CLK clock frequency */ switch (LL_RCC_GetUSARTClockSource(USARTxSource)) { case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ usart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { usart_frequency = LSE_VALUE; } break; #if defined(RCC_CFGR3_USART1SW_PCLK1) case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); #else case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ default: usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); #endif /* RCC_CFGR3_USART1SW_PCLK1 */ break; } } #endif /* RCC_CFGR3_USART1SW */ #if defined(RCC_CFGR3_USART2SW) if (USARTxSource == LL_RCC_USART2_CLKSOURCE) { /* USART2CLK clock frequency */ switch (LL_RCC_GetUSARTClockSource(USARTxSource)) { case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ usart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #endif /* RCC_CFGR3_USART2SW */ #if defined(RCC_CFGR3_USART3SW) if (USARTxSource == LL_RCC_USART3_CLKSOURCE) { /* USART3CLK clock frequency */ switch (LL_RCC_GetUSARTClockSource(USARTxSource)) { case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ usart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { usart_frequency = HSI_VALUE; } break; case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { usart_frequency = LSE_VALUE; } break; case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ default: usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #endif /* RCC_CFGR3_USART3SW */ return usart_frequency; } #if defined(UART4) || defined(UART5) /** * @brief Return UARTx clock frequency * @param UARTxSource This parameter can be one of the following values: * @arg @ref LL_RCC_UART4_CLKSOURCE * @arg @ref LL_RCC_UART5_CLKSOURCE * @retval UART clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready */ uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) { uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource)); #if defined(UART4) if (UARTxSource == LL_RCC_UART4_CLKSOURCE) { /* UART4CLK clock frequency */ switch (LL_RCC_GetUARTClockSource(UARTxSource)) { case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */ uart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #endif /* UART4 */ #if defined(UART5) if (UARTxSource == LL_RCC_UART5_CLKSOURCE) { /* UART5CLK clock frequency */ switch (LL_RCC_GetUARTClockSource(UARTxSource)) { case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */ uart_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ if (LL_RCC_HSI_IsReady()) { uart_frequency = HSI_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ if (LL_RCC_LSE_IsReady()) { uart_frequency = LSE_VALUE; } break; case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ default: uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); break; } } #endif /* UART5 */ return uart_frequency; } #endif /* UART4 || UART5 */ /** * @brief Return I2Cx clock frequency * @param I2CxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2C1_CLKSOURCE * @arg @ref LL_RCC_I2C2_CLKSOURCE (*) * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) * * (*) value not defined in all devices * @retval I2C clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready */ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) { uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); /* I2C1 CLK clock frequency */ if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) { switch (LL_RCC_GetI2CClockSource(I2CxSource)) { case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ i2c_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ default: if (LL_RCC_HSI_IsReady()) { i2c_frequency = HSI_VALUE; } break; } } #if defined(RCC_CFGR3_I2C2SW) /* I2C2 CLK clock frequency */ if (I2CxSource == LL_RCC_I2C2_CLKSOURCE) { switch (LL_RCC_GetI2CClockSource(I2CxSource)) { case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ i2c_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ default: if (LL_RCC_HSI_IsReady()) { i2c_frequency = HSI_VALUE; } break; } } #endif /*RCC_CFGR3_I2C2SW*/ #if defined(RCC_CFGR3_I2C3SW) /* I2C3 CLK clock frequency */ if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) { switch (LL_RCC_GetI2CClockSource(I2CxSource)) { case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ i2c_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ default: if (LL_RCC_HSI_IsReady()) { i2c_frequency = HSI_VALUE; } break; } } #endif /*RCC_CFGR3_I2C3SW*/ return i2c_frequency; } #if defined(RCC_CFGR_I2SSRC) /** * @brief Return I2Sx clock frequency * @param I2SxSource This parameter can be one of the following values: * @arg @ref LL_RCC_I2S_CLKSOURCE * @retval I2S clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) { uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); /* I2S1CLK clock frequency */ switch (LL_RCC_GetI2SClockSource(I2SxSource)) { case LL_RCC_I2S_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */ i2s_frequency = RCC_GetSystemClockFreq(); break; case LL_RCC_I2S_CLKSOURCE_PIN: /*!< External clock selected as I2S clock source */ default: i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NA; break; } return i2s_frequency; } #endif /* RCC_CFGR_I2SSRC */ #if defined(USB) /** * @brief Return USBx clock frequency * @param USBxSource This parameter can be one of the following values: * @arg @ref LL_RCC_USB_CLKSOURCE * @retval USB clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected */ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) { uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); /* USBCLK clock frequency */ switch (LL_RCC_GetUSBClockSource(USBxSource)) { case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ if (LL_RCC_PLL_IsReady()) { usb_frequency = RCC_PLL_GetFreqDomain_SYS(); } break; case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock used as USB clock source */ default: if (LL_RCC_PLL_IsReady()) { usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U; } break; } return usb_frequency; } #endif /* USB */ #if defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) /** * @brief Return ADCx clock frequency * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE (*) * @arg @ref LL_RCC_ADC1_CLKSOURCE (*) * @arg @ref LL_RCC_ADC12_CLKSOURCE (*) * @arg @ref LL_RCC_ADC34_CLKSOURCE (*) * * (*) value not defined in all devices * @retval ADC clock frequency (in Hz) */ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) { uint32_t adc_prescaler = 0U; uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); /* Get ADC prescaler */ adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource); #if defined(RCC_CFGR_ADCPRE) /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U); #else if ((adc_prescaler & 0x0000FFFFU) == ((uint32_t)0x00000000U)) { /* ADC frequency = HCLK frequency */ adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()); } else { /* ADC frequency = PCLK2 frequency / ADC prescaler (from 1 to 256) */ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) / (aADCPrescTable[((adc_prescaler & 0x0000FFFFU) >> POSITION_VAL(ADCxSource)) & 0xFU]); } #endif /* RCC_CFGR_ADCPRE */ return adc_frequency; } #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ #if defined(RCC_CFGR_SDPRE) /** * @brief Return SDADCx clock frequency * @param SDADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_SDADC_CLKSOURCE * @retval SDADC clock frequency (in Hz) */ uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource) { uint32_t sdadc_prescaler = 0U; uint32_t sdadc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_SDADC_CLKSOURCE(SDADCxSource)); /* Get SDADC prescaler */ sdadc_prescaler = LL_RCC_GetSDADCClockSource(SDADCxSource); /* SDADC frequency = SYSTEM frequency / SDADC prescaler (from 2 to 48) */ sdadc_frequency = RCC_GetSystemClockFreq() / (aSDADCPrescTable[(sdadc_prescaler >> POSITION_VAL(SDADCxSource)) & 0xFU]); return sdadc_frequency; } #endif /*RCC_CFGR_SDPRE */ #if defined(CEC) /** * @brief Return CECx clock frequency * @param CECxSource This parameter can be one of the following values: * @arg @ref LL_RCC_CEC_CLKSOURCE * @retval CEC clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready */ uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) { uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); /* CECCLK clock frequency */ switch (LL_RCC_GetCECClockSource(CECxSource)) { case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */ if (LL_RCC_HSI_IsReady()) { cec_frequency = HSI_VALUE / 244U; } break; case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */ default: if (LL_RCC_LSE_IsReady()) { cec_frequency = LSE_VALUE; } break; } return cec_frequency; } #endif /* CEC */ #if defined(RCC_CFGR3_TIMSW) /** * @brief Return TIMx clock frequency * @param TIMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_TIM1_CLKSOURCE * @arg @ref LL_RCC_TIM8_CLKSOURCE (*) * @arg @ref LL_RCC_TIM15_CLKSOURCE (*) * @arg @ref LL_RCC_TIM16_CLKSOURCE (*) * @arg @ref LL_RCC_TIM17_CLKSOURCE (*) * @arg @ref LL_RCC_TIM20_CLKSOURCE (*) * @arg @ref LL_RCC_TIM2_CLKSOURCE (*) * @arg @ref LL_RCC_TIM34_CLKSOURCE (*) * * (*) value not defined in all devices * @retval TIM clock frequency (in Hz) */ uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource) { uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource)); if (TIMxSource == LL_RCC_TIM1_CLKSOURCE) { /* TIM1CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM1_CLKSOURCE) == LL_RCC_TIM1_CLKSOURCE_PCLK2) { /* PCLK2 used as TIM1 clock source */ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM1_CLKSOURCE_PLL */ { /* PLL clock used as TIM1 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #if defined(RCC_CFGR3_TIM8SW) if (TIMxSource == LL_RCC_TIM8_CLKSOURCE) { /* TIM8CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM8_CLKSOURCE) == LL_RCC_TIM8_CLKSOURCE_PCLK2) { /* PCLK2 used as TIM8 clock source */ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM8_CLKSOURCE_PLL */ { /* PLL clock used as TIM8 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #endif /*RCC_CFGR3_TIM8SW*/ #if defined(RCC_CFGR3_TIM15SW) if (TIMxSource == LL_RCC_TIM15_CLKSOURCE) { /* TIM15CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM15_CLKSOURCE) == LL_RCC_TIM15_CLKSOURCE_PCLK2) { /* PCLK2 used as TIM15 clock source */ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM15_CLKSOURCE_PLL */ { /* PLL clock used as TIM15 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #endif /*RCC_CFGR3_TIM15SW*/ #if defined(RCC_CFGR3_TIM16SW) if (TIMxSource == LL_RCC_TIM16_CLKSOURCE) { /* TIM16CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM16_CLKSOURCE) == LL_RCC_TIM16_CLKSOURCE_PCLK2) { /* PCLK2 used as TIM16 clock source */ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM16_CLKSOURCE_PLL */ { /* PLL clock used as TIM16 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #endif /*RCC_CFGR3_TIM16SW*/ #if defined(RCC_CFGR3_TIM17SW) if (TIMxSource == LL_RCC_TIM17_CLKSOURCE) { /* TIM17CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM17_CLKSOURCE) == LL_RCC_TIM17_CLKSOURCE_PCLK2) { /* PCLK2 used as TIM17 clock source */ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM17_CLKSOURCE_PLL */ { /* PLL clock used as TIM17 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #endif /*RCC_CFGR3_TIM17SW*/ #if defined(RCC_CFGR3_TIM20SW) if (TIMxSource == LL_RCC_TIM20_CLKSOURCE) { /* TIM20CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM20_CLKSOURCE) == LL_RCC_TIM20_CLKSOURCE_PCLK2) { /* PCLK2 used as TIM20 clock source */ tim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM20_CLKSOURCE_PLL */ { /* PLL clock used as TIM20 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #endif /*RCC_CFGR3_TIM20SW*/ #if defined(RCC_CFGR3_TIM2SW) if (TIMxSource == LL_RCC_TIM2_CLKSOURCE) { /* TIM2CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM2_CLKSOURCE) == LL_RCC_TIM2_CLKSOURCE_PCLK1) { /* PCLK1 used as TIM2 clock source */ tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM2_CLKSOURCE_PLL */ { /* PLL clock used as TIM2 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #endif /*RCC_CFGR3_TIM2SW*/ #if defined(RCC_CFGR3_TIM34SW) if (TIMxSource == LL_RCC_TIM34_CLKSOURCE) { /* TIM3/4 CLK clock frequency */ if (LL_RCC_GetTIMClockSource(LL_RCC_TIM34_CLKSOURCE) == LL_RCC_TIM34_CLKSOURCE_PCLK1) { /* PCLK1 used as TIM3/4 clock source */ tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_TIM34_CLKSOURCE_PLL */ { /* PLL clock used as TIM3/4 clock source */ tim_frequency = RCC_PLL_GetFreqDomain_SYS(); } } #endif /*RCC_CFGR3_TIM34SW*/ return tim_frequency; } #endif /*RCC_CFGR3_TIMSW*/ #if defined(HRTIM1) /** * @brief Return HRTIMx clock frequency * @param HRTIMxSource This parameter can be one of the following values: * @arg @ref LL_RCC_HRTIM1_CLKSOURCE * @retval HRTIM clock frequency (in Hz) */ uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource) { uint32_t hrtim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; /* Check parameter */ assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource)); /* HRTIM1CLK clock frequency */ if (LL_RCC_GetHRTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2) { /* PCLK2 used as HRTIM1 clock source */ hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); } else /* LL_RCC_HRTIM1_CLKSOURCE_PLL */ { /* PLL clock used as HRTIM1 clock source */ hrtim_frequency = RCC_PLL_GetFreqDomain_SYS(); } return hrtim_frequency; } #endif /* HRTIM1 */ /** * @} */ /** * @} */ /** @addtogroup RCC_LL_Private_Functions * @{ */ /** * @brief Return SYSTEM clock frequency * @retval SYSTEM clock frequency (in Hz) */ uint32_t RCC_GetSystemClockFreq(void) { uint32_t frequency = 0U; /* Get SYSCLK source -------------------------------------------------------*/ switch (LL_RCC_GetSysClkSource()) { case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ frequency = HSI_VALUE; break; case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ frequency = HSE_VALUE; break; case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ frequency = RCC_PLL_GetFreqDomain_SYS(); break; default: frequency = HSI_VALUE; break; } return frequency; } /** * @brief Return HCLK clock frequency * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK clock frequency (in Hz) */ uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); } /** * @brief Return PCLK1 clock frequency * @param HCLK_Frequency HCLK clock frequency * @retval PCLK1 clock frequency (in Hz) */ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) { /* PCLK1 clock frequency */ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); } /** * @brief Return PCLK2 clock frequency * @param HCLK_Frequency HCLK clock frequency * @retval PCLK2 clock frequency (in Hz) */ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) { /* PCLK2 clock frequency */ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); } /** * @brief Return PLL clock frequency used for system domain * @retval PLL clock frequency (in Hz) */ uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq = 0U, pllsource = 0U; /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ /* Get PLL source */ pllsource = LL_RCC_PLL_GetMainSource(); switch (pllsource) { #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE; #else case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ pllinputfreq = HSI_VALUE / 2U; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllinputfreq = HSE_VALUE; break; default: #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) pllinputfreq = HSI_VALUE; #else pllinputfreq = HSI_VALUE / 2U; #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ break; } #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv()); #else return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator()); #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ } /** * @} */ /** * @} */ #endif /* defined(RCC) */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_tim.c * @author MCD Application Team * @brief TIM LL module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_ll_tim.h" #include "stm32f3xx_ll_bus.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F3xx_LL_Driver * @{ */ #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20) /** @addtogroup TIM_LL * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup TIM_LL_Private_Macros * @{ */ #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) #if defined(TIM_CCMR1_OC1M_3) #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) #else #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) #endif #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) #if defined(TIM_BDTR_BKF) #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) #endif /* TIM_BDTR_BKF */ #if defined(TIM_BDTR_BK2E) #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) #endif /* TIM_BDTR_BK2E */ #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); #if defined(TIM_CCER_CC5E) static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); #endif /* TIM_CCER_CC5E */ #if defined(TIM_CCER_CC6E) static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); #endif /* TIM_CCER_CC6E */ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIM_LL_Exported_Functions * @{ */ /** @addtogroup TIM_LL_EF_Init * @{ */ /** * @brief Set TIMx registers to their reset values. * @param TIMx Timer instance * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: invalid TIMx instance */ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) { ErrorStatus result = SUCCESS; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); if (TIMx == TIM2) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } #if defined(TIM1) else if (TIMx == TIM1) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); } #endif #if defined(TIM3) else if (TIMx == TIM3) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); } #endif #if defined(TIM4) else if (TIMx == TIM4) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); } #endif #if defined(TIM5) else if (TIMx == TIM5) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); } #endif #if defined(TIM6) else if (TIMx == TIM6) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); } #endif #if defined(TIM7) else if (TIMx == TIM7) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); } #endif #if defined(TIM8) else if (TIMx == TIM8) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); } #endif #if defined(TIM12) else if (TIMx == TIM12) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); } #endif #if defined(TIM13) else if (TIMx == TIM13) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); } #endif #if defined(TIM14) else if (TIMx == TIM14) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); } #endif #if defined(TIM15) else if (TIMx == TIM15) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); } #endif #if defined(TIM16) else if (TIMx == TIM16) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); } #endif #if defined(TIM17) else if (TIMx == TIM17) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); } #endif #if defined(TIM18) else if (TIMx == TIM18) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18); } #endif #if defined(TIM19) else if (TIMx == TIM19) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19); } #endif #if defined(TIM20) else if (TIMx == TIM20) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20); } #endif else { result = ERROR; } return result; } /** * @brief Set the fields of the time base unit configuration data structure * to their default values. * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) * @retval None */ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) { /* Set the default configuration */ TIM_InitStruct->Prescaler = (uint16_t)0x0000; TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; } /** * @brief Configure the TIMx time base unit. * @param TIMx Timer Instance * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(TIMx)); assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { /* Select the Counter Mode */ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); } /* Write to TIMx CR1 */ LL_TIM_WriteReg(TIMx, CR1, tmpcr1); /* Set the Autoreload value */ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); /* Set the Prescaler value */ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); } /* Generate an update event to reload the Prescaler and the repetition counter value (if applicable) immediately */ LL_TIM_GenerateEvent_UPDATE(TIMx); return SUCCESS; } /** * @brief Set the fields of the TIMx output channel configuration data * structure to their default values. * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) * @retval None */ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { /* Set the default configuration */ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; TIM_OC_InitStruct->CompareValue = 0x00000000U; TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; } /** * @brief Configure the TIMx output channel. * @param TIMx Timer Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) * @note OC5 and OC6 are not available for all F3 devices * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; switch (Channel) { case LL_TIM_CHANNEL_CH1: result = OC1Config(TIMx, TIM_OC_InitStruct); break; case LL_TIM_CHANNEL_CH2: result = OC2Config(TIMx, TIM_OC_InitStruct); break; case LL_TIM_CHANNEL_CH3: result = OC3Config(TIMx, TIM_OC_InitStruct); break; case LL_TIM_CHANNEL_CH4: result = OC4Config(TIMx, TIM_OC_InitStruct); break; #if defined(TIM_CCER_CC5E) case LL_TIM_CHANNEL_CH5: result = OC5Config(TIMx, TIM_OC_InitStruct); break; case LL_TIM_CHANNEL_CH6: result = OC6Config(TIMx, TIM_OC_InitStruct); break; #endif /* TIM_CCER_CC5E */ default: break; } return result; } /** * @brief Set the fields of the TIMx input channel configuration data * structure to their default values. * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) * @retval None */ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Set the default configuration */ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; } /** * @brief Configure the TIMx input channel. * @param TIMx Timer Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_TIM_CHANNEL_CH1 * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; switch (Channel) { case LL_TIM_CHANNEL_CH1: result = IC1Config(TIMx, TIM_IC_InitStruct); break; case LL_TIM_CHANNEL_CH2: result = IC2Config(TIMx, TIM_IC_InitStruct); break; case LL_TIM_CHANNEL_CH3: result = IC3Config(TIMx, TIM_IC_InitStruct); break; case LL_TIM_CHANNEL_CH4: result = IC4Config(TIMx, TIM_IC_InitStruct); break; default: break; } return result; } /** * @brief Fills each TIM_EncoderInitStruct field with its default value * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) * @retval None */ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { /* Set the default configuration */ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; } /** * @brief Configure the encoder interface of the timer instance. * @param TIMx Timer Instance * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Get the TIMx CCMR1 register value */ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Configure TI1 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); /* Configure TI2 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Set encoder mode */ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); /* Write to TIMx CCMR1 */ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; } #if defined TIM_CR2_MMS2 /** * @brief Set the fields of the TIMx Hall sensor interface configuration data * structure to their default values. * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) * @retval None */ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { /* Set the default configuration */ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; TIM_HallSensorInitStruct->CommutationDelay = 0U; } /** * @brief Configure the Hall sensor interface of the timer instance. * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR * to the TI1 input channel * @note TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED. * @note Channel 1 is configured as input, IC1 is mapped on TRC. * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed * between 2 changes on the inputs. It gives information about motor speed. * @note Channel 2 is configured in output PWM 2 mode. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. * @note OC2REF is selected as trigger output on TRGO. * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; uint32_t tmpccer; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR1 register value */ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx SMCR register value */ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ tmpcr2 |= TIM_CR2_TI1S; /* OC2REF signal is used as trigger output (TRGO) */ tmpcr2 |= LL_TIM_TRGO_OC2REF; /* Configure the slave mode controller */ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); tmpsmcr |= LL_TIM_TS_TI1F_ED; tmpsmcr |= LL_TIM_SLAVEMODE_RESET; /* Configure input channel 1 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); /* Configure input channel 2 */ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx SMCR */ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); /* Write to TIMx CCMR1 */ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); /* Write to TIMx CCR2 */ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); return SUCCESS; } #endif /* TIM_CR2_MMS2 */ /** * @brief Set the fields of the Break and Dead Time configuration data structure * to their default values. * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) * @retval None */ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { /* Set the default configuration */ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; #if defined(TIM_BDTR_BKF) TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; #endif /* TIM_BDTR_BKF */ #if defined(TIM_BDTR_BK2E) TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; #endif /* TIM_BDTR_BK2E */ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; } /** * @brief Configure the Break and Dead Time feature of the timer instance. * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR * and DTG[7:0] can be write-locked depending on the LOCK configuration, it * can be necessary to configure all of them during the first write access to * the TIMx_BDTR register. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); #if defined(TIM_BDTR_BKF) if (IS_TIM_ADVANCED_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); } #endif /* TIM_BDTR_BKF */ #if defined(TIM_BDTR_BK2E) if (IS_TIM_BKIN2_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); /* Set the BREAK2 input related BDTR bit-fields */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); } #endif /* TIM_BDTR_BK2E */ /* Set TIMx_BDTR */ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); return SUCCESS; } /** * @} */ /** * @} */ /** @addtogroup TIM_LL_Private_Functions TIM Private Functions * @brief Private functions * @{ */ /** * @brief Configure the TIMx output channel 1. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR1 register value */ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); /* Reset Capture/Compare selection Bits */ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); /* Set the Output Compare Mode */ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); /* Set the complementary output State */ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); } /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx CCMR1 */ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; } /** * @brief Configure the TIMx output channel 2. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR1 register value */ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); /* Reset Capture/Compare selection Bits */ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); /* Set the complementary output State */ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); #if defined(STM32F373xC) || defined(STM32F378xx) #else /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); #endif } /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx CCMR1 */ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; } /** * @brief Configure the TIMx output channel 3. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR2 register value */ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); /* Reset Capture/Compare selection Bits */ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); /* Set the complementary output State */ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); #if defined(STM32F373xC) || defined(STM32F378xx) #else /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); /* Set the complementary output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); #endif } /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx CCMR2 */ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; } /** * @brief Configure the TIMx output channel 4. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CR2 register value */ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); /* Get the TIMx CCMR2 register value */ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); /* Reset Capture/Compare selection Bits */ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); #if defined(STM32F373xC) || defined(STM32F378xx) #else /* Set the Output Idle state */ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); #endif } /* Write to TIMx CR2 */ LL_TIM_WriteReg(TIMx, CR2, tmpcr2); /* Write to TIMx CCMR2 */ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; } #if defined(TIM_CCER_CC5E) /** * @brief Configure the TIMx output channel 5. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure * @note OC5 is not available for all F3 devices * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 5: Reset the CC5E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CCMR3 register value */ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); } /* Write to TIMx CCMR3 */ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; } /** * @brief Configure the TIMx output channel 6. * @param TIMx Timer Instance * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure * @note OC6 is not available for all F3 devices * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(TIMx)); assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 5: Reset the CC6E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); /* Get the TIMx CCER register value */ tmpccer = LL_TIM_ReadReg(TIMx, CCER); /* Get the TIMx CCMR3 register value */ tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); /* Select the Output Compare Mode */ MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); /* Set the Output Compare Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); /* Set the Output State */ MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); /* Set the Output Idle state */ MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); } /* Write to TIMx CCMR3 */ LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); /* Set the Capture Compare Register value */ LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); /* Write to TIMx CCER */ LL_TIM_WriteReg(TIMx, CCER, tmpccer); return SUCCESS; } #endif /* TIM_CCER_CC5E */ /** * @brief Configure the TIMx input channel 1. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; /* Select the Input and set the filter and the prescaler value */ MODIFY_REG(TIMx->CCMR1, (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); /* Select the Polarity and set the CC1E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P | TIM_CCER_CC1NP), (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); return SUCCESS; } /** * @brief Configure the TIMx input channel 2. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; /* Select the Input and set the filter and the prescaler value */ MODIFY_REG(TIMx->CCMR1, (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); /* Select the Polarity and set the CC2E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC2P | TIM_CCER_CC2NP), ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); return SUCCESS; } /** * @brief Configure the TIMx input channel 3. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; /* Select the Input and set the filter and the prescaler value */ MODIFY_REG(TIMx->CCMR2, (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); /* Select the Polarity and set the CC3E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC3P | TIM_CCER_CC3NP), ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); return SUCCESS; } /** * @brief Configure the TIMx input channel 4. * @param TIMx Timer Instance * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; /* Select the Input and set the filter and the prescaler value */ MODIFY_REG(TIMx->CCMR2, (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); /* Select the Polarity and set the CC2E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); return SUCCESS; } /** * @} */ /** * @} */ #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c ================================================ /** ****************************************************************************** * @file stm32f3xx_ll_utils.c * @author MCD Application Team * @brief UTILS LL module driver. ****************************************************************************** * @attention * *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx_ll_rcc.h" #include "stm32f3xx_ll_utils.h" #include "stm32f3xx_ll_system.h" #include "stm32f3xx_ll_pwr.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F3xx_LL_Driver * @{ */ /** @addtogroup UTILS_LL * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup UTILS_LL_Private_Constants * @{ */ /* Defines used for PLL range */ #define UTILS_PLL_OUTPUT_MAX 72000000U /*!< Frequency max for PLL output, in Hz */ /* Defines used for HSE range */ #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ #define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ /* Defines used for FLASH latency according to SYSCLK Frequency */ #define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ #define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup UTILS_LL_Private_Macros * @{ */ #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ || ((__VALUE__) == LL_RCC_APB1_DIV_16)) #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ || ((__VALUE__) == LL_RCC_APB2_DIV_16)) #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ || ((__VALUE__) == LL_RCC_PLL_MUL_16)) #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX) #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup UTILS_LL_Private_Functions UTILS Private functions * @{ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); #if defined(FLASH_ACR_LATENCY) static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); #endif /* FLASH_ACR_LATENCY */ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup UTILS_LL_Exported_Functions * @{ */ /** @addtogroup UTILS_LL_EF_DELAY * @{ */ /** * @brief This function configures the Cortex-M SysTick source to have 1ms time base. * @note When a RTOS is used, it is recommended to avoid changing the Systick * configuration by calling this function, for a delay use rather osDelay RTOS service. * @param HCLKFrequency HCLK frequency in Hz * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq * @retval None */ void LL_Init1msTick(uint32_t HCLKFrequency) { /* Use frequency provided in argument */ LL_InitTick(HCLKFrequency, 1000U); } /** * @brief This function provides accurate delay (in milliseconds) based * on SysTick counter flag * @note When a RTOS is used, it is recommended to avoid using blocking delay * and use rather osDelay service. * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which * will configure Systick to 1ms * @param Delay specifies the delay time length, in milliseconds. * @retval None */ void LL_mDelay(uint32_t Delay) { __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ /* Add this code to indicate that local variable is not used */ ((void)tmp); /* Add a period to guaranty minimum wait */ if (Delay < LL_MAX_DELAY) { Delay++; } while (Delay) { if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) { Delay--; } } } /** * @} */ /** @addtogroup UTILS_EF_SYSTEM * @brief System Configuration functions * @verbatim =============================================================================== ##### System Configuration functions ##### =============================================================================== [..] System, AHB and APB buses clocks configuration (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72000000 Hz. @endverbatim @internal Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: (++) +-----------------------------------------------+ (++) | Latency | SYSCLK clock frequency (MHz) | (++) |---------------|-------------------------------| (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | (++) |---------------|-------------------------------| (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | (++) |---------------|-------------------------------| (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | (++) +-----------------------------------------------+ @endinternal * @{ */ /** * @brief This function sets directly SystemCoreClock CMSIS variable. * @note Variable can be calculated also through SystemCoreClockUpdate function. * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) * @retval None */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) { /* HCLK clock frequency */ SystemCoreClock = HCLKFrequency; } /** * @brief This function configures system clock with HSI as clock source of the PLL * @note The application need to ensure that PLL is disabled. * @note Function is based on the following formula: * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) * - PREDIV: Set to 2 for few devices * - PLLMUL: The application software must set correctly the PLL multiplication factor to * not exceed 72MHz * @note FLASH latency can be modified through this function. * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains * the configuration information for the PLL. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains * the configuration information for the BUS prescalers. * @retval An ErrorStatus enumeration value: * - SUCCESS: Max frequency configuration done * - ERROR: Max frequency configuration not done */ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U; /* Check if one of the PLL is enabled */ if (UTILS_PLL_IsBusy() == SUCCESS) { #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) /* Check PREDIV value */ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); #else /* Force PREDIV value to 2 */ UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ /* Calculate the new PLL output frequency */ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); /* Enable HSI if not enabled */ if (LL_RCC_HSI_IsReady() != 1U) { LL_RCC_HSI_Enable(); while (LL_RCC_HSI_IsReady() != 1U) { /* Wait for HSI ready */ } } /* Configure PLL */ #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); #else LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); } else { /* Current PLL configuration cannot be modified */ status = ERROR; } return status; } /** * @brief This function configures system clock with HSE as clock source of the PLL * @note The application need to ensure that PLL is disabled. * @note Function is based on the following formula: * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) * - PREDIV: Set to 2 for few devices * - PLLMUL: The application software must set correctly the PLL multiplication factor to * not exceed @ref UTILS_PLL_OUTPUT_MAX * @note FLASH latency can be modified through this function. * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000 * @param HSEBypass This parameter can be one of the following values: * @arg @ref LL_UTILS_HSEBYPASS_ON * @arg @ref LL_UTILS_HSEBYPASS_OFF * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains * the configuration information for the PLL. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains * the configuration information for the BUS prescalers. * @retval An ErrorStatus enumeration value: * - SUCCESS: Max frequency configuration done * - ERROR: Max frequency configuration not done */ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; uint32_t pllfreq = 0U; /* Check the parameters */ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); /* Check if one of the PLL is enabled */ if (UTILS_PLL_IsBusy() == SUCCESS) { /* Check PREDIV value */ #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); #else assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ /* Calculate the new PLL output frequency */ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); /* Enable HSE if not enabled */ if (LL_RCC_HSE_IsReady() != 1U) { /* Check if need to enable HSE bypass feature or not */ if (HSEBypass == LL_UTILS_HSEBYPASS_ON) { LL_RCC_HSE_EnableBypass(); } else { LL_RCC_HSE_DisableBypass(); } /* Enable HSE */ LL_RCC_HSE_Enable(); while (LL_RCC_HSE_IsReady() != 1U) { /* Wait for HSE ready */ } } /* Configure PLL */ #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); #else LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ /* Enable PLL and switch system clock to PLL */ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); } else { /* Current PLL configuration cannot be modified */ status = ERROR; } return status; } /** * @} */ /** * @} */ /** @addtogroup UTILS_LL_Private_Functions * @{ */ /** * @brief Update number of Flash wait states in line with new frequency and current voltage range. * @param Frequency SYSCLK frequency * @retval An ErrorStatus enumeration value: * - SUCCESS: Latency has been modified * - ERROR: Latency cannot be modified */ #if defined(FLASH_ACR_LATENCY) static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) { ErrorStatus status = SUCCESS; uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ /* Frequency cannot be equal to 0 */ if (Frequency == 0U) { status = ERROR; } else { if (Frequency > UTILS_LATENCY2_FREQ) { /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */ latency = LL_FLASH_LATENCY_2; } else { if (Frequency > UTILS_LATENCY1_FREQ) { /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ latency = LL_FLASH_LATENCY_1; } /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ } LL_FLASH_SetLatency(latency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (LL_FLASH_GetLatency() != latency) { status = ERROR; } } return status; } #endif /* FLASH_ACR_LATENCY */ /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains * the configuration information for the PLL. * @retval PLL output frequency (in Hz) */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) { uint32_t pllfreq = 0U; /* Check the parameters */ assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); /* Check different PLL parameters according to RM */ /* The application software must set correctly the PLL multiplication factor to not exceed @ref UTILS_PLL_OUTPUT_MAX */ #if defined(RCC_PLLSRC_PREDIV1_SUPPORT) pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); #else pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); return pllfreq; } /** * @brief Function to check that PLL can be modified * @retval An ErrorStatus enumeration value: * - SUCCESS: PLL modification can be done * - ERROR: PLL is busy */ static ErrorStatus UTILS_PLL_IsBusy(void) { ErrorStatus status = SUCCESS; /* Check if PLL is busy*/ if (LL_RCC_PLL_IsReady() != 0U) { /* PLL configuration cannot be modified */ status = ERROR; } return status; } /** * @brief Function to enable PLL and switch system clock to PLL * @param SYSCLK_Frequency SYSCLK frequency * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains * the configuration information for the BUS prescalers. * @retval An ErrorStatus enumeration value: * - SUCCESS: No problem to switch system to PLL * - ERROR: Problem to switch system to PLL */ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; uint32_t sysclk_frequency_current = 0U; assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); /* Calculate current SYSCLK frequency */ sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]); /* Increasing the number of wait states because of higher CPU frequency */ if (sysclk_frequency_current < SYSCLK_Frequency) { /* Set FLASH latency to highest latency */ status = UTILS_SetFlashLatency(SYSCLK_Frequency); } /* Update system clock configuration */ if (status == SUCCESS) { /* Enable PLL */ LL_RCC_PLL_Enable(); while (LL_RCC_PLL_IsReady() != 1U) { /* Wait for PLL ready */ } /* Sysclk activation on the main PLL */ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) { /* Wait for system clock switch to PLL */ } /* Set APB1 & APB2 prescaler*/ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); } /* Decreasing the number of wait states because of lower CPU frequency */ if (sysclk_frequency_current > SYSCLK_Frequency) { /* Set FLASH latency to lowest latency */ status = UTILS_SetFlashLatency(SYSCLK_Frequency); } /* Update SystemCoreClock variable */ if (status == SUCCESS) { LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); } return status; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Production Modules/2OPFM/firmware/_archive/2OPFM_2020/STM32F334K8TX_FLASH.ld ================================================ /* ****************************************************************************** ** ** File : LinkerScript.ld ** ** Author : Auto-generated by STM32CubeIDE ** ** Abstract : Linker script for STM32F334K8Tx Device from stm32f3 series ** 64Kbytes FLASH ** 4Kbytes CCMRAM ** 12Kbytes RAM ** ** Set heap size, stack size and stack location according ** to application requirements. ** ** Set memory bank area and size if external memory is used. ** ** Target : STMicroelectronics STM32 ** ** Distribution: The file is distributed as is without any warranty ** of any kind. ** ***************************************************************************** ** @attention ** **

© COPYRIGHT(c) 2020 STMicroelectronics

** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** 1. Redistributions of source code must retain the above copyright notice, ** this list of conditions and the following disclaimer. ** 2. Redistributions in binary form must reproduce the above copyright notice, ** this list of conditions and the following disclaimer in the documentation ** and/or other materials provided with the distribution. ** 3. Neither the name of STMicroelectronics nor the names of its contributors ** may be used to endorse or promote products derived from this software ** without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ***************************************************************************** */ /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ _Min_Heap_Size = 0x200 ; /* required amount of heap */ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 4K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 12K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K } /* Sections */ SECTIONS { /* The startup code into "FLASH" Rom type memory */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >FLASH /* The program code and other data into "FLASH" Rom type memory */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ *(.glue_7) /* glue arm to thumb code */ *(.glue_7t) /* glue thumb to arm code */ *(.eh_frame) KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ } >FLASH /* Constant data into "FLASH" Rom type memory */ .rodata : { . = ALIGN(4); *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); } >FLASH .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH .ARM : { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; . = ALIGN(4); } >FLASH .preinit_array : { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); } >FLASH .init_array : { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); } >FLASH .fini_array : { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); . = ALIGN(4); } >FLASH /* Used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections into "RAM" Ram type memory */ .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH /* Uninitialized data section into "RAM" Ram type memory */ . = ALIGN(4); .bss : { /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; } >RAM /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ ._user_heap_stack : { . = ALIGN(8); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM /* Remove information from the compiler libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } .ARM.attributes 0 : { *(.ARM.attributes) } } ================================================ FILE: Production Modules/2OPFM/jlcpcb/2OPFM_REV5_JLCBOM.csv ================================================ Comment,Designator,Footprint,JLCPCB Part # CJ431,D8,SOT23,C3113 100nf50V0603,"C5,C6,C7,C8,C11,C12,C13,C16,C18,C19,C20,C22,C28",0603CAP,C14663 MCP6002,"U2,U10",SOIC-8/150mil,C444396 STM32G431KBU3,U4,QFN50P500X500X60-33N,C1341901 100k1%0603,"R1,R3,R7,R13,R14,R16",0603RES,C25803 EUROPWR-10p,J1,10P_euro_power,C492422 100p0603,C14,0603CAP,C14858 10uF1206,"C3,C15,C21",CAP_1206,C13585 AMS1117-3.3,U15,SOT223-4,C6186 2PHDR,J8,HDR-1x2T/2.54/5x2,C234182 100k0.1%0603,R17,0603RES,C335088 1k1%0603,"R5,R6,R18,R19,R23,R27",0603RES,C21190 60.4k1%0603,"R20,R26",0603RES,C844800 33k1%0603,"R4,R24",0603RES,C269485 TL072,U3,SOIC-8/150mil,C5157710 MMBT3904,Q1,SOT23,C7420353 1n0603,"C10,C17,C23",0603CAP,C1588 10k1%0603,"R8,R21,R25,R43,R44",0603RES,C3152123 1N4148WS,"D1,D2,D10,D11",SOD-323,C2128 33k0.1%0603,R15,0603RES,C705768 WQP-WQP518MA,"J2, J4, J5, J6, J7",WQP-WQP518MA, RV9012NO-PA25B7.0 Tall Trimmer 10k,"R9, R10",VerticalPot, PTA2043-2015DPB103,"R11, R12",20mmSlider, VAOL-3LAE2,D5,3mm LED , ================================================ FILE: Production Modules/2OPFM/jlcpcb/2OPFM_REV5_JLCXY.csv ================================================ Designator,Mid X,Mid Y,Layer,Rotation C3,24.765,18.097,Bottom,180.0 C5,14.763,101.441,Bottom,0.0 C6,18.891,93.345,Bottom,0.0 C7,19.368,63.183,Bottom,180.0 C8,19.685,60.007,Bottom,90.0 C10,9.684,72.39,Bottom,270.0 C11,21.272,46.775,Bottom,0.0 C12,10.002,84.875,Bottom,180.0 C13,10.795,55.721,Bottom,90.0 C14,26.352,97.472,Bottom,90.0 C15,24.765,27.622,Bottom,0.0 C16,14.764,76.041,Bottom,180.0 C17,19.845,75.18,Bottom,270.0 C18,6.089,46.673,Bottom,0.0 C19,22.123,8.89,Bottom,0.0 C20,6.668,11.43,Bottom,180.0 C21,6.35,25.082,Bottom,0.0 C22,7.2,8.89,Bottom,0.0 C23,6.191,81.439,Bottom,270.0 C28,6.033,28.734,Bottom,180.0 D1,6.974,92.551,Bottom,0.0 D2,26.194,89.376,Bottom,0.0 D5,6.985,96.52,Top,180.0 D8,16.351,85.09,Bottom,180.0 D10,20.003,27.94,Bottom,180.0 D11,20.002,17.78,Bottom,0.0 J1,14.605,22.543,Bottom,180.0 J2,22.225,80.721,Top,180.0 J3,14.605,42.227,Bottom,270.0 J4,22.225,95.961,Top,180.0 J5,22.225,65.481,Top,180.0 J6,6.985,65.481,Top,180.0 J7,6.985,80.721,Top,180.0 J8,2.699,59.372,Bottom,90.0 Q1,26.194,86.519,Bottom,270.0 R1,26.193,92.075,Bottom,0.0 R3,6.032,88.582,Bottom,0.0 R4,3.493,81.439,Bottom,270.0 R5,6.191,57.626,Bottom,0.0 R6,8.255,100.012,Bottom,90.0 R7,18.891,82.13,Bottom,90.0 R8,11.748,87.948,Bottom,270.0 R9,22.225,49.607,Top,0.0 R10,6.985,49.607,Top,0.0 R11,22.225,22.86,Top,90.0 R12,6.985,22.86,Top,90.0 R13,25.4,72.708,Bottom,270.0 R14,24.606,82.073,Bottom,90.0 R15,4.445,72.549,Bottom,270.0 R16,21.749,82.073,Bottom,90.0 R17,4.445,68.422,Bottom,270.0 R18,18.732,89.852,Bottom,90.0 R19,16.668,89.059,Bottom,0.0 R20,23.495,97.472,Bottom,90.0 R21,13.177,54.293,Bottom,180.0 R23,19.05,101.283,Bottom,180.0 R24,25.4,76.2,Bottom,270.0 R25,21.465,66.62,Bottom,270.0 R26,23.815,67.49,Bottom,0.0 R27,4.265,101.38,Bottom,180.0 R43,18.891,85.408,Bottom,270.0 R44,17.938,87.63,Bottom,0.0 U2,11.746,81.28,Bottom,180.0 U3,16.669,97.314,Bottom,0.0 U4,15.716,59.531,Bottom,0.0 U10,14.605,72.39,Bottom,180.0 U15,5.715,18.415,Bottom,90.0 ================================================ FILE: Production Modules/2OPFM/jlcpcb/_archive/2OPFM_2022_NOTES.txt ================================================ 2OPFM 2022 NOTES Main thing, C13 is now a 1k resistor. it was in series with the current limiting resistor for the output led, leftover from when that signal was AC coupled. it's way better as a 1k. ================================================ FILE: Production Modules/2OPFM/jlcpcb/_archive/2OPFM_REV3_JLCBOM.csv ================================================ Comment,Designator,Footprint,LCSC Part #（optional）, 100nf 50V 0603,"C1, C2, C4, C5, C6, C11, C12, C16, C18, C19, C20, C22, C28",0603 CAP,, 10uF 1206,"C3, C15, C21",CAP_1206,, *RST*,C9,0603 CAP,, 1n 0603,"C10, C17, C23",0603 CAP,, 100p 0603 ,C14,0603 CAP,, 1N4148WS,"D1, D2, D10, D11",SOD-323,, VAOL-3MAE2,D5,LEDT1,, LM4040-5V,D12,SOT23,, EUROPWR-10p,J1,10P_euro_power,, WQP-PJ398SM,J2,Thonkiconn Jack,, C37208,J3,HDR-1x6T/2.54/15x2,, WQP-PJ398SM,J4,Thonkiconn Jack,, WQP-PJ398SM,J5,Thonkiconn Jack,, WQP-PJ398SM,J6,Thonkiconn Jack,, WQP-PJ398SM,J7,Thonkiconn Jack,, MMBT3904,Q1,SOT23,, 100kΩ 0603 ,"R1, R3, R7, R13, R14, R16, R17",0603 RES,, 10kΩ 0603,"R2, R8, R19, R25",0603 RES,, 33kΩ 0603,"R4, R15, R24",0603 RES,, 1kΩ 0603,"R6, R23, C13",0603 RES,, RV09AF-40-20K-B10K,R9,EVUF,, RV09AF-40-20K-B10K,R10,EVUF,, PTA2053-2015DPB103,R11,PTA2043,, PTA2053-2015DPB103,R12,PTA2043,, 60.04kΩ 0603,"R20, R26",0603 RES,, MCP6002-I/SN,"U2, U10",SOIC-8/150mil,, TL072D,U3,SOIC-8/150mil,, STM32F334K8,U5,QFP-32/9x9x0.8,, 1117 3.3V,U15,SOT223-4,, ================================================ FILE: Production Modules/2OPFM/jlcpcb/_archive/2OPFM_REV3_JLCXY.csv ================================================ Designator,Mid X,Mid Y,Layer,Rotation C1,15.716,66.357,Bottom,90.0 C2,20.955,53.975,Bottom,180.0 C3,25.4,18.098,Bottom,180.0 C4,10.477,65.087,Bottom,0.0 C5,15.398,101.441,Bottom,0.0 C6,19.526,93.345,Bottom,0.0 C9,14.129,66.357,Bottom,90.0 C10,10.319,72.39,Bottom,270.0 C11,21.907,46.775,Bottom,0.0 C12,10.637,84.875,Bottom,180.0 C13,4.901,101.38,Bottom,180.0 C14,26.988,97.472,Bottom,90.0 C15,25.4,27.623,Bottom,0.0 C16,15.399,76.041,Bottom,180.0 C17,20.48,75.18,Bottom,270.0 C18,6.724,46.672,Bottom,0.0 C19,22.758,8.89,Bottom,0.0 C20,7.303,11.43,Bottom,180.0 C21,6.985,25.082,Bottom,0.0 C22,7.835,8.89,Bottom,0.0 C23,6.826,81.439,Bottom,270.0 C28,6.668,28.734,Bottom,180.0 D1,7.609,92.551,Bottom,0.0 D2,26.829,89.376,Bottom,0.0 D5,7.62,96.52,Top,180.0 D10,20.638,27.94,Bottom,180.0 D11,20.637,17.78,Bottom,0.0 D12,15.875,87.789,Bottom,180.0 J1,15.24,22.543,Bottom,180.0 J2,22.86,80.721,Top,180.0 J3,15.24,42.227,Bottom,270.0 J4,22.86,95.961,Top,180.0 J5,22.86,65.481,Top,180.0 J6,7.62,65.481,Top,180.0 J7,7.62,80.721,Top,180.0 Q1,26.829,86.519,Bottom,270.0 R1,26.828,92.075,Bottom,0.0 R2,3.651,59.214,Bottom,270.0 R3,6.667,88.582,Bottom,0.0 R4,4.128,81.439,Bottom,270.0 R6,8.89,100.012,Bottom,90.0 R7,19.526,82.13,Bottom,90.0 R8,12.383,87.948,Bottom,270.0 R9,22.86,49.607,Top,0.0 R10,7.62,49.607,Top,0.0 R11,22.86,22.86,Top,90.0 R12,7.62,22.86,Top,90.0 R13,26.035,72.708,Bottom,270.0 R14,25.241,82.073,Bottom,90.0 R15,5.08,72.549,Bottom,270.0 R16,22.384,82.073,Bottom,90.0 R17,5.08,68.422,Bottom,270.0 R19,20.479,87.788,Bottom,90.0 R20,24.13,97.472,Bottom,90.0 R23,19.685,101.282,Bottom,180.0 R24,26.035,76.2,Bottom,270.0 R25,22.1,66.62,Bottom,270.0 R26,24.45,67.49,Bottom,0.0 U2,12.381,81.28,Bottom,180.0 U3,17.304,97.314,Bottom,0.0 U5,15.24,58.738,Bottom,270.0 U10,15.24,72.39,Bottom,180.0 U15,6.35,18.415,Bottom,90.0 ================================================ FILE: Production Modules/2OPFM/jlcpcb/_archive/2OPFM_REV4_JLCBOM.csv ================================================ Comment,Designator,Footprint,LCSC Part #（optional）, 100nf 50V,"C1, C2, C4, C5, C6, C11, C12, C16, C18, C19, C20, C22, C28",0603 CAP,, 10uF,"C3, C15, C21",CAP_1206,, *RST*,C9,0603 CAP,, 1n,"C10, C17, C23",0603 CAP,, 100p,C14,0603 CAP,, 1N4148WS,"D1, D2, D10, D11",SOD-323,, VAOL-3MAE2,D5,LEDT1,, LM4040-5V,D12,SOT23,, EUROPWR-10p,J1,10P_euro_power,, WQP-WQP518MA,J2,Thonkiconn Jack,, C37208,J3,HDR-1x6T/2.54/15x2,, WQP-WQP518MA,J4,Thonkiconn Jack,, WQP-WQP518MA,J5,Thonkiconn Jack,, WQP-WQP518MA,J6,Thonkiconn Jack,, WQP-WQP518MA,J7,Thonkiconn Jack,, MMBT3904,Q1,SOT23,, 100k 1% 0603,"R1, R3, R7, R13, R14, R16, R17",0603 RES,, 10k 1% 0603,"R2, R8, R19, R25",0603 RES,, 33k 1% 0603,"R4, R15, R24",0603 RES,, 1k 1% 0603,"R6, R23, R27",0603 RES,, "R0904N-B10k, L-25 KQ",R9,EVUF,, "R0904N-B10k, L-25 KQ",R10,EVUF,, PTA2053-2015DPB103,R11,PTA2043,, PTA2053-2015DPB103,R12,PTA2043,, 60.4k 1% 0603,"R20, R26",0603 RES,, MCP6002-I/SN,"U2, U10",SOIC-8/150mil,, TL072D,U3,SOIC-8/150mil,, STM32F334K8,U5,QFP-32/9x9x0.8,, 1117 3.3V,U15,SOT223-4,, ================================================ FILE: Production Modules/2OPFM/jlcpcb/_archive/2OPFM_REV4_JLCXY.csv ================================================ Designator,Mid X,Mid Y,Layer,Rotation C1,15.716,66.357,Bottom,90.0 C2,20.955,53.975,Bottom,180.0 C3,25.4,18.098,Bottom,180.0 C4,10.477,65.087,Bottom,0.0 C5,15.398,101.441,Bottom,0.0 C6,19.526,93.345,Bottom,0.0 C9,14.129,66.357,Bottom,90.0 C10,10.319,72.39,Bottom,270.0 C11,21.907,46.775,Bottom,0.0 C12,10.637,84.875,Bottom,180.0 C14,26.988,97.472,Bottom,90.0 C15,25.4,27.623,Bottom,0.0 C16,15.399,76.041,Bottom,180.0 C17,20.48,75.18,Bottom,270.0 C18,6.724,46.672,Bottom,0.0 C19,22.758,8.89,Bottom,0.0 C20,7.303,11.43,Bottom,180.0 C21,6.985,25.082,Bottom,0.0 C22,7.835,8.89,Bottom,0.0 C23,6.826,81.439,Bottom,270.0 C28,6.668,28.734,Bottom,180.0 D1,7.609,92.551,Bottom,0.0 D2,26.829,89.376,Bottom,0.0 D5,7.62,96.52,Top,180.0 D10,20.638,27.94,Bottom,180.0 D11,20.637,17.78,Bottom,0.0 D12,15.875,87.789,Bottom,180.0 J1,15.24,22.543,Bottom,180.0 J2,22.86,80.721,Top,180.0 J3,15.24,42.227,Bottom,270.0 J4,22.86,95.961,Top,180.0 J5,22.86,65.481,Top,180.0 J6,7.62,65.481,Top,180.0 J7,7.62,80.721,Top,180.0 Q1,26.829,86.519,Bottom,270.0 R1,26.828,92.075,Bottom,0.0 R2,3.651,59.214,Bottom,270.0 R3,6.667,88.582,Bottom,0.0 R4,4.128,81.439,Bottom,270.0 R6,8.89,100.012,Bottom,90.0 R7,19.526,82.13,Bottom,90.0 R8,12.383,87.948,Bottom,270.0 R9,22.86,49.607,Top,0.0 R10,7.62,49.607,Top,0.0 R11,22.86,22.86,Top,90.0 R12,7.62,22.86,Top,90.0 R13,26.035,72.708,Bottom,270.0 R14,25.241,82.073,Bottom,90.0 R15,5.08,72.549,Bottom,270.0 R16,22.384,82.073,Bottom,90.0 R17,5.08,68.422,Bottom,270.0 R19,20.479,87.788,Bottom,90.0 R20,24.13,97.472,Bottom,90.0 R23,19.685,101.282,Bottom,180.0 R24,26.035,76.2,Bottom,270.0 R25,22.1,66.62,Bottom,270.0 R26,24.45,67.49,Bottom,0.0 R27,4.901,101.38,Bottom,180.0 U2,12.381,81.28,Bottom,180.0 U3,17.304,97.314,Bottom,0.0 U5,15.24,58.738,Bottom,270.0 U10,15.24,72.39,Bottom,180.0 U15,6.35,18.415,Bottom,90.0 ================================================ FILE: Production Modules/2OPFM/jlcpcb/_archive/2OPFM_REV5_JLCBOM.csv ================================================ #,Comment,Designator,Footprint 1,10uF 1206,"C3, C15, C21",CAP_1206 2,100nf 50V 0603,"C5, C6, C7, C8, C11, C12, C13, C16, C18, C19, C20, C22, C28",0603 CAP 4,1n 0603,"C10, C17, C23",0603 CAP 5,100p 0603,C14,0603 CAP 7,1N4148WS,"D1, D2, D10, D11",SOD-323 8,VAOL-3MAE2,D5,LEDT1 9,CJ431,D8,SOT23 10,EUROPWR-10p,J1,10P_euro_power 11,WQP-PJ398SM,"J2, J4, J5, J6, J7",Thonkiconn Jack 12,C37208,J3,HDR-1x6T/2.54/15x2 17,2PHDR,J8,HDR-1x2T/2.54/5x2 18,MMBT3904,Q1,SOT23 19,100k 1% 0603,"R1, R3, R7, R13, R14, R16",0603 RES 20,33k 1% 0603,"R4, R24",0603 RES 21,1k 1% 0603,"R5, R6, R18, R19, R23, R27",0603 RES 22,10k 1% 0603,"R8, R21, R25, R43, R44",0603 RES 23,RV9012NO-PA25B7.0,R9,EVUF 24,RV9012NO-PA25B7.0,R10,EVUF 25,PTA2043-2015DPB103,R11,PTA2043 26,PTA2043-2015DPB103,R12,PTA2043 27,33k 0.1% 0603,R15,0603 RES 28,100k 0.1% 0603,R17,0603 RES 29,60.4k 1% 0603,"R20, R26",0603 RES 31,MCP6002,"U2, U10",SOIC-8/150mil 32,TL072,U3,SOIC-8/150mil 33,STM32G431KBU3,U4,QFN50P500X500X60-33N 35,AMS1117-3.3,U15,SOT223-4 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/.cproject ================================================ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/.mxproject ================================================ [PreviousLibFiles] LibFiles=Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h;Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h; [PreviousUsedCubeIDEFiles] SourceFiles=Core/Src/main.c;Core/Src/gpio.c;Core/Src/adc.c;Core/Src/dac.c;Core/Src/dma.c;Core/Src/tim.c;Core/Src/stm32g4xx_it.c;Core/Src/stm32g4xx_hal_msp.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c;Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c;Core/Src/system_stm32g4xx.c;;; HeaderPath=Drivers/STM32G4xx_HAL_Driver/Inc;Drivers/STM32G4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32G4xx/Include;Drivers/CMSIS/Include;Core/Inc; CDefines=USE_HAL_DRIVER;STM32G431xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=8 HeaderFiles#0=../Core/Inc/gpio.h HeaderFiles#1=../Core/Inc/adc.h HeaderFiles#2=../Core/Inc/dac.h HeaderFiles#3=../Core/Inc/dma.h HeaderFiles#4=../Core/Inc/tim.h HeaderFiles#5=../Core/Inc/stm32g4xx_it.h HeaderFiles#6=../Core/Inc/stm32g4xx_hal_conf.h HeaderFiles#7=../Core/Inc/main.h HeaderFolderListSize=1 HeaderPath#0=../Core/Inc HeaderFiles=; SourceFileListSize=8 SourceFiles#0=../Core/Src/gpio.c SourceFiles#1=../Core/Src/adc.c SourceFiles#2=../Core/Src/dac.c SourceFiles#3=../Core/Src/dma.c SourceFiles#4=../Core/Src/tim.c SourceFiles#5=../Core/Src/stm32g4xx_it.c SourceFiles#6=../Core/Src/stm32g4xx_hal_msp.c SourceFiles#7=../Core/Src/main.c SourceFolderListSize=1 SourcePath#0=../Core/Src SourceFiles=; ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/.project ================================================ chorus_G431 org.eclipse.cdt.managedbuilder.core.genmakebuilder clean,full,incremental, org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder full,incremental, com.st.stm32cube.ide.mcu.MCUProjectNature com.st.stm32cube.ide.mcu.MCUCubeProjectNature org.eclipse.cdt.core.cnature com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature com.st.stm32cube.ide.mcu.MCURootProjectNature org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature org.eclipse.cdt.core.ccnature ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs ================================================ eclipse.preferences.version=1 sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/.settings/language.settings.xml ================================================ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/.settings/stm32cubeide.project.prefs ================================================ 66BE74F758C12D739921AEA421D593D3=4 8DF89ED150041C4CBC7CB9A9CAA90856=0FBBB2C2AEE50CCE13462D1ACE6578A9 DC22A860405A8BF2F2C095E5B6529F12=0FBBB2C2AEE50CCE13462D1ACE6578A9 eclipse.preferences.version=1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/adc.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file adc.h * @brief This file contains all the function prototypes for * the adc.c file ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __ADC_H__ #define __ADC_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc2; /* USER CODE BEGIN Private defines */ #define NUM_ADC1_CHANNELS 5 #define NUM_ADC2_CHANNELS 1 volatile uint16_t ADC1_raw_data; volatile uint16_t ADC2_raw_data; volatile uint16_t ADC1_channel_data[NUM_ADC1_CHANNELS]; /* USER CODE END Private defines */ void MX_ADC1_Init(void); void MX_ADC2_Init(void); /* USER CODE BEGIN Prototypes */ void ADC1_Start(); void ADC2_Start(); /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __ADC_H__ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/big_sine_wave.h ================================================ /* * big_sine_wave.h * * Created on: Mar 31, 2020 * Author: SUPER */ #ifndef BIG_SINE_WAVE_H_ #define BIG_SINE_WAVE_H_ #include "main.h" static const uint16_t big_sine_wave[1024] = { 32768, 32969, 33170, 33371, 33572, 33773, 33974, 34174, 34375, 34576, 34777, 34977, 35178, 35378, 35579, 35779, 35979, 36179, 36379, 36579, 36779, 36978, 37177, 37377, 37575, 37774, 37973, 38171, 38369, 38567, 38765, 38963, 39160, 39357, 39554, 39751, 39947, 40143, 40339, 40534, 40729, 40924, 41119, 41313, 41507, 41701, 41894, 42087, 42279, 42472, 42663, 42855, 43046, 43237, 43427, 43617, 43807, 43996, 44184, 44373, 44560, 44748, 44935, 45121, 45307, 45493, 45678, 45862, 46046, 46230, 46413, 46595, 46777, 46959, 47140, 47320, 47500, 47679, 47858, 48036, 48214, 48391, 48567, 48743, 48919, 49093, 49267, 49441, 49613, 49785, 49957, 50128, 50298, 50468, 50636, 50805, 50972, 51139, 51305, 51471, 51635, 51799, 51963, 52125, 52287, 52448, 52609, 52768, 52927, 53085, 53243, 53399, 53555, 53710, 53864, 54018, 54170, 54322, 54473, 54623, 54773, 54921, 55069, 55216, 55362, 55507, 55652, 55795, 55938, 56079, 56220, 56360, 56499, 56637, 56775, 56911, 57047, 57181, 57315, 57448, 57579, 57710, 57840, 57969, 58097, 58224, 58350, 58475, 58600, 58723, 58845, 58966, 59087, 59206, 59324, 59441, 59558, 59673, 59787, 59900, 60013, 60124, 60234, 60343, 60451, 60558, 60664, 60769, 60873, 60976, 61078, 61178, 61278, 61377, 61474, 61571, 61666, 61760, 61853, 61945, 62036, 62126, 62215, 62302, 62389, 62474, 62559, 62642, 62724, 62805, 62885, 62963, 63041, 63117, 63192, 63266, 63339, 63411, 63482, 63551, 63620, 63687, 63753, 63818, 63881, 63944, 64005, 64065, 64124, 64182, 64238, 64294, 64348, 64401, 64453, 64504, 64553, 64601, 64648, 64694, 64739, 64782, 64825, 64866, 64905, 64944, 64981, 65018, 65053, 65086, 65119, 65150, 65180, 65209, 65237, 65263, 65289, 65313, 65335, 65357, 65377, 65396, 65414, 65431, 65446, 65460, 65473, 65485, 65496, 65505, 65513, 65520, 65525, 65529, 65533, 65534, 65535, 65534, 65533, 65529, 65525, 65520, 65513, 65505, 65496, 65485, 65473, 65460, 65446, 65431, 65414, 65396, 65377, 65357, 65335, 65313, 65289, 65263, 65237, 65209, 65180, 65150, 65119, 65086, 65053, 65018, 64981, 64944, 64905, 64866, 64825, 64782, 64739, 64694, 64648, 64601, 64553, 64504, 64453, 64401, 64348, 64294, 64238, 64182, 64124, 64065, 64005, 63944, 63881, 63818, 63753, 63687, 63620, 63551, 63482, 63411, 63339, 63266, 63192, 63117, 63041, 62963, 62885, 62805, 62724, 62642, 62559, 62474, 62389, 62302, 62215, 62126, 62036, 61945, 61853, 61760, 61666, 61571, 61474, 61377, 61278, 61178, 61078, 60976, 60873, 60769, 60664, 60558, 60451, 60343, 60234, 60124, 60013, 59900, 59787, 59673, 59558, 59441, 59324, 59206, 59087, 58966, 58845, 58723, 58600, 58475, 58350, 58224, 58097, 57969, 57840, 57710, 57579, 57448, 57315, 57181, 57047, 56911, 56775, 56637, 56499, 56360, 56220, 56079, 55938, 55795, 55652, 55507, 55362, 55216, 55069, 54921, 54773, 54623, 54473, 54322, 54170, 54018, 53864, 53710, 53555, 53399, 53243, 53085, 52927, 52768, 52609, 52448, 52287, 52125, 51963, 51799, 51635, 51471, 51305, 51139, 50972, 50805, 50636, 50468, 50298, 50128, 49957, 49785, 49613, 49441, 49267, 49093, 48919, 48743, 48567, 48391, 48214, 48036, 47858, 47679, 47500, 47320, 47140, 46959, 46777, 46595, 46413, 46230, 46046, 45862, 45678, 45493, 45307, 45121, 44935, 44748, 44560, 44373, 44184, 43996, 43807, 43617, 43427, 43237, 43046, 42855, 42663, 42472, 42279, 42087, 41894, 41701, 41507, 41313, 41119, 40924, 40729, 40534, 40339, 40143, 39947, 39751, 39554, 39357, 39160, 38963, 38765, 38567, 38369, 38171, 37973, 37774, 37575, 37377, 37177, 36978, 36779, 36579, 36379, 36179, 35979, 35779, 35579, 35378, 35178, 34977, 34777, 34576, 34375, 34174, 33974, 33773, 33572, 33371, 33170, 32969, 32768, 32566, 32365, 32164, 31963, 31762, 31561, 31361, 31160, 30959, 30758, 30558, 30357, 30157, 29956, 29756, 29556, 29356, 29156, 28956, 28756, 28557, 28358, 28158, 27960, 27761, 27562, 27364, 27166, 26968, 26770, 26572, 26375, 26178, 25981, 25784, 25588, 25392, 25196, 25001, 24806, 24611, 24416, 24222, 24028, 23834, 23641, 23448, 23256, 23063, 22872, 22680, 22489, 22298, 22108, 21918, 21728, 21539, 21351, 21162, 20975, 20787, 20600, 20414, 20228, 20042, 19857, 19673, 19489, 19305, 19122, 18940, 18758, 18576, 18395, 18215, 18035, 17856, 17677, 17499, 17321, 17144, 16968, 16792, 16616, 16442, 16268, 16094, 15922, 15750, 15578, 15407, 15237, 15067, 14899, 14730, 14563, 14396, 14230, 14064, 13900, 13736, 13572, 13410, 13248, 13087, 12926, 12767, 12608, 12450, 12292, 12136, 11980, 11825, 11671, 11517, 11365, 11213, 11062, 10912, 10762, 10614, 10466, 10319, 10173, 10028, 9883, 9740, 9597, 9456, 9315, 9175, 9036, 8898, 8760, 8624, 8488, 8354, 8220, 8087, 7956, 7825, 7695, 7566, 7438, 7311, 7185, 7060, 6935, 6812, 6690, 6569, 6448, 6329, 6211, 6094, 5977, 5862, 5748, 5635, 5522, 5411, 5301, 5192, 5084, 4977, 4871, 4766, 4662, 4559, 4457, 4357, 4257, 4158, 4061, 3964, 3869, 3775, 3682, 3590, 3499, 3409, 3320, 3233, 3146, 3061, 2976, 2893, 2811, 2730, 2650, 2572, 2494, 2418, 2343, 2269, 2196, 2124, 2053, 1984, 1915, 1848, 1782, 1717, 1654, 1591, 1530, 1470, 1411, 1353, 1297, 1241, 1187, 1134, 1082, 1031, 982, 934, 887, 841, 796, 753, 710, 669, 630, 591, 554, 517, 482, 449, 416, 385, 355, 326, 298, 272, 246, 222, 200, 178, 158, 139, 121, 104, 89, 75, 62, 50, 39, 30, 22, 15, 10, 6, 2, 1, 0, 1, 2, 6, 10, 15, 22, 30, 39, 50, 62, 75, 89, 104, 121, 139, 158, 178, 200, 222, 246, 272, 298, 326, 355, 385, 416, 449, 482, 517, 554, 591, 630, 669, 710, 753, 796, 841, 887, 934, 982, 1031, 1082, 1134, 1187, 1241, 1297, 1353, 1411, 1470, 1530, 1591, 1654, 1717, 1782, 1848, 1915, 1984, 2053, 2124, 2196, 2269, 2343, 2418, 2494, 2572, 2650, 2730, 2811, 2893, 2976, 3061, 3146, 3233, 3320, 3409, 3499, 3590, 3682, 3775, 3869, 3964, 4061, 4158, 4257, 4357, 4457, 4559, 4662, 4766, 4871, 4977, 5084, 5192, 5301, 5411, 5522, 5635, 5748, 5862, 5977, 6094, 6211, 6329, 6448, 6569, 6690, 6812, 6935, 7060, 7185, 7311, 7438, 7566, 7695, 7825, 7956, 8087, 8220, 8354, 8488, 8624, 8760, 8898, 9036, 9175, 9315, 9456, 9597, 9740, 9883, 10028, 10173, 10319, 10466, 10614, 10762, 10912, 11062, 11213, 11365, 11517, 11671, 11825, 11980, 12136, 12292, 12450, 12608, 12767, 12926, 13087, 13248, 13410, 13572, 13736, 13900, 14064, 14230, 14396, 14563, 14730, 14899, 15067, 15237, 15407, 15578, 15750, 15922, 16094, 16268, 16442, 16616, 16792, 16968, 17144, 17321, 17499, 17677, 17856, 18035, 18215, 18395, 18576, 18758, 18940, 19122, 19305, 19489, 19673, 19857, 20042, 20228, 20414, 20600, 20787, 20975, 21162, 21351, 21539, 21728, 21918, 22108, 22298, 22489, 22680, 22872, 23063, 23256, 23448, 23641, 23834, 24028, 24222, 24416, 24611, 24806, 25001, 25196, 25392, 25588, 25784, 25981, 26178, 26375, 26572, 26770, 26968, 27166, 27364, 27562, 27761, 27960, 28158, 28358, 28557, 28756, 28956, 29156, 29356, 29556, 29756, 29956, 30157, 30357, 30558, 30758, 30959, 31160, 31361, 31561, 31762, 31963, 32164, 32365, 32566 }; static const uint16_t sine_10b[1024] = {512,515,518,521,524,527,530,533,537,540,543,546,549,552,555,559,562,565,568,571,574,577,580,584,587,590,593,596,599,602,605,608,611,614,618,621,624,627,630,633,636,639,642,645,648,651,654,657,660,663,666,669,672,675,678,681,684,687,690,693,696,699,702,705,707,710,713,716,719,722,725,728,730,733,736,739,742,744,747,750,753,756,758,761,764,767,769,772,775,777,780,783,785,788,791,793,796,799,801,804,806,809,811,814,816,819,821,824,826,829,831,834,836,839,841,843,846,848,851,853,855,858,860,862,864,867,869,871,873,876,878,880,882,884,887,889,891,893,895,897,899,901,903,905,907,909,911,913,915,917,919,921,923,924,926,928,930,932,934,935,937,939,941,942,944,946,947,949,950,952,954,955,957,958,960,961,963,964,966,967,969,970,971,973,974,975,977,978,979,981,982,983,984,985,987,988,989,990,991,992,993,994,995,996,997,998,999,1000,1001,1002,1003,1004,1005,1005,1006,1007,1008,1009,1009,1010,1011,1011,1012,1013,1013,1014,1014,1015,1016,1016,1017,1017,1018,1018,1018,1019,1019,1020,1020,1020,1021,1021,1021,1021,1022,1022,1022,1022,1022,1023,1023,1023,1023,1023,1023,1023,1023,1023,1023,1023,1023,1023,1023,1022,1022,1022,1022,1022,1022,1021,1021,1021,1020,1020,1020,1019,1019,1019,1018,1018,1017,1017,1016,1016,1015,1015,1014,1014,1013,1012,1012,1011,1010,1010,1009,1008,1007,1007,1006,1005,1004,1003,1003,1002,1001,1000,999,998,997,996,995,994,993,992,991,990,988,987,986,985,984,982,981,980,979,977,976,975,973,972,971,969,968,966,965,964,962,961,959,958,956,954,953,951,950,948,946,945,943,941,940,938,936,934,933,931,929,927,925,924,922,920,918,916,914,912,910,908,906,904,902,900,898,896,894,892,890,888,885,883,881,879,877,875,872,870,868,866,863,861,859,856,854,852,849,847,845,842,840,837,835,833,830,828,825,823,820,818,815,813,810,808,805,802,800,797,795,792,789,787,784,781,779,776,773,771,768,765,762,760,757,754,751,749,746,743,740,737,735,732,729,726,723,720,718,715,712,709,706,703,700,697,694,691,688,685,683,680,677,674,671,668,665,662,659,656,653,650,647,644,640,637,634,631,628,625,622,619,616,613,610,607,604,601,597,594,591,588,585,582,579,576,573,569,566,563,560,557,554,551,548,544,541,538,535,532,529,526,522,519,516,513,510,507,504,501,497,494,491,488,485,482,479,475,472,469,466,463,460,457,454,450,447,444,441,438,435,432,429,426,422,419,416,413,410,407,404,401,398,395,392,389,386,383,379,376,373,370,367,364,361,358,355,352,349,346,343,340,338,335,332,329,326,323,320,317,314,311,308,305,303,300,297,294,291,288,286,283,280,277,274,272,269,266,263,261,258,255,252,250,247,244,242,239,236,234,231,228,226,223,221,218,215,213,210,208,205,203,200,198,195,193,190,188,186,183,181,178,176,174,171,169,167,164,162,160,157,155,153,151,148,146,144,142,140,138,135,133,131,129,127,125,123,121,119,117,115,113,111,109,107,105,103,101,99,98,96,94,92,90,89,87,85,83,82,80,78,77,75,73,72,70,69,67,65,64,62,61,59,58,57,55,54,52,51,50,48,47,46,44,43,42,41,39,38,37,36,35,33,32,31,30,29,28,27,26,25,24,23,22,21,20,20,19,18,17,16,16,15,14,13,13,12,11,11,10,9,9,8,8,7,7,6,6,5,5,4,4,4,3,3,3,2,2,2,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,2,2,2,2,3,3,3,4,4,5,5,5,6,6,7,7,8,9,9,10,10,11,12,12,13,14,14,15,16,17,18,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,38,39,40,41,42,44,45,46,48,49,50,52,53,54,56,57,59,60,62,63,65,66,68,69,71,73,74,76,77,79,81,82,84,86,88,89,91,93,95,97,99,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,139,141,143,145,147,150,152,154,156,159,161,163,165,168,170,172,175,177,180,182,184,187,189,192,194,197,199,202,204,207,209,212,214,217,219,222,224,227,230,232,235,238,240,243,246,248,251,254,256,259,262,265,267,270,273,276,279,281,284,287,290,293,295,298,301,304,307,310,313,316,318,321,324,327,330,333,336,339,342,345,348,351,354,357,360,363,366,369,372,375,378,381,384,387,390,393,396,399,402,405,409,412,415,418,421,424,427,430,433,436,439,443,446,449,452,455,458,461,464,468,471,474,477,480,483,486,490,493,496,499,502,505,508,512}; #endif /* BIG_SINE_WAVE_H_ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/c_filters.h ================================================ /* * c_filters.h * * Created on: Jan 6, 2023 * Author: chrismcdowell */ #ifndef INC_C_FILTERS_H_ #define INC_C_FILTERS_H_ #ifdef __cplusplus extern "C" { #endif #include "main.h" // note: SAMPLE_RATE must be defined in main.h typedef struct { float low; float high; float band; float delay1; float delay2; float freq; float a; float q; } svf_typedef; void svf_init(svf_typedef *svf, float _freq, float _q); void svf_tick(svf_typedef *svf, float _input); void svf_set_freq(svf_typedef *svf, float _freq); void svf_set_a_direct(svf_typedef *svf, float _a); void svf_set_q(svf_typedef *svf, float _q); float svf_get_low(svf_typedef *svf); float svf_get_high(svf_typedef *svf); float svf_get_band(svf_typedef *svf); #ifdef __cplusplus } #endif #endif /* INC_C_FILTERS_H_ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/chorus.h ================================================ /* * chorus.h * * Created on: Nov 22, 2020 * Author: SUPER */ #ifndef INC_CHORUS_H_ #define INC_CHORUS_H_ #ifdef __cplusplus extern "C" { #endif #include "dynamic_smooth.h" #include "c_filters.h" #define CHORUS_BUFFER_LENGTH 15000 float chorus_signal_input; float chorus_hp_input; float chorus_lp_input; float chorus_signal_output; float feedback; int16_t chorus_buffer[CHORUS_BUFFER_LENGTH]; uint32_t chorus_buffer_accumulator; uint16_t chorus_buffer_index_in; uint16_t chorus_buffer_index_out; float buffer_signal_input; float buffer_modulation; float max_sig; typedef struct { float output; float amplitude; float frequency; uint32_t phase_increment; uint32_t phase_index; } lfo_typedef; uint32_t lfo_tick(volatile lfo_typedef *lfo, float _frequency, float _amplitude); uint32_t lfo_tri_tick(volatile lfo_typedef *lfo, float _frequency, float _amplitude); volatile lfo_typedef chorus_lfo; typedef struct { uint16_t delay; uint16_t delay_cv; uint16_t lfo_amount; uint16_t lfo_rate; uint16_t feedback; } chorus_params_typedef; volatile float rate_pot; volatile float feedback_pot; volatile float lfo_amt_pot; volatile float delay_pot; volatile float delay_pot_filter; volatile float delay_cv; #define magic_cv_offset 1900 volatile float lfo_rate_pot; dynamic_smooth smooth_delay; float chorus_tick(float _input); void chorus_control_tick(chorus_params_typedef *chorus); void chorus_init(); svf_typedef input_lowpass; svf_typedef input_highpass; svf_typedef feedback_svf; #ifdef __cplusplus } #endif #endif /* INC_CHORUS_H_ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/dac.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dac.h * @brief This file contains all the function prototypes for * the dac.c file ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __DAC_H__ #define __DAC_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern DAC_HandleTypeDef hdac1; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_DAC1_Init(void); /* USER CODE BEGIN Prototypes */ void DAC_Start(); /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __DAC_H__ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/dma.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dma.h * @brief This file contains all the function prototypes for * the dma.c file ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __DMA_H__ #define __DMA_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* DMA memory to memory transfer handles -------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_DMA_Init(void); /* USER CODE BEGIN Prototypes */ /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __DMA_H__ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/dynamic_smooth.h ================================================ /* * dynamic_smooth.h * * Created on: Sep 19, 2020 * Author: SUPER */ #ifndef INC_DYNAMIC_SMOOTH_H_ #define INC_DYNAMIC_SMOOTH_H_ #ifdef __cplusplus extern "C" { #endif #include "main.h" #define DYN_SMOOTH_SAMPLE_RATE 53000.0f typedef struct { //init values float g0; float sense; //tick values float low1; float low2; float low1z; float low2z; float bandz; float out; }dynamic_smooth; float dynamic_smooth_tick(dynamic_smooth* _smooth, float in); void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity); #ifdef __cplusplus } #endif #endif /* INC_DYNAMIC_SMOOTH_H_ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/float_expo_table.h ================================================ /* * float_expot_table.h * * Created on: Nov 23, 2020 * Author: SUPER */ #ifndef INC_FLOAT_EXPO_TABLE_H_ #define INC_FLOAT_EXPO_TABLE_H_ const float float_expo_table[1024]; #endif /* INC_FLOAT_EXPO_TABLE_H_ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/gpio.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file gpio.h * @brief This file contains all the function prototypes for * the gpio.c file ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __GPIO_H__ #define __GPIO_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_GPIO_Init(void); /* USER CODE BEGIN Prototypes */ /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /*__ GPIO_H__ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/lerp.h ================================================ /* * lerp.h * * Created on: Jan 6, 2023 * Author: chrismcdowell */ #ifndef INC_LERP_H_ #define INC_LERP_H_ #ifdef __cplusplus extern "C" { #endif #include "main.h" float lerp_int16(int16_t _buf[], uint16_t _bufsize, float position); #ifdef __cplusplus } #endif #endif /* INC_LERP_H_ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/main.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.h * @brief : Header for main.c file. * This file contains the common defines of the application. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MAIN_H #define __MAIN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ /* USER CODE BEGIN ET */ /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ /* USER CODE BEGIN EC */ /* USER CODE END EC */ /* Exported macro ------------------------------------------------------------*/ /* USER CODE BEGIN EM */ /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ void Error_Handler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ #define MUX_C_Pin GPIO_PIN_6 #define MUX_C_GPIO_Port GPIOA #define MUX_B_Pin GPIO_PIN_7 #define MUX_B_GPIO_Port GPIOA #define MUX_A_Pin GPIO_PIN_0 #define MUX_A_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ #define AMT_POT_INDEX 0 #define DELAY_POT_INDEX 1 #define CV_INPUT_INDEX 2 #define RATE_POT_INDEX 3 #define FB_POT_INDEX 4 #define SAMPLE_RATE 53333 /* USER CODE END Private defines */ #ifdef __cplusplus } #endif #endif /* __MAIN_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/stm32g4xx_hal_conf.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_hal_conf.h * @author MCD Application Team * @brief HAL configuration file ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_CONF_H #define STM32G4xx_HAL_CONF_H #ifdef __cplusplus extern "C" { #endif /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* ########################## Module Selection ############################## */ /** * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED /*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_CORDIC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */ #define HAL_DAC_MODULE_ENABLED /*#define HAL_FDCAN_MODULE_ENABLED */ /*#define HAL_FMAC_MODULE_ENABLED */ /*#define HAL_HRTIM_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */ /*#define HAL_IWDG_MODULE_ENABLED */ /*#define HAL_I2C_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_RNG_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_SAI_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */ #define HAL_TIM_MODULE_ENABLED /*#define HAL_UART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED /* ########################## Register Callbacks selection ############################## */ /** * @brief This is the list of modules where register callback can be used */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U #define USE_HAL_COMP_REGISTER_CALLBACKS 0U #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U #define USE_HAL_DAC_REGISTER_CALLBACKS 0U #define USE_HAL_EXTI_REGISTER_CALLBACKS 0U #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U #define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U #define USE_HAL_I2C_REGISTER_CALLBACKS 0U #define USE_HAL_I2S_REGISTER_CALLBACKS 0U #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U #define USE_HAL_NAND_REGISTER_CALLBACKS 0U #define USE_HAL_NOR_REGISTER_CALLBACKS 0U #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U #define USE_HAL_PCD_REGISTER_CALLBACKS 0U #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U #define USE_HAL_RNG_REGISTER_CALLBACKS 0U #define USE_HAL_RTC_REGISTER_CALLBACKS 0U #define USE_HAL_SAI_REGISTER_CALLBACKS 0U #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U #define USE_HAL_SPI_REGISTER_CALLBACKS 0U #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U #define USE_HAL_TIM_REGISTER_CALLBACKS 0U #define USE_HAL_UART_REGISTER_CALLBACKS 0U #define USE_HAL_USART_REGISTER_CALLBACKS 0U #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* ########################## Oscillator Values adaptation ####################*/ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * This value is used by the RCC HAL module to compute the system frequency * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG. * This internal oscillator is mainly dedicated to provide a high precision clock to * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) #define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ /** * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) #define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ #endif /* LSE_STARTUP_TIMEOUT */ /** * @brief External clock source for I2S and SAI peripherals * This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source * frequency, this source is inserted directly through I2S_CKIN pad. */ #if !defined (EXTERNAL_CLOCK_VALUE) #define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ /* ########################### System Configuration ######################### */ /** * @brief This is the HAL system configuration section */ #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ #define USE_RTOS 0U #define PREFETCH_ENABLE 0U #define INSTRUCTION_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U /* ########################## Assert Selection ############################## */ /** * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ /* #define USE_FULL_ASSERT 1U */ /* ################## SPI peripheral configuration ########################## */ /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver * Activated: CRC code is present inside driver * Deactivated: CRC code cleaned from driver */ #define USE_SPI_CRC 0U /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file */ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32g4xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32g4xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32g4xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32g4xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ #ifdef HAL_ADC_MODULE_ENABLED #include "stm32g4xx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ #ifdef HAL_COMP_MODULE_ENABLED #include "stm32g4xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ #ifdef HAL_CORDIC_MODULE_ENABLED #include "stm32g4xx_hal_cordic.h" #endif /* HAL_CORDIC_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED #include "stm32g4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED #include "stm32g4xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED #include "stm32g4xx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ #ifdef HAL_EXTI_MODULE_ENABLED #include "stm32g4xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ #ifdef HAL_FDCAN_MODULE_ENABLED #include "stm32g4xx_hal_fdcan.h" #endif /* HAL_FDCAN_MODULE_ENABLED */ #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32g4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_FMAC_MODULE_ENABLED #include "stm32g4xx_hal_fmac.h" #endif /* HAL_FMAC_MODULE_ENABLED */ #ifdef HAL_HRTIM_MODULE_ENABLED #include "stm32g4xx_hal_hrtim.h" #endif /* HAL_HRTIM_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED #include "stm32g4xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED #include "stm32g4xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED #include "stm32g4xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_I2S_MODULE_ENABLED #include "stm32g4xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED #include "stm32g4xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ #ifdef HAL_NAND_MODULE_ENABLED #include "stm32g4xx_hal_nand.h" #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_NOR_MODULE_ENABLED #include "stm32g4xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ #ifdef HAL_OPAMP_MODULE_ENABLED #include "stm32g4xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED #include "stm32g4xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED #include "stm32g4xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_QSPI_MODULE_ENABLED #include "stm32g4xx_hal_qspi.h" #endif /* HAL_QSPI_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED #include "stm32g4xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED #include "stm32g4xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED #include "stm32g4xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED #include "stm32g4xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED #include "stm32g4xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED #include "stm32g4xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SRAM_MODULE_ENABLED #include "stm32g4xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED #include "stm32g4xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED #include "stm32g4xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED #include "stm32g4xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED #include "stm32g4xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t *file, uint32_t line); #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_CONF_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/stm32g4xx_it.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_it.h * @brief This file contains the headers of the interrupt handlers. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_IT_H #define __STM32G4xx_IT_H #ifdef __cplusplus extern "C" { #endif /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ /* USER CODE BEGIN ET */ /* USER CODE END ET */ /* Exported constants --------------------------------------------------------*/ /* USER CODE BEGIN EC */ /* USER CODE END EC */ /* Exported macro ------------------------------------------------------------*/ /* USER CODE BEGIN EM */ /* USER CODE END EM */ /* Exported functions prototypes ---------------------------------------------*/ void NMI_Handler(void); void HardFault_Handler(void); void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void DMA1_Channel1_IRQHandler(void); void DMA1_Channel2_IRQHandler(void); void TIM2_IRQHandler(void); void TIM3_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_IT_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/super_filters.h ================================================ /* * super_filters.h * * Created on: Jan 6, 2023 * Author: chrismcdowell */ #ifndef INC_SUPER_FILTERS_H_ #define INC_SUPER_FILTERS_H_ #include "main.h" class Svf { private: float low; float high; float band; float delay1; float delay2; float freq; float q; float sample_rate; public: Svf(float _sample_rate, float _freq, float _q); void tick(float _input); float getLow() { return low; } float getHigh() { return high; } float getBand() { return band; } }; #endif /* INC_SUPER_FILTERS_H_ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Inc/tim.h ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file tim.h * @brief This file contains all the function prototypes for * the tim.c file ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __TIM_H__ #define __TIM_H__ #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ extern TIM_HandleTypeDef htim1; extern TIM_HandleTypeDef htim2; extern TIM_HandleTypeDef htim3; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_TIM1_Init(void); void MX_TIM2_Init(void); void MX_TIM3_Init(void); void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /* USER CODE BEGIN Prototypes */ void TIM1_Start(); void TIM2_Start(); void TIM3_Start(); /* USER CODE END Prototypes */ #ifdef __cplusplus } #endif #endif /* __TIM_H__ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/adc.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file adc.c * @brief This file provides code for the configuration * of the ADC instances. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "adc.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; DMA_HandleTypeDef hdma_adc1; DMA_HandleTypeDef hdma_adc2; /* ADC1 init function */ void MX_ADC1_Init(void) { /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; ADC_ChannelConfTypeDef sConfig = {0}; /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; hadc1.Init.Resolution = ADC_RESOLUTION_12B; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.GainCompensation = 0; hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; hadc1.Init.LowPowerAutoWait = DISABLE; hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.NbrOfConversion = 1; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T3_TRGO; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; hadc1.Init.DMAContinuousRequests = ENABLE; hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; hadc1.Init.OversamplingMode = DISABLE; if (HAL_ADC_Init(&hadc1) != HAL_OK) { Error_Handler(); } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_24CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } /* ADC2 init function */ void MX_ADC2_Init(void) { /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; /* USER CODE BEGIN ADC2_Init 1 */ /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; hadc2.Init.Resolution = ADC_RESOLUTION_12B; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.GainCompensation = 0; hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; hadc2.Init.LowPowerAutoWait = DISABLE; hadc2.Init.ContinuousConvMode = DISABLE; hadc2.Init.NbrOfConversion = 1; hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; hadc2.Init.DMAContinuousRequests = ENABLE; hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; hadc2.Init.OversamplingMode = DISABLE; if (HAL_ADC_Init(&hadc2) != HAL_OK) { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0; void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; if(adcHandle->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } /* ADC1 clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; if(HAL_RCC_ADC12_CLK_ENABLED==1){ __HAL_RCC_ADC12_CLK_ENABLE(); } __HAL_RCC_GPIOA_CLK_ENABLE(); /**ADC1 GPIO Configuration PA2 ------> ADC1_IN3 */ GPIO_InitStruct.Pin = GPIO_PIN_2; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Channel2; hdma_adc1.Init.Request = DMA_REQUEST_ADC1; hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc1.Init.MemInc = DMA_MINC_DISABLE; hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_adc1.Init.Mode = DMA_CIRCULAR; hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) { Error_Handler(); } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } else if(adcHandle->Instance==ADC2) { /* USER CODE BEGIN ADC2_MspInit 0 */ /* USER CODE END ADC2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { Error_Handler(); } /* ADC2 clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; if(HAL_RCC_ADC12_CLK_ENABLED==1){ __HAL_RCC_ADC12_CLK_ENABLE(); } __HAL_RCC_GPIOA_CLK_ENABLE(); /**ADC2 GPIO Configuration PA0 ------> ADC2_IN1 */ GPIO_InitStruct.Pin = GPIO_PIN_0; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* ADC2 DMA Init */ /* ADC2 Init */ hdma_adc2.Instance = DMA1_Channel1; hdma_adc2.Init.Request = DMA_REQUEST_ADC2; hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; hdma_adc2.Init.MemInc = DMA_MINC_DISABLE; hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_adc2.Init.Mode = DMA_CIRCULAR; hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) { Error_Handler(); } __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc2); /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) { if(adcHandle->Instance==ADC1) { /* USER CODE BEGIN ADC1_MspDeInit 0 */ /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC12_CLK_ENABLED--; if(HAL_RCC_ADC12_CLK_ENABLED==0){ __HAL_RCC_ADC12_CLK_DISABLE(); } /**ADC1 GPIO Configuration PA2 ------> ADC1_IN3 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2); /* ADC1 DMA DeInit */ HAL_DMA_DeInit(adcHandle->DMA_Handle); /* USER CODE BEGIN ADC1_MspDeInit 1 */ /* USER CODE END ADC1_MspDeInit 1 */ } else if(adcHandle->Instance==ADC2) { /* USER CODE BEGIN ADC2_MspDeInit 0 */ /* USER CODE END ADC2_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC12_CLK_ENABLED--; if(HAL_RCC_ADC12_CLK_ENABLED==0){ __HAL_RCC_ADC12_CLK_DISABLE(); } /**ADC2 GPIO Configuration PA0 ------> ADC2_IN1 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0); /* ADC2 DMA DeInit */ HAL_DMA_DeInit(adcHandle->DMA_Handle); /* USER CODE BEGIN ADC2_MspDeInit 1 */ /* USER CODE END ADC2_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void ADC1_Start() { HAL_ADC_Start_DMA(&hadc1, &ADC1_raw_data, 1); } void ADC2_Start() { HAL_ADC_Start_DMA(&hadc2, &ADC2_raw_data, 1); } /* USER CODE END 1 */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/c_filters.c ================================================ /* * c_filters.c * * Created on: Jan 6, 2023 * Author: chrismcdowell */ #include "c_filters.h" void svf_init(svf_typedef *svf, float _freq, float _q) { svf->freq = _freq; svf->a = (6.28f * _freq) / SAMPLE_RATE; if (svf->a > 1.0f) { svf->a = 1.0f; } if (_q < 0.500f) { _q = 0.500f; } svf->q = 1.0f / _q; } void svf_tick(svf_typedef *svf, float _input) { svf->low = svf->delay2 + svf->a * svf->delay1; svf->high = _input - svf->low - (svf->q * svf->delay1); svf->band = (svf->a * svf->high) + svf->delay1; svf->delay1 = svf->band; svf->delay2 = svf->low; } void svf_set_freq(svf_typedef *svf, float _freq) { svf->freq = _freq; svf->a = (6.28f * _freq) / SAMPLE_RATE; if (svf->a > 1.0f) { svf->a = 1.0f; } } void svf_set_a_direct(svf_typedef *svf, float _a) { svf->a = _a; } void svf_set_q(svf_typedef *svf, float _q) { if (_q < 0.500f) { _q = 0.500f; } svf->q = 1.0f / _q; } float svf_get_low(svf_typedef *svf) { return svf->low; } float svf_get_high(svf_typedef *svf) { return svf->high; } float svf_get_band(svf_typedef *svf) { return svf->band; } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/chorus.c ================================================ /* * chorus.c * * Created on: Nov 22, 2020 * Author: SUPER */ #include "main.h" #include "chorus.h" #include "big_sine_wave.h" #include "float_expo_table.h" #include "lerp.h" #define SINE //#define FB_LP //#define BP_LP #define NO_FB_FILTER #define HP_INPUT_CUTOFF 150 #define LP_INPUT_CUTOFF 8000 #define FB_SVF_CUTOFF 5000 uint32_t lfo_tick(volatile lfo_typedef *lfo, float _frequency, float _amplitude) { lfo->phase_increment = ((42949.6710f) * (_frequency)); lfo->phase_index += lfo->phase_increment; lfo->output = ((((sine_10b[lfo->phase_index >> 22] - 512) * 0.001953125f) * 0.5f) + 0.5f) * _amplitude; //lfo->output = (big_sine_wave[lfo->phase_index >> 22]) >> 5; return lfo->phase_index; } float chorus_tick(float _input) { //input highpass svf_tick(&input_highpass, _input); chorus_hp_input = svf_get_high(&input_highpass); // input lowpass svf_tick(&input_lowpass, chorus_hp_input); chorus_lp_input = svf_get_low(&input_lowpass); // a lil' pad chorus_signal_input = chorus_lp_input * 0.7f; // increment buffer index and wrap chorus_buffer_index_in++; if (chorus_buffer_index_in > (CHORUS_BUFFER_LENGTH - 1)) { chorus_buffer_index_in -= CHORUS_BUFFER_LENGTH; } // add feedback buffer_signal_input = chorus_signal_input + (feedback); // store in the buffer chorus_buffer[chorus_buffer_index_in] = buffer_signal_input; lfo_tick(&chorus_lfo, lfo_rate_pot, lfo_amt_pot); // 1p low pass filter the lfo modulation buffer_modulation += ((chorus_lfo.output) - buffer_modulation) * 0.03f; // dynamic smooth the delay pot and cv input (summed in control tick) delay_pot_filter = dynamic_smooth_tick(&smooth_delay, delay_pot); // use the lerp to calculate our buffer output sample chorus_signal_output = lerp_int16(chorus_buffer, CHORUS_BUFFER_LENGTH, chorus_buffer_index_in - (buffer_modulation * (1.0f - delay_pot_filter)) - ((delay_pot_filter) * (CHORUS_BUFFER_LENGTH - 1))); // clip if (chorus_signal_output > 2047.0f) { chorus_signal_output = 2047.0f; } if (chorus_signal_output < -2047.0f) { chorus_signal_output = -2047.0f; } // calculate feedback with a filter or not #ifdef BP_LP svf_tick(&feedback_svf, chorus_signal_output); feedback = svf_get_band(&feedback_svf) * (feedback_pot * -1.0f); #endif #ifdef FB_LP svf_tick(&feedback_svf, chorus_signal_output); feedback = svf_get_low(&feedback_svf) * (feedback_pot * -1.0f); #endif #ifdef NO_FB_FILTER feedback = chorus_signal_output * (feedback_pot * -1.0f); #endif //check for max if (chorus_signal_output > max_sig) { max_sig = chorus_signal_output; } return chorus_signal_output; } void chorus_control_tick(chorus_params_typedef *chorus) { lfo_rate_pot += ((float_expo_table[chorus->lfo_rate] * 75.0f) - lfo_rate_pot) * 0.03f; lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; float delay_input = chorus->delay + ((chorus->delay_cv - magic_cv_offset) * 0.75f); if (delay_input > 1023.0f) { delay_input = 1023.0f; } if (delay_input < 0.0f) { delay_input = 0.0f; } delay_pot += (((delay_input) / 1024.0f) - delay_pot) * 0.5f; } void chorus_init() { dynamic_smooth_init(&smooth_delay, 0.05f, 0.5f); svf_init(&input_lowpass, LP_INPUT_CUTOFF, 0.707f); svf_init(&input_highpass, HP_INPUT_CUTOFF, 1.5f); svf_init(&feedback_svf, FB_SVF_CUTOFF, 1.0f); } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/dac.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dac.c * @brief This file provides code for the configuration * of the DAC instances. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "dac.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ DAC_HandleTypeDef hdac1; /* DAC1 init function */ void MX_DAC1_Init(void) { /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; if (HAL_DAC_Init(&hdac1) != HAL_OK) { Error_Handler(); } /** DAC channel OUT1 config */ sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; sConfig.DAC_DMADoubleDataMode = DISABLE; sConfig.DAC_SignedFormat = DISABLE; sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; sConfig.DAC_Trigger = DAC_TRIGGER_NONE; sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE; sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_EXTERNAL; sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) { Error_Handler(); } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(dacHandle->Instance==DAC1) { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* DAC1 clock enable */ __HAL_RCC_DAC1_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } void HAL_DAC_MspDeInit(DAC_HandleTypeDef* dacHandle) { if(dacHandle->Instance==DAC1) { /* USER CODE BEGIN DAC1_MspDeInit 0 */ /* USER CODE END DAC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DAC1_CLK_DISABLE(); /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5); /* USER CODE BEGIN DAC1_MspDeInit 1 */ /* USER CODE END DAC1_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void DAC_Start() { HAL_DAC_Start(&hdac1, DAC_CHANNEL_1); HAL_DAC_Start(&hdac1, DAC_CHANNEL_2); HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 2047); HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, 2047); } /* USER CODE END 1 */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/dma.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dma.c * @brief This file provides code for the configuration * of all the requested memory to memory DMA transfers. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "dma.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /*----------------------------------------------------------------------------*/ /* Configure DMA */ /*----------------------------------------------------------------------------*/ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /** * Enable DMA controller clock */ void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 2, 0); HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); } /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/dynamic_smooth.c ================================================ /* * dynamic_smooth.c * * Created on: Sep 19, 2020 * Author: SUPER */ #include "dynamic_smooth.h" #include "math.h" float cm_min(float a, float b) { return ((a) < (b) ? a : b); } float cm_abs(float a) { if (a < 0.0f) { return a*-1.0; } else { return a; } } void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity) { float basefreq, wc, gc; //init values basefreq = _base; wc = basefreq / DYN_SMOOTH_SAMPLE_RATE; gc = tan(3.14f * wc); _smooth->g0 = 2*gc/(1+gc); _smooth->sense = _sensitivity * 4.0f; //tick values _smooth->low1 = 0.0f; _smooth->low2 = 0.0f; _smooth->low1z = 0.0f; _smooth->low2z = 0.0f; _smooth->bandz = 0.0f; _smooth->out = 0.0f; } float dynamic_smooth_tick(dynamic_smooth* _smooth, float in) { float g; _smooth->low1z = _smooth->low1; _smooth->low2z = _smooth->low2; _smooth->bandz = _smooth->low2z - _smooth->low1z; g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); return _smooth->low2; } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/float_expo_table.c ================================================ /* * float_expo_table.c * * Created on: Nov 23, 2020 * Author: SUPER */ #include "main.h" #include "float_expo_table.h" const float float_expo_table[1024] = { 0.0000009536743164, 0.000003814697266, 0.000008583068848, 0.00001525878906, 0.00002384185791, 0.00003433227539, 0.0000467300415, 0.00006103515625, 0.00007724761963, 0.00009536743164, 0.0001153945923, 0.0001373291016, 0.0001611709595, 0.000186920166, 0.0002145767212, 0.000244140625, 0.0002756118774, 0.0003089904785, 0.0003442764282, 0.0003814697266, 0.0004205703735, 0.0004615783691, 0.0005044937134, 0.0005493164063, 0.0005960464478, 0.0006446838379, 0.0006952285767, 0.0007476806641, 0.0008020401001, 0.0008583068848, 0.0009164810181, 0.0009765625, 0.001038551331, 0.00110244751, 0.001168251038, 0.001235961914, 0.001305580139, 0.001377105713, 0.001450538635, 0.001525878906, 0.001603126526, 0.001682281494, 0.001763343811, 0.001846313477, 0.001931190491, 0.002017974854, 0.002106666565, 0.002197265625, 0.002289772034, 0.002384185791, 0.002480506897, 0.002578735352, 0.002678871155, 0.002780914307, 0.002884864807, 0.002990722656, 0.003098487854, 0.0032081604, 0.003319740295, 0.003433227539, 0.003548622131, 0.003665924072, 0.003785133362, 0.00390625, 0.004029273987, 0.004154205322, 0.004281044006, 0.004409790039, 0.00454044342, 0.00467300415, 0.004807472229, 0.004943847656, 0.005082130432, 0.005222320557, 0.00536441803, 0.005508422852, 0.005654335022, 0.005802154541, 0.005951881409, 0.006103515625, 0.00625705719, 0.006412506104, 0.006569862366, 0.006729125977, 0.006890296936, 0.007053375244, 0.007218360901, 0.007385253906, 0.00755405426, 0.007724761963, 0.007897377014, 0.008071899414, 0.008248329163, 0.00842666626, 0.008606910706, 0.0087890625, 0.008973121643, 0.009159088135, 0.009346961975, 0.009536743164, 0.009728431702, 0.009922027588, 0.01011753082, 0.01031494141, 0.01051425934, 0.01071548462, 0.01091861725, 0.01112365723, 0.01133060455, 0.01153945923, 0.01175022125, 0.01196289063, 0.01217746735, 0.01239395142, 0.01261234283, 0.0128326416, 0.01305484772, 0.01327896118, 0.01350498199, 0.01373291016, 0.01396274567, 0.01419448853, 0.01442813873, 0.01466369629, 0.01490116119, 0.01514053345, 0.01538181305, 0.015625, 0.0158700943, 0.01611709595, 0.01636600494, 0.01661682129, 0.01686954498, 0.01712417603, 0.01738071442, 0.01763916016, 0.01789951324, 0.01816177368, 0.01842594147, 0.0186920166, 0.01895999908, 0.01922988892, 0.0195016861, 0.01977539063, 0.0200510025, 0.02032852173, 0.0206079483, 0.02088928223, 0.0211725235, 0.02145767212, 0.02174472809, 0.02203369141, 0.02232456207, 0.02261734009, 0.02291202545, 0.02320861816, 0.02350711823, 0.02380752563, 0.02410984039, 0.0244140625, 0.02472019196, 0.02502822876, 0.02533817291, 0.02565002441, 0.02596378326, 0.02627944946, 0.02659702301, 0.02691650391, 0.02723789215, 0.02756118774, 0.02788639069, 0.02821350098, 0.02854251862, 0.0288734436, 0.02920627594, 0.02954101563, 0.02987766266, 0.03021621704, 0.03055667877, 0.03089904785, 0.03124332428, 0.03158950806, 0.03193759918, 0.03228759766, 0.03263950348, 0.03299331665, 0.03334903717, 0.03370666504, 0.03406620026, 0.03442764282, 0.03479099274, 0.03515625, 0.03552341461, 0.03589248657, 0.03626346588, 0.03663635254, 0.03701114655, 0.0373878479, 0.0377664566, 0.03814697266, 0.03852939606, 0.03891372681, 0.0392999649, 0.03968811035, 0.04007816315, 0.04047012329, 0.04086399078, 0.04125976563, 0.04165744781, 0.04205703735, 0.04245853424, 0.04286193848, 0.04326725006, 0.04367446899, 0.04408359528, 0.04449462891, 0.04490756989, 0.04532241821, 0.04573917389, 0.04615783691, 0.04657840729, 0.04700088501, 0.04742527008, 0.0478515625, 0.04827976227, 0.04870986938, 0.04914188385, 0.04957580566, 0.05001163483, 0.05044937134, 0.0508890152, 0.05133056641, 0.05177402496, 0.05221939087, 0.05266666412, 0.05311584473, 0.05356693268, 0.05401992798, 0.05447483063, 0.05493164063, 0.05539035797, 0.05585098267, 0.05631351471, 0.0567779541, 0.05724430084, 0.05771255493, 0.05818271637, 0.05865478516, 0.05912876129, 0.05960464478, 0.06008243561, 0.06056213379, 0.06104373932, 0.0615272522, 0.06201267242, 0.0625, 0.06298923492, 0.0634803772, 0.06397342682, 0.06446838379, 0.06496524811, 0.06546401978, 0.06596469879, 0.06646728516, 0.06697177887, 0.06747817993, 0.06798648834, 0.0684967041, 0.06900882721, 0.06952285767, 0.07003879547, 0.07055664063, 0.07107639313, 0.07159805298, 0.07212162018, 0.07264709473, 0.07317447662, 0.07370376587, 0.07423496246, 0.07476806641, 0.0753030777, 0.07583999634, 0.07637882233, 0.07691955566, 0.07746219635, 0.07800674438, 0.07855319977, 0.0791015625, 0.07965183258, 0.08020401001, 0.08075809479, 0.08131408691, 0.08187198639, 0.08243179321, 0.08299350739, 0.08355712891, 0.08412265778, 0.08469009399, 0.08525943756, 0.08583068848, 0.08640384674, 0.08697891235, 0.08755588531, 0.08813476563, 0.08871555328, 0.08929824829, 0.08988285065, 0.09046936035, 0.0910577774, 0.09164810181, 0.09224033356, 0.09283447266, 0.0934305191, 0.0940284729, 0.09462833405, 0.09523010254, 0.09583377838, 0.09643936157, 0.09704685211, 0.09765625, 0.09826755524, 0.09888076782, 0.09949588776, 0.100112915, 0.1007318497, 0.1013526917, 0.101975441, 0.1026000977, 0.1032266617, 0.1038551331, 0.1044855118, 0.1051177979, 0.1057519913, 0.106388092, 0.1070261002, 0.1076660156, 0.1083078384, 0.1089515686, 0.1095972061, 0.110244751, 0.1108942032, 0.1115455627, 0.1121988297, 0.1128540039, 0.1135110855, 0.1141700745, 0.1148309708, 0.1154937744, 0.1161584854, 0.1168251038, 0.1174936295, 0.1181640625, 0.1188364029, 0.1195106506, 0.1201868057, 0.1208648682, 0.121544838, 0.1222267151, 0.1229104996, 0.1235961914, 0.1242837906, 0.1249732971, 0.125664711, 0.1263580322, 0.1270532608, 0.1277503967, 0.12844944, 0.1291503906, 0.1298532486, 0.1305580139, 0.1312646866, 0.1319732666, 0.132683754, 0.1333961487, 0.1341104507, 0.1348266602, 0.1355447769, 0.136264801, 0.1369867325, 0.1377105713, 0.1384363174, 0.1391639709, 0.1398935318, 0.140625, 0.1413583755, 0.1420936584, 0.1428308487, 0.1435699463, 0.1443109512, 0.1450538635, 0.1457986832, 0.1465454102, 0.1472940445, 0.1480445862, 0.1487970352, 0.1495513916, 0.1503076553, 0.1510658264, 0.1518259048, 0.1525878906, 0.1533517838, 0.1541175842, 0.1548852921, 0.1556549072, 0.1564264297, 0.1571998596, 0.1579751968, 0.1587524414, 0.1595315933, 0.1603126526, 0.1610956192, 0.1618804932, 0.1626672745, 0.1634559631, 0.1642465591, 0.1650390625, 0.1658334732, 0.1666297913, 0.1674280167, 0.1682281494, 0.1690301895, 0.169834137, 0.1706399918, 0.1714477539, 0.1722574234, 0.1730690002, 0.1738824844, 0.174697876, 0.1755151749, 0.1763343811, 0.1771554947, 0.1779785156, 0.1788034439, 0.1796302795, 0.1804590225, 0.1812896729, 0.1821222305, 0.1829566956, 0.1837930679, 0.1846313477, 0.1854715347, 0.1863136292, 0.1871576309, 0.18800354, 0.1888513565, 0.1897010803, 0.1905527115, 0.19140625, 0.1922616959, 0.1931190491, 0.1939783096, 0.1948394775, 0.1957025528, 0.1965675354, 0.1974344254, 0.1983032227, 0.1991739273, 0.2000465393, 0.2009210587, 0.2017974854, 0.2026758194, 0.2035560608, 0.2044382095, 0.2053222656, 0.2062082291, 0.2070960999, 0.207985878, 0.2088775635, 0.2097711563, 0.2106666565, 0.211564064, 0.2124633789, 0.2133646011, 0.2142677307, 0.2151727676, 0.2160797119, 0.2169885635, 0.2178993225, 0.2188119888, 0.2197265625, 0.2206430435, 0.2215614319, 0.2224817276, 0.2234039307, 0.2243280411, 0.2252540588, 0.2261819839, 0.2271118164, 0.2280435562, 0.2289772034, 0.2299127579, 0.2308502197, 0.2317895889, 0.2327308655, 0.2336740494, 0.2346191406, 0.2355661392, 0.2365150452, 0.2374658585, 0.2384185791, 0.2393732071, 0.2403297424, 0.2412881851, 0.2422485352, 0.2432107925, 0.2441749573, 0.2451410294, 0.2461090088, 0.2470788956, 0.2480506897, 0.2490243912, 0.25, 0.2509775162, 0.2519569397, 0.2529382706, 0.2539215088, 0.2549066544, 0.2558937073, 0.2568826675, 0.2578735352, 0.2588663101, 0.2598609924, 0.2608575821, 0.2618560791, 0.2628564835, 0.2638587952, 0.2648630142, 0.2658691406, 0.2668771744, 0.2678871155, 0.2688989639, 0.2699127197, 0.2709283829, 0.2719459534, 0.2729654312, 0.2739868164, 0.2750101089, 0.2760353088, 0.2770624161, 0.2780914307, 0.2791223526, 0.2801551819, 0.2811899185, 0.2822265625, 0.2832651138, 0.2843055725, 0.2853479385, 0.2863922119, 0.2874383926, 0.2884864807, 0.2895364761, 0.2905883789, 0.291642189, 0.2926979065, 0.2937555313, 0.2948150635, 0.295876503, 0.2969398499, 0.2980051041, 0.2990722656, 0.3001413345, 0.3012123108, 0.3022851944, 0.3033599854, 0.3044366837, 0.3055152893, 0.3065958023, 0.3076782227, 0.3087625504, 0.3098487854, 0.3109369278, 0.3120269775, 0.3131189346, 0.3142127991, 0.3153085709, 0.31640625, 0.3175058365, 0.3186073303, 0.3197107315, 0.32081604, 0.3219232559, 0.3230323792, 0.3241434097, 0.3252563477, 0.3263711929, 0.3274879456, 0.3286066055, 0.3297271729, 0.3308496475, 0.3319740295, 0.3331003189, 0.3342285156, 0.3353586197, 0.3364906311, 0.3376245499, 0.338760376, 0.3398981094, 0.3410377502, 0.3421792984, 0.3433227539, 0.3444681168, 0.345615387, 0.3467645645, 0.3479156494, 0.3490686417, 0.3502235413, 0.3513803482, 0.3525390625, 0.3536996841, 0.3548622131, 0.3560266495, 0.3571929932, 0.3583612442, 0.3595314026, 0.3607034683, 0.3618774414, 0.3630533218, 0.3642311096, 0.3654108047, 0.3665924072, 0.3677759171, 0.3689613342, 0.3701486588, 0.3713378906, 0.3725290298, 0.3737220764, 0.3749170303, 0.3761138916, 0.3773126602, 0.3785133362, 0.3797159195, 0.3809204102, 0.3821268082, 0.3833351135, 0.3845453262, 0.3857574463, 0.3869714737, 0.3881874084, 0.3894052505, 0.390625, 0.3918466568, 0.3930702209, 0.3942956924, 0.3955230713, 0.3967523575, 0.397983551, 0.3992166519, 0.4004516602, 0.4016885757, 0.4029273987, 0.404168129, 0.4054107666, 0.4066553116, 0.4079017639, 0.4091501236, 0.4104003906, 0.411652565, 0.4129066467, 0.4141626358, 0.4154205322, 0.416680336, 0.4179420471, 0.4192056656, 0.4204711914, 0.4217386246, 0.4230079651, 0.424279213, 0.4255523682, 0.4268274307, 0.4281044006, 0.4293832779, 0.4306640625, 0.4319467545, 0.4332313538, 0.4345178604, 0.4358062744, 0.4370965958, 0.4383888245, 0.4396829605, 0.4409790039, 0.4422769547, 0.4435768127, 0.4448785782, 0.446182251, 0.4474878311, 0.4487953186, 0.4501047134, 0.4514160156, 0.4527292252, 0.454044342, 0.4553613663, 0.4566802979, 0.4580011368, 0.4593238831, 0.4606485367, 0.4619750977, 0.463303566, 0.4646339417, 0.4659662247, 0.467300415, 0.4686365128, 0.4699745178, 0.4713144302, 0.47265625, 0.4739999771, 0.4753456116, 0.4766931534, 0.4780426025, 0.479393959, 0.4807472229, 0.4821023941, 0.4834594727, 0.4848184586, 0.4861793518, 0.4875421524, 0.4889068604, 0.4902734756, 0.4916419983, 0.4930124283, 0.4943847656, 0.4957590103, 0.4971351624, 0.4985132217, 0.4998931885, 0.5012750626, 0.502658844, 0.5040445328, 0.5054321289, 0.5068216324, 0.5082130432, 0.5096063614, 0.5110015869, 0.5123987198, 0.51379776, 0.5151987076, 0.5166015625, 0.5180063248, 0.5194129944, 0.5208215714, 0.5222320557, 0.5236444473, 0.5250587463, 0.5264749527, 0.5278930664, 0.5293130875, 0.5307350159, 0.5321588516, 0.5335845947, 0.5350122452, 0.536441803, 0.5378732681, 0.5393066406, 0.5407419205, 0.5421791077, 0.5436182022, 0.5450592041, 0.5465021133, 0.5479469299, 0.5493936539, 0.5508422852, 0.5522928238, 0.5537452698, 0.5551996231, 0.5566558838, 0.5581140518, 0.5595741272, 0.5610361099, 0.5625, 0.5639657974, 0.5654335022, 0.5669031143, 0.5683746338, 0.5698480606, 0.5713233948, 0.5728006363, 0.5742797852, 0.5757608414, 0.5772438049, 0.5787286758, 0.5802154541, 0.5817041397, 0.5831947327, 0.584687233, 0.5861816406, 0.5876779556, 0.589176178, 0.5906763077, 0.5921783447, 0.5936822891, 0.5951881409, 0.5966959, 0.5982055664, 0.5997171402, 0.6012306213, 0.6027460098, 0.6042633057, 0.6057825089, 0.6073036194, 0.6088266373, 0.6103515625, 0.6118783951, 0.613407135, 0.6149377823, 0.6164703369, 0.6180047989, 0.6195411682, 0.6210794449, 0.6226196289, 0.6241617203, 0.625705719, 0.6272516251, 0.6287994385, 0.6303491592, 0.6319007874, 0.6334543228, 0.6350097656, 0.6365671158, 0.6381263733, 0.6396875381, 0.6412506104, 0.6428155899, 0.6443824768, 0.6459512711, 0.6475219727, 0.6490945816, 0.6506690979, 0.6522455215, 0.6538238525, 0.6554040909, 0.6569862366, 0.6585702896, 0.66015625, 0.6617441177, 0.6633338928, 0.6649255753, 0.666519165, 0.6681146622, 0.6697120667, 0.6713113785, 0.6729125977, 0.6745157242, 0.6761207581, 0.6777276993, 0.6793365479, 0.6809473038, 0.682559967, 0.6841745377, 0.6857910156, 0.6874094009, 0.6890296936, 0.6906518936, 0.692276001, 0.6939020157, 0.6955299377, 0.6971597672, 0.6987915039, 0.700425148, 0.7020606995, 0.7036981583, 0.7053375244, 0.7069787979, 0.7086219788, 0.710267067, 0.7119140625, 0.7135629654, 0.7152137756, 0.7168664932, 0.7185211182, 0.7201776505, 0.7218360901, 0.7234964371, 0.7251586914, 0.7268228531, 0.7284889221, 0.7301568985, 0.7318267822, 0.7334985733, 0.7351722717, 0.7368478775, 0.7385253906, 0.7402048111, 0.7418861389, 0.7435693741, 0.7452545166, 0.7469415665, 0.7486305237, 0.7503213882, 0.7520141602, 0.7537088394, 0.755405426, 0.75710392, 0.7588043213, 0.7605066299, 0.7622108459, 0.7639169693, 0.765625, 0.767334938, 0.7690467834, 0.7707605362, 0.7724761963, 0.7741937637, 0.7759132385, 0.7776346207, 0.7793579102, 0.781083107, 0.7828102112, 0.7845392227, 0.7862701416, 0.7880029678, 0.7897377014, 0.7914743423, 0.7932128906, 0.7949533463, 0.7966957092, 0.7984399796, 0.8001861572, 0.8019342422, 0.8036842346, 0.8054361343, 0.8071899414, 0.8089456558, 0.8107032776, 0.8124628067, 0.8142242432, 0.815987587, 0.8177528381, 0.8195199966, 0.8212890625, 0.8230600357, 0.8248329163, 0.8266077042, 0.8283843994, 0.830163002, 0.831943512, 0.8337259293, 0.8355102539, 0.8372964859, 0.8390846252, 0.8408746719, 0.842666626, 0.8444604874, 0.8462562561, 0.8480539322, 0.8498535156, 0.8516550064, 0.8534584045, 0.85526371, 0.8570709229, 0.858880043, 0.8606910706, 0.8625040054, 0.8643188477, 0.8661355972, 0.8679542542, 0.8697748184, 0.87159729, 0.873421669, 0.8752479553, 0.877076149, 0.87890625, 0.8807382584, 0.8825721741, 0.8844079971, 0.8862457275, 0.8880853653, 0.8899269104, 0.8917703629, 0.8936157227, 0.8954629898, 0.8973121643, 0.8991632462, 0.9010162354, 0.9028711319, 0.9047279358, 0.906586647, 0.9084472656, 0.9103097916, 0.9121742249, 0.9140405655, 0.9159088135, 0.9177789688, 0.9196510315, 0.9215250015, 0.9234008789, 0.9252786636, 0.9271583557, 0.9290399551, 0.9309234619, 0.932808876, 0.9346961975, 0.9365854263, 0.9384765625, 0.940369606, 0.9422645569, 0.9441614151, 0.9460601807, 0.9479608536, 0.9498634338, 0.9517679214, 0.9536743164, 0.9555826187, 0.9574928284, 0.9594049454, 0.9613189697, 0.9632349014, 0.9651527405, 0.9670724869, 0.9689941406, 0.9709177017, 0.9728431702, 0.974770546, 0.9766998291, 0.9786310196, 0.9805641174, 0.9824991226, 0.9844360352, 0.986374855, 0.9883155823, 0.9902582169, 0.9922027588, 0.9941492081 }; ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/gpio.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file gpio.c * @brief This file provides code for the configuration * of all used GPIO pins. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "gpio.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /*----------------------------------------------------------------------------*/ /* Configure GPIO */ /*----------------------------------------------------------------------------*/ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /** Configure pins */ void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, MUX_C_Pin|MUX_B_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(MUX_A_GPIO_Port, MUX_A_Pin, GPIO_PIN_RESET); /*Configure GPIO pins : PAPin PAPin */ GPIO_InitStruct.Pin = MUX_C_Pin|MUX_B_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = MUX_A_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(MUX_A_GPIO_Port, &GPIO_InitStruct); } /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/lerp.c ================================================ /* * lerp.c * * Created on: Jan 6, 2023 * Author: chrismcdowell */ #include "lerp.h" float lerp_int16(int16_t _buf[], uint16_t _bufsize, float position) { uint16_t integer_part; float float_part; int16_t this_sample, next_sample; if (position < 0.0f) { position += _bufsize; } if (position > (_bufsize - 1)) { position -= _bufsize; } integer_part = (uint16_t) (position); float_part = position - integer_part; this_sample = _buf[integer_part]; if (integer_part < (_bufsize - 1)) { next_sample = _buf[integer_part + 1]; } else { next_sample = _buf[(integer_part + 1) - _bufsize]; } return (((next_sample - this_sample) * float_part) + this_sample); } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/main.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "adc.h" #include "dac.h" #include "dma.h" #include "tim.h" #include "gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #include "chorus.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN PTD */ /* USER CODE END PTD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ volatile uint8_t mux_channel; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); /* USER CODE BEGIN PFP */ void DWT_Start(); /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /** * @brief The application entry point. * @retval int */ int main(void) { /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_DMA_Init(); MX_ADC1_Init(); MX_ADC2_Init(); MX_DAC1_Init(); MX_TIM2_Init(); MX_TIM1_Init(); MX_TIM3_Init(); /* USER CODE BEGIN 2 */ DAC_Start(); ADC1_Start(); ADC2_Start(); TIM1_Start(); TIM2_Start(); TIM3_Start(); DWT_Start(); chorus_init(); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } /* USER CODE END 3 */ } /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; RCC_OscInitStruct.PLL.PLLN = 12; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { Error_Handler(); } } /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { if (hadc->Instance == ADC1) { ADC1_channel_data[mux_channel++] = ADC1_raw_data; if (mux_channel > NUM_ADC1_CHANNELS) { mux_channel = 0; } HAL_GPIO_WritePin(MUX_A_GPIO_Port, MUX_A_Pin, (GPIO_PinState) (mux_channel & 1)); HAL_GPIO_WritePin(MUX_B_GPIO_Port, MUX_B_Pin, (GPIO_PinState) ((mux_channel >> 1) & 1)); HAL_GPIO_WritePin(MUX_C_GPIO_Port, MUX_C_Pin, (GPIO_PinState) ((mux_channel >> 2) & 1)); } } void DWT_Start() { CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; DWT->CYCCNT = 0; DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; } /* USER CODE END 4 */ /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { } /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. * @param file: pointer to the source file name * @param line: assert_param error line source number * @retval None */ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/stm32g4xx_hal_msp.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_hal_msp.c * @brief This file provides code for the MSP Initialization * and de-Initialization codes. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN Define */ /* USER CODE END Define */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN Macro */ /* USER CODE END Macro */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* External functions --------------------------------------------------------*/ /* USER CODE BEGIN ExternalFunctions */ /* USER CODE END ExternalFunctions */ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE(); /* System interrupt init*/ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_PWREx_DisableUCPDDeadBattery(); /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/stm32g4xx_it.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file stm32g4xx_it.c * @brief Interrupt Service Routines. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "stm32g4xx_it.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #include "dac.h" #include "adc.h" #include "chorus.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ /* USER CODE END TD */ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ uint32_t tim2_tick_start; uint32_t tim2_tick_end; uint32_t tim2_ticks; uint32_t chorus_tick_start; uint32_t chorus_tick_end; uint32_t chorus_ticks; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ extern DMA_HandleTypeDef hdma_adc1; extern DMA_HandleTypeDef hdma_adc2; extern TIM_HandleTypeDef htim2; extern TIM_HandleTypeDef htim3; /* USER CODE BEGIN EV */ /* USER CODE END EV */ /******************************************************************************/ /* Cortex-M4 Processor Interruption and Exception Handlers */ /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) { } /* USER CODE END NonMaskableInt_IRQn 1 */ } /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_HardFault_IRQn 0 */ /* USER CODE END W1_HardFault_IRQn 0 */ } } /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ /* USER CODE END W1_MemoryManagement_IRQn 0 */ } } /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_BusFault_IRQn 0 */ /* USER CODE END W1_BusFault_IRQn 0 */ } } /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) { /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ /* USER CODE END W1_UsageFault_IRQn 0 */ } } /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { /* USER CODE BEGIN SVCall_IRQn 0 */ /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { /* USER CODE BEGIN DebugMonitor_IRQn 0 */ /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { /* USER CODE BEGIN PendSV_IRQn 0 */ /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } /******************************************************************************/ /* STM32G4xx Peripheral Interrupt Handlers */ /* Add here the Interrupt Handlers for the used peripherals. */ /* For the available peripheral interrupt handler names, */ /* please refer to the startup file (startup_stm32g4xx.s). */ /******************************************************************************/ /** * @brief This function handles DMA1 channel1 global interrupt. */ void DMA1_Channel1_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } /** * @brief This function handles DMA1 channel2 global interrupt. */ void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ /* USER CODE END DMA1_Channel2_IRQn 1 */ } /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { /* USER CODE BEGIN TIM2_IRQn 0 */ tim2_tick_end = DWT->CYCCNT; tim2_ticks = tim2_tick_end - tim2_tick_start; tim2_tick_start = DWT->CYCCNT; if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(&htim2, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); chorus_tick_start = DWT->CYCCNT; HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, chorus_tick(ADC2_raw_data - 2048) + 2048); chorus_tick_end = DWT->CYCCNT; chorus_ticks = chorus_tick_end - chorus_tick_start; } } #if 0 /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); /* USER CODE BEGIN TIM2_IRQn 1 */ #endif /* USER CODE END TIM2_IRQn 1 */ } /** * @brief This function handles TIM3 global interrupt. */ void TIM3_IRQHandler(void) { /* USER CODE BEGIN TIM3_IRQn 0 */ if (__HAL_TIM_GET_FLAG(&htim3, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(&htim3, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(&htim3, TIM_IT_UPDATE); chorus_params_typedef params; params.delay = ADC1_channel_data[DELAY_POT_INDEX] >> 2; params.delay_cv = ADC1_channel_data[CV_INPUT_INDEX]; params.feedback = ADC1_channel_data[FB_POT_INDEX] >> 2; params.lfo_rate = ADC1_channel_data[RATE_POT_INDEX] >> 2; params.lfo_amount = ADC1_channel_data[AMT_POT_INDEX] >> 2; chorus_control_tick(¶ms); TIM1->CCR1 = (uint16_t) chorus_lfo.output; } } #if 0 /* USER CODE END TIM3_IRQn 0 */ HAL_TIM_IRQHandler(&htim3); /* USER CODE BEGIN TIM3_IRQn 1 */ #endif /* USER CODE END TIM3_IRQn 1 */ } /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/super_filters.cpp ================================================ /* * super_filters.cpp * * Created on: Jan 6, 2023 * Author: chrismcdowell */ #include "super_filters.h" Svf::Svf(float _sample_rate, float _freq, float _q) { freq = (6.28f * _freq) / _sample_rate; q = 1.0f / _q; } void Svf::tick(float _input) { low = delay2 + freq * delay1; high = _input - low - (q * delay1); band = (freq * high) + delay1; delay1 = band; delay2 = low; } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/syscalls.c ================================================ /** ****************************************************************************** * @file syscalls.c * @author Auto-generated by STM32CubeIDE * @brief STM32CubeIDE Minimal System calls file * * For more information about which c-functions * need which of these lowlevel functions * please consult the Newlib libc-manual ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes */ #include #include #include #include #include #include #include #include /* Variables */ extern int __io_putchar(int ch) __attribute__((weak)); extern int __io_getchar(void) __attribute__((weak)); char *__env[1] = { 0 }; char **environ = __env; /* Functions */ void initialise_monitor_handles() { } int _getpid(void) { return 1; } int _kill(int pid, int sig) { errno = EINVAL; return -1; } void _exit (int status) { _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) { *ptr++ = __io_getchar(); } return len; } __attribute__((weak)) int _write(int file, char *ptr, int len) { int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) { __io_putchar(*ptr++); } return len; } int _close(int file) { return -1; } int _fstat(int file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } int _isatty(int file) { return 1; } int _lseek(int file, int ptr, int dir) { return 0; } int _open(char *path, int flags, ...) { /* Pretend like we always fail */ return -1; } int _wait(int *status) { errno = ECHILD; return -1; } int _unlink(char *name) { errno = ENOENT; return -1; } int _times(struct tms *buf) { return -1; } int _stat(char *file, struct stat *st) { st->st_mode = S_IFCHR; return 0; } int _link(char *old, char *new) { errno = EMLINK; return -1; } int _fork(void) { errno = EAGAIN; return -1; } int _execve(char *name, char **argv, char **env) { errno = ENOMEM; return -1; } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/sysmem.c ================================================ /** ****************************************************************************** * @file sysmem.c * @author Generated by STM32CubeIDE * @brief STM32CubeIDE System Memory calls file * * For more information about which C functions * need which of these lowlevel functions * please consult the newlib libc manual ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes */ #include #include /** * Pointer to the current high watermark of the heap usage */ static uint8_t *__sbrk_heap_end = NULL; /** * @brief _sbrk() allocates memory to the newlib heap and is used by malloc * and others from the C library * * @verbatim * ############################################################################ * # .data # .bss # newlib heap # MSP stack # * # # # # Reserved by _Min_Stack_Size # * ############################################################################ * ^-- RAM start ^-- _end _estack, RAM end --^ * @endverbatim * * This implementation starts allocating at the '_end' linker symbol * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack * The implementation considers '_estack' linker symbol to be RAM end * NOTE: If the MSP stack, at any point during execution, grows larger than the * reserved size, please increase the '_Min_Stack_Size'. * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; const uint8_t *max_heap = (uint8_t *)stack_limit; uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) { __sbrk_heap_end = &_end; } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) { errno = ENOMEM; return (void *)-1; } prev_heap_end = __sbrk_heap_end; __sbrk_heap_end += incr; return (void *)prev_heap_end; } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/system_stm32g4xx.c ================================================ /** ****************************************************************************** * @file system_stm32g4xx.c * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File * * This file provides two functions and one global variable to be called from * user application: * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32g4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * After each device reset the HSI (16 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to * configure the system clock before to branch to main program. * * This file configures the system clock as follows: *============================================================================= *----------------------------------------------------------------------------- * System Clock source | HSI *----------------------------------------------------------------------------- * SYSCLK(Hz) | 16000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 16000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 1 *----------------------------------------------------------------------------- * APB2 Prescaler | 1 *----------------------------------------------------------------------------- * PLL_M | 1 *----------------------------------------------------------------------------- * PLL_N | 16 *----------------------------------------------------------------------------- * PLL_P | 7 *----------------------------------------------------------------------------- * PLL_Q | 2 *----------------------------------------------------------------------------- * PLL_R | 2 *----------------------------------------------------------------------------- * Require 48MHz for RNG | Disabled *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32g4xx_system * @{ */ /** @addtogroup STM32G4xx_System_Private_Includes * @{ */ #include "stm32g4xx.h" #if !defined (HSE_VALUE) #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Defines * @{ */ /************************* Miscellaneous Configuration ************************/ /* Note: Following vector table addresses must be defined in line with linker configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ /* #define USER_VECT_TAB_ADDRESS */ #if defined(USER_VECT_TAB_ADDRESS) /*!< Uncomment the following line if you need to relocate your vector Table in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Variables * @{ */ /* The SystemCoreClock variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ uint32_t SystemCoreClock = HSI_VALUE; const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; /** * @} */ /** @addtogroup STM32G4xx_System_Private_FunctionPrototypes * @{ */ /** * @} */ /** @addtogroup STM32G4xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ #endif /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value * 24 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp, pllvco, pllr, pllsource, pllm; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) { case 0x04: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; break; case 0x08: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; break; case 0x0C: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ; if (pllsource == 0x02UL) /* HSI used as PLL clock source */ { pllvco = (HSI_VALUE / pllm); } else /* HSE used as PLL clock source */ { pllvco = (HSE_VALUE / pllm); } pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8); pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U; SystemCoreClock = pllvco/pllr; break; default: break; } /* Compute HCLK clock frequency --------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } /** * @} */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Src/tim.c ================================================ /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file tim.c * @brief This file provides code for the configuration * of the TIM instances. ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "tim.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ TIM_HandleTypeDef htim1; TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM1 init function */ void MX_TIM1_Init(void) { /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; TIM_OC_InitTypeDef sConfigOC = {0}; TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; htim1.Init.Prescaler = 200; htim1.Init.CounterMode = TIM_COUNTERMODE_UP; htim1.Init.Period = 4096; htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim1.Init.RepetitionCounter = 0; htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim1) != HAL_OK) { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) { Error_Handler(); } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) { Error_Handler(); } sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.Pulse = 512; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) { Error_Handler(); } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; sBreakDeadTimeConfig.DeadTime = 0; sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; sBreakDeadTimeConfig.BreakFilter = 0; sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; sBreakDeadTimeConfig.Break2Filter = 0; sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); } /* TIM2 init function */ void MX_TIM2_Init(void) { /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; htim2.Init.Prescaler = 0; htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.Period = 960; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim2) != HAL_OK) { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } /* TIM3 init function */ void MX_TIM3_Init(void) { /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0}; /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; htim3.Init.Prescaler = 0; htim3.Init.CounterMode = TIM_COUNTERMODE_UP; htim3.Init.Period = 6400; htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&htim3) != HAL_OK) { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) { Error_Handler(); } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) { if(tim_baseHandle->Instance==TIM1) { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* TIM1 clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); /* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE END TIM1_MspInit 1 */ } else if(tim_baseHandle->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* TIM2 clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); HAL_NVIC_EnableIRQ(TIM2_IRQn); /* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */ } else if(tim_baseHandle->Instance==TIM3) { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* TIM3 clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 2, 0); HAL_NVIC_EnableIRQ(TIM3_IRQn); /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(timHandle->Instance==TIM1) { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); /**TIM1 GPIO Configuration PA8 ------> TIM1_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_8; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF6_TIM1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* USER CODE BEGIN TIM1_MspPostInit 1 */ /* USER CODE END TIM1_MspPostInit 1 */ } } void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) { if(tim_baseHandle->Instance==TIM1) { /* USER CODE BEGIN TIM1_MspDeInit 0 */ /* USER CODE END TIM1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM1_CLK_DISABLE(); /* USER CODE BEGIN TIM1_MspDeInit 1 */ /* USER CODE END TIM1_MspDeInit 1 */ } else if(tim_baseHandle->Instance==TIM2) { /* USER CODE BEGIN TIM2_MspDeInit 0 */ /* USER CODE END TIM2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM2_CLK_DISABLE(); /* TIM2 interrupt Deinit */ HAL_NVIC_DisableIRQ(TIM2_IRQn); /* USER CODE BEGIN TIM2_MspDeInit 1 */ /* USER CODE END TIM2_MspDeInit 1 */ } else if(tim_baseHandle->Instance==TIM3) { /* USER CODE BEGIN TIM3_MspDeInit 0 */ /* USER CODE END TIM3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM3_CLK_DISABLE(); /* TIM3 interrupt Deinit */ HAL_NVIC_DisableIRQ(TIM3_IRQn); /* USER CODE BEGIN TIM3_MspDeInit 1 */ /* USER CODE END TIM3_MspDeInit 1 */ } } /* USER CODE BEGIN 1 */ void TIM1_Start() { HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); } void TIM2_Start() { HAL_TIM_Base_Start_IT(&htim2); } void TIM3_Start() { HAL_TIM_Base_Start_IT(&htim3); } /* USER CODE END 1 */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Core/Startup/startup_stm32g431kbux.s ================================================ /** ****************************************************************************** * @file startup_stm32g431xx.s * @author MCD Application Team * @brief STM32G431xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address, * - Configure the clock system * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss .equ BootRAM, 0xF1E0F85F /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata ldr r2, =_sidata movs r3, #0 b LoopCopyDataInit CopyDataInit: ldr r4, [r2, r3] str r4, [r0, r3] adds r3, r3, #4 LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss movs r3, #0 b LoopFillZerobss FillZerobss: str r3, [r2] adds r2, r2, #4 LoopFillZerobss: cmp r2, r4 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main LoopForever: b LoopForever .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex-M4. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler .word WWDG_IRQHandler .word PVD_PVM_IRQHandler .word RTC_TAMP_LSECSS_IRQHandler .word RTC_WKUP_IRQHandler .word FLASH_IRQHandler .word RCC_IRQHandler .word EXTI0_IRQHandler .word EXTI1_IRQHandler .word EXTI2_IRQHandler .word EXTI3_IRQHandler .word EXTI4_IRQHandler .word DMA1_Channel1_IRQHandler .word DMA1_Channel2_IRQHandler .word DMA1_Channel3_IRQHandler .word DMA1_Channel4_IRQHandler .word DMA1_Channel5_IRQHandler .word DMA1_Channel6_IRQHandler .word 0 .word ADC1_2_IRQHandler .word USB_HP_IRQHandler .word USB_LP_IRQHandler .word FDCAN1_IT0_IRQHandler .word FDCAN1_IT1_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_TIM15_IRQHandler .word TIM1_UP_TIM16_IRQHandler .word TIM1_TRG_COM_TIM17_IRQHandler .word TIM1_CC_IRQHandler .word TIM2_IRQHandler .word TIM3_IRQHandler .word TIM4_IRQHandler .word I2C1_EV_IRQHandler .word I2C1_ER_IRQHandler .word I2C2_EV_IRQHandler .word I2C2_ER_IRQHandler .word SPI1_IRQHandler .word SPI2_IRQHandler .word USART1_IRQHandler .word USART2_IRQHandler .word USART3_IRQHandler .word EXTI15_10_IRQHandler .word RTC_Alarm_IRQHandler .word USBWakeUp_IRQHandler .word TIM8_BRK_IRQHandler .word TIM8_UP_IRQHandler .word TIM8_TRG_COM_IRQHandler .word TIM8_CC_IRQHandler .word 0 .word 0 .word LPTIM1_IRQHandler .word 0 .word SPI3_IRQHandler .word UART4_IRQHandler .word 0 .word TIM6_DAC_IRQHandler .word TIM7_IRQHandler .word DMA2_Channel1_IRQHandler .word DMA2_Channel2_IRQHandler .word DMA2_Channel3_IRQHandler .word DMA2_Channel4_IRQHandler .word DMA2_Channel5_IRQHandler .word 0 .word 0 .word UCPD1_IRQHandler .word COMP1_2_3_IRQHandler .word COMP4_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word CRS_IRQHandler .word SAI1_IRQHandler .word 0 .word 0 .word 0 .word 0 .word FPU_IRQHandler .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word 0 .word RNG_IRQHandler .word LPUART1_IRQHandler .word I2C3_EV_IRQHandler .word I2C3_ER_IRQHandler .word DMAMUX_OVR_IRQHandler .word 0 .word 0 .word DMA2_Channel6_IRQHandler .word 0 .word 0 .word CORDIC_IRQHandler .word FMAC_IRQHandler /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_PVM_IRQHandler .thumb_set PVD_PVM_IRQHandler,Default_Handler .weak RTC_TAMP_LSECSS_IRQHandler .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Channel1_IRQHandler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler .weak DMA1_Channel2_IRQHandler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler .weak DMA1_Channel3_IRQHandler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler .weak DMA1_Channel4_IRQHandler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler .weak DMA1_Channel6_IRQHandler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler .weak USB_HP_IRQHandler .thumb_set USB_HP_IRQHandler,Default_Handler .weak USB_LP_IRQHandler .thumb_set USB_LP_IRQHandler,Default_Handler .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM15_IRQHandler .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler .weak TIM1_UP_TIM16_IRQHandler .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM17_IRQHandler .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak USBWakeUp_IRQHandler .thumb_set USBWakeUp_IRQHandler,Default_Handler .weak TIM8_BRK_IRQHandler .thumb_set TIM8_BRK_IRQHandler,Default_Handler .weak TIM8_UP_IRQHandler .thumb_set TIM8_UP_IRQHandler,Default_Handler .weak TIM8_TRG_COM_IRQHandler .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Channel1_IRQHandler .thumb_set DMA2_Channel1_IRQHandler,Default_Handler .weak DMA2_Channel2_IRQHandler .thumb_set DMA2_Channel2_IRQHandler,Default_Handler .weak DMA2_Channel3_IRQHandler .thumb_set DMA2_Channel3_IRQHandler,Default_Handler .weak DMA2_Channel4_IRQHandler .thumb_set DMA2_Channel4_IRQHandler,Default_Handler .weak DMA2_Channel5_IRQHandler .thumb_set DMA2_Channel5_IRQHandler,Default_Handler .weak UCPD1_IRQHandler .thumb_set UCPD1_IRQHandler,Default_Handler .weak COMP1_2_3_IRQHandler .thumb_set COMP1_2_3_IRQHandler,Default_Handler .weak COMP4_IRQHandler .thumb_set COMP4_IRQHandler,Default_Handler .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler .weak LPUART1_IRQHandler .thumb_set LPUART1_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak DMAMUX_OVR_IRQHandler .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler .weak DMA2_Channel6_IRQHandler .thumb_set DMA2_Channel6_IRQHandler,Default_Handler .weak CORDIC_IRQHandler .thumb_set CORDIC_IRQHandler,Default_Handler .weak FMAC_IRQHandler .thumb_set FMAC_IRQHandler,Default_Handler ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Inc/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (11.3.rel1) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables # Each subdirectory must supply rules for building sources it contributes ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/adc.cyclo ================================================ ../Core/Src/adc.c:33:6:MX_ADC1_Init 4 ../Core/Src/adc.c:93:6:MX_ADC2_Init 3 ../Core/Src/adc.c:147:6:HAL_ADC_MspInit 9 ../Core/Src/adc.c:257:6:HAL_ADC_MspDeInit 5 ../Core/Src/adc.c:308:6:ADC1_Start 1 ../Core/Src/adc.c:311:6:ADC2_Start 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/adc.d ================================================ Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/adc.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/adc.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/adc.su ================================================ ../Core/Src/adc.c:33:6:MX_ADC1_Init 56 static ../Core/Src/adc.c:93:6:MX_ADC2_Init 40 static ../Core/Src/adc.c:147:6:HAL_ADC_MspInit 120 static ../Core/Src/adc.c:257:6:HAL_ADC_MspDeInit 8 static ../Core/Src/adc.c:308:6:ADC1_Start 0 static ../Core/Src/adc.c:311:6:ADC2_Start 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/c_filters.cyclo ================================================ ../Core/Src/c_filters.c:10:6:svf_init 2 ../Core/Src/c_filters.c:24:6:svf_tick 1 ../Core/Src/c_filters.c:33:6:svf_set_freq 2 ../Core/Src/c_filters.c:41:6:svf_set_a_direct 1 ../Core/Src/c_filters.c:45:6:svf_set_q 1 ../Core/Src/c_filters.c:52:7:svf_get_low 1 ../Core/Src/c_filters.c:56:7:svf_get_high 1 ../Core/Src/c_filters.c:60:7:svf_get_band 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/c_filters.d ================================================ Core/Src/c_filters.o: ../Core/Src/c_filters.c ../Core/Inc/c_filters.h \ ../Core/Inc/main.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/c_filters.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/c_filters.su ================================================ ../Core/Src/c_filters.c:10:6:svf_init 0 static ../Core/Src/c_filters.c:24:6:svf_tick 0 static ../Core/Src/c_filters.c:33:6:svf_set_freq 0 static ../Core/Src/c_filters.c:41:6:svf_set_a_direct 0 static ../Core/Src/c_filters.c:45:6:svf_set_q 0 static ../Core/Src/c_filters.c:52:7:svf_get_low 0 static ../Core/Src/c_filters.c:56:7:svf_get_high 0 static ../Core/Src/c_filters.c:60:7:svf_get_band 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/chorus.cyclo ================================================ ../Core/Src/chorus.c:24:10:lfo_tick 1 ../Core/Src/chorus.c:32:7:chorus_tick 5 ../Core/Src/chorus.c:101:6:chorus_control_tick 1 ../Core/Src/chorus.c:121:6:chorus_init 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/chorus.d ================================================ Core/Src/chorus.o: ../Core/Src/chorus.c ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Core/Inc/chorus.h ../Core/Inc/dynamic_smooth.h ../Core/Inc/main.h \ ../Core/Inc/c_filters.h ../Core/Inc/big_sine_wave.h \ ../Core/Inc/float_expo_table.h ../Core/Inc/lerp.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Core/Inc/chorus.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/main.h: ../Core/Inc/c_filters.h: ../Core/Inc/big_sine_wave.h: ../Core/Inc/float_expo_table.h: ../Core/Inc/lerp.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/chorus.su ================================================ ../Core/Src/chorus.c:24:10:lfo_tick 0 static ../Core/Src/chorus.c:32:7:chorus_tick 24 static ../Core/Src/chorus.c:101:6:chorus_control_tick 0 static ../Core/Src/chorus.c:121:6:chorus_init 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dac.cyclo ================================================ ../Core/Src/dac.c:30:6:MX_DAC1_Init 4 ../Core/Src/dac.c:76:6:HAL_DAC_MspInit 2 ../Core/Src/dac.c:104:6:HAL_DAC_MspDeInit 2 ../Core/Src/dac.c:129:6:DAC_Start 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dac.d ================================================ Core/Src/dac.o: ../Core/Src/dac.c ../Core/Inc/dac.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/dac.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dac.su ================================================ ../Core/Src/dac.c:30:6:MX_DAC1_Init 56 static ../Core/Src/dac.c:76:6:HAL_DAC_MspInit 40 static ../Core/Src/dac.c:104:6:HAL_DAC_MspDeInit 0 static ../Core/Src/dac.c:129:6:DAC_Start 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dma.cyclo ================================================ ../Core/Src/dma.c:39:6:MX_DMA_Init 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dma.d ================================================ Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/dma.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dma.su ================================================ ../Core/Src/dma.c:39:6:MX_DMA_Init 16 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dynamic_smooth.cyclo ================================================ ../Core/Src/dynamic_smooth.c:12:7:cm_min 1 ../Core/Src/dynamic_smooth.c:16:7:cm_abs 1 ../Core/Src/dynamic_smooth.c:24:6:dynamic_smooth_init 1 ../Core/Src/dynamic_smooth.c:43:7:dynamic_smooth_tick 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dynamic_smooth.d ================================================ Core/Src/dynamic_smooth.o: ../Core/Src/dynamic_smooth.c \ ../Core/Inc/dynamic_smooth.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/dynamic_smooth.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/dynamic_smooth.su ================================================ ../Core/Src/dynamic_smooth.c:12:7:cm_min 0 static ../Core/Src/dynamic_smooth.c:16:7:cm_abs 0 static ../Core/Src/dynamic_smooth.c:24:6:dynamic_smooth_init 16 static ../Core/Src/dynamic_smooth.c:43:7:dynamic_smooth_tick 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/float_expo_table.cyclo ================================================ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/float_expo_table.d ================================================ Core/Src/float_expo_table.o: ../Core/Src/float_expo_table.c \ ../Core/Inc/main.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Core/Inc/float_expo_table.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Core/Inc/float_expo_table.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/float_expo_table.su ================================================ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/gpio.cyclo ================================================ ../Core/Src/gpio.c:37:6:MX_GPIO_Init 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/gpio.d ================================================ Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/gpio.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/gpio.su ================================================ ../Core/Src/gpio.c:37:6:MX_GPIO_Init 56 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/lerp.cyclo ================================================ ../Core/Src/lerp.c:10:7:lerp_int16 4 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/lerp.d ================================================ Core/Src/lerp.o: ../Core/Src/lerp.c ../Core/Inc/lerp.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/lerp.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/lerp.su ================================================ ../Core/Src/lerp.c:10:7:lerp_int16 4 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/main.cyclo ================================================ ../Core/Src/main.c:124:6:void SystemClock_Config() 3 ../Core/Src/main.c:68:5:int main() 1 ../Core/Src/main.c:166:6:void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef*) 3 ../Core/Src/main.c:185:6:void DWT_Start() 1 ../Core/Src/main.c:197:6:void Error_Handler() 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/main.d ================================================ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Core/Inc/adc.h ../Core/Inc/main.h ../Core/Inc/dac.h ../Core/Inc/dma.h \ ../Core/Inc/tim.h ../Core/Inc/gpio.h ../Core/Inc/chorus.h \ ../Core/Inc/dynamic_smooth.h ../Core/Inc/c_filters.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Core/Inc/adc.h: ../Core/Inc/main.h: ../Core/Inc/dac.h: ../Core/Inc/dma.h: ../Core/Inc/tim.h: ../Core/Inc/gpio.h: ../Core/Inc/chorus.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/c_filters.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/main.su ================================================ ../Core/Src/main.c:124:6:void SystemClock_Config() 88 static,ignoring_inline_asm ../Core/Src/main.c:68:5:int main() 8 static ../Core/Src/main.c:166:6:void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef*) 8 static ../Core/Src/main.c:185:6:void DWT_Start() 0 static ../Core/Src/main.c:197:6:void Error_Handler() 0 static,ignoring_inline_asm ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/stm32g4xx_hal_msp.cyclo ================================================ ../Core/Src/stm32g4xx_hal_msp.c:63:6:HAL_MspInit 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/stm32g4xx_hal_msp.d ================================================ Core/Src/stm32g4xx_hal_msp.o: ../Core/Src/stm32g4xx_hal_msp.c \ ../Core/Inc/main.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/stm32g4xx_hal_msp.su ================================================ ../Core/Src/stm32g4xx_hal_msp.c:63:6:HAL_MspInit 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/stm32g4xx_it.cyclo ================================================ ../Core/Src/stm32g4xx_it.c:81:6:NMI_Handler 1 ../Core/Src/stm32g4xx_it.c:95:6:HardFault_Handler 1 ../Core/Src/stm32g4xx_it.c:110:6:MemManage_Handler 1 ../Core/Src/stm32g4xx_it.c:125:6:BusFault_Handler 1 ../Core/Src/stm32g4xx_it.c:140:6:UsageFault_Handler 1 ../Core/Src/stm32g4xx_it.c:155:6:SVC_Handler 1 ../Core/Src/stm32g4xx_it.c:168:6:DebugMon_Handler 1 ../Core/Src/stm32g4xx_it.c:181:6:PendSV_Handler 1 ../Core/Src/stm32g4xx_it.c:194:6:SysTick_Handler 1 ../Core/Src/stm32g4xx_it.c:215:6:DMA1_Channel1_IRQHandler 1 ../Core/Src/stm32g4xx_it.c:229:6:DMA1_Channel2_IRQHandler 1 ../Core/Src/stm32g4xx_it.c:243:6:TIM2_IRQHandler 3 ../Core/Src/stm32g4xx_it.c:276:6:TIM3_IRQHandler 3 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/stm32g4xx_it.d ================================================ Core/Src/stm32g4xx_it.o: ../Core/Src/stm32g4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h \ ../Core/Inc/stm32g4xx_it.h ../Core/Inc/dac.h ../Core/Inc/main.h \ ../Core/Inc/adc.h ../Core/Inc/chorus.h ../Core/Inc/dynamic_smooth.h \ ../Core/Inc/c_filters.h ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ../Core/Inc/stm32g4xx_it.h: ../Core/Inc/dac.h: ../Core/Inc/main.h: ../Core/Inc/adc.h: ../Core/Inc/chorus.h: ../Core/Inc/dynamic_smooth.h: ../Core/Inc/c_filters.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/stm32g4xx_it.su ================================================ ../Core/Src/stm32g4xx_it.c:81:6:NMI_Handler 0 static ../Core/Src/stm32g4xx_it.c:95:6:HardFault_Handler 0 static ../Core/Src/stm32g4xx_it.c:110:6:MemManage_Handler 0 static ../Core/Src/stm32g4xx_it.c:125:6:BusFault_Handler 0 static ../Core/Src/stm32g4xx_it.c:140:6:UsageFault_Handler 0 static ../Core/Src/stm32g4xx_it.c:155:6:SVC_Handler 0 static ../Core/Src/stm32g4xx_it.c:168:6:DebugMon_Handler 0 static ../Core/Src/stm32g4xx_it.c:181:6:PendSV_Handler 0 static ../Core/Src/stm32g4xx_it.c:194:6:SysTick_Handler 0 static ../Core/Src/stm32g4xx_it.c:215:6:DMA1_Channel1_IRQHandler 0 static ../Core/Src/stm32g4xx_it.c:229:6:DMA1_Channel2_IRQHandler 0 static ../Core/Src/stm32g4xx_it.c:243:6:TIM2_IRQHandler 16 static ../Core/Src/stm32g4xx_it.c:276:6:TIM3_IRQHandler 24 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (11.3.rel1) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables CPP_SRCS += \ ../Core/Src/super_filters.cpp C_SRCS += \ ../Core/Src/adc.c \ ../Core/Src/c_filters.c \ ../Core/Src/chorus.c \ ../Core/Src/dac.c \ ../Core/Src/dma.c \ ../Core/Src/dynamic_smooth.c \ ../Core/Src/float_expo_table.c \ ../Core/Src/gpio.c \ ../Core/Src/lerp.c \ ../Core/Src/main.c \ ../Core/Src/stm32g4xx_hal_msp.c \ ../Core/Src/stm32g4xx_it.c \ ../Core/Src/syscalls.c \ ../Core/Src/sysmem.c \ ../Core/Src/system_stm32g4xx.c \ ../Core/Src/tim.c C_DEPS += \ ./Core/Src/adc.d \ ./Core/Src/c_filters.d \ ./Core/Src/chorus.d \ ./Core/Src/dac.d \ ./Core/Src/dma.d \ ./Core/Src/dynamic_smooth.d \ ./Core/Src/float_expo_table.d \ ./Core/Src/gpio.d \ ./Core/Src/lerp.d \ ./Core/Src/main.d \ ./Core/Src/stm32g4xx_hal_msp.d \ ./Core/Src/stm32g4xx_it.d \ ./Core/Src/syscalls.d \ ./Core/Src/sysmem.d \ ./Core/Src/system_stm32g4xx.d \ ./Core/Src/tim.d OBJS += \ ./Core/Src/adc.o \ ./Core/Src/c_filters.o \ ./Core/Src/chorus.o \ ./Core/Src/dac.o \ ./Core/Src/dma.o \ ./Core/Src/dynamic_smooth.o \ ./Core/Src/float_expo_table.o \ ./Core/Src/gpio.o \ ./Core/Src/lerp.o \ ./Core/Src/main.o \ ./Core/Src/stm32g4xx_hal_msp.o \ ./Core/Src/stm32g4xx_it.o \ ./Core/Src/super_filters.o \ ./Core/Src/syscalls.o \ ./Core/Src/sysmem.o \ ./Core/Src/system_stm32g4xx.o \ ./Core/Src/tim.o CPP_DEPS += \ ./Core/Src/super_filters.d # Each subdirectory must supply rules for building sources it contributes Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -Ofast -ffunction-sections -fdata-sections -Wall -fcommon -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" Core/Src/main.o: ../Core/Src/main.c Core/Src/subdir.mk arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -Ofast -ffunction-sections -fdata-sections -Wall -fcommon -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.cpp Core/Src/subdir.mk arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -Ofast -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fcommon -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Core-2f-Src clean-Core-2f-Src: -$(RM) ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/c_filters.cyclo ./Core/Src/c_filters.d ./Core/Src/c_filters.o ./Core/Src/c_filters.su ./Core/Src/chorus.cyclo ./Core/Src/chorus.d ./Core/Src/chorus.o ./Core/Src/chorus.su ./Core/Src/dac.cyclo ./Core/Src/dac.d ./Core/Src/dac.o ./Core/Src/dac.su ./Core/Src/dma.cyclo ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/dma.su ./Core/Src/dynamic_smooth.cyclo ./Core/Src/dynamic_smooth.d ./Core/Src/dynamic_smooth.o ./Core/Src/dynamic_smooth.su ./Core/Src/float_expo_table.cyclo ./Core/Src/float_expo_table.d ./Core/Src/float_expo_table.o ./Core/Src/float_expo_table.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/lerp.cyclo ./Core/Src/lerp.d ./Core/Src/lerp.o ./Core/Src/lerp.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32g4xx_hal_msp.cyclo ./Core/Src/stm32g4xx_hal_msp.d ./Core/Src/stm32g4xx_hal_msp.o ./Core/Src/stm32g4xx_hal_msp.su ./Core/Src/stm32g4xx_it.cyclo ./Core/Src/stm32g4xx_it.d ./Core/Src/stm32g4xx_it.o ./Core/Src/stm32g4xx_it.su ./Core/Src/super_filters.cyclo ./Core/Src/super_filters.d ./Core/Src/super_filters.o ./Core/Src/super_filters.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32g4xx.cyclo ./Core/Src/system_stm32g4xx.d ./Core/Src/system_stm32g4xx.o ./Core/Src/system_stm32g4xx.su ./Core/Src/tim.cyclo ./Core/Src/tim.d ./Core/Src/tim.o ./Core/Src/tim.su .PHONY: clean-Core-2f-Src ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/super_filters.cyclo ================================================ ../Core/Src/super_filters.cpp:10:1:Svf::Svf(float, float, float) 1 ../Core/Src/super_filters.cpp:14:6:void Svf::tick(float) 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/super_filters.d ================================================ Core/Src/super_filters.o: ../Core/Src/super_filters.cpp \ ../Core/Inc/super_filters.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/super_filters.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/super_filters.su ================================================ ../Core/Src/super_filters.cpp:10:1:Svf::Svf(float, float, float) 0 static ../Core/Src/super_filters.cpp:14:6:void Svf::tick(float) 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/syscalls.cyclo ================================================ ../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 ../Core/Src/syscalls.c:48:5:_getpid 1 ../Core/Src/syscalls.c:53:5:_kill 1 ../Core/Src/syscalls.c:59:6:_exit 1 ../Core/Src/syscalls.c:65:27:_read 3 ../Core/Src/syscalls.c:77:27:_write 3 ../Core/Src/syscalls.c:88:5:_close 1 ../Core/Src/syscalls.c:94:5:_fstat 1 ../Core/Src/syscalls.c:100:5:_isatty 1 ../Core/Src/syscalls.c:105:5:_lseek 1 ../Core/Src/syscalls.c:110:5:_open 1 ../Core/Src/syscalls.c:116:5:_wait 1 ../Core/Src/syscalls.c:122:5:_unlink 1 ../Core/Src/syscalls.c:128:5:_times 1 ../Core/Src/syscalls.c:133:5:_stat 1 ../Core/Src/syscalls.c:139:5:_link 1 ../Core/Src/syscalls.c:145:5:_fork 1 ../Core/Src/syscalls.c:151:5:_execve 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/syscalls.d ================================================ Core/Src/syscalls.o: ../Core/Src/syscalls.c ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/syscalls.su ================================================ ../Core/Src/syscalls.c:44:6:initialise_monitor_handles 0 static ../Core/Src/syscalls.c:48:5:_getpid 0 static ../Core/Src/syscalls.c:53:5:_kill 8 static ../Core/Src/syscalls.c:59:6:_exit 8 static ../Core/Src/syscalls.c:65:27:_read 16 static ../Core/Src/syscalls.c:77:27:_write 16 static ../Core/Src/syscalls.c:88:5:_close 0 static ../Core/Src/syscalls.c:94:5:_fstat 0 static ../Core/Src/syscalls.c:100:5:_isatty 0 static ../Core/Src/syscalls.c:105:5:_lseek 0 static ../Core/Src/syscalls.c:110:5:_open 0 static ../Core/Src/syscalls.c:116:5:_wait 8 static ../Core/Src/syscalls.c:122:5:_unlink 8 static ../Core/Src/syscalls.c:128:5:_times 0 static ../Core/Src/syscalls.c:133:5:_stat 0 static ../Core/Src/syscalls.c:139:5:_link 8 static ../Core/Src/syscalls.c:145:5:_fork 8 static ../Core/Src/syscalls.c:151:5:_execve 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/sysmem.cyclo ================================================ ../Core/Src/sysmem.c:53:7:_sbrk 3 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/sysmem.d ================================================ Core/Src/sysmem.o: ../Core/Src/sysmem.c ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/sysmem.su ================================================ ../Core/Src/sysmem.c:53:7:_sbrk 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/system_stm32g4xx.cyclo ================================================ ../Core/Src/system_stm32g4xx.c:179:6:SystemInit 1 ../Core/Src/system_stm32g4xx.c:228:6:SystemCoreClockUpdate 5 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/system_stm32g4xx.d ================================================ Core/Src/system_stm32g4xx.o: ../Core/Src/system_stm32g4xx.c \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/system_stm32g4xx.su ================================================ ../Core/Src/system_stm32g4xx.c:179:6:SystemInit 0 static ../Core/Src/system_stm32g4xx.c:228:6:SystemCoreClockUpdate 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/tim.cyclo ================================================ ../Core/Src/tim.c:32:6:MX_TIM1_Init 8 ../Core/Src/tim.c:109:6:MX_TIM2_Init 4 ../Core/Src/tim.c:149:6:MX_TIM3_Init 4 ../Core/Src/tim.c:189:6:HAL_TIM_Base_MspInit 4 ../Core/Src/tim.c:234:6:HAL_TIM_MspPostInit 2 ../Core/Src/tim.c:262:6:HAL_TIM_Base_MspDeInit 4 ../Core/Src/tim.c:308:6:TIM1_Start 1 ../Core/Src/tim.c:312:6:TIM2_Start 1 ../Core/Src/tim.c:316:6:TIM3_Start 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/tim.d ================================================ Core/Src/tim.o: ../Core/Src/tim.c ../Core/Inc/tim.h ../Core/Inc/main.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Core/Inc/tim.h: ../Core/Inc/main.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Src/tim.su ================================================ ../Core/Src/tim.c:32:6:MX_TIM1_Init 160 static ../Core/Src/tim.c:109:6:MX_TIM2_Init 40 static ../Core/Src/tim.c:149:6:MX_TIM3_Init 40 static ../Core/Src/tim.c:189:6:HAL_TIM_Base_MspInit 24 static ../Core/Src/tim.c:234:6:HAL_TIM_MspPostInit 40 static ../Core/Src/tim.c:262:6:HAL_TIM_Base_MspDeInit 0 static ../Core/Src/tim.c:308:6:TIM1_Start 0 static ../Core/Src/tim.c:312:6:TIM2_Start 0 static ../Core/Src/tim.c:316:6:TIM3_Start 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Startup/startup_stm32g431kbux.d ================================================ Core/Startup/startup_stm32g431kbux.o: \ ../Core/Startup/startup_stm32g431kbux.s ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Core/Startup/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (11.3.rel1) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables S_SRCS += \ ../Core/Startup/startup_stm32g431kbux.s S_DEPS += \ ./Core/Startup/startup_stm32g431kbux.d OBJS += \ ./Core/Startup/startup_stm32g431kbux.o # Each subdirectory must supply rules for building sources it contributes Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" clean: clean-Core-2f-Startup clean-Core-2f-Startup: -$(RM) ./Core/Startup/startup_stm32g431kbux.d ./Core/Startup/startup_stm32g431kbux.o .PHONY: clean-Core-2f-Startup ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:221:13:HAL_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:232:13:HAL_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:192:19:HAL_DeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:255:26:HAL_InitTick 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:148:19:HAL_Init 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:322:13:HAL_IncTick 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:333:17:HAL_GetTick 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:342:10:HAL_GetTickPrio 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:351:19:HAL_SetTickFreq 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:383:10:HAL_GetTickFreq 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:399:13:HAL_Delay 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:425:13:HAL_SuspendTick 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:441:13:HAL_ResumeTick 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:451:10:HAL_GetHalVersion 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:460:10:HAL_GetREVID 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:469:10:HAL_GetDEVID 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:498:6:HAL_DBGMCU_EnableDBGSleepMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:507:6:HAL_DBGMCU_DisableDBGSleepMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStopMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStopMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:534:6:HAL_DBGMCU_EnableDBGStandbyMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:543:6:HAL_DBGMCU_DisableDBGStandbyMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:576:6:HAL_SYSCFG_CCMSRAMErase 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:595:6:HAL_SYSCFG_EnableMemorySwappingBank 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:610:6:HAL_SYSCFG_DisableMemorySwappingBank 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:628:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:644:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:658:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:670:19:HAL_SYSCFG_EnableVREFBUF 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:696:6:HAL_SYSCFG_DisableVREFBUF 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:707:6:HAL_SYSCFG_EnableIOSwitchBooster 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:717:6:HAL_SYSCFG_DisableIOSwitchBooster 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:727:6:HAL_SYSCFG_EnableIOSwitchVDD 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:737:6:HAL_SYSCFG_DisableIOSwitchVDD 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:748:6:HAL_SYSCFG_CCMSRAM_WriteProtectionEnable 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:221:13:HAL_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:232:13:HAL_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:192:19:HAL_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:255:26:HAL_InitTick 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:148:19:HAL_Init 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:322:13:HAL_IncTick 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:333:17:HAL_GetTick 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:342:10:HAL_GetTickPrio 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:351:19:HAL_SetTickFreq 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:383:10:HAL_GetTickFreq 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:399:13:HAL_Delay 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:425:13:HAL_SuspendTick 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:441:13:HAL_ResumeTick 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:451:10:HAL_GetHalVersion 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:460:10:HAL_GetREVID 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:469:10:HAL_GetDEVID 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:498:6:HAL_DBGMCU_EnableDBGSleepMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:507:6:HAL_DBGMCU_DisableDBGSleepMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStopMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStopMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:534:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:543:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:576:6:HAL_SYSCFG_CCMSRAMErase 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:595:6:HAL_SYSCFG_EnableMemorySwappingBank 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:610:6:HAL_SYSCFG_DisableMemorySwappingBank 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:628:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:644:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:658:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:670:19:HAL_SYSCFG_EnableVREFBUF 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:696:6:HAL_SYSCFG_DisableVREFBUF 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:707:6:HAL_SYSCFG_EnableIOSwitchBooster 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:717:6:HAL_SYSCFG_DisableIOSwitchBooster 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:727:6:HAL_SYSCFG_EnableIOSwitchVDD 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:737:6:HAL_SYSCFG_DisableIOSwitchVDD 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c:748:6:HAL_SYSCFG_CCMSRAM_WriteProtectionEnable 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:913:13:HAL_ADC_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:395:19:HAL_ADC_Init 19 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:930:13:HAL_ADC_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1409:19:HAL_ADC_PollForConversion 19 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1592:19:HAL_ADC_PollForEvent 14 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2228:10:HAL_ADC_GetValue 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2249:19:HAL_ADC_StartSampling 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2271:19:HAL_ADC_StopSampling 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2660:13:HAL_ADC_ConvCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2675:13:HAL_ADC_ConvHalfCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3634:6:ADC_DMAHalfConvCplt 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2690:13:HAL_ADC_LevelOutOfWindowCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2712:13:HAL_ADC_ErrorCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2288:6:HAL_ADC_IRQHandler 44 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3556:6:ADC_DMAConvCplt 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3652:6:ADC_DMAError 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2758:19:HAL_ADC_ConfigChannel 47 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2991:19:HAL_ADC_AnalogWDGConfig 31 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3246:10:HAL_ADC_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3260:10:HAL_ADC_GetError 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3290:19:ADC_ConversionStop 22 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3422:19:ADC_Enable 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1220:19:HAL_ADC_Start 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1741:19:HAL_ADC_Start_IT 15 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2001:19:HAL_ADC_Start_DMA 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3494:19:ADC_Disable 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:714:19:HAL_ADC_DeInit 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1355:19:HAL_ADC_Stop 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1948:19:HAL_ADC_Stop_IT 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2143:19:HAL_ADC_Stop_DMA 6 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:913:13:HAL_ADC_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:395:19:HAL_ADC_Init 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:930:13:HAL_ADC_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1409:19:HAL_ADC_PollForConversion 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1592:19:HAL_ADC_PollForEvent 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2228:10:HAL_ADC_GetValue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2249:19:HAL_ADC_StartSampling 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2271:19:HAL_ADC_StopSampling 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2660:13:HAL_ADC_ConvCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2675:13:HAL_ADC_ConvHalfCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3634:6:ADC_DMAHalfConvCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2690:13:HAL_ADC_LevelOutOfWindowCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2712:13:HAL_ADC_ErrorCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2288:6:HAL_ADC_IRQHandler 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3556:6:ADC_DMAConvCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3652:6:ADC_DMAError 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2758:19:HAL_ADC_ConfigChannel 32 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2991:19:HAL_ADC_AnalogWDGConfig 12 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3246:10:HAL_ADC_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3260:10:HAL_ADC_GetError 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3290:19:ADC_ConversionStop 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3422:19:ADC_Enable 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1220:19:HAL_ADC_Start 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1741:19:HAL_ADC_Start_IT 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2001:19:HAL_ADC_Start_DMA 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:3494:19:ADC_Disable 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:714:19:HAL_ADC_DeInit 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1355:19:HAL_ADC_Stop 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:1948:19:HAL_ADC_Stop_IT 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c:2143:19:HAL_ADC_Stop_DMA 16 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:125:19:HAL_ADCEx_Calibration_Start 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:199:10:HAL_ADCEx_Calibration_GetValue 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:219:19:HAL_ADCEx_Calibration_SetValue 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:276:19:HAL_ADCEx_InjectedStart 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:425:19:HAL_ADCEx_InjectedStop 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:480:19:HAL_ADCEx_InjectedPollForConversion 16 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:621:19:HAL_ADCEx_InjectedStart_IT 14 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:794:19:HAL_ADCEx_InjectedStop_IT 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:861:19:HAL_ADCEx_MultiModeStart_DMA 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:980:19:HAL_ADCEx_MultiModeStop_DMA 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1104:10:HAL_ADCEx_MultiModeGetValue 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1151:10:HAL_ADCEx_InjectedGetValue 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1186:13:HAL_ADCEx_InjectedConvCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1205:13:HAL_ADCEx_InjectedQueueOverflowCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1220:13:HAL_ADCEx_LevelOutOfWindow2Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1235:13:HAL_ADCEx_LevelOutOfWindow3Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1251:13:HAL_ADCEx_EndOfSamplingCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1268:19:HAL_ADCEx_RegularStop 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1326:19:HAL_ADCEx_RegularStop_IT 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1386:19:HAL_ADCEx_RegularStop_DMA 7 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1473:19:HAL_ADCEx_RegularMultiModeStop_DMA 16 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1658:19:HAL_ADCEx_InjectedConfigChannel 60 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2105:19:HAL_ADCEx_MultiModeConfigChannel 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2222:19:HAL_ADCEx_EnableInjectedQueue 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2263:19:HAL_ADCEx_DisableInjectedQueue 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2300:19:HAL_ADCEx_DisableVoltageRegulator 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2337:19:HAL_ADCEx_EnterADCDeepPowerDownMode 2 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:125:19:HAL_ADCEx_Calibration_Start 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:199:10:HAL_ADCEx_Calibration_GetValue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:219:19:HAL_ADCEx_Calibration_SetValue 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:276:19:HAL_ADCEx_InjectedStart 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:425:19:HAL_ADCEx_InjectedStop 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:480:19:HAL_ADCEx_InjectedPollForConversion 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:621:19:HAL_ADCEx_InjectedStart_IT 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:794:19:HAL_ADCEx_InjectedStop_IT 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:861:19:HAL_ADCEx_MultiModeStart_DMA 136 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:980:19:HAL_ADCEx_MultiModeStop_DMA 128 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1104:10:HAL_ADCEx_MultiModeGetValue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1151:10:HAL_ADCEx_InjectedGetValue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1186:13:HAL_ADCEx_InjectedConvCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1205:13:HAL_ADCEx_InjectedQueueOverflowCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1220:13:HAL_ADCEx_LevelOutOfWindow2Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1235:13:HAL_ADCEx_LevelOutOfWindow3Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1251:13:HAL_ADCEx_EndOfSamplingCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1268:19:HAL_ADCEx_RegularStop 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1326:19:HAL_ADCEx_RegularStop_IT 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1386:19:HAL_ADCEx_RegularStop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1473:19:HAL_ADCEx_RegularMultiModeStop_DMA 128 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:1658:19:HAL_ADCEx_InjectedConfigChannel 32 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2105:19:HAL_ADCEx_MultiModeConfigChannel 136 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2222:19:HAL_ADCEx_EnableInjectedQueue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2263:19:HAL_ADCEx_DisableInjectedQueue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2300:19:HAL_ADCEx_DisableVoltageRegulator 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c:2337:19:HAL_ADCEx_EnterADCDeepPowerDownMode 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriorityGrouping 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:185:6:HAL_NVIC_SetPriority 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:207:6:HAL_NVIC_EnableIRQ 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:223:6:HAL_NVIC_DisableIRQ 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:236:6:HAL_NVIC_SystemReset 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:249:10:HAL_SYSTICK_Config 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:277:10:HAL_NVIC_GetPriorityGrouping 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:304:6:HAL_NVIC_GetPriority 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:319:6:HAL_NVIC_SetPendingIRQ 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:337:10:HAL_NVIC_GetPendingIRQ 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:353:6:HAL_NVIC_ClearPendingIRQ 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:370:10:HAL_NVIC_GetActive 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:384:6:HAL_SYSTICK_CLKSourceConfig 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:411:13:HAL_SYSTICK_Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:402:6:HAL_SYSTICK_IRQHandler 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:430:6:HAL_MPU_Enable 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:445:6:HAL_MPU_Disable 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:461:6:HAL_MPU_ConfigRegion 2 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:163:6:HAL_NVIC_SetPriorityGrouping 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:185:6:HAL_NVIC_SetPriority 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:207:6:HAL_NVIC_EnableIRQ 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:223:6:HAL_NVIC_DisableIRQ 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:236:6:HAL_NVIC_SystemReset 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:249:10:HAL_SYSTICK_Config 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:277:10:HAL_NVIC_GetPriorityGrouping 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:304:6:HAL_NVIC_GetPriority 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:319:6:HAL_NVIC_SetPendingIRQ 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:337:10:HAL_NVIC_GetPendingIRQ 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:353:6:HAL_NVIC_ClearPendingIRQ 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:370:10:HAL_NVIC_GetActive 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:384:6:HAL_SYSTICK_CLKSourceConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:411:13:HAL_SYSTICK_Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:402:6:HAL_SYSTICK_IRQHandler 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:430:6:HAL_MPU_Enable 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:445:6:HAL_MPU_Disable 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c:461:6:HAL_MPU_ConfigRegion 4 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:511:13:HAL_DAC_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:405:19:HAL_DAC_Init 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:527:13:HAL_DAC_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:466:19:HAL_DAC_DeInit 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:572:19:HAL_DAC_Start 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:632:19:HAL_DAC_Stop 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:669:19:HAL_DAC_Start_DMA 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:806:19:HAL_DAC_Stop_DMA 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:932:19:HAL_DAC_SetValue 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:970:13:HAL_DAC_ConvCpltCallbackCh1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1608:6:DAC_DMAConvCpltCh1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:986:13:HAL_DAC_ConvHalfCpltCallbackCh1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1627:6:DAC_DMAHalfConvCpltCh1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1002:13:HAL_DAC_ErrorCallbackCh1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1644:6:DAC_DMAErrorCh1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1018:13:HAL_DAC_DMAUnderrunCallbackCh1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:856:6:HAL_DAC_IRQHandler 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1060:10:HAL_DAC_GetValue 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1100:19:HAL_DAC_ConfigChannel 14 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1329:22:HAL_DAC_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1342:10:HAL_DAC_GetError 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:511:13:HAL_DAC_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:405:19:HAL_DAC_Init 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:527:13:HAL_DAC_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:466:19:HAL_DAC_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:572:19:HAL_DAC_Start 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:632:19:HAL_DAC_Stop 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:669:19:HAL_DAC_Start_DMA 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:806:19:HAL_DAC_Stop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:932:19:HAL_DAC_SetValue 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:970:13:HAL_DAC_ConvCpltCallbackCh1 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1608:6:DAC_DMAConvCpltCh1 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:986:13:HAL_DAC_ConvHalfCpltCallbackCh1 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1627:6:DAC_DMAHalfConvCpltCh1 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1002:13:HAL_DAC_ErrorCallbackCh1 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1644:6:DAC_DMAErrorCh1 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1018:13:HAL_DAC_DMAUnderrunCallbackCh1 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:856:6:HAL_DAC_IRQHandler 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1060:10:HAL_DAC_GetValue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1100:19:HAL_DAC_ConfigChannel 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1329:22:HAL_DAC_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c:1342:10:HAL_DAC_GetError 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:123:19:HAL_DACEx_DualStart 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:170:19:HAL_DACEx_DualStop 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:205:19:HAL_DACEx_DualStart_DMA 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:318:19:HAL_DACEx_DualStop_DMA 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:398:19:HAL_DACEx_TriangleWaveGenerate 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:451:19:HAL_DACEx_NoiseWaveGenerate 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:501:19:HAL_DACEx_SawtoothWaveGenerate 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:563:19:HAL_DACEx_SawtoothWaveDataReset 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:619:19:HAL_DACEx_SawtoothWaveDataStep 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:676:19:HAL_DACEx_DualSetValue 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:712:13:HAL_DACEx_ConvCpltCallbackCh2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:1032:6:DAC_DMAConvCpltCh2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:728:13:HAL_DACEx_ConvHalfCpltCallbackCh2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:1051:6:DAC_DMAHalfConvCpltCh2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:744:13:HAL_DACEx_ErrorCallbackCh2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:1068:6:DAC_DMAErrorCh2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:760:13:HAL_DACEx_DMAUnderrunCallbackCh2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:787:19:HAL_DACEx_SelfCalibrate 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:920:19:HAL_DACEx_SetUserTrimming 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:965:10:HAL_DACEx_GetTrimOffset 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:999:10:HAL_DACEx_DualGetValue 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:123:19:HAL_DACEx_DualStart 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:170:19:HAL_DACEx_DualStop 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:205:19:HAL_DACEx_DualStart_DMA 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:318:19:HAL_DACEx_DualStop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:398:19:HAL_DACEx_TriangleWaveGenerate 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:451:19:HAL_DACEx_NoiseWaveGenerate 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:501:19:HAL_DACEx_SawtoothWaveGenerate 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:563:19:HAL_DACEx_SawtoothWaveDataReset 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:619:19:HAL_DACEx_SawtoothWaveDataStep 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:676:19:HAL_DACEx_DualSetValue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:712:13:HAL_DACEx_ConvCpltCallbackCh2 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:1032:6:DAC_DMAConvCpltCh2 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:728:13:HAL_DACEx_ConvHalfCpltCallbackCh2 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:1051:6:DAC_DMAHalfConvCpltCh2 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:744:13:HAL_DACEx_ErrorCallbackCh2 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:1068:6:DAC_DMAErrorCh2 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:760:13:HAL_DACEx_DMAUnderrunCallbackCh2 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:787:19:HAL_DACEx_SelfCalibrate 56 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:920:19:HAL_DACEx_SetUserTrimming 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:965:10:HAL_DACEx_GetTrimOffset 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c:999:10:HAL_DACEx_DualGetValue 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:152:19:HAL_DMA_Init 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:263:19:HAL_DMA_DeInit 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:378:19:HAL_DMA_Start 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:421:19:HAL_DMA_Start_IT 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:491:19:HAL_DMA_Abort 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:544:19:HAL_DMA_Abort_IT 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:611:19:HAL_DMA_PollForTransfer 15 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:741:6:HAL_DMA_IRQHandler 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:835:19:HAL_DMA_RegisterCallback 7 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:886:19:HAL_DMA_UnRegisterCallback 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:964:22:HAL_DMA_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:976:10:HAL_DMA_GetError 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:152:19:HAL_DMA_Init 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:263:19:HAL_DMA_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:378:19:HAL_DMA_Start 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:421:19:HAL_DMA_Start_IT 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:491:19:HAL_DMA_Abort 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:544:19:HAL_DMA_Abort_IT 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:611:19:HAL_DMA_PollForTransfer 32 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:741:6:HAL_DMA_IRQHandler 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:835:19:HAL_DMA_RegisterCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:886:19:HAL_DMA_UnRegisterCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:964:22:HAL_DMA_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c:976:10:HAL_DMA_GetError 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:95:19:HAL_DMAEx_ConfigMuxSync 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:141:19:HAL_DMAEx_ConfigMuxRequestGenerator 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:209:19:HAL_DMAEx_DisableMuxRequestGenerator 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:237:6:HAL_DMAEx_MUX_IRQHandler 6 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:95:19:HAL_DMAEx_ConfigMuxSync 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:141:19:HAL_DMAEx_ConfigMuxRequestGenerator 4 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:209:19:HAL_DMAEx_DisableMuxRequestGenerator 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c:237:6:HAL_DMAEx_MUX_IRQHandler 16 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:144:19:HAL_EXTI_SetConfigLine 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:268:19:HAL_EXTI_GetConfigLine 7 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:364:19:HAL_EXTI_ClearConfigLine 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:432:19:HAL_EXTI_RegisterCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:463:19:HAL_EXTI_GetHandle 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:504:6:HAL_EXTI_IRQHandler 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:539:10:HAL_EXTI_GetPending 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:574:6:HAL_EXTI_ClearPending 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:603:6:HAL_EXTI_GenerateSWI 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:144:19:HAL_EXTI_SetConfigLine 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:268:19:HAL_EXTI_GetConfigLine 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:364:19:HAL_EXTI_ClearConfigLine 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:432:19:HAL_EXTI_RegisterCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:463:19:HAL_EXTI_GetHandle 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:504:6:HAL_EXTI_IRQHandler 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:539:10:HAL_EXTI_GetPending 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:574:6:HAL_EXTI_ClearPending 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c:603:6:HAL_EXTI_GenerateSWI 4 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:173:19:HAL_FLASH_Program 17 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:241:19:HAL_FLASH_Program_IT 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:441:13:HAL_FLASH_EndOfOperationCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:459:13:HAL_FLASH_OperationErrorCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:301:6:HAL_FLASH_IRQHandler 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:492:19:HAL_FLASH_Unlock 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:516:19:HAL_FLASH_Lock 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:536:19:HAL_FLASH_OB_Unlock 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:560:19:HAL_FLASH_OB_Lock 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:580:19:HAL_FLASH_OB_Launch 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:628:10:HAL_FLASH_GetError 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:652:19:FLASH_WaitForLastOperation 5 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:173:19:HAL_FLASH_Program 32 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:241:19:HAL_FLASH_Program_IT 32 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:441:13:HAL_FLASH_EndOfOperationCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:459:13:HAL_FLASH_OperationErrorCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:301:6:HAL_FLASH_IRQHandler 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:492:19:HAL_FLASH_Unlock 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:516:19:HAL_FLASH_Lock 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:536:19:HAL_FLASH_OB_Unlock 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:560:19:HAL_FLASH_OB_Lock 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:580:19:HAL_FLASH_OB_Launch 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:628:10:HAL_FLASH_GetError 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c:652:19:FLASH_WaitForLastOperation 16 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:138:19:HAL_FLASHEx_Erase 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:237:19:HAL_FLASHEx_Erase_IT 7 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:310:19:HAL_FLASHEx_OBProgram 39 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:399:6:HAL_FLASHEx_OBGetConfig 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:459:19:HAL_FLASHEx_EnableSecMemProtection 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:493:6:HAL_FLASHEx_EnableDebugger 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:505:6:HAL_FLASHEx_DisableDebugger 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:578:6:FLASH_PageErase 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:613:6:FLASH_FlushCaches 3 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:138:19:HAL_FLASHEx_Erase 32 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:237:19:HAL_FLASHEx_Erase_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:310:19:HAL_FLASHEx_OBProgram 32 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:399:6:HAL_FLASHEx_OBGetConfig 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:459:19:HAL_FLASHEx_EnableSecMemProtection 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:493:6:HAL_FLASHEx_EnableDebugger 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:505:6:HAL_FLASHEx_DisableDebugger 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:578:6:FLASH_PageErase 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c:613:6:FLASH_FlushCaches 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c:92:30:HAL_FLASHEx_EnableRunPowerDown 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c:106:30:HAL_FLASHEx_DisableRunPowerDown 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c:92:30:HAL_FLASHEx_EnableRunPowerDown 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c:106:30:HAL_FLASHEx_DisableRunPowerDown 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:162:6:HAL_GPIO_Init 18 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:292:6:HAL_GPIO_DeInit 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:373:15:HAL_GPIO_ReadPin 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:407:6:HAL_GPIO_WritePin 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:430:6:HAL_GPIO_TogglePin 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:455:19:HAL_GPIO_LockPin 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:505:13:HAL_GPIO_EXTI_Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:490:6:HAL_GPIO_EXTI_IRQHandler 2 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:162:6:HAL_GPIO_Init 56 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:292:6:HAL_GPIO_DeInit 36 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:373:15:HAL_GPIO_ReadPin 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:407:6:HAL_GPIO_WritePin 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:430:6:HAL_GPIO_TogglePin 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:455:19:HAL_GPIO_LockPin 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:505:13:HAL_GPIO_EXTI_Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c:490:6:HAL_GPIO_EXTI_IRQHandler 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:86:6:HAL_PWR_DeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:104:6:HAL_PWR_EnableBkUpAccess 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:114:6:HAL_PWR_DisableBkUpAccess 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:308:19:HAL_PWR_ConfigPVD 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:354:6:HAL_PWR_EnablePVD 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:363:6:HAL_PWR_DisablePVD 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:388:6:HAL_PWR_EnableWakeUpPin 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:409:6:HAL_PWR_DisableWakeUpPin 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:441:6:HAL_PWR_EnterSLEEPMode 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:516:6:HAL_PWR_EnterSTOPMode 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:549:6:HAL_PWR_EnterSTANDBYMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:575:6:HAL_PWR_EnableSleepOnExit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:588:6:HAL_PWR_DisableSleepOnExit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:602:6:HAL_PWR_EnableSEVOnPend 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:615:6:HAL_PWR_DisableSEVOnPend 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:629:13:HAL_PWR_PVDCallback 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:86:6:HAL_PWR_DeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:104:6:HAL_PWR_EnableBkUpAccess 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:114:6:HAL_PWR_DisableBkUpAccess 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:308:19:HAL_PWR_ConfigPVD 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:354:6:HAL_PWR_EnablePVD 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:363:6:HAL_PWR_DisablePVD 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:388:6:HAL_PWR_EnableWakeUpPin 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:409:6:HAL_PWR_DisableWakeUpPin 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:441:6:HAL_PWR_EnterSLEEPMode 8 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:516:6:HAL_PWR_EnterSTOPMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:549:6:HAL_PWR_EnterSTANDBYMode 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:575:6:HAL_PWR_EnableSleepOnExit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:588:6:HAL_PWR_DisableSleepOnExit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:602:6:HAL_PWR_EnableSEVOnPend 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:615:6:HAL_PWR_DisableSEVOnPend 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c:629:13:HAL_PWR_PVDCallback 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:109:10:HAL_PWREx_GetVoltageRange 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:153:19:HAL_PWREx_ControlVoltageScaling 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:238:6:HAL_PWREx_EnableBatteryCharging 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:254:6:HAL_PWREx_DisableBatteryCharging 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:264:6:HAL_PWREx_EnableInternalWakeUpLine 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:274:6:HAL_PWREx_DisableInternalWakeUpLine 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:302:19:HAL_PWREx_EnableGPIOPullUp 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:363:19:HAL_PWREx_DisableGPIOPullUp 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:424:19:HAL_PWREx_EnableGPIOPullDown 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:485:19:HAL_PWREx_DisableGPIOPullDown 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:535:6:HAL_PWREx_EnablePullUpPullDownConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:547:6:HAL_PWREx_DisablePullUpPullDownConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:560:6:HAL_PWREx_EnableSRAM2ContentRetention 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:572:6:HAL_PWREx_DisableSRAM2ContentRetention 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:585:6:HAL_PWREx_EnablePVM1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:594:6:HAL_PWREx_DisablePVM1 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:606:6:HAL_PWREx_EnablePVM2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:615:6:HAL_PWREx_DisablePVM2 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:626:6:HAL_PWREx_EnablePVM3 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:635:6:HAL_PWREx_DisablePVM3 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:645:6:HAL_PWREx_EnablePVM4 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:654:6:HAL_PWREx_DisablePVM4 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:674:19:HAL_PWREx_ConfigPVM 22 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:835:6:HAL_PWREx_EnableLowPowerRunMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:850:19:HAL_PWREx_DisableLowPowerRunMode 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:894:6:HAL_PWREx_EnterSTOP0Mode 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:945:6:HAL_PWREx_EnterSTOP1Mode 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:986:6:HAL_PWREx_EnterSHUTDOWNMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1067:13:HAL_PWREx_PVM1Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1080:13:HAL_PWREx_PVM2Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1092:13:HAL_PWREx_PVM3Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1103:13:HAL_PWREx_PVM4Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1011:6:HAL_PWREx_PVD_PVM_IRQHandler 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1115:6:HAL_PWREx_EnableUCPDStandbyMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1127:6:HAL_PWREx_DisableUCPDStandbyMode 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1141:6:HAL_PWREx_EnableUCPDDeadBattery 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1157:6:HAL_PWREx_DisableUCPDDeadBattery 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:109:10:HAL_PWREx_GetVoltageRange 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:153:19:HAL_PWREx_ControlVoltageScaling 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:238:6:HAL_PWREx_EnableBatteryCharging 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:254:6:HAL_PWREx_DisableBatteryCharging 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:264:6:HAL_PWREx_EnableInternalWakeUpLine 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:274:6:HAL_PWREx_DisableInternalWakeUpLine 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:302:19:HAL_PWREx_EnableGPIOPullUp 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:363:19:HAL_PWREx_DisableGPIOPullUp 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:424:19:HAL_PWREx_EnableGPIOPullDown 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:485:19:HAL_PWREx_DisableGPIOPullDown 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:535:6:HAL_PWREx_EnablePullUpPullDownConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:547:6:HAL_PWREx_DisablePullUpPullDownConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:560:6:HAL_PWREx_EnableSRAM2ContentRetention 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:572:6:HAL_PWREx_DisableSRAM2ContentRetention 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:585:6:HAL_PWREx_EnablePVM1 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:594:6:HAL_PWREx_DisablePVM1 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:606:6:HAL_PWREx_EnablePVM2 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:615:6:HAL_PWREx_DisablePVM2 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:626:6:HAL_PWREx_EnablePVM3 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:635:6:HAL_PWREx_DisablePVM3 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:645:6:HAL_PWREx_EnablePVM4 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:654:6:HAL_PWREx_DisablePVM4 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:674:19:HAL_PWREx_ConfigPVM 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:835:6:HAL_PWREx_EnableLowPowerRunMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:850:19:HAL_PWREx_DisableLowPowerRunMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:894:6:HAL_PWREx_EnterSTOP0Mode 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:945:6:HAL_PWREx_EnterSTOP1Mode 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:986:6:HAL_PWREx_EnterSHUTDOWNMode 0 static,ignoring_inline_asm ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1067:13:HAL_PWREx_PVM1Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1080:13:HAL_PWREx_PVM2Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1092:13:HAL_PWREx_PVM3Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1103:13:HAL_PWREx_PVM4Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1011:6:HAL_PWREx_PVD_PVM_IRQHandler 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1115:6:HAL_PWREx_EnableUCPDStandbyMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1127:6:HAL_PWREx_DisableUCPDStandbyMode 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1141:6:HAL_PWREx_EnableUCPDDeadBattery 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c:1157:6:HAL_PWREx_DisableUCPDDeadBattery 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:219:19:HAL_RCC_DeInit 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:312:19:HAL_RCC_OscConfig 67 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:995:6:HAL_RCC_MCOConfig 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1064:10:HAL_RCC_GetSysClockFreq 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:767:19:HAL_RCC_ClockConfig 28 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1119:10:HAL_RCC_GetHCLKFreq 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1130:10:HAL_RCC_GetPCLK1Freq 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1142:10:HAL_RCC_GetPCLK2Freq 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1155:6:HAL_RCC_GetOscConfig 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1249:6:HAL_RCC_GetClockConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1284:6:HAL_RCC_EnableCSS 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1298:6:HAL_RCC_EnableLSECSS 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1309:6:HAL_RCC_DisableLSECSS 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1336:13:HAL_RCC_CSSCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1319:6:HAL_RCC_NMI_IRQHandler 2 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:219:19:HAL_RCC_DeInit 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:312:19:HAL_RCC_OscConfig 32 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:995:6:HAL_RCC_MCOConfig 48 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1064:10:HAL_RCC_GetSysClockFreq 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:767:19:HAL_RCC_ClockConfig 32 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1119:10:HAL_RCC_GetHCLKFreq 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1130:10:HAL_RCC_GetPCLK1Freq 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1142:10:HAL_RCC_GetPCLK2Freq 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1155:6:HAL_RCC_GetOscConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1249:6:HAL_RCC_GetClockConfig 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1284:6:HAL_RCC_EnableCSS 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1298:6:HAL_RCC_EnableLSECSS 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1309:6:HAL_RCC_DisableLSECSS 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1336:13:HAL_RCC_CSSCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c:1319:6:HAL_RCC_NMI_IRQHandler 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:123:19:HAL_RCCEx_PeriphCLKConfig 32 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:485:6:HAL_RCCEx_GetPeriphCLKConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:648:10:HAL_RCCEx_GetPeriphCLKFreq 90 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1286:6:HAL_RCCEx_EnableLSECSS 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1296:6:HAL_RCCEx_DisableLSECSS 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1309:6:HAL_RCCEx_EnableLSECSS_IT 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1343:13:HAL_RCCEx_LSECSS_Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1326:6:HAL_RCCEx_LSECSS_IRQHandler 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1358:6:HAL_RCCEx_EnableLSCO 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1405:6:HAL_RCCEx_DisableLSCO 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1513:6:HAL_RCCEx_CRSConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1555:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1565:6:HAL_RCCEx_CRSGetSynchronizationInfo 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1598:10:HAL_RCCEx_CRSWaitSynchronization 26 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1746:13:HAL_RCCEx_CRS_SyncOkCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1757:13:HAL_RCCEx_CRS_SyncWarnCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1768:13:HAL_RCCEx_CRS_ExpectedSyncCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1784:13:HAL_RCCEx_CRS_ErrorCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1681:6:HAL_RCCEx_CRS_IRQHandler 11 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:123:19:HAL_RCCEx_PeriphCLKConfig 32 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:485:6:HAL_RCCEx_GetPeriphCLKConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:648:10:HAL_RCCEx_GetPeriphCLKFreq 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1286:6:HAL_RCCEx_EnableLSECSS 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1296:6:HAL_RCCEx_DisableLSECSS 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1309:6:HAL_RCCEx_EnableLSECSS_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1343:13:HAL_RCCEx_LSECSS_Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1326:6:HAL_RCCEx_LSECSS_IRQHandler 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1358:6:HAL_RCCEx_EnableLSCO 48 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1405:6:HAL_RCCEx_DisableLSCO 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1513:6:HAL_RCCEx_CRSConfig 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1555:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1565:6:HAL_RCCEx_CRSGetSynchronizationInfo 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1598:10:HAL_RCCEx_CRSWaitSynchronization 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1746:13:HAL_RCCEx_CRS_SyncOkCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1757:13:HAL_RCCEx_CRS_SyncWarnCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1768:13:HAL_RCCEx_CRS_ExpectedSyncCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1784:13:HAL_RCCEx_CRS_ErrorCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c:1681:6:HAL_RCCEx_CRS_IRQHandler 8 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7154:13:TIM_OC1_SetConfig 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7305:13:TIM_OC3_SetConfig 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7379:13:TIM_OC4_SetConfig 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:383:13:HAL_TIM_Base_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:281:19:HAL_TIM_Base_Init 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:398:13:HAL_TIM_Base_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:340:19:HAL_TIM_Base_DeInit 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:414:19:HAL_TIM_Base_Start 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:453:19:HAL_TIM_Base_Stop 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:473:19:HAL_TIM_Base_Start_IT 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:515:19:HAL_TIM_Base_Stop_IT 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:540:19:HAL_TIM_Base_Start_DMA 14 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:609:19:HAL_TIM_Base_Stop_DMA 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:766:13:HAL_TIM_OC_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:664:19:HAL_TIM_OC_Init 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:781:13:HAL_TIM_OC_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:723:19:HAL_TIM_OC_DeInit 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:804:19:HAL_TIM_OC_Start 28 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:860:19:HAL_TIM_OC_Stop 15 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:895:19:HAL_TIM_OC_Start_IT 31 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:988:19:HAL_TIM_OC_Stop_IT 17 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1065:19:HAL_TIM_OC_Start_DMA 42 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1228:19:HAL_TIM_OC_Stop_DMA 17 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1331:19:HAL_TIM_PWM_Init 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1448:13:HAL_TIM_PWM_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1390:19:HAL_TIM_PWM_DeInit 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1471:19:HAL_TIM_PWM_Start 28 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1527:19:HAL_TIM_PWM_Stop 15 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1562:19:HAL_TIM_PWM_Start_IT 31 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1655:19:HAL_TIM_PWM_Stop_IT 17 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1732:19:HAL_TIM_PWM_Start_DMA 42 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1894:19:HAL_TIM_PWM_Stop_DMA 17 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2099:13:HAL_TIM_IC_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1997:19:HAL_TIM_IC_Init 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2114:13:HAL_TIM_IC_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2056:19:HAL_TIM_IC_DeInit 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2135:19:HAL_TIM_IC_Start 23 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2187:19:HAL_TIM_IC_Stop 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2217:19:HAL_TIM_IC_Start_IT 24 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2309:19:HAL_TIM_IC_Stop_IT 15 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2381:19:HAL_TIM_IC_Start_DMA 34 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2540:19:HAL_TIM_IC_Stop_DMA 15 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2758:13:HAL_TIM_OnePulse_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2645:19:HAL_TIM_OnePulse_Init 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2773:13:HAL_TIM_OnePulse_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2713:19:HAL_TIM_OnePulse_DeInit 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2793:19:HAL_TIM_OnePulse_Start 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2850:19:HAL_TIM_OnePulse_Stop 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2893:19:HAL_TIM_OnePulse_Start_IT 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2956:19:HAL_TIM_OnePulse_Stop_IT 10 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3194:13:HAL_TIM_Encoder_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3035:19:HAL_TIM_Encoder_Init 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3209:13:HAL_TIM_Encoder_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3149:19:HAL_TIM_Encoder_DeInit 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3229:19:HAL_TIM_Encoder_Start 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3323:19:HAL_TIM_Encoder_Stop 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3383:19:HAL_TIM_Encoder_Start_IT 11 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3483:19:HAL_TIM_Encoder_Stop_IT 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3548:19:HAL_TIM_Encoder_Start_DMA 30 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3761:19:HAL_TIM_Encoder_Stop_DMA 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4219:19:HAL_TIM_IC_ConfigChannel 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4625:19:HAL_TIM_DMABurst_WriteStart 20 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4686:19:HAL_TIM_DMABurst_MultiWriteStart 20 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4870:19:HAL_TIM_DMABurst_WriteStop 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4980:19:HAL_TIM_DMABurst_ReadStart 20 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5040:19:HAL_TIM_DMABurst_MultiReadStart 20 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5224:19:HAL_TIM_DMABurst_ReadStop 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5308:19:HAL_TIM_GenerateEvent 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5347:19:HAL_TIM_ConfigOCrefClear 42 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5549:19:HAL_TIM_ConfigClockSource 21 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5717:19:HAL_TIM_ConfigTI1Input 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5749:19:HAL_TIM_SlaveConfigSynchro 21 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5789:19:HAL_TIM_SlaveConfigSynchro_IT 21 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5832:10:HAL_TIM_ReadCapturedValue 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5920:13:HAL_TIM_PeriodElapsedCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7031:13:TIM_DMAPeriodElapsedCplt 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5935:13:HAL_TIM_PeriodElapsedHalfCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7052:13:TIM_DMAPeriodElapsedHalfCplt 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5950:13:HAL_TIM_OC_DelayElapsedCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5965:13:HAL_TIM_IC_CaptureCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6929:6:TIM_DMACaptureCplt 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5980:13:HAL_TIM_IC_CaptureHalfCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6992:6:TIM_DMACaptureHalfCplt 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5995:13:HAL_TIM_PWM_PulseFinishedCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6831:13:TIM_DMADelayPulseCplt 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6010:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6890:6:TIM_DMADelayPulseHalfCplt 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6025:13:HAL_TIM_TriggerCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3838:6:HAL_TIM_IRQHandler 31 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7068:13:TIM_DMATriggerCplt 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6040:13:HAL_TIM_TriggerHalfCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7089:13:TIM_DMATriggerHalfCplt 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6055:13:HAL_TIM_ErrorCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6788:6:TIM_DMAError 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6668:22:HAL_TIM_Base_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6678:22:HAL_TIM_OC_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6688:22:HAL_TIM_PWM_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6698:22:HAL_TIM_IC_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6708:22:HAL_TIM_OnePulse_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6718:22:HAL_TIM_Encoder_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6728:23:HAL_TIM_GetActiveChannel 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6746:29:HAL_TIM_GetChannelState 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6763:30:HAL_TIM_DMABurstState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7106:6:TIM_Base_SetConfig 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7229:6:TIM_OC2_SetConfig 6 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4120:19:HAL_TIM_OC_ConfigChannel 18 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4320:19:HAL_TIM_PWM_ConfigChannel 18 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4468:19:HAL_TIM_OnePulse_ConfigChannel 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7712:6:TIM_TI1_SetConfig 7 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:8017:6:TIM_ETR_SetConfig 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:8049:6:TIM_CCxChannelCmd 1 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7154:13:TIM_OC1_SetConfig 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7305:13:TIM_OC3_SetConfig 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7379:13:TIM_OC4_SetConfig 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:383:13:HAL_TIM_Base_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:281:19:HAL_TIM_Base_Init 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:398:13:HAL_TIM_Base_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:340:19:HAL_TIM_Base_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:414:19:HAL_TIM_Base_Start 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:453:19:HAL_TIM_Base_Stop 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:473:19:HAL_TIM_Base_Start_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:515:19:HAL_TIM_Base_Stop_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:540:19:HAL_TIM_Base_Start_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:609:19:HAL_TIM_Base_Stop_DMA 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:766:13:HAL_TIM_OC_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:664:19:HAL_TIM_OC_Init 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:781:13:HAL_TIM_OC_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:723:19:HAL_TIM_OC_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:804:19:HAL_TIM_OC_Start 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:860:19:HAL_TIM_OC_Stop 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:895:19:HAL_TIM_OC_Start_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:988:19:HAL_TIM_OC_Stop_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1065:19:HAL_TIM_OC_Start_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1228:19:HAL_TIM_OC_Stop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1331:19:HAL_TIM_PWM_Init 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1448:13:HAL_TIM_PWM_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1390:19:HAL_TIM_PWM_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1471:19:HAL_TIM_PWM_Start 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1527:19:HAL_TIM_PWM_Stop 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1562:19:HAL_TIM_PWM_Start_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1655:19:HAL_TIM_PWM_Stop_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1732:19:HAL_TIM_PWM_Start_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1894:19:HAL_TIM_PWM_Stop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2099:13:HAL_TIM_IC_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:1997:19:HAL_TIM_IC_Init 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2114:13:HAL_TIM_IC_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2056:19:HAL_TIM_IC_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2135:19:HAL_TIM_IC_Start 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2187:19:HAL_TIM_IC_Stop 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2217:19:HAL_TIM_IC_Start_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2309:19:HAL_TIM_IC_Stop_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2381:19:HAL_TIM_IC_Start_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2540:19:HAL_TIM_IC_Stop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2758:13:HAL_TIM_OnePulse_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2645:19:HAL_TIM_OnePulse_Init 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2773:13:HAL_TIM_OnePulse_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2713:19:HAL_TIM_OnePulse_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2793:19:HAL_TIM_OnePulse_Start 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2850:19:HAL_TIM_OnePulse_Stop 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2893:19:HAL_TIM_OnePulse_Start_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:2956:19:HAL_TIM_OnePulse_Stop_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3194:13:HAL_TIM_Encoder_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3035:19:HAL_TIM_Encoder_Init 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3209:13:HAL_TIM_Encoder_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3149:19:HAL_TIM_Encoder_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3229:19:HAL_TIM_Encoder_Start 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3323:19:HAL_TIM_Encoder_Stop 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3383:19:HAL_TIM_Encoder_Start_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3483:19:HAL_TIM_Encoder_Stop_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3548:19:HAL_TIM_Encoder_Start_DMA 32 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3761:19:HAL_TIM_Encoder_Stop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4219:19:HAL_TIM_IC_ConfigChannel 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4625:19:HAL_TIM_DMABurst_WriteStart 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4686:19:HAL_TIM_DMABurst_MultiWriteStart 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4870:19:HAL_TIM_DMABurst_WriteStop 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4980:19:HAL_TIM_DMABurst_ReadStart 24 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5040:19:HAL_TIM_DMABurst_MultiReadStart 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5224:19:HAL_TIM_DMABurst_ReadStop 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5308:19:HAL_TIM_GenerateEvent 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5347:19:HAL_TIM_ConfigOCrefClear 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5549:19:HAL_TIM_ConfigClockSource 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5717:19:HAL_TIM_ConfigTI1Input 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5749:19:HAL_TIM_SlaveConfigSynchro 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5789:19:HAL_TIM_SlaveConfigSynchro_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5832:10:HAL_TIM_ReadCapturedValue 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5920:13:HAL_TIM_PeriodElapsedCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7031:13:TIM_DMAPeriodElapsedCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5935:13:HAL_TIM_PeriodElapsedHalfCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7052:13:TIM_DMAPeriodElapsedHalfCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5950:13:HAL_TIM_OC_DelayElapsedCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5965:13:HAL_TIM_IC_CaptureCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6929:6:TIM_DMACaptureCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5980:13:HAL_TIM_IC_CaptureHalfCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6992:6:TIM_DMACaptureHalfCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:5995:13:HAL_TIM_PWM_PulseFinishedCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6831:13:TIM_DMADelayPulseCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6010:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6890:6:TIM_DMADelayPulseHalfCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6025:13:HAL_TIM_TriggerCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:3838:6:HAL_TIM_IRQHandler 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7068:13:TIM_DMATriggerCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6040:13:HAL_TIM_TriggerHalfCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7089:13:TIM_DMATriggerHalfCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6055:13:HAL_TIM_ErrorCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6788:6:TIM_DMAError 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6668:22:HAL_TIM_Base_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6678:22:HAL_TIM_OC_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6688:22:HAL_TIM_PWM_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6698:22:HAL_TIM_IC_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6708:22:HAL_TIM_OnePulse_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6718:22:HAL_TIM_Encoder_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6728:23:HAL_TIM_GetActiveChannel 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6746:29:HAL_TIM_GetChannelState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:6763:30:HAL_TIM_DMABurstState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7106:6:TIM_Base_SetConfig 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7229:6:TIM_OC2_SetConfig 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4120:19:HAL_TIM_OC_ConfigChannel 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4320:19:HAL_TIM_PWM_ConfigChannel 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:4468:19:HAL_TIM_OnePulse_ConfigChannel 56 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:7712:6:TIM_TI1_SetConfig 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:8017:6:TIM_ETR_SetConfig 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c:8049:6:TIM_CCxChannelCmd 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.cyclo ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3632:13:TIM_DMAErrorCCxN 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3573:13:TIM_DMADelayPulseNCplt 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:303:13:HAL_TIMEx_HallSensor_MspInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:157:19:HAL_TIMEx_HallSensor_Init 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:318:13:HAL_TIMEx_HallSensor_MspDeInit 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:258:19:HAL_TIMEx_HallSensor_DeInit 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:333:19:HAL_TIMEx_HallSensor_Start 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:387:19:HAL_TIMEx_HallSensor_Stop 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:415:19:HAL_TIMEx_HallSensor_Start_IT 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:472:19:HAL_TIMEx_HallSensor_Stop_IT 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:505:19:HAL_TIMEx_HallSensor_Start_DMA 16 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:581:19:HAL_TIMEx_HallSensor_Stop_DMA 3 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:644:19:HAL_TIMEx_OCN_Start 16 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:696:19:HAL_TIMEx_OCN_Stop 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:729:19:HAL_TIMEx_OCN_Start_IT 21 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:824:19:HAL_TIMEx_OCN_Stop_IT 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:907:19:HAL_TIMEx_OCN_Start_DMA 36 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1066:19:HAL_TIMEx_OCN_Stop_DMA 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1176:19:HAL_TIMEx_PWMN_Start 16 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1227:19:HAL_TIMEx_PWMN_Stop 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1260:19:HAL_TIMEx_PWMN_Start_IT 21 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Stop_IT 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1437:19:HAL_TIMEx_PWMN_Start_DMA 36 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1596:19:HAL_TIMEx_PWMN_Stop_DMA 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1695:19:HAL_TIMEx_OnePulseN_Start 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1744:19:HAL_TIMEx_OnePulseN_Stop 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1783:19:HAL_TIMEx_OnePulseN_Start_IT 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1838:19:HAL_TIMEx_OnePulseN_Stop_IT 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1932:19:HAL_TIMEx_ConfigCommutEvent 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2023:19:HAL_TIMEx_ConfigCommutEvent_IT 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2115:19:HAL_TIMEx_ConfigCommutEvent_DMA 12 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2188:19:HAL_TIMEx_MasterConfigSynchronization 9 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2261:19:HAL_TIMEx_ConfigBreakDeadTime 4 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2343:19:HAL_TIMEx_ConfigBreakInput 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2607:19:HAL_TIMEx_RemapConfig 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2781:20:HAL_TIMEx_TISelection 8 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2836:19:HAL_TIMEx_GroupChannel5 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2874:19:HAL_TIMEx_DisarmBreakInput 5 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2929:19:HAL_TIMEx_ReArmBreakInput 13 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3012:19:HAL_TIMEx_DitheringEnable 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3036:19:HAL_TIMEx_DitheringDisable 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3054:19:HAL_TIMEx_OC_ConfigPulseOnCompare 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3099:19:HAL_TIMEx_ConfigSlaveModePreload 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3114:19:HAL_TIMEx_EnableSlaveModePreload 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3128:19:HAL_TIMEx_DisableSlaveModePreload 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3142:19:HAL_TIMEx_EnableDeadTimePreload 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3156:19:HAL_TIMEx_DisableDeadTimePreload 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3172:19:HAL_TIMEx_ConfigDeadTime 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3189:19:HAL_TIMEx_ConfigAsymmetricalDeadTime 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3204:19:HAL_TIMEx_EnableAsymmetricalDeadTime 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3218:19:HAL_TIMEx_DisableAsymmetricalDeadTime 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3236:19:HAL_TIMEx_ConfigEncoderIndex 2 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3275:19:HAL_TIMEx_EnableEncoderIndex 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3289:19:HAL_TIMEx_DisableEncoderIndex 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3303:19:HAL_TIMEx_EnableEncoderFirstIndex 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3317:19:HAL_TIMEx_DisableEncoderFirstIndex 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3351:13:HAL_TIMEx_CommutCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3534:6:TIMEx_DMACommutationCplt 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3365:13:HAL_TIMEx_CommutHalfCpltCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3553:6:TIMEx_DMACommutationHalfCplt 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3380:13:HAL_TIMEx_BreakCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3395:13:HAL_TIMEx_Break2Callback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3410:13:HAL_TIMEx_EncoderIndexCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3425:13:HAL_TIMEx_DirectionChangeCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3440:13:HAL_TIMEx_IndexErrorCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3455:13:HAL_TIMEx_TransitionErrorCallback 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3489:22:HAL_TIMEx_HallSensor_GetState 1 ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3505:29:HAL_TIMEx_GetChannelNState 4 ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h \ ../Core/Inc/stm32g4xx_hal_conf.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h \ ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h \ ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h: ../Core/Inc/stm32g4xx_hal_conf.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h: ../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: ../Drivers/CMSIS/Include/cmsis_compiler.h: ../Drivers/CMSIS/Include/cmsis_gcc.h: ../Drivers/CMSIS/Include/mpu_armv7.h: ../Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h: ../Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h: ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.su ================================================ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3632:13:TIM_DMAErrorCCxN 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3573:13:TIM_DMADelayPulseNCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:303:13:HAL_TIMEx_HallSensor_MspInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:157:19:HAL_TIMEx_HallSensor_Init 48 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:318:13:HAL_TIMEx_HallSensor_MspDeInit 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:258:19:HAL_TIMEx_HallSensor_DeInit 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:333:19:HAL_TIMEx_HallSensor_Start 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:387:19:HAL_TIMEx_HallSensor_Stop 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:415:19:HAL_TIMEx_HallSensor_Start_IT 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:472:19:HAL_TIMEx_HallSensor_Stop_IT 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:505:19:HAL_TIMEx_HallSensor_Start_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:581:19:HAL_TIMEx_HallSensor_Stop_DMA 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:644:19:HAL_TIMEx_OCN_Start 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:696:19:HAL_TIMEx_OCN_Stop 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:729:19:HAL_TIMEx_OCN_Start_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:824:19:HAL_TIMEx_OCN_Stop_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:907:19:HAL_TIMEx_OCN_Start_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1066:19:HAL_TIMEx_OCN_Stop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1176:19:HAL_TIMEx_PWMN_Start 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1227:19:HAL_TIMEx_PWMN_Stop 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1260:19:HAL_TIMEx_PWMN_Start_IT 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Stop_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1437:19:HAL_TIMEx_PWMN_Start_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1596:19:HAL_TIMEx_PWMN_Stop_DMA 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1695:19:HAL_TIMEx_OnePulseN_Start 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1744:19:HAL_TIMEx_OnePulseN_Stop 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1783:19:HAL_TIMEx_OnePulseN_Start_IT 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1838:19:HAL_TIMEx_OnePulseN_Stop_IT 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:1932:19:HAL_TIMEx_ConfigCommutEvent 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2023:19:HAL_TIMEx_ConfigCommutEvent_IT 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2115:19:HAL_TIMEx_ConfigCommutEvent_DMA 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2188:19:HAL_TIMEx_MasterConfigSynchronization 12 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2261:19:HAL_TIMEx_ConfigBreakDeadTime 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2343:19:HAL_TIMEx_ConfigBreakInput 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2607:19:HAL_TIMEx_RemapConfig 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2781:20:HAL_TIMEx_TISelection 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2836:19:HAL_TIMEx_GroupChannel5 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2874:19:HAL_TIMEx_DisarmBreakInput 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:2929:19:HAL_TIMEx_ReArmBreakInput 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3012:19:HAL_TIMEx_DitheringEnable 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3036:19:HAL_TIMEx_DitheringDisable 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3054:19:HAL_TIMEx_OC_ConfigPulseOnCompare 4 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3099:19:HAL_TIMEx_ConfigSlaveModePreload 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3114:19:HAL_TIMEx_EnableSlaveModePreload 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3128:19:HAL_TIMEx_DisableSlaveModePreload 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3142:19:HAL_TIMEx_EnableDeadTimePreload 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3156:19:HAL_TIMEx_DisableDeadTimePreload 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3172:19:HAL_TIMEx_ConfigDeadTime 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3189:19:HAL_TIMEx_ConfigAsymmetricalDeadTime 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3204:19:HAL_TIMEx_EnableAsymmetricalDeadTime 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3218:19:HAL_TIMEx_DisableAsymmetricalDeadTime 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3236:19:HAL_TIMEx_ConfigEncoderIndex 16 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3275:19:HAL_TIMEx_EnableEncoderIndex 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3289:19:HAL_TIMEx_DisableEncoderIndex 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3303:19:HAL_TIMEx_EnableEncoderFirstIndex 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3317:19:HAL_TIMEx_DisableEncoderFirstIndex 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3351:13:HAL_TIMEx_CommutCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3534:6:TIMEx_DMACommutationCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3365:13:HAL_TIMEx_CommutHalfCpltCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3553:6:TIMEx_DMACommutationHalfCplt 8 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3380:13:HAL_TIMEx_BreakCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3395:13:HAL_TIMEx_Break2Callback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3410:13:HAL_TIMEx_EncoderIndexCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3425:13:HAL_TIMEx_DirectionChangeCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3440:13:HAL_TIMEx_IndexErrorCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3455:13:HAL_TIMEx_TransitionErrorCallback 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3489:22:HAL_TIMEx_HallSensor_GetState 0 static ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c:3505:29:HAL_TIMEx_GetChannelNState 0 static ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.cyclo ================================================ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d ================================================ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o: \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.su ================================================ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (11.3.rel1) ################################################################################ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \ ../Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c C_DEPS += \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d OBJS += \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o \ ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o # Each subdirectory must supply rules for building sources it contributes Drivers/STM32G4xx_HAL_Driver/Src/%.o Drivers/STM32G4xx_HAL_Driver/Src/%.su Drivers/STM32G4xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32G4xx_HAL_Driver/Src/%.c Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32G431xx -c -I../Core/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc -I../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32G4xx/Include -I../Drivers/CMSIS/Include -Ofast -ffunction-sections -fdata-sections -Wall -fcommon -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" clean: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src: -$(RM) ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.su ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.cyclo ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.d ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.su .PHONY: clean-Drivers-2f-STM32G4xx_HAL_Driver-2f-Src ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/chorus_G431.list ================================================ chorus_G431.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d8 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00006358 080001d8 080001d8 000101d8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000019e8 08006530 08006530 00016530 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000024 08007f18 08007f18 00017f18 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .ARM 000000d8 08007f3c 08007f3c 00017f3c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08008014 08008014 0002005c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08008014 08008014 00018014 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08008018 08008018 00018018 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000005c 20000000 0800801c 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00007a18 2000005c 08008078 0002005c 2**2 ALLOC 10 ._user_heap_stack 00000404 20007a74 08008078 00027a74 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0002005c 2**0 CONTENTS, READONLY 12 .debug_info 0001c467 00000000 00000000 0002008c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00003eca 00000000 00000000 0003c4f3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loclists 0000c31c 00000000 00000000 000403bd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00000f70 00000000 00000000 0004c6e0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 00001760 00000000 00000000 0004d650 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 00023e70 00000000 00000000 0004edb0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 0001ef62 00000000 00000000 00072c20 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000dafb4 00000000 00000000 00091b82 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 0016cb36 2**0 CONTENTS, READONLY 21 .debug_frame 0000390c 00000000 00000000 0016cb7c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 0000006b 00000000 00000000 00170488 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001d8 <__do_global_dtors_aux>: 80001d8: b510 push {r4, lr} 80001da: 4c05 ldr r4, [pc, #20] ; (80001f0 <__do_global_dtors_aux+0x18>) 80001dc: 7823 ldrb r3, [r4, #0] 80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16> 80001e0: 4b04 ldr r3, [pc, #16] ; (80001f4 <__do_global_dtors_aux+0x1c>) 80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12> 80001e4: 4804 ldr r0, [pc, #16] ; (80001f8 <__do_global_dtors_aux+0x20>) 80001e6: f3af 8000 nop.w 80001ea: 2301 movs r3, #1 80001ec: 7023 strb r3, [r4, #0] 80001ee: bd10 pop {r4, pc} 80001f0: 2000005c .word 0x2000005c 80001f4: 00000000 .word 0x00000000 80001f8: 08006518 .word 0x08006518 080001fc : 80001fc: b508 push {r3, lr} 80001fe: 4b03 ldr r3, [pc, #12] ; (800020c ) 8000200: b11b cbz r3, 800020a 8000202: 4903 ldr r1, [pc, #12] ; (8000210 ) 8000204: 4803 ldr r0, [pc, #12] ; (8000214 ) 8000206: f3af 8000 nop.w 800020a: bd08 pop {r3, pc} 800020c: 00000000 .word 0x00000000 8000210: 20000060 .word 0x20000060 8000214: 08006518 .word 0x08006518 08000218 <__aeabi_drsub>: 8000218: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 800021c: e002 b.n 8000224 <__adddf3> 800021e: bf00 nop 08000220 <__aeabi_dsub>: 8000220: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 08000224 <__adddf3>: 8000224: b530 push {r4, r5, lr} 8000226: ea4f 0441 mov.w r4, r1, lsl #1 800022a: ea4f 0543 mov.w r5, r3, lsl #1 800022e: ea94 0f05 teq r4, r5 8000232: bf08 it eq 8000234: ea90 0f02 teqeq r0, r2 8000238: bf1f itttt ne 800023a: ea54 0c00 orrsne.w ip, r4, r0 800023e: ea55 0c02 orrsne.w ip, r5, r2 8000242: ea7f 5c64 mvnsne.w ip, r4, asr #21 8000246: ea7f 5c65 mvnsne.w ip, r5, asr #21 800024a: f000 80e2 beq.w 8000412 <__adddf3+0x1ee> 800024e: ea4f 5454 mov.w r4, r4, lsr #21 8000252: ebd4 5555 rsbs r5, r4, r5, lsr #21 8000256: bfb8 it lt 8000258: 426d neglt r5, r5 800025a: dd0c ble.n 8000276 <__adddf3+0x52> 800025c: 442c add r4, r5 800025e: ea80 0202 eor.w r2, r0, r2 8000262: ea81 0303 eor.w r3, r1, r3 8000266: ea82 0000 eor.w r0, r2, r0 800026a: ea83 0101 eor.w r1, r3, r1 800026e: ea80 0202 eor.w r2, r0, r2 8000272: ea81 0303 eor.w r3, r1, r3 8000276: 2d36 cmp r5, #54 ; 0x36 8000278: bf88 it hi 800027a: bd30 pophi {r4, r5, pc} 800027c: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000280: ea4f 3101 mov.w r1, r1, lsl #12 8000284: f44f 1c80 mov.w ip, #1048576 ; 0x100000 8000288: ea4c 3111 orr.w r1, ip, r1, lsr #12 800028c: d002 beq.n 8000294 <__adddf3+0x70> 800028e: 4240 negs r0, r0 8000290: eb61 0141 sbc.w r1, r1, r1, lsl #1 8000294: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 8000298: ea4f 3303 mov.w r3, r3, lsl #12 800029c: ea4c 3313 orr.w r3, ip, r3, lsr #12 80002a0: d002 beq.n 80002a8 <__adddf3+0x84> 80002a2: 4252 negs r2, r2 80002a4: eb63 0343 sbc.w r3, r3, r3, lsl #1 80002a8: ea94 0f05 teq r4, r5 80002ac: f000 80a7 beq.w 80003fe <__adddf3+0x1da> 80002b0: f1a4 0401 sub.w r4, r4, #1 80002b4: f1d5 0e20 rsbs lr, r5, #32 80002b8: db0d blt.n 80002d6 <__adddf3+0xb2> 80002ba: fa02 fc0e lsl.w ip, r2, lr 80002be: fa22 f205 lsr.w r2, r2, r5 80002c2: 1880 adds r0, r0, r2 80002c4: f141 0100 adc.w r1, r1, #0 80002c8: fa03 f20e lsl.w r2, r3, lr 80002cc: 1880 adds r0, r0, r2 80002ce: fa43 f305 asr.w r3, r3, r5 80002d2: 4159 adcs r1, r3 80002d4: e00e b.n 80002f4 <__adddf3+0xd0> 80002d6: f1a5 0520 sub.w r5, r5, #32 80002da: f10e 0e20 add.w lr, lr, #32 80002de: 2a01 cmp r2, #1 80002e0: fa03 fc0e lsl.w ip, r3, lr 80002e4: bf28 it cs 80002e6: f04c 0c02 orrcs.w ip, ip, #2 80002ea: fa43 f305 asr.w r3, r3, r5 80002ee: 18c0 adds r0, r0, r3 80002f0: eb51 71e3 adcs.w r1, r1, r3, asr #31 80002f4: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 80002f8: d507 bpl.n 800030a <__adddf3+0xe6> 80002fa: f04f 0e00 mov.w lr, #0 80002fe: f1dc 0c00 rsbs ip, ip, #0 8000302: eb7e 0000 sbcs.w r0, lr, r0 8000306: eb6e 0101 sbc.w r1, lr, r1 800030a: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 800030e: d31b bcc.n 8000348 <__adddf3+0x124> 8000310: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 8000314: d30c bcc.n 8000330 <__adddf3+0x10c> 8000316: 0849 lsrs r1, r1, #1 8000318: ea5f 0030 movs.w r0, r0, rrx 800031c: ea4f 0c3c mov.w ip, ip, rrx 8000320: f104 0401 add.w r4, r4, #1 8000324: ea4f 5244 mov.w r2, r4, lsl #21 8000328: f512 0f80 cmn.w r2, #4194304 ; 0x400000 800032c: f080 809a bcs.w 8000464 <__adddf3+0x240> 8000330: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 8000334: bf08 it eq 8000336: ea5f 0c50 movseq.w ip, r0, lsr #1 800033a: f150 0000 adcs.w r0, r0, #0 800033e: eb41 5104 adc.w r1, r1, r4, lsl #20 8000342: ea41 0105 orr.w r1, r1, r5 8000346: bd30 pop {r4, r5, pc} 8000348: ea5f 0c4c movs.w ip, ip, lsl #1 800034c: 4140 adcs r0, r0 800034e: eb41 0101 adc.w r1, r1, r1 8000352: 3c01 subs r4, #1 8000354: bf28 it cs 8000356: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000 800035a: d2e9 bcs.n 8000330 <__adddf3+0x10c> 800035c: f091 0f00 teq r1, #0 8000360: bf04 itt eq 8000362: 4601 moveq r1, r0 8000364: 2000 moveq r0, #0 8000366: fab1 f381 clz r3, r1 800036a: bf08 it eq 800036c: 3320 addeq r3, #32 800036e: f1a3 030b sub.w r3, r3, #11 8000372: f1b3 0220 subs.w r2, r3, #32 8000376: da0c bge.n 8000392 <__adddf3+0x16e> 8000378: 320c adds r2, #12 800037a: dd08 ble.n 800038e <__adddf3+0x16a> 800037c: f102 0c14 add.w ip, r2, #20 8000380: f1c2 020c rsb r2, r2, #12 8000384: fa01 f00c lsl.w r0, r1, ip 8000388: fa21 f102 lsr.w r1, r1, r2 800038c: e00c b.n 80003a8 <__adddf3+0x184> 800038e: f102 0214 add.w r2, r2, #20 8000392: bfd8 it le 8000394: f1c2 0c20 rsble ip, r2, #32 8000398: fa01 f102 lsl.w r1, r1, r2 800039c: fa20 fc0c lsr.w ip, r0, ip 80003a0: bfdc itt le 80003a2: ea41 010c orrle.w r1, r1, ip 80003a6: 4090 lslle r0, r2 80003a8: 1ae4 subs r4, r4, r3 80003aa: bfa2 ittt ge 80003ac: eb01 5104 addge.w r1, r1, r4, lsl #20 80003b0: 4329 orrge r1, r5 80003b2: bd30 popge {r4, r5, pc} 80003b4: ea6f 0404 mvn.w r4, r4 80003b8: 3c1f subs r4, #31 80003ba: da1c bge.n 80003f6 <__adddf3+0x1d2> 80003bc: 340c adds r4, #12 80003be: dc0e bgt.n 80003de <__adddf3+0x1ba> 80003c0: f104 0414 add.w r4, r4, #20 80003c4: f1c4 0220 rsb r2, r4, #32 80003c8: fa20 f004 lsr.w r0, r0, r4 80003cc: fa01 f302 lsl.w r3, r1, r2 80003d0: ea40 0003 orr.w r0, r0, r3 80003d4: fa21 f304 lsr.w r3, r1, r4 80003d8: ea45 0103 orr.w r1, r5, r3 80003dc: bd30 pop {r4, r5, pc} 80003de: f1c4 040c rsb r4, r4, #12 80003e2: f1c4 0220 rsb r2, r4, #32 80003e6: fa20 f002 lsr.w r0, r0, r2 80003ea: fa01 f304 lsl.w r3, r1, r4 80003ee: ea40 0003 orr.w r0, r0, r3 80003f2: 4629 mov r1, r5 80003f4: bd30 pop {r4, r5, pc} 80003f6: fa21 f004 lsr.w r0, r1, r4 80003fa: 4629 mov r1, r5 80003fc: bd30 pop {r4, r5, pc} 80003fe: f094 0f00 teq r4, #0 8000402: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 8000406: bf06 itte eq 8000408: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 800040c: 3401 addeq r4, #1 800040e: 3d01 subne r5, #1 8000410: e74e b.n 80002b0 <__adddf3+0x8c> 8000412: ea7f 5c64 mvns.w ip, r4, asr #21 8000416: bf18 it ne 8000418: ea7f 5c65 mvnsne.w ip, r5, asr #21 800041c: d029 beq.n 8000472 <__adddf3+0x24e> 800041e: ea94 0f05 teq r4, r5 8000422: bf08 it eq 8000424: ea90 0f02 teqeq r0, r2 8000428: d005 beq.n 8000436 <__adddf3+0x212> 800042a: ea54 0c00 orrs.w ip, r4, r0 800042e: bf04 itt eq 8000430: 4619 moveq r1, r3 8000432: 4610 moveq r0, r2 8000434: bd30 pop {r4, r5, pc} 8000436: ea91 0f03 teq r1, r3 800043a: bf1e ittt ne 800043c: 2100 movne r1, #0 800043e: 2000 movne r0, #0 8000440: bd30 popne {r4, r5, pc} 8000442: ea5f 5c54 movs.w ip, r4, lsr #21 8000446: d105 bne.n 8000454 <__adddf3+0x230> 8000448: 0040 lsls r0, r0, #1 800044a: 4149 adcs r1, r1 800044c: bf28 it cs 800044e: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 8000452: bd30 pop {r4, r5, pc} 8000454: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8000458: bf3c itt cc 800045a: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 800045e: bd30 popcc {r4, r5, pc} 8000460: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8000464: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8000468: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 800046c: f04f 0000 mov.w r0, #0 8000470: bd30 pop {r4, r5, pc} 8000472: ea7f 5c64 mvns.w ip, r4, asr #21 8000476: bf1a itte ne 8000478: 4619 movne r1, r3 800047a: 4610 movne r0, r2 800047c: ea7f 5c65 mvnseq.w ip, r5, asr #21 8000480: bf1c itt ne 8000482: 460b movne r3, r1 8000484: 4602 movne r2, r0 8000486: ea50 3401 orrs.w r4, r0, r1, lsl #12 800048a: bf06 itte eq 800048c: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8000490: ea91 0f03 teqeq r1, r3 8000494: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 8000498: bd30 pop {r4, r5, pc} 800049a: bf00 nop 0800049c <__aeabi_ui2d>: 800049c: f090 0f00 teq r0, #0 80004a0: bf04 itt eq 80004a2: 2100 moveq r1, #0 80004a4: 4770 bxeq lr 80004a6: b530 push {r4, r5, lr} 80004a8: f44f 6480 mov.w r4, #1024 ; 0x400 80004ac: f104 0432 add.w r4, r4, #50 ; 0x32 80004b0: f04f 0500 mov.w r5, #0 80004b4: f04f 0100 mov.w r1, #0 80004b8: e750 b.n 800035c <__adddf3+0x138> 80004ba: bf00 nop 080004bc <__aeabi_i2d>: 80004bc: f090 0f00 teq r0, #0 80004c0: bf04 itt eq 80004c2: 2100 moveq r1, #0 80004c4: 4770 bxeq lr 80004c6: b530 push {r4, r5, lr} 80004c8: f44f 6480 mov.w r4, #1024 ; 0x400 80004cc: f104 0432 add.w r4, r4, #50 ; 0x32 80004d0: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 80004d4: bf48 it mi 80004d6: 4240 negmi r0, r0 80004d8: f04f 0100 mov.w r1, #0 80004dc: e73e b.n 800035c <__adddf3+0x138> 80004de: bf00 nop 080004e0 <__aeabi_f2d>: 80004e0: 0042 lsls r2, r0, #1 80004e2: ea4f 01e2 mov.w r1, r2, asr #3 80004e6: ea4f 0131 mov.w r1, r1, rrx 80004ea: ea4f 7002 mov.w r0, r2, lsl #28 80004ee: bf1f itttt ne 80004f0: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 80004f4: f093 4f7f teqne r3, #4278190080 ; 0xff000000 80004f8: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 80004fc: 4770 bxne lr 80004fe: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 8000502: bf08 it eq 8000504: 4770 bxeq lr 8000506: f093 4f7f teq r3, #4278190080 ; 0xff000000 800050a: bf04 itt eq 800050c: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 8000510: 4770 bxeq lr 8000512: b530 push {r4, r5, lr} 8000514: f44f 7460 mov.w r4, #896 ; 0x380 8000518: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 800051c: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8000520: e71c b.n 800035c <__adddf3+0x138> 8000522: bf00 nop 08000524 <__aeabi_ul2d>: 8000524: ea50 0201 orrs.w r2, r0, r1 8000528: bf08 it eq 800052a: 4770 bxeq lr 800052c: b530 push {r4, r5, lr} 800052e: f04f 0500 mov.w r5, #0 8000532: e00a b.n 800054a <__aeabi_l2d+0x16> 08000534 <__aeabi_l2d>: 8000534: ea50 0201 orrs.w r2, r0, r1 8000538: bf08 it eq 800053a: 4770 bxeq lr 800053c: b530 push {r4, r5, lr} 800053e: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 8000542: d502 bpl.n 800054a <__aeabi_l2d+0x16> 8000544: 4240 negs r0, r0 8000546: eb61 0141 sbc.w r1, r1, r1, lsl #1 800054a: f44f 6480 mov.w r4, #1024 ; 0x400 800054e: f104 0432 add.w r4, r4, #50 ; 0x32 8000552: ea5f 5c91 movs.w ip, r1, lsr #22 8000556: f43f aed8 beq.w 800030a <__adddf3+0xe6> 800055a: f04f 0203 mov.w r2, #3 800055e: ea5f 0cdc movs.w ip, ip, lsr #3 8000562: bf18 it ne 8000564: 3203 addne r2, #3 8000566: ea5f 0cdc movs.w ip, ip, lsr #3 800056a: bf18 it ne 800056c: 3203 addne r2, #3 800056e: eb02 02dc add.w r2, r2, ip, lsr #3 8000572: f1c2 0320 rsb r3, r2, #32 8000576: fa00 fc03 lsl.w ip, r0, r3 800057a: fa20 f002 lsr.w r0, r0, r2 800057e: fa01 fe03 lsl.w lr, r1, r3 8000582: ea40 000e orr.w r0, r0, lr 8000586: fa21 f102 lsr.w r1, r1, r2 800058a: 4414 add r4, r2 800058c: e6bd b.n 800030a <__adddf3+0xe6> 800058e: bf00 nop 08000590 <__aeabi_dmul>: 8000590: b570 push {r4, r5, r6, lr} 8000592: f04f 0cff mov.w ip, #255 ; 0xff 8000596: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 800059a: ea1c 5411 ands.w r4, ip, r1, lsr #20 800059e: bf1d ittte ne 80005a0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80005a4: ea94 0f0c teqne r4, ip 80005a8: ea95 0f0c teqne r5, ip 80005ac: f000 f8de bleq 800076c <__aeabi_dmul+0x1dc> 80005b0: 442c add r4, r5 80005b2: ea81 0603 eor.w r6, r1, r3 80005b6: ea21 514c bic.w r1, r1, ip, lsl #21 80005ba: ea23 534c bic.w r3, r3, ip, lsl #21 80005be: ea50 3501 orrs.w r5, r0, r1, lsl #12 80005c2: bf18 it ne 80005c4: ea52 3503 orrsne.w r5, r2, r3, lsl #12 80005c8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80005cc: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80005d0: d038 beq.n 8000644 <__aeabi_dmul+0xb4> 80005d2: fba0 ce02 umull ip, lr, r0, r2 80005d6: f04f 0500 mov.w r5, #0 80005da: fbe1 e502 umlal lr, r5, r1, r2 80005de: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 80005e2: fbe0 e503 umlal lr, r5, r0, r3 80005e6: f04f 0600 mov.w r6, #0 80005ea: fbe1 5603 umlal r5, r6, r1, r3 80005ee: f09c 0f00 teq ip, #0 80005f2: bf18 it ne 80005f4: f04e 0e01 orrne.w lr, lr, #1 80005f8: f1a4 04ff sub.w r4, r4, #255 ; 0xff 80005fc: f5b6 7f00 cmp.w r6, #512 ; 0x200 8000600: f564 7440 sbc.w r4, r4, #768 ; 0x300 8000604: d204 bcs.n 8000610 <__aeabi_dmul+0x80> 8000606: ea5f 0e4e movs.w lr, lr, lsl #1 800060a: 416d adcs r5, r5 800060c: eb46 0606 adc.w r6, r6, r6 8000610: ea42 21c6 orr.w r1, r2, r6, lsl #11 8000614: ea41 5155 orr.w r1, r1, r5, lsr #21 8000618: ea4f 20c5 mov.w r0, r5, lsl #11 800061c: ea40 505e orr.w r0, r0, lr, lsr #21 8000620: ea4f 2ece mov.w lr, lr, lsl #11 8000624: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000628: bf88 it hi 800062a: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 800062e: d81e bhi.n 800066e <__aeabi_dmul+0xde> 8000630: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 8000634: bf08 it eq 8000636: ea5f 0e50 movseq.w lr, r0, lsr #1 800063a: f150 0000 adcs.w r0, r0, #0 800063e: eb41 5104 adc.w r1, r1, r4, lsl #20 8000642: bd70 pop {r4, r5, r6, pc} 8000644: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8000648: ea46 0101 orr.w r1, r6, r1 800064c: ea40 0002 orr.w r0, r0, r2 8000650: ea81 0103 eor.w r1, r1, r3 8000654: ebb4 045c subs.w r4, r4, ip, lsr #1 8000658: bfc2 ittt gt 800065a: ebd4 050c rsbsgt r5, r4, ip 800065e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8000662: bd70 popgt {r4, r5, r6, pc} 8000664: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000668: f04f 0e00 mov.w lr, #0 800066c: 3c01 subs r4, #1 800066e: f300 80ab bgt.w 80007c8 <__aeabi_dmul+0x238> 8000672: f114 0f36 cmn.w r4, #54 ; 0x36 8000676: bfde ittt le 8000678: 2000 movle r0, #0 800067a: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 800067e: bd70 pople {r4, r5, r6, pc} 8000680: f1c4 0400 rsb r4, r4, #0 8000684: 3c20 subs r4, #32 8000686: da35 bge.n 80006f4 <__aeabi_dmul+0x164> 8000688: 340c adds r4, #12 800068a: dc1b bgt.n 80006c4 <__aeabi_dmul+0x134> 800068c: f104 0414 add.w r4, r4, #20 8000690: f1c4 0520 rsb r5, r4, #32 8000694: fa00 f305 lsl.w r3, r0, r5 8000698: fa20 f004 lsr.w r0, r0, r4 800069c: fa01 f205 lsl.w r2, r1, r5 80006a0: ea40 0002 orr.w r0, r0, r2 80006a4: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 80006a8: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 80006ac: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006b0: fa21 f604 lsr.w r6, r1, r4 80006b4: eb42 0106 adc.w r1, r2, r6 80006b8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006bc: bf08 it eq 80006be: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006c2: bd70 pop {r4, r5, r6, pc} 80006c4: f1c4 040c rsb r4, r4, #12 80006c8: f1c4 0520 rsb r5, r4, #32 80006cc: fa00 f304 lsl.w r3, r0, r4 80006d0: fa20 f005 lsr.w r0, r0, r5 80006d4: fa01 f204 lsl.w r2, r1, r4 80006d8: ea40 0002 orr.w r0, r0, r2 80006dc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80006e0: eb10 70d3 adds.w r0, r0, r3, lsr #31 80006e4: f141 0100 adc.w r1, r1, #0 80006e8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 80006ec: bf08 it eq 80006ee: ea20 70d3 biceq.w r0, r0, r3, lsr #31 80006f2: bd70 pop {r4, r5, r6, pc} 80006f4: f1c4 0520 rsb r5, r4, #32 80006f8: fa00 f205 lsl.w r2, r0, r5 80006fc: ea4e 0e02 orr.w lr, lr, r2 8000700: fa20 f304 lsr.w r3, r0, r4 8000704: fa01 f205 lsl.w r2, r1, r5 8000708: ea43 0302 orr.w r3, r3, r2 800070c: fa21 f004 lsr.w r0, r1, r4 8000710: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000714: fa21 f204 lsr.w r2, r1, r4 8000718: ea20 0002 bic.w r0, r0, r2 800071c: eb00 70d3 add.w r0, r0, r3, lsr #31 8000720: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8000724: bf08 it eq 8000726: ea20 70d3 biceq.w r0, r0, r3, lsr #31 800072a: bd70 pop {r4, r5, r6, pc} 800072c: f094 0f00 teq r4, #0 8000730: d10f bne.n 8000752 <__aeabi_dmul+0x1c2> 8000732: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 8000736: 0040 lsls r0, r0, #1 8000738: eb41 0101 adc.w r1, r1, r1 800073c: f411 1f80 tst.w r1, #1048576 ; 0x100000 8000740: bf08 it eq 8000742: 3c01 subeq r4, #1 8000744: d0f7 beq.n 8000736 <__aeabi_dmul+0x1a6> 8000746: ea41 0106 orr.w r1, r1, r6 800074a: f095 0f00 teq r5, #0 800074e: bf18 it ne 8000750: 4770 bxne lr 8000752: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 8000756: 0052 lsls r2, r2, #1 8000758: eb43 0303 adc.w r3, r3, r3 800075c: f413 1f80 tst.w r3, #1048576 ; 0x100000 8000760: bf08 it eq 8000762: 3d01 subeq r5, #1 8000764: d0f7 beq.n 8000756 <__aeabi_dmul+0x1c6> 8000766: ea43 0306 orr.w r3, r3, r6 800076a: 4770 bx lr 800076c: ea94 0f0c teq r4, ip 8000770: ea0c 5513 and.w r5, ip, r3, lsr #20 8000774: bf18 it ne 8000776: ea95 0f0c teqne r5, ip 800077a: d00c beq.n 8000796 <__aeabi_dmul+0x206> 800077c: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000780: bf18 it ne 8000782: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8000786: d1d1 bne.n 800072c <__aeabi_dmul+0x19c> 8000788: ea81 0103 eor.w r1, r1, r3 800078c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8000790: f04f 0000 mov.w r0, #0 8000794: bd70 pop {r4, r5, r6, pc} 8000796: ea50 0641 orrs.w r6, r0, r1, lsl #1 800079a: bf06 itte eq 800079c: 4610 moveq r0, r2 800079e: 4619 moveq r1, r3 80007a0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 80007a4: d019 beq.n 80007da <__aeabi_dmul+0x24a> 80007a6: ea94 0f0c teq r4, ip 80007aa: d102 bne.n 80007b2 <__aeabi_dmul+0x222> 80007ac: ea50 3601 orrs.w r6, r0, r1, lsl #12 80007b0: d113 bne.n 80007da <__aeabi_dmul+0x24a> 80007b2: ea95 0f0c teq r5, ip 80007b6: d105 bne.n 80007c4 <__aeabi_dmul+0x234> 80007b8: ea52 3603 orrs.w r6, r2, r3, lsl #12 80007bc: bf1c itt ne 80007be: 4610 movne r0, r2 80007c0: 4619 movne r1, r3 80007c2: d10a bne.n 80007da <__aeabi_dmul+0x24a> 80007c4: ea81 0103 eor.w r1, r1, r3 80007c8: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 80007cc: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007d0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 80007d4: f04f 0000 mov.w r0, #0 80007d8: bd70 pop {r4, r5, r6, pc} 80007da: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 80007de: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 80007e2: bd70 pop {r4, r5, r6, pc} 080007e4 <__aeabi_ddiv>: 80007e4: b570 push {r4, r5, r6, lr} 80007e6: f04f 0cff mov.w ip, #255 ; 0xff 80007ea: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 80007ee: ea1c 5411 ands.w r4, ip, r1, lsr #20 80007f2: bf1d ittte ne 80007f4: ea1c 5513 andsne.w r5, ip, r3, lsr #20 80007f8: ea94 0f0c teqne r4, ip 80007fc: ea95 0f0c teqne r5, ip 8000800: f000 f8a7 bleq 8000952 <__aeabi_ddiv+0x16e> 8000804: eba4 0405 sub.w r4, r4, r5 8000808: ea81 0e03 eor.w lr, r1, r3 800080c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8000810: ea4f 3101 mov.w r1, r1, lsl #12 8000814: f000 8088 beq.w 8000928 <__aeabi_ddiv+0x144> 8000818: ea4f 3303 mov.w r3, r3, lsl #12 800081c: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8000820: ea45 1313 orr.w r3, r5, r3, lsr #4 8000824: ea43 6312 orr.w r3, r3, r2, lsr #24 8000828: ea4f 2202 mov.w r2, r2, lsl #8 800082c: ea45 1511 orr.w r5, r5, r1, lsr #4 8000830: ea45 6510 orr.w r5, r5, r0, lsr #24 8000834: ea4f 2600 mov.w r6, r0, lsl #8 8000838: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 800083c: 429d cmp r5, r3 800083e: bf08 it eq 8000840: 4296 cmpeq r6, r2 8000842: f144 04fd adc.w r4, r4, #253 ; 0xfd 8000846: f504 7440 add.w r4, r4, #768 ; 0x300 800084a: d202 bcs.n 8000852 <__aeabi_ddiv+0x6e> 800084c: 085b lsrs r3, r3, #1 800084e: ea4f 0232 mov.w r2, r2, rrx 8000852: 1ab6 subs r6, r6, r2 8000854: eb65 0503 sbc.w r5, r5, r3 8000858: 085b lsrs r3, r3, #1 800085a: ea4f 0232 mov.w r2, r2, rrx 800085e: f44f 1080 mov.w r0, #1048576 ; 0x100000 8000862: f44f 2c00 mov.w ip, #524288 ; 0x80000 8000866: ebb6 0e02 subs.w lr, r6, r2 800086a: eb75 0e03 sbcs.w lr, r5, r3 800086e: bf22 ittt cs 8000870: 1ab6 subcs r6, r6, r2 8000872: 4675 movcs r5, lr 8000874: ea40 000c orrcs.w r0, r0, ip 8000878: 085b lsrs r3, r3, #1 800087a: ea4f 0232 mov.w r2, r2, rrx 800087e: ebb6 0e02 subs.w lr, r6, r2 8000882: eb75 0e03 sbcs.w lr, r5, r3 8000886: bf22 ittt cs 8000888: 1ab6 subcs r6, r6, r2 800088a: 4675 movcs r5, lr 800088c: ea40 005c orrcs.w r0, r0, ip, lsr #1 8000890: 085b lsrs r3, r3, #1 8000892: ea4f 0232 mov.w r2, r2, rrx 8000896: ebb6 0e02 subs.w lr, r6, r2 800089a: eb75 0e03 sbcs.w lr, r5, r3 800089e: bf22 ittt cs 80008a0: 1ab6 subcs r6, r6, r2 80008a2: 4675 movcs r5, lr 80008a4: ea40 009c orrcs.w r0, r0, ip, lsr #2 80008a8: 085b lsrs r3, r3, #1 80008aa: ea4f 0232 mov.w r2, r2, rrx 80008ae: ebb6 0e02 subs.w lr, r6, r2 80008b2: eb75 0e03 sbcs.w lr, r5, r3 80008b6: bf22 ittt cs 80008b8: 1ab6 subcs r6, r6, r2 80008ba: 4675 movcs r5, lr 80008bc: ea40 00dc orrcs.w r0, r0, ip, lsr #3 80008c0: ea55 0e06 orrs.w lr, r5, r6 80008c4: d018 beq.n 80008f8 <__aeabi_ddiv+0x114> 80008c6: ea4f 1505 mov.w r5, r5, lsl #4 80008ca: ea45 7516 orr.w r5, r5, r6, lsr #28 80008ce: ea4f 1606 mov.w r6, r6, lsl #4 80008d2: ea4f 03c3 mov.w r3, r3, lsl #3 80008d6: ea43 7352 orr.w r3, r3, r2, lsr #29 80008da: ea4f 02c2 mov.w r2, r2, lsl #3 80008de: ea5f 1c1c movs.w ip, ip, lsr #4 80008e2: d1c0 bne.n 8000866 <__aeabi_ddiv+0x82> 80008e4: f411 1f80 tst.w r1, #1048576 ; 0x100000 80008e8: d10b bne.n 8000902 <__aeabi_ddiv+0x11e> 80008ea: ea41 0100 orr.w r1, r1, r0 80008ee: f04f 0000 mov.w r0, #0 80008f2: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 80008f6: e7b6 b.n 8000866 <__aeabi_ddiv+0x82> 80008f8: f411 1f80 tst.w r1, #1048576 ; 0x100000 80008fc: bf04 itt eq 80008fe: 4301 orreq r1, r0 8000900: 2000 moveq r0, #0 8000902: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8000906: bf88 it hi 8000908: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 800090c: f63f aeaf bhi.w 800066e <__aeabi_dmul+0xde> 8000910: ebb5 0c03 subs.w ip, r5, r3 8000914: bf04 itt eq 8000916: ebb6 0c02 subseq.w ip, r6, r2 800091a: ea5f 0c50 movseq.w ip, r0, lsr #1 800091e: f150 0000 adcs.w r0, r0, #0 8000922: eb41 5104 adc.w r1, r1, r4, lsl #20 8000926: bd70 pop {r4, r5, r6, pc} 8000928: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 800092c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8000930: eb14 045c adds.w r4, r4, ip, lsr #1 8000934: bfc2 ittt gt 8000936: ebd4 050c rsbsgt r5, r4, ip 800093a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 800093e: bd70 popgt {r4, r5, r6, pc} 8000940: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000944: f04f 0e00 mov.w lr, #0 8000948: 3c01 subs r4, #1 800094a: e690 b.n 800066e <__aeabi_dmul+0xde> 800094c: ea45 0e06 orr.w lr, r5, r6 8000950: e68d b.n 800066e <__aeabi_dmul+0xde> 8000952: ea0c 5513 and.w r5, ip, r3, lsr #20 8000956: ea94 0f0c teq r4, ip 800095a: bf08 it eq 800095c: ea95 0f0c teqeq r5, ip 8000960: f43f af3b beq.w 80007da <__aeabi_dmul+0x24a> 8000964: ea94 0f0c teq r4, ip 8000968: d10a bne.n 8000980 <__aeabi_ddiv+0x19c> 800096a: ea50 3401 orrs.w r4, r0, r1, lsl #12 800096e: f47f af34 bne.w 80007da <__aeabi_dmul+0x24a> 8000972: ea95 0f0c teq r5, ip 8000976: f47f af25 bne.w 80007c4 <__aeabi_dmul+0x234> 800097a: 4610 mov r0, r2 800097c: 4619 mov r1, r3 800097e: e72c b.n 80007da <__aeabi_dmul+0x24a> 8000980: ea95 0f0c teq r5, ip 8000984: d106 bne.n 8000994 <__aeabi_ddiv+0x1b0> 8000986: ea52 3503 orrs.w r5, r2, r3, lsl #12 800098a: f43f aefd beq.w 8000788 <__aeabi_dmul+0x1f8> 800098e: 4610 mov r0, r2 8000990: 4619 mov r1, r3 8000992: e722 b.n 80007da <__aeabi_dmul+0x24a> 8000994: ea50 0641 orrs.w r6, r0, r1, lsl #1 8000998: bf18 it ne 800099a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 800099e: f47f aec5 bne.w 800072c <__aeabi_dmul+0x19c> 80009a2: ea50 0441 orrs.w r4, r0, r1, lsl #1 80009a6: f47f af0d bne.w 80007c4 <__aeabi_dmul+0x234> 80009aa: ea52 0543 orrs.w r5, r2, r3, lsl #1 80009ae: f47f aeeb bne.w 8000788 <__aeabi_dmul+0x1f8> 80009b2: e712 b.n 80007da <__aeabi_dmul+0x24a> 080009b4 <__gedf2>: 80009b4: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 80009b8: e006 b.n 80009c8 <__cmpdf2+0x4> 80009ba: bf00 nop 080009bc <__ledf2>: 80009bc: f04f 0c01 mov.w ip, #1 80009c0: e002 b.n 80009c8 <__cmpdf2+0x4> 80009c2: bf00 nop 080009c4 <__cmpdf2>: 80009c4: f04f 0c01 mov.w ip, #1 80009c8: f84d cd04 str.w ip, [sp, #-4]! 80009cc: ea4f 0c41 mov.w ip, r1, lsl #1 80009d0: ea7f 5c6c mvns.w ip, ip, asr #21 80009d4: ea4f 0c43 mov.w ip, r3, lsl #1 80009d8: bf18 it ne 80009da: ea7f 5c6c mvnsne.w ip, ip, asr #21 80009de: d01b beq.n 8000a18 <__cmpdf2+0x54> 80009e0: b001 add sp, #4 80009e2: ea50 0c41 orrs.w ip, r0, r1, lsl #1 80009e6: bf0c ite eq 80009e8: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 80009ec: ea91 0f03 teqne r1, r3 80009f0: bf02 ittt eq 80009f2: ea90 0f02 teqeq r0, r2 80009f6: 2000 moveq r0, #0 80009f8: 4770 bxeq lr 80009fa: f110 0f00 cmn.w r0, #0 80009fe: ea91 0f03 teq r1, r3 8000a02: bf58 it pl 8000a04: 4299 cmppl r1, r3 8000a06: bf08 it eq 8000a08: 4290 cmpeq r0, r2 8000a0a: bf2c ite cs 8000a0c: 17d8 asrcs r0, r3, #31 8000a0e: ea6f 70e3 mvncc.w r0, r3, asr #31 8000a12: f040 0001 orr.w r0, r0, #1 8000a16: 4770 bx lr 8000a18: ea4f 0c41 mov.w ip, r1, lsl #1 8000a1c: ea7f 5c6c mvns.w ip, ip, asr #21 8000a20: d102 bne.n 8000a28 <__cmpdf2+0x64> 8000a22: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8000a26: d107 bne.n 8000a38 <__cmpdf2+0x74> 8000a28: ea4f 0c43 mov.w ip, r3, lsl #1 8000a2c: ea7f 5c6c mvns.w ip, ip, asr #21 8000a30: d1d6 bne.n 80009e0 <__cmpdf2+0x1c> 8000a32: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8000a36: d0d3 beq.n 80009e0 <__cmpdf2+0x1c> 8000a38: f85d 0b04 ldr.w r0, [sp], #4 8000a3c: 4770 bx lr 8000a3e: bf00 nop 08000a40 <__aeabi_cdrcmple>: 8000a40: 4684 mov ip, r0 8000a42: 4610 mov r0, r2 8000a44: 4662 mov r2, ip 8000a46: 468c mov ip, r1 8000a48: 4619 mov r1, r3 8000a4a: 4663 mov r3, ip 8000a4c: e000 b.n 8000a50 <__aeabi_cdcmpeq> 8000a4e: bf00 nop 08000a50 <__aeabi_cdcmpeq>: 8000a50: b501 push {r0, lr} 8000a52: f7ff ffb7 bl 80009c4 <__cmpdf2> 8000a56: 2800 cmp r0, #0 8000a58: bf48 it mi 8000a5a: f110 0f00 cmnmi.w r0, #0 8000a5e: bd01 pop {r0, pc} 08000a60 <__aeabi_dcmpeq>: 8000a60: f84d ed08 str.w lr, [sp, #-8]! 8000a64: f7ff fff4 bl 8000a50 <__aeabi_cdcmpeq> 8000a68: bf0c ite eq 8000a6a: 2001 moveq r0, #1 8000a6c: 2000 movne r0, #0 8000a6e: f85d fb08 ldr.w pc, [sp], #8 8000a72: bf00 nop 08000a74 <__aeabi_dcmplt>: 8000a74: f84d ed08 str.w lr, [sp, #-8]! 8000a78: f7ff ffea bl 8000a50 <__aeabi_cdcmpeq> 8000a7c: bf34 ite cc 8000a7e: 2001 movcc r0, #1 8000a80: 2000 movcs r0, #0 8000a82: f85d fb08 ldr.w pc, [sp], #8 8000a86: bf00 nop 08000a88 <__aeabi_dcmple>: 8000a88: f84d ed08 str.w lr, [sp, #-8]! 8000a8c: f7ff ffe0 bl 8000a50 <__aeabi_cdcmpeq> 8000a90: bf94 ite ls 8000a92: 2001 movls r0, #1 8000a94: 2000 movhi r0, #0 8000a96: f85d fb08 ldr.w pc, [sp], #8 8000a9a: bf00 nop 08000a9c <__aeabi_dcmpge>: 8000a9c: f84d ed08 str.w lr, [sp, #-8]! 8000aa0: f7ff ffce bl 8000a40 <__aeabi_cdrcmple> 8000aa4: bf94 ite ls 8000aa6: 2001 movls r0, #1 8000aa8: 2000 movhi r0, #0 8000aaa: f85d fb08 ldr.w pc, [sp], #8 8000aae: bf00 nop 08000ab0 <__aeabi_dcmpgt>: 8000ab0: f84d ed08 str.w lr, [sp, #-8]! 8000ab4: f7ff ffc4 bl 8000a40 <__aeabi_cdrcmple> 8000ab8: bf34 ite cc 8000aba: 2001 movcc r0, #1 8000abc: 2000 movcs r0, #0 8000abe: f85d fb08 ldr.w pc, [sp], #8 8000ac2: bf00 nop 08000ac4 <__aeabi_d2iz>: 8000ac4: ea4f 0241 mov.w r2, r1, lsl #1 8000ac8: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 8000acc: d215 bcs.n 8000afa <__aeabi_d2iz+0x36> 8000ace: d511 bpl.n 8000af4 <__aeabi_d2iz+0x30> 8000ad0: f46f 7378 mvn.w r3, #992 ; 0x3e0 8000ad4: ebb3 5262 subs.w r2, r3, r2, asr #21 8000ad8: d912 bls.n 8000b00 <__aeabi_d2iz+0x3c> 8000ada: ea4f 23c1 mov.w r3, r1, lsl #11 8000ade: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8000ae2: ea43 5350 orr.w r3, r3, r0, lsr #21 8000ae6: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 8000aea: fa23 f002 lsr.w r0, r3, r2 8000aee: bf18 it ne 8000af0: 4240 negne r0, r0 8000af2: 4770 bx lr 8000af4: f04f 0000 mov.w r0, #0 8000af8: 4770 bx lr 8000afa: ea50 3001 orrs.w r0, r0, r1, lsl #12 8000afe: d105 bne.n 8000b0c <__aeabi_d2iz+0x48> 8000b00: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8000b04: bf08 it eq 8000b06: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 8000b0a: 4770 bx lr 8000b0c: f04f 0000 mov.w r0, #0 8000b10: 4770 bx lr 8000b12: bf00 nop 08000b14 <__aeabi_d2f>: 8000b14: ea4f 0241 mov.w r2, r1, lsl #1 8000b18: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 8000b1c: bf24 itt cs 8000b1e: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 8000b22: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 8000b26: d90d bls.n 8000b44 <__aeabi_d2f+0x30> 8000b28: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 8000b2c: ea4f 02c0 mov.w r2, r0, lsl #3 8000b30: ea4c 7050 orr.w r0, ip, r0, lsr #29 8000b34: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 8000b38: eb40 0083 adc.w r0, r0, r3, lsl #2 8000b3c: bf08 it eq 8000b3e: f020 0001 biceq.w r0, r0, #1 8000b42: 4770 bx lr 8000b44: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 8000b48: d121 bne.n 8000b8e <__aeabi_d2f+0x7a> 8000b4a: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 8000b4e: bfbc itt lt 8000b50: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 8000b54: 4770 bxlt lr 8000b56: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8000b5a: ea4f 5252 mov.w r2, r2, lsr #21 8000b5e: f1c2 0218 rsb r2, r2, #24 8000b62: f1c2 0c20 rsb ip, r2, #32 8000b66: fa10 f30c lsls.w r3, r0, ip 8000b6a: fa20 f002 lsr.w r0, r0, r2 8000b6e: bf18 it ne 8000b70: f040 0001 orrne.w r0, r0, #1 8000b74: ea4f 23c1 mov.w r3, r1, lsl #11 8000b78: ea4f 23d3 mov.w r3, r3, lsr #11 8000b7c: fa03 fc0c lsl.w ip, r3, ip 8000b80: ea40 000c orr.w r0, r0, ip 8000b84: fa23 f302 lsr.w r3, r3, r2 8000b88: ea4f 0343 mov.w r3, r3, lsl #1 8000b8c: e7cc b.n 8000b28 <__aeabi_d2f+0x14> 8000b8e: ea7f 5362 mvns.w r3, r2, asr #21 8000b92: d107 bne.n 8000ba4 <__aeabi_d2f+0x90> 8000b94: ea50 3301 orrs.w r3, r0, r1, lsl #12 8000b98: bf1e ittt ne 8000b9a: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 8000b9e: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 8000ba2: 4770 bxne lr 8000ba4: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 8000ba8: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 8000bac: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8000bb0: 4770 bx lr 8000bb2: bf00 nop 08000bb4 : 8000bb4: 6803 ldr r3, [r0, #0] 8000bb6: 005a lsls r2, r3, #1 8000bb8: bf4c ite mi 8000bba: f043 4300 orrmi.w r3, r3, #2147483648 ; 0x80000000 8000bbe: f023 4300 bicpl.w r3, r3, #2147483648 ; 0x80000000 8000bc2: 4418 add r0, r3 8000bc4: 4770 bx lr 8000bc6: bf00 nop 08000bc8 : 8000bc8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8000bcc: b329 cbz r1, 8000c1a 8000bce: 1e4f subs r7, r1, #1 8000bd0: 4604 mov r4, r0 8000bd2: 4615 mov r5, r2 8000bd4: 463e mov r6, r7 8000bd6: f04f 0800 mov.w r8, #0 8000bda: eb08 0106 add.w r1, r8, r6 8000bde: eb01 71d1 add.w r1, r1, r1, lsr #31 8000be2: 1049 asrs r1, r1, #1 8000be4: eb04 09c1 add.w r9, r4, r1, lsl #3 8000be8: 4648 mov r0, r9 8000bea: f7ff ffe3 bl 8000bb4 8000bee: 4603 mov r3, r0 8000bf0: 00c8 lsls r0, r1, #3 8000bf2: 3008 adds r0, #8 8000bf4: 428f cmp r7, r1 8000bf6: 4420 add r0, r4 8000bf8: d009 beq.n 8000c0e 8000bfa: 42ab cmp r3, r5 8000bfc: d809 bhi.n 8000c12 8000bfe: f7ff ffd9 bl 8000bb4 8000c02: 3801 subs r0, #1 8000c04: 42a8 cmp r0, r5 8000c06: d20a bcs.n 8000c1e 8000c08: f101 0801 add.w r8, r1, #1 8000c0c: e7e5 b.n 8000bda 8000c0e: 42ab cmp r3, r5 8000c10: d905 bls.n 8000c1e 8000c12: 4588 cmp r8, r1 8000c14: d001 beq.n 8000c1a 8000c16: 1e4e subs r6, r1, #1 8000c18: e7df b.n 8000bda 8000c1a: f04f 0900 mov.w r9, #0 8000c1e: 4648 mov r0, r9 8000c20: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 08000c24 <__gnu_unwind_get_pr_addr>: 8000c24: 2801 cmp r0, #1 8000c26: d007 beq.n 8000c38 <__gnu_unwind_get_pr_addr+0x14> 8000c28: 2802 cmp r0, #2 8000c2a: d007 beq.n 8000c3c <__gnu_unwind_get_pr_addr+0x18> 8000c2c: 4b04 ldr r3, [pc, #16] ; (8000c40 <__gnu_unwind_get_pr_addr+0x1c>) 8000c2e: 2800 cmp r0, #0 8000c30: bf0c ite eq 8000c32: 4618 moveq r0, r3 8000c34: 2000 movne r0, #0 8000c36: 4770 bx lr 8000c38: 4802 ldr r0, [pc, #8] ; (8000c44 <__gnu_unwind_get_pr_addr+0x20>) 8000c3a: 4770 bx lr 8000c3c: 4802 ldr r0, [pc, #8] ; (8000c48 <__gnu_unwind_get_pr_addr+0x24>) 8000c3e: 4770 bx lr 8000c40: 080012f9 .word 0x080012f9 8000c44: 080012fd .word 0x080012fd 8000c48: 08001301 .word 0x08001301 08000c4c : 8000c4c: b530 push {r4, r5, lr} 8000c4e: 4b22 ldr r3, [pc, #136] ; (8000cd8 ) 8000c50: b083 sub sp, #12 8000c52: 4604 mov r4, r0 8000c54: 1e8d subs r5, r1, #2 8000c56: b343 cbz r3, 8000caa 8000c58: a901 add r1, sp, #4 8000c5a: 4628 mov r0, r5 8000c5c: f3af 8000 nop.w 8000c60: b1f0 cbz r0, 8000ca0 8000c62: 9901 ldr r1, [sp, #4] 8000c64: 462a mov r2, r5 8000c66: f7ff ffaf bl 8000bc8 8000c6a: 4601 mov r1, r0 8000c6c: b1c0 cbz r0, 8000ca0 8000c6e: f7ff ffa1 bl 8000bb4 8000c72: 684b ldr r3, [r1, #4] 8000c74: 64a0 str r0, [r4, #72] ; 0x48 8000c76: 2b01 cmp r3, #1 8000c78: d02b beq.n 8000cd2 8000c7a: 2b00 cmp r3, #0 8000c7c: f101 0004 add.w r0, r1, #4 8000c80: db25 blt.n 8000cce 8000c82: f7ff ff97 bl 8000bb4 8000c86: 2300 movs r3, #0 8000c88: 6523 str r3, [r4, #80] ; 0x50 8000c8a: 6803 ldr r3, [r0, #0] 8000c8c: 64e0 str r0, [r4, #76] ; 0x4c 8000c8e: 2b00 cmp r3, #0 8000c90: db12 blt.n 8000cb8 8000c92: f7ff ff8f bl 8000bb4 8000c96: 4603 mov r3, r0 8000c98: 2000 movs r0, #0 8000c9a: 6123 str r3, [r4, #16] 8000c9c: b003 add sp, #12 8000c9e: bd30 pop {r4, r5, pc} 8000ca0: 2300 movs r3, #0 8000ca2: 2009 movs r0, #9 8000ca4: 6123 str r3, [r4, #16] 8000ca6: b003 add sp, #12 8000ca8: bd30 pop {r4, r5, pc} 8000caa: 4b0c ldr r3, [pc, #48] ; (8000cdc ) 8000cac: 490c ldr r1, [pc, #48] ; (8000ce0 ) 8000cae: 1ac9 subs r1, r1, r3 8000cb0: 10c9 asrs r1, r1, #3 8000cb2: 4618 mov r0, r3 8000cb4: 9101 str r1, [sp, #4] 8000cb6: e7d5 b.n 8000c64 8000cb8: f3c3 6003 ubfx r0, r3, #24, #4 8000cbc: f7ff ffb2 bl 8000c24 <__gnu_unwind_get_pr_addr> 8000cc0: 1e03 subs r3, r0, #0 8000cc2: bf0c ite eq 8000cc4: 2009 moveq r0, #9 8000cc6: 2000 movne r0, #0 8000cc8: 6123 str r3, [r4, #16] 8000cca: b003 add sp, #12 8000ccc: bd30 pop {r4, r5, pc} 8000cce: 2301 movs r3, #1 8000cd0: e7da b.n 8000c88 8000cd2: 2300 movs r3, #0 8000cd4: 2005 movs r0, #5 8000cd6: e7e0 b.n 8000c9a 8000cd8: 00000000 .word 0x00000000 8000cdc: 08007f3c .word 0x08007f3c 8000ce0: 08008014 .word 0x08008014 08000ce4 : 8000ce4: 6803 ldr r3, [r0, #0] 8000ce6: 07da lsls r2, r3, #31 8000ce8: b510 push {r4, lr} 8000cea: 4604 mov r4, r0 8000cec: d406 bmi.n 8000cfc 8000cee: 079b lsls r3, r3, #30 8000cf0: f100 0048 add.w r0, r0, #72 ; 0x48 8000cf4: d509 bpl.n 8000d0a 8000cf6: f000 fc71 bl 80015dc <__gnu_Unwind_Restore_VFP_D> 8000cfa: 6823 ldr r3, [r4, #0] 8000cfc: 0759 lsls r1, r3, #29 8000cfe: d509 bpl.n 8000d14 8000d00: 071a lsls r2, r3, #28 8000d02: d50e bpl.n 8000d22 8000d04: 06db lsls r3, r3, #27 8000d06: d513 bpl.n 8000d30 8000d08: bd10 pop {r4, pc} 8000d0a: f000 fc5f bl 80015cc <__gnu_Unwind_Restore_VFP> 8000d0e: 6823 ldr r3, [r4, #0] 8000d10: 0759 lsls r1, r3, #29 8000d12: d4f5 bmi.n 8000d00 8000d14: f104 00d0 add.w r0, r4, #208 ; 0xd0 8000d18: f000 fc68 bl 80015ec <__gnu_Unwind_Restore_VFP_D_16_to_31> 8000d1c: 6823 ldr r3, [r4, #0] 8000d1e: 071a lsls r2, r3, #28 8000d20: d4f0 bmi.n 8000d04 8000d22: f504 70a8 add.w r0, r4, #336 ; 0x150 8000d26: f000 fc69 bl 80015fc <__gnu_Unwind_Restore_WMMXD> 8000d2a: 6823 ldr r3, [r4, #0] 8000d2c: 06db lsls r3, r3, #27 8000d2e: d4eb bmi.n 8000d08 8000d30: f504 70e8 add.w r0, r4, #464 ; 0x1d0 8000d34: e8bd 4010 ldmia.w sp!, {r4, lr} 8000d38: f000 bca4 b.w 8001684 <__gnu_Unwind_Restore_WMMXC> 08000d3c <__gnu_unwind_24bit.constprop.0>: 8000d3c: 2009 movs r0, #9 8000d3e: 4770 bx lr 08000d40 <_Unwind_decode_typeinfo_ptr.constprop.0>: 8000d40: 4603 mov r3, r0 8000d42: 6800 ldr r0, [r0, #0] 8000d44: b100 cbz r0, 8000d48 <_Unwind_decode_typeinfo_ptr.constprop.0+0x8> 8000d46: 4418 add r0, r3 8000d48: 4770 bx lr 8000d4a: bf00 nop 08000d4c <_Unwind_DebugHook>: 8000d4c: 4770 bx lr 8000d4e: bf00 nop 08000d50 : 8000d50: b570 push {r4, r5, r6, lr} 8000d52: 4604 mov r4, r0 8000d54: 460e mov r6, r1 8000d56: 6c31 ldr r1, [r6, #64] ; 0x40 8000d58: 4620 mov r0, r4 8000d5a: f7ff ff77 bl 8000c4c 8000d5e: 4605 mov r5, r0 8000d60: b988 cbnz r0, 8000d86 8000d62: 6c32 ldr r2, [r6, #64] ; 0x40 8000d64: 6162 str r2, [r4, #20] 8000d66: 6923 ldr r3, [r4, #16] 8000d68: 4632 mov r2, r6 8000d6a: 4621 mov r1, r4 8000d6c: 2001 movs r0, #1 8000d6e: 4798 blx r3 8000d70: 2808 cmp r0, #8 8000d72: d0f0 beq.n 8000d56 8000d74: 2807 cmp r0, #7 8000d76: d106 bne.n 8000d86 8000d78: 4628 mov r0, r5 8000d7a: 6c31 ldr r1, [r6, #64] ; 0x40 8000d7c: f7ff ffe6 bl 8000d4c <_Unwind_DebugHook> 8000d80: 1d30 adds r0, r6, #4 8000d82: f000 fc17 bl 80015b4 <__restore_core_regs> 8000d86: f005 fb6d bl 8006464 8000d8a: bf00 nop 08000d8c : 8000d8c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000d90: 1d0d adds r5, r1, #4 8000d92: f8d0 800c ldr.w r8, [r0, #12] 8000d96: f8d0 9018 ldr.w r9, [r0, #24] 8000d9a: 4607 mov r7, r0 8000d9c: 4614 mov r4, r2 8000d9e: cd0f ldmia r5!, {r0, r1, r2, r3} 8000da0: f5ad 7d72 sub.w sp, sp, #968 ; 0x3c8 8000da4: f10d 0c0c add.w ip, sp, #12 8000da8: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} 8000dac: cd0f ldmia r5!, {r0, r1, r2, r3} 8000dae: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} 8000db2: cd0f ldmia r5!, {r0, r1, r2, r3} 8000db4: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} 8000db8: e895 000f ldmia.w r5, {r0, r1, r2, r3} 8000dbc: ae02 add r6, sp, #8 8000dbe: f04f 0e00 mov.w lr, #0 8000dc2: e88c 000f stmia.w ip, {r0, r1, r2, r3} 8000dc6: f8c6 e000 str.w lr, [r6] 8000dca: e020 b.n 8000e0e 8000dcc: 6c33 ldr r3, [r6, #64] ; 0x40 8000dce: 617b str r3, [r7, #20] 8000dd0: f44f 72f0 mov.w r2, #480 ; 0x1e0 8000dd4: 4631 mov r1, r6 8000dd6: a87a add r0, sp, #488 ; 0x1e8 8000dd8: f005 fb90 bl 80064fc 8000ddc: 693b ldr r3, [r7, #16] 8000dde: aa7a add r2, sp, #488 ; 0x1e8 8000de0: 4639 mov r1, r7 8000de2: 4650 mov r0, sl 8000de4: 4798 blx r3 8000de6: 9b88 ldr r3, [sp, #544] ; 0x220 8000de8: 6473 str r3, [r6, #68] ; 0x44 8000dea: 4621 mov r1, r4 8000dec: e9cd 6900 strd r6, r9, [sp] 8000df0: 4605 mov r5, r0 8000df2: 463b mov r3, r7 8000df4: 463a mov r2, r7 8000df6: 2001 movs r0, #1 8000df8: 47c0 blx r8 8000dfa: 4604 mov r4, r0 8000dfc: b9e0 cbnz r0, 8000e38 8000dfe: f44f 72f0 mov.w r2, #480 ; 0x1e0 8000e02: a97a add r1, sp, #488 ; 0x1e8 8000e04: 4630 mov r0, r6 8000e06: f005 fb79 bl 80064fc 8000e0a: 2d08 cmp r5, #8 8000e0c: d11a bne.n 8000e44 8000e0e: 6c31 ldr r1, [r6, #64] ; 0x40 8000e10: 4638 mov r0, r7 8000e12: f7ff ff1b bl 8000c4c 8000e16: 3409 adds r4, #9 8000e18: fa5f fa84 uxtb.w sl, r4 8000e1c: 4605 mov r5, r0 8000e1e: 2800 cmp r0, #0 8000e20: d0d4 beq.n 8000dcc 8000e22: 6bb3 ldr r3, [r6, #56] ; 0x38 8000e24: 6473 str r3, [r6, #68] ; 0x44 8000e26: 463a mov r2, r7 8000e28: e9cd 6900 strd r6, r9, [sp] 8000e2c: 463b mov r3, r7 8000e2e: f04a 0110 orr.w r1, sl, #16 8000e32: 2001 movs r0, #1 8000e34: 47c0 blx r8 8000e36: b100 cbz r0, 8000e3a 8000e38: 2509 movs r5, #9 8000e3a: 4628 mov r0, r5 8000e3c: f50d 7d72 add.w sp, sp, #968 ; 0x3c8 8000e40: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000e44: 2d07 cmp r5, #7 8000e46: d1f7 bne.n 8000e38 8000e48: 4620 mov r0, r4 8000e4a: 6c31 ldr r1, [r6, #64] ; 0x40 8000e4c: f7ff ff7e bl 8000d4c <_Unwind_DebugHook> 8000e50: a803 add r0, sp, #12 8000e52: f000 fbaf bl 80015b4 <__restore_core_regs> 8000e56: bf00 nop 08000e58 <_Unwind_GetCFA>: 8000e58: 6c40 ldr r0, [r0, #68] ; 0x44 8000e5a: 4770 bx lr 08000e5c <__gnu_Unwind_RaiseException>: 8000e5c: b5f0 push {r4, r5, r6, r7, lr} 8000e5e: 6bcb ldr r3, [r1, #60] ; 0x3c 8000e60: 640b str r3, [r1, #64] ; 0x40 8000e62: f101 0c04 add.w ip, r1, #4 8000e66: 460e mov r6, r1 8000e68: 4605 mov r5, r0 8000e6a: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} 8000e6e: b0f9 sub sp, #484 ; 0x1e4 8000e70: ac01 add r4, sp, #4 8000e72: c40f stmia r4!, {r0, r1, r2, r3} 8000e74: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} 8000e78: c40f stmia r4!, {r0, r1, r2, r3} 8000e7a: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} 8000e7e: c40f stmia r4!, {r0, r1, r2, r3} 8000e80: e89c 000f ldmia.w ip, {r0, r1, r2, r3} 8000e84: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 8000e88: e884 000f stmia.w r4, {r0, r1, r2, r3} 8000e8c: 9700 str r7, [sp, #0] 8000e8e: e006 b.n 8000e9e <__gnu_Unwind_RaiseException+0x42> 8000e90: 692b ldr r3, [r5, #16] 8000e92: 466a mov r2, sp 8000e94: 4629 mov r1, r5 8000e96: 4798 blx r3 8000e98: 2808 cmp r0, #8 8000e9a: 4604 mov r4, r0 8000e9c: d108 bne.n 8000eb0 <__gnu_Unwind_RaiseException+0x54> 8000e9e: 9910 ldr r1, [sp, #64] ; 0x40 8000ea0: 4628 mov r0, r5 8000ea2: f7ff fed3 bl 8000c4c 8000ea6: 2800 cmp r0, #0 8000ea8: d0f2 beq.n 8000e90 <__gnu_Unwind_RaiseException+0x34> 8000eaa: 2009 movs r0, #9 8000eac: b079 add sp, #484 ; 0x1e4 8000eae: bdf0 pop {r4, r5, r6, r7, pc} 8000eb0: 4668 mov r0, sp 8000eb2: f7ff ff17 bl 8000ce4 8000eb6: 2c06 cmp r4, #6 8000eb8: d1f7 bne.n 8000eaa <__gnu_Unwind_RaiseException+0x4e> 8000eba: 4631 mov r1, r6 8000ebc: 4628 mov r0, r5 8000ebe: f7ff ff47 bl 8000d50 8000ec2: bf00 nop 08000ec4 <__gnu_Unwind_ForcedUnwind>: 8000ec4: 60c1 str r1, [r0, #12] 8000ec6: 6bd9 ldr r1, [r3, #60] ; 0x3c 8000ec8: 6182 str r2, [r0, #24] 8000eca: 6419 str r1, [r3, #64] ; 0x40 8000ecc: 2200 movs r2, #0 8000ece: 4619 mov r1, r3 8000ed0: e75c b.n 8000d8c 8000ed2: bf00 nop 08000ed4 <__gnu_Unwind_Resume>: 8000ed4: b570 push {r4, r5, r6, lr} 8000ed6: 68c6 ldr r6, [r0, #12] 8000ed8: 6943 ldr r3, [r0, #20] 8000eda: 640b str r3, [r1, #64] ; 0x40 8000edc: b9ae cbnz r6, 8000f0a <__gnu_Unwind_Resume+0x36> 8000ede: 6903 ldr r3, [r0, #16] 8000ee0: 460a mov r2, r1 8000ee2: 4604 mov r4, r0 8000ee4: 460d mov r5, r1 8000ee6: 4601 mov r1, r0 8000ee8: 2002 movs r0, #2 8000eea: 4798 blx r3 8000eec: 2807 cmp r0, #7 8000eee: d005 beq.n 8000efc <__gnu_Unwind_Resume+0x28> 8000ef0: 2808 cmp r0, #8 8000ef2: d10f bne.n 8000f14 <__gnu_Unwind_Resume+0x40> 8000ef4: 4629 mov r1, r5 8000ef6: 4620 mov r0, r4 8000ef8: f7ff ff2a bl 8000d50 8000efc: 4630 mov r0, r6 8000efe: 6c29 ldr r1, [r5, #64] ; 0x40 8000f00: f7ff ff24 bl 8000d4c <_Unwind_DebugHook> 8000f04: 1d28 adds r0, r5, #4 8000f06: f000 fb55 bl 80015b4 <__restore_core_regs> 8000f0a: 2201 movs r2, #1 8000f0c: f7ff ff3e bl 8000d8c 8000f10: f005 faa8 bl 8006464 8000f14: f005 faa6 bl 8006464 08000f18 <__gnu_Unwind_Resume_or_Rethrow>: 8000f18: 68c2 ldr r2, [r0, #12] 8000f1a: b11a cbz r2, 8000f24 <__gnu_Unwind_Resume_or_Rethrow+0xc> 8000f1c: 6bca ldr r2, [r1, #60] ; 0x3c 8000f1e: 640a str r2, [r1, #64] ; 0x40 8000f20: 2200 movs r2, #0 8000f22: e733 b.n 8000d8c 8000f24: e79a b.n 8000e5c <__gnu_Unwind_RaiseException> 8000f26: bf00 nop 08000f28 <_Unwind_Complete>: 8000f28: 4770 bx lr 8000f2a: bf00 nop 08000f2c <_Unwind_DeleteException>: 8000f2c: 6883 ldr r3, [r0, #8] 8000f2e: 4601 mov r1, r0 8000f30: b10b cbz r3, 8000f36 <_Unwind_DeleteException+0xa> 8000f32: 2001 movs r0, #1 8000f34: 4718 bx r3 8000f36: 4770 bx lr 08000f38 <_Unwind_VRS_Get>: 8000f38: 2901 cmp r1, #1 8000f3a: d012 beq.n 8000f62 <_Unwind_VRS_Get+0x2a> 8000f3c: d809 bhi.n 8000f52 <_Unwind_VRS_Get+0x1a> 8000f3e: b973 cbnz r3, 8000f5e <_Unwind_VRS_Get+0x26> 8000f40: 2a0f cmp r2, #15 8000f42: d80c bhi.n 8000f5e <_Unwind_VRS_Get+0x26> 8000f44: eb00 0282 add.w r2, r0, r2, lsl #2 8000f48: 4618 mov r0, r3 8000f4a: 6853 ldr r3, [r2, #4] 8000f4c: 9a00 ldr r2, [sp, #0] 8000f4e: 6013 str r3, [r2, #0] 8000f50: 4770 bx lr 8000f52: 3903 subs r1, #3 8000f54: 2901 cmp r1, #1 8000f56: bf94 ite ls 8000f58: 2001 movls r0, #1 8000f5a: 2002 movhi r0, #2 8000f5c: 4770 bx lr 8000f5e: 2002 movs r0, #2 8000f60: 4770 bx lr 8000f62: 4608 mov r0, r1 8000f64: 4770 bx lr 8000f66: bf00 nop 08000f68 <_Unwind_GetGR>: 8000f68: b500 push {lr} 8000f6a: b085 sub sp, #20 8000f6c: 460a mov r2, r1 8000f6e: 2300 movs r3, #0 8000f70: a903 add r1, sp, #12 8000f72: 9100 str r1, [sp, #0] 8000f74: 4619 mov r1, r3 8000f76: f7ff ffdf bl 8000f38 <_Unwind_VRS_Get> 8000f7a: 9803 ldr r0, [sp, #12] 8000f7c: b005 add sp, #20 8000f7e: f85d fb04 ldr.w pc, [sp], #4 8000f82: bf00 nop 08000f84 <_Unwind_VRS_Set>: 8000f84: 2901 cmp r1, #1 8000f86: d012 beq.n 8000fae <_Unwind_VRS_Set+0x2a> 8000f88: d809 bhi.n 8000f9e <_Unwind_VRS_Set+0x1a> 8000f8a: b973 cbnz r3, 8000faa <_Unwind_VRS_Set+0x26> 8000f8c: 2a0f cmp r2, #15 8000f8e: d80c bhi.n 8000faa <_Unwind_VRS_Set+0x26> 8000f90: 9900 ldr r1, [sp, #0] 8000f92: eb00 0282 add.w r2, r0, r2, lsl #2 8000f96: 6809 ldr r1, [r1, #0] 8000f98: 6051 str r1, [r2, #4] 8000f9a: 4618 mov r0, r3 8000f9c: 4770 bx lr 8000f9e: 3903 subs r1, #3 8000fa0: 2901 cmp r1, #1 8000fa2: bf94 ite ls 8000fa4: 2001 movls r0, #1 8000fa6: 2002 movhi r0, #2 8000fa8: 4770 bx lr 8000faa: 2002 movs r0, #2 8000fac: 4770 bx lr 8000fae: 4608 mov r0, r1 8000fb0: 4770 bx lr 8000fb2: bf00 nop 08000fb4 <_Unwind_SetGR>: 8000fb4: b510 push {r4, lr} 8000fb6: b084 sub sp, #16 8000fb8: 2300 movs r3, #0 8000fba: ac03 add r4, sp, #12 8000fbc: 9203 str r2, [sp, #12] 8000fbe: 9400 str r4, [sp, #0] 8000fc0: 460a mov r2, r1 8000fc2: 4619 mov r1, r3 8000fc4: f7ff ffde bl 8000f84 <_Unwind_VRS_Set> 8000fc8: b004 add sp, #16 8000fca: bd10 pop {r4, pc} 08000fcc <__gnu_Unwind_Backtrace>: 8000fcc: b570 push {r4, r5, r6, lr} 8000fce: 6bd3 ldr r3, [r2, #60] ; 0x3c 8000fd0: 6413 str r3, [r2, #64] ; 0x40 8000fd2: f102 0c04 add.w ip, r2, #4 8000fd6: 4605 mov r5, r0 8000fd8: 460c mov r4, r1 8000fda: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} 8000fde: f5ad 7d0e sub.w sp, sp, #568 ; 0x238 8000fe2: f10d 0e5c add.w lr, sp, #92 ; 0x5c 8000fe6: e8ae 000f stmia.w lr!, {r0, r1, r2, r3} 8000fea: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} 8000fee: e8ae 000f stmia.w lr!, {r0, r1, r2, r3} 8000ff2: e8bc 000f ldmia.w ip!, {r0, r1, r2, r3} 8000ff6: e8ae 000f stmia.w lr!, {r0, r1, r2, r3} 8000ffa: e89c 000f ldmia.w ip, {r0, r1, r2, r3} 8000ffe: f04f 36ff mov.w r6, #4294967295 ; 0xffffffff 8001002: e88e 000f stmia.w lr, {r0, r1, r2, r3} 8001006: 9616 str r6, [sp, #88] ; 0x58 8001008: e010 b.n 800102c <__gnu_Unwind_Backtrace+0x60> 800100a: f7ff ffd3 bl 8000fb4 <_Unwind_SetGR> 800100e: 4621 mov r1, r4 8001010: a816 add r0, sp, #88 ; 0x58 8001012: 47a8 blx r5 8001014: 4603 mov r3, r0 8001016: aa16 add r2, sp, #88 ; 0x58 8001018: 4669 mov r1, sp 800101a: 2008 movs r0, #8 800101c: b983 cbnz r3, 8001040 <__gnu_Unwind_Backtrace+0x74> 800101e: 9b04 ldr r3, [sp, #16] 8001020: 4798 blx r3 8001022: 2805 cmp r0, #5 8001024: 4606 mov r6, r0 8001026: d00c beq.n 8001042 <__gnu_Unwind_Backtrace+0x76> 8001028: 2809 cmp r0, #9 800102a: d009 beq.n 8001040 <__gnu_Unwind_Backtrace+0x74> 800102c: 9926 ldr r1, [sp, #152] ; 0x98 800102e: 4668 mov r0, sp 8001030: f7ff fe0c bl 8000c4c 8001034: 4603 mov r3, r0 8001036: 466a mov r2, sp 8001038: 210c movs r1, #12 800103a: a816 add r0, sp, #88 ; 0x58 800103c: 2b00 cmp r3, #0 800103e: d0e4 beq.n 800100a <__gnu_Unwind_Backtrace+0x3e> 8001040: 2609 movs r6, #9 8001042: a816 add r0, sp, #88 ; 0x58 8001044: f7ff fe4e bl 8000ce4 8001048: 4630 mov r0, r6 800104a: f50d 7d0e add.w sp, sp, #568 ; 0x238 800104e: bd70 pop {r4, r5, r6, pc} 08001050 <__gnu_unwind_pr_common>: 8001050: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8001054: 6ccc ldr r4, [r1, #76] ; 0x4c 8001056: b089 sub sp, #36 ; 0x24 8001058: 461e mov r6, r3 800105a: f854 3b04 ldr.w r3, [r4], #4 800105e: 9406 str r4, [sp, #24] 8001060: 460d mov r5, r1 8001062: 4617 mov r7, r2 8001064: f000 0803 and.w r8, r0, #3 8001068: 2e00 cmp r6, #0 800106a: d079 beq.n 8001160 <__gnu_unwind_pr_common+0x110> 800106c: 0c1a lsrs r2, r3, #16 800106e: f88d 201d strb.w r2, [sp, #29] 8001072: 041b lsls r3, r3, #16 8001074: b2d2 uxtb r2, r2 8001076: 9305 str r3, [sp, #20] 8001078: eb04 0482 add.w r4, r4, r2, lsl #2 800107c: 2302 movs r3, #2 800107e: f88d 301c strb.w r3, [sp, #28] 8001082: 6d2b ldr r3, [r5, #80] ; 0x50 8001084: f1b8 0f02 cmp.w r8, #2 8001088: bf08 it eq 800108a: 6bac ldreq r4, [r5, #56] ; 0x38 800108c: f013 0301 ands.w r3, r3, #1 8001090: d00c beq.n 80010ac <__gnu_unwind_pr_common+0x5c> 8001092: a905 add r1, sp, #20 8001094: 4638 mov r0, r7 8001096: f000 fb8f bl 80017b8 <__gnu_unwind_execute> 800109a: b918 cbnz r0, 80010a4 <__gnu_unwind_pr_common+0x54> 800109c: 2008 movs r0, #8 800109e: b009 add sp, #36 ; 0x24 80010a0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80010a4: 2009 movs r0, #9 80010a6: b009 add sp, #36 ; 0x24 80010a8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80010ac: f8d4 a000 ldr.w sl, [r4] 80010b0: f1ba 0f00 cmp.w sl, #0 80010b4: d0ed beq.n 8001092 <__gnu_unwind_pr_common+0x42> 80010b6: 9301 str r3, [sp, #4] 80010b8: f000 0308 and.w r3, r0, #8 80010bc: 9302 str r3, [sp, #8] 80010be: 2e02 cmp r6, #2 80010c0: d04a beq.n 8001158 <__gnu_unwind_pr_common+0x108> 80010c2: f8b4 a000 ldrh.w sl, [r4] 80010c6: f8b4 9002 ldrh.w r9, [r4, #2] 80010ca: 3404 adds r4, #4 80010cc: 6cab ldr r3, [r5, #72] ; 0x48 80010ce: f029 0b01 bic.w fp, r9, #1 80010d2: 210f movs r1, #15 80010d4: 4638 mov r0, r7 80010d6: 449b add fp, r3 80010d8: f7ff ff46 bl 8000f68 <_Unwind_GetGR> 80010dc: 4583 cmp fp, r0 80010de: d839 bhi.n 8001154 <__gnu_unwind_pr_common+0x104> 80010e0: f02a 0201 bic.w r2, sl, #1 80010e4: 445a add r2, fp 80010e6: 4282 cmp r2, r0 80010e8: bf94 ite ls 80010ea: 2200 movls r2, #0 80010ec: 2201 movhi r2, #1 80010ee: ea4f 0349 mov.w r3, r9, lsl #1 80010f2: f003 0302 and.w r3, r3, #2 80010f6: f00a 0a01 and.w sl, sl, #1 80010fa: ea43 030a orr.w r3, r3, sl 80010fe: 2b01 cmp r3, #1 8001100: d04b beq.n 800119a <__gnu_unwind_pr_common+0x14a> 8001102: 2b02 cmp r3, #2 8001104: d032 beq.n 800116c <__gnu_unwind_pr_common+0x11c> 8001106: 2b00 cmp r3, #0 8001108: d1cc bne.n 80010a4 <__gnu_unwind_pr_common+0x54> 800110a: f1b8 0f00 cmp.w r8, #0 800110e: d002 beq.n 8001116 <__gnu_unwind_pr_common+0xc6> 8001110: 2a00 cmp r2, #0 8001112: f040 80cd bne.w 80012b0 <__gnu_unwind_pr_common+0x260> 8001116: 3404 adds r4, #4 8001118: f8d4 a000 ldr.w sl, [r4] 800111c: f1ba 0f00 cmp.w sl, #0 8001120: d1cd bne.n 80010be <__gnu_unwind_pr_common+0x6e> 8001122: a905 add r1, sp, #20 8001124: 4638 mov r0, r7 8001126: f000 fb47 bl 80017b8 <__gnu_unwind_execute> 800112a: 2800 cmp r0, #0 800112c: d1ba bne.n 80010a4 <__gnu_unwind_pr_common+0x54> 800112e: 9b01 ldr r3, [sp, #4] 8001130: 2b00 cmp r3, #0 8001132: d0b3 beq.n 800109c <__gnu_unwind_pr_common+0x4c> 8001134: 210f movs r1, #15 8001136: 4638 mov r0, r7 8001138: f7ff ff16 bl 8000f68 <_Unwind_GetGR> 800113c: 210e movs r1, #14 800113e: 4602 mov r2, r0 8001140: 4638 mov r0, r7 8001142: f7ff ff37 bl 8000fb4 <_Unwind_SetGR> 8001146: 4638 mov r0, r7 8001148: 4a6a ldr r2, [pc, #424] ; (80012f4 <__gnu_unwind_pr_common+0x2a4>) 800114a: 210f movs r1, #15 800114c: f7ff ff32 bl 8000fb4 <_Unwind_SetGR> 8001150: 2007 movs r0, #7 8001152: e7a8 b.n 80010a6 <__gnu_unwind_pr_common+0x56> 8001154: 2200 movs r2, #0 8001156: e7ca b.n 80010ee <__gnu_unwind_pr_common+0x9e> 8001158: f8d4 9004 ldr.w r9, [r4, #4] 800115c: 3408 adds r4, #8 800115e: e7b5 b.n 80010cc <__gnu_unwind_pr_common+0x7c> 8001160: 021b lsls r3, r3, #8 8001162: 9305 str r3, [sp, #20] 8001164: f88d 601d strb.w r6, [sp, #29] 8001168: 2303 movs r3, #3 800116a: e788 b.n 800107e <__gnu_unwind_pr_common+0x2e> 800116c: f8d4 9000 ldr.w r9, [r4] 8001170: f029 4b00 bic.w fp, r9, #2147483648 ; 0x80000000 8001174: f1b8 0f00 cmp.w r8, #0 8001178: d146 bne.n 8001208 <__gnu_unwind_pr_common+0x1b8> 800117a: b12a cbz r2, 8001188 <__gnu_unwind_pr_common+0x138> 800117c: 9b02 ldr r3, [sp, #8] 800117e: 2b00 cmp r3, #0 8001180: d05b beq.n 800123a <__gnu_unwind_pr_common+0x1ea> 8001182: f1bb 0f00 cmp.w fp, #0 8001186: d073 beq.n 8001270 <__gnu_unwind_pr_common+0x220> 8001188: f1b9 0f00 cmp.w r9, #0 800118c: da00 bge.n 8001190 <__gnu_unwind_pr_common+0x140> 800118e: 3404 adds r4, #4 8001190: f10b 0b01 add.w fp, fp, #1 8001194: eb04 048b add.w r4, r4, fp, lsl #2 8001198: e7be b.n 8001118 <__gnu_unwind_pr_common+0xc8> 800119a: f1b8 0f00 cmp.w r8, #0 800119e: d119 bne.n 80011d4 <__gnu_unwind_pr_common+0x184> 80011a0: b1b2 cbz r2, 80011d0 <__gnu_unwind_pr_common+0x180> 80011a2: 6861 ldr r1, [r4, #4] 80011a4: 6822 ldr r2, [r4, #0] 80011a6: 1c88 adds r0, r1, #2 80011a8: ea4f 72d2 mov.w r2, r2, lsr #31 80011ac: f43f af7a beq.w 80010a4 <__gnu_unwind_pr_common+0x54> 80011b0: f105 0358 add.w r3, r5, #88 ; 0x58 80011b4: 3101 adds r1, #1 80011b6: 9304 str r3, [sp, #16] 80011b8: f000 808e beq.w 80012d8 <__gnu_unwind_pr_common+0x288> 80011bc: 1d20 adds r0, r4, #4 80011be: f7ff fdbf bl 8000d40 <_Unwind_decode_typeinfo_ptr.constprop.0> 80011c2: ab04 add r3, sp, #16 80011c4: 4601 mov r1, r0 80011c6: 4628 mov r0, r5 80011c8: f3af 8000 nop.w 80011cc: 2800 cmp r0, #0 80011ce: d159 bne.n 8001284 <__gnu_unwind_pr_common+0x234> 80011d0: 3408 adds r4, #8 80011d2: e7a1 b.n 8001118 <__gnu_unwind_pr_common+0xc8> 80011d4: 210d movs r1, #13 80011d6: 4638 mov r0, r7 80011d8: f8d5 9020 ldr.w r9, [r5, #32] 80011dc: f7ff fec4 bl 8000f68 <_Unwind_GetGR> 80011e0: 4581 cmp r9, r0 80011e2: d1f5 bne.n 80011d0 <__gnu_unwind_pr_common+0x180> 80011e4: 6aab ldr r3, [r5, #40] ; 0x28 80011e6: 429c cmp r4, r3 80011e8: d1f2 bne.n 80011d0 <__gnu_unwind_pr_common+0x180> 80011ea: 4620 mov r0, r4 80011ec: f7ff fce2 bl 8000bb4 80011f0: 210f movs r1, #15 80011f2: 4602 mov r2, r0 80011f4: 4638 mov r0, r7 80011f6: f7ff fedd bl 8000fb4 <_Unwind_SetGR> 80011fa: 4638 mov r0, r7 80011fc: 462a mov r2, r5 80011fe: 2100 movs r1, #0 8001200: f7ff fed8 bl 8000fb4 <_Unwind_SetGR> 8001204: 2007 movs r0, #7 8001206: e74e b.n 80010a6 <__gnu_unwind_pr_common+0x56> 8001208: 210d movs r1, #13 800120a: 4638 mov r0, r7 800120c: f8d5 a020 ldr.w sl, [r5, #32] 8001210: f7ff feaa bl 8000f68 <_Unwind_GetGR> 8001214: 4582 cmp sl, r0 8001216: d1b7 bne.n 8001188 <__gnu_unwind_pr_common+0x138> 8001218: 6aab ldr r3, [r5, #40] ; 0x28 800121a: 429c cmp r4, r3 800121c: d1b4 bne.n 8001188 <__gnu_unwind_pr_common+0x138> 800121e: 2304 movs r3, #4 8001220: 2200 movs r2, #0 8001222: e9c5 230b strd r2, r3, [r5, #44] ; 0x2c 8001226: 18e3 adds r3, r4, r3 8001228: f8c5 b028 str.w fp, [r5, #40] ; 0x28 800122c: 636b str r3, [r5, #52] ; 0x34 800122e: 6823 ldr r3, [r4, #0] 8001230: 2b00 cmp r3, #0 8001232: db59 blt.n 80012e8 <__gnu_unwind_pr_common+0x298> 8001234: 2301 movs r3, #1 8001236: 9301 str r3, [sp, #4] 8001238: e7aa b.n 8001190 <__gnu_unwind_pr_common+0x140> 800123a: 4699 mov r9, r3 800123c: f105 0358 add.w r3, r5, #88 ; 0x58 8001240: f8cd 800c str.w r8, [sp, #12] 8001244: f104 0a04 add.w sl, r4, #4 8001248: 46b0 mov r8, r6 800124a: 461e mov r6, r3 800124c: e00e b.n 800126c <__gnu_unwind_pr_common+0x21c> 800124e: 4650 mov r0, sl 8001250: 9604 str r6, [sp, #16] 8001252: f7ff fd75 bl 8000d40 <_Unwind_decode_typeinfo_ptr.constprop.0> 8001256: 2200 movs r2, #0 8001258: 4601 mov r1, r0 800125a: ab04 add r3, sp, #16 800125c: 4628 mov r0, r5 800125e: f109 0901 add.w r9, r9, #1 8001262: f10a 0a04 add.w sl, sl, #4 8001266: f3af 8000 nop.w 800126a: b9d8 cbnz r0, 80012a4 <__gnu_unwind_pr_common+0x254> 800126c: 45d9 cmp r9, fp 800126e: d1ee bne.n 800124e <__gnu_unwind_pr_common+0x1fe> 8001270: 210d movs r1, #13 8001272: 4638 mov r0, r7 8001274: f7ff fe78 bl 8000f68 <_Unwind_GetGR> 8001278: 9b04 ldr r3, [sp, #16] 800127a: 6228 str r0, [r5, #32] 800127c: e9c5 3409 strd r3, r4, [r5, #36] ; 0x24 8001280: 2006 movs r0, #6 8001282: e710 b.n 80010a6 <__gnu_unwind_pr_common+0x56> 8001284: 4681 mov r9, r0 8001286: 210d movs r1, #13 8001288: 4638 mov r0, r7 800128a: f7ff fe6d bl 8000f68 <_Unwind_GetGR> 800128e: f1b9 0f02 cmp.w r9, #2 8001292: bf04 itt eq 8001294: 462b moveq r3, r5 8001296: 9a04 ldreq r2, [sp, #16] 8001298: 6228 str r0, [r5, #32] 800129a: bf14 ite ne 800129c: 9b04 ldrne r3, [sp, #16] 800129e: f843 2f2c streq.w r2, [r3, #44]! 80012a2: e7eb b.n 800127c <__gnu_unwind_pr_common+0x22c> 80012a4: 4646 mov r6, r8 80012a6: f8d4 9000 ldr.w r9, [r4] 80012aa: f8dd 800c ldr.w r8, [sp, #12] 80012ae: e76b b.n 8001188 <__gnu_unwind_pr_common+0x138> 80012b0: 4620 mov r0, r4 80012b2: f7ff fc7f bl 8000bb4 80012b6: 3404 adds r4, #4 80012b8: 4602 mov r2, r0 80012ba: 63ac str r4, [r5, #56] ; 0x38 80012bc: 4628 mov r0, r5 80012be: 4614 mov r4, r2 80012c0: f3af 8000 nop.w 80012c4: 2800 cmp r0, #0 80012c6: f43f aeed beq.w 80010a4 <__gnu_unwind_pr_common+0x54> 80012ca: 4638 mov r0, r7 80012cc: 4622 mov r2, r4 80012ce: 210f movs r1, #15 80012d0: f7ff fe70 bl 8000fb4 <_Unwind_SetGR> 80012d4: 2007 movs r0, #7 80012d6: e6e6 b.n 80010a6 <__gnu_unwind_pr_common+0x56> 80012d8: 210d movs r1, #13 80012da: 4638 mov r0, r7 80012dc: 9301 str r3, [sp, #4] 80012de: f7ff fe43 bl 8000f68 <_Unwind_GetGR> 80012e2: 9b01 ldr r3, [sp, #4] 80012e4: 6228 str r0, [r5, #32] 80012e6: e7c9 b.n 800127c <__gnu_unwind_pr_common+0x22c> 80012e8: f10b 0001 add.w r0, fp, #1 80012ec: eb04 0080 add.w r0, r4, r0, lsl #2 80012f0: e77c b.n 80011ec <__gnu_unwind_pr_common+0x19c> 80012f2: bf00 nop 80012f4: 00000000 .word 0x00000000 080012f8 <__aeabi_unwind_cpp_pr0>: 80012f8: 2300 movs r3, #0 80012fa: e6a9 b.n 8001050 <__gnu_unwind_pr_common> 080012fc <__aeabi_unwind_cpp_pr1>: 80012fc: 2301 movs r3, #1 80012fe: e6a7 b.n 8001050 <__gnu_unwind_pr_common> 08001300 <__aeabi_unwind_cpp_pr2>: 8001300: 2302 movs r3, #2 8001302: e6a5 b.n 8001050 <__gnu_unwind_pr_common> 08001304 <_Unwind_VRS_Pop>: 8001304: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 8001308: 4606 mov r6, r0 800130a: b0c3 sub sp, #268 ; 0x10c 800130c: 4691 mov r9, r2 800130e: 461c mov r4, r3 8001310: 2904 cmp r1, #4 8001312: f200 809b bhi.w 800144c <_Unwind_VRS_Pop+0x148> 8001316: e8df f001 tbb [pc, r1] 800131a: 567b .short 0x567b 800131c: 2e99 .short 0x2e99 800131e: 03 .byte 0x03 800131f: 00 .byte 0x00 8001320: 2c00 cmp r4, #0 8001322: f040 8093 bne.w 800144c <_Unwind_VRS_Pop+0x148> 8001326: 2a10 cmp r2, #16 8001328: f200 8090 bhi.w 800144c <_Unwind_VRS_Pop+0x148> 800132c: 6803 ldr r3, [r0, #0] 800132e: 06dc lsls r4, r3, #27 8001330: f100 80f3 bmi.w 800151a <_Unwind_VRS_Pop+0x216> 8001334: af20 add r7, sp, #128 ; 0x80 8001336: 4638 mov r0, r7 8001338: f000 f9ae bl 8001698 <__gnu_Unwind_Save_WMMXC> 800133c: 6bb4 ldr r4, [r6, #56] ; 0x38 800133e: 4639 mov r1, r7 8001340: 2300 movs r3, #0 8001342: f04f 0c01 mov.w ip, #1 8001346: fa0c f203 lsl.w r2, ip, r3 800134a: ea12 0f09 tst.w r2, r9 800134e: 4620 mov r0, r4 8001350: f103 0301 add.w r3, r3, #1 8001354: d003 beq.n 800135e <_Unwind_VRS_Pop+0x5a> 8001356: f850 2b04 ldr.w r2, [r0], #4 800135a: 600a str r2, [r1, #0] 800135c: 4604 mov r4, r0 800135e: 2b04 cmp r3, #4 8001360: f101 0104 add.w r1, r1, #4 8001364: d1ef bne.n 8001346 <_Unwind_VRS_Pop+0x42> 8001366: 4638 mov r0, r7 8001368: 63b4 str r4, [r6, #56] ; 0x38 800136a: f000 f98b bl 8001684 <__gnu_Unwind_Restore_WMMXC> 800136e: 2000 movs r0, #0 8001370: b043 add sp, #268 ; 0x10c 8001372: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8001376: 2c03 cmp r4, #3 8001378: d168 bne.n 800144c <_Unwind_VRS_Pop+0x148> 800137a: b294 uxth r4, r2 800137c: eb04 4312 add.w r3, r4, r2, lsr #16 8001380: 2b10 cmp r3, #16 8001382: ea4f 4912 mov.w r9, r2, lsr #16 8001386: d861 bhi.n 800144c <_Unwind_VRS_Pop+0x148> 8001388: 6803 ldr r3, [r0, #0] 800138a: 071d lsls r5, r3, #28 800138c: f100 80cd bmi.w 800152a <_Unwind_VRS_Pop+0x226> 8001390: af20 add r7, sp, #128 ; 0x80 8001392: 4638 mov r0, r7 8001394: f000 f954 bl 8001640 <__gnu_Unwind_Save_WMMXD> 8001398: 6bb2 ldr r2, [r6, #56] ; 0x38 800139a: eb07 01c9 add.w r1, r7, r9, lsl #3 800139e: b154 cbz r4, 80013b6 <_Unwind_VRS_Pop+0xb2> 80013a0: 460b mov r3, r1 80013a2: 1ad0 subs r0, r2, r3 80013a4: eb01 01c4 add.w r1, r1, r4, lsl #3 80013a8: 00e4 lsls r4, r4, #3 80013aa: 581d ldr r5, [r3, r0] 80013ac: f843 5b04 str.w r5, [r3], #4 80013b0: 428b cmp r3, r1 80013b2: d1fa bne.n 80013aa <_Unwind_VRS_Pop+0xa6> 80013b4: 4422 add r2, r4 80013b6: 4638 mov r0, r7 80013b8: 63b2 str r2, [r6, #56] ; 0x38 80013ba: f000 f91f bl 80015fc <__gnu_Unwind_Restore_WMMXD> 80013be: 2000 movs r0, #0 80013c0: b043 add sp, #268 ; 0x10c 80013c2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 80013c6: 2c01 cmp r4, #1 80013c8: ea4f 4812 mov.w r8, r2, lsr #16 80013cc: fa1f f982 uxth.w r9, r2 80013d0: d038 beq.n 8001444 <_Unwind_VRS_Pop+0x140> 80013d2: 2c05 cmp r4, #5 80013d4: d13a bne.n 800144c <_Unwind_VRS_Pop+0x148> 80013d6: eb08 0309 add.w r3, r8, r9 80013da: 2b20 cmp r3, #32 80013dc: d836 bhi.n 800144c <_Unwind_VRS_Pop+0x148> 80013de: f1b8 0f0f cmp.w r8, #15 80013e2: d976 bls.n 80014d2 <_Unwind_VRS_Pop+0x1ce> 80013e4: f1b9 0f00 cmp.w r9, #0 80013e8: f040 8083 bne.w 80014f2 <_Unwind_VRS_Pop+0x1ee> 80013ec: 2b0f cmp r3, #15 80013ee: d80b bhi.n 8001408 <_Unwind_VRS_Pop+0x104> 80013f0: 6833 ldr r3, [r6, #0] 80013f2: 07d8 lsls r0, r3, #31 80013f4: d508 bpl.n 8001408 <_Unwind_VRS_Pop+0x104> 80013f6: 4630 mov r0, r6 80013f8: f023 0301 bic.w r3, r3, #1 80013fc: f043 0302 orr.w r3, r3, #2 8001400: f840 3b48 str.w r3, [r0], #72 8001404: f000 f8ee bl 80015e4 <__gnu_Unwind_Save_VFP_D> 8001408: 2000 movs r0, #0 800140a: b043 add sp, #268 ; 0x10c 800140c: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8001410: b9e4 cbnz r4, 800144c <_Unwind_VRS_Pop+0x148> 8001412: 6b87 ldr r7, [r0, #56] ; 0x38 8001414: 4623 mov r3, r4 8001416: fa1f fc82 uxth.w ip, r2 800141a: 2001 movs r0, #1 800141c: 1d34 adds r4, r6, #4 800141e: fa00 f203 lsl.w r2, r0, r3 8001422: ea12 0f0c tst.w r2, ip 8001426: 4639 mov r1, r7 8001428: d004 beq.n 8001434 <_Unwind_VRS_Pop+0x130> 800142a: f851 2b04 ldr.w r2, [r1], #4 800142e: f844 2023 str.w r2, [r4, r3, lsl #2] 8001432: 460f mov r7, r1 8001434: 3301 adds r3, #1 8001436: 2b10 cmp r3, #16 8001438: d1f1 bne.n 800141e <_Unwind_VRS_Pop+0x11a> 800143a: f419 5000 ands.w r0, r9, #8192 ; 0x2000 800143e: d1e3 bne.n 8001408 <_Unwind_VRS_Pop+0x104> 8001440: 63b7 str r7, [r6, #56] ; 0x38 8001442: e004 b.n 800144e <_Unwind_VRS_Pop+0x14a> 8001444: eb08 0309 add.w r3, r8, r9 8001448: 2b10 cmp r3, #16 800144a: d903 bls.n 8001454 <_Unwind_VRS_Pop+0x150> 800144c: 2002 movs r0, #2 800144e: b043 add sp, #268 ; 0x10c 8001450: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8001454: f1b8 0f0f cmp.w r8, #15 8001458: d8f8 bhi.n 800144c <_Unwind_VRS_Pop+0x148> 800145a: 6833 ldr r3, [r6, #0] 800145c: 07da lsls r2, r3, #31 800145e: d506 bpl.n 800146e <_Unwind_VRS_Pop+0x16a> 8001460: 4630 mov r0, r6 8001462: f023 0303 bic.w r3, r3, #3 8001466: f840 3b48 str.w r3, [r0], #72 800146a: f000 f8b3 bl 80015d4 <__gnu_Unwind_Save_VFP> 800146e: af20 add r7, sp, #128 ; 0x80 8001470: 4638 mov r0, r7 8001472: 464d mov r5, r9 8001474: f000 f8ae bl 80015d4 <__gnu_Unwind_Save_VFP> 8001478: 6bb2 ldr r2, [r6, #56] ; 0x38 800147a: 2d00 cmp r5, #0 800147c: d05e beq.n 800153c <_Unwind_VRS_Pop+0x238> 800147e: f04f 0900 mov.w r9, #0 8001482: eb07 01c8 add.w r1, r7, r8, lsl #3 8001486: eb02 03c5 add.w r3, r2, r5, lsl #3 800148a: 3904 subs r1, #4 800148c: f852 0b04 ldr.w r0, [r2], #4 8001490: f841 0f04 str.w r0, [r1, #4]! 8001494: 429a cmp r2, r3 8001496: d1f9 bne.n 800148c <_Unwind_VRS_Pop+0x188> 8001498: f1b9 0f00 cmp.w r9, #0 800149c: d054 beq.n 8001548 <_Unwind_VRS_Pop+0x244> 800149e: 466f mov r7, sp 80014a0: 4641 mov r1, r8 80014a2: 2910 cmp r1, #16 80014a4: bf38 it cc 80014a6: 2110 movcc r1, #16 80014a8: eb07 01c1 add.w r1, r7, r1, lsl #3 80014ac: 3984 subs r1, #132 ; 0x84 80014ae: eb03 02c9 add.w r2, r3, r9, lsl #3 80014b2: f853 5b04 ldr.w r5, [r3], #4 80014b6: f841 5f04 str.w r5, [r1, #4]! 80014ba: 429a cmp r2, r3 80014bc: d1f9 bne.n 80014b2 <_Unwind_VRS_Pop+0x1ae> 80014be: 2c01 cmp r4, #1 80014c0: d03b beq.n 800153a <_Unwind_VRS_Pop+0x236> 80014c2: f1b8 0f0f cmp.w r8, #15 80014c6: 63b2 str r2, [r6, #56] ; 0x38 80014c8: d958 bls.n 800157c <_Unwind_VRS_Pop+0x278> 80014ca: 4638 mov r0, r7 80014cc: f000 f88e bl 80015ec <__gnu_Unwind_Restore_VFP_D_16_to_31> 80014d0: e79a b.n 8001408 <_Unwind_VRS_Pop+0x104> 80014d2: 2b10 cmp r3, #16 80014d4: d954 bls.n 8001580 <_Unwind_VRS_Pop+0x27c> 80014d6: 6832 ldr r2, [r6, #0] 80014d8: 07d7 lsls r7, r2, #31 80014da: f1a3 0910 sub.w r9, r3, #16 80014de: d509 bpl.n 80014f4 <_Unwind_VRS_Pop+0x1f0> 80014e0: f022 0301 bic.w r3, r2, #1 80014e4: 4630 mov r0, r6 80014e6: f043 0302 orr.w r3, r3, #2 80014ea: f840 3b48 str.w r3, [r0], #72 80014ee: f000 f879 bl 80015e4 <__gnu_Unwind_Save_VFP_D> 80014f2: 6832 ldr r2, [r6, #0] 80014f4: 0753 lsls r3, r2, #29 80014f6: d439 bmi.n 800156c <_Unwind_VRS_Pop+0x268> 80014f8: f1b8 0f0f cmp.w r8, #15 80014fc: d802 bhi.n 8001504 <_Unwind_VRS_Pop+0x200> 80014fe: a820 add r0, sp, #128 ; 0x80 8001500: f000 f870 bl 80015e4 <__gnu_Unwind_Save_VFP_D> 8001504: 466f mov r7, sp 8001506: 4638 mov r0, r7 8001508: f1c8 0510 rsb r5, r8, #16 800150c: f000 f872 bl 80015f4 <__gnu_Unwind_Save_VFP_D_16_to_31> 8001510: 2d00 cmp r5, #0 8001512: 6bb2 ldr r2, [r6, #56] ; 0x38 8001514: dd28 ble.n 8001568 <_Unwind_VRS_Pop+0x264> 8001516: af20 add r7, sp, #128 ; 0x80 8001518: e7b3 b.n 8001482 <_Unwind_VRS_Pop+0x17e> 800151a: f023 0310 bic.w r3, r3, #16 800151e: 6003 str r3, [r0, #0] 8001520: f500 70e8 add.w r0, r0, #464 ; 0x1d0 8001524: f000 f8b8 bl 8001698 <__gnu_Unwind_Save_WMMXC> 8001528: e704 b.n 8001334 <_Unwind_VRS_Pop+0x30> 800152a: f023 0308 bic.w r3, r3, #8 800152e: 6003 str r3, [r0, #0] 8001530: f500 70a8 add.w r0, r0, #336 ; 0x150 8001534: f000 f884 bl 8001640 <__gnu_Unwind_Save_WMMXD> 8001538: e72a b.n 8001390 <_Unwind_VRS_Pop+0x8c> 800153a: af20 add r7, sp, #128 ; 0x80 800153c: 3204 adds r2, #4 800153e: 63b2 str r2, [r6, #56] ; 0x38 8001540: 4638 mov r0, r7 8001542: f000 f843 bl 80015cc <__gnu_Unwind_Restore_VFP> 8001546: e75f b.n 8001408 <_Unwind_VRS_Pop+0x104> 8001548: 2c01 cmp r4, #1 800154a: d0f7 beq.n 800153c <_Unwind_VRS_Pop+0x238> 800154c: f1b8 0f0f cmp.w r8, #15 8001550: 63b2 str r2, [r6, #56] ; 0x38 8001552: f63f af59 bhi.w 8001408 <_Unwind_VRS_Pop+0x104> 8001556: 4638 mov r0, r7 8001558: f000 f840 bl 80015dc <__gnu_Unwind_Restore_VFP_D> 800155c: f1b9 0f00 cmp.w r9, #0 8001560: f43f af52 beq.w 8001408 <_Unwind_VRS_Pop+0x104> 8001564: 466f mov r7, sp 8001566: e7b0 b.n 80014ca <_Unwind_VRS_Pop+0x1c6> 8001568: 4613 mov r3, r2 800156a: e799 b.n 80014a0 <_Unwind_VRS_Pop+0x19c> 800156c: 4630 mov r0, r6 800156e: f022 0204 bic.w r2, r2, #4 8001572: f840 2bd0 str.w r2, [r0], #208 8001576: f000 f83d bl 80015f4 <__gnu_Unwind_Save_VFP_D_16_to_31> 800157a: e7bd b.n 80014f8 <_Unwind_VRS_Pop+0x1f4> 800157c: af20 add r7, sp, #128 ; 0x80 800157e: e7ea b.n 8001556 <_Unwind_VRS_Pop+0x252> 8001580: 6833 ldr r3, [r6, #0] 8001582: 07d9 lsls r1, r3, #31 8001584: d508 bpl.n 8001598 <_Unwind_VRS_Pop+0x294> 8001586: f023 0301 bic.w r3, r3, #1 800158a: 4630 mov r0, r6 800158c: f043 0302 orr.w r3, r3, #2 8001590: f840 3b48 str.w r3, [r0], #72 8001594: f000 f826 bl 80015e4 <__gnu_Unwind_Save_VFP_D> 8001598: af20 add r7, sp, #128 ; 0x80 800159a: 4638 mov r0, r7 800159c: 464d mov r5, r9 800159e: f000 f821 bl 80015e4 <__gnu_Unwind_Save_VFP_D> 80015a2: 6bb2 ldr r2, [r6, #56] ; 0x38 80015a4: 2d00 cmp r5, #0 80015a6: f47f af6a bne.w 800147e <_Unwind_VRS_Pop+0x17a> 80015aa: 4638 mov r0, r7 80015ac: f000 f816 bl 80015dc <__gnu_Unwind_Restore_VFP_D> 80015b0: e72a b.n 8001408 <_Unwind_VRS_Pop+0x104> 80015b2: bf00 nop 080015b4 <__restore_core_regs>: 80015b4: f100 0134 add.w r1, r0, #52 ; 0x34 80015b8: e891 0038 ldmia.w r1, {r3, r4, r5} 80015bc: 469c mov ip, r3 80015be: 46a6 mov lr, r4 80015c0: f84c 5d04 str.w r5, [ip, #-4]! 80015c4: e890 0fff ldmia.w r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp} 80015c8: 46e5 mov sp, ip 80015ca: bd00 pop {pc} 080015cc <__gnu_Unwind_Restore_VFP>: 80015cc: ec90 0b21 fldmiax r0, {d0-d15} ;@ Deprecated 80015d0: 4770 bx lr 80015d2: bf00 nop 080015d4 <__gnu_Unwind_Save_VFP>: 80015d4: ec80 0b21 fstmiax r0, {d0-d15} ;@ Deprecated 80015d8: 4770 bx lr 80015da: bf00 nop 080015dc <__gnu_Unwind_Restore_VFP_D>: 80015dc: ec90 0b20 vldmia r0, {d0-d15} 80015e0: 4770 bx lr 80015e2: bf00 nop 080015e4 <__gnu_Unwind_Save_VFP_D>: 80015e4: ec80 0b20 vstmia r0, {d0-d15} 80015e8: 4770 bx lr 80015ea: bf00 nop 080015ec <__gnu_Unwind_Restore_VFP_D_16_to_31>: 80015ec: ecd0 0b20 vldmia r0, {d16-d31} 80015f0: 4770 bx lr 80015f2: bf00 nop 080015f4 <__gnu_Unwind_Save_VFP_D_16_to_31>: 80015f4: ecc0 0b20 vstmia r0, {d16-d31} 80015f8: 4770 bx lr 80015fa: bf00 nop 080015fc <__gnu_Unwind_Restore_WMMXD>: 80015fc: ecf0 0102 ldfe f0, [r0], #8 8001600: ecf0 1102 ldfe f1, [r0], #8 8001604: ecf0 2102 ldfe f2, [r0], #8 8001608: ecf0 3102 ldfe f3, [r0], #8 800160c: ecf0 4102 ldfe f4, [r0], #8 8001610: ecf0 5102 ldfe f5, [r0], #8 8001614: ecf0 6102 ldfe f6, [r0], #8 8001618: ecf0 7102 ldfe f7, [r0], #8 800161c: ecf0 8102 ldfp f0, [r0], #8 8001620: ecf0 9102 ldfp f1, [r0], #8 8001624: ecf0 a102 ldfp f2, [r0], #8 8001628: ecf0 b102 ldfp f3, [r0], #8 800162c: ecf0 c102 ldfp f4, [r0], #8 8001630: ecf0 d102 ldfp f5, [r0], #8 8001634: ecf0 e102 ldfp f6, [r0], #8 8001638: ecf0 f102 ldfp f7, [r0], #8 800163c: 4770 bx lr 800163e: bf00 nop 08001640 <__gnu_Unwind_Save_WMMXD>: 8001640: ece0 0102 stfe f0, [r0], #8 8001644: ece0 1102 stfe f1, [r0], #8 8001648: ece0 2102 stfe f2, [r0], #8 800164c: ece0 3102 stfe f3, [r0], #8 8001650: ece0 4102 stfe f4, [r0], #8 8001654: ece0 5102 stfe f5, [r0], #8 8001658: ece0 6102 stfe f6, [r0], #8 800165c: ece0 7102 stfe f7, [r0], #8 8001660: ece0 8102 stfp f0, [r0], #8 8001664: ece0 9102 stfp f1, [r0], #8 8001668: ece0 a102 stfp f2, [r0], #8 800166c: ece0 b102 stfp f3, [r0], #8 8001670: ece0 c102 stfp f4, [r0], #8 8001674: ece0 d102 stfp f5, [r0], #8 8001678: ece0 e102 stfp f6, [r0], #8 800167c: ece0 f102 stfp f7, [r0], #8 8001680: 4770 bx lr 8001682: bf00 nop 08001684 <__gnu_Unwind_Restore_WMMXC>: 8001684: fcb0 8101 ldc2 1, cr8, [r0], #4 8001688: fcb0 9101 ldc2 1, cr9, [r0], #4 800168c: fcb0 a101 ldc2 1, cr10, [r0], #4 8001690: fcb0 b101 ldc2 1, cr11, [r0], #4 8001694: 4770 bx lr 8001696: bf00 nop 08001698 <__gnu_Unwind_Save_WMMXC>: 8001698: fca0 8101 stc2 1, cr8, [r0], #4 800169c: fca0 9101 stc2 1, cr9, [r0], #4 80016a0: fca0 a101 stc2 1, cr10, [r0], #4 80016a4: fca0 b101 stc2 1, cr11, [r0], #4 80016a8: 4770 bx lr 80016aa: bf00 nop 080016ac <_Unwind_RaiseException>: 80016ac: 46ec mov ip, sp 80016ae: b500 push {lr} 80016b0: e92d 5000 stmdb sp!, {ip, lr} 80016b4: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 80016b8: f04f 0300 mov.w r3, #0 80016bc: e92d 000c stmdb sp!, {r2, r3} 80016c0: a901 add r1, sp, #4 80016c2: f7ff fbcb bl 8000e5c <__gnu_Unwind_RaiseException> 80016c6: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 80016ca: b012 add sp, #72 ; 0x48 80016cc: 4770 bx lr 80016ce: bf00 nop 080016d0 <_Unwind_Resume>: 80016d0: 46ec mov ip, sp 80016d2: b500 push {lr} 80016d4: e92d 5000 stmdb sp!, {ip, lr} 80016d8: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 80016dc: f04f 0300 mov.w r3, #0 80016e0: e92d 000c stmdb sp!, {r2, r3} 80016e4: a901 add r1, sp, #4 80016e6: f7ff fbf5 bl 8000ed4 <__gnu_Unwind_Resume> 80016ea: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 80016ee: b012 add sp, #72 ; 0x48 80016f0: 4770 bx lr 80016f2: bf00 nop 080016f4 <_Unwind_Resume_or_Rethrow>: 80016f4: 46ec mov ip, sp 80016f6: b500 push {lr} 80016f8: e92d 5000 stmdb sp!, {ip, lr} 80016fc: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8001700: f04f 0300 mov.w r3, #0 8001704: e92d 000c stmdb sp!, {r2, r3} 8001708: a901 add r1, sp, #4 800170a: f7ff fc05 bl 8000f18 <__gnu_Unwind_Resume_or_Rethrow> 800170e: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 8001712: b012 add sp, #72 ; 0x48 8001714: 4770 bx lr 8001716: bf00 nop 08001718 <_Unwind_ForcedUnwind>: 8001718: 46ec mov ip, sp 800171a: b500 push {lr} 800171c: e92d 5000 stmdb sp!, {ip, lr} 8001720: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8001724: f04f 0300 mov.w r3, #0 8001728: e92d 000c stmdb sp!, {r2, r3} 800172c: ab01 add r3, sp, #4 800172e: f7ff fbc9 bl 8000ec4 <__gnu_Unwind_ForcedUnwind> 8001732: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 8001736: b012 add sp, #72 ; 0x48 8001738: 4770 bx lr 800173a: bf00 nop 0800173c <_Unwind_Backtrace>: 800173c: 46ec mov ip, sp 800173e: b500 push {lr} 8001740: e92d 5000 stmdb sp!, {ip, lr} 8001744: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8001748: f04f 0300 mov.w r3, #0 800174c: e92d 000c stmdb sp!, {r2, r3} 8001750: aa01 add r2, sp, #4 8001752: f7ff fc3b bl 8000fcc <__gnu_Unwind_Backtrace> 8001756: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 800175a: b012 add sp, #72 ; 0x48 800175c: 4770 bx lr 800175e: bf00 nop 08001760 : 8001760: 7a02 ldrb r2, [r0, #8] 8001762: 4603 mov r3, r0 8001764: b97a cbnz r2, 8001786 8001766: 7a42 ldrb r2, [r0, #9] 8001768: b1a2 cbz r2, 8001794 800176a: 6841 ldr r1, [r0, #4] 800176c: 3a01 subs r2, #1 800176e: b410 push {r4} 8001770: 7242 strb r2, [r0, #9] 8001772: 6808 ldr r0, [r1, #0] 8001774: 2203 movs r2, #3 8001776: 1d0c adds r4, r1, #4 8001778: 721a strb r2, [r3, #8] 800177a: 0202 lsls r2, r0, #8 800177c: 605c str r4, [r3, #4] 800177e: 0e00 lsrs r0, r0, #24 8001780: bc10 pop {r4} 8001782: 601a str r2, [r3, #0] 8001784: 4770 bx lr 8001786: 6800 ldr r0, [r0, #0] 8001788: 3a01 subs r2, #1 800178a: 721a strb r2, [r3, #8] 800178c: 0202 lsls r2, r0, #8 800178e: 601a str r2, [r3, #0] 8001790: 0e00 lsrs r0, r0, #24 8001792: 4770 bx lr 8001794: 20b0 movs r0, #176 ; 0xb0 8001796: 4770 bx lr 08001798 <_Unwind_GetGR.constprop.0>: 8001798: b500 push {lr} 800179a: b085 sub sp, #20 800179c: 2300 movs r3, #0 800179e: aa03 add r2, sp, #12 80017a0: 9200 str r2, [sp, #0] 80017a2: 4619 mov r1, r3 80017a4: 220c movs r2, #12 80017a6: f7ff fbc7 bl 8000f38 <_Unwind_VRS_Get> 80017aa: 9803 ldr r0, [sp, #12] 80017ac: b005 add sp, #20 80017ae: f85d fb04 ldr.w pc, [sp], #4 80017b2: bf00 nop 080017b4 : 80017b4: e7f0 b.n 8001798 <_Unwind_GetGR.constprop.0> 80017b6: bf00 nop 080017b8 <__gnu_unwind_execute>: 80017b8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 80017bc: b085 sub sp, #20 80017be: 4607 mov r7, r0 80017c0: 460e mov r6, r1 80017c2: f04f 0800 mov.w r8, #0 80017c6: ad03 add r5, sp, #12 80017c8: 4630 mov r0, r6 80017ca: f7ff ffc9 bl 8001760 80017ce: 28b0 cmp r0, #176 ; 0xb0 80017d0: 4604 mov r4, r0 80017d2: f000 80cb beq.w 800196c <__gnu_unwind_execute+0x1b4> 80017d6: 0603 lsls r3, r0, #24 80017d8: d540 bpl.n 800185c <__gnu_unwind_execute+0xa4> 80017da: f000 03f0 and.w r3, r0, #240 ; 0xf0 80017de: 2b80 cmp r3, #128 ; 0x80 80017e0: d056 beq.n 8001890 <__gnu_unwind_execute+0xd8> 80017e2: 2bb0 cmp r3, #176 ; 0xb0 80017e4: d07d beq.n 80018e2 <__gnu_unwind_execute+0x12a> 80017e6: d81c bhi.n 8001822 <__gnu_unwind_execute+0x6a> 80017e8: 2b90 cmp r3, #144 ; 0x90 80017ea: f000 8093 beq.w 8001914 <__gnu_unwind_execute+0x15c> 80017ee: 2ba0 cmp r3, #160 ; 0xa0 80017f0: d113 bne.n 800181a <__gnu_unwind_execute+0x62> 80017f2: 43c3 mvns r3, r0 80017f4: f003 0307 and.w r3, r3, #7 80017f8: f44f 627f mov.w r2, #4080 ; 0xff0 80017fc: 411a asrs r2, r3 80017fe: 0701 lsls r1, r0, #28 8001800: f402 627f and.w r2, r2, #4080 ; 0xff0 8001804: f04f 0300 mov.w r3, #0 8001808: bf48 it mi 800180a: f442 4280 orrmi.w r2, r2, #16384 ; 0x4000 800180e: 4619 mov r1, r3 8001810: 4638 mov r0, r7 8001812: f7ff fd77 bl 8001304 <_Unwind_VRS_Pop> 8001816: 2800 cmp r0, #0 8001818: d0d6 beq.n 80017c8 <__gnu_unwind_execute+0x10> 800181a: 2009 movs r0, #9 800181c: b005 add sp, #20 800181e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 8001822: 2bc0 cmp r3, #192 ; 0xc0 8001824: d14b bne.n 80018be <__gnu_unwind_execute+0x106> 8001826: 28c6 cmp r0, #198 ; 0xc6 8001828: f000 8089 beq.w 800193e <__gnu_unwind_execute+0x186> 800182c: 28c7 cmp r0, #199 ; 0xc7 800182e: f000 80a2 beq.w 8001976 <__gnu_unwind_execute+0x1be> 8001832: f000 03f8 and.w r3, r0, #248 ; 0xf8 8001836: 2bc0 cmp r3, #192 ; 0xc0 8001838: f000 80bc beq.w 80019b4 <__gnu_unwind_execute+0x1fc> 800183c: 28c8 cmp r0, #200 ; 0xc8 800183e: f000 80bf beq.w 80019c0 <__gnu_unwind_execute+0x208> 8001842: 28c9 cmp r0, #201 ; 0xc9 8001844: d1e9 bne.n 800181a <__gnu_unwind_execute+0x62> 8001846: 4630 mov r0, r6 8001848: f7ff ff8a bl 8001760 800184c: 0302 lsls r2, r0, #12 800184e: f000 000f and.w r0, r0, #15 8001852: f402 2270 and.w r2, r2, #983040 ; 0xf0000 8001856: 3001 adds r0, #1 8001858: 4302 orrs r2, r0 800185a: e039 b.n 80018d0 <__gnu_unwind_execute+0x118> 800185c: 0083 lsls r3, r0, #2 800185e: b2db uxtb r3, r3 8001860: f103 0904 add.w r9, r3, #4 8001864: 2300 movs r3, #0 8001866: 4619 mov r1, r3 8001868: 9500 str r5, [sp, #0] 800186a: 220d movs r2, #13 800186c: 4638 mov r0, r7 800186e: f7ff fb63 bl 8000f38 <_Unwind_VRS_Get> 8001872: 9b03 ldr r3, [sp, #12] 8001874: 0660 lsls r0, r4, #25 8001876: bf4c ite mi 8001878: eba3 0309 submi.w r3, r3, r9 800187c: 444b addpl r3, r9 800187e: 9303 str r3, [sp, #12] 8001880: 2300 movs r3, #0 8001882: 9500 str r5, [sp, #0] 8001884: 220d movs r2, #13 8001886: 4619 mov r1, r3 8001888: 4638 mov r0, r7 800188a: f7ff fb7b bl 8000f84 <_Unwind_VRS_Set> 800188e: e79b b.n 80017c8 <__gnu_unwind_execute+0x10> 8001890: 0204 lsls r4, r0, #8 8001892: 4630 mov r0, r6 8001894: f7ff ff64 bl 8001760 8001898: 4320 orrs r0, r4 800189a: f5b0 4f00 cmp.w r0, #32768 ; 0x8000 800189e: d0bc beq.n 800181a <__gnu_unwind_execute+0x62> 80018a0: 0104 lsls r4, r0, #4 80018a2: 2300 movs r3, #0 80018a4: b2a2 uxth r2, r4 80018a6: 4619 mov r1, r3 80018a8: 4638 mov r0, r7 80018aa: f7ff fd2b bl 8001304 <_Unwind_VRS_Pop> 80018ae: 2800 cmp r0, #0 80018b0: d1b3 bne.n 800181a <__gnu_unwind_execute+0x62> 80018b2: f414 4f00 tst.w r4, #32768 ; 0x8000 80018b6: bf18 it ne 80018b8: f04f 0801 movne.w r8, #1 80018bc: e784 b.n 80017c8 <__gnu_unwind_execute+0x10> 80018be: f000 03f8 and.w r3, r0, #248 ; 0xf8 80018c2: 2bd0 cmp r3, #208 ; 0xd0 80018c4: d1a9 bne.n 800181a <__gnu_unwind_execute+0x62> 80018c6: f000 0207 and.w r2, r0, #7 80018ca: 3201 adds r2, #1 80018cc: f442 2200 orr.w r2, r2, #524288 ; 0x80000 80018d0: 2305 movs r3, #5 80018d2: 2101 movs r1, #1 80018d4: 4638 mov r0, r7 80018d6: f7ff fd15 bl 8001304 <_Unwind_VRS_Pop> 80018da: 2800 cmp r0, #0 80018dc: f43f af74 beq.w 80017c8 <__gnu_unwind_execute+0x10> 80018e0: e79b b.n 800181a <__gnu_unwind_execute+0x62> 80018e2: 28b1 cmp r0, #177 ; 0xb1 80018e4: d037 beq.n 8001956 <__gnu_unwind_execute+0x19e> 80018e6: 28b2 cmp r0, #178 ; 0xb2 80018e8: f000 8087 beq.w 80019fa <__gnu_unwind_execute+0x242> 80018ec: 28b3 cmp r0, #179 ; 0xb3 80018ee: d056 beq.n 800199e <__gnu_unwind_execute+0x1e6> 80018f0: f000 03fc and.w r3, r0, #252 ; 0xfc 80018f4: 2bb4 cmp r3, #180 ; 0xb4 80018f6: d090 beq.n 800181a <__gnu_unwind_execute+0x62> 80018f8: f000 0207 and.w r2, r0, #7 80018fc: 3201 adds r2, #1 80018fe: f442 2200 orr.w r2, r2, #524288 ; 0x80000 8001902: 2301 movs r3, #1 8001904: 4619 mov r1, r3 8001906: 4638 mov r0, r7 8001908: f7ff fcfc bl 8001304 <_Unwind_VRS_Pop> 800190c: 2800 cmp r0, #0 800190e: f43f af5b beq.w 80017c8 <__gnu_unwind_execute+0x10> 8001912: e782 b.n 800181a <__gnu_unwind_execute+0x62> 8001914: f000 030d and.w r3, r0, #13 8001918: 2b0d cmp r3, #13 800191a: f43f af7e beq.w 800181a <__gnu_unwind_execute+0x62> 800191e: 2300 movs r3, #0 8001920: f000 020f and.w r2, r0, #15 8001924: 4619 mov r1, r3 8001926: 9500 str r5, [sp, #0] 8001928: 4638 mov r0, r7 800192a: f7ff fb05 bl 8000f38 <_Unwind_VRS_Get> 800192e: 2300 movs r3, #0 8001930: 9500 str r5, [sp, #0] 8001932: 220d movs r2, #13 8001934: 4619 mov r1, r3 8001936: 4638 mov r0, r7 8001938: f7ff fb24 bl 8000f84 <_Unwind_VRS_Set> 800193c: e744 b.n 80017c8 <__gnu_unwind_execute+0x10> 800193e: 4630 mov r0, r6 8001940: f7ff ff0e bl 8001760 8001944: 0302 lsls r2, r0, #12 8001946: f000 000f and.w r0, r0, #15 800194a: f402 2270 and.w r2, r2, #983040 ; 0xf0000 800194e: 3001 adds r0, #1 8001950: 4302 orrs r2, r0 8001952: 2303 movs r3, #3 8001954: e7d6 b.n 8001904 <__gnu_unwind_execute+0x14c> 8001956: 4630 mov r0, r6 8001958: f7ff ff02 bl 8001760 800195c: 4602 mov r2, r0 800195e: 2800 cmp r0, #0 8001960: f43f af5b beq.w 800181a <__gnu_unwind_execute+0x62> 8001964: f010 03f0 ands.w r3, r0, #240 ; 0xf0 8001968: d0cc beq.n 8001904 <__gnu_unwind_execute+0x14c> 800196a: e756 b.n 800181a <__gnu_unwind_execute+0x62> 800196c: f1b8 0f00 cmp.w r8, #0 8001970: d032 beq.n 80019d8 <__gnu_unwind_execute+0x220> 8001972: 2000 movs r0, #0 8001974: e752 b.n 800181c <__gnu_unwind_execute+0x64> 8001976: 4630 mov r0, r6 8001978: f7ff fef2 bl 8001760 800197c: 4602 mov r2, r0 800197e: 2800 cmp r0, #0 8001980: f43f af4b beq.w 800181a <__gnu_unwind_execute+0x62> 8001984: f010 0ff0 tst.w r0, #240 ; 0xf0 8001988: f47f af47 bne.w 800181a <__gnu_unwind_execute+0x62> 800198c: 2300 movs r3, #0 800198e: 2104 movs r1, #4 8001990: 4638 mov r0, r7 8001992: f7ff fcb7 bl 8001304 <_Unwind_VRS_Pop> 8001996: 2800 cmp r0, #0 8001998: f43f af16 beq.w 80017c8 <__gnu_unwind_execute+0x10> 800199c: e73d b.n 800181a <__gnu_unwind_execute+0x62> 800199e: 4630 mov r0, r6 80019a0: f7ff fede bl 8001760 80019a4: 0302 lsls r2, r0, #12 80019a6: f000 000f and.w r0, r0, #15 80019aa: f402 2270 and.w r2, r2, #983040 ; 0xf0000 80019ae: 3001 adds r0, #1 80019b0: 4302 orrs r2, r0 80019b2: e7a6 b.n 8001902 <__gnu_unwind_execute+0x14a> 80019b4: f000 020f and.w r2, r0, #15 80019b8: 3201 adds r2, #1 80019ba: f442 2220 orr.w r2, r2, #655360 ; 0xa0000 80019be: e7c8 b.n 8001952 <__gnu_unwind_execute+0x19a> 80019c0: 4630 mov r0, r6 80019c2: f7ff fecd bl 8001760 80019c6: f000 02f0 and.w r2, r0, #240 ; 0xf0 80019ca: f000 030f and.w r3, r0, #15 80019ce: 3210 adds r2, #16 80019d0: 3301 adds r3, #1 80019d2: ea43 3202 orr.w r2, r3, r2, lsl #12 80019d6: e77b b.n 80018d0 <__gnu_unwind_execute+0x118> 80019d8: ac03 add r4, sp, #12 80019da: 4643 mov r3, r8 80019dc: 220e movs r2, #14 80019de: 4641 mov r1, r8 80019e0: 9400 str r4, [sp, #0] 80019e2: 4638 mov r0, r7 80019e4: f7ff faa8 bl 8000f38 <_Unwind_VRS_Get> 80019e8: 9400 str r4, [sp, #0] 80019ea: 4643 mov r3, r8 80019ec: 220f movs r2, #15 80019ee: 4641 mov r1, r8 80019f0: 4638 mov r0, r7 80019f2: f7ff fac7 bl 8000f84 <_Unwind_VRS_Set> 80019f6: 4640 mov r0, r8 80019f8: e710 b.n 800181c <__gnu_unwind_execute+0x64> 80019fa: 2300 movs r3, #0 80019fc: 220d movs r2, #13 80019fe: 4619 mov r1, r3 8001a00: 9500 str r5, [sp, #0] 8001a02: 4638 mov r0, r7 8001a04: f7ff fa98 bl 8000f38 <_Unwind_VRS_Get> 8001a08: 4630 mov r0, r6 8001a0a: f7ff fea9 bl 8001760 8001a0e: 0602 lsls r2, r0, #24 8001a10: 9c03 ldr r4, [sp, #12] 8001a12: f04f 0902 mov.w r9, #2 8001a16: d50c bpl.n 8001a32 <__gnu_unwind_execute+0x27a> 8001a18: f000 007f and.w r0, r0, #127 ; 0x7f 8001a1c: fa00 f009 lsl.w r0, r0, r9 8001a20: 4404 add r4, r0 8001a22: 4630 mov r0, r6 8001a24: 9403 str r4, [sp, #12] 8001a26: f7ff fe9b bl 8001760 8001a2a: 0603 lsls r3, r0, #24 8001a2c: f109 0907 add.w r9, r9, #7 8001a30: d4f2 bmi.n 8001a18 <__gnu_unwind_execute+0x260> 8001a32: f000 037f and.w r3, r0, #127 ; 0x7f 8001a36: fa03 f309 lsl.w r3, r3, r9 8001a3a: f504 7401 add.w r4, r4, #516 ; 0x204 8001a3e: 4423 add r3, r4 8001a40: e71d b.n 800187e <__gnu_unwind_execute+0xc6> 8001a42: bf00 nop 08001a44 <__gnu_unwind_frame>: 8001a44: b510 push {r4, lr} 8001a46: 6cc2 ldr r2, [r0, #76] ; 0x4c 8001a48: 6853 ldr r3, [r2, #4] 8001a4a: b084 sub sp, #16 8001a4c: f04f 0c03 mov.w ip, #3 8001a50: 3208 adds r2, #8 8001a52: 021c lsls r4, r3, #8 8001a54: 4608 mov r0, r1 8001a56: 0e1b lsrs r3, r3, #24 8001a58: a901 add r1, sp, #4 8001a5a: 9401 str r4, [sp, #4] 8001a5c: 9202 str r2, [sp, #8] 8001a5e: f88d c00c strb.w ip, [sp, #12] 8001a62: f88d 300d strb.w r3, [sp, #13] 8001a66: f7ff fea7 bl 80017b8 <__gnu_unwind_execute> 8001a6a: b004 add sp, #16 8001a6c: bd10 pop {r4, pc} 8001a6e: bf00 nop 08001a70 <_Unwind_GetRegionStart>: 8001a70: b508 push {r3, lr} 8001a72: f7ff fe9f bl 80017b4 8001a76: 6c80 ldr r0, [r0, #72] ; 0x48 8001a78: bd08 pop {r3, pc} 8001a7a: bf00 nop 08001a7c <_Unwind_GetLanguageSpecificData>: 8001a7c: b508 push {r3, lr} 8001a7e: f7ff fe99 bl 80017b4 8001a82: 6cc0 ldr r0, [r0, #76] ; 0x4c 8001a84: 79c3 ldrb r3, [r0, #7] 8001a86: 3302 adds r3, #2 8001a88: eb00 0083 add.w r0, r0, r3, lsl #2 8001a8c: bd08 pop {r3, pc} 8001a8e: bf00 nop 08001a90 : DMA_HandleTypeDef hdma_adc1; DMA_HandleTypeDef hdma_adc2; /* ADC1 init function */ void MX_ADC1_Init(void) { 8001a90: b510 push {r4, lr} /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8001a92: 2400 movs r4, #0 { 8001a94: b08c sub sp, #48 ; 0x30 ADC_ChannelConfTypeDef sConfig = {0}; 8001a96: 2220 movs r2, #32 8001a98: 4621 mov r1, r4 8001a9a: a804 add r0, sp, #16 ADC_MultiModeTypeDef multimode = {0}; 8001a9c: e9cd 4401 strd r4, r4, [sp, #4] 8001aa0: 9403 str r4, [sp, #12] ADC_ChannelConfTypeDef sConfig = {0}; 8001aa2: f004 fcad bl 8006400 /* USER CODE BEGIN ADC1_Init 1 */ /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8001aa6: 4822 ldr r0, [pc, #136] ; (8001b30 ) hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 8001aa8: f44f 3200 mov.w r2, #131072 ; 0x20000 8001aac: f04f 41a0 mov.w r1, #1342177280 ; 0x50000000 8001ab0: e9c0 1200 strd r1, r2, [r0] hadc1.Init.Resolution = ADC_RESOLUTION_12B; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.GainCompensation = 0; hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8001ab4: 2204 movs r2, #4 8001ab6: 6182 str r2, [r0, #24] hadc1.Init.LowPowerAutoWait = DISABLE; hadc1.Init.ContinuousConvMode = DISABLE; hadc1.Init.NbrOfConversion = 1; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T3_TRGO; 8001ab8: f44f 6290 mov.w r2, #1152 ; 0x480 hadc1.Init.NbrOfConversion = 1; 8001abc: 2301 movs r3, #1 hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T3_TRGO; 8001abe: 62c2 str r2, [r0, #44] ; 0x2c hadc1.Init.LowPowerAutoWait = DISABLE; 8001ac0: 8384 strh r4, [r0, #28] hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8001ac2: f44f 6280 mov.w r2, #1024 ; 0x400 hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8001ac6: e9c0 4402 strd r4, r4, [r0, #8] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 8001aca: e9c0 4404 strd r4, r4, [r0, #16] hadc1.Init.NbrOfConversion = 1; 8001ace: 6203 str r3, [r0, #32] hadc1.Init.DiscontinuousConvMode = DISABLE; 8001ad0: f880 4024 strb.w r4, [r0, #36] ; 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8001ad4: 6302 str r2, [r0, #48] ; 0x30 hadc1.Init.DMAContinuousRequests = ENABLE; 8001ad6: f880 3038 strb.w r3, [r0, #56] ; 0x38 hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8001ada: 63c4 str r4, [r0, #60] ; 0x3c hadc1.Init.OversamplingMode = DISABLE; 8001adc: f880 4040 strb.w r4, [r0, #64] ; 0x40 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8001ae0: f001 f85c bl 8002b9c 8001ae4: b9c8 cbnz r0, 8001b1a { Error_Handler(); } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8001ae6: 2300 movs r3, #0 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8001ae8: 4811 ldr r0, [pc, #68] ; (8001b30 ) multimode.Mode = ADC_MODE_INDEPENDENT; 8001aea: 9301 str r3, [sp, #4] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8001aec: a901 add r1, sp, #4 8001aee: f001 fcc1 bl 8003474 8001af2: b9c8 cbnz r0, 8001b28 { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8001af4: 4a0f ldr r2, [pc, #60] ; (8001b34 ) sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_24CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001af6: 480e ldr r0, [pc, #56] ; (8001b30 ) sConfig.Rank = ADC_REGULAR_RANK_1; 8001af8: 2306 movs r3, #6 8001afa: e9cd 2304 strd r2, r3, [sp, #16] sConfig.SamplingTime = ADC_SAMPLETIME_24CYCLES_5; 8001afe: 2403 movs r4, #3 sConfig.SingleDiff = ADC_SINGLE_ENDED; 8001b00: 237f movs r3, #127 ; 0x7f 8001b02: e9cd 4306 strd r4, r3, [sp, #24] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8001b06: 2204 movs r2, #4 sConfig.Offset = 0; 8001b08: 2300 movs r3, #0 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001b0a: a904 add r1, sp, #16 sConfig.Offset = 0; 8001b0c: e9cd 2308 strd r2, r3, [sp, #32] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8001b10: f001 f996 bl 8002e40 8001b14: b920 cbnz r0, 8001b20 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 8001b16: b00c add sp, #48 ; 0x30 8001b18: bd10 pop {r4, pc} Error_Handler(); 8001b1a: f000 fd57 bl 80025cc 8001b1e: e7e2 b.n 8001ae6 Error_Handler(); 8001b20: f000 fd54 bl 80025cc } 8001b24: b00c add sp, #48 ; 0x30 8001b26: bd10 pop {r4, pc} Error_Handler(); 8001b28: f000 fd50 bl 80025cc 8001b2c: e7e2 b.n 8001af4 8001b2e: bf00 nop 8001b30: 20007834 .word 0x20007834 8001b34: 0c900008 .word 0x0c900008 08001b38 : /* ADC2 init function */ void MX_ADC2_Init(void) { 8001b38: b510 push {r4, lr} 8001b3a: b088 sub sp, #32 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8001b3c: 2220 movs r2, #32 8001b3e: 2100 movs r1, #0 8001b40: 4668 mov r0, sp 8001b42: f004 fc5d bl 8006400 /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 8001b46: 4c1c ldr r4, [pc, #112] ; (8001bb8 ) hadc2.Instance = ADC2; 8001b48: 481c ldr r0, [pc, #112] ; (8001bbc ) hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; 8001b4a: f44f 3100 mov.w r1, #131072 ; 0x20000 8001b4e: e9c0 4100 strd r4, r1, [r0] hadc2.Init.Resolution = ADC_RESOLUTION_12B; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.GainCompensation = 0; hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8001b52: 2104 movs r1, #4 hadc2.Init.Resolution = ADC_RESOLUTION_12B; 8001b54: 2300 movs r3, #0 hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 8001b56: 6181 str r1, [r0, #24] hadc2.Init.LowPowerAutoWait = DISABLE; hadc2.Init.ContinuousConvMode = DISABLE; hadc2.Init.NbrOfConversion = 1; hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8001b58: f44f 61ac mov.w r1, #1376 ; 0x560 hadc2.Init.NbrOfConversion = 1; 8001b5c: 2201 movs r2, #1 hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8001b5e: 62c1 str r1, [r0, #44] ; 0x2c hadc2.Init.LowPowerAutoWait = DISABLE; 8001b60: 8383 strh r3, [r0, #28] hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8001b62: f44f 6180 mov.w r1, #1024 ; 0x400 hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8001b66: e9c0 3302 strd r3, r3, [r0, #8] hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; 8001b6a: e9c0 3304 strd r3, r3, [r0, #16] hadc2.Init.NbrOfConversion = 1; 8001b6e: 6202 str r2, [r0, #32] hadc2.Init.DiscontinuousConvMode = DISABLE; 8001b70: f880 3024 strb.w r3, [r0, #36] ; 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8001b74: 6301 str r1, [r0, #48] ; 0x30 hadc2.Init.DMAContinuousRequests = ENABLE; 8001b76: f880 2038 strb.w r2, [r0, #56] ; 0x38 hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8001b7a: 63c3 str r3, [r0, #60] ; 0x3c hadc2.Init.OversamplingMode = DISABLE; 8001b7c: f880 3040 strb.w r3, [r0, #64] ; 0x40 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8001b80: f001 f80c bl 8002b9c 8001b84: b988 cbnz r0, 8001baa { Error_Handler(); } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8001b86: 4a0e ldr r2, [pc, #56] ; (8001bc0 ) 8001b88: 9200 str r2, [sp, #0] sConfig.Rank = ADC_REGULAR_RANK_1; sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; 8001b8a: 227f movs r2, #127 ; 0x7f sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; 8001b8c: 2300 movs r3, #0 sConfig.Rank = ADC_REGULAR_RANK_1; 8001b8e: 2406 movs r4, #6 sConfig.SingleDiff = ADC_SINGLE_ENDED; 8001b90: 9203 str r2, [sp, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8001b92: 480a ldr r0, [pc, #40] ; (8001bbc ) sConfig.OffsetNumber = ADC_OFFSET_NONE; 8001b94: 2204 movs r2, #4 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8001b96: 4669 mov r1, sp sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; 8001b98: e9cd 4301 strd r4, r3, [sp, #4] sConfig.Offset = 0; 8001b9c: e9cd 2304 strd r2, r3, [sp, #16] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8001ba0: f001 f94e bl 8002e40 8001ba4: b920 cbnz r0, 8001bb0 } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } 8001ba6: b008 add sp, #32 8001ba8: bd10 pop {r4, pc} Error_Handler(); 8001baa: f000 fd0f bl 80025cc 8001bae: e7ea b.n 8001b86 Error_Handler(); 8001bb0: f000 fd0c bl 80025cc } 8001bb4: b008 add sp, #32 8001bb6: bd10 pop {r4, pc} 8001bb8: 50000100 .word 0x50000100 8001bbc: 200077c8 .word 0x200077c8 8001bc0: 04300002 .word 0x04300002 08001bc4 : static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0; void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) { 8001bc4: b570 push {r4, r5, r6, lr} 8001bc6: 4604 mov r4, r0 8001bc8: b09a sub sp, #104 ; 0x68 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001bca: 2100 movs r1, #0 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001bcc: 2244 movs r2, #68 ; 0x44 8001bce: a809 add r0, sp, #36 ; 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001bd0: e9cd 1104 strd r1, r1, [sp, #16] 8001bd4: e9cd 1106 strd r1, r1, [sp, #24] 8001bd8: 9108 str r1, [sp, #32] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001bda: f004 fc11 bl 8006400 if(adcHandle->Instance==ADC1) 8001bde: 6823 ldr r3, [r4, #0] 8001be0: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8001be4: d004 beq.n 8001bf0 /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } else if(adcHandle->Instance==ADC2) 8001be6: 4a46 ldr r2, [pc, #280] ; (8001d00 ) 8001be8: 4293 cmp r3, r2 8001bea: d04b beq.n 8001c84 /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8001bec: b01a add sp, #104 ; 0x68 8001bee: bd70 pop {r4, r5, r6, pc} PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8001bf0: f44f 4200 mov.w r2, #32768 ; 0x8000 PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8001bf4: f04f 5300 mov.w r3, #536870912 ; 0x20000000 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001bf8: a809 add r0, sp, #36 ; 0x24 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8001bfa: 9209 str r2, [sp, #36] ; 0x24 PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8001bfc: 9318 str r3, [sp, #96] ; 0x60 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001bfe: f002 fcb7 bl 8004570 8001c02: 2800 cmp r0, #0 8001c04: d175 bne.n 8001cf2 HAL_RCC_ADC12_CLK_ENABLED++; 8001c06: 4a3f ldr r2, [pc, #252] ; (8001d04 ) 8001c08: 6813 ldr r3, [r2, #0] 8001c0a: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8001c0c: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 8001c0e: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8001c10: d109 bne.n 8001c26 __HAL_RCC_ADC12_CLK_ENABLE(); 8001c12: 4b3d ldr r3, [pc, #244] ; (8001d08 ) 8001c14: 6cda ldr r2, [r3, #76] ; 0x4c 8001c16: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8001c1a: 64da str r2, [r3, #76] ; 0x4c 8001c1c: 6cdb ldr r3, [r3, #76] ; 0x4c 8001c1e: f403 5300 and.w r3, r3, #8192 ; 0x2000 8001c22: 9300 str r3, [sp, #0] 8001c24: 9b00 ldr r3, [sp, #0] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c26: 4b38 ldr r3, [pc, #224] ; (8001d08 ) hdma_adc1.Instance = DMA1_Channel2; 8001c28: 4d38 ldr r5, [pc, #224] ; (8001d0c ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c2a: 6cda ldr r2, [r3, #76] ; 0x4c 8001c2c: f042 0201 orr.w r2, r2, #1 8001c30: 64da str r2, [r3, #76] ; 0x4c 8001c32: 6cdb ldr r3, [r3, #76] ; 0x4c 8001c34: f003 0301 and.w r3, r3, #1 8001c38: 9301 str r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_2; 8001c3a: 2204 movs r2, #4 8001c3c: 2303 movs r3, #3 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001c3e: a904 add r1, sp, #16 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001c40: 2600 movs r6, #0 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001c42: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_2; 8001c46: e9cd 2304 strd r2, r3, [sp, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001c4a: 9606 str r6, [sp, #24] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001c4c: 9b01 ldr r3, [sp, #4] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001c4e: f001 ff83 bl 8003b58 hdma_adc1.Instance = DMA1_Channel2; 8001c52: 4a2f ldr r2, [pc, #188] ; (8001d10 ) hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8001c54: 2305 movs r3, #5 hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8001c56: e9c5 2300 strd r2, r3, [r5] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8001c5a: f44f 6380 mov.w r3, #1024 ; 0x400 hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8001c5e: f44f 7280 mov.w r2, #256 ; 0x100 hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8001c62: 61ab str r3, [r5, #24] hdma_adc2.Init.Mode = DMA_CIRCULAR; 8001c64: 2320 movs r3, #32 hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8001c66: e9c5 6602 strd r6, r6, [r5, #8] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8001c6a: e9c5 6204 strd r6, r2, [r5, #16] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8001c6e: e9c5 3607 strd r3, r6, [r5, #28] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8001c72: 4628 mov r0, r5 8001c74: f001 fe32 bl 80038dc 8001c78: 2800 cmp r0, #0 8001c7a: d137 bne.n 8001cec __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc2); 8001c7c: 6565 str r5, [r4, #84] ; 0x54 8001c7e: 62ac str r4, [r5, #40] ; 0x28 } 8001c80: b01a add sp, #104 ; 0x68 8001c82: bd70 pop {r4, r5, r6, pc} PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8001c84: f44f 4200 mov.w r2, #32768 ; 0x8000 PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8001c88: f04f 5300 mov.w r3, #536870912 ; 0x20000000 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001c8c: a809 add r0, sp, #36 ; 0x24 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8001c8e: 9209 str r2, [sp, #36] ; 0x24 PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8001c90: 9318 str r3, [sp, #96] ; 0x60 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001c92: f002 fc6d bl 8004570 8001c96: 2800 cmp r0, #0 8001c98: d12e bne.n 8001cf8 HAL_RCC_ADC12_CLK_ENABLED++; 8001c9a: 4a1a ldr r2, [pc, #104] ; (8001d04 ) 8001c9c: 6813 ldr r3, [r2, #0] 8001c9e: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8001ca0: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 8001ca2: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8001ca4: d109 bne.n 8001cba __HAL_RCC_ADC12_CLK_ENABLE(); 8001ca6: 4b18 ldr r3, [pc, #96] ; (8001d08 ) 8001ca8: 6cda ldr r2, [r3, #76] ; 0x4c 8001caa: f442 5200 orr.w r2, r2, #8192 ; 0x2000 8001cae: 64da str r2, [r3, #76] ; 0x4c 8001cb0: 6cdb ldr r3, [r3, #76] ; 0x4c 8001cb2: f403 5300 and.w r3, r3, #8192 ; 0x2000 8001cb6: 9302 str r3, [sp, #8] 8001cb8: 9b02 ldr r3, [sp, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001cba: 4b13 ldr r3, [pc, #76] ; (8001d08 ) hdma_adc2.Instance = DMA1_Channel1; 8001cbc: 4d15 ldr r5, [pc, #84] ; (8001d14 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8001cbe: 6cda ldr r2, [r3, #76] ; 0x4c 8001cc0: f042 0201 orr.w r2, r2, #1 8001cc4: 64da str r2, [r3, #76] ; 0x4c 8001cc6: 6cdb ldr r3, [r3, #76] ; 0x4c 8001cc8: f003 0301 and.w r3, r3, #1 8001ccc: 9303 str r3, [sp, #12] GPIO_InitStruct.Pin = GPIO_PIN_0; 8001cce: 2201 movs r2, #1 8001cd0: 2303 movs r3, #3 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001cd2: a904 add r1, sp, #16 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001cd4: 2600 movs r6, #0 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001cd6: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_0; 8001cda: e9cd 2304 strd r2, r3, [sp, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001cde: 9606 str r6, [sp, #24] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001ce0: 9b03 ldr r3, [sp, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001ce2: f001 ff39 bl 8003b58 hdma_adc2.Instance = DMA1_Channel1; 8001ce6: 4a0c ldr r2, [pc, #48] ; (8001d18 ) hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8001ce8: 2324 movs r3, #36 ; 0x24 8001cea: e7b4 b.n 8001c56 Error_Handler(); 8001cec: f000 fc6e bl 80025cc 8001cf0: e7c4 b.n 8001c7c Error_Handler(); 8001cf2: f000 fc6b bl 80025cc 8001cf6: e786 b.n 8001c06 Error_Handler(); 8001cf8: f000 fc68 bl 80025cc 8001cfc: e7cd b.n 8001c9a 8001cfe: bf00 nop 8001d00: 50000100 .word 0x50000100 8001d04: 20000078 .word 0x20000078 8001d08: 40021000 .word 0x40021000 8001d0c: 200078a0 .word 0x200078a0 8001d10: 4002001c .word 0x4002001c 8001d14: 20007900 .word 0x20007900 8001d18: 40020008 .word 0x40020008 08001d1c : } /* USER CODE BEGIN 1 */ void ADC1_Start() { HAL_ADC_Start_DMA(&hadc1, &ADC1_raw_data, 1); 8001d1c: 4902 ldr r1, [pc, #8] ; (8001d28 ) 8001d1e: 4803 ldr r0, [pc, #12] ; (8001d2c ) 8001d20: 2201 movs r2, #1 8001d22: f001 bb2f b.w 8003384 8001d26: bf00 nop 8001d28: 20000086 .word 0x20000086 8001d2c: 20007834 .word 0x20007834 08001d30 : } void ADC2_Start() { HAL_ADC_Start_DMA(&hadc2, &ADC2_raw_data, 1); 8001d30: 4902 ldr r1, [pc, #8] ; (8001d3c ) 8001d32: 4803 ldr r0, [pc, #12] ; (8001d40 ) 8001d34: 2201 movs r2, #1 8001d36: f001 bb25 b.w 8003384 8001d3a: bf00 nop 8001d3c: 20000088 .word 0x20000088 8001d40: 200077c8 .word 0x200077c8 08001d44 : void svf_init(svf_typedef *svf, float _freq, float _q) { svf->freq = _freq; svf->a = (6.28f * _freq) / SAMPLE_RATE; if (svf->a > 1.0f) { 8001d44: eddf 7a10 vldr s15, [pc, #64] ; 8001d88 svf->freq = _freq; 8001d48: ed80 0a05 vstr s0, [r0, #20] if (svf->a > 1.0f) { 8001d4c: eeb4 0ae7 vcmpe.f32 s0, s15 8001d50: eef1 fa10 vmrs APSR_nzcv, fpscr svf->a = (6.28f * _freq) / SAMPLE_RATE; 8001d54: bfdc itt le 8001d56: eddf 7a0d vldrle s15, [pc, #52] ; 8001d8c 8001d5a: ee20 0a27 vmulle.f32 s0, s0, s15 } if (_q < 0.500f) { _q = 0.500f; } svf->q = 1.0f / _q; 8001d5e: eef6 7a00 vmov.f32 s15, #96 ; 0x3f000000 0.5 8001d62: eef4 0ae7 vcmpe.f32 s1, s15 svf->a = 1.0f; 8001d66: bfc8 it gt 8001d68: eeb7 0a00 vmovgt.f32 s0, #112 ; 0x3f800000 1.0 svf->q = 1.0f / _q; 8001d6c: eef1 fa10 vmrs APSR_nzcv, fpscr 8001d70: bfb8 it lt 8001d72: eef0 0a67 vmovlt.f32 s1, s15 8001d76: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8001d7a: eec7 7a20 vdiv.f32 s15, s14, s1 8001d7e: ed80 0a06 vstr s0, [r0, #24] 8001d82: edc0 7a07 vstr s15, [r0, #28] } 8001d86: 4770 bx lr 8001d88: 4604b210 .word 0x4604b210 8001d8c: 38f6f0f3 .word 0x38f6f0f3 08001d90 : void svf_tick(svf_typedef *svf, float _input) { svf->low = svf->delay2 + svf->a * svf->delay1; 8001d90: edd0 7a03 vldr s15, [r0, #12] 8001d94: edd0 6a06 vldr s13, [r0, #24] 8001d98: ed90 7a04 vldr s14, [r0, #16] 8001d9c: ed90 6a07 vldr s12, [r0, #28] 8001da0: eea6 7aa7 vfma.f32 s14, s13, s15 8001da4: eea7 0ac6 vfms.f32 s0, s15, s12 8001da8: ed80 7a00 vstr s14, [r0] svf->high = _input - svf->low - (svf->q * svf->delay1); 8001dac: ee30 0a47 vsub.f32 s0, s0, s14 svf->band = (svf->a * svf->high) + svf->delay1; svf->delay1 = svf->band; svf->delay2 = svf->low; 8001db0: ed80 7a04 vstr s14, [r0, #16] svf->band = (svf->a * svf->high) + svf->delay1; 8001db4: eee6 7a80 vfma.f32 s15, s13, s0 svf->high = _input - svf->low - (svf->q * svf->delay1); 8001db8: ed80 0a01 vstr s0, [r0, #4] svf->band = (svf->a * svf->high) + svf->delay1; 8001dbc: edc0 7a02 vstr s15, [r0, #8] svf->delay1 = svf->band; 8001dc0: edc0 7a03 vstr s15, [r0, #12] } 8001dc4: 4770 bx lr 8001dc6: bf00 nop 08001dc8 : svf->q = 1.0f / _q; } float svf_get_low(svf_typedef *svf) { return svf->low; } 8001dc8: ed90 0a00 vldr s0, [r0] 8001dcc: 4770 bx lr 8001dce: bf00 nop 08001dd0 : float svf_get_high(svf_typedef *svf) { return svf->high; } 8001dd0: ed90 0a01 vldr s0, [r0, #4] 8001dd4: 4770 bx lr 8001dd6: bf00 nop 08001dd8 : lfo->output = ((((sine_10b[lfo->phase_index >> 22] - 512) * 0.001953125f) * 0.5f) + 0.5f) * _amplitude; //lfo->output = (big_sine_wave[lfo->phase_index >> 22]) >> 5; return lfo->phase_index; } float chorus_tick(float _input) { 8001dd8: b5f8 push {r3, r4, r5, r6, r7, lr} //input highpass svf_tick(&input_highpass, _input); 8001dda: 485e ldr r0, [pc, #376] ; (8001f54 ) // a lil' pad chorus_signal_input = chorus_lp_input * 0.7f; // increment buffer index and wrap chorus_buffer_index_in++; 8001ddc: 4d5e ldr r5, [pc, #376] ; (8001f58 ) if (chorus_buffer_index_in > (CHORUS_BUFFER_LENGTH - 1)) { chorus_buffer_index_in -= CHORUS_BUFFER_LENGTH; } // add feedback buffer_signal_input = chorus_signal_input + (feedback); 8001dde: 4e5f ldr r6, [pc, #380] ; (8001f5c ) chorus_buffer[chorus_buffer_index_in] = buffer_signal_input; lfo_tick(&chorus_lfo, lfo_rate_pot, lfo_amt_pot); // 1p low pass filter the lfo modulation buffer_modulation += ((chorus_lfo.output) - buffer_modulation) * 0.03f; 8001de0: 4c5f ldr r4, [pc, #380] ; (8001f60 ) chorus_buffer[chorus_buffer_index_in] = buffer_signal_input; 8001de2: 4f60 ldr r7, [pc, #384] ; (8001f64 ) svf_tick(&input_highpass, _input); 8001de4: f7ff ffd4 bl 8001d90 chorus_hp_input = svf_get_high(&input_highpass); 8001de8: 485a ldr r0, [pc, #360] ; (8001f54 ) 8001dea: f7ff fff1 bl 8001dd0 8001dee: 4b5e ldr r3, [pc, #376] ; (8001f68 ) svf_tick(&input_lowpass, chorus_hp_input); 8001df0: 485e ldr r0, [pc, #376] ; (8001f6c ) chorus_hp_input = svf_get_high(&input_highpass); 8001df2: ed83 0a00 vstr s0, [r3] svf_tick(&input_lowpass, chorus_hp_input); 8001df6: f7ff ffcb bl 8001d90 chorus_lp_input = svf_get_low(&input_lowpass); 8001dfa: 485c ldr r0, [pc, #368] ; (8001f6c ) 8001dfc: f7ff ffe4 bl 8001dc8 chorus_signal_input = chorus_lp_input * 0.7f; 8001e00: eddf 7a5b vldr s15, [pc, #364] ; 8001f70 chorus_buffer_index_in++; 8001e04: 882b ldrh r3, [r5, #0] chorus_signal_input = chorus_lp_input * 0.7f; 8001e06: 495b ldr r1, [pc, #364] ; (8001f74 ) buffer_signal_input = chorus_signal_input + (feedback); 8001e08: ed96 7a00 vldr s14, [r6] lfo->phase_increment = ((42949.6710f) * (_frequency)); 8001e0c: ed9f 6a5a vldr s12, [pc, #360] ; 8001f78 chorus_lp_input = svf_get_low(&input_lowpass); 8001e10: 485a ldr r0, [pc, #360] ; (8001f7c ) lfo->output = ((((sine_10b[lfo->phase_index >> 22] - 512) * 0.001953125f) * 0.5f) + 0.5f) * _amplitude; 8001e12: eddf 4a5b vldr s9, [pc, #364] ; 8001f80 chorus_lp_input = svf_get_low(&input_lowpass); 8001e16: ed80 0a00 vstr s0, [r0] chorus_signal_input = chorus_lp_input * 0.7f; 8001e1a: ee60 7a27 vmul.f32 s15, s0, s15 chorus_buffer_index_in++; 8001e1e: 1c5a adds r2, r3, #1 8001e20: b292 uxth r2, r2 chorus_signal_input = chorus_lp_input * 0.7f; 8001e22: edc1 7a00 vstr s15, [r1] if (chorus_buffer_index_in > (CHORUS_BUFFER_LENGTH - 1)) { 8001e26: f643 2197 movw r1, #14999 ; 0x3a97 8001e2a: 428a cmp r2, r1 lfo_tick(&chorus_lfo, lfo_rate_pot, lfo_amt_pot); 8001e2c: 4955 ldr r1, [pc, #340] ; (8001f84 ) buffer_modulation += ((chorus_lfo.output) - buffer_modulation) * 0.03f; 8001e2e: edd4 6a00 vldr s13, [r4] 8001e32: ed9f 5a55 vldr s10, [pc, #340] ; 8001f88 buffer_signal_input = chorus_signal_input + (feedback); 8001e36: ee77 7a87 vadd.f32 s15, s15, s14 lfo_tick(&chorus_lfo, lfo_rate_pot, lfo_amt_pot); 8001e3a: ed91 7a00 vldr s14, [r1] 8001e3e: 4953 ldr r1, [pc, #332] ; (8001f8c ) chorus_buffer_index_in -= CHORUS_BUFFER_LENGTH; 8001e40: bf88 it hi 8001e42: f5a3 536a subhi.w r3, r3, #14976 ; 0x3a80 lfo->phase_increment = ((42949.6710f) * (_frequency)); 8001e46: ee27 7a06 vmul.f32 s14, s14, s12 chorus_buffer_index_in -= CHORUS_BUFFER_LENGTH; 8001e4a: bf84 itt hi 8001e4c: 3b17 subhi r3, #23 8001e4e: b29a uxthhi r2, r3 lfo->phase_increment = ((42949.6710f) * (_frequency)); 8001e50: eebc 7ac7 vcvt.u32.f32 s14, s14 8001e54: 4b4e ldr r3, [pc, #312] ; (8001f90 ) lfo_tick(&chorus_lfo, lfo_rate_pot, lfo_amt_pot); 8001e56: ed91 6a00 vldr s12, [r1] lfo->phase_increment = ((42949.6710f) * (_frequency)); 8001e5a: ed83 7a03 vstr s14, [r3, #12] lfo->phase_index += lfo->phase_increment; 8001e5e: 68d9 ldr r1, [r3, #12] 8001e60: 6918 ldr r0, [r3, #16] chorus_buffer_index_in -= CHORUS_BUFFER_LENGTH; 8001e62: 802a strh r2, [r5, #0] lfo->phase_index += lfo->phase_increment; 8001e64: 4401 add r1, r0 8001e66: 6119 str r1, [r3, #16] lfo->output = ((((sine_10b[lfo->phase_index >> 22] - 512) * 0.001953125f) * 0.5f) + 0.5f) * _amplitude; 8001e68: 6919 ldr r1, [r3, #16] 8001e6a: 484a ldr r0, [pc, #296] ; (8001f94 ) 8001e6c: 0d89 lsrs r1, r1, #22 8001e6e: eef6 5a00 vmov.f32 s11, #96 ; 0x3f000000 0.5 8001e72: f830 1011 ldrh.w r1, [r0, r1, lsl #1] // dynamic smooth the delay pot and cv input (summed in control tick) delay_pot_filter = dynamic_smooth_tick(&smooth_delay, delay_pot); 8001e76: 4848 ldr r0, [pc, #288] ; (8001f98 ) lfo->output = ((((sine_10b[lfo->phase_index >> 22] - 512) * 0.001953125f) * 0.5f) + 0.5f) * _amplitude; 8001e78: f5a1 7100 sub.w r1, r1, #512 ; 0x200 8001e7c: ee07 1a10 vmov s14, r1 8001e80: eeb8 7ac7 vcvt.f32.s32 s14, s14 8001e84: eee7 5a24 vfma.f32 s11, s14, s9 8001e88: ee26 7a25 vmul.f32 s14, s12, s11 8001e8c: ed83 7a00 vstr s14, [r3] return lfo->phase_index; 8001e90: 6919 ldr r1, [r3, #16] buffer_modulation += ((chorus_lfo.output) - buffer_modulation) * 0.03f; 8001e92: ed93 7a00 vldr s14, [r3] delay_pot_filter = dynamic_smooth_tick(&smooth_delay, delay_pot); 8001e96: 4b41 ldr r3, [pc, #260] ; (8001f9c ) buffer_modulation += ((chorus_lfo.output) - buffer_modulation) * 0.03f; 8001e98: ee37 7a66 vsub.f32 s14, s14, s13 delay_pot_filter = dynamic_smooth_tick(&smooth_delay, delay_pot); 8001e9c: ed93 0a00 vldr s0, [r3] buffer_modulation += ((chorus_lfo.output) - buffer_modulation) * 0.03f; 8001ea0: eee7 6a05 vfma.f32 s13, s14, s10 chorus_buffer[chorus_buffer_index_in] = buffer_signal_input; 8001ea4: eebd 7ae7 vcvt.s32.f32 s14, s15 buffer_modulation += ((chorus_lfo.output) - buffer_modulation) * 0.03f; 8001ea8: edc4 6a00 vstr s13, [r4] chorus_buffer[chorus_buffer_index_in] = buffer_signal_input; 8001eac: ee17 3a10 vmov r3, s14 8001eb0: f827 3012 strh.w r3, [r7, r2, lsl #1] buffer_signal_input = chorus_signal_input + (feedback); 8001eb4: 4b3a ldr r3, [pc, #232] ; (8001fa0 ) 8001eb6: edc3 7a00 vstr s15, [r3] delay_pot_filter = dynamic_smooth_tick(&smooth_delay, delay_pot); 8001eba: f000 fa1f bl 80022fc 8001ebe: 4a39 ldr r2, [pc, #228] ; (8001fa4 ) // use the lerp to calculate our buffer output sample chorus_signal_output = lerp_int16(chorus_buffer, CHORUS_BUFFER_LENGTH, chorus_buffer_index_in - (buffer_modulation * (1.0f - delay_pot_filter)) - ((delay_pot_filter) * (CHORUS_BUFFER_LENGTH - 1))); 8001ec0: 882b ldrh r3, [r5, #0] delay_pot_filter = dynamic_smooth_tick(&smooth_delay, delay_pot); 8001ec2: ed82 0a00 vstr s0, [r2] chorus_buffer_index_in - (buffer_modulation * (1.0f - delay_pot_filter)) - ((delay_pot_filter) * (CHORUS_BUFFER_LENGTH - 1))); 8001ec6: edd2 7a00 vldr s15, [r2] 8001eca: ee06 3a90 vmov s13, r3 8001ece: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 8001ed2: ee77 7ac7 vsub.f32 s15, s15, s14 8001ed6: eeb8 0ae6 vcvt.f32.s32 s0, s13 8001eda: edd4 6a00 vldr s13, [r4] 8001ede: ed92 7a00 vldr s14, [r2] 8001ee2: eea7 0aa6 vfma.f32 s0, s15, s13 chorus_signal_output = lerp_int16(chorus_buffer, CHORUS_BUFFER_LENGTH, 8001ee6: f643 2198 movw r1, #15000 ; 0x3a98 8001eea: 4638 mov r0, r7 8001eec: eddf 7a2e vldr s15, [pc, #184] ; 8001fa8 8001ef0: eea7 0a67 vfms.f32 s0, s14, s15 8001ef4: f000 fa74 bl 80023e0 // clip if (chorus_signal_output > 2047.0f) { 8001ef8: eddf 7a2c vldr s15, [pc, #176] ; 8001fac 8001efc: eeb4 0ae7 vcmpe.f32 s0, s15 8001f00: eef1 fa10 vmrs APSR_nzcv, fpscr 8001f04: dd16 ble.n 8001f34 chorus_signal_output = 2047.0f; 8001f06: 4b2a ldr r3, [pc, #168] ; (8001fb0 ) 8001f08: eeb0 0a67 vmov.f32 s0, s15 8001f0c: edc3 7a00 vstr s15, [r3] #ifdef NO_FB_FILTER feedback = chorus_signal_output * (feedback_pot * -1.0f); #endif //check for max if (chorus_signal_output > max_sig) { 8001f10: 4b28 ldr r3, [pc, #160] ; (8001fb4 ) feedback = chorus_signal_output * (feedback_pot * -1.0f); 8001f12: 4a29 ldr r2, [pc, #164] ; (8001fb8 ) if (chorus_signal_output > max_sig) { 8001f14: ed93 7a00 vldr s14, [r3] feedback = chorus_signal_output * (feedback_pot * -1.0f); 8001f18: edd2 7a00 vldr s15, [r2] if (chorus_signal_output > max_sig) { 8001f1c: eeb4 7ac0 vcmpe.f32 s14, s0 feedback = chorus_signal_output * (feedback_pot * -1.0f); 8001f20: ee60 7a67 vnmul.f32 s15, s0, s15 if (chorus_signal_output > max_sig) { 8001f24: eef1 fa10 vmrs APSR_nzcv, fpscr feedback = chorus_signal_output * (feedback_pot * -1.0f); 8001f28: edc6 7a00 vstr s15, [r6] max_sig = chorus_signal_output; 8001f2c: bf48 it mi 8001f2e: ed83 0a00 vstrmi s0, [r3] } return chorus_signal_output; } 8001f32: bdf8 pop {r3, r4, r5, r6, r7, pc} if (chorus_signal_output < -2047.0f) { 8001f34: eddf 7a21 vldr s15, [pc, #132] ; 8001fbc chorus_signal_output = -2047.0f; 8001f38: 4b1d ldr r3, [pc, #116] ; (8001fb0 ) if (chorus_signal_output < -2047.0f) { 8001f3a: eeb4 0ae7 vcmpe.f32 s0, s15 8001f3e: eef1 fa10 vmrs APSR_nzcv, fpscr chorus_signal_output = lerp_int16(chorus_buffer, CHORUS_BUFFER_LENGTH, 8001f42: bf52 itee pl 8001f44: ed83 0a00 vstrpl s0, [r3] chorus_signal_output = -2047.0f; 8001f48: eeb0 0a67 vmovmi.f32 s0, s15 8001f4c: edc3 7a00 vstrmi s15, [r3] 8001f50: e7de b.n 8001f10 8001f52: bf00 nop 8001f54: 2000761c .word 0x2000761c 8001f58: 200075c4 .word 0x200075c4 8001f5c: 200075f4 .word 0x200075f4 8001f60: 2000008c .word 0x2000008c 8001f64: 20000094 .word 0x20000094 8001f68: 200075c8 .word 0x200075c8 8001f6c: 2000763c .word 0x2000763c 8001f70: 3f333333 .word 0x3f333333 8001f74: 200075e4 .word 0x200075e4 8001f78: 4727c5ac .word 0x4727c5ac 8001f7c: 200075e0 .word 0x200075e0 8001f80: 3a800000 .word 0x3a800000 8001f84: 20007660 .word 0x20007660 8001f88: 3cf5c28f .word 0x3cf5c28f 8001f8c: 2000765c .word 0x2000765c 8001f90: 200075cc .word 0x200075cc 8001f94: 08006530 .word 0x08006530 8001f98: 2000766c .word 0x2000766c 8001f9c: 200075ec .word 0x200075ec 8001fa0: 20000090 .word 0x20000090 8001fa4: 200075f0 .word 0x200075f0 8001fa8: 466a5c00 .word 0x466a5c00 8001fac: 44ffe000 .word 0x44ffe000 8001fb0: 200075e8 .word 0x200075e8 8001fb4: 20007664 .word 0x20007664 8001fb8: 200075f8 .word 0x200075f8 8001fbc: c4ffe000 .word 0xc4ffe000 08001fc0 : void chorus_control_tick(chorus_params_typedef *chorus) { lfo_rate_pot += ((float_expo_table[chorus->lfo_rate] * 75.0f) - lfo_rate_pot) * 0.03f; 8001fc0: 4b35 ldr r3, [pc, #212] ; (8002098 ) 8001fc2: 88c1 ldrh r1, [r0, #6] 8001fc4: 4a35 ldr r2, [pc, #212] ; (800209c ) 8001fc6: eddf 6a36 vldr s13, [pc, #216] ; 80020a0 8001fca: ed92 7a00 vldr s14, [r2] 8001fce: edd2 7a00 vldr s15, [r2] lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 8001fd2: f8b0 c004 ldrh.w ip, [r0, #4] feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 8001fd6: ed9f 5a33 vldr s10, [pc, #204] ; 80020a4 lfo_rate_pot += ((float_expo_table[chorus->lfo_rate] * 75.0f) - lfo_rate_pot) * 0.03f; 8001fda: eb03 0181 add.w r1, r3, r1, lsl #2 8001fde: ed91 6a00 vldr s12, [r1] lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 8001fe2: 4931 ldr r1, [pc, #196] ; (80020a8 ) lfo_rate_pot += ((float_expo_table[chorus->lfo_rate] * 75.0f) - lfo_rate_pot) * 0.03f; 8001fe4: ee96 7a26 vfnms.f32 s14, s12, s13 lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 8001fe8: eb03 038c add.w r3, r3, ip, lsl #2 feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 8001fec: f8b0 c008 ldrh.w ip, [r0, #8] lfo_rate_pot += ((float_expo_table[chorus->lfo_rate] * 75.0f) - lfo_rate_pot) * 0.03f; 8001ff0: eddf 6a2e vldr s13, [pc, #184] ; 80020ac lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 8001ff4: edd3 5a00 vldr s11, [r3] 8001ff8: ed9f 6a2d vldr s12, [pc, #180] ; 80020b0 float delay_input = chorus->delay + ((chorus->delay_cv - magic_cv_offset) * 0.75f); 8001ffc: 8843 ldrh r3, [r0, #2] 8001ffe: 8800 ldrh r0, [r0, #0] lfo_rate_pot += ((float_expo_table[chorus->lfo_rate] * 75.0f) - lfo_rate_pot) * 0.03f; 8002000: eee7 7a26 vfma.f32 s15, s14, s13 float delay_input = chorus->delay + ((chorus->delay_cv - magic_cv_offset) * 0.75f); 8002004: f2a3 736c subw r3, r3, #1900 ; 0x76c lfo_rate_pot += ((float_expo_table[chorus->lfo_rate] * 75.0f) - lfo_rate_pot) * 0.03f; 8002008: edc2 7a00 vstr s15, [r2] lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 800200c: edd1 7a00 vldr s15, [r1] 8002010: ed91 7a00 vldr s14, [r1] feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 8002014: 4a27 ldr r2, [pc, #156] ; (80020b4 ) lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 8002016: eed5 7a86 vfnms.f32 s15, s11, s12 feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 800201a: ee05 ca90 vmov s11, ip lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 800201e: eea7 7aa6 vfma.f32 s14, s15, s13 float delay_input = chorus->delay + ((chorus->delay_cv - magic_cv_offset) * 0.75f); 8002022: ee07 0a90 vmov s15, r0 lfo_amt_pot += ((float_expo_table[chorus->lfo_amount] * (CHORUS_BUFFER_LENGTH - 1)) - lfo_amt_pot) * 0.03f; 8002026: ed81 7a00 vstr s14, [r1] float delay_input = chorus->delay + ((chorus->delay_cv - magic_cv_offset) * 0.75f); 800202a: ee07 3a10 vmov s14, r3 feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 800202e: ed92 6a00 vldr s12, [r2] } if (delay_input < 0.0f) { delay_input = 0.0f; } delay_pot += (((delay_input) / 1024.0f) - delay_pot) * 0.01f; 8002032: 4b21 ldr r3, [pc, #132] ; (80020b8 ) feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 8002034: eef8 5ae5 vcvt.f32.s32 s11, s11 float delay_input = chorus->delay + ((chorus->delay_cv - magic_cv_offset) * 0.75f); 8002038: eeb8 7ac7 vcvt.f32.s32 s14, s14 800203c: eef8 7ae7 vcvt.f32.s32 s15, s15 feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 8002040: ee95 6a85 vfnms.f32 s12, s11, s10 float delay_input = chorus->delay + ((chorus->delay_cv - magic_cv_offset) * 0.75f); 8002044: eef6 5a08 vmov.f32 s11, #104 ; 0x3f400000 0.750 8002048: eee7 7a25 vfma.f32 s15, s14, s11 feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 800204c: ed92 7a00 vldr s14, [r2] delay_pot += (((delay_input) / 1024.0f) - delay_pot) * 0.01f; 8002050: eddf 5a1a vldr s11, [pc, #104] ; 80020bc feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 8002054: eea6 7a26 vfma.f32 s14, s12, s13 delay_pot += (((delay_input) / 1024.0f) - delay_pot) * 0.01f; 8002058: eef4 7ae5 vcmpe.f32 s15, s11 800205c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002060: bf88 it hi 8002062: eef0 7a65 vmovhi.f32 s15, s11 feedback_pot += ((chorus->feedback / 1024.0f) - feedback_pot) * 0.03f; 8002066: ed82 7a00 vstr s14, [r2] delay_pot += (((delay_input) / 1024.0f) - delay_pot) * 0.01f; 800206a: eddf 6a15 vldr s13, [pc, #84] ; 80020c0 800206e: ed93 7a00 vldr s14, [r3] 8002072: eef5 7ac0 vcmpe.f32 s15, #0.0 8002076: eef1 fa10 vmrs APSR_nzcv, fpscr 800207a: bfb8 it lt 800207c: eef0 7a66 vmovlt.f32 s15, s13 8002080: ee97 7a85 vfnms.f32 s14, s15, s10 8002084: eddf 6a0f vldr s13, [pc, #60] ; 80020c4 8002088: edd3 7a00 vldr s15, [r3] 800208c: eee7 7a26 vfma.f32 s15, s14, s13 8002090: edc3 7a00 vstr s15, [r3] } 8002094: 4770 bx lr 8002096: bf00 nop 8002098: 08006d30 .word 0x08006d30 800209c: 20007660 .word 0x20007660 80020a0: 42960000 .word 0x42960000 80020a4: 3a800000 .word 0x3a800000 80020a8: 2000765c .word 0x2000765c 80020ac: 3cf5c28f .word 0x3cf5c28f 80020b0: 466a5c00 .word 0x466a5c00 80020b4: 200075f8 .word 0x200075f8 80020b8: 200075ec .word 0x200075ec 80020bc: 447fc000 .word 0x447fc000 80020c0: 00000000 .word 0x00000000 80020c4: 3c23d70a .word 0x3c23d70a 080020c8 : void chorus_init() { 80020c8: b508 push {r3, lr} dynamic_smooth_init(&smooth_delay, 0.05f, 0.5f); 80020ca: ed9f 0a0f vldr s0, [pc, #60] ; 8002108 80020ce: 480f ldr r0, [pc, #60] ; (800210c ) 80020d0: eef6 0a00 vmov.f32 s1, #96 ; 0x3f000000 0.5 80020d4: f000 f8de bl 8002294 svf_init(&input_lowpass, LP_INPUT_CUTOFF, 0.707f); 80020d8: eddf 0a0d vldr s1, [pc, #52] ; 8002110 80020dc: ed9f 0a0d vldr s0, [pc, #52] ; 8002114 80020e0: 480d ldr r0, [pc, #52] ; (8002118 ) 80020e2: f7ff fe2f bl 8001d44 svf_init(&input_highpass, HP_INPUT_CUTOFF, 1.5f); 80020e6: ed9f 0a0d vldr s0, [pc, #52] ; 800211c 80020ea: 480d ldr r0, [pc, #52] ; (8002120 ) 80020ec: eef7 0a08 vmov.f32 s1, #120 ; 0x3fc00000 1.5 80020f0: f7ff fe28 bl 8001d44 svf_init(&feedback_svf, FB_SVF_CUTOFF, 1.0f); } 80020f4: e8bd 4008 ldmia.w sp!, {r3, lr} svf_init(&feedback_svf, FB_SVF_CUTOFF, 1.0f); 80020f8: ed9f 0a0a vldr s0, [pc, #40] ; 8002124 80020fc: 480a ldr r0, [pc, #40] ; (8002128 ) 80020fe: eef7 0a00 vmov.f32 s1, #112 ; 0x3f800000 1.0 8002102: f7ff be1f b.w 8001d44 8002106: bf00 nop 8002108: 3d4ccccd .word 0x3d4ccccd 800210c: 2000766c .word 0x2000766c 8002110: 3f34fdf4 .word 0x3f34fdf4 8002114: 45fa0000 .word 0x45fa0000 8002118: 2000763c .word 0x2000763c 800211c: 43160000 .word 0x43160000 8002120: 2000761c .word 0x2000761c 8002124: 459c4000 .word 0x459c4000 8002128: 200075fc .word 0x200075fc 0800212c : DAC_HandleTypeDef hdac1; /* DAC1 init function */ void MX_DAC1_Init(void) { 800212c: b500 push {lr} 800212e: b08d sub sp, #52 ; 0x34 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8002130: 2230 movs r2, #48 ; 0x30 8002132: 2100 movs r1, #0 8002134: 4668 mov r0, sp 8002136: f004 f963 bl 8006400 /* USER CODE BEGIN DAC1_Init 1 */ /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 800213a: 4815 ldr r0, [pc, #84] ; (8002190 ) 800213c: 4b15 ldr r3, [pc, #84] ; (8002194 ) 800213e: 6003 str r3, [r0, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8002140: f001 fa7c bl 800363c 8002144: b9c8 cbnz r0, 800217a { Error_Handler(); } /** DAC channel OUT1 config */ sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; 8002146: 2102 movs r1, #2 sConfig.DAC_DMADoubleDataMode = DISABLE; 8002148: 2200 movs r2, #0 sConfig.DAC_SignedFormat = DISABLE; sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; sConfig.DAC_Trigger = DAC_TRIGGER_NONE; sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE; sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_EXTERNAL; 800214a: 2301 movs r3, #1 sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; 800214c: 9100 str r1, [sp, #0] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 800214e: 4810 ldr r0, [pc, #64] ; (8002190 ) sConfig.DAC_DMADoubleDataMode = DISABLE; 8002150: f8ad 2004 strh.w r2, [sp, #4] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8002154: 4669 mov r1, sp sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8002156: e9cd 2202 strd r2, r2, [sp, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 800215a: e9cd 2204 strd r2, r2, [sp, #16] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_EXTERNAL; 800215e: 9306 str r3, [sp, #24] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8002160: 9207 str r2, [sp, #28] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8002162: f001 facf bl 8003704 8002166: b980 cbnz r0, 800218a { Error_Handler(); } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8002168: 4809 ldr r0, [pc, #36] ; (8002190 ) 800216a: 2210 movs r2, #16 800216c: 4669 mov r1, sp 800216e: f001 fac9 bl 8003704 8002172: b928 cbnz r0, 8002180 } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8002174: b00d add sp, #52 ; 0x34 8002176: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 800217a: f000 fa27 bl 80025cc 800217e: e7e2 b.n 8002146 Error_Handler(); 8002180: f000 fa24 bl 80025cc } 8002184: b00d add sp, #52 ; 0x34 8002186: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 800218a: f000 fa1f bl 80025cc 800218e: e7eb b.n 8002168 8002190: 20007960 .word 0x20007960 8002194: 50000800 .word 0x50000800 08002198 : void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) { 8002198: b500 push {lr} GPIO_InitTypeDef GPIO_InitStruct = {0}; if(dacHandle->Instance==DAC1) 800219a: 4a1b ldr r2, [pc, #108] ; (8002208 ) 800219c: 6801 ldr r1, [r0, #0] { 800219e: b089 sub sp, #36 ; 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80021a0: 2300 movs r3, #0 if(dacHandle->Instance==DAC1) 80021a2: 4291 cmp r1, r2 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80021a4: e9cd 3302 strd r3, r3, [sp, #8] 80021a8: e9cd 3304 strd r3, r3, [sp, #16] 80021ac: 9306 str r3, [sp, #24] if(dacHandle->Instance==DAC1) 80021ae: d002 beq.n 80021b6 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 80021b0: b009 add sp, #36 ; 0x24 80021b2: f85d fb04 ldr.w pc, [sp], #4 __HAL_RCC_DAC1_CLK_ENABLE(); 80021b6: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 80021ba: f503 3304 add.w r3, r3, #135168 ; 0x21000 GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80021be: ed9f 7b10 vldr d7, [pc, #64] ; 8002200 __HAL_RCC_DAC1_CLK_ENABLE(); 80021c2: 6cda ldr r2, [r3, #76] ; 0x4c 80021c4: f442 3280 orr.w r2, r2, #65536 ; 0x10000 80021c8: 64da str r2, [r3, #76] ; 0x4c 80021ca: 6cda ldr r2, [r3, #76] ; 0x4c 80021cc: f402 3280 and.w r2, r2, #65536 ; 0x10000 80021d0: 9200 str r2, [sp, #0] 80021d2: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOA_CLK_ENABLE(); 80021d4: 6cda ldr r2, [r3, #76] ; 0x4c 80021d6: f042 0201 orr.w r2, r2, #1 80021da: 64da str r2, [r3, #76] ; 0x4c 80021dc: 6cdb ldr r3, [r3, #76] ; 0x4c 80021de: f003 0301 and.w r3, r3, #1 80021e2: 9301 str r3, [sp, #4] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80021e4: a902 add r1, sp, #8 80021e6: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80021ea: ed8d 7b02 vstr d7, [sp, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 80021ee: 9b01 ldr r3, [sp, #4] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80021f0: f001 fcb2 bl 8003b58 } 80021f4: b009 add sp, #36 ; 0x24 80021f6: f85d fb04 ldr.w pc, [sp], #4 80021fa: bf00 nop 80021fc: f3af 8000 nop.w 8002200: 00000030 .word 0x00000030 8002204: 00000003 .word 0x00000003 8002208: 50000800 .word 0x50000800 0800220c : } } /* USER CODE BEGIN 1 */ void DAC_Start() { 800220c: b510 push {r4, lr} HAL_DAC_Start(&hdac1, DAC_CHANNEL_1); 800220e: 4c0c ldr r4, [pc, #48] ; (8002240 ) 8002210: 2100 movs r1, #0 8002212: 4620 mov r0, r4 8002214: f001 fa28 bl 8003668 HAL_DAC_Start(&hdac1, DAC_CHANNEL_2); 8002218: 2110 movs r1, #16 800221a: 4620 mov r0, r4 800221c: f001 fa24 bl 8003668 HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 2047); 8002220: 2200 movs r2, #0 8002222: 4611 mov r1, r2 8002224: f240 73ff movw r3, #2047 ; 0x7ff 8002228: 4620 mov r0, r4 800222a: f001 fa53 bl 80036d4 HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, 2047); 800222e: 4620 mov r0, r4 8002230: f240 73ff movw r3, #2047 ; 0x7ff } 8002234: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, 2047); 8002238: 2200 movs r2, #0 800223a: 2110 movs r1, #16 800223c: f001 ba4a b.w 80036d4 8002240: 20007960 .word 0x20007960 08002244 : */ void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); 8002244: 4b12 ldr r3, [pc, #72] ; (8002290 ) { 8002246: b510 push {r4, lr} __HAL_RCC_DMAMUX1_CLK_ENABLE(); 8002248: 6c98 ldr r0, [r3, #72] ; 0x48 800224a: f040 0004 orr.w r0, r0, #4 800224e: 6498 str r0, [r3, #72] ; 0x48 8002250: 6c9c ldr r4, [r3, #72] ; 0x48 { 8002252: b082 sub sp, #8 __HAL_RCC_DMAMUX1_CLK_ENABLE(); 8002254: f004 0404 and.w r4, r4, #4 8002258: 9400 str r4, [sp, #0] 800225a: 9c00 ldr r4, [sp, #0] __HAL_RCC_DMA1_CLK_ENABLE(); 800225c: 6c9c ldr r4, [r3, #72] ; 0x48 /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 800225e: 2101 movs r1, #1 __HAL_RCC_DMA1_CLK_ENABLE(); 8002260: 430c orrs r4, r1 8002262: 649c str r4, [r3, #72] ; 0x48 8002264: 6c9b ldr r3, [r3, #72] ; 0x48 8002266: 400b ands r3, r1 HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 8002268: 2200 movs r2, #0 __HAL_RCC_DMA1_CLK_ENABLE(); 800226a: 9301 str r3, [sp, #4] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 800226c: 200b movs r0, #11 __HAL_RCC_DMA1_CLK_ENABLE(); 800226e: 9b01 ldr r3, [sp, #4] HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 1, 0); 8002270: f001 f97e bl 8003570 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 8002274: 200b movs r0, #11 8002276: f001 f9b9 bl 80035ec /* DMA1_Channel2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 2, 0); 800227a: 200c movs r0, #12 800227c: 2200 movs r2, #0 800227e: 2102 movs r1, #2 8002280: f001 f976 bl 8003570 HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 8002284: 200c movs r0, #12 } 8002286: b002 add sp, #8 8002288: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); 800228c: f001 b9ae b.w 80035ec 8002290: 40021000 .word 0x40021000 08002294 : } else { return a; } } void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity) { 8002294: b510 push {r4, lr} float basefreq, wc, gc; //init values basefreq = _base; wc = basefreq / DYN_SMOOTH_SAMPLE_RATE; gc = tan(3.14f * wc); 8002296: eddf 7a18 vldr s15, [pc, #96] ; 80022f8 800229a: ee60 7a27 vmul.f32 s15, s0, s15 void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity) { 800229e: 4604 mov r4, r0 80022a0: ed2d 8b02 vpush {d8} gc = tan(3.14f * wc); 80022a4: ee17 0a90 vmov r0, s15 void dynamic_smooth_init(dynamic_smooth* _smooth, float _base, float _sensitivity) { 80022a8: eeb0 8a60 vmov.f32 s16, s1 gc = tan(3.14f * wc); 80022ac: f7fe f918 bl 80004e0 <__aeabi_f2d> 80022b0: ec41 0b10 vmov d0, r0, r1 80022b4: f003 f804 bl 80052c0 80022b8: ec51 0b10 vmov r0, r1, d0 80022bc: f7fe fc2a bl 8000b14 <__aeabi_d2f> 80022c0: ee07 0a90 vmov s15, r0 _smooth->g0 = 2*gc/(1+gc); 80022c4: eeb7 7a00 vmov.f32 s14, #112 ; 0x3f800000 1.0 80022c8: ee37 6aa7 vadd.f32 s12, s15, s15 80022cc: ee77 7a87 vadd.f32 s15, s15, s14 _smooth->sense = _sensitivity * 4.0f; 80022d0: eef1 6a00 vmov.f32 s13, #16 ; 0x40800000 4.0 _smooth->g0 = 2*gc/(1+gc); 80022d4: ee86 7a27 vdiv.f32 s14, s12, s15 //tick values _smooth->low1 = 0.0f; 80022d8: 2300 movs r3, #0 80022da: 60a3 str r3, [r4, #8] _smooth->low2 = 0.0f; 80022dc: 60e3 str r3, [r4, #12] _smooth->low1z = 0.0f; 80022de: 6123 str r3, [r4, #16] _smooth->low2z = 0.0f; 80022e0: 6163 str r3, [r4, #20] _smooth->bandz = 0.0f; 80022e2: 61a3 str r3, [r4, #24] _smooth->out = 0.0f; 80022e4: 61e3 str r3, [r4, #28] _smooth->sense = _sensitivity * 4.0f; 80022e6: ee28 8a26 vmul.f32 s16, s16, s13 _smooth->g0 = 2*gc/(1+gc); 80022ea: ed84 7a00 vstr s14, [r4] _smooth->sense = _sensitivity * 4.0f; 80022ee: ed84 8a01 vstr s16, [r4, #4] } 80022f2: ecbd 8b02 vpop {d8} 80022f6: bd10 pop {r4, pc} 80022f8: 38787e24 .word 0x38787e24 080022fc : float dynamic_smooth_tick(dynamic_smooth* _smooth, float in) { float g; _smooth->low1z = _smooth->low1; 80022fc: edd0 6a02 vldr s13, [r0, #8] _smooth->low2z = _smooth->low2; 8002300: edd0 7a03 vldr s15, [r0, #12] _smooth->bandz = _smooth->low2z - _smooth->low1z; g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); 8002304: ed90 6a01 vldr s12, [r0, #4] 8002308: ed90 7a00 vldr s14, [r0] _smooth->low1z = _smooth->low1; 800230c: edc0 6a04 vstr s13, [r0, #16] _smooth->bandz = _smooth->low2z - _smooth->low1z; 8002310: ee77 5ae6 vsub.f32 s11, s15, s13 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8002314: ee30 0a66 vsub.f32 s0, s0, s13 g = cm_min(_smooth->g0 + _smooth->sense*cm_abs(_smooth->bandz), 1.0f); 8002318: eeb0 5ae5 vabs.f32 s10, s11 800231c: eea5 7a06 vfma.f32 s14, s10, s12 return ((a) < (b) ? a : b); 8002320: eeb7 6a00 vmov.f32 s12, #112 ; 0x3f800000 1.0 8002324: eeb4 7ac6 vcmpe.f32 s14, s12 8002328: eef1 fa10 vmrs APSR_nzcv, fpscr 800232c: bf88 it hi 800232e: eeb0 7a46 vmovhi.f32 s14, s12 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 8002332: eeb0 6a66 vmov.f32 s12, s13 8002336: eea0 6a07 vfma.f32 s12, s0, s14 _smooth->low2z = _smooth->low2; 800233a: edc0 7a05 vstr s15, [r0, #20] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 800233e: ee76 6a67 vsub.f32 s13, s12, s15 _smooth->bandz = _smooth->low2z - _smooth->low1z; 8002342: edc0 5a06 vstr s11, [r0, #24] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 8002346: eee6 7a87 vfma.f32 s15, s13, s14 _smooth->low1 = _smooth->low1z + g*(in-_smooth->low1z); 800234a: ed80 6a02 vstr s12, [r0, #8] _smooth->low2 = _smooth->low2z + g*(_smooth->low1 - _smooth->low2z); 800234e: eeb0 0a67 vmov.f32 s0, s15 8002352: edc0 7a03 vstr s15, [r0, #12] return _smooth->low2; } 8002356: 4770 bx lr 08002358 : /* USER CODE END 1 */ /** Configure pins */ void MX_GPIO_Init(void) { 8002358: b5f0 push {r4, r5, r6, r7, lr} GPIO_InitTypeDef GPIO_InitStruct = {0}; 800235a: 2400 movs r4, #0 { 800235c: b089 sub sp, #36 ; 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800235e: e9cd 4402 strd r4, r4, [sp, #8] 8002362: e9cd 4404 strd r4, r4, [sp, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8002366: 4b1c ldr r3, [pc, #112] ; (80023d8 ) GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002368: 9406 str r4, [sp, #24] __HAL_RCC_GPIOA_CLK_ENABLE(); 800236a: 6cd9 ldr r1, [r3, #76] ; 0x4c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, MUX_C_Pin|MUX_B_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(MUX_A_GPIO_Port, MUX_A_Pin, GPIO_PIN_RESET); 800236c: 4d1b ldr r5, [pc, #108] ; (80023dc ) __HAL_RCC_GPIOA_CLK_ENABLE(); 800236e: f041 0101 orr.w r1, r1, #1 8002372: 64d9 str r1, [r3, #76] ; 0x4c 8002374: 6cd9 ldr r1, [r3, #76] ; 0x4c 8002376: f001 0101 and.w r1, r1, #1 800237a: 9100 str r1, [sp, #0] 800237c: 9900 ldr r1, [sp, #0] __HAL_RCC_GPIOB_CLK_ENABLE(); 800237e: 6cd9 ldr r1, [r3, #76] ; 0x4c 8002380: f041 0102 orr.w r1, r1, #2 8002384: 64d9 str r1, [r3, #76] ; 0x4c 8002386: 6cdb ldr r3, [r3, #76] ; 0x4c 8002388: f003 0302 and.w r3, r3, #2 HAL_GPIO_WritePin(GPIOA, MUX_C_Pin|MUX_B_Pin, GPIO_PIN_RESET); 800238c: 4622 mov r2, r4 __HAL_RCC_GPIOB_CLK_ENABLE(); 800238e: 9301 str r3, [sp, #4] HAL_GPIO_WritePin(GPIOA, MUX_C_Pin|MUX_B_Pin, GPIO_PIN_RESET); 8002390: 21c0 movs r1, #192 ; 0xc0 8002392: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002396: 9b01 ldr r3, [sp, #4] HAL_GPIO_WritePin(GPIOA, MUX_C_Pin|MUX_B_Pin, GPIO_PIN_RESET); 8002398: f001 fcd8 bl 8003d4c HAL_GPIO_WritePin(MUX_A_GPIO_Port, MUX_A_Pin, GPIO_PIN_RESET); 800239c: 4622 mov r2, r4 800239e: 4628 mov r0, r5 80023a0: 2101 movs r1, #1 80023a2: f001 fcd3 bl 8003d4c /*Configure GPIO pins : PAPin PAPin */ GPIO_InitStruct.Pin = MUX_C_Pin|MUX_B_Pin; 80023a6: 2600 movs r6, #0 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80023a8: a902 add r1, sp, #8 GPIO_InitStruct.Pin = MUX_C_Pin|MUX_B_Pin; 80023aa: 22c0 movs r2, #192 ; 0xc0 80023ac: 2301 movs r3, #1 80023ae: 2700 movs r7, #0 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80023b0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = MUX_C_Pin|MUX_B_Pin; 80023b4: e9cd 2302 strd r2, r3, [sp, #8] 80023b8: e9cd 6704 strd r6, r7, [sp, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80023bc: f001 fbcc bl 8003b58 /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = MUX_A_Pin; 80023c0: 2201 movs r2, #1 80023c2: 2301 movs r3, #1 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(MUX_A_GPIO_Port, &GPIO_InitStruct); 80023c4: a902 add r1, sp, #8 80023c6: 4628 mov r0, r5 GPIO_InitStruct.Pin = MUX_A_Pin; 80023c8: e9cd 6704 strd r6, r7, [sp, #16] 80023cc: e9cd 2302 strd r2, r3, [sp, #8] HAL_GPIO_Init(MUX_A_GPIO_Port, &GPIO_InitStruct); 80023d0: f001 fbc2 bl 8003b58 } 80023d4: b009 add sp, #36 ; 0x24 80023d6: bdf0 pop {r4, r5, r6, r7, pc} 80023d8: 40021000 .word 0x40021000 80023dc: 48000400 .word 0x48000400 080023e0 : float lerp_int16(int16_t _buf[], uint16_t _bufsize, float position) { uint16_t integer_part; float float_part; int16_t this_sample, next_sample; if (position < 0.0f) { 80023e0: eeb5 0ac0 vcmpe.f32 s0, #0.0 80023e4: eef1 fa10 vmrs APSR_nzcv, fpscr float lerp_int16(int16_t _buf[], uint16_t _bufsize, float position) { 80023e8: b500 push {lr} if (position < 0.0f) { 80023ea: d505 bpl.n 80023f8 position += _bufsize; 80023ec: ee07 1a90 vmov s15, r1 80023f0: eef8 7ae7 vcvt.f32.s32 s15, s15 80023f4: ee30 0a27 vadd.f32 s0, s0, s15 } if (position > (_bufsize - 1)) { 80023f8: f101 3cff add.w ip, r1, #4294967295 ; 0xffffffff 80023fc: ee07 ca90 vmov s15, ip 8002400: eef8 7ae7 vcvt.f32.s32 s15, s15 8002404: eef4 7ac0 vcmpe.f32 s15, s0 8002408: eef1 fa10 vmrs APSR_nzcv, fpscr 800240c: d505 bpl.n 800241a position -= _bufsize; 800240e: ee07 1a90 vmov s15, r1 8002412: eef8 7ae7 vcvt.f32.s32 s15, s15 8002416: ee30 0a67 vsub.f32 s0, s0, s15 } integer_part = (uint16_t) (position); 800241a: eefc 7ac0 vcvt.u32.f32 s15, s0 800241e: ee17 3a90 vmov r3, s15 8002422: b29b uxth r3, r3 float_part = position - integer_part; 8002424: ee07 3a90 vmov s15, r3 8002428: eef8 7ae7 vcvt.f32.s32 s15, s15 this_sample = _buf[integer_part]; if (integer_part < (_bufsize - 1)) { 800242c: 459c cmp ip, r3 float_part = position - integer_part; 800242e: ee70 7a67 vsub.f32 s15, s0, s15 this_sample = _buf[integer_part]; 8002432: f930 2013 ldrsh.w r2, [r0, r3, lsl #1] 8002436: ea4f 0e43 mov.w lr, r3, lsl #1 if (integer_part < (_bufsize - 1)) { 800243a: dd0f ble.n 800245c next_sample = _buf[integer_part + 1]; 800243c: 4470 add r0, lr 800243e: f9b0 3002 ldrsh.w r3, [r0, #2] } else { next_sample = _buf[(integer_part + 1) - _bufsize]; } return (((next_sample - this_sample) * float_part) + this_sample); 8002442: 1a9b subs r3, r3, r2 8002444: ee07 3a10 vmov s14, r3 8002448: ee06 2a90 vmov s13, r2 800244c: eeb8 7ac7 vcvt.f32.s32 s14, s14 8002450: eeb8 0ae6 vcvt.f32.s32 s0, s13 } 8002454: eea7 0a27 vfma.f32 s0, s14, s15 8002458: f85d fb04 ldr.w pc, [sp], #4 next_sample = _buf[(integer_part + 1) - _bufsize]; 800245c: 3301 adds r3, #1 800245e: 1a59 subs r1, r3, r1 8002460: f930 3011 ldrsh.w r3, [r0, r1, lsl #1] 8002464: e7ed b.n 8002442 8002466: bf00 nop 08002468 <_Z18SystemClock_Configv>: /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8002468: b510 push {r4, lr} 800246a: b094 sub sp, #80 ; 0x50 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800246c: 2238 movs r2, #56 ; 0x38 800246e: 2100 movs r1, #0 8002470: a806 add r0, sp, #24 8002472: f003 ffc5 bl 8006400 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8002476: 2300 movs r3, #0 /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8002478: f44f 7000 mov.w r0, #512 ; 0x200 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800247c: e9cd 3300 strd r3, r3, [sp] 8002480: e9cd 3302 strd r3, r3, [sp, #8] 8002484: 9304 str r3, [sp, #16] HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8002486: f001 fc67 bl 8003d58 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800248a: f44f 7280 mov.w r2, #256 ; 0x100 800248e: 9209 str r2, [sp, #36] ; 0x24 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8002490: 2240 movs r2, #64 ; 0x40 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 8002492: 2401 movs r4, #1 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8002494: 920a str r2, [sp, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLN = 12; 8002496: 220c movs r2, #12 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8002498: 2302 movs r3, #2 RCC_OscInitStruct.PLL.PLLN = 12; 800249a: e9cd 420f strd r4, r2, [sp, #60] ; 0x3c RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800249e: a806 add r0, sp, #24 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4; 80024a0: 2204 movs r2, #4 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 80024a2: e9cd 330d strd r3, r3, [sp, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 80024a6: e9cd 3311 strd r3, r3, [sp, #68] ; 0x44 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 80024aa: 9306 str r3, [sp, #24] RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4; 80024ac: 9213 str r2, [sp, #76] ; 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80024ae: f001 fcd1 bl 8003e54 80024b2: b108 cbz r0, 80024b8 <_Z18SystemClock_Configv+0x50> \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80024b4: b672 cpsid i void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { 80024b6: e7fe b.n 80024b6 <_Z18SystemClock_Configv+0x4e> RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80024b8: ed9f 7b09 vldr d7, [pc, #36] ; 80024e0 <_Z18SystemClock_Configv+0x78> 80024bc: ed8d 7b00 vstr d7, [sp] 80024c0: ed9f 7b09 vldr d7, [pc, #36] ; 80024e8 <_Z18SystemClock_Configv+0x80> 80024c4: 4603 mov r3, r0 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80024c6: 4621 mov r1, r4 80024c8: 4668 mov r0, sp RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80024ca: ed8d 7b02 vstr d7, [sp, #8] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80024ce: 9304 str r3, [sp, #16] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80024d0: f001 ff44 bl 800435c 80024d4: b108 cbz r0, 80024da <_Z18SystemClock_Configv+0x72> 80024d6: b672 cpsid i while (1) { 80024d8: e7fe b.n 80024d8 <_Z18SystemClock_Configv+0x70> } 80024da: b014 add sp, #80 ; 0x50 80024dc: bd10 pop {r4, pc} 80024de: bf00 nop 80024e0: 0000000f .word 0x0000000f 80024e4: 00000003 .word 0x00000003 ... 080024f0
: { 80024f0: b508 push {r3, lr} HAL_Init(); 80024f2: f000 fb1f bl 8002b34 SystemClock_Config(); 80024f6: f7ff ffb7 bl 8002468 <_Z18SystemClock_Configv> MX_GPIO_Init(); 80024fa: f7ff ff2d bl 8002358 MX_DMA_Init(); 80024fe: f7ff fea1 bl 8002244 MX_ADC1_Init(); 8002502: f7ff fac5 bl 8001a90 MX_ADC2_Init(); 8002506: f7ff fb17 bl 8001b38 MX_DAC1_Init(); 800250a: f7ff fe0f bl 800212c MX_TIM2_Init(); 800250e: f000 f9ef bl 80028f0 MX_TIM1_Init(); 8002512: f000 f941 bl 8002798 MX_TIM3_Init(); 8002516: f000 fa25 bl 8002964 DAC_Start(); 800251a: f7ff fe77 bl 800220c ADC1_Start(); 800251e: f7ff fbfd bl 8001d1c ADC2_Start(); 8002522: f7ff fc05 bl 8001d30 TIM1_Start(); 8002526: f000 faa3 bl 8002a70 TIM2_Start(); 800252a: f000 faa7 bl 8002a7c TIM3_Start(); 800252e: f000 faab bl 8002a88 CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 8002532: 4908 ldr r1, [pc, #32] ; (8002554 ) DWT->CYCCNT = 0; 8002534: 4b08 ldr r3, [pc, #32] ; (8002558 ) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 8002536: f8d1 20fc ldr.w r2, [r1, #252] ; 0xfc DWT->CYCCNT = 0; 800253a: 2000 movs r0, #0 CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 800253c: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000 8002540: f8c1 20fc str.w r2, [r1, #252] ; 0xfc DWT->CYCCNT = 0; 8002544: 6058 str r0, [r3, #4] DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; 8002546: 681a ldr r2, [r3, #0] 8002548: f042 0201 orr.w r2, r2, #1 800254c: 601a str r2, [r3, #0] chorus_init(); 800254e: f7ff fdbb bl 80020c8 while (1) { 8002552: e7fe b.n 8002552 8002554: e000ed00 .word 0xe000ed00 8002558: e0001000 .word 0xe0001000 0800255c : if (hadc->Instance == ADC1) { 800255c: 6803 ldr r3, [r0, #0] 800255e: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8002562: d000 beq.n 8002566 8002564: 4770 bx lr void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 8002566: b510 push {r4, lr} ADC1_channel_data[mux_channel++] = ADC1_raw_data; 8002568: 4b14 ldr r3, [pc, #80] ; (80025bc ) 800256a: 4c15 ldr r4, [pc, #84] ; (80025c0 ) 800256c: 881a ldrh r2, [r3, #0] 800256e: 7823 ldrb r3, [r4, #0] HAL_GPIO_WritePin(MUX_A_GPIO_Port, MUX_A_Pin, 8002570: 4814 ldr r0, [pc, #80] ; (80025c4 ) ADC1_channel_data[mux_channel++] = ADC1_raw_data; 8002572: b2d9 uxtb r1, r3 8002574: 3301 adds r3, #1 8002576: b2db uxtb r3, r3 8002578: 7023 strb r3, [r4, #0] 800257a: 4b13 ldr r3, [pc, #76] ; (80025c8 ) 800257c: b292 uxth r2, r2 800257e: f823 2011 strh.w r2, [r3, r1, lsl #1] if (mux_channel > NUM_ADC1_CHANNELS) { 8002582: 7823 ldrb r3, [r4, #0] 8002584: 2b05 cmp r3, #5 mux_channel = 0; 8002586: bf84 itt hi 8002588: 2300 movhi r3, #0 800258a: 7023 strbhi r3, [r4, #0] (GPIO_PinState) (mux_channel & 1)); 800258c: 7822 ldrb r2, [r4, #0] HAL_GPIO_WritePin(MUX_A_GPIO_Port, MUX_A_Pin, 800258e: 2101 movs r1, #1 8002590: f002 0201 and.w r2, r2, #1 8002594: f001 fbda bl 8003d4c (GPIO_PinState) ((mux_channel >> 1) & 1)); 8002598: 7822 ldrb r2, [r4, #0] HAL_GPIO_WritePin(MUX_B_GPIO_Port, MUX_B_Pin, 800259a: 2180 movs r1, #128 ; 0x80 800259c: f3c2 0240 ubfx r2, r2, #1, #1 80025a0: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 80025a4: f001 fbd2 bl 8003d4c (GPIO_PinState) ((mux_channel >> 2) & 1)); 80025a8: 7822 ldrb r2, [r4, #0] HAL_GPIO_WritePin(MUX_C_GPIO_Port, MUX_C_Pin, 80025aa: 2140 movs r1, #64 ; 0x40 } 80025ac: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_GPIO_WritePin(MUX_C_GPIO_Port, MUX_C_Pin, 80025b0: f3c2 0280 ubfx r2, r2, #2, #1 80025b4: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 80025b8: f001 bbc8 b.w 8003d4c 80025bc: 20000086 .word 0x20000086 80025c0: 20007668 .word 0x20007668 80025c4: 48000400 .word 0x48000400 80025c8: 2000007c .word 0x2000007c 080025cc : 80025cc: b672 cpsid i while (1) { 80025ce: e7fe b.n 80025ce 080025d0 : { /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 80025d0: 4b0b ldr r3, [pc, #44] ; (8002600 ) 80025d2: 6e1a ldr r2, [r3, #96] ; 0x60 80025d4: f042 0201 orr.w r2, r2, #1 80025d8: 661a str r2, [r3, #96] ; 0x60 80025da: 6e1a ldr r2, [r3, #96] ; 0x60 { 80025dc: b082 sub sp, #8 __HAL_RCC_SYSCFG_CLK_ENABLE(); 80025de: f002 0201 and.w r2, r2, #1 80025e2: 9200 str r2, [sp, #0] 80025e4: 9a00 ldr r2, [sp, #0] __HAL_RCC_PWR_CLK_ENABLE(); 80025e6: 6d9a ldr r2, [r3, #88] ; 0x58 80025e8: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 80025ec: 659a str r2, [r3, #88] ; 0x58 80025ee: 6d9b ldr r3, [r3, #88] ; 0x58 80025f0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80025f4: 9301 str r3, [sp, #4] 80025f6: 9b01 ldr r3, [sp, #4] HAL_PWREx_DisableUCPDDeadBattery(); /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80025f8: b002 add sp, #8 HAL_PWREx_DisableUCPDDeadBattery(); 80025fa: f001 bc23 b.w 8003e44 80025fe: bf00 nop 8002600: 40021000 .word 0x40021000 08002604 : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) { 8002604: e7fe b.n 8002604 8002606: bf00 nop 08002608 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002608: e7fe b.n 8002608 800260a: bf00 nop 0800260c : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800260c: e7fe b.n 800260c 800260e: bf00 nop 08002610 : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002610: e7fe b.n 8002610 8002612: bf00 nop 08002614 : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8002614: e7fe b.n 8002614 8002616: bf00 nop 08002618 : /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8002618: 4770 bx lr 800261a: bf00 nop 0800261c : 800261c: 4770 bx lr 800261e: bf00 nop 08002620 : 8002620: 4770 bx lr 8002622: bf00 nop 08002624 : void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8002624: f000 ba96 b.w 8002b54 08002628 : void DMA1_Channel1_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 8002628: 4801 ldr r0, [pc, #4] ; (8002630 ) 800262a: f001 ba47 b.w 8003abc 800262e: bf00 nop 8002630: 20007900 .word 0x20007900 08002634 : void DMA1_Channel2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ /* USER CODE END DMA1_Channel2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8002634: 4801 ldr r0, [pc, #4] ; (800263c ) 8002636: f001 ba41 b.w 8003abc 800263a: bf00 nop 800263c: 200078a0 .word 0x200078a0 08002640 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8002640: b538 push {r3, r4, r5, lr} /* USER CODE BEGIN TIM2_IRQn 0 */ tim2_tick_end = DWT->CYCCNT; tim2_ticks = tim2_tick_end - tim2_tick_start; 8002642: 4a1d ldr r2, [pc, #116] ; (80026b8 ) tim2_tick_end = DWT->CYCCNT; 8002644: 4c1d ldr r4, [pc, #116] ; (80026bc ) tim2_ticks = tim2_tick_end - tim2_tick_start; 8002646: 6810 ldr r0, [r2, #0] tim2_tick_end = DWT->CYCCNT; 8002648: 6863 ldr r3, [r4, #4] 800264a: 4d1d ldr r5, [pc, #116] ; (80026c0 ) tim2_tick_start = DWT->CYCCNT; if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET) { 800264c: 491d ldr r1, [pc, #116] ; (80026c4 ) tim2_tick_end = DWT->CYCCNT; 800264e: 602b str r3, [r5, #0] tim2_ticks = tim2_tick_end - tim2_tick_start; 8002650: 1a1b subs r3, r3, r0 8002652: 481d ldr r0, [pc, #116] ; (80026c8 ) if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET) { 8002654: 6809 ldr r1, [r1, #0] tim2_ticks = tim2_tick_end - tim2_tick_start; 8002656: 6003 str r3, [r0, #0] tim2_tick_start = DWT->CYCCNT; 8002658: 6860 ldr r0, [r4, #4] if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET) { 800265a: 690b ldr r3, [r1, #16] tim2_tick_start = DWT->CYCCNT; 800265c: 6010 str r0, [r2, #0] if (__HAL_TIM_GET_FLAG(&htim2, TIM_FLAG_UPDATE) != RESET) { 800265e: 07da lsls r2, r3, #31 8002660: d502 bpl.n 8002668 if (__HAL_TIM_GET_IT_SOURCE(&htim2, TIM_IT_UPDATE) != RESET) { 8002662: 68cb ldr r3, [r1, #12] 8002664: 07db lsls r3, r3, #31 8002666: d400 bmi.n 800266a HAL_TIM_IRQHandler(&htim2); /* USER CODE BEGIN TIM2_IRQn 1 */ #endif /* USER CODE END TIM2_IRQn 1 */ } 8002668: bd38 pop {r3, r4, r5, pc} __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); 800266a: f06f 0201 mvn.w r2, #1 chorus_tick(ADC2_raw_data - 2048) + 2048); 800266e: 4b17 ldr r3, [pc, #92] ; (80026cc ) __HAL_TIM_CLEAR_IT(&htim2, TIM_IT_UPDATE); 8002670: 610a str r2, [r1, #16] chorus_tick_start = DWT->CYCCNT; 8002672: 6862 ldr r2, [r4, #4] chorus_tick(ADC2_raw_data - 2048) + 2048); 8002674: 881b ldrh r3, [r3, #0] chorus_tick_start = DWT->CYCCNT; 8002676: 4d16 ldr r5, [pc, #88] ; (80026d0 ) chorus_tick(ADC2_raw_data - 2048) + 2048); 8002678: b29b uxth r3, r3 800267a: f5a3 6300 sub.w r3, r3, #2048 ; 0x800 800267e: ee00 3a10 vmov s0, r3 8002682: eeb8 0ac0 vcvt.f32.s32 s0, s0 chorus_tick_start = DWT->CYCCNT; 8002686: 602a str r2, [r5, #0] chorus_tick(ADC2_raw_data - 2048) + 2048); 8002688: f7ff fba6 bl 8001dd8 800268c: eddf 7a11 vldr s15, [pc, #68] ; 80026d4 HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 8002690: 4811 ldr r0, [pc, #68] ; (80026d8 ) chorus_tick(ADC2_raw_data - 2048) + 2048); 8002692: ee30 0a27 vadd.f32 s0, s0, s15 HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 8002696: 2200 movs r2, #0 8002698: eefc 7ac0 vcvt.u32.f32 s15, s0 800269c: 4611 mov r1, r2 800269e: ee17 3a90 vmov r3, s15 80026a2: f001 f817 bl 80036d4 chorus_tick_end = DWT->CYCCNT; 80026a6: 6862 ldr r2, [r4, #4] chorus_ticks = chorus_tick_end - chorus_tick_start; 80026a8: 682b ldr r3, [r5, #0] chorus_tick_end = DWT->CYCCNT; 80026aa: 480c ldr r0, [pc, #48] ; (80026dc ) chorus_ticks = chorus_tick_end - chorus_tick_start; 80026ac: 490c ldr r1, [pc, #48] ; (80026e0 ) chorus_tick_end = DWT->CYCCNT; 80026ae: 6002 str r2, [r0, #0] chorus_ticks = chorus_tick_end - chorus_tick_start; 80026b0: 1ad3 subs r3, r2, r3 80026b2: 600b str r3, [r1, #0] } 80026b4: bd38 pop {r3, r4, r5, pc} 80026b6: bf00 nop 80026b8: 20007978 .word 0x20007978 80026bc: e0001000 .word 0xe0001000 80026c0: 20007988 .word 0x20007988 80026c4: 20007a24 .word 0x20007a24 80026c8: 20007980 .word 0x20007980 80026cc: 20000088 .word 0x20000088 80026d0: 20007984 .word 0x20007984 80026d4: 45000000 .word 0x45000000 80026d8: 20007960 .word 0x20007960 80026dc: 20007974 .word 0x20007974 80026e0: 2000797c .word 0x2000797c 080026e4 : */ void TIM3_IRQHandler(void) { /* USER CODE BEGIN TIM3_IRQn 0 */ if (__HAL_TIM_GET_FLAG(&htim3, TIM_FLAG_UPDATE) != RESET) { 80026e4: 4b1b ldr r3, [pc, #108] ; (8002754 ) 80026e6: 681b ldr r3, [r3, #0] 80026e8: 691a ldr r2, [r3, #16] 80026ea: 07d1 lsls r1, r2, #31 80026ec: d502 bpl.n 80026f4 if (__HAL_TIM_GET_IT_SOURCE(&htim3, TIM_IT_UPDATE) != RESET) { 80026ee: 68da ldr r2, [r3, #12] 80026f0: 07d2 lsls r2, r2, #31 80026f2: d400 bmi.n 80026f6 80026f4: 4770 bx lr { 80026f6: b500 push {lr} __HAL_TIM_CLEAR_IT(&htim3, TIM_IT_UPDATE); chorus_params_typedef params; params.delay = ADC1_channel_data[DELAY_POT_INDEX] >> 2; 80026f8: 4a17 ldr r2, [pc, #92] ; (8002758 ) __HAL_TIM_CLEAR_IT(&htim3, TIM_IT_UPDATE); 80026fa: f06f 0101 mvn.w r1, #1 80026fe: 6119 str r1, [r3, #16] params.delay = ADC1_channel_data[DELAY_POT_INDEX] >> 2; 8002700: f8b2 c002 ldrh.w ip, [r2, #2] params.delay_cv = ADC1_channel_data[CV_INPUT_INDEX]; 8002704: f8b2 e004 ldrh.w lr, [r2, #4] params.feedback = ADC1_channel_data[FB_POT_INDEX] >> 2; 8002708: 8910 ldrh r0, [r2, #8] params.lfo_rate = ADC1_channel_data[RATE_POT_INDEX] >> 2; 800270a: 88d1 ldrh r1, [r2, #6] params.lfo_amount = ADC1_channel_data[AMT_POT_INDEX] >> 2; 800270c: 8813 ldrh r3, [r2, #0] { 800270e: b085 sub sp, #20 params.feedback = ADC1_channel_data[FB_POT_INDEX] >> 2; 8002710: f3c0 008d ubfx r0, r0, #2, #14 params.lfo_rate = ADC1_channel_data[RATE_POT_INDEX] >> 2; 8002714: f3c1 028d ubfx r2, r1, #2, #14 params.delay = ADC1_channel_data[DELAY_POT_INDEX] >> 2; 8002718: f3cc 0c8d ubfx ip, ip, #2, #14 params.lfo_amount = ADC1_channel_data[AMT_POT_INDEX] >> 2; 800271c: f3c3 038d ubfx r3, r3, #2, #14 params.feedback = ADC1_channel_data[FB_POT_INDEX] >> 2; 8002720: f8ad 000c strh.w r0, [sp, #12] chorus_control_tick(¶ms); 8002724: a801 add r0, sp, #4 params.lfo_rate = ADC1_channel_data[RATE_POT_INDEX] >> 2; 8002726: f8ad 200a strh.w r2, [sp, #10] params.lfo_amount = ADC1_channel_data[AMT_POT_INDEX] >> 2; 800272a: f8ad 3008 strh.w r3, [sp, #8] params.delay = ADC1_channel_data[DELAY_POT_INDEX] >> 2; 800272e: f8ad c004 strh.w ip, [sp, #4] params.delay_cv = ADC1_channel_data[CV_INPUT_INDEX]; 8002732: f8ad e006 strh.w lr, [sp, #6] chorus_control_tick(¶ms); 8002736: f7ff fc43 bl 8001fc0 TIM1->CCR1 = (uint16_t) chorus_lfo.output; 800273a: 4b08 ldr r3, [pc, #32] ; (800275c ) 800273c: 4a08 ldr r2, [pc, #32] ; (8002760 ) 800273e: edd3 7a00 vldr s15, [r3] 8002742: eefc 7ae7 vcvt.u32.f32 s15, s15 8002746: ee17 3a90 vmov r3, s15 800274a: b29b uxth r3, r3 800274c: 6353 str r3, [r2, #52] ; 0x34 HAL_TIM_IRQHandler(&htim3); /* USER CODE BEGIN TIM3_IRQn 1 */ #endif /* USER CODE END TIM3_IRQn 1 */ } 800274e: b005 add sp, #20 8002750: f85d fb04 ldr.w pc, [sp], #4 8002754: 2000798c .word 0x2000798c 8002758: 2000007c .word 0x2000007c 800275c: 200075cc .word 0x200075cc 8002760: 40012c00 .word 0x40012c00 08002764 <_getpid>: } int _getpid(void) { return 1; } 8002764: 2001 movs r0, #1 8002766: 4770 bx lr 08002768 <_kill>: int _kill(int pid, int sig) { 8002768: b508 push {r3, lr} errno = EINVAL; 800276a: f003 fe51 bl 8006410 <__errno> 800276e: 2316 movs r3, #22 8002770: 6003 str r3, [r0, #0] return -1; } 8002772: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8002776: bd08 pop {r3, pc} 08002778 <_exit>: void _exit (int status) { 8002778: b508 push {r3, lr} errno = EINVAL; 800277a: f003 fe49 bl 8006410 <__errno> 800277e: 2316 movs r3, #22 8002780: 6003 str r3, [r0, #0] _kill(status, -1); while (1) {} /* Make sure we hang here */ 8002782: e7fe b.n 8002782 <_exit+0xa> 08002784 : void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8002784: 4a03 ldr r2, [pc, #12] ; (8002794 ) 8002786: f8d2 3088 ldr.w r3, [r2, #136] ; 0x88 800278a: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 800278e: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8002792: 4770 bx lr 8002794: e000ed00 .word 0xe000ed00 08002798 : TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim3; /* TIM1 init function */ void MX_TIM1_Init(void) { 8002798: b530 push {r4, r5, lr} /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800279a: 2400 movs r4, #0 { 800279c: b0a5 sub sp, #148 ; 0x94 TIM_MasterConfigTypeDef sMasterConfig = {0}; TIM_OC_InitTypeDef sConfigOC = {0}; TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 800279e: 2234 movs r2, #52 ; 0x34 80027a0: 4621 mov r1, r4 80027a2: a817 add r0, sp, #92 ; 0x5c /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 80027a4: 4d50 ldr r5, [pc, #320] ; (80028e8 ) TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80027a6: 9406 str r4, [sp, #24] 80027a8: e9cd 4407 strd r4, r4, [sp, #28] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80027ac: e9cd 4403 strd r4, r4, [sp, #12] TIM_OC_InitTypeDef sConfigOC = {0}; 80027b0: e9cd 4411 strd r4, r4, [sp, #68] ; 0x44 80027b4: e9cd 4413 strd r4, r4, [sp, #76] ; 0x4c 80027b8: e9cd 4415 strd r4, r4, [sp, #84] ; 0x54 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80027bc: 9402 str r4, [sp, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80027be: 9410 str r4, [sp, #64] ; 0x40 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80027c0: 9409 str r4, [sp, #36] ; 0x24 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 80027c2: f003 fe1d bl 8006400 htim1.Init.Prescaler = 200; 80027c6: 4a49 ldr r2, [pc, #292] ; (80028ec ) htim1.Init.CounterMode = TIM_COUNTERMODE_UP; htim1.Init.Period = 4096; htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim1.Init.RepetitionCounter = 0; htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80027c8: 61ac str r4, [r5, #24] htim1.Init.Prescaler = 200; 80027ca: 23c8 movs r3, #200 ; 0xc8 80027cc: e9c5 2300 strd r2, r3, [r5] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 80027d0: 4628 mov r0, r5 htim1.Init.Period = 4096; 80027d2: f44f 5380 mov.w r3, #4096 ; 0x1000 80027d6: e9c5 4302 strd r4, r3, [r5, #8] htim1.Init.RepetitionCounter = 0; 80027da: e9c5 4404 strd r4, r4, [r5, #16] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 80027de: f002 f8cf bl 8004980 80027e2: 2800 cmp r0, #0 80027e4: d14e bne.n 8002884 { Error_Handler(); } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80027e6: f44f 5380 mov.w r3, #4096 ; 0x1000 if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 80027ea: 483f ldr r0, [pc, #252] ; (80028e8 ) sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80027ec: 9306 str r3, [sp, #24] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 80027ee: a906 add r1, sp, #24 80027f0: f002 fab8 bl 8004d64 80027f4: 2800 cmp r0, #0 80027f6: d154 bne.n 80028a2 { Error_Handler(); } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 80027f8: 483b ldr r0, [pc, #236] ; (80028e8 ) 80027fa: f002 f985 bl 8004b08 80027fe: 2800 cmp r0, #0 8002800: d14c bne.n 800289c { Error_Handler(); } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8002802: 2300 movs r3, #0 8002804: 2200 movs r2, #0 8002806: e9cd 2302 strd r2, r3, [sp, #8] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 800280a: 4837 ldr r0, [pc, #220] ; (80028e8 ) sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800280c: 2300 movs r3, #0 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 800280e: a902 add r1, sp, #8 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8002810: 9304 str r3, [sp, #16] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8002812: f002 fcbb bl 800518c 8002816: 2800 cmp r0, #0 8002818: d13d bne.n 8002896 } sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.Pulse = 512; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 800281a: ed9f 7b31 vldr d7, [pc, #196] ; 80028e0 sConfigOC.OCMode = TIM_OCMODE_PWM1; 800281e: 2360 movs r3, #96 ; 0x60 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8002820: 2200 movs r2, #0 sConfigOC.OCMode = TIM_OCMODE_PWM1; 8002822: 9310 str r3, [sp, #64] ; 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8002824: 4830 ldr r0, [pc, #192] ; (80028e8 ) sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8002826: 9213 str r2, [sp, #76] ; 0x4c sConfigOC.Pulse = 512; 8002828: f44f 7300 mov.w r3, #512 ; 0x200 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 800282c: a910 add r1, sp, #64 ; 0x40 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800282e: e9cd 3211 strd r3, r2, [sp, #68] ; 0x44 sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8002832: ed8d 7b14 vstr d7, [sp, #80] ; 0x50 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8002836: 9216 str r2, [sp, #88] ; 0x58 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8002838: f002 fba6 bl 8004f88 800283c: bb40 cbnz r0, 8002890 { Error_Handler(); } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 800283e: 2300 movs r3, #0 sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; sBreakDeadTimeConfig.DeadTime = 0; sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8002840: f44f 5200 mov.w r2, #8192 ; 0x2000 8002844: e9cd 321b strd r3, r2, [sp, #108] ; 0x6c sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; sBreakDeadTimeConfig.Break2Filter = 0; sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 8002848: 4827 ldr r0, [pc, #156] ; (80028e8 ) sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 800284a: 9323 str r3, [sp, #140] ; 0x8c sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800284c: f04f 7200 mov.w r2, #33554432 ; 0x2000000 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 8002850: a917 add r1, sp, #92 ; 0x5c sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8002852: e9cd 3317 strd r3, r3, [sp, #92] ; 0x5c sBreakDeadTimeConfig.DeadTime = 0; 8002856: e9cd 3319 strd r3, r3, [sp, #100] ; 0x64 sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; 800285a: e9cd 331d strd r3, r3, [sp, #116] ; 0x74 sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800285e: e9cd 321f strd r3, r2, [sp, #124] ; 0x7c sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; 8002862: e9cd 3321 strd r3, r3, [sp, #132] ; 0x84 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 8002866: f002 fcdb bl 8005220 800286a: b970 cbnz r0, 800288a } void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(timHandle->Instance==TIM1) 800286c: 4a1f ldr r2, [pc, #124] ; (80028ec ) 800286e: 6829 ldr r1, [r5, #0] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002870: 2300 movs r3, #0 if(timHandle->Instance==TIM1) 8002872: 4291 cmp r1, r2 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002874: e9cd 330a strd r3, r3, [sp, #40] ; 0x28 8002878: e9cd 330c strd r3, r3, [sp, #48] ; 0x30 800287c: 930e str r3, [sp, #56] ; 0x38 if(timHandle->Instance==TIM1) 800287e: d013 beq.n 80028a8 } 8002880: b025 add sp, #148 ; 0x94 8002882: bd30 pop {r4, r5, pc} Error_Handler(); 8002884: f7ff fea2 bl 80025cc 8002888: e7ad b.n 80027e6 Error_Handler(); 800288a: f7ff fe9f bl 80025cc 800288e: e7ed b.n 800286c Error_Handler(); 8002890: f7ff fe9c bl 80025cc 8002894: e7d3 b.n 800283e Error_Handler(); 8002896: f7ff fe99 bl 80025cc 800289a: e7be b.n 800281a Error_Handler(); 800289c: f7ff fe96 bl 80025cc 80028a0: e7af b.n 8002802 Error_Handler(); 80028a2: f7ff fe93 bl 80025cc 80028a6: e7a7 b.n 80027f8 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 80028a8: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 80028ac: f503 3304 add.w r3, r3, #135168 ; 0x21000 /**TIM1 GPIO Configuration PA8 ------> TIM1_CH1 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 80028b0: f44f 7480 mov.w r4, #256 ; 0x100 __HAL_RCC_GPIOA_CLK_ENABLE(); 80028b4: 6cda ldr r2, [r3, #76] ; 0x4c 80028b6: f042 0201 orr.w r2, r2, #1 80028ba: 64da str r2, [r3, #76] ; 0x4c 80028bc: 6cdb ldr r3, [r3, #76] ; 0x4c 80028be: f003 0301 and.w r3, r3, #1 80028c2: 9301 str r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_8; 80028c4: 2502 movs r5, #2 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF6_TIM1; 80028c6: 2306 movs r3, #6 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80028c8: a90a add r1, sp, #40 ; 0x28 80028ca: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 GPIO_InitStruct.Pin = GPIO_PIN_8; 80028ce: e9cd 450a strd r4, r5, [sp, #40] ; 0x28 __HAL_RCC_GPIOA_CLK_ENABLE(); 80028d2: 9a01 ldr r2, [sp, #4] GPIO_InitStruct.Alternate = GPIO_AF6_TIM1; 80028d4: 930e str r3, [sp, #56] ; 0x38 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80028d6: f001 f93f bl 8003b58 } 80028da: b025 add sp, #148 ; 0x94 80028dc: bd30 pop {r4, r5, pc} 80028de: bf00 nop ... 80028e8: 200079d8 .word 0x200079d8 80028ec: 40012c00 .word 0x40012c00 080028f0 : { 80028f0: b500 push {lr} htim2.Instance = TIM2; 80028f2: 481b ldr r0, [pc, #108] ; (8002960 ) { 80028f4: b089 sub sp, #36 ; 0x24 htim2.Instance = TIM2; 80028f6: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80028fa: 2300 movs r3, #0 htim2.Instance = TIM2; 80028fc: 6002 str r2, [r0, #0] htim2.Init.Period = 960; 80028fe: f44f 7270 mov.w r2, #960 ; 0x3c0 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8002902: e9cd 3304 strd r3, r3, [sp, #16] 8002906: e9cd 3306 strd r3, r3, [sp, #24] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800290a: e9cd 3301 strd r3, r3, [sp, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 800290e: e9c0 3301 strd r3, r3, [r0, #4] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8002912: e9c0 2303 strd r2, r3, [r0, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8002916: 9303 str r3, [sp, #12] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8002918: 6183 str r3, [r0, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 800291a: f002 f831 bl 8004980 800291e: b998 cbnz r0, 8002948 sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8002920: f44f 5380 mov.w r3, #4096 ; 0x1000 if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 8002924: 480e ldr r0, [pc, #56] ; (8002960 ) sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8002926: 9304 str r3, [sp, #16] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 8002928: a904 add r1, sp, #16 800292a: f002 fa1b bl 8004d64 800292e: b998 cbnz r0, 8002958 sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8002930: 2220 movs r2, #32 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8002932: 2300 movs r3, #0 if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8002934: 480a ldr r0, [pc, #40] ; (8002960 ) sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8002936: 9201 str r2, [sp, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8002938: a901 add r1, sp, #4 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800293a: 9303 str r3, [sp, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800293c: f002 fc26 bl 800518c 8002940: b928 cbnz r0, 800294e } 8002942: b009 add sp, #36 ; 0x24 8002944: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8002948: f7ff fe40 bl 80025cc 800294c: e7e8 b.n 8002920 Error_Handler(); 800294e: f7ff fe3d bl 80025cc } 8002952: b009 add sp, #36 ; 0x24 8002954: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 8002958: f7ff fe38 bl 80025cc 800295c: e7e8 b.n 8002930 800295e: bf00 nop 8002960: 20007a24 .word 0x20007a24 08002964 : { 8002964: b500 push {lr} htim3.Instance = TIM3; 8002966: 481a ldr r0, [pc, #104] ; (80029d0 ) 8002968: 4a1a ldr r2, [pc, #104] ; (80029d4 ) 800296a: 6002 str r2, [r0, #0] { 800296c: b089 sub sp, #36 ; 0x24 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800296e: 2300 movs r3, #0 htim3.Init.Period = 6400; 8002970: f44f 52c8 mov.w r2, #6400 ; 0x1900 TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8002974: e9cd 3304 strd r3, r3, [sp, #16] 8002978: e9cd 3306 strd r3, r3, [sp, #24] TIM_MasterConfigTypeDef sMasterConfig = {0}; 800297c: e9cd 3301 strd r3, r3, [sp, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8002980: e9c0 3301 strd r3, r3, [r0, #4] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8002984: e9c0 2303 strd r2, r3, [r0, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8002988: 9303 str r3, [sp, #12] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800298a: 6183 str r3, [r0, #24] if (HAL_TIM_Base_Init(&htim3) != HAL_OK) 800298c: f001 fff8 bl 8004980 8002990: b998 cbnz r0, 80029ba sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8002992: f44f 5380 mov.w r3, #4096 ; 0x1000 if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 8002996: 480e ldr r0, [pc, #56] ; (80029d0 ) sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8002998: 9304 str r3, [sp, #16] if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK) 800299a: a904 add r1, sp, #16 800299c: f002 f9e2 bl 8004d64 80029a0: b998 cbnz r0, 80029ca sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80029a2: 2220 movs r2, #32 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80029a4: 2300 movs r3, #0 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80029a6: 480a ldr r0, [pc, #40] ; (80029d0 ) sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 80029a8: 9201 str r2, [sp, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80029aa: a901 add r1, sp, #4 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80029ac: 9303 str r3, [sp, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80029ae: f002 fbed bl 800518c 80029b2: b928 cbnz r0, 80029c0 } 80029b4: b009 add sp, #36 ; 0x24 80029b6: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 80029ba: f7ff fe07 bl 80025cc 80029be: e7e8 b.n 8002992 Error_Handler(); 80029c0: f7ff fe04 bl 80025cc } 80029c4: b009 add sp, #36 ; 0x24 80029c6: f85d fb04 ldr.w pc, [sp], #4 Error_Handler(); 80029ca: f7ff fdff bl 80025cc 80029ce: e7e8 b.n 80029a2 80029d0: 2000798c .word 0x2000798c 80029d4: 40000400 .word 0x40000400 080029d8 : { 80029d8: b500 push {lr} if(tim_baseHandle->Instance==TIM1) 80029da: 4a22 ldr r2, [pc, #136] ; (8002a64 ) 80029dc: 6803 ldr r3, [r0, #0] 80029de: 4293 cmp r3, r2 { 80029e0: b085 sub sp, #20 if(tim_baseHandle->Instance==TIM1) 80029e2: d008 beq.n 80029f6 else if(tim_baseHandle->Instance==TIM2) 80029e4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80029e8: d026 beq.n 8002a38 else if(tim_baseHandle->Instance==TIM3) 80029ea: 4a1f ldr r2, [pc, #124] ; (8002a68 ) 80029ec: 4293 cmp r3, r2 80029ee: d00f beq.n 8002a10 } 80029f0: b005 add sp, #20 80029f2: f85d fb04 ldr.w pc, [sp], #4 __HAL_RCC_TIM1_CLK_ENABLE(); 80029f6: 4b1d ldr r3, [pc, #116] ; (8002a6c ) 80029f8: 6e1a ldr r2, [r3, #96] ; 0x60 80029fa: f442 6200 orr.w r2, r2, #2048 ; 0x800 80029fe: 661a str r2, [r3, #96] ; 0x60 8002a00: 6e1b ldr r3, [r3, #96] ; 0x60 8002a02: f403 6300 and.w r3, r3, #2048 ; 0x800 8002a06: 9301 str r3, [sp, #4] 8002a08: 9b01 ldr r3, [sp, #4] } 8002a0a: b005 add sp, #20 8002a0c: f85d fb04 ldr.w pc, [sp], #4 __HAL_RCC_TIM3_CLK_ENABLE(); 8002a10: 4b16 ldr r3, [pc, #88] ; (8002a6c ) 8002a12: 6d99 ldr r1, [r3, #88] ; 0x58 8002a14: f041 0102 orr.w r1, r1, #2 8002a18: 6599 str r1, [r3, #88] ; 0x58 8002a1a: 6d9b ldr r3, [r3, #88] ; 0x58 HAL_NVIC_SetPriority(TIM3_IRQn, 2, 0); 8002a1c: 2102 movs r1, #2 __HAL_RCC_TIM3_CLK_ENABLE(); 8002a1e: 400b ands r3, r1 8002a20: 9303 str r3, [sp, #12] HAL_NVIC_SetPriority(TIM3_IRQn, 2, 0); 8002a22: 201d movs r0, #29 8002a24: 2200 movs r2, #0 __HAL_RCC_TIM3_CLK_ENABLE(); 8002a26: 9b03 ldr r3, [sp, #12] HAL_NVIC_SetPriority(TIM3_IRQn, 2, 0); 8002a28: f000 fda2 bl 8003570 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002a2c: 201d movs r0, #29 } 8002a2e: b005 add sp, #20 8002a30: f85d eb04 ldr.w lr, [sp], #4 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002a34: f000 bdda b.w 80035ec __HAL_RCC_TIM2_CLK_ENABLE(); 8002a38: f503 3304 add.w r3, r3, #135168 ; 0x21000 HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 8002a3c: 2200 movs r2, #0 __HAL_RCC_TIM2_CLK_ENABLE(); 8002a3e: 6d99 ldr r1, [r3, #88] ; 0x58 8002a40: f041 0101 orr.w r1, r1, #1 8002a44: 6599 str r1, [r3, #88] ; 0x58 8002a46: 6d9b ldr r3, [r3, #88] ; 0x58 8002a48: f003 0301 and.w r3, r3, #1 8002a4c: 9302 str r3, [sp, #8] HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 8002a4e: 201c movs r0, #28 8002a50: 4611 mov r1, r2 __HAL_RCC_TIM2_CLK_ENABLE(); 8002a52: 9b02 ldr r3, [sp, #8] HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 8002a54: f000 fd8c bl 8003570 HAL_NVIC_EnableIRQ(TIM2_IRQn); 8002a58: 201c movs r0, #28 } 8002a5a: b005 add sp, #20 8002a5c: f85d eb04 ldr.w lr, [sp], #4 HAL_NVIC_EnableIRQ(TIM3_IRQn); 8002a60: f000 bdc4 b.w 80035ec 8002a64: 40012c00 .word 0x40012c00 8002a68: 40000400 .word 0x40000400 8002a6c: 40021000 .word 0x40021000 08002a70 : } /* USER CODE BEGIN 1 */ void TIM1_Start() { HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); 8002a70: 4801 ldr r0, [pc, #4] ; (8002a78 ) 8002a72: 2100 movs r1, #0 8002a74: f002 b8d0 b.w 8004c18 8002a78: 200079d8 .word 0x200079d8 08002a7c : } void TIM2_Start() { HAL_TIM_Base_Start_IT(&htim2); 8002a7c: 4801 ldr r0, [pc, #4] ; (8002a84 ) 8002a7e: f002 b807 b.w 8004a90 8002a82: bf00 nop 8002a84: 20007a24 .word 0x20007a24 08002a88 : } void TIM3_Start() { HAL_TIM_Base_Start_IT(&htim3); 8002a88: 4801 ldr r0, [pc, #4] ; (8002a90 ) 8002a8a: f002 b801 b.w 8004a90 8002a8e: bf00 nop 8002a90: 2000798c .word 0x2000798c 08002a94 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8002a94: 480d ldr r0, [pc, #52] ; (8002acc ) mov sp, r0 /* set stack pointer */ 8002a96: 4685 mov sp, r0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002a98: 480d ldr r0, [pc, #52] ; (8002ad0 ) ldr r1, =_edata 8002a9a: 490e ldr r1, [pc, #56] ; (8002ad4 ) ldr r2, =_sidata 8002a9c: 4a0e ldr r2, [pc, #56] ; (8002ad8 ) movs r3, #0 8002a9e: 2300 movs r3, #0 b LoopCopyDataInit 8002aa0: e002 b.n 8002aa8 08002aa2 : CopyDataInit: ldr r4, [r2, r3] 8002aa2: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8002aa4: 50c4 str r4, [r0, r3] adds r3, r3, #4 8002aa6: 3304 adds r3, #4 08002aa8 : LoopCopyDataInit: adds r4, r0, r3 8002aa8: 18c4 adds r4, r0, r3 cmp r4, r1 8002aaa: 428c cmp r4, r1 bcc CopyDataInit 8002aac: d3f9 bcc.n 8002aa2 /* Zero fill the bss segment. */ ldr r2, =_sbss 8002aae: 4a0b ldr r2, [pc, #44] ; (8002adc ) ldr r4, =_ebss 8002ab0: 4c0b ldr r4, [pc, #44] ; (8002ae0 ) movs r3, #0 8002ab2: 2300 movs r3, #0 b LoopFillZerobss 8002ab4: e001 b.n 8002aba 08002ab6 : FillZerobss: str r3, [r2] 8002ab6: 6013 str r3, [r2, #0] adds r2, r2, #4 8002ab8: 3204 adds r2, #4 08002aba : LoopFillZerobss: cmp r2, r4 8002aba: 42a2 cmp r2, r4 bcc FillZerobss 8002abc: d3fb bcc.n 8002ab6 /* Call the clock system intitialization function.*/ bl SystemInit 8002abe: f7ff fe61 bl 8002784 /* Call static constructors */ bl __libc_init_array 8002ac2: f003 fcab bl 800641c <__libc_init_array> /* Call the application's entry point.*/ bl main 8002ac6: f7ff fd13 bl 80024f0
08002aca : LoopForever: b LoopForever 8002aca: e7fe b.n 8002aca ldr r0, =_estack 8002acc: 20008000 .word 0x20008000 ldr r0, =_sdata 8002ad0: 20000000 .word 0x20000000 ldr r1, =_edata 8002ad4: 2000005c .word 0x2000005c ldr r2, =_sidata 8002ad8: 0800801c .word 0x0800801c ldr r2, =_sbss 8002adc: 2000005c .word 0x2000005c ldr r4, =_ebss 8002ae0: 20007a74 .word 0x20007a74 08002ae4 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8002ae4: e7fe b.n 8002ae4 ... 08002ae8 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8002ae8: b538 push {r3, r4, r5, lr} HAL_StatusTypeDef status = HAL_OK; if (uwTickFreq != 0U) 8002aea: 4b0f ldr r3, [pc, #60] ; (8002b28 ) 8002aec: 681b ldr r3, [r3, #0] 8002aee: b90b cbnz r3, 8002af4 status = HAL_ERROR; } } else { status = HAL_ERROR; 8002af0: 2001 movs r0, #1 } /* Return function status */ return status; } 8002af2: bd38 pop {r3, r4, r5, pc} if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) 8002af4: 490d ldr r1, [pc, #52] ; (8002b2c ) 8002af6: f44f 727a mov.w r2, #1000 ; 0x3e8 8002afa: 4605 mov r5, r0 8002afc: fbb2 f3f3 udiv r3, r2, r3 8002b00: 6808 ldr r0, [r1, #0] 8002b02: fbb0 f0f3 udiv r0, r0, r3 8002b06: f000 fd7f bl 8003608 8002b0a: 4604 mov r4, r0 8002b0c: 2800 cmp r0, #0 8002b0e: d1ef bne.n 8002af0 if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8002b10: 2d0f cmp r5, #15 8002b12: d8ed bhi.n 8002af0 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8002b14: 4602 mov r2, r0 8002b16: 4629 mov r1, r5 8002b18: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8002b1c: f000 fd28 bl 8003570 uwTickPrio = TickPriority; 8002b20: 4b03 ldr r3, [pc, #12] ; (8002b30 ) 8002b22: 4620 mov r0, r4 8002b24: 601d str r5, [r3, #0] } 8002b26: bd38 pop {r3, r4, r5, pc} 8002b28: 20000004 .word 0x20000004 8002b2c: 20000000 .word 0x20000000 8002b30: 20000008 .word 0x20000008 08002b34 : { 8002b34: b510 push {r4, lr} HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8002b36: 2003 movs r0, #3 8002b38: f000 fd08 bl 800354c if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8002b3c: 200f movs r0, #15 8002b3e: f7ff ffd3 bl 8002ae8 8002b42: b110 cbz r0, 8002b4a status = HAL_ERROR; 8002b44: 2401 movs r4, #1 } 8002b46: 4620 mov r0, r4 8002b48: bd10 pop {r4, pc} 8002b4a: 4604 mov r4, r0 HAL_MspInit(); 8002b4c: f7ff fd40 bl 80025d0 } 8002b50: 4620 mov r0, r4 8002b52: bd10 pop {r4, pc} 08002b54 : * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; 8002b54: 4a03 ldr r2, [pc, #12] ; (8002b64 ) 8002b56: 4904 ldr r1, [pc, #16] ; (8002b68 ) 8002b58: 6813 ldr r3, [r2, #0] 8002b5a: 6809 ldr r1, [r1, #0] 8002b5c: 440b add r3, r1 8002b5e: 6013 str r3, [r2, #0] } 8002b60: 4770 bx lr 8002b62: bf00 nop 8002b64: 20007a70 .word 0x20007a70 8002b68: 20000004 .word 0x20000004 08002b6c : * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; 8002b6c: 4b01 ldr r3, [pc, #4] ; (8002b74 ) 8002b6e: 6818 ldr r0, [r3, #0] } 8002b70: 4770 bx lr 8002b72: bf00 nop 8002b74: 20007a70 .word 0x20007a70 08002b78 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8002b78: b538 push {r3, r4, r5, lr} 8002b7a: 4604 mov r4, r0 uint32_t tickstart = HAL_GetTick(); 8002b7c: f7ff fff6 bl 8002b6c uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8002b80: 1c63 adds r3, r4, #1 uint32_t tickstart = HAL_GetTick(); 8002b82: 4605 mov r5, r0 if (wait < HAL_MAX_DELAY) 8002b84: d002 beq.n 8002b8c { wait += (uint32_t)(uwTickFreq); 8002b86: 4b04 ldr r3, [pc, #16] ; (8002b98 ) 8002b88: 681b ldr r3, [r3, #0] 8002b8a: 441c add r4, r3 } while ((HAL_GetTick() - tickstart) < wait) 8002b8c: f7ff ffee bl 8002b6c 8002b90: 1b43 subs r3, r0, r5 8002b92: 42a3 cmp r3, r4 8002b94: d3fa bcc.n 8002b8c { } } 8002b96: bd38 pop {r3, r4, r5, pc} 8002b98: 20000004 .word 0x20000004 08002b9c : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 8002b9c: b530 push {r4, r5, lr} 8002b9e: b083 sub sp, #12 HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 8002ba0: 2300 movs r3, #0 8002ba2: 9301 str r3, [sp, #4] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 8002ba4: 2800 cmp r0, #0 8002ba6: f000 80c9 beq.w 8002d3c /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8002baa: 6dc5 ldr r5, [r0, #92] ; 0x5c 8002bac: 4604 mov r4, r0 8002bae: 2d00 cmp r5, #0 8002bb0: f000 8092 beq.w 8002cd8 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8002bb4: 6822 ldr r2, [r4, #0] * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 8002bb6: 6893 ldr r3, [r2, #8] 8002bb8: 009b lsls r3, r3, #2 8002bba: d505 bpl.n 8002bc8 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8002bbc: 6893 ldr r3, [r2, #8] 8002bbe: f023 4320 bic.w r3, r3, #2684354560 ; 0xa0000000 8002bc2: f023 033f bic.w r3, r3, #63 ; 0x3f 8002bc6: 6093 str r3, [r2, #8] * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8002bc8: 6893 ldr r3, [r2, #8] 8002bca: 00dd lsls r5, r3, #3 8002bcc: d419 bmi.n 8002c02 LL_ADC_EnableInternalRegulator(hadc->Instance); /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8002bce: 4b70 ldr r3, [pc, #448] ; (8002d90 ) 8002bd0: 4870 ldr r0, [pc, #448] ; (8002d94 ) 8002bd2: 681b ldr r3, [r3, #0] MODIFY_REG(ADCx->CR, 8002bd4: 6891 ldr r1, [r2, #8] 8002bd6: 099b lsrs r3, r3, #6 8002bd8: fba0 0303 umull r0, r3, r0, r3 8002bdc: f021 4110 bic.w r1, r1, #2415919104 ; 0x90000000 8002be0: 099b lsrs r3, r3, #6 8002be2: f021 013f bic.w r1, r1, #63 ; 0x3f 8002be6: 3301 adds r3, #1 8002be8: 005b lsls r3, r3, #1 8002bea: f041 5180 orr.w r1, r1, #268435456 ; 0x10000000 8002bee: 6091 str r1, [r2, #8] 8002bf0: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 8002bf2: 9b01 ldr r3, [sp, #4] 8002bf4: b12b cbz r3, 8002c02 { wait_loop_index--; 8002bf6: 9b01 ldr r3, [sp, #4] 8002bf8: 3b01 subs r3, #1 8002bfa: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 8002bfc: 9b01 ldr r3, [sp, #4] 8002bfe: 2b00 cmp r3, #0 8002c00: d1f9 bne.n 8002bf6 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8002c02: 6893 ldr r3, [r2, #8] 8002c04: 00d8 lsls r0, r3, #3 8002c06: d459 bmi.n 8002cbc /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002c08: 6de3 ldr r3, [r4, #92] ; 0x5c 8002c0a: f043 0310 orr.w r3, r3, #16 8002c0e: 65e3 str r3, [r4, #92] ; 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002c10: 6e23 ldr r3, [r4, #96] ; 0x60 tmp_hal_status = HAL_ERROR; 8002c12: 2001 movs r0, #1 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002c14: 4303 orrs r3, r0 8002c16: 6623 str r3, [r4, #96] ; 0x60 * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8002c18: 6893 ldr r3, [r2, #8] 8002c1a: f013 0f04 tst.w r3, #4 /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8002c1e: 6de3 ldr r3, [r4, #92] ; 0x5c 8002c20: d153 bne.n 8002cca 8002c22: 06d9 lsls r1, r3, #27 8002c24: d451 bmi.n 8002cca && (tmp_adc_reg_is_conversion_on_going == 0UL) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8002c26: 6de3 ldr r3, [r4, #92] ; 0x5c 8002c28: f423 7381 bic.w r3, r3, #258 ; 0x102 8002c2c: f043 0302 orr.w r3, r3, #2 8002c30: 65e3 str r3, [r4, #92] ; 0x5c return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8002c32: 6893 ldr r3, [r2, #8] 8002c34: 07db lsls r3, r3, #31 8002c36: d40e bmi.n 8002c56 8002c38: 4b57 ldr r3, [pc, #348] ; (8002d98 ) 8002c3a: f04f 41a0 mov.w r1, #1342177280 ; 0x50000000 8002c3e: 6889 ldr r1, [r1, #8] 8002c40: 689b ldr r3, [r3, #8] 8002c42: 430b orrs r3, r1 8002c44: 07dd lsls r5, r3, #31 8002c46: d406 bmi.n 8002c56 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8002c48: 4954 ldr r1, [pc, #336] ; (8002d9c ) 8002c4a: 6865 ldr r5, [r4, #4] 8002c4c: 688b ldr r3, [r1, #8] 8002c4e: f423 137c bic.w r3, r3, #4128768 ; 0x3f0000 8002c52: 432b orrs r3, r5 8002c54: 608b str r3, [r1, #8] /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | hadc->Init.Overrun | hadc->Init.DataAlign | 8002c56: 68e5 ldr r5, [r4, #12] 8002c58: 6be3 ldr r3, [r4, #60] ; 0x3c hadc->Init.Resolution | ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8002c5a: f894 1024 ldrb.w r1, [r4, #36] ; 0x24 hadc->Init.DataAlign | 8002c5e: 432b orrs r3, r5 8002c60: 68a5 ldr r5, [r4, #8] 8002c62: 432b orrs r3, r5 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8002c64: 7f65 ldrb r5, [r4, #29] if (hadc->Init.DiscontinuousConvMode == ENABLE) 8002c66: 2901 cmp r1, #1 hadc->Init.DataAlign | 8002c68: ea43 3345 orr.w r3, r3, r5, lsl #13 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8002c6c: ea43 4301 orr.w r3, r3, r1, lsl #16 if (hadc->Init.DiscontinuousConvMode == ENABLE) 8002c70: d05f beq.n 8002d32 /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8002c72: 6ae1 ldr r1, [r4, #44] ; 0x2c 8002c74: b121 cbz r1, 8002c80 { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) | hadc->Init.ExternalTrigConvEdge 8002c76: 6b25 ldr r5, [r4, #48] ; 0x30 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8002c78: f401 7178 and.w r1, r1, #992 ; 0x3e0 | hadc->Init.ExternalTrigConvEdge 8002c7c: 4329 orrs r1, r5 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8002c7e: 430b orrs r3, r1 ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 8002c80: 68d5 ldr r5, [r2, #12] 8002c82: 4947 ldr r1, [pc, #284] ; (8002da0 ) 8002c84: 4029 ands r1, r5 8002c86: 4319 orrs r1, r3 8002c88: 60d1 str r1, [r2, #12] /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); 8002c8a: 6913 ldr r3, [r2, #16] 8002c8c: 6b61 ldr r1, [r4, #52] ; 0x34 8002c8e: f023 6340 bic.w r3, r3, #201326592 ; 0xc000000 8002c92: 430b orrs r3, r1 8002c94: 6113 str r3, [r2, #16] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8002c96: 6893 ldr r3, [r2, #8] 8002c98: 0759 lsls r1, r3, #29 8002c9a: d523 bpl.n 8002ce4 * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8002c9c: 6893 ldr r3, [r2, #8] /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8002c9e: 6963 ldr r3, [r4, #20] 8002ca0: 2b01 cmp r3, #1 8002ca2: d04e beq.n 8002d42 /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 8002ca4: 6b13 ldr r3, [r2, #48] ; 0x30 8002ca6: f023 030f bic.w r3, r3, #15 8002caa: 6313 str r3, [r2, #48] ; 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 8002cac: 6de3 ldr r3, [r4, #92] ; 0x5c 8002cae: f023 0303 bic.w r3, r3, #3 8002cb2: f043 0301 orr.w r3, r3, #1 8002cb6: 65e3 str r3, [r4, #92] ; 0x5c tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } 8002cb8: b003 add sp, #12 8002cba: bd30 pop {r4, r5, pc} return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8002cbc: 6893 ldr r3, [r2, #8] 8002cbe: f013 0f04 tst.w r3, #4 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002cc2: f04f 0000 mov.w r0, #0 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8002cc6: 6de3 ldr r3, [r4, #92] ; 0x5c 8002cc8: d0ab beq.n 8002c22 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002cca: 6de3 ldr r3, [r4, #92] ; 0x5c tmp_hal_status = HAL_ERROR; 8002ccc: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002cce: f043 0310 orr.w r3, r3, #16 8002cd2: 65e3 str r3, [r4, #92] ; 0x5c } 8002cd4: b003 add sp, #12 8002cd6: bd30 pop {r4, r5, pc} HAL_ADC_MspInit(hadc); 8002cd8: f7fe ff74 bl 8001bc4 ADC_CLEAR_ERRORCODE(hadc); 8002cdc: 6625 str r5, [r4, #96] ; 0x60 hadc->Lock = HAL_UNLOCKED; 8002cde: f884 5058 strb.w r5, [r4, #88] ; 0x58 8002ce2: e767 b.n 8002bb4 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8002ce4: 6893 ldr r3, [r2, #8] 8002ce6: 071b lsls r3, r3, #28 8002ce8: d4d9 bmi.n 8002c9e MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8002cea: 68d1 ldr r1, [r2, #12] ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); 8002cec: f894 3038 ldrb.w r3, [r4, #56] ; 0x38 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8002cf0: 7f25 ldrb r5, [r4, #28] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8002cf2: f421 4180 bic.w r1, r1, #16384 ; 0x4000 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); 8002cf6: 005b lsls r3, r3, #1 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8002cf8: f021 0102 bic.w r1, r1, #2 tmpCFGR = (ADC_CFGR_DFSDM(hadc) | 8002cfc: ea43 3385 orr.w r3, r3, r5, lsl #14 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8002d00: 430b orrs r3, r1 if (hadc->Init.GainCompensation != 0UL) 8002d02: 6921 ldr r1, [r4, #16] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8002d04: 60d3 str r3, [r2, #12] SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8002d06: 6913 ldr r3, [r2, #16] if (hadc->Init.GainCompensation != 0UL) 8002d08: bb19 cbnz r1, 8002d52 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8002d0a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8002d0e: 6113 str r3, [r2, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); 8002d10: f8d2 30c0 ldr.w r3, [r2, #192] ; 0xc0 8002d14: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 8002d18: f023 033f bic.w r3, r3, #63 ; 0x3f 8002d1c: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0 if (hadc->Init.OversamplingMode == ENABLE) 8002d20: f894 3040 ldrb.w r3, [r4, #64] ; 0x40 8002d24: 2b01 cmp r3, #1 8002d26: d021 beq.n 8002d6c CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8002d28: 6913 ldr r3, [r2, #16] 8002d2a: f023 0301 bic.w r3, r3, #1 8002d2e: 6113 str r3, [r2, #16] 8002d30: e7b5 b.n 8002c9e tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8002d32: 6aa1 ldr r1, [r4, #40] ; 0x28 8002d34: 3901 subs r1, #1 8002d36: ea43 4341 orr.w r3, r3, r1, lsl #17 8002d3a: e79a b.n 8002c72 return HAL_ERROR; 8002d3c: 2001 movs r0, #1 } 8002d3e: b003 add sp, #12 8002d40: bd30 pop {r4, r5, pc} MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8002d42: 6b11 ldr r1, [r2, #48] ; 0x30 8002d44: 6a23 ldr r3, [r4, #32] 8002d46: f021 010f bic.w r1, r1, #15 8002d4a: 3b01 subs r3, #1 8002d4c: 430b orrs r3, r1 8002d4e: 6313 str r3, [r2, #48] ; 0x30 8002d50: e7ac b.n 8002cac SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 8002d52: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8002d56: 6113 str r3, [r2, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); 8002d58: f8d2 30c0 ldr.w r3, [r2, #192] ; 0xc0 8002d5c: f423 537f bic.w r3, r3, #16320 ; 0x3fc0 8002d60: f023 033f bic.w r3, r3, #63 ; 0x3f 8002d64: 430b orrs r3, r1 8002d66: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0 8002d6a: e7d9 b.n 8002d20 MODIFY_REG(hadc->Instance->CFGR2, 8002d6c: 6911 ldr r1, [r2, #16] 8002d6e: 6c63 ldr r3, [r4, #68] ; 0x44 8002d70: 6ca5 ldr r5, [r4, #72] ; 0x48 8002d72: f421 61ff bic.w r1, r1, #2040 ; 0x7f8 8002d76: f021 0104 bic.w r1, r1, #4 8002d7a: 432b orrs r3, r5 8002d7c: 430b orrs r3, r1 8002d7e: 6ce1 ldr r1, [r4, #76] ; 0x4c 8002d80: 430b orrs r3, r1 8002d82: 6d21 ldr r1, [r4, #80] ; 0x50 8002d84: 430b orrs r3, r1 8002d86: f043 0301 orr.w r3, r3, #1 8002d8a: 6113 str r3, [r2, #16] 8002d8c: e787 b.n 8002c9e 8002d8e: bf00 nop 8002d90: 20000000 .word 0x20000000 8002d94: 053e2d63 .word 0x053e2d63 8002d98: 50000100 .word 0x50000100 8002d9c: 50000300 .word 0x50000300 8002da0: fff04007 .word 0xfff04007 08002da4 : 8002da4: 4770 bx lr 8002da6: bf00 nop 08002da8 : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8002da8: b508 push {r3, lr} /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8002daa: 6a80 ldr r0, [r0, #40] ; 0x28 8002dac: f7ff fffa bl 8002da4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8002db0: bd08 pop {r3, pc} 8002db2: bf00 nop 08002db4 : 8002db4: 4770 bx lr 8002db6: bf00 nop 08002db8 : ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8002db8: 6a83 ldr r3, [r0, #40] ; 0x28 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8002dba: 6dda ldr r2, [r3, #92] ; 0x5c 8002dbc: f012 0f50 tst.w r2, #80 ; 0x50 { 8002dc0: b510 push {r4, lr} SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8002dc2: 6dda ldr r2, [r3, #92] ; 0x5c if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8002dc4: d11d bne.n 8002e02 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8002dc6: 6819 ldr r1, [r3, #0] SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8002dc8: f442 7200 orr.w r2, r2, #512 ; 0x200 8002dcc: 65da str r2, [r3, #92] ; 0x5c if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8002dce: 680a ldr r2, [r1, #0] 8002dd0: f012 0f08 tst.w r2, #8 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8002dd4: 68ca ldr r2, [r1, #12] 8002dd6: d01b beq.n 8002e10 8002dd8: f412 6f40 tst.w r2, #3072 ; 0xc00 8002ddc: d10d bne.n 8002dfa if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 8002dde: 68ca ldr r2, [r1, #12] 8002de0: 0494 lsls r4, r2, #18 8002de2: d40a bmi.n 8002dfa CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8002de4: 6dda ldr r2, [r3, #92] ; 0x5c 8002de6: f422 7280 bic.w r2, r2, #256 ; 0x100 8002dea: 65da str r2, [r3, #92] ; 0x5c if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8002dec: 6dda ldr r2, [r3, #92] ; 0x5c 8002dee: 04d1 lsls r1, r2, #19 8002df0: d403 bmi.n 8002dfa SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8002df2: 6dda ldr r2, [r3, #92] ; 0x5c 8002df4: f042 0201 orr.w r2, r2, #1 8002df8: 65da str r2, [r3, #92] ; 0x5c HAL_ADC_ConvCpltCallback(hadc); 8002dfa: 4618 mov r0, r3 8002dfc: f7ff fbae bl 800255c } 8002e00: bd10 pop {r4, pc} if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 8002e02: 06d2 lsls r2, r2, #27 8002e04: d40a bmi.n 8002e1c hadc->DMA_Handle->XferErrorCallback(hdma); 8002e06: 6d5b ldr r3, [r3, #84] ; 0x54 } 8002e08: e8bd 4010 ldmia.w sp!, {r4, lr} hadc->DMA_Handle->XferErrorCallback(hdma); 8002e0c: 6b5b ldr r3, [r3, #52] ; 0x34 8002e0e: 4718 bx r3 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) 8002e10: 0790 lsls r0, r2, #30 8002e12: d5e7 bpl.n 8002de4 HAL_ADC_ConvCpltCallback(hadc); 8002e14: 4618 mov r0, r3 8002e16: f7ff fba1 bl 800255c 8002e1a: e7f1 b.n 8002e00 HAL_ADC_ErrorCallback(hadc); 8002e1c: 4618 mov r0, r3 8002e1e: f7ff ffc9 bl 8002db4 } 8002e22: bd10 pop {r4, pc} 08002e24 : * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8002e24: 6a80 ldr r0, [r0, #40] ; 0x28 { 8002e26: b508 push {r3, lr} /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8002e28: 6dc3 ldr r3, [r0, #92] ; 0x5c 8002e2a: f043 0340 orr.w r3, r3, #64 ; 0x40 8002e2e: 65c3 str r3, [r0, #92] ; 0x5c /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8002e30: 6e03 ldr r3, [r0, #96] ; 0x60 8002e32: f043 0304 orr.w r3, r3, #4 8002e36: 6603 str r3, [r0, #96] ; 0x60 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8002e38: f7ff ffbc bl 8002db4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8002e3c: bd08 pop {r3, pc} 8002e3e: bf00 nop 08002e40 : { 8002e40: b5f0 push {r4, r5, r6, r7, lr} __HAL_LOCK(hadc); 8002e42: f890 2058 ldrb.w r2, [r0, #88] ; 0x58 { 8002e46: b083 sub sp, #12 8002e48: 4603 mov r3, r0 __HAL_LOCK(hadc); 8002e4a: 2a01 cmp r2, #1 __IO uint32_t wait_loop_index = 0UL; 8002e4c: f04f 0000 mov.w r0, #0 8002e50: 9001 str r0, [sp, #4] __HAL_LOCK(hadc); 8002e52: f000 8141 beq.w 80030d8 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8002e56: 681c ldr r4, [r3, #0] __HAL_LOCK(hadc); 8002e58: 2001 movs r0, #1 8002e5a: f883 0058 strb.w r0, [r3, #88] ; 0x58 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8002e5e: 68a2 ldr r2, [r4, #8] 8002e60: 0756 lsls r6, r2, #29 8002e62: d44c bmi.n 8002efe LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 8002e64: 6848 ldr r0, [r1, #4] MODIFY_REG(*preg, 8002e66: 680a ldr r2, [r1, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8002e68: ea4f 1c90 mov.w ip, r0, lsr #6 8002e6c: f00c 0c0c and.w ip, ip, #12 8002e70: f104 0e30 add.w lr, r4, #48 ; 0x30 MODIFY_REG(*preg, 8002e74: f000 001f and.w r0, r0, #31 8002e78: f85e 500c ldr.w r5, [lr, ip] 8002e7c: f3c2 6284 ubfx r2, r2, #26, #5 8002e80: 261f movs r6, #31 8002e82: 4082 lsls r2, r0 8002e84: fa06 f000 lsl.w r0, r6, r0 8002e88: ea25 0000 bic.w r0, r5, r0 8002e8c: 4302 orrs r2, r0 8002e8e: f84e 200c str.w r2, [lr, ip] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8002e92: 68a2 ldr r2, [r4, #8] 8002e94: 0755 lsls r5, r2, #29 8002e96: d543 bpl.n 8002f20 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8002e98: 68a2 ldr r2, [r4, #8] 8002e9a: 6808 ldr r0, [r1, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8002e9c: 68a2 ldr r2, [r4, #8] 8002e9e: f012 0f01 tst.w r2, #1 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8002ea2: 4602 mov r2, r0 8002ea4: d10c bne.n 8002ec0 if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED) 8002ea6: 4dbf ldr r5, [pc, #764] ; (80031a4 ) 8002ea8: 68ce ldr r6, [r1, #12] 8002eaa: 42ae cmp r6, r5 8002eac: f000 80bc beq.w 8003028 CLEAR_BIT(ADCx->DIFSEL, 8002eb0: f8d4 10b0 ldr.w r1, [r4, #176] ; 0xb0 8002eb4: f3c0 0012 ubfx r0, r0, #0, #19 8002eb8: ea21 0100 bic.w r1, r1, r0 8002ebc: f8c4 10b0 str.w r1, [r4, #176] ; 0xb0 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8002ec0: 49b9 ldr r1, [pc, #740] ; (80031a8 ) 8002ec2: 420a tst r2, r1 8002ec4: d02a beq.n 8002f1c return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); 8002ec6: 49b9 ldr r1, [pc, #740] ; (80031ac ) if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) 8002ec8: 4db9 ldr r5, [pc, #740] ; (80031b0 ) 8002eca: 6888 ldr r0, [r1, #8] 8002ecc: 42aa cmp r2, r5 8002ece: f000 76e0 and.w r6, r0, #29360128 ; 0x1c00000 8002ed2: d01d beq.n 8002f10 8002ed4: 4db7 ldr r5, [pc, #732] ; (80031b4 ) 8002ed6: 42aa cmp r2, r5 8002ed8: d01a beq.n 8002f10 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8002eda: 4db7 ldr r5, [pc, #732] ; (80031b8 ) 8002edc: 42aa cmp r2, r5 8002ede: f040 812d bne.w 800313c 8002ee2: f010 7080 ands.w r0, r0, #16777216 ; 0x1000000 8002ee6: d119 bne.n 8002f1c if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8002ee8: 4ab4 ldr r2, [pc, #720] ; (80031bc ) 8002eea: 4294 cmp r4, r2 8002eec: d016 beq.n 8002f1c MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); 8002eee: 688a ldr r2, [r1, #8] 8002ef0: f022 72e0 bic.w r2, r2, #29360128 ; 0x1c00000 8002ef4: 4332 orrs r2, r6 8002ef6: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000 8002efa: 608a str r2, [r1, #8] } 8002efc: e003 b.n 8002f06 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002efe: 6dda ldr r2, [r3, #92] ; 0x5c 8002f00: f042 0220 orr.w r2, r2, #32 8002f04: 65da str r2, [r3, #92] ; 0x5c __HAL_UNLOCK(hadc); 8002f06: 2200 movs r2, #0 8002f08: f883 2058 strb.w r2, [r3, #88] ; 0x58 } 8002f0c: b003 add sp, #12 8002f0e: bdf0 pop {r4, r5, r6, r7, pc} && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8002f10: 0202 lsls r2, r0, #8 8002f12: d403 bmi.n 8002f1c if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8002f14: f1b4 4fa0 cmp.w r4, #1342177280 ; 0x50000000 8002f18: f000 80f1 beq.w 80030fe HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8002f1c: 2000 movs r0, #0 8002f1e: e7f2 b.n 8002f06 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8002f20: 68a2 ldr r2, [r4, #8] 8002f22: 0710 lsls r0, r2, #28 8002f24: d47e bmi.n 8003024 if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) 8002f26: 688a ldr r2, [r1, #8] LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); 8002f28: 680d ldr r5, [r1, #0] if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) 8002f2a: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 8002f2e: f000 8119 beq.w 8003164 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8002f32: 0dee lsrs r6, r5, #23 8002f34: f104 0c14 add.w ip, r4, #20 8002f38: f006 0604 and.w r6, r6, #4 MODIFY_REG(*preg, 8002f3c: f3c5 5504 ubfx r5, r5, #20, #5 8002f40: f85c 0006 ldr.w r0, [ip, r6] 8002f44: 2707 movs r7, #7 8002f46: 40aa lsls r2, r5 8002f48: fa07 f505 lsl.w r5, r7, r5 8002f4c: ea20 0005 bic.w r0, r0, r5 8002f50: 4302 orrs r2, r0 8002f52: f84c 2006 str.w r2, [ip, r6] MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); 8002f56: 6962 ldr r2, [r4, #20] 8002f58: f022 4200 bic.w r2, r2, #2147483648 ; 0x80000000 8002f5c: 6162 str r2, [r4, #20] tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8002f5e: e9d1 5604 ldrd r5, r6, [r1, #16] if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 8002f62: 2d04 cmp r5, #4 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8002f64: 68e2 ldr r2, [r4, #12] if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 8002f66: d02d beq.n 8002fc4 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8002f68: f104 0060 add.w r0, r4, #96 ; 0x60 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8002f6c: f3c2 02c1 ubfx r2, r2, #3, #2 8002f70: 0052 lsls r2, r2, #1 MODIFY_REG(*preg, 8002f72: f850 c025 ldr.w ip, [r0, r5, lsl #2] 8002f76: 4f92 ldr r7, [pc, #584] ; (80031c0 ) 8002f78: 4096 lsls r6, r2 8002f7a: 680a ldr r2, [r1, #0] 8002f7c: ea0c 0707 and.w r7, ip, r7 8002f80: f002 42f8 and.w r2, r2, #2080374784 ; 0x7c000000 8002f84: 433a orrs r2, r7 8002f86: 4332 orrs r2, r6 8002f88: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000 8002f8c: f840 2025 str.w r2, [r0, r5, lsl #2] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8002f90: 690d ldr r5, [r1, #16] MODIFY_REG(*preg, 8002f92: 698e ldr r6, [r1, #24] 8002f94: f850 2025 ldr.w r2, [r0, r5, lsl #2] 8002f98: f022 7280 bic.w r2, r2, #16777216 ; 0x1000000 8002f9c: 4332 orrs r2, r6 8002f9e: f840 2025 str.w r2, [r0, r5, lsl #2] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8002fa2: 690e ldr r6, [r1, #16] LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); 8002fa4: 7f0d ldrb r5, [r1, #28] MODIFY_REG(*preg, 8002fa6: f850 2026 ldr.w r2, [r0, r6, lsl #2] 8002faa: f1a5 0501 sub.w r5, r5, #1 8002fae: fab5 f585 clz r5, r5 8002fb2: 096d lsrs r5, r5, #5 8002fb4: f022 7200 bic.w r2, r2, #33554432 ; 0x2000000 8002fb8: ea42 6245 orr.w r2, r2, r5, lsl #25 8002fbc: f840 2026 str.w r2, [r0, r6, lsl #2] 8002fc0: 6808 ldr r0, [r1, #0] } 8002fc2: e76b b.n 8002e9c == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 8002fc4: 6808 ldr r0, [r1, #0] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8002fc6: 6e22 ldr r2, [r4, #96] ; 0x60 8002fc8: 6e22 ldr r2, [r4, #96] ; 0x60 8002fca: f3c0 0512 ubfx r5, r0, #0, #19 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8002fce: f3c2 6284 ubfx r2, r2, #26, #5 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 8002fd2: 2d00 cmp r5, #0 8002fd4: f040 80fc bne.w 80031d0 8002fd8: f3c0 6584 ubfx r5, r0, #26, #5 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8002fdc: 42aa cmp r2, r5 8002fde: f000 8170 beq.w 80032c2 8002fe2: 6e62 ldr r2, [r4, #100] ; 0x64 8002fe4: 6e66 ldr r6, [r4, #100] ; 0x64 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8002fe6: f104 0260 add.w r2, r4, #96 ; 0x60 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8002fea: f3c6 6684 ubfx r6, r6, #26, #5 8002fee: f104 0764 add.w r7, r4, #100 ; 0x64 8002ff2: 42ae cmp r6, r5 8002ff4: f000 8153 beq.w 800329e return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8002ff8: 6896 ldr r6, [r2, #8] 8002ffa: 6896 ldr r6, [r2, #8] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8002ffc: f102 0708 add.w r7, r2, #8 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 8003000: f3c6 6684 ubfx r6, r6, #26, #5 8003004: 42ae cmp r6, r5 8003006: f000 8138 beq.w 800327a return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 800300a: 68d6 ldr r6, [r2, #12] 800300c: 68d6 ldr r6, [r2, #12] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 800300e: f102 070c add.w r7, r2, #12 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 8003012: f3c6 6284 ubfx r2, r6, #26, #5 8003016: 4295 cmp r5, r2 8003018: f47f af40 bne.w 8002e9c MODIFY_REG(*preg, 800301c: 683a ldr r2, [r7, #0] 800301e: f022 4200 bic.w r2, r2, #2147483648 ; 0x80000000 8003022: 603a str r2, [r7, #0] 8003024: 6808 ldr r0, [r1, #0] } 8003026: e739 b.n 8002e9c SET_BIT(ADCx->DIFSEL, 8003028: f8d4 20b0 ldr.w r2, [r4, #176] ; 0xb0 800302c: f3c0 0512 ubfx r5, r0, #0, #19 8003030: 432a orrs r2, r5 8003032: f8c4 20b0 str.w r2, [r4, #176] ; 0xb0 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8003036: 2d00 cmp r5, #0 8003038: d051 beq.n 80030de uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800303a: fa90 f2a0 rbit r2, r0 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 800303e: 2a00 cmp r2, #0 8003040: f000 80f7 beq.w 8003232 { return 32U; } return __builtin_clz(value); 8003044: fab2 f282 clz r2, r2 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8003048: 3201 adds r2, #1 800304a: f002 021f and.w r2, r2, #31 800304e: 2a09 cmp r2, #9 8003050: f240 80ef bls.w 8003232 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8003054: fa90 f5a0 rbit r5, r0 if (value == 0U) 8003058: 2d00 cmp r5, #0 800305a: f000 814e beq.w 80032fa return __builtin_clz(value); 800305e: fab5 f585 clz r5, r5 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8003062: 3501 adds r5, #1 8003064: 06ad lsls r5, r5, #26 8003066: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800306a: fa90 f2a0 rbit r2, r0 if (value == 0U) 800306e: 2a00 cmp r2, #0 8003070: f000 8148 beq.w 8003304 return __builtin_clz(value); 8003074: fab2 f282 clz r2, r2 8003078: 3201 adds r2, #1 800307a: f002 021f and.w r2, r2, #31 800307e: 2601 movs r6, #1 8003080: fa06 f202 lsl.w r2, r6, r2 8003084: 4315 orrs r5, r2 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8003086: fa90 f0a0 rbit r0, r0 if (value == 0U) 800308a: 2800 cmp r0, #0 800308c: f000 8138 beq.w 8003300 return __builtin_clz(value); 8003090: fab0 f080 clz r0, r0 8003094: 3001 adds r0, #1 8003096: f000 001f and.w r0, r0, #31 800309a: 2203 movs r2, #3 800309c: f06f 061d mvn.w r6, #29 80030a0: fb12 6200 smlabb r2, r2, r0, r6 80030a4: 0512 lsls r2, r2, #20 80030a6: f042 7200 orr.w r2, r2, #33554432 ; 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 80030aa: 432a orrs r2, r5 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 80030ac: 0dd5 lsrs r5, r2, #23 MODIFY_REG(*preg, 80030ae: 6888 ldr r0, [r1, #8] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 80030b0: f005 0504 and.w r5, r5, #4 80030b4: f104 0614 add.w r6, r4, #20 MODIFY_REG(*preg, 80030b8: f3c2 5204 ubfx r2, r2, #20, #5 80030bc: fa00 fc02 lsl.w ip, r0, r2 80030c0: f04f 0e07 mov.w lr, #7 80030c4: 5970 ldr r0, [r6, r5] 80030c6: fa0e f202 lsl.w r2, lr, r2 80030ca: ea20 0202 bic.w r2, r0, r2 80030ce: ea42 020c orr.w r2, r2, ip 80030d2: 5172 str r2, [r6, r5] if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 80030d4: 680a ldr r2, [r1, #0] } 80030d6: e6f3 b.n 8002ec0 __HAL_LOCK(hadc); 80030d8: 2002 movs r0, #2 } 80030da: b003 add sp, #12 80030dc: bdf0 pop {r4, r5, r6, r7, pc} (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80030de: 0e82 lsrs r2, r0, #26 80030e0: 3201 adds r2, #1 80030e2: f002 001f and.w r0, r2, #31 LL_ADC_SetChannelSamplingTime(hadc->Instance, 80030e6: 2809 cmp r0, #9 80030e8: d84e bhi.n 8003188 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80030ea: 0695 lsls r5, r2, #26 80030ec: 2201 movs r2, #1 80030ee: 4082 lsls r2, r0 80030f0: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 80030f4: 4315 orrs r5, r2 80030f6: eb00 0240 add.w r2, r0, r0, lsl #1 80030fa: 0512 lsls r2, r2, #20 80030fc: e7d5 b.n 80030aa MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); 80030fe: 492b ldr r1, [pc, #172] ; (80031ac ) wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8003100: 4830 ldr r0, [pc, #192] ; (80031c4 ) 8003102: 688a ldr r2, [r1, #8] 8003104: f022 72e0 bic.w r2, r2, #29360128 ; 0x1c00000 8003108: 4332 orrs r2, r6 800310a: f442 0200 orr.w r2, r2, #8388608 ; 0x800000 800310e: 608a str r2, [r1, #8] 8003110: 6802 ldr r2, [r0, #0] 8003112: 492d ldr r1, [pc, #180] ; (80031c8 ) 8003114: 0992 lsrs r2, r2, #6 8003116: fba1 1202 umull r1, r2, r1, r2 800311a: 0992 lsrs r2, r2, #6 800311c: 3201 adds r2, #1 800311e: eb02 0242 add.w r2, r2, r2, lsl #1 8003122: 0092 lsls r2, r2, #2 8003124: 9201 str r2, [sp, #4] while (wait_loop_index != 0UL) 8003126: 9a01 ldr r2, [sp, #4] 8003128: 2a00 cmp r2, #0 800312a: f43f aef7 beq.w 8002f1c wait_loop_index--; 800312e: 9a01 ldr r2, [sp, #4] 8003130: 3a01 subs r2, #1 8003132: 9201 str r2, [sp, #4] while (wait_loop_index != 0UL) 8003134: 9a01 ldr r2, [sp, #4] 8003136: 2a00 cmp r2, #0 8003138: d1f9 bne.n 800312e 800313a: e6ef b.n 8002f1c else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) 800313c: 4d23 ldr r5, [pc, #140] ; (80031cc ) 800313e: 42aa cmp r2, r5 8003140: f47f aeec bne.w 8002f1c && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8003144: f410 0080 ands.w r0, r0, #4194304 ; 0x400000 8003148: f47f aee8 bne.w 8002f1c if (ADC_VREFINT_INSTANCE(hadc)) 800314c: 4a1b ldr r2, [pc, #108] ; (80031bc ) 800314e: 4294 cmp r4, r2 8003150: f43f aee4 beq.w 8002f1c 8003154: 688a ldr r2, [r1, #8] 8003156: f022 72e0 bic.w r2, r2, #29360128 ; 0x1c00000 800315a: 4332 orrs r2, r6 800315c: f442 0280 orr.w r2, r2, #4194304 ; 0x400000 8003160: 608a str r2, [r1, #8] } 8003162: e6d0 b.n 8002f06 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8003164: 0dea lsrs r2, r5, #23 8003166: f002 0204 and.w r2, r2, #4 800316a: f104 0014 add.w r0, r4, #20 MODIFY_REG(*preg, 800316e: f3c5 5504 ubfx r5, r5, #20, #5 8003172: 2607 movs r6, #7 8003174: 40ae lsls r6, r5 8003176: 5885 ldr r5, [r0, r2] 8003178: ea25 0506 bic.w r5, r5, r6 800317c: 5085 str r5, [r0, r2] MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); 800317e: 6962 ldr r2, [r4, #20] 8003180: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000 8003184: 6162 str r2, [r4, #20] } 8003186: e6ea b.n 8002f5e (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8003188: 0695 lsls r5, r2, #26 800318a: eb00 0240 add.w r2, r0, r0, lsl #1 800318e: 3a1e subs r2, #30 8003190: 2601 movs r6, #1 8003192: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 8003196: 0512 lsls r2, r2, #20 8003198: fa06 f000 lsl.w r0, r6, r0 800319c: f042 7200 orr.w r2, r2, #33554432 ; 0x2000000 80031a0: 4305 orrs r5, r0 80031a2: e782 b.n 80030aa 80031a4: 407f0000 .word 0x407f0000 80031a8: 80080000 .word 0x80080000 80031ac: 50000300 .word 0x50000300 80031b0: c3210000 .word 0xc3210000 80031b4: 90c00010 .word 0x90c00010 80031b8: c7520000 .word 0xc7520000 80031bc: 50000100 .word 0x50000100 80031c0: 03fff000 .word 0x03fff000 80031c4: 20000000 .word 0x20000000 80031c8: 053e2d63 .word 0x053e2d63 80031cc: cb840000 .word 0xcb840000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80031d0: fa90 f5a0 rbit r5, r0 if (value == 0U) 80031d4: b11d cbz r5, 80031de return __builtin_clz(value); 80031d6: fab5 f585 clz r5, r5 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 80031da: 42aa cmp r2, r5 80031dc: d071 beq.n 80032c2 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 80031de: 6e62 ldr r2, [r4, #100] ; 0x64 80031e0: 6e66 ldr r6, [r4, #100] ; 0x64 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80031e2: f104 0260 add.w r2, r4, #96 ; 0x60 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 80031e6: f3c6 6684 ubfx r6, r6, #26, #5 80031ea: f104 0764 add.w r7, r4, #100 ; 0x64 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80031ee: fa90 f5a0 rbit r5, r0 if (value == 0U) 80031f2: b11d cbz r5, 80031fc return __builtin_clz(value); 80031f4: fab5 f585 clz r5, r5 80031f8: 42ae cmp r6, r5 80031fa: d050 beq.n 800329e return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 80031fc: 6895 ldr r5, [r2, #8] 80031fe: 6896 ldr r6, [r2, #8] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8003200: f102 0708 add.w r7, r2, #8 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 8003204: f3c6 6684 ubfx r6, r6, #26, #5 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8003208: fa90 f5a0 rbit r5, r0 if (value == 0U) 800320c: b11d cbz r5, 8003216 return __builtin_clz(value); 800320e: fab5 f585 clz r5, r5 8003212: 42ae cmp r6, r5 8003214: d031 beq.n 800327a return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8003216: 68d5 ldr r5, [r2, #12] 8003218: 68d5 ldr r5, [r2, #12] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 800321a: f102 070c add.w r7, r2, #12 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 800321e: f3c5 6284 ubfx r2, r5, #26, #5 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8003222: fa90 f5a0 rbit r5, r0 if (value == 0U) 8003226: 2d00 cmp r5, #0 8003228: f43f ae38 beq.w 8002e9c return __builtin_clz(value); 800322c: fab5 f585 clz r5, r5 8003230: e6f1 b.n 8003016 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8003232: fa90 f5a0 rbit r5, r0 if (value == 0U) 8003236: 2d00 cmp r5, #0 8003238: d059 beq.n 80032ee return __builtin_clz(value); 800323a: fab5 f585 clz r5, r5 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 800323e: 3501 adds r5, #1 8003240: 06ad lsls r5, r5, #26 8003242: f005 45f8 and.w r5, r5, #2080374784 ; 0x7c000000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8003246: fa90 f2a0 rbit r2, r0 if (value == 0U) 800324a: 2a00 cmp r2, #0 800324c: d04d beq.n 80032ea return __builtin_clz(value); 800324e: fab2 f282 clz r2, r2 8003252: 3201 adds r2, #1 8003254: f002 021f and.w r2, r2, #31 8003258: 2601 movs r6, #1 800325a: fa06 f202 lsl.w r2, r6, r2 800325e: 4315 orrs r5, r2 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8003260: fa90 f0a0 rbit r0, r0 if (value == 0U) 8003264: 2800 cmp r0, #0 8003266: d045 beq.n 80032f4 return __builtin_clz(value); 8003268: fab0 f280 clz r2, r0 800326c: 3201 adds r2, #1 800326e: f002 021f and.w r2, r2, #31 8003272: eb02 0242 add.w r2, r2, r2, lsl #1 8003276: 0512 lsls r2, r2, #20 8003278: e717 b.n 80030aa MODIFY_REG(*preg, 800327a: 6838 ldr r0, [r7, #0] 800327c: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 8003280: 6038 str r0, [r7, #0] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 8003282: 68d0 ldr r0, [r2, #12] == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 8003284: 6808 ldr r0, [r1, #0] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8003286: f102 070c add.w r7, r2, #12 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 800328a: 68d2 ldr r2, [r2, #12] 800328c: f3c0 0512 ubfx r5, r0, #0, #19 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 8003290: f3c2 6284 ubfx r2, r2, #26, #5 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 8003294: 2d00 cmp r5, #0 8003296: d1c4 bne.n 8003222 8003298: f3c0 6584 ubfx r5, r0, #26, #5 800329c: e6bb b.n 8003016 MODIFY_REG(*preg, 800329e: 6838 ldr r0, [r7, #0] 80032a0: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 80032a4: 6038 str r0, [r7, #0] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 80032a6: 6890 ldr r0, [r2, #8] == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 80032a8: 6808 ldr r0, [r1, #0] 80032aa: 6896 ldr r6, [r2, #8] 80032ac: f3c0 0512 ubfx r5, r0, #0, #19 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80032b0: f102 0708 add.w r7, r2, #8 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 80032b4: f3c6 6684 ubfx r6, r6, #26, #5 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 80032b8: 2d00 cmp r5, #0 80032ba: d1a5 bne.n 8003208 80032bc: f3c0 6584 ubfx r5, r0, #26, #5 80032c0: e6a0 b.n 8003004 MODIFY_REG(*preg, 80032c2: 6e20 ldr r0, [r4, #96] ; 0x60 80032c4: 4622 mov r2, r4 80032c6: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 80032ca: f842 0f60 str.w r0, [r2, #96]! return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 80032ce: 6e60 ldr r0, [r4, #100] ; 0x64 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 80032d0: 6808 ldr r0, [r1, #0] 80032d2: 6e66 ldr r6, [r4, #100] ; 0x64 80032d4: f3c0 0512 ubfx r5, r0, #0, #19 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80032d8: f104 0764 add.w r7, r4, #100 ; 0x64 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 80032dc: f3c6 6684 ubfx r6, r6, #26, #5 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 80032e0: 2d00 cmp r5, #0 80032e2: d184 bne.n 80031ee 80032e4: f3c0 6584 ubfx r5, r0, #26, #5 80032e8: e683 b.n 8002ff2 80032ea: 2202 movs r2, #2 80032ec: e7b7 b.n 800325e 80032ee: f04f 6580 mov.w r5, #67108864 ; 0x4000000 80032f2: e7a8 b.n 8003246 80032f4: f44f 1240 mov.w r2, #3145728 ; 0x300000 80032f8: e6d7 b.n 80030aa 80032fa: f04f 6580 mov.w r5, #67108864 ; 0x4000000 80032fe: e6b4 b.n 800306a 8003300: 4a01 ldr r2, [pc, #4] ; (8003308 ) 8003302: e6d2 b.n 80030aa 8003304: 2202 movs r2, #2 8003306: e6bd b.n 8003084 8003308: fe500000 .word 0xfe500000 0800330c : if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 800330c: 6803 ldr r3, [r0, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 800330e: 689a ldr r2, [r3, #8] 8003310: 07d2 lsls r2, r2, #31 8003312: d501 bpl.n 8003318 return HAL_OK; 8003314: 2000 movs r0, #0 } 8003316: 4770 bx lr if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART 8003318: 6899 ldr r1, [r3, #8] 800331a: 4a18 ldr r2, [pc, #96] ; (800337c ) 800331c: 4211 tst r1, r2 { 800331e: b570 push {r4, r5, r6, lr} 8003320: 4606 mov r6, r0 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART 8003322: d008 beq.n 8003336 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8003324: 6df3 ldr r3, [r6, #92] ; 0x5c 8003326: f043 0310 orr.w r3, r3, #16 800332a: 65f3 str r3, [r6, #92] ; 0x5c SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800332c: 6e33 ldr r3, [r6, #96] ; 0x60 return HAL_ERROR; 800332e: 2001 movs r0, #1 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8003330: 4303 orrs r3, r0 8003332: 6633 str r3, [r6, #96] ; 0x60 } 8003334: bd70 pop {r4, r5, r6, pc} MODIFY_REG(ADCx->CR, 8003336: 689a ldr r2, [r3, #8] 8003338: 4d11 ldr r5, [pc, #68] ; (8003380 ) 800333a: 402a ands r2, r5 800333c: f042 0201 orr.w r2, r2, #1 8003340: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8003342: f7ff fc13 bl 8002b6c while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8003346: 6833 ldr r3, [r6, #0] tickstart = HAL_GetTick(); 8003348: 4604 mov r4, r0 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 800334a: 681a ldr r2, [r3, #0] 800334c: 07d0 lsls r0, r2, #31 800334e: d413 bmi.n 8003378 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8003350: 689a ldr r2, [r3, #8] 8003352: 07d1 lsls r1, r2, #31 8003354: d404 bmi.n 8003360 MODIFY_REG(ADCx->CR, 8003356: 689a ldr r2, [r3, #8] 8003358: 402a ands r2, r5 800335a: f042 0201 orr.w r2, r2, #1 800335e: 609a str r2, [r3, #8] if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8003360: f7ff fc04 bl 8002b6c 8003364: 1b03 subs r3, r0, r4 8003366: 2b02 cmp r3, #2 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8003368: 6833 ldr r3, [r6, #0] if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 800336a: d9ee bls.n 800334a if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 800336c: 681a ldr r2, [r3, #0] 800336e: 07d2 lsls r2, r2, #31 8003370: d5d8 bpl.n 8003324 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8003372: 681a ldr r2, [r3, #0] 8003374: 07d0 lsls r0, r2, #31 8003376: d5eb bpl.n 8003350 return HAL_OK; 8003378: 2000 movs r0, #0 } 800337a: bd70 pop {r4, r5, r6, pc} 800337c: 8000003f .word 0x8000003f 8003380: 7fffffc0 .word 0x7fffffc0 08003384 : return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8003384: 4b36 ldr r3, [pc, #216] ; (8003460 ) { 8003386: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800338a: f8d3 8008 ldr.w r8, [r3, #8] if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800338e: 6803 ldr r3, [r0, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8003390: 689d ldr r5, [r3, #8] 8003392: f015 0504 ands.w r5, r5, #4 8003396: d116 bne.n 80033c6 __HAL_LOCK(hadc); 8003398: f890 3058 ldrb.w r3, [r0, #88] ; 0x58 800339c: 2b01 cmp r3, #1 800339e: 4604 mov r4, r0 80033a0: d011 beq.n 80033c6 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 80033a2: f008 081f and.w r8, r8, #31 if ((ADC_IS_INDEPENDENT(hadc) != RESET) 80033a6: f240 2321 movw r3, #545 ; 0x221 __HAL_LOCK(hadc); 80033aa: f04f 0c01 mov.w ip, #1 if ((ADC_IS_INDEPENDENT(hadc) != RESET) 80033ae: fa23 f308 lsr.w r3, r3, r8 80033b2: ea13 030c ands.w r3, r3, ip __HAL_LOCK(hadc); 80033b6: f880 c058 strb.w ip, [r0, #88] ; 0x58 if ((ADC_IS_INDEPENDENT(hadc) != RESET) 80033ba: d107 bne.n 80033cc __HAL_UNLOCK(hadc); 80033bc: f880 3058 strb.w r3, [r0, #88] ; 0x58 tmp_hal_status = HAL_ERROR; 80033c0: 4660 mov r0, ip } 80033c2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} tmp_hal_status = HAL_BUSY; 80033c6: 2002 movs r0, #2 } 80033c8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} tmp_hal_status = ADC_Enable(hadc); 80033cc: 460e mov r6, r1 80033ce: 4617 mov r7, r2 80033d0: f7ff ff9c bl 800330c if (tmp_hal_status == HAL_OK) 80033d4: 2800 cmp r0, #0 80033d6: d13b bne.n 8003450 ADC_STATE_CLR_SET(hadc->State, 80033d8: 6de3 ldr r3, [r4, #92] ; 0x5c if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80033da: 6821 ldr r1, [r4, #0] ADC_STATE_CLR_SET(hadc->State, 80033dc: f423 6370 bic.w r3, r3, #3840 ; 0xf00 80033e0: f023 0301 bic.w r3, r3, #1 80033e4: f443 7380 orr.w r3, r3, #256 ; 0x100 80033e8: 65e3 str r3, [r4, #92] ; 0x5c if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80033ea: 4b1e ldr r3, [pc, #120] ; (8003464 ) 80033ec: 4299 cmp r1, r3 80033ee: d033 beq.n 8003458 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 80033f0: 6de3 ldr r3, [r4, #92] ; 0x5c 80033f2: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 80033f6: 65e3 str r3, [r4, #92] ; 0x5c if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 80033f8: 6de3 ldr r3, [r4, #92] ; 0x5c hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 80033fa: 6d60 ldr r0, [r4, #84] ; 0x54 80033fc: 4d1a ldr r5, [pc, #104] ; (8003468 ) if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 80033fe: f413 5380 ands.w r3, r3, #4096 ; 0x1000 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8003402: bf1c itt ne 8003404: 6e23 ldrne r3, [r4, #96] ; 0x60 8003406: f023 0306 bicne.w r3, r3, #6 ADC_CLEAR_ERRORCODE(hadc); 800340a: 6623 str r3, [r4, #96] ; 0x60 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800340c: 62c5 str r5, [r0, #44] ; 0x2c hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800340e: 4d17 ldr r5, [pc, #92] ; (800346c ) 8003410: 6305 str r5, [r0, #48] ; 0x30 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8003412: 4d17 ldr r5, [pc, #92] ; (8003470 ) 8003414: 6345 str r5, [r0, #52] ; 0x34 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8003416: 251c movs r5, #28 8003418: 600d str r5, [r1, #0] __HAL_UNLOCK(hadc); 800341a: 2500 movs r5, #0 800341c: f884 5058 strb.w r5, [r4, #88] ; 0x58 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8003420: 684d ldr r5, [r1, #4] 8003422: f045 0510 orr.w r5, r5, #16 8003426: 604d str r5, [r1, #4] SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 8003428: 68cd ldr r5, [r1, #12] 800342a: f045 0501 orr.w r5, r5, #1 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800342e: 463b mov r3, r7 8003430: 4632 mov r2, r6 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 8003432: 60cd str r5, [r1, #12] tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8003434: 3140 adds r1, #64 ; 0x40 8003436: f000 fae7 bl 8003a08 LL_ADC_REG_StartConversion(hadc->Instance); 800343a: 6822 ldr r2, [r4, #0] MODIFY_REG(ADCx->CR, 800343c: 6893 ldr r3, [r2, #8] 800343e: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 8003442: f023 033f bic.w r3, r3, #63 ; 0x3f 8003446: f043 0304 orr.w r3, r3, #4 800344a: 6093 str r3, [r2, #8] } 800344c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_UNLOCK(hadc); 8003450: f884 5058 strb.w r5, [r4, #88] ; 0x58 } 8003454: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8003458: f1b8 0f00 cmp.w r8, #0 800345c: d0c8 beq.n 80033f0 800345e: e7cb b.n 80033f8 8003460: 50000300 .word 0x50000300 8003464: 50000100 .word 0x50000100 8003468: 08002db9 .word 0x08002db9 800346c: 08002da9 .word 0x08002da9 8003470: 08002e25 .word 0x08002e25 08003474 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 8003474: b5f0 push {r4, r5, r6, r7, lr} assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8003476: f890 2058 ldrb.w r2, [r0, #88] ; 0x58 if (multimode->Mode != ADC_MODE_INDEPENDENT) 800347a: 680e ldr r6, [r1, #0] __HAL_LOCK(hadc); 800347c: 2a01 cmp r2, #1 { 800347e: b09d sub sp, #116 ; 0x74 __HAL_LOCK(hadc); 8003480: d047 beq.n 8003512 /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); ADC_CLEAR_ERRORCODE(&tmphadcSlave); ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8003482: 6804 ldr r4, [r0, #0] 8003484: 4603 mov r3, r0 __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); 8003486: 2200 movs r2, #0 __HAL_LOCK(hadc); 8003488: 2001 movs r0, #1 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 800348a: f1b4 4fa0 cmp.w r4, #1342177280 ; 0x50000000 __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); 800348e: 9218 str r2, [sp, #96] ; 0x60 __HAL_LOCK(hadc); 8003490: f883 0058 strb.w r0, [r3, #88] ; 0x58 ADC_CLEAR_ERRORCODE(&tmphadcSlave); 8003494: 9219 str r2, [sp, #100] ; 0x64 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8003496: d007 beq.n 80034a8 if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8003498: 6dd9 ldr r1, [r3, #92] ; 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); 800349a: f883 2058 strb.w r2, [r3, #88] ; 0x58 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800349e: f041 0120 orr.w r1, r1, #32 80034a2: 65d9 str r1, [r3, #92] ; 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } 80034a4: b01d add sp, #116 ; 0x74 80034a6: bdf0 pop {r4, r5, r6, r7, pc} return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80034a8: 4d26 ldr r5, [pc, #152] ; (8003544 ) 80034aa: 68aa ldr r2, [r5, #8] 80034ac: 0752 lsls r2, r2, #29 80034ae: d50a bpl.n 80034c6 80034b0: 68a2 ldr r2, [r4, #8] SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80034b2: 6dda ldr r2, [r3, #92] ; 0x5c 80034b4: f042 0220 orr.w r2, r2, #32 tmp_hal_status = HAL_ERROR; 80034b8: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80034ba: 65da str r2, [r3, #92] ; 0x5c __HAL_UNLOCK(hadc); 80034bc: 2200 movs r2, #0 80034be: f883 2058 strb.w r2, [r3, #88] ; 0x58 } 80034c2: b01d add sp, #116 ; 0x74 80034c4: bdf0 pop {r4, r5, r6, r7, pc} 80034c6: 68a0 ldr r0, [r4, #8] 80034c8: f010 0004 ands.w r0, r0, #4 80034cc: d1f1 bne.n 80034b2 if (multimode->Mode != ADC_MODE_INDEPENDENT) 80034ce: b31e cbz r6, 8003518 MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 80034d0: f8df e074 ldr.w lr, [pc, #116] ; 8003548 80034d4: 684f ldr r7, [r1, #4] 80034d6: f8de 2008 ldr.w r2, [lr, #8] 80034da: f893 c038 ldrb.w ip, [r3, #56] ; 0x38 80034de: f422 4260 bic.w r2, r2, #57344 ; 0xe000 80034e2: 433a orrs r2, r7 80034e4: ea42 324c orr.w r2, r2, ip, lsl #13 80034e8: f8ce 2008 str.w r2, [lr, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80034ec: 68a2 ldr r2, [r4, #8] 80034ee: 07d4 lsls r4, r2, #31 80034f0: d426 bmi.n 8003540 80034f2: 68a8 ldr r0, [r5, #8] 80034f4: f010 0001 ands.w r0, r0, #1 80034f8: d119 bne.n 800352e MODIFY_REG(tmpADC_Common->CCR, 80034fa: 688a ldr r2, [r1, #8] 80034fc: f8de 1008 ldr.w r1, [lr, #8] 8003500: f421 6171 bic.w r1, r1, #3856 ; 0xf10 8003504: 4332 orrs r2, r6 8003506: f021 010f bic.w r1, r1, #15 800350a: 430a orrs r2, r1 800350c: f8ce 2008 str.w r2, [lr, #8] 8003510: e7d4 b.n 80034bc __HAL_LOCK(hadc); 8003512: 2002 movs r0, #2 } 8003514: b01d add sp, #116 ; 0x74 8003516: bdf0 pop {r4, r5, r6, r7, pc} CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); 8003518: 490b ldr r1, [pc, #44] ; (8003548 ) 800351a: 688a ldr r2, [r1, #8] 800351c: f422 4260 bic.w r2, r2, #57344 ; 0xe000 8003520: 608a str r2, [r1, #8] 8003522: 68a2 ldr r2, [r4, #8] 8003524: 68a8 ldr r0, [r5, #8] 8003526: 4310 orrs r0, r2 8003528: f010 0001 ands.w r0, r0, #1 800352c: d001 beq.n 8003532 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800352e: 2000 movs r0, #0 8003530: e7c4 b.n 80034bc CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8003532: 688a ldr r2, [r1, #8] 8003534: f422 6271 bic.w r2, r2, #3856 ; 0xf10 8003538: f022 020f bic.w r2, r2, #15 800353c: 608a str r2, [r1, #8] 800353e: e7bd b.n 80034bc 8003540: 68aa ldr r2, [r5, #8] 8003542: e7bb b.n 80034bc 8003544: 50000100 .word 0x50000100 8003548: 50000300 .word 0x50000300 0800354c : __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ 800354c: 4907 ldr r1, [pc, #28] ; (800356c ) 800354e: 68ca ldr r2, [r1, #12] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8003550: 0203 lsls r3, r0, #8 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8003552: f64f 00ff movw r0, #63743 ; 0xf8ff (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8003556: f403 63e0 and.w r3, r3, #1792 ; 0x700 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 800355a: 4002 ands r2, r0 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800355c: 4313 orrs r3, r2 reg_value = (reg_value | 800355e: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 8003562: f443 3300 orr.w r3, r3, #131072 ; 0x20000 SCB->AIRCR = reg_value; 8003566: 60cb str r3, [r1, #12] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } 8003568: 4770 bx lr 800356a: bf00 nop 800356c: e000ed00 .word 0xe000ed00 08003570 : \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8003570: 4b1c ldr r3, [pc, #112] ; (80035e4 ) 8003572: 68db ldr r3, [r3, #12] 8003574: f3c3 2302 ubfx r3, r3, #8, #3 * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8003578: b500 push {lr} { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 800357a: f1c3 0e07 rsb lr, r3, #7 800357e: f1be 0f04 cmp.w lr, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8003582: f103 0c04 add.w ip, r3, #4 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8003586: bf28 it cs 8003588: f04f 0e04 movcs.w lr, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 800358c: f1bc 0f06 cmp.w ip, #6 8003590: d91b bls.n 80035ca 8003592: 3b03 subs r3, #3 return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8003594: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 8003598: fa0c fc03 lsl.w ip, ip, r3 800359c: ea22 020c bic.w r2, r2, ip ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80035a0: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff 80035a4: fa0c fc0e lsl.w ip, ip, lr 80035a8: ea21 010c bic.w r1, r1, ip 80035ac: 4099 lsls r1, r3 if ((int32_t)(IRQn) >= 0) 80035ae: 2800 cmp r0, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80035b0: ea41 0102 orr.w r1, r1, r2 if ((int32_t)(IRQn) >= 0) 80035b4: db0c blt.n 80035d0 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80035b6: f100 4060 add.w r0, r0, #3758096384 ; 0xe0000000 80035ba: 0109 lsls r1, r1, #4 80035bc: f500 4061 add.w r0, r0, #57600 ; 0xe100 80035c0: b2c9 uxtb r1, r1 80035c2: f880 1300 strb.w r1, [r0, #768] ; 0x300 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } 80035c6: f85d fb04 ldr.w pc, [sp], #4 80035ca: 2200 movs r2, #0 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80035cc: 4613 mov r3, r2 80035ce: e7e7 b.n 80035a0 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80035d0: 4b05 ldr r3, [pc, #20] ; (80035e8 ) 80035d2: f000 000f and.w r0, r0, #15 80035d6: 0109 lsls r1, r1, #4 80035d8: 4403 add r3, r0 80035da: b2c9 uxtb r1, r1 80035dc: 7619 strb r1, [r3, #24] 80035de: f85d fb04 ldr.w pc, [sp], #4 80035e2: bf00 nop 80035e4: e000ed00 .word 0xe000ed00 80035e8: e000ecfc .word 0xe000ecfc 080035ec : if ((int32_t)(IRQn) >= 0) 80035ec: 2800 cmp r0, #0 80035ee: db07 blt.n 8003600 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80035f0: 4a04 ldr r2, [pc, #16] ; (8003604 ) 80035f2: 0941 lsrs r1, r0, #5 80035f4: 2301 movs r3, #1 80035f6: f000 001f and.w r0, r0, #31 80035fa: 4083 lsls r3, r0 80035fc: f842 3021 str.w r3, [r2, r1, lsl #2] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } 8003600: 4770 bx lr 8003602: bf00 nop 8003604: e000e100 .word 0xe000e100 08003608 : function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8003608: 3801 subs r0, #1 800360a: f1b0 7f80 cmp.w r0, #16777216 ; 0x1000000 800360e: d210 bcs.n 8003632 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8003610: b410 push {r4} { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8003612: f04f 23e0 mov.w r3, #3758153728 ; 0xe000e000 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8003616: 4c08 ldr r4, [pc, #32] ; (8003638 ) SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8003618: 6158 str r0, [r3, #20] SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800361a: f04f 0cf0 mov.w ip, #240 ; 0xf0 800361e: f884 c023 strb.w ip, [r4, #35] ; 0x23 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8003622: 2200 movs r2, #0 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8003624: 2107 movs r1, #7 SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8003626: 4610 mov r0, r2 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8003628: 619a str r2, [r3, #24] return SysTick_Config(TicksNumb); } 800362a: f85d 4b04 ldr.w r4, [sp], #4 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800362e: 6119 str r1, [r3, #16] 8003630: 4770 bx lr return (1UL); /* Reload value impossible */ 8003632: 2001 movs r0, #1 8003634: 4770 bx lr 8003636: bf00 nop 8003638: e000ed00 .word 0xe000ed00 0800363c : * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { /* Check DAC handle */ if (hdac == NULL) 800363c: b188 cbz r0, 8003662 { 800363e: b510 push {r4, lr} return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 8003640: 7903 ldrb r3, [r0, #4] 8003642: 4604 mov r4, r0 8003644: f003 02ff and.w r2, r3, #255 ; 0xff 8003648: b13b cbz r3, 800365a /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 800364a: 2300 movs r3, #0 hdac->State = HAL_DAC_STATE_BUSY; 800364c: 2102 movs r1, #2 /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 800364e: 2201 movs r2, #1 hdac->State = HAL_DAC_STATE_BUSY; 8003650: 7121 strb r1, [r4, #4] hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8003652: 6123 str r3, [r4, #16] hdac->State = HAL_DAC_STATE_READY; 8003654: 7122 strb r2, [r4, #4] /* Return function status */ return HAL_OK; 8003656: 4618 mov r0, r3 } 8003658: bd10 pop {r4, pc} hdac->Lock = HAL_UNLOCKED; 800365a: 7142 strb r2, [r0, #5] HAL_DAC_MspInit(hdac); 800365c: f7fe fd9c bl 8002198 8003660: e7f3 b.n 800364a return HAL_ERROR; 8003662: 2001 movs r0, #1 } 8003664: 4770 bx lr 8003666: bf00 nop 08003668 : * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 8003668: b5f8 push {r3, r4, r5, r6, r7, lr} /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); 800366a: 7943 ldrb r3, [r0, #5] 800366c: 2b01 cmp r3, #1 800366e: d02e beq.n 80036ce 8003670: 4604 mov r4, r0 /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8003672: 2602 movs r6, #2 /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 8003674: 6822 ldr r2, [r4, #0] hdac->State = HAL_DAC_STATE_BUSY; 8003676: 7126 strb r6, [r4, #4] __HAL_LOCK(hdac); 8003678: 2001 movs r0, #1 800367a: 7160 strb r0, [r4, #5] __HAL_DAC_ENABLE(hdac, Channel); 800367c: 460d mov r5, r1 800367e: f005 0710 and.w r7, r5, #16 8003682: 6811 ldr r1, [r2, #0] 8003684: fa00 f307 lsl.w r3, r0, r7 8003688: 430b orrs r3, r1 800368a: 6013 str r3, [r2, #0] /* Ensure minimum wait before using peripheral after enabling it */ HAL_Delay(1); 800368c: f7ff fa74 bl 8002b78 if (Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8003690: 6822 ldr r2, [r4, #0] if (Channel == DAC_CHANNEL_1) 8003692: b96d cbnz r5, 80036b0 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8003694: 6813 ldr r3, [r2, #0] 8003696: f003 033e and.w r3, r3, #62 ; 0x3e 800369a: 42b3 cmp r3, r6 800369c: d103 bne.n 80036a6 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 800369e: 6853 ldr r3, [r2, #4] 80036a0: f043 0301 orr.w r3, r3, #1 80036a4: 6053 str r3, [r2, #4] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); 80036a6: 2000 movs r0, #0 hdac->State = HAL_DAC_STATE_READY; 80036a8: 2301 movs r3, #1 80036aa: 7123 strb r3, [r4, #4] __HAL_UNLOCK(hdac); 80036ac: 7160 strb r0, [r4, #5] /* Return function status */ return HAL_OK; } 80036ae: bdf8 pop {r3, r4, r5, r6, r7, pc} if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 80036b0: 6813 ldr r3, [r2, #0] 80036b2: 40be lsls r6, r7 80036b4: f403 1378 and.w r3, r3, #4063232 ; 0x3e0000 80036b8: 42b3 cmp r3, r6 80036ba: d1f4 bne.n 80036a6 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 80036bc: 6853 ldr r3, [r2, #4] 80036be: f043 0302 orr.w r3, r3, #2 80036c2: 6053 str r3, [r2, #4] __HAL_UNLOCK(hdac); 80036c4: 2000 movs r0, #0 hdac->State = HAL_DAC_STATE_READY; 80036c6: 2301 movs r3, #1 80036c8: 7123 strb r3, [r4, #4] __HAL_UNLOCK(hdac); 80036ca: 7160 strb r0, [r4, #5] return HAL_OK; 80036cc: e7ef b.n 80036ae __HAL_LOCK(hdac); 80036ce: 2002 movs r0, #2 } 80036d0: bdf8 pop {r3, r4, r5, r6, r7, pc} 80036d2: bf00 nop 080036d4 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 80036d4: b410 push {r4} 80036d6: b083 sub sp, #12 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */ if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL) 80036d8: 6800 ldr r0, [r0, #0] __IO uint32_t tmp = 0UL; 80036da: 2400 movs r4, #0 80036dc: 9401 str r4, [sp, #4] if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL) 80036de: 6bc4 ldr r4, [r0, #60] ; 0x3c { assert_param(IS_DAC_DATA(Data)); } tmp = (uint32_t)hdac->Instance; 80036e0: 9001 str r0, [sp, #4] if (Channel == DAC_CHANNEL_1) 80036e2: b951 cbnz r1, 80036fa { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 80036e4: 9901 ldr r1, [sp, #4] 80036e6: 3108 adds r1, #8 80036e8: 440a add r2, r1 80036ea: 9201 str r2, [sp, #4] tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 80036ec: 9a01 ldr r2, [sp, #4] /* Return function status */ return HAL_OK; } 80036ee: 2000 movs r0, #0 *(__IO uint32_t *) tmp = Data; 80036f0: 6013 str r3, [r2, #0] } 80036f2: b003 add sp, #12 80036f4: f85d 4b04 ldr.w r4, [sp], #4 80036f8: 4770 bx lr tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 80036fa: 9901 ldr r1, [sp, #4] 80036fc: 3114 adds r1, #20 80036fe: 440a add r2, r1 8003700: 9201 str r2, [sp, #4] 8003702: e7f3 b.n 80036ec 08003704 : assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); /* Process locked */ __HAL_LOCK(hdac); 8003704: 7943 ldrb r3, [r0, #5] if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) 8003706: f8d1 c008 ldr.w ip, [r1, #8] __HAL_LOCK(hdac); 800370a: 2b01 cmp r3, #1 800370c: f000 80d0 beq.w 80038b0 8003710: 2301 movs r3, #1 { 8003712: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 8003716: f1bc 0f04 cmp.w ip, #4 __HAL_LOCK(hdac); 800371a: 7143 strb r3, [r0, #5] hdac->State = HAL_DAC_STATE_BUSY; 800371c: f04f 0302 mov.w r3, #2 8003720: 4605 mov r5, r0 8003722: 460f mov r7, r1 8003724: 4616 mov r6, r2 8003726: 7103 strb r3, [r0, #4] if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 8003728: d07d beq.n 8003826 if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 800372a: 6800 ldr r0, [r0, #0] MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 800372c: f002 0610 and.w r6, r2, #16 if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 8003730: 69fb ldr r3, [r7, #28] 8003732: 2b01 cmp r3, #1 8003734: d108 bne.n 8003748 tmpreg1 = hdac->Instance->CCR; 8003736: 6b82 ldr r2, [r0, #56] ; 0x38 /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8003738: 6a3b ldr r3, [r7, #32] tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 800373a: 211f movs r1, #31 800373c: 40b1 lsls r1, r6 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 800373e: 40b3 lsls r3, r6 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 8003740: ea22 0201 bic.w r2, r2, r1 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8003744: 4313 orrs r3, r2 /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 8003746: 6383 str r3, [r0, #56] ; 0x38 /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 8003748: 69ba ldr r2, [r7, #24] tmpreg1 = hdac->Instance->MCR; 800374a: 6bc3 ldr r3, [r0, #60] ; 0x3c tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 800374c: 2107 movs r1, #7 if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 800374e: 2a01 cmp r2, #1 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 8003750: fa01 f106 lsl.w r1, r1, r6 if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 8003754: d063 beq.n 800381e { connectOnChip = 0x00000000UL; } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 8003756: 2a02 cmp r2, #2 { connectOnChip = DAC_MCR_MODE1_0; } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8003758: 697a ldr r2, [r7, #20] 800375a: bf16 itet ne 800375c: fab2 fe82 clzne lr, r2 connectOnChip = DAC_MCR_MODE1_0; 8003760: f04f 0e01 moveq.w lr, #1 if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8003764: ea4f 1e5e movne.w lr, lr, lsr #5 /* Configure for the selected DAC channel: DMA double data mode */ tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; /* Clear DAC_MCR_SINFORMATx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: Signed format */ tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; 8003768: 797c ldrb r4, [r7, #5] tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; 800376a: f897 8004 ldrb.w r8, [r7, #4] tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; 800376e: f1a4 0401 sub.w r4, r4, #1 8003772: fab4 f484 clz r4, r4 tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; 8003776: f1a8 0801 sub.w r8, r8, #1 tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; 800377a: 0964 lsrs r4, r4, #5 tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; 800377c: fab8 f888 clz r8, r8 8003780: ea4f 1858 mov.w r8, r8, lsr #5 tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; 8003784: 0264 lsls r4, r4, #9 8003786: ea44 2408 orr.w r4, r4, r8, lsl #8 800378a: ea44 040c orr.w r4, r4, ip 800378e: ea44 040e orr.w r4, r4, lr 8003792: 4314 orrs r4, r2 tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); 8003794: f44f 7200 mov.w r2, #512 ; 0x200 8003798: 40b2 lsls r2, r6 800379a: 430a orrs r2, r1 800379c: ea23 0802 bic.w r8, r3, r2 tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL)); 80037a0: f44f 7380 mov.w r3, #256 ; 0x100 80037a4: 40b3 lsls r3, r6 tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); 80037a6: ea28 0803 bic.w r8, r8, r3 /* Clear DAC_MCR_HFSEL bits */ tmpreg1 &= ~(DAC_MCR_HFSEL); /* Configure for both DAC channels: high frequency mode */ if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) 80037aa: 683b ldr r3, [r7, #0] 80037ac: 2b02 cmp r3, #2 tmpreg1 &= ~(DAC_MCR_HFSEL); 80037ae: f428 4840 bic.w r8, r8, #49152 ; 0xc000 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) 80037b2: d074 beq.n 800389e tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE; } } else { tmpreg1 |= sConfig->DAC_HighFrequency; 80037b4: ea48 0803 orr.w r8, r8, r3 } /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80037b8: 40b4 lsls r4, r6 80037ba: ea44 0408 orr.w r4, r4, r8 /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 80037be: 63c4 str r4, [r0, #60] ; 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 80037c0: 6803 ldr r3, [r0, #0] 80037c2: f44f 4280 mov.w r2, #16384 ; 0x4000 80037c6: 40b2 lsls r2, r6 80037c8: ea23 0302 bic.w r3, r3, r2 80037cc: 6003 str r3, [r0, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */ tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 80037ce: e9d7 2303 ldrd r2, r3, [r7, #12] tmpreg1 = hdac->Instance->CR; 80037d2: 6804 ldr r4, [r0, #0] tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 80037d4: f640 71fe movw r1, #4094 ; 0xffe 80037d8: 40b1 lsls r1, r6 80037da: ea24 0401 bic.w r4, r4, r1 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80037de: fa02 f106 lsl.w r1, r2, r6 80037e2: 4321 orrs r1, r4 tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 80037e4: 019b lsls r3, r3, #6 hdac->Instance->CR = tmpreg1; 80037e6: 6001 str r1, [r0, #0] tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; 80037e8: f3c2 0283 ubfx r2, r2, #2, #4 tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; 80037ec: f403 6370 and.w r3, r3, #3840 ; 0xf00 80037f0: 4313 orrs r3, r2 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 80037f2: 24c0 movs r4, #192 ; 0xc0 80037f4: 6802 ldr r2, [r0, #0] 80037f6: 40b4 lsls r4, r6 80037f8: ea22 0204 bic.w r2, r2, r4 80037fc: 6002 str r2, [r0, #0] /* Modify STMODR register value depending on DAC_Channel */ MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); 80037fe: 6e02 ldr r2, [r0, #96] ; 0x60 8003800: f640 710f movw r1, #3855 ; 0xf0f 8003804: 40b1 lsls r1, r6 8003806: ea22 0201 bic.w r2, r2, r1 800380a: 40b3 lsls r3, r6 /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); 800380c: 2100 movs r1, #0 MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); 800380e: 4313 orrs r3, r2 hdac->State = HAL_DAC_STATE_READY; 8003810: 2201 movs r2, #1 MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); 8003812: 6603 str r3, [r0, #96] ; 0x60 /* Return function status */ return HAL_OK; 8003814: 4608 mov r0, r1 hdac->State = HAL_DAC_STATE_READY; 8003816: 712a strb r2, [r5, #4] __HAL_UNLOCK(hdac); 8003818: 7169 strb r1, [r5, #5] } 800381a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 800381e: 697a ldr r2, [r7, #20] connectOnChip = 0x00000000UL; 8003820: f04f 0e00 mov.w lr, #0 8003824: e7a0 b.n 8003768 tickstart = HAL_GetTick(); 8003826: f7ff f9a1 bl 8002b6c 800382a: 4604 mov r4, r0 if (Channel == DAC_CHANNEL_1) 800382c: b12e cbz r6, 800383a 800382e: e014 b.n 800385a if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8003830: f7ff f99c bl 8002b6c 8003834: 1b03 subs r3, r0, r4 8003836: 2b01 cmp r3, #1 8003838: d83c bhi.n 80038b4 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800383a: 682b ldr r3, [r5, #0] 800383c: 6b5b ldr r3, [r3, #52] ; 0x34 800383e: 041b lsls r3, r3, #16 8003840: d4f6 bmi.n 8003830 HAL_Delay(1); 8003842: 2001 movs r0, #1 8003844: f7ff f998 bl 8002b78 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8003848: 6828 ldr r0, [r5, #0] 800384a: 6a7b ldr r3, [r7, #36] ; 0x24 800384c: 6403 str r3, [r0, #64] ; 0x40 800384e: e00e b.n 800386e if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8003850: f7ff f98c bl 8002b6c 8003854: 1b03 subs r3, r0, r4 8003856: 2b01 cmp r3, #1 8003858: d82c bhi.n 80038b4 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 800385a: 682b ldr r3, [r5, #0] 800385c: 6b5b ldr r3, [r3, #52] ; 0x34 800385e: 2b00 cmp r3, #0 8003860: dbf6 blt.n 8003850 HAL_Delay(1U); 8003862: 2001 movs r0, #1 8003864: f7ff f988 bl 8002b78 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8003868: 6828 ldr r0, [r5, #0] 800386a: 6a7b ldr r3, [r7, #36] ; 0x24 800386c: 6443 str r3, [r0, #68] ; 0x44 MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 800386e: 6c83 ldr r3, [r0, #72] ; 0x48 8003870: 6aba ldr r2, [r7, #40] ; 0x28 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 8003872: f8d7 c008 ldr.w ip, [r7, #8] MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 8003876: f006 0610 and.w r6, r6, #16 800387a: f240 31ff movw r1, #1023 ; 0x3ff 800387e: 40b1 lsls r1, r6 8003880: 40b2 lsls r2, r6 8003882: ea23 0301 bic.w r3, r3, r1 8003886: 4313 orrs r3, r2 8003888: 6483 str r3, [r0, #72] ; 0x48 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 800388a: 6cc3 ldr r3, [r0, #76] ; 0x4c 800388c: 6afa ldr r2, [r7, #44] ; 0x2c 800388e: 21ff movs r1, #255 ; 0xff 8003890: 40b1 lsls r1, r6 8003892: 40b2 lsls r2, r6 8003894: ea23 0301 bic.w r3, r3, r1 8003898: 4313 orrs r3, r2 800389a: 64c3 str r3, [r0, #76] ; 0x4c 800389c: e748 b.n 8003730 hclkfreq = HAL_RCC_GetHCLKFreq(); 800389e: f000 fe61 bl 8004564 if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ) 80038a2: 4b0c ldr r3, [pc, #48] ; (80038d4 ) 80038a4: 4298 cmp r0, r3 80038a6: d90d bls.n 80038c4 hdac->Instance->MCR = tmpreg1; 80038a8: 6828 ldr r0, [r5, #0] tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ; 80038aa: f448 4800 orr.w r8, r8, #32768 ; 0x8000 80038ae: e783 b.n 80037b8 __HAL_LOCK(hdac); 80038b0: 2002 movs r0, #2 } 80038b2: 4770 bx lr SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 80038b4: 692b ldr r3, [r5, #16] hdac->State = HAL_DAC_STATE_TIMEOUT; 80038b6: 2203 movs r2, #3 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 80038b8: f043 0308 orr.w r3, r3, #8 80038bc: 612b str r3, [r5, #16] return HAL_TIMEOUT; 80038be: 4610 mov r0, r2 hdac->State = HAL_DAC_STATE_TIMEOUT; 80038c0: 712a strb r2, [r5, #4] return HAL_TIMEOUT; 80038c2: e7aa b.n 800381a else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) 80038c4: 4b04 ldr r3, [pc, #16] ; (80038d8 ) 80038c6: 4298 cmp r0, r3 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ; 80038c8: bf88 it hi 80038ca: f448 4880 orrhi.w r8, r8, #16384 ; 0x4000 hdac->Instance->MCR = tmpreg1; 80038ce: 6828 ldr r0, [r5, #0] 80038d0: e772 b.n 80037b8 80038d2: bf00 nop 80038d4: 09896800 .word 0x09896800 80038d8: 04c4b400 .word 0x04c4b400 080038dc : HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) 80038dc: 2800 cmp r0, #0 80038de: d078 beq.n 80039d2 { 80038e0: b4f0 push {r4, r5, r6, r7} assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 80038e2: 4b3d ldr r3, [pc, #244] ; (80039d8 ) 80038e4: 6804 ldr r4, [r0, #0] 80038e6: 429c cmp r4, r3 80038e8: d95f bls.n 80039aa hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 80038ea: 4a3c ldr r2, [pc, #240] ; (80039dc ) 80038ec: 4b3c ldr r3, [pc, #240] ; (80039e0 ) hdma->DmaBaseAddress = DMA2; 80038ee: 493d ldr r1, [pc, #244] ; (80039e4 ) hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 80038f0: 4422 add r2, r4 80038f2: fba3 3202 umull r3, r2, r3, r2 80038f6: 0912 lsrs r2, r2, #4 80038f8: 0092 lsls r2, r2, #2 } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 80038fa: 2302 movs r3, #2 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | 80038fc: 6885 ldr r5, [r0, #8] hdma->State = HAL_DMA_STATE_BUSY; 80038fe: f880 3025 strb.w r3, [r0, #37] ; 0x25 tmp |= hdma->Init.Direction | 8003902: 68c3 ldr r3, [r0, #12] #else DMAMUX1_ChannelBase = DMAMUX1_Channel7; #endif /* STM32G4x1xx) */ } dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8003904: 4e36 ldr r6, [pc, #216] ; (80039e0 ) if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8003906: 4f34 ldr r7, [pc, #208] ; (80039d8 ) 8003908: e9c0 1210 strd r1, r2, [r0, #64] ; 0x40 hdma->Init.PeriphInc | hdma->Init.MemInc | 800390c: 6901 ldr r1, [r0, #16] tmp |= hdma->Init.Direction | 800390e: 432b orrs r3, r5 hdma->Init.PeriphInc | hdma->Init.MemInc | 8003910: 430b orrs r3, r1 8003912: 6941 ldr r1, [r0, #20] 8003914: 430b orrs r3, r1 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8003916: 6981 ldr r1, [r0, #24] 8003918: 430b orrs r3, r1 tmp = hdma->Instance->CCR; 800391a: 6821 ldr r1, [r4, #0] tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 800391c: f421 4cff bic.w ip, r1, #32640 ; 0x7f80 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8003920: 69c1 ldr r1, [r0, #28] 8003922: 430b orrs r3, r1 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 8003924: b2e1 uxtb r1, r4 8003926: 3908 subs r1, #8 8003928: fba6 6101 umull r6, r1, r6, r1 hdma->Init.Mode | hdma->Init.Priority; 800392c: 6a06 ldr r6, [r0, #32] tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 800392e: f02c 0c70 bic.w ip, ip, #112 ; 0x70 hdma->Init.Mode | hdma->Init.Priority; 8003932: 4333 orrs r3, r6 tmp |= hdma->Init.Direction | 8003934: ea43 030c orr.w r3, r3, ip hdma->Instance->CCR = tmp; 8003938: 6023 str r3, [r4, #0] if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 800393a: 4e2b ldr r6, [pc, #172] ; (80039e8 ) 800393c: 4b2b ldr r3, [pc, #172] ; (80039ec ) hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 800393e: f3c1 1104 ubfx r1, r1, #4, #5 if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 8003942: 42bc cmp r4, r7 8003944: bf98 it ls 8003946: 4633 movls r3, r6 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 8003948: f04f 0c01 mov.w ip, #1 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800394c: 4c28 ldr r4, [pc, #160] ; (80039f0 ) 800394e: 64c4 str r4, [r0, #76] ; 0x4c hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 8003950: fa0c f101 lsl.w r1, ip, r1 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 8003954: 18d4 adds r4, r2, r3 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8003956: f5b5 4f80 cmp.w r5, #16384 ; 0x4000 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); 800395a: 6501 str r1, [r0, #80] ; 0x50 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 800395c: 6484 str r4, [r0, #72] ; 0x48 800395e: ea4f 0292 mov.w r2, r2, lsr #2 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8003962: d02b beq.n 80039bc hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8003964: 6845 ldr r5, [r0, #4] 8003966: b2ec uxtb r4, r5 if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8003968: 3d01 subs r5, #1 800396a: 2d03 cmp r5, #3 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 800396c: f843 4022 str.w r4, [r3, r2, lsl #2] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003970: f8c6 1084 str.w r1, [r6, #132] ; 0x84 if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 8003974: d828 bhi.n 80039c8 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8003976: 4b1f ldr r3, [pc, #124] ; (80039f4 ) hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8003978: 4d1f ldr r5, [pc, #124] ; (80039f8 ) hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800397a: 4a20 ldr r2, [pc, #128] ; (80039fc ) hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800397c: 4423 add r3, r4 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); 800397e: 3c01 subs r4, #1 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8003980: 009b lsls r3, r3, #2 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); 8003982: f004 041f and.w r4, r4, #31 8003986: fa0c f404 lsl.w r4, ip, r4 hdma->DMAmuxRequestGen->RGCR = 0U; 800398a: 2100 movs r1, #0 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800398c: e9c0 3515 strd r3, r5, [r0, #84] ; 0x54 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); 8003990: 65c4 str r4, [r0, #92] ; 0x5c hdma->DMAmuxRequestGen->RGCR = 0U; 8003992: 6019 str r1, [r3, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003994: 6454 str r4, [r2, #68] ; 0x44 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8003996: 2300 movs r3, #0 hdma->State = HAL_DMA_STATE_READY; 8003998: 2201 movs r2, #1 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800399a: 63c3 str r3, [r0, #60] ; 0x3c hdma->Lock = HAL_UNLOCKED; 800399c: f880 3024 strb.w r3, [r0, #36] ; 0x24 hdma->State = HAL_DMA_STATE_READY; 80039a0: f880 2025 strb.w r2, [r0, #37] ; 0x25 } 80039a4: bcf0 pop {r4, r5, r6, r7} return HAL_OK; 80039a6: 4618 mov r0, r3 } 80039a8: 4770 bx lr hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 80039aa: 4a15 ldr r2, [pc, #84] ; (8003a00 ) 80039ac: 4b0c ldr r3, [pc, #48] ; (80039e0 ) hdma->DmaBaseAddress = DMA1; 80039ae: 4915 ldr r1, [pc, #84] ; (8003a04 ) hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 80039b0: 4422 add r2, r4 80039b2: fba3 3202 umull r3, r2, r3, r2 80039b6: 0912 lsrs r2, r2, #4 80039b8: 0092 lsls r2, r2, #2 hdma->DmaBaseAddress = DMA1; 80039ba: e79e b.n 80038fa hdma->Init.Request = DMA_REQUEST_MEM2MEM; 80039bc: 2400 movs r4, #0 80039be: 6044 str r4, [r0, #4] hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 80039c0: f843 4022 str.w r4, [r3, r2, lsl #2] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80039c4: f8c6 1084 str.w r1, [r6, #132] ; 0x84 hdma->DMAmuxRequestGen = 0U; 80039c8: 2300 movs r3, #0 hdma->DMAmuxRequestGenStatus = 0U; 80039ca: e9c0 3315 strd r3, r3, [r0, #84] ; 0x54 hdma->DMAmuxRequestGenStatusMask = 0U; 80039ce: 65c3 str r3, [r0, #92] ; 0x5c 80039d0: e7e1 b.n 8003996 return HAL_ERROR; 80039d2: 2001 movs r0, #1 } 80039d4: 4770 bx lr 80039d6: bf00 nop 80039d8: 40020407 .word 0x40020407 80039dc: bffdfbf8 .word 0xbffdfbf8 80039e0: cccccccd .word 0xcccccccd 80039e4: 40020400 .word 0x40020400 80039e8: 40020800 .word 0x40020800 80039ec: 40020820 .word 0x40020820 80039f0: 40020880 .word 0x40020880 80039f4: 1000823f .word 0x1000823f 80039f8: 40020940 .word 0x40020940 80039fc: 40020900 .word 0x40020900 8003a00: bffdfff8 .word 0xbffdfff8 8003a04: 40020000 .word 0x40020000 08003a08 : { 8003a08: b4f0 push {r4, r5, r6, r7} __HAL_LOCK(hdma); 8003a0a: f890 4024 ldrb.w r4, [r0, #36] ; 0x24 8003a0e: 2c01 cmp r4, #1 8003a10: d051 beq.n 8003ab6 8003a12: 2401 movs r4, #1 8003a14: f880 4024 strb.w r4, [r0, #36] ; 0x24 if (HAL_DMA_STATE_READY == hdma->State) 8003a18: f890 4025 ldrb.w r4, [r0, #37] ; 0x25 8003a1c: 2c01 cmp r4, #1 8003a1e: d005 beq.n 8003a2c __HAL_UNLOCK(hdma); 8003a20: 2300 movs r3, #0 8003a22: f880 3024 strb.w r3, [r0, #36] ; 0x24 } 8003a26: bcf0 pop {r4, r5, r6, r7} status = HAL_BUSY; 8003a28: 2002 movs r0, #2 } 8003a2a: 4770 bx lr hdma->State = HAL_DMA_STATE_BUSY; 8003a2c: 2402 movs r4, #2 8003a2e: f880 4025 strb.w r4, [r0, #37] ; 0x25 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8003a32: 2400 movs r4, #0 8003a34: 63c4 str r4, [r0, #60] ; 0x3c __HAL_DMA_DISABLE(hdma); 8003a36: 6804 ldr r4, [r0, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003a38: 6cc6 ldr r6, [r0, #76] ; 0x4c __HAL_DMA_DISABLE(hdma); 8003a3a: 6825 ldr r5, [r4, #0] 8003a3c: f025 0501 bic.w r5, r5, #1 8003a40: 6025 str r5, [r4, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003a42: e9d0 7514 ldrd r7, r5, [r0, #80] ; 0x50 8003a46: 6077 str r7, [r6, #4] if (hdma->DMAmuxRequestGen != 0U) 8003a48: b115 cbz r5, 8003a50 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003a4a: e9d0 6716 ldrd r6, r7, [r0, #88] ; 0x58 8003a4e: 6077 str r7, [r6, #4] hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 8003a50: 6c46 ldr r6, [r0, #68] ; 0x44 8003a52: 6c07 ldr r7, [r0, #64] ; 0x40 8003a54: f006 0c1f and.w ip, r6, #31 8003a58: 2601 movs r6, #1 8003a5a: fa06 f60c lsl.w r6, r6, ip 8003a5e: 607e str r6, [r7, #4] hdma->Instance->CNDTR = DataLength; 8003a60: 6063 str r3, [r4, #4] if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8003a62: 6883 ldr r3, [r0, #8] 8003a64: 2b10 cmp r3, #16 if (NULL != hdma->XferHalfCpltCallback) 8003a66: 6b03 ldr r3, [r0, #48] ; 0x30 hdma->Instance->CPAR = DstAddress; 8003a68: bf0b itete eq 8003a6a: 60a2 streq r2, [r4, #8] hdma->Instance->CPAR = SrcAddress; 8003a6c: 60a1 strne r1, [r4, #8] hdma->Instance->CMAR = SrcAddress; 8003a6e: 60e1 streq r1, [r4, #12] hdma->Instance->CMAR = DstAddress; 8003a70: 60e2 strne r2, [r4, #12] if (NULL != hdma->XferHalfCpltCallback) 8003a72: b1bb cbz r3, 8003aa4 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003a74: 6823 ldr r3, [r4, #0] 8003a76: f043 030e orr.w r3, r3, #14 8003a7a: 6023 str r3, [r4, #0] if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8003a7c: 6c83 ldr r3, [r0, #72] ; 0x48 8003a7e: 681a ldr r2, [r3, #0] 8003a80: 03d2 lsls r2, r2, #15 8003a82: d503 bpl.n 8003a8c hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8003a84: 681a ldr r2, [r3, #0] 8003a86: f442 7280 orr.w r2, r2, #256 ; 0x100 8003a8a: 601a str r2, [r3, #0] if (hdma->DMAmuxRequestGen != 0U) 8003a8c: b11d cbz r5, 8003a96 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8003a8e: 682b ldr r3, [r5, #0] 8003a90: f443 7380 orr.w r3, r3, #256 ; 0x100 8003a94: 602b str r3, [r5, #0] __HAL_DMA_ENABLE(hdma); 8003a96: 6823 ldr r3, [r4, #0] 8003a98: f043 0301 orr.w r3, r3, #1 HAL_StatusTypeDef status = HAL_OK; 8003a9c: 2000 movs r0, #0 __HAL_DMA_ENABLE(hdma); 8003a9e: 6023 str r3, [r4, #0] } 8003aa0: bcf0 pop {r4, r5, r6, r7} 8003aa2: 4770 bx lr __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8003aa4: 6823 ldr r3, [r4, #0] 8003aa6: f023 0304 bic.w r3, r3, #4 8003aaa: 6023 str r3, [r4, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 8003aac: 6823 ldr r3, [r4, #0] 8003aae: f043 030a orr.w r3, r3, #10 8003ab2: 6023 str r3, [r4, #0] 8003ab4: e7e2 b.n 8003a7c __HAL_LOCK(hdma); 8003ab6: 2002 movs r0, #2 } 8003ab8: bcf0 pop {r4, r5, r6, r7} 8003aba: 4770 bx lr 08003abc : { 8003abc: b470 push {r4, r5, r6} if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT))) 8003abe: 6c43 ldr r3, [r0, #68] ; 0x44 uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8003ac0: 6c06 ldr r6, [r0, #64] ; 0x40 uint32_t source_it = hdma->Instance->CCR; 8003ac2: 6805 ldr r5, [r0, #0] uint32_t flag_it = hdma->DmaBaseAddress->ISR; 8003ac4: 6831 ldr r1, [r6, #0] uint32_t source_it = hdma->Instance->CCR; 8003ac6: 682c ldr r4, [r5, #0] if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT))) 8003ac8: f003 031f and.w r3, r3, #31 8003acc: 2204 movs r2, #4 8003ace: 409a lsls r2, r3 8003ad0: 420a tst r2, r1 8003ad2: d00e beq.n 8003af2 8003ad4: f014 0f04 tst.w r4, #4 8003ad8: d00b beq.n 8003af2 if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8003ada: 682b ldr r3, [r5, #0] 8003adc: 069b lsls r3, r3, #26 8003ade: d403 bmi.n 8003ae8 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8003ae0: 682b ldr r3, [r5, #0] 8003ae2: f023 0304 bic.w r3, r3, #4 8003ae6: 602b str r3, [r5, #0] if (hdma->XferHalfCpltCallback != NULL) 8003ae8: 6b03 ldr r3, [r0, #48] ; 0x30 hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU)); 8003aea: 6072 str r2, [r6, #4] if (hdma->XferHalfCpltCallback != NULL) 8003aec: b1cb cbz r3, 8003b22 } 8003aee: bc70 pop {r4, r5, r6} hdma->XferCpltCallback(hdma); 8003af0: 4718 bx r3 else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)))) 8003af2: 2202 movs r2, #2 8003af4: 409a lsls r2, r3 8003af6: 420a tst r2, r1 8003af8: d015 beq.n 8003b26 && (0U != (source_it & DMA_IT_TC))) 8003afa: f014 0f02 tst.w r4, #2 8003afe: d012 beq.n 8003b26 if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8003b00: 682b ldr r3, [r5, #0] 8003b02: 0699 lsls r1, r3, #26 8003b04: d406 bmi.n 8003b14 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8003b06: 682b ldr r3, [r5, #0] 8003b08: f023 030a bic.w r3, r3, #10 8003b0c: 602b str r3, [r5, #0] hdma->State = HAL_DMA_STATE_READY; 8003b0e: 2301 movs r3, #1 8003b10: f880 3025 strb.w r3, [r0, #37] ; 0x25 if (hdma->XferCpltCallback != NULL) 8003b14: 6ac3 ldr r3, [r0, #44] ; 0x2c hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU)); 8003b16: 6072 str r2, [r6, #4] __HAL_UNLOCK(hdma); 8003b18: 2100 movs r1, #0 8003b1a: f880 1024 strb.w r1, [r0, #36] ; 0x24 if (hdma->XferCpltCallback != NULL) 8003b1e: 2b00 cmp r3, #0 8003b20: d1e5 bne.n 8003aee } 8003b22: bc70 pop {r4, r5, r6} 8003b24: 4770 bx lr else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))) 8003b26: 2208 movs r2, #8 8003b28: 409a lsls r2, r3 8003b2a: 420a tst r2, r1 8003b2c: d0f9 beq.n 8003b22 && (0U != (source_it & DMA_IT_TE))) 8003b2e: 0722 lsls r2, r4, #28 8003b30: d5f7 bpl.n 8003b22 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003b32: 682a ldr r2, [r5, #0] if (hdma->XferErrorCallback != NULL) 8003b34: 6b41 ldr r1, [r0, #52] ; 0x34 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8003b36: f022 020e bic.w r2, r2, #14 8003b3a: 602a str r2, [r5, #0] hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 8003b3c: 2201 movs r2, #1 8003b3e: fa02 f303 lsl.w r3, r2, r3 __HAL_UNLOCK(hdma); 8003b42: 2400 movs r4, #0 hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 8003b44: 6073 str r3, [r6, #4] hdma->ErrorCode = HAL_DMA_ERROR_TE; 8003b46: 63c2 str r2, [r0, #60] ; 0x3c __HAL_UNLOCK(hdma); 8003b48: f880 4024 strb.w r4, [r0, #36] ; 0x24 hdma->State = HAL_DMA_STATE_READY; 8003b4c: f880 2025 strb.w r2, [r0, #37] ; 0x25 if (hdma->XferErrorCallback != NULL) 8003b50: 2900 cmp r1, #0 8003b52: d0e6 beq.n 8003b22 } 8003b54: bc70 pop {r4, r5, r6} hdma->XferErrorCallback(hdma); 8003b56: 4708 bx r1 08003b58 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8003b58: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) 8003b5c: 680c ldr r4, [r1, #0] { 8003b5e: b085 sub sp, #20 while (((GPIO_Init->Pin) >> position) != 0U) 8003b60: 2c00 cmp r4, #0 8003b62: d07d beq.n 8003c60 8003b64: f04f 0c00 mov.w ip, #0 temp &= ~(0x0FUL << (4U * (position & 0x03U))); temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8003b68: 4e71 ldr r6, [pc, #452] ; (8003d30 ) uint32_t position = 0x00U; 8003b6a: 4663 mov r3, ip iocurrent = (GPIO_Init->Pin) & (1UL << position); 8003b6c: f04f 0b01 mov.w fp, #1 temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8003b70: 468e mov lr, r1 iocurrent = (GPIO_Init->Pin) & (1UL << position); 8003b72: fa0b f703 lsl.w r7, fp, r3 if (iocurrent != 0x00u) 8003b76: ea17 0a04 ands.w sl, r7, r4 8003b7a: d06b beq.n 8003c54 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8003b7c: f8de 1004 ldr.w r1, [lr, #4] 8003b80: f001 0203 and.w r2, r1, #3 8003b84: 1e55 subs r5, r2, #1 8003b86: 2d01 cmp r5, #1 8003b88: d96d bls.n 8003c66 if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8003b8a: 2a03 cmp r2, #3 8003b8c: f040 80b1 bne.w 8003cf2 temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8003b90: fa02 f20c lsl.w r2, r2, ip 8003b94: 43d5 mvns r5, r2 temp = GPIOx->MODER; 8003b96: 6807 ldr r7, [r0, #0] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8003b98: 403d ands r5, r7 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8003b9a: 432a orrs r2, r5 if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8003b9c: f411 3f40 tst.w r1, #196608 ; 0x30000 GPIOx->MODER = temp; 8003ba0: 6002 str r2, [r0, #0] if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8003ba2: d057 beq.n 8003c54 __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003ba4: 4d63 ldr r5, [pc, #396] ; (8003d34 ) 8003ba6: 6e2a ldr r2, [r5, #96] ; 0x60 8003ba8: f042 0201 orr.w r2, r2, #1 8003bac: 662a str r2, [r5, #96] ; 0x60 8003bae: 6e2a ldr r2, [r5, #96] ; 0x60 8003bb0: f002 0201 and.w r2, r2, #1 8003bb4: 9203 str r2, [sp, #12] 8003bb6: 9a03 ldr r2, [sp, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8003bb8: f023 0203 bic.w r2, r3, #3 8003bbc: f102 4280 add.w r2, r2, #1073741824 ; 0x40000000 8003bc0: f502 3280 add.w r2, r2, #65536 ; 0x10000 temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8003bc4: f003 0703 and.w r7, r3, #3 temp = SYSCFG->EXTICR[position >> 2U]; 8003bc8: 6895 ldr r5, [r2, #8] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8003bca: 00bf lsls r7, r7, #2 8003bcc: f04f 080f mov.w r8, #15 8003bd0: fa08 f807 lsl.w r8, r8, r7 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8003bd4: f1b0 4f90 cmp.w r0, #1207959552 ; 0x48000000 temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8003bd8: ea25 0908 bic.w r9, r5, r8 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8003bdc: d01a beq.n 8003c14 8003bde: 4d56 ldr r5, [pc, #344] ; (8003d38 ) 8003be0: 42a8 cmp r0, r5 8003be2: f000 8092 beq.w 8003d0a 8003be6: 4d55 ldr r5, [pc, #340] ; (8003d3c ) 8003be8: 42a8 cmp r0, r5 8003bea: f000 8093 beq.w 8003d14 8003bee: 4d54 ldr r5, [pc, #336] ; (8003d40 ) 8003bf0: 42a8 cmp r0, r5 8003bf2: f000 8083 beq.w 8003cfc 8003bf6: 4d53 ldr r5, [pc, #332] ; (8003d44 ) 8003bf8: 42a8 cmp r0, r5 8003bfa: f000 8092 beq.w 8003d22 8003bfe: 4d52 ldr r5, [pc, #328] ; (8003d48 ) 8003c00: 42a8 cmp r0, r5 8003c02: bf0c ite eq 8003c04: f04f 0805 moveq.w r8, #5 8003c08: f04f 0806 movne.w r8, #6 8003c0c: fa08 f707 lsl.w r7, r8, r7 8003c10: ea49 0907 orr.w r9, r9, r7 SYSCFG->EXTICR[position >> 2U] = temp; 8003c14: f8c2 9008 str.w r9, [r2, #8] temp = EXTI->RTSR1; 8003c18: 68b2 ldr r2, [r6, #8] temp &= ~(iocurrent); 8003c1a: ea6f 050a mvn.w r5, sl if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8003c1e: 02cf lsls r7, r1, #11 temp &= ~(iocurrent); 8003c20: bf54 ite pl 8003c22: 402a andpl r2, r5 { temp |= iocurrent; 8003c24: ea4a 0202 orrmi.w r2, sl, r2 } EXTI->RTSR1 = temp; 8003c28: 60b2 str r2, [r6, #8] temp = EXTI->FTSR1; 8003c2a: 68f2 ldr r2, [r6, #12] temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8003c2c: 028f lsls r7, r1, #10 temp &= ~(iocurrent); 8003c2e: bf54 ite pl 8003c30: 402a andpl r2, r5 { temp |= iocurrent; 8003c32: ea4a 0202 orrmi.w r2, sl, r2 } EXTI->FTSR1 = temp; 8003c36: 60f2 str r2, [r6, #12] temp = EXTI->EMR1; 8003c38: 6872 ldr r2, [r6, #4] temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8003c3a: 038f lsls r7, r1, #14 temp &= ~(iocurrent); 8003c3c: bf54 ite pl 8003c3e: 402a andpl r2, r5 { temp |= iocurrent; 8003c40: ea4a 0202 orrmi.w r2, sl, r2 } EXTI->EMR1 = temp; 8003c44: 6072 str r2, [r6, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 8003c46: 6832 ldr r2, [r6, #0] temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8003c48: 03c9 lsls r1, r1, #15 temp &= ~(iocurrent); 8003c4a: bf54 ite pl 8003c4c: 402a andpl r2, r5 { temp |= iocurrent; 8003c4e: ea4a 0202 orrmi.w r2, sl, r2 } EXTI->IMR1 = temp; 8003c52: 6032 str r2, [r6, #0] } } position++; 8003c54: 3301 adds r3, #1 while (((GPIO_Init->Pin) >> position) != 0U) 8003c56: fa34 f203 lsrs.w r2, r4, r3 8003c5a: f10c 0c02 add.w ip, ip, #2 8003c5e: d188 bne.n 8003b72 } } 8003c60: b005 add sp, #20 8003c62: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} temp = GPIOx->OSPEEDR; 8003c66: f8d0 9008 ldr.w r9, [r0, #8] temp |= (GPIO_Init->Speed << (position * 2U)); 8003c6a: f8de 500c ldr.w r5, [lr, #12] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8003c6e: f04f 0803 mov.w r8, #3 8003c72: fa08 f80c lsl.w r8, r8, ip 8003c76: ea29 0908 bic.w r9, r9, r8 temp |= (GPIO_Init->Speed << (position * 2U)); 8003c7a: fa05 f50c lsl.w r5, r5, ip 8003c7e: ea45 0509 orr.w r5, r5, r9 GPIOx->OSPEEDR = temp; 8003c82: 6085 str r5, [r0, #8] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8003c84: ea6f 0508 mvn.w r5, r8 temp = GPIOx->OTYPER; 8003c88: f8d0 8004 ldr.w r8, [r0, #4] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8003c8c: ea28 0807 bic.w r8, r8, r7 temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8003c90: f3c1 1700 ubfx r7, r1, #4, #1 8003c94: 409f lsls r7, r3 8003c96: ea47 0708 orr.w r7, r7, r8 GPIOx->OTYPER = temp; 8003c9a: 6047 str r7, [r0, #4] temp = GPIOx->PUPDR; 8003c9c: 68c7 ldr r7, [r0, #12] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8003c9e: ea07 0805 and.w r8, r7, r5 temp |= ((GPIO_Init->Pull) << (position * 2U)); 8003ca2: f8de 7008 ldr.w r7, [lr, #8] 8003ca6: fa07 f70c lsl.w r7, r7, ip 8003caa: ea47 0708 orr.w r7, r7, r8 if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8003cae: 2a02 cmp r2, #2 GPIOx->PUPDR = temp; 8003cb0: 60c7 str r7, [r0, #12] if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8003cb2: fa02 f20c lsl.w r2, r2, ip 8003cb6: f47f af6e bne.w 8003b96 temp = GPIOx->AFR[position >> 3U]; 8003cba: ea4f 09d3 mov.w r9, r3, lsr #3 8003cbe: eb00 0989 add.w r9, r0, r9, lsl #2 temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8003cc2: f003 0807 and.w r8, r3, #7 temp = GPIOx->AFR[position >> 3U]; 8003cc6: f8d9 7020 ldr.w r7, [r9, #32] 8003cca: 9700 str r7, [sp, #0] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8003ccc: f8de 7010 ldr.w r7, [lr, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8003cd0: ea4f 0888 mov.w r8, r8, lsl #2 temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8003cd4: fa07 f708 lsl.w r7, r7, r8 8003cd8: 9701 str r7, [sp, #4] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8003cda: 270f movs r7, #15 8003cdc: fa07 f808 lsl.w r8, r7, r8 8003ce0: 9f00 ldr r7, [sp, #0] 8003ce2: ea27 0808 bic.w r8, r7, r8 temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8003ce6: 9f01 ldr r7, [sp, #4] 8003ce8: ea47 0708 orr.w r7, r7, r8 GPIOx->AFR[position >> 3U] = temp; 8003cec: f8c9 7020 str.w r7, [r9, #32] 8003cf0: e751 b.n 8003b96 temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8003cf2: 2503 movs r5, #3 8003cf4: fa05 f50c lsl.w r5, r5, ip 8003cf8: 43ed mvns r5, r5 8003cfa: e7cf b.n 8003c9c temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8003cfc: f04f 0803 mov.w r8, #3 8003d00: fa08 f707 lsl.w r7, r8, r7 8003d04: ea49 0907 orr.w r9, r9, r7 8003d08: e784 b.n 8003c14 8003d0a: fa0b f707 lsl.w r7, fp, r7 8003d0e: ea49 0907 orr.w r9, r9, r7 8003d12: e77f b.n 8003c14 8003d14: f04f 0802 mov.w r8, #2 8003d18: fa08 f707 lsl.w r7, r8, r7 8003d1c: ea49 0907 orr.w r9, r9, r7 8003d20: e778 b.n 8003c14 8003d22: f04f 0804 mov.w r8, #4 8003d26: fa08 f707 lsl.w r7, r8, r7 8003d2a: ea49 0907 orr.w r9, r9, r7 8003d2e: e771 b.n 8003c14 8003d30: 40010400 .word 0x40010400 8003d34: 40021000 .word 0x40021000 8003d38: 48000400 .word 0x48000400 8003d3c: 48000800 .word 0x48000800 8003d40: 48000c00 .word 0x48000c00 8003d44: 48001000 .word 0x48001000 8003d48: 48001400 .word 0x48001400 08003d4c : { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8003d4c: b10a cbz r2, 8003d52 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8003d4e: 6181 str r1, [r0, #24] 8003d50: 4770 bx lr } else { GPIOx->BRR = (uint32_t)GPIO_Pin; 8003d52: 6281 str r1, [r0, #40] ; 0x28 } } 8003d54: 4770 bx lr 8003d56: bf00 nop 08003d58 : assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8003d58: 4a37 ldr r2, [pc, #220] ; (8003e38 ) if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) 8003d5a: b960 cbnz r0, 8003d76 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8003d5c: 6813 ldr r3, [r2, #0] 8003d5e: f403 63c0 and.w r3, r3, #1536 ; 0x600 8003d62: f5b3 6f80 cmp.w r3, #1024 ; 0x400 { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003d66: f8d2 3080 ldr.w r3, [r2, #128] ; 0x80 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8003d6a: d01d beq.n 8003da8 } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003d6c: f423 7380 bic.w r3, r3, #256 ; 0x100 8003d70: f8c2 3080 str.w r3, [r2, #128] ; 0x80 8003d74: 4770 bx lr } } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 8003d76: f5b0 7f00 cmp.w r0, #512 ; 0x200 8003d7a: d007 beq.n 8003d8c } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 8003d7c: 6813 ldr r3, [r2, #0] 8003d7e: f423 63c0 bic.w r3, r3, #1536 ; 0x600 8003d82: f443 6380 orr.w r3, r3, #1024 ; 0x400 /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; 8003d86: 2000 movs r0, #0 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 8003d88: 6013 str r3, [r2, #0] } 8003d8a: 4770 bx lr if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8003d8c: 6813 ldr r3, [r2, #0] 8003d8e: f403 63c0 and.w r3, r3, #1536 ; 0x600 8003d92: f5b3 6f80 cmp.w r3, #1024 ; 0x400 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003d96: f8d2 3080 ldr.w r3, [r2, #128] ; 0x80 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8003d9a: d02b beq.n 8003df4 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003d9c: f443 7380 orr.w r3, r3, #256 ; 0x100 return HAL_OK; 8003da0: 2000 movs r0, #0 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003da2: f8c2 3080 str.w r3, [r2, #128] ; 0x80 8003da6: 4770 bx lr CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003da8: f423 7380 bic.w r3, r3, #256 ; 0x100 8003dac: f8c2 3080 str.w r3, [r2, #128] ; 0x80 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8003db0: 6813 ldr r3, [r2, #0] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003db2: 4822 ldr r0, [pc, #136] ; (8003e3c ) 8003db4: 4922 ldr r1, [pc, #136] ; (8003e40 ) MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8003db6: f423 63c0 bic.w r3, r3, #1536 ; 0x600 8003dba: f443 7300 orr.w r3, r3, #512 ; 0x200 8003dbe: 6013 str r3, [r2, #0] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003dc0: 6803 ldr r3, [r0, #0] 8003dc2: 2032 movs r0, #50 ; 0x32 8003dc4: fb00 f303 mul.w r3, r0, r3 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003dc8: 6950 ldr r0, [r2, #20] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003dca: fba1 1303 umull r1, r3, r1, r3 8003dce: 0c9b lsrs r3, r3, #18 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003dd0: 0540 lsls r0, r0, #21 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003dd2: f103 0301 add.w r3, r3, #1 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003dd6: d506 bpl.n 8003de6 8003dd8: e000 b.n 8003ddc 8003dda: b123 cbz r3, 8003de6 8003ddc: 6951 ldr r1, [r2, #20] 8003dde: 0549 lsls r1, r1, #21 wait_loop_index--; 8003de0: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003de4: d4f9 bmi.n 8003dda if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8003de6: 4b14 ldr r3, [pc, #80] ; (8003e38 ) 8003de8: 695b ldr r3, [r3, #20] 8003dea: 055b lsls r3, r3, #21 return HAL_OK; 8003dec: bf54 ite pl 8003dee: 2000 movpl r0, #0 return HAL_TIMEOUT; 8003df0: 2003 movmi r0, #3 8003df2: 4770 bx lr SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003df4: f443 7380 orr.w r3, r3, #256 ; 0x100 8003df8: f8c2 3080 str.w r3, [r2, #128] ; 0x80 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8003dfc: 6813 ldr r3, [r2, #0] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003dfe: 480f ldr r0, [pc, #60] ; (8003e3c ) 8003e00: 490f ldr r1, [pc, #60] ; (8003e40 ) MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8003e02: f423 63c0 bic.w r3, r3, #1536 ; 0x600 8003e06: f443 7300 orr.w r3, r3, #512 ; 0x200 8003e0a: 6013 str r3, [r2, #0] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003e0c: 6803 ldr r3, [r0, #0] 8003e0e: 2032 movs r0, #50 ; 0x32 8003e10: fb00 f303 mul.w r3, r0, r3 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003e14: 6950 ldr r0, [r2, #20] wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003e16: fba1 1303 umull r1, r3, r1, r3 8003e1a: 0c9b lsrs r3, r3, #18 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003e1c: 0540 lsls r0, r0, #21 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003e1e: f103 0301 add.w r3, r3, #1 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003e22: d5e0 bpl.n 8003de6 8003e24: e001 b.n 8003e2a 8003e26: 2b00 cmp r3, #0 8003e28: d0dd beq.n 8003de6 8003e2a: 6951 ldr r1, [r2, #20] 8003e2c: 0549 lsls r1, r1, #21 wait_loop_index--; 8003e2e: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003e32: d5d8 bpl.n 8003de6 8003e34: e7f7 b.n 8003e26 8003e36: bf00 nop 8003e38: 40007000 .word 0x40007000 8003e3c: 20000000 .word 0x20000000 8003e40: 431bde83 .word 0x431bde83 08003e44 : * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); 8003e44: 4a02 ldr r2, [pc, #8] ; (8003e50 ) 8003e46: 6893 ldr r3, [r2, #8] 8003e48: f443 4380 orr.w r3, r3, #16384 ; 0x4000 8003e4c: 6093 str r3, [r2, #8] } 8003e4e: 4770 bx lr 8003e50: 40007000 .word 0x40007000 08003e54 : uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003e54: 2800 cmp r0, #0 8003e56: f000 81c3 beq.w 80041e0 { 8003e5a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8003e5e: 6803 ldr r3, [r0, #0] 8003e60: 07d9 lsls r1, r3, #31 { 8003e62: b082 sub sp, #8 8003e64: 4604 mov r4, r0 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8003e66: d52d bpl.n 8003ec4 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003e68: 49a6 ldr r1, [pc, #664] ; (8004104 ) 8003e6a: 688a ldr r2, [r1, #8] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8003e6c: 68c9 ldr r1, [r1, #12] temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003e6e: f002 020c and.w r2, r2, #12 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) 8003e72: 2a0c cmp r2, #12 8003e74: f000 810a beq.w 800408c 8003e78: 2a08 cmp r2, #8 8003e7a: f000 810c beq.w 8004096 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8003e7e: 6863 ldr r3, [r4, #4] 8003e80: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8003e84: f000 8133 beq.w 80040ee 8003e88: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003e8c: f000 819b beq.w 80041c6 8003e90: 4d9c ldr r5, [pc, #624] ; (8004104 ) 8003e92: 682a ldr r2, [r5, #0] 8003e94: f422 3280 bic.w r2, r2, #65536 ; 0x10000 8003e98: 602a str r2, [r5, #0] 8003e9a: 682a ldr r2, [r5, #0] 8003e9c: f422 2280 bic.w r2, r2, #262144 ; 0x40000 8003ea0: 602a str r2, [r5, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003ea2: 2b00 cmp r3, #0 8003ea4: f040 8128 bne.w 80040f8 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ea8: f7fe fe60 bl 8002b6c 8003eac: 4606 mov r6, r0 /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8003eae: e005 b.n 8003ebc { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003eb0: f7fe fe5c bl 8002b6c 8003eb4: 1b80 subs r0, r0, r6 8003eb6: 2864 cmp r0, #100 ; 0x64 8003eb8: f200 8142 bhi.w 8004140 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8003ebc: 682b ldr r3, [r5, #0] 8003ebe: 039f lsls r7, r3, #14 8003ec0: d4f6 bmi.n 8003eb0 } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003ec2: 6823 ldr r3, [r4, #0] 8003ec4: 079e lsls r6, r3, #30 8003ec6: d528 bpl.n 8003f1a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003ec8: 4a8e ldr r2, [pc, #568] ; (8004104 ) 8003eca: 6893 ldr r3, [r2, #8] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8003ecc: 68d2 ldr r2, [r2, #12] temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003ece: f003 030c and.w r3, r3, #12 if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) 8003ed2: 2b0c cmp r3, #12 8003ed4: f000 80ec beq.w 80040b0 8003ed8: 2b04 cmp r3, #4 8003eda: f000 80ee beq.w 80040ba } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8003ede: 68e3 ldr r3, [r4, #12] { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8003ee0: 4d88 ldr r5, [pc, #544] ; (8004104 ) if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8003ee2: 2b00 cmp r3, #0 8003ee4: f000 811d beq.w 8004122 __HAL_RCC_HSI_ENABLE(); 8003ee8: 682b ldr r3, [r5, #0] 8003eea: f443 7380 orr.w r3, r3, #256 ; 0x100 8003eee: 602b str r3, [r5, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ef0: f7fe fe3c bl 8002b6c 8003ef4: 4606 mov r6, r0 /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003ef6: e005 b.n 8003f04 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003ef8: f7fe fe38 bl 8002b6c 8003efc: 1b80 subs r0, r0, r6 8003efe: 2802 cmp r0, #2 8003f00: f200 811e bhi.w 8004140 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003f04: 682b ldr r3, [r5, #0] 8003f06: 0558 lsls r0, r3, #21 8003f08: d5f6 bpl.n 8003ef8 return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003f0a: 686b ldr r3, [r5, #4] 8003f0c: 6922 ldr r2, [r4, #16] 8003f0e: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 8003f12: ea43 6302 orr.w r3, r3, r2, lsl #24 8003f16: 606b str r3, [r5, #4] } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003f18: 6823 ldr r3, [r4, #0] 8003f1a: 071a lsls r2, r3, #28 8003f1c: d519 bpl.n 8003f52 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8003f1e: 6963 ldr r3, [r4, #20] { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003f20: 4d78 ldr r5, [pc, #480] ; (8004104 ) if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8003f22: 2b00 cmp r3, #0 8003f24: f000 809e beq.w 8004064 __HAL_RCC_LSI_ENABLE(); 8003f28: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8003f2c: f043 0301 orr.w r3, r3, #1 8003f30: f8c5 3094 str.w r3, [r5, #148] ; 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003f34: f7fe fe1a bl 8002b6c 8003f38: 4606 mov r6, r0 /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003f3a: e005 b.n 8003f48 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8003f3c: f7fe fe16 bl 8002b6c 8003f40: 1b80 subs r0, r0, r6 8003f42: 2802 cmp r0, #2 8003f44: f200 80fc bhi.w 8004140 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003f48: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8003f4c: 079f lsls r7, r3, #30 8003f4e: d5f5 bpl.n 8003f3c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8003f50: 6823 ldr r3, [r4, #0] 8003f52: 0759 lsls r1, r3, #29 8003f54: d541 bpl.n 8003fda /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8003f56: 4b6b ldr r3, [pc, #428] ; (8004104 ) 8003f58: 6d9a ldr r2, [r3, #88] ; 0x58 8003f5a: 00d2 lsls r2, r2, #3 8003f5c: f100 80f4 bmi.w 8004148 { __HAL_RCC_PWR_CLK_ENABLE(); 8003f60: 6d9a ldr r2, [r3, #88] ; 0x58 8003f62: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 8003f66: 659a str r2, [r3, #88] ; 0x58 8003f68: 6d9b ldr r3, [r3, #88] ; 0x58 8003f6a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8003f6e: 9301 str r3, [sp, #4] 8003f70: 9b01 ldr r3, [sp, #4] pwrclkchanged = SET; 8003f72: 2501 movs r5, #1 } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003f74: 4e64 ldr r6, [pc, #400] ; (8004108 ) 8003f76: 6833 ldr r3, [r6, #0] 8003f78: 05df lsls r7, r3, #23 8003f7a: f140 8113 bpl.w 80041a4 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003f7e: 68a3 ldr r3, [r4, #8] 8003f80: 2b01 cmp r3, #1 8003f82: f000 80e3 beq.w 800414c 8003f86: 2b05 cmp r3, #5 8003f88: f000 8169 beq.w 800425e 8003f8c: 4e5d ldr r6, [pc, #372] ; (8004104 ) 8003f8e: f8d6 2090 ldr.w r2, [r6, #144] ; 0x90 8003f92: f022 0201 bic.w r2, r2, #1 8003f96: f8c6 2090 str.w r2, [r6, #144] ; 0x90 8003f9a: f8d6 2090 ldr.w r2, [r6, #144] ; 0x90 8003f9e: f022 0204 bic.w r2, r2, #4 8003fa2: f8c6 2090 str.w r2, [r6, #144] ; 0x90 /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8003fa6: 2b00 cmp r3, #0 8003fa8: f040 80d7 bne.w 800415a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003fac: f7fe fdde bl 8002b6c /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003fb0: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 8003fb4: 4607 mov r7, r0 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003fb6: e005 b.n 8003fc4 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003fb8: f7fe fdd8 bl 8002b6c 8003fbc: 1bc0 subs r0, r0, r7 8003fbe: 4540 cmp r0, r8 8003fc0: f200 80be bhi.w 8004140 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003fc4: f8d6 3090 ldr.w r3, [r6, #144] ; 0x90 8003fc8: 079a lsls r2, r3, #30 8003fca: d4f5 bmi.n 8003fb8 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8003fcc: b125 cbz r5, 8003fd8 { __HAL_RCC_PWR_CLK_DISABLE(); 8003fce: 4a4d ldr r2, [pc, #308] ; (8004104 ) 8003fd0: 6d93 ldr r3, [r2, #88] ; 0x58 8003fd2: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003fd6: 6593 str r3, [r2, #88] ; 0x58 } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8003fd8: 6823 ldr r3, [r4, #0] 8003fda: 069b lsls r3, r3, #26 8003fdc: d518 bpl.n 8004010 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8003fde: 69a3 ldr r3, [r4, #24] { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8003fe0: 4d48 ldr r5, [pc, #288] ; (8004104 ) if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8003fe2: 2b00 cmp r3, #0 8003fe4: f000 80ca beq.w 800417c __HAL_RCC_HSI48_ENABLE(); 8003fe8: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 8003fec: f043 0301 orr.w r3, r3, #1 8003ff0: f8c5 3098 str.w r3, [r5, #152] ; 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ff4: f7fe fdba bl 8002b6c 8003ff8: 4606 mov r6, r0 /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 8003ffa: e005 b.n 8004008 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8003ffc: f7fe fdb6 bl 8002b6c 8004000: 1b80 subs r0, r0, r6 8004002: 2802 cmp r0, #2 8004004: f200 809c bhi.w 8004140 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 8004008: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 800400c: 079f lsls r7, r3, #30 800400e: d5f5 bpl.n 8003ffc /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8004010: 69e0 ldr r0, [r4, #28] 8004012: b318 cbz r0, 800405c { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8004014: 4d3b ldr r5, [pc, #236] ; (8004104 ) 8004016: 68ab ldr r3, [r5, #8] 8004018: f003 030c and.w r3, r3, #12 800401c: 2b0c cmp r3, #12 800401e: f000 812c beq.w 800427a assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8004022: 682b ldr r3, [r5, #0] if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8004024: 2802 cmp r0, #2 __HAL_RCC_PLL_DISABLE(); 8004026: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 800402a: 602b str r3, [r5, #0] if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 800402c: f000 80da beq.w 80041e4 { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Disable all PLL outputs to save power if no PLLs on */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); 8004030: 68eb ldr r3, [r5, #12] 8004032: f023 0303 bic.w r3, r3, #3 8004036: 60eb str r3, [r5, #12] __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); 8004038: 68eb ldr r3, [r5, #12] 800403a: f023 7388 bic.w r3, r3, #17825792 ; 0x1100000 800403e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8004042: 60eb str r3, [r5, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004044: f7fe fd92 bl 8002b6c 8004048: 4604 mov r4, r0 /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800404a: e004 b.n 8004056 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800404c: f7fe fd8e bl 8002b6c 8004050: 1b00 subs r0, r0, r4 8004052: 2802 cmp r0, #2 8004054: d874 bhi.n 8004140 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8004056: 682b ldr r3, [r5, #0] 8004058: 019b lsls r3, r3, #6 800405a: d4f7 bmi.n 800404c } } } } return HAL_OK; 800405c: 2000 movs r0, #0 } 800405e: b002 add sp, #8 8004060: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_RCC_LSI_DISABLE(); 8004064: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8004068: f023 0301 bic.w r3, r3, #1 800406c: f8c5 3094 str.w r3, [r5, #148] ; 0x94 tickstart = HAL_GetTick(); 8004070: f7fe fd7c bl 8002b6c 8004074: 4606 mov r6, r0 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8004076: e004 b.n 8004082 if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004078: f7fe fd78 bl 8002b6c 800407c: 1b80 subs r0, r0, r6 800407e: 2802 cmp r0, #2 8004080: d85e bhi.n 8004140 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8004082: f8d5 3094 ldr.w r3, [r5, #148] ; 0x94 8004086: 0798 lsls r0, r3, #30 8004088: d4f6 bmi.n 8004078 800408a: e761 b.n 8003f50 temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 800408c: f001 0103 and.w r1, r1, #3 if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) 8004090: 2903 cmp r1, #3 8004092: f47f aef4 bne.w 8003e7e if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004096: 4a1b ldr r2, [pc, #108] ; (8004104 ) 8004098: 6812 ldr r2, [r2, #0] 800409a: 0392 lsls r2, r2, #14 800409c: f57f af12 bpl.w 8003ec4 80040a0: 6862 ldr r2, [r4, #4] 80040a2: 2a00 cmp r2, #0 80040a4: f47f af0e bne.w 8003ec4 return HAL_ERROR; 80040a8: 2001 movs r0, #1 } 80040aa: b002 add sp, #8 80040ac: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 80040b0: f002 0203 and.w r2, r2, #3 if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) 80040b4: 2a02 cmp r2, #2 80040b6: f47f af12 bne.w 8003ede if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80040ba: 4b12 ldr r3, [pc, #72] ; (8004104 ) 80040bc: 681b ldr r3, [r3, #0] 80040be: 055d lsls r5, r3, #21 80040c0: d502 bpl.n 80040c8 80040c2: 68e3 ldr r3, [r4, #12] 80040c4: 2b00 cmp r3, #0 80040c6: d0ef beq.n 80040a8 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80040c8: 4a0e ldr r2, [pc, #56] ; (8004104 ) 80040ca: 6920 ldr r0, [r4, #16] 80040cc: 6853 ldr r3, [r2, #4] if (HAL_InitTick(uwTickPrio) != HAL_OK) 80040ce: 490f ldr r1, [pc, #60] ; (800410c ) __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80040d0: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 80040d4: ea43 6300 orr.w r3, r3, r0, lsl #24 80040d8: 6053 str r3, [r2, #4] if (HAL_InitTick(uwTickPrio) != HAL_OK) 80040da: 6808 ldr r0, [r1, #0] 80040dc: f7fe fd04 bl 8002ae8 80040e0: 2800 cmp r0, #0 80040e2: d1e1 bne.n 80040a8 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80040e4: 6823 ldr r3, [r4, #0] 80040e6: 071a lsls r2, r3, #28 80040e8: f57f af33 bpl.w 8003f52 80040ec: e717 b.n 8003f1e __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80040ee: 4a05 ldr r2, [pc, #20] ; (8004104 ) 80040f0: 6813 ldr r3, [r2, #0] 80040f2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80040f6: 6013 str r3, [r2, #0] tickstart = HAL_GetTick(); 80040f8: f7fe fd38 bl 8002b6c while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80040fc: 4e01 ldr r6, [pc, #4] ; (8004104 ) tickstart = HAL_GetTick(); 80040fe: 4605 mov r5, r0 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8004100: e00b b.n 800411a 8004102: bf00 nop 8004104: 40021000 .word 0x40021000 8004108: 40007000 .word 0x40007000 800410c: 20000008 .word 0x20000008 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004110: f7fe fd2c bl 8002b6c 8004114: 1b40 subs r0, r0, r5 8004116: 2864 cmp r0, #100 ; 0x64 8004118: d812 bhi.n 8004140 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 800411a: 6833 ldr r3, [r6, #0] 800411c: 039b lsls r3, r3, #14 800411e: d5f7 bpl.n 8004110 8004120: e6cf b.n 8003ec2 __HAL_RCC_HSI_DISABLE(); 8004122: 682b ldr r3, [r5, #0] 8004124: f423 7380 bic.w r3, r3, #256 ; 0x100 8004128: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 800412a: f7fe fd1f bl 8002b6c 800412e: 4606 mov r6, r0 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8004130: 682b ldr r3, [r5, #0] 8004132: 0559 lsls r1, r3, #21 8004134: d5d6 bpl.n 80040e4 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8004136: f7fe fd19 bl 8002b6c 800413a: 1b80 subs r0, r0, r6 800413c: 2802 cmp r0, #2 800413e: d9f7 bls.n 8004130 return HAL_TIMEOUT; 8004140: 2003 movs r0, #3 } 8004142: b002 add sp, #8 8004144: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} FlagStatus pwrclkchanged = RESET; 8004148: 2500 movs r5, #0 800414a: e713 b.n 8003f74 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800414c: 4a65 ldr r2, [pc, #404] ; (80042e4 ) 800414e: f8d2 3090 ldr.w r3, [r2, #144] ; 0x90 8004152: f043 0301 orr.w r3, r3, #1 8004156: f8c2 3090 str.w r3, [r2, #144] ; 0x90 tickstart = HAL_GetTick(); 800415a: f7fe fd07 bl 8002b6c while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800415e: 4f61 ldr r7, [pc, #388] ; (80042e4 ) tickstart = HAL_GetTick(); 8004160: 4606 mov r6, r0 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004162: f241 3888 movw r8, #5000 ; 0x1388 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8004166: e004 b.n 8004172 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004168: f7fe fd00 bl 8002b6c 800416c: 1b80 subs r0, r0, r6 800416e: 4540 cmp r0, r8 8004170: d8e6 bhi.n 8004140 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8004172: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 8004176: 0799 lsls r1, r3, #30 8004178: d5f6 bpl.n 8004168 800417a: e727 b.n 8003fcc __HAL_RCC_HSI48_DISABLE(); 800417c: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 8004180: f023 0301 bic.w r3, r3, #1 8004184: f8c5 3098 str.w r3, [r5, #152] ; 0x98 tickstart = HAL_GetTick(); 8004188: f7fe fcf0 bl 8002b6c 800418c: 4606 mov r6, r0 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 800418e: e004 b.n 800419a if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8004190: f7fe fcec bl 8002b6c 8004194: 1b80 subs r0, r0, r6 8004196: 2802 cmp r0, #2 8004198: d8d2 bhi.n 8004140 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 800419a: f8d5 3098 ldr.w r3, [r5, #152] ; 0x98 800419e: 0798 lsls r0, r3, #30 80041a0: d4f6 bmi.n 8004190 80041a2: e735 b.n 8004010 SET_BIT(PWR->CR1, PWR_CR1_DBP); 80041a4: 6833 ldr r3, [r6, #0] 80041a6: f443 7380 orr.w r3, r3, #256 ; 0x100 80041aa: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 80041ac: f7fe fcde bl 8002b6c 80041b0: 4607 mov r7, r0 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80041b2: 6833 ldr r3, [r6, #0] 80041b4: 05d8 lsls r0, r3, #23 80041b6: f53f aee2 bmi.w 8003f7e if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80041ba: f7fe fcd7 bl 8002b6c 80041be: 1bc0 subs r0, r0, r7 80041c0: 2802 cmp r0, #2 80041c2: d9f6 bls.n 80041b2 80041c4: e7bc b.n 8004140 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80041c6: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 80041ca: f5a3 333c sub.w r3, r3, #192512 ; 0x2f000 80041ce: 681a ldr r2, [r3, #0] 80041d0: f442 2280 orr.w r2, r2, #262144 ; 0x40000 80041d4: 601a str r2, [r3, #0] 80041d6: 681a ldr r2, [r3, #0] 80041d8: f442 3280 orr.w r2, r2, #65536 ; 0x10000 80041dc: 601a str r2, [r3, #0] if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 80041de: e78b b.n 80040f8 return HAL_ERROR; 80041e0: 2001 movs r0, #1 } 80041e2: 4770 bx lr tickstart = HAL_GetTick(); 80041e4: f7fe fcc2 bl 8002b6c 80041e8: 4606 mov r6, r0 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80041ea: e004 b.n 80041f6 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80041ec: f7fe fcbe bl 8002b6c 80041f0: 1b80 subs r0, r0, r6 80041f2: 2802 cmp r0, #2 80041f4: d8a4 bhi.n 8004140 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80041f6: 682b ldr r3, [r5, #0] 80041f8: 0199 lsls r1, r3, #6 80041fa: d4f7 bmi.n 80041ec __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80041fc: 68e9 ldr r1, [r5, #12] 80041fe: 4b3a ldr r3, [pc, #232] ; (80042e8 ) 8004200: 6a22 ldr r2, [r4, #32] 8004202: 6a60 ldr r0, [r4, #36] ; 0x24 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8004204: 4e37 ldr r6, [pc, #220] ; (80042e4 ) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8004206: 400b ands r3, r1 8004208: 4313 orrs r3, r2 800420a: e9d4 120a ldrd r1, r2, [r4, #40] ; 0x28 800420e: ea43 2301 orr.w r3, r3, r1, lsl #8 8004212: ea43 63c2 orr.w r3, r3, r2, lsl #27 8004216: e9d4 120c ldrd r1, r2, [r4, #48] ; 0x30 800421a: 3801 subs r0, #1 800421c: 0849 lsrs r1, r1, #1 800421e: ea43 1300 orr.w r3, r3, r0, lsl #4 8004222: 3901 subs r1, #1 8004224: 0852 lsrs r2, r2, #1 8004226: ea43 5341 orr.w r3, r3, r1, lsl #21 800422a: 3a01 subs r2, #1 800422c: ea43 6342 orr.w r3, r3, r2, lsl #25 8004230: 60eb str r3, [r5, #12] __HAL_RCC_PLL_ENABLE(); 8004232: 682b ldr r3, [r5, #0] 8004234: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8004238: 602b str r3, [r5, #0] __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 800423a: 68eb ldr r3, [r5, #12] 800423c: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8004240: 60eb str r3, [r5, #12] tickstart = HAL_GetTick(); 8004242: f7fe fc93 bl 8002b6c 8004246: 4604 mov r4, r0 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8004248: e005 b.n 8004256 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800424a: f7fe fc8f bl 8002b6c 800424e: 1b00 subs r0, r0, r4 8004250: 2802 cmp r0, #2 8004252: f63f af75 bhi.w 8004140 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8004256: 6833 ldr r3, [r6, #0] 8004258: 019a lsls r2, r3, #6 800425a: d5f6 bpl.n 800424a 800425c: e6fe b.n 800405c __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800425e: 4b21 ldr r3, [pc, #132] ; (80042e4 ) 8004260: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 8004264: f042 0204 orr.w r2, r2, #4 8004268: f8c3 2090 str.w r2, [r3, #144] ; 0x90 800426c: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 8004270: f042 0201 orr.w r2, r2, #1 8004274: f8c3 2090 str.w r2, [r3, #144] ; 0x90 if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8004278: e76f b.n 800415a if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 800427a: 2801 cmp r0, #1 800427c: f43f aeef beq.w 800405e temp_pllckcfg = RCC->PLLCFGR; 8004280: 68eb ldr r3, [r5, #12] if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004282: 6a22 ldr r2, [r4, #32] 8004284: f003 0103 and.w r1, r3, #3 8004288: 4291 cmp r1, r2 800428a: f47f af0d bne.w 80040a8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 800428e: 6a61 ldr r1, [r4, #36] ; 0x24 8004290: f003 02f0 and.w r2, r3, #240 ; 0xf0 8004294: 3901 subs r1, #1 if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004296: ebb2 1f01 cmp.w r2, r1, lsl #4 800429a: f47f af05 bne.w 80040a8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 800429e: 6aa1 ldr r1, [r4, #40] ; 0x28 80042a0: f403 42fe and.w r2, r3, #32512 ; 0x7f00 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 80042a4: ebb2 2f01 cmp.w r2, r1, lsl #8 80042a8: f47f aefe bne.w 80040a8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 80042ac: 6ae1 ldr r1, [r4, #44] ; 0x2c 80042ae: f003 4278 and.w r2, r3, #4160749568 ; 0xf8000000 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 80042b2: ebb2 6fc1 cmp.w r2, r1, lsl #27 80042b6: f47f aef7 bne.w 80040a8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 80042ba: 6b22 ldr r2, [r4, #48] ; 0x30 80042bc: 0852 lsrs r2, r2, #1 80042be: f403 01c0 and.w r1, r3, #6291456 ; 0x600000 80042c2: 3a01 subs r2, #1 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 80042c4: ebb1 5f42 cmp.w r1, r2, lsl #21 80042c8: f47f aeee bne.w 80040a8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 80042cc: 6b62 ldr r2, [r4, #52] ; 0x34 80042ce: 0852 lsrs r2, r2, #1 80042d0: f003 63c0 and.w r3, r3, #100663296 ; 0x6000000 80042d4: 3a01 subs r2, #1 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 80042d6: ebb3 6f42 cmp.w r3, r2, lsl #25 return HAL_ERROR; 80042da: bf14 ite ne 80042dc: 2001 movne r0, #1 80042de: 2000 moveq r0, #0 80042e0: e6bd b.n 800405e 80042e2: bf00 nop 80042e4: 40021000 .word 0x40021000 80042e8: 019f800c .word 0x019f800c 080042ec : uint32_t HAL_RCC_GetSysClockFreq(void) { uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 80042ec: 4b18 ldr r3, [pc, #96] ; (8004350 ) 80042ee: 689a ldr r2, [r3, #8] 80042f0: f002 020c and.w r2, r2, #12 80042f4: 2a04 cmp r2, #4 80042f6: d026 beq.n 8004346 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 80042f8: 689a ldr r2, [r3, #8] 80042fa: f002 020c and.w r2, r2, #12 80042fe: 2a08 cmp r2, #8 8004300: d023 beq.n 800434a { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) 8004302: 689a ldr r2, [r3, #8] 8004304: f002 020c and.w r2, r2, #12 8004308: 2a0c cmp r2, #12 800430a: d001 beq.n 8004310 pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; } else { sysclockfreq = 0U; 800430c: 2000 movs r0, #0 } return sysclockfreq; } 800430e: 4770 bx lr pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8004310: 68d9 ldr r1, [r3, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8004312: 68da ldr r2, [r3, #12] pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8004314: 68d8 ldr r0, [r3, #12] pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8004316: f001 0103 and.w r1, r1, #3 switch (pllsource) 800431a: 2903 cmp r1, #3 pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 800431c: f3c2 1203 ubfx r2, r2, #4, #4 pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8004320: f3c0 2006 ubfx r0, r0, #8, #7 pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8004324: bf0c ite eq 8004326: 4b0b ldreq r3, [pc, #44] ; (8004354 ) pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8004328: 4b0b ldrne r3, [pc, #44] ; (8004358 ) pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 800432a: 3201 adds r2, #1 pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 800432c: fbb3 f3f2 udiv r3, r3, r2 8004330: fb03 f000 mul.w r0, r3, r0 pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8004334: 4b06 ldr r3, [pc, #24] ; (8004350 ) 8004336: 68db ldr r3, [r3, #12] 8004338: f3c3 6341 ubfx r3, r3, #25, #2 800433c: 3301 adds r3, #1 800433e: 005b lsls r3, r3, #1 sysclockfreq = pllvco/pllr; 8004340: fbb0 f0f3 udiv r0, r0, r3 return sysclockfreq; 8004344: 4770 bx lr sysclockfreq = HSI_VALUE; 8004346: 4804 ldr r0, [pc, #16] ; (8004358 ) 8004348: 4770 bx lr sysclockfreq = HSE_VALUE; 800434a: 4802 ldr r0, [pc, #8] ; (8004354 ) 800434c: 4770 bx lr 800434e: bf00 nop 8004350: 40021000 .word 0x40021000 8004354: 007a1200 .word 0x007a1200 8004358: 00f42400 .word 0x00f42400 0800435c : if (RCC_ClkInitStruct == NULL) 800435c: 2800 cmp r0, #0 800435e: f000 80ee beq.w 800453e if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004362: 4a78 ldr r2, [pc, #480] ; (8004544 ) { 8004364: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004368: 6813 ldr r3, [r2, #0] 800436a: f003 030f and.w r3, r3, #15 800436e: 428b cmp r3, r1 8004370: 460d mov r5, r1 8004372: 4604 mov r4, r0 8004374: d20c bcs.n 8004390 __HAL_FLASH_SET_LATENCY(FLatency); 8004376: 6813 ldr r3, [r2, #0] 8004378: f023 030f bic.w r3, r3, #15 800437c: 430b orrs r3, r1 800437e: 6013 str r3, [r2, #0] if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004380: 6813 ldr r3, [r2, #0] 8004382: f003 030f and.w r3, r3, #15 8004386: 428b cmp r3, r1 8004388: d002 beq.n 8004390 return HAL_ERROR; 800438a: 2001 movs r0, #1 } 800438c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8004390: 6823 ldr r3, [r4, #0] 8004392: 07df lsls r7, r3, #31 8004394: d569 bpl.n 800446a if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8004396: 6867 ldr r7, [r4, #4] 8004398: 2f03 cmp r7, #3 800439a: f000 80a0 beq.w 80044de if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 800439e: 4b6a ldr r3, [pc, #424] ; (8004548 ) if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80043a0: 2f02 cmp r7, #2 if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80043a2: 681b ldr r3, [r3, #0] if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80043a4: f000 8097 beq.w 80044d6 if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 80043a8: 055b lsls r3, r3, #21 80043aa: d5ee bpl.n 800438a pllfreq = HAL_RCC_GetSysClockFreq(); 80043ac: f7ff ff9e bl 80042ec if(pllfreq > 80000000U) 80043b0: 4b66 ldr r3, [pc, #408] ; (800454c ) 80043b2: 4298 cmp r0, r3 80043b4: f240 80c0 bls.w 8004538 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 80043b8: 4a63 ldr r2, [pc, #396] ; (8004548 ) 80043ba: 6893 ldr r3, [r2, #8] 80043bc: f023 03f0 bic.w r3, r3, #240 ; 0xf0 80043c0: f043 0380 orr.w r3, r3, #128 ; 0x80 80043c4: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 80043c6: f04f 0980 mov.w r9, #128 ; 0x80 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 80043ca: 4e5f ldr r6, [pc, #380] ; (8004548 ) 80043cc: 68b3 ldr r3, [r6, #8] 80043ce: f023 0303 bic.w r3, r3, #3 80043d2: 433b orrs r3, r7 80043d4: 60b3 str r3, [r6, #8] tickstart = HAL_GetTick(); 80043d6: f7fe fbc9 bl 8002b6c if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80043da: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 80043de: 4607 mov r7, r0 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80043e0: e004 b.n 80043ec if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80043e2: f7fe fbc3 bl 8002b6c 80043e6: 1bc0 subs r0, r0, r7 80043e8: 4540 cmp r0, r8 80043ea: d871 bhi.n 80044d0 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80043ec: 68b3 ldr r3, [r6, #8] 80043ee: 6862 ldr r2, [r4, #4] 80043f0: f003 030c and.w r3, r3, #12 80043f4: ebb3 0f82 cmp.w r3, r2, lsl #2 80043f8: d1f3 bne.n 80043e2 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80043fa: 6823 ldr r3, [r4, #0] 80043fc: 079f lsls r7, r3, #30 80043fe: d436 bmi.n 800446e if(hpre == RCC_SYSCLK_DIV2) 8004400: f1b9 0f00 cmp.w r9, #0 8004404: d003 beq.n 800440e MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); 8004406: 68b3 ldr r3, [r6, #8] 8004408: f023 03f0 bic.w r3, r3, #240 ; 0xf0 800440c: 60b3 str r3, [r6, #8] if (FLatency < __HAL_FLASH_GET_LATENCY()) 800440e: 4e4d ldr r6, [pc, #308] ; (8004544 ) 8004410: 6833 ldr r3, [r6, #0] 8004412: f003 030f and.w r3, r3, #15 8004416: 42ab cmp r3, r5 8004418: d846 bhi.n 80044a8 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800441a: 6823 ldr r3, [r4, #0] 800441c: 075a lsls r2, r3, #29 800441e: d506 bpl.n 800442e MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004420: 4949 ldr r1, [pc, #292] ; (8004548 ) 8004422: 68e0 ldr r0, [r4, #12] 8004424: 688a ldr r2, [r1, #8] 8004426: f422 62e0 bic.w r2, r2, #1792 ; 0x700 800442a: 4302 orrs r2, r0 800442c: 608a str r2, [r1, #8] if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800442e: 071b lsls r3, r3, #28 8004430: d507 bpl.n 8004442 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004432: 4a45 ldr r2, [pc, #276] ; (8004548 ) 8004434: 6921 ldr r1, [r4, #16] 8004436: 6893 ldr r3, [r2, #8] 8004438: f423 5360 bic.w r3, r3, #14336 ; 0x3800 800443c: ea43 03c1 orr.w r3, r3, r1, lsl #3 8004440: 6093 str r3, [r2, #8] SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 8004442: f7ff ff53 bl 80042ec 8004446: 4a40 ldr r2, [pc, #256] ; (8004548 ) 8004448: 4c41 ldr r4, [pc, #260] ; (8004550 ) 800444a: 6892 ldr r2, [r2, #8] 800444c: 4941 ldr r1, [pc, #260] ; (8004554 ) 800444e: f3c2 1203 ubfx r2, r2, #4, #4 8004452: 4603 mov r3, r0 8004454: 5ca2 ldrb r2, [r4, r2] return HAL_InitTick(uwTickPrio); 8004456: 4840 ldr r0, [pc, #256] ; (8004558 ) SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 8004458: f002 021f and.w r2, r2, #31 800445c: 40d3 lsrs r3, r2 800445e: 600b str r3, [r1, #0] return HAL_InitTick(uwTickPrio); 8004460: 6800 ldr r0, [r0, #0] } 8004462: e8bd 43f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, lr} return HAL_InitTick(uwTickPrio); 8004466: f7fe bb3f b.w 8002ae8 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800446a: 079e lsls r6, r3, #30 800446c: d5cf bpl.n 800440e if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800446e: 0758 lsls r0, r3, #29 8004470: d504 bpl.n 800447c MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004472: 4935 ldr r1, [pc, #212] ; (8004548 ) 8004474: 688a ldr r2, [r1, #8] 8004476: f442 62e0 orr.w r2, r2, #1792 ; 0x700 800447a: 608a str r2, [r1, #8] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800447c: 0719 lsls r1, r3, #28 800447e: d506 bpl.n 800448e MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); 8004480: 4a31 ldr r2, [pc, #196] ; (8004548 ) 8004482: 6893 ldr r3, [r2, #8] 8004484: f423 537c bic.w r3, r3, #16128 ; 0x3f00 8004488: f443 63e0 orr.w r3, r3, #1792 ; 0x700 800448c: 6093 str r3, [r2, #8] MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800448e: 4a2e ldr r2, [pc, #184] ; (8004548 ) 8004490: 68a1 ldr r1, [r4, #8] 8004492: 6893 ldr r3, [r2, #8] if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004494: 4e2b ldr r6, [pc, #172] ; (8004544 ) MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004496: f023 03f0 bic.w r3, r3, #240 ; 0xf0 800449a: 430b orrs r3, r1 800449c: 6093 str r3, [r2, #8] if (FLatency < __HAL_FLASH_GET_LATENCY()) 800449e: 6833 ldr r3, [r6, #0] 80044a0: f003 030f and.w r3, r3, #15 80044a4: 42ab cmp r3, r5 80044a6: d9b8 bls.n 800441a __HAL_FLASH_SET_LATENCY(FLatency); 80044a8: 6833 ldr r3, [r6, #0] 80044aa: f023 030f bic.w r3, r3, #15 80044ae: 432b orrs r3, r5 80044b0: 6033 str r3, [r6, #0] tickstart = HAL_GetTick(); 80044b2: f7fe fb5b bl 8002b6c if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80044b6: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 80044ba: 4607 mov r7, r0 while (__HAL_FLASH_GET_LATENCY() != FLatency) 80044bc: 6833 ldr r3, [r6, #0] 80044be: f003 030f and.w r3, r3, #15 80044c2: 42ab cmp r3, r5 80044c4: d0a9 beq.n 800441a if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80044c6: f7fe fb51 bl 8002b6c 80044ca: 1bc0 subs r0, r0, r7 80044cc: 4540 cmp r0, r8 80044ce: d9f5 bls.n 80044bc return HAL_TIMEOUT; 80044d0: 2003 movs r0, #3 } 80044d2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80044d6: 039a lsls r2, r3, #14 80044d8: f53f af68 bmi.w 80043ac 80044dc: e755 b.n 800438a if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 80044de: 4a1a ldr r2, [pc, #104] ; (8004548 ) 80044e0: 6811 ldr r1, [r2, #0] 80044e2: 0188 lsls r0, r1, #6 80044e4: f57f af51 bpl.w 800438a uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 80044e8: 68d0 ldr r0, [r2, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80044ea: 68d1 ldr r1, [r2, #12] pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80044ec: 68d2 ldr r2, [r2, #12] if(pllfreq > 80000000U) 80044ee: 4e17 ldr r6, [pc, #92] ; (800454c ) pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 80044f0: f000 0003 and.w r0, r0, #3 switch (pllsource) 80044f4: 2803 cmp r0, #3 pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80044f6: f3c1 1103 ubfx r1, r1, #4, #4 pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80044fa: bf0c ite eq 80044fc: 4817 ldreq r0, [pc, #92] ; (800455c ) pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80044fe: 4818 ldrne r0, [pc, #96] ; (8004560 ) pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8004500: 3101 adds r1, #1 pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8004502: fbb0 f1f1 udiv r1, r0, r1 break; } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8004506: 4810 ldr r0, [pc, #64] ; (8004548 ) pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8004508: f3c2 2206 ubfx r2, r2, #8, #7 800450c: fb01 f202 mul.w r2, r1, r2 pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8004510: 68c1 ldr r1, [r0, #12] 8004512: f3c1 6141 ubfx r1, r1, #25, #2 8004516: 3101 adds r1, #1 8004518: 0049 lsls r1, r1, #1 sysclockfreq = pllvco/pllr; 800451a: fbb2 f2f1 udiv r2, r2, r1 if(pllfreq > 80000000U) 800451e: 42b2 cmp r2, r6 8004520: d90a bls.n 8004538 if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 8004522: 6882 ldr r2, [r0, #8] 8004524: f012 0ff0 tst.w r2, #240 ; 0xf0 8004528: f43f af46 beq.w 80043b8 800452c: 0799 lsls r1, r3, #30 800452e: d503 bpl.n 8004538 (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 8004530: 68a3 ldr r3, [r4, #8] 8004532: 2b00 cmp r3, #0 8004534: f43f af40 beq.w 80043b8 uint32_t hpre = RCC_SYSCLK_DIV1; 8004538: f04f 0900 mov.w r9, #0 800453c: e745 b.n 80043ca return HAL_ERROR; 800453e: 2001 movs r0, #1 } 8004540: 4770 bx lr 8004542: bf00 nop 8004544: 40022000 .word 0x40022000 8004548: 40021000 .word 0x40021000 800454c: 04c4b400 .word 0x04c4b400 8004550: 08007d30 .word 0x08007d30 8004554: 20000000 .word 0x20000000 8004558: 20000008 .word 0x20000008 800455c: 007a1200 .word 0x007a1200 8004560: 00f42400 .word 0x00f42400 08004564 : return SystemCoreClock; 8004564: 4b01 ldr r3, [pc, #4] ; (800456c ) } 8004566: 6818 ldr r0, [r3, #0] 8004568: 4770 bx lr 800456a: bf00 nop 800456c: 20000000 .word 0x20000000 08004570 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004570: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8004574: 6803 ldr r3, [r0, #0] { 8004576: 4604 mov r4, r0 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8004578: f413 2000 ands.w r0, r3, #524288 ; 0x80000 { 800457c: b082 sub sp, #8 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800457e: d056 beq.n 800462e /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8004580: 4b9f ldr r3, [pc, #636] ; (8004800 ) 8004582: 6d9a ldr r2, [r3, #88] ; 0x58 8004584: 00d5 lsls r5, r2, #3 8004586: f140 810c bpl.w 80047a2 FlagStatus pwrclkchanged = RESET; 800458a: 2700 movs r7, #0 __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800458c: 4d9d ldr r5, [pc, #628] ; (8004804 ) 800458e: 682b ldr r3, [r5, #0] 8004590: f443 7380 orr.w r3, r3, #256 ; 0x100 8004594: 602b str r3, [r5, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004596: f7fe fae9 bl 8002b6c 800459a: 4606 mov r6, r0 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 800459c: e005 b.n 80045aa { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800459e: f7fe fae5 bl 8002b6c 80045a2: 1b83 subs r3, r0, r6 80045a4: 2b02 cmp r3, #2 80045a6: f200 8107 bhi.w 80047b8 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 80045aa: 682b ldr r3, [r5, #0] 80045ac: 05d8 lsls r0, r3, #23 80045ae: d5f6 bpl.n 800459e } if(ret == HAL_OK) { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 80045b0: 4d93 ldr r5, [pc, #588] ; (8004800 ) 80045b2: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 80045b6: f413 7340 ands.w r3, r3, #768 ; 0x300 80045ba: d027 beq.n 800460c 80045bc: 6c22 ldr r2, [r4, #64] ; 0x40 80045be: 429a cmp r2, r3 80045c0: d025 beq.n 800460e { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 80045c2: f8d5 1090 ldr.w r1, [r5, #144] ; 0x90 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80045c6: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 80045ca: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80045ce: f8c5 3090 str.w r3, [r5, #144] ; 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); 80045d2: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 80045d6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80045da: f8c5 3090 str.w r3, [r5, #144] ; 0x90 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 80045de: f421 7340 bic.w r3, r1, #768 ; 0x300 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80045e2: 07c9 lsls r1, r1, #31 RCC->BDCR = tmpregister; 80045e4: f8c5 3090 str.w r3, [r5, #144] ; 0x90 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80045e8: f140 8108 bpl.w 80047fc { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80045ec: f7fe fabe bl 8002b6c /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80045f0: f241 3888 movw r8, #5000 ; 0x1388 tickstart = HAL_GetTick(); 80045f4: 4606 mov r6, r0 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80045f6: e005 b.n 8004604 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80045f8: f7fe fab8 bl 8002b6c 80045fc: 1b80 subs r0, r0, r6 80045fe: 4540 cmp r0, r8 8004600: f200 80da bhi.w 80047b8 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8004604: f8d5 3090 ldr.w r3, [r5, #144] ; 0x90 8004608: 079b lsls r3, r3, #30 800460a: d5f5 bpl.n 80045f8 if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 800460c: 6c23 ldr r3, [r4, #64] ; 0x40 } if(ret == HAL_OK) { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800460e: 497c ldr r1, [pc, #496] ; (8004800 ) 8004610: f8d1 2090 ldr.w r2, [r1, #144] ; 0x90 8004614: f422 7240 bic.w r2, r2, #768 ; 0x300 8004618: 4313 orrs r3, r2 800461a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800461e: 2000 movs r0, #0 /* set overall return value */ status = ret; } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 8004620: b127 cbz r7, 800462c { __HAL_RCC_PWR_CLK_DISABLE(); 8004622: 4a77 ldr r2, [pc, #476] ; (8004800 ) 8004624: 6d93 ldr r3, [r2, #88] ; 0x58 8004626: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800462a: 6593 str r3, [r2, #88] ; 0x58 } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 800462c: 6823 ldr r3, [r4, #0] 800462e: 07de lsls r6, r3, #31 8004630: d508 bpl.n 8004644 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8004632: 4973 ldr r1, [pc, #460] ; (8004800 ) 8004634: 6865 ldr r5, [r4, #4] 8004636: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 800463a: f022 0203 bic.w r2, r2, #3 800463e: 432a orrs r2, r5 8004640: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 8004644: 079d lsls r5, r3, #30 8004646: d508 bpl.n 800465a { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8004648: 496d ldr r1, [pc, #436] ; (8004800 ) 800464a: 68a5 ldr r5, [r4, #8] 800464c: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8004650: f022 020c bic.w r2, r2, #12 8004654: 432a orrs r2, r5 8004656: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 800465a: 0759 lsls r1, r3, #29 800465c: d508 bpl.n 8004670 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 800465e: 4968 ldr r1, [pc, #416] ; (8004800 ) 8004660: 68e5 ldr r5, [r4, #12] 8004662: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8004666: f022 0230 bic.w r2, r2, #48 ; 0x30 800466a: 432a orrs r2, r5 800466c: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 8004670: 071a lsls r2, r3, #28 8004672: d508 bpl.n 8004686 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 8004674: 4962 ldr r1, [pc, #392] ; (8004800 ) 8004676: 6925 ldr r5, [r4, #16] 8004678: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 800467c: f022 02c0 bic.w r2, r2, #192 ; 0xc0 8004680: 432a orrs r2, r5 8004682: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8004686: 069f lsls r7, r3, #26 8004688: d508 bpl.n 800469c { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800468a: 495d ldr r1, [pc, #372] ; (8004800 ) 800468c: 6965 ldr r5, [r4, #20] 800468e: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8004692: f422 6240 bic.w r2, r2, #3072 ; 0xc00 8004696: 432a orrs r2, r5 8004698: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 800469c: 065e lsls r6, r3, #25 800469e: d508 bpl.n 80046b2 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 80046a0: 4957 ldr r1, [pc, #348] ; (8004800 ) 80046a2: 69a5 ldr r5, [r4, #24] 80046a4: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80046a8: f422 5240 bic.w r2, r2, #12288 ; 0x3000 80046ac: 432a orrs r2, r5 80046ae: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 80046b2: 061d lsls r5, r3, #24 80046b4: d508 bpl.n 80046c8 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 80046b6: 4952 ldr r1, [pc, #328] ; (8004800 ) 80046b8: 69e5 ldr r5, [r4, #28] 80046ba: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80046be: f422 4240 bic.w r2, r2, #49152 ; 0xc000 80046c2: 432a orrs r2, r5 80046c4: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 80046c8: 05d9 lsls r1, r3, #23 80046ca: d508 bpl.n 80046de { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 80046cc: 494c ldr r1, [pc, #304] ; (8004800 ) 80046ce: 6a25 ldr r5, [r4, #32] 80046d0: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80046d4: f422 3240 bic.w r2, r2, #196608 ; 0x30000 80046d8: 432a orrs r2, r5 80046da: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 80046de: 059a lsls r2, r3, #22 80046e0: d508 bpl.n 80046f4 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 80046e2: 4947 ldr r1, [pc, #284] ; (8004800 ) 80046e4: 6a65 ldr r5, [r4, #36] ; 0x24 80046e6: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 80046ea: f422 2240 bic.w r2, r2, #786432 ; 0xc0000 80046ee: 432a orrs r2, r5 80046f0: f8c1 2088 str.w r2, [r1, #136] ; 0x88 } /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80046f4: 055f lsls r7, r3, #21 80046f6: d50b bpl.n 8004710 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80046f8: 4941 ldr r1, [pc, #260] ; (8004800 ) 80046fa: 6aa5 ldr r5, [r4, #40] ; 0x28 80046fc: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8004700: f422 1240 bic.w r2, r2, #3145728 ; 0x300000 8004704: 432a orrs r2, r5 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) 8004706: f5b5 1f80 cmp.w r5, #1048576 ; 0x100000 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800470a: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) 800470e: d055 beq.n 80047bc __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) 8004710: 051e lsls r6, r3, #20 8004712: d50b bpl.n 800472c { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 8004714: 493a ldr r1, [pc, #232] ; (8004800 ) 8004716: 6ae5 ldr r5, [r4, #44] ; 0x2c 8004718: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 800471c: f422 0240 bic.w r2, r2, #12582912 ; 0xc00000 8004720: 432a orrs r2, r5 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) 8004722: f5b5 0f80 cmp.w r5, #4194304 ; 0x400000 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 8004726: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) 800472a: d04c beq.n 80047c6 } } #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800472c: 04dd lsls r5, r3, #19 800472e: d50b bpl.n 8004748 { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8004730: 4933 ldr r1, [pc, #204] ; (8004800 ) 8004732: 6b25 ldr r5, [r4, #48] ; 0x30 8004734: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8004738: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000 800473c: 432a orrs r2, r5 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) 800473e: f1b5 7f80 cmp.w r5, #16777216 ; 0x1000000 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8004742: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) 8004746: d043 beq.n 80047d0 #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 8004748: 0499 lsls r1, r3, #18 800474a: d50b bpl.n 8004764 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800474c: 492c ldr r1, [pc, #176] ; (8004800 ) 800474e: 6b65 ldr r5, [r4, #52] ; 0x34 8004750: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8004754: f022 6240 bic.w r2, r2, #201326592 ; 0xc000000 8004758: 432a orrs r2, r5 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 800475a: f1b5 6f00 cmp.w r5, #134217728 ; 0x8000000 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800475e: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 8004762: d03a beq.n 80047da } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 8004764: 045a lsls r2, r3, #17 8004766: d50b bpl.n 8004780 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8004768: 4925 ldr r1, [pc, #148] ; (8004800 ) 800476a: 6ba5 ldr r5, [r4, #56] ; 0x38 800476c: f8d1 2088 ldr.w r2, [r1, #136] ; 0x88 8004770: f022 6240 bic.w r2, r2, #201326592 ; 0xc000000 8004774: 432a orrs r2, r5 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 8004776: f1b5 6f00 cmp.w r5, #134217728 ; 0x8000000 __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800477a: f8c1 2088 str.w r2, [r1, #136] ; 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 800477e: d031 beq.n 80047e4 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) 8004780: 041b lsls r3, r3, #16 8004782: d50b bpl.n 800479c { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 8004784: 4a1e ldr r2, [pc, #120] ; (8004800 ) 8004786: 6be1 ldr r1, [r4, #60] ; 0x3c 8004788: f8d2 3088 ldr.w r3, [r2, #136] ; 0x88 800478c: f023 5340 bic.w r3, r3, #805306368 ; 0x30000000 8004790: 430b orrs r3, r1 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) 8004792: f1b1 5f80 cmp.w r1, #268435456 ; 0x10000000 __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 8004796: f8c2 3088 str.w r3, [r2, #136] ; 0x88 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) 800479a: d028 beq.n 80047ee } #endif /* QUADSPI */ return status; } 800479c: b002 add sp, #8 800479e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_RCC_PWR_CLK_ENABLE(); 80047a2: 6d9a ldr r2, [r3, #88] ; 0x58 80047a4: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000 80047a8: 659a str r2, [r3, #88] ; 0x58 80047aa: 6d9b ldr r3, [r3, #88] ; 0x58 80047ac: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80047b0: 9301 str r3, [sp, #4] 80047b2: 9b01 ldr r3, [sp, #4] pwrclkchanged = SET; 80047b4: 2701 movs r7, #1 80047b6: e6e9 b.n 800458c status = ret; 80047b8: 2003 movs r0, #3 80047ba: e731 b.n 8004620 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80047bc: 68ca ldr r2, [r1, #12] 80047be: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80047c2: 60ca str r2, [r1, #12] 80047c4: e7a4 b.n 8004710 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80047c6: 68ca ldr r2, [r1, #12] 80047c8: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80047cc: 60ca str r2, [r1, #12] 80047ce: e7ad b.n 800472c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80047d0: 68ca ldr r2, [r1, #12] 80047d2: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80047d6: 60ca str r2, [r1, #12] 80047d8: e7b6 b.n 8004748 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80047da: 68ca ldr r2, [r1, #12] 80047dc: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80047e0: 60ca str r2, [r1, #12] 80047e2: e7bf b.n 8004764 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80047e4: 68ca ldr r2, [r1, #12] 80047e6: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 80047ea: 60ca str r2, [r1, #12] 80047ec: e7c8 b.n 8004780 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 80047ee: 68d3 ldr r3, [r2, #12] 80047f0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80047f4: 60d3 str r3, [r2, #12] } 80047f6: b002 add sp, #8 80047f8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80047fc: 4613 mov r3, r2 80047fe: e706 b.n 800460e 8004800: 40021000 .word 0x40021000 8004804: 40007000 .word 0x40007000 08004808 : uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8004808: 6a03 ldr r3, [r0, #32] 800480a: f023 0301 bic.w r3, r3, #1 800480e: 6203 str r3, [r0, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8004810: 6a03 ldr r3, [r0, #32] { 8004812: b470 push {r4, r5, r6} /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8004814: 6844 ldr r4, [r0, #4] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8004816: 6982 ldr r2, [r0, #24] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8004818: 680d ldr r5, [r1, #0] tmpccmrx &= ~TIM_CCMR1_CC1S; 800481a: f422 3280 bic.w r2, r2, #65536 ; 0x10000 800481e: f022 0273 bic.w r2, r2, #115 ; 0x73 tmpccmrx |= OC_Config->OCMode; 8004822: 432a orrs r2, r5 /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8004824: 688d ldr r5, [r1, #8] tmpccer &= ~TIM_CCER_CC1P; 8004826: f023 0302 bic.w r3, r3, #2 tmpccer |= OC_Config->OCPolarity; 800482a: 432b orrs r3, r5 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800482c: 4d13 ldr r5, [pc, #76] ; (800487c ) 800482e: 42a8 cmp r0, r5 8004830: d00f beq.n 8004852 8004832: f505 6500 add.w r5, r5, #2048 ; 0x800 8004836: 42a8 cmp r0, r5 8004838: d00b beq.n 8004852 800483a: f505 6540 add.w r5, r5, #3072 ; 0xc00 800483e: 42a8 cmp r0, r5 8004840: d007 beq.n 8004852 8004842: f505 6580 add.w r5, r5, #1024 ; 0x400 8004846: 42a8 cmp r0, r5 8004848: d003 beq.n 8004852 800484a: f505 6580 add.w r5, r5, #1024 ; 0x400 800484e: 42a8 cmp r0, r5 8004850: d10d bne.n 800486e assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8004852: 68cd ldr r5, [r1, #12] tmpccer &= ~TIM_CCER_CC1NP; 8004854: f023 0308 bic.w r3, r3, #8 tmpccer |= OC_Config->OCNPolarity; 8004858: 432b orrs r3, r5 tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800485a: e9d1 6505 ldrd r6, r5, [r1, #20] tmpcr2 &= ~TIM_CR2_OIS1N; 800485e: f424 7440 bic.w r4, r4, #768 ; 0x300 tmpcr2 |= OC_Config->OCNIdleState; 8004862: ea46 0c05 orr.w ip, r6, r5 tmpccer &= ~TIM_CCER_CC1NE; 8004866: f023 0304 bic.w r3, r3, #4 tmpcr2 |= OC_Config->OCNIdleState; 800486a: ea4c 0404 orr.w r4, ip, r4 /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800486e: 6849 ldr r1, [r1, #4] TIMx->CR2 = tmpcr2; 8004870: 6044 str r4, [r0, #4] TIMx->CCMR1 = tmpccmrx; 8004872: 6182 str r2, [r0, #24] /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } 8004874: bc70 pop {r4, r5, r6} TIMx->CCR1 = OC_Config->Pulse; 8004876: 6341 str r1, [r0, #52] ; 0x34 TIMx->CCER = tmpccer; 8004878: 6203 str r3, [r0, #32] } 800487a: 4770 bx lr 800487c: 40012c00 .word 0x40012c00 08004880 : uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8004880: 6a03 ldr r3, [r0, #32] 8004882: f423 7380 bic.w r3, r3, #256 ; 0x100 8004886: 6203 str r3, [r0, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8004888: 6a03 ldr r3, [r0, #32] { 800488a: b470 push {r4, r5, r6} /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800488c: 6844 ldr r4, [r0, #4] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800488e: 69c2 ldr r2, [r0, #28] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8004890: 680d ldr r5, [r1, #0] tmpccmrx &= ~TIM_CCMR2_CC3S; 8004892: f422 3280 bic.w r2, r2, #65536 ; 0x10000 8004896: f022 0273 bic.w r2, r2, #115 ; 0x73 tmpccmrx |= OC_Config->OCMode; 800489a: 432a orrs r2, r5 /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800489c: 688d ldr r5, [r1, #8] tmpccer &= ~TIM_CCER_CC3P; 800489e: f423 7300 bic.w r3, r3, #512 ; 0x200 tmpccer |= (OC_Config->OCPolarity << 8U); 80048a2: ea43 2305 orr.w r3, r3, r5, lsl #8 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80048a6: 4d15 ldr r5, [pc, #84] ; (80048fc ) 80048a8: 42a8 cmp r0, r5 80048aa: d010 beq.n 80048ce 80048ac: f505 6500 add.w r5, r5, #2048 ; 0x800 80048b0: 42a8 cmp r0, r5 80048b2: d00c beq.n 80048ce tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80048b4: f505 6540 add.w r5, r5, #3072 ; 0xc00 80048b8: 42a8 cmp r0, r5 80048ba: d00f beq.n 80048dc 80048bc: f505 6580 add.w r5, r5, #1024 ; 0x400 80048c0: 42a8 cmp r0, r5 80048c2: d00b beq.n 80048dc 80048c4: f505 6580 add.w r5, r5, #1024 ; 0x400 80048c8: 42a8 cmp r0, r5 80048ca: d10f bne.n 80048ec 80048cc: e006 b.n 80048dc tmpccer |= (OC_Config->OCNPolarity << 8U); 80048ce: 68cd ldr r5, [r1, #12] tmpccer &= ~TIM_CCER_CC3NP; 80048d0: f423 6300 bic.w r3, r3, #2048 ; 0x800 tmpccer |= (OC_Config->OCNPolarity << 8U); 80048d4: ea43 2305 orr.w r3, r3, r5, lsl #8 tmpccer &= ~TIM_CCER_CC3NE; 80048d8: f423 6380 bic.w r3, r3, #1024 ; 0x400 tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80048dc: e9d1 6505 ldrd r6, r5, [r1, #20] tmpcr2 &= ~TIM_CR2_OIS3N; 80048e0: f424 5440 bic.w r4, r4, #12288 ; 0x3000 tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80048e4: ea46 0c05 orr.w ip, r6, r5 80048e8: ea44 140c orr.w r4, r4, ip, lsl #4 /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80048ec: 6849 ldr r1, [r1, #4] TIMx->CR2 = tmpcr2; 80048ee: 6044 str r4, [r0, #4] TIMx->CCMR2 = tmpccmrx; 80048f0: 61c2 str r2, [r0, #28] /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } 80048f2: bc70 pop {r4, r5, r6} TIMx->CCR3 = OC_Config->Pulse; 80048f4: 63c1 str r1, [r0, #60] ; 0x3c TIMx->CCER = tmpccer; 80048f6: 6203 str r3, [r0, #32] } 80048f8: 4770 bx lr 80048fa: bf00 nop 80048fc: 40012c00 .word 0x40012c00 08004900 : uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8004900: 6a03 ldr r3, [r0, #32] 8004902: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8004906: 6203 str r3, [r0, #32] /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8004908: 6a03 ldr r3, [r0, #32] { 800490a: b470 push {r4, r5, r6} /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800490c: 6844 ldr r4, [r0, #4] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800490e: 69c2 ldr r2, [r0, #28] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8004910: 680d ldr r5, [r1, #0] tmpccmrx &= ~TIM_CCMR2_CC4S; 8004912: f022 7280 bic.w r2, r2, #16777216 ; 0x1000000 8004916: f422 42e6 bic.w r2, r2, #29440 ; 0x7300 tmpccmrx |= (OC_Config->OCMode << 8U); 800491a: ea42 2205 orr.w r2, r2, r5, lsl #8 /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 800491e: 688d ldr r5, [r1, #8] tmpccer &= ~TIM_CCER_CC4P; 8004920: f423 5300 bic.w r3, r3, #8192 ; 0x2000 tmpccer |= (OC_Config->OCPolarity << 12U); 8004924: ea43 3305 orr.w r3, r3, r5, lsl #12 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) 8004928: 4d14 ldr r5, [pc, #80] ; (800497c ) 800492a: 42a8 cmp r0, r5 800492c: d010 beq.n 8004950 800492e: f505 6500 add.w r5, r5, #2048 ; 0x800 8004932: 42a8 cmp r0, r5 8004934: d00c beq.n 8004950 tmpccer |= (OC_Config->OCNPolarity << 12U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC4NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004936: f505 6540 add.w r5, r5, #3072 ; 0xc00 800493a: 42a8 cmp r0, r5 800493c: d00f beq.n 800495e 800493e: f505 6580 add.w r5, r5, #1024 ; 0x400 8004942: 42a8 cmp r0, r5 8004944: d00b beq.n 800495e 8004946: f505 6580 add.w r5, r5, #1024 ; 0x400 800494a: 42a8 cmp r0, r5 800494c: d10f bne.n 800496e 800494e: e006 b.n 800495e tmpccer |= (OC_Config->OCNPolarity << 12U); 8004950: 68cd ldr r5, [r1, #12] tmpccer &= ~TIM_CCER_CC4NP; 8004952: f423 4300 bic.w r3, r3, #32768 ; 0x8000 tmpccer |= (OC_Config->OCNPolarity << 12U); 8004956: ea43 3305 orr.w r3, r3, r5, lsl #12 tmpccer &= ~TIM_CCER_CC4NE; 800495a: f423 4380 bic.w r3, r3, #16384 ; 0x4000 tmpcr2 &= ~TIM_CR2_OIS4N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 6U); 800495e: e9d1 6505 ldrd r6, r5, [r1, #20] tmpcr2 &= ~TIM_CR2_OIS4N; 8004962: f424 4440 bic.w r4, r4, #49152 ; 0xc000 tmpcr2 |= (OC_Config->OCNIdleState << 6U); 8004966: ea46 0c05 orr.w ip, r6, r5 800496a: ea44 148c orr.w r4, r4, ip, lsl #6 /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 800496e: 6849 ldr r1, [r1, #4] TIMx->CR2 = tmpcr2; 8004970: 6044 str r4, [r0, #4] TIMx->CCMR2 = tmpccmrx; 8004972: 61c2 str r2, [r0, #28] /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } 8004974: bc70 pop {r4, r5, r6} TIMx->CCR4 = OC_Config->Pulse; 8004976: 6401 str r1, [r0, #64] ; 0x40 TIMx->CCER = tmpccer; 8004978: 6203 str r3, [r0, #32] } 800497a: 4770 bx lr 800497c: 40012c00 .word 0x40012c00 08004980 : if (htim == NULL) 8004980: 2800 cmp r0, #0 8004982: f000 8081 beq.w 8004a88 { 8004986: b510 push {r4, lr} if (htim->State == HAL_TIM_STATE_RESET) 8004988: f890 303d ldrb.w r3, [r0, #61] ; 0x3d 800498c: 4604 mov r4, r0 800498e: f003 02ff and.w r2, r3, #255 ; 0xff 8004992: 2b00 cmp r3, #0 8004994: d06d beq.n 8004a72 TIM_Base_SetConfig(htim->Instance, &htim->Init); 8004996: 6822 ldr r2, [r4, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8004998: 493c ldr r1, [pc, #240] ; (8004a8c ) htim->State = HAL_TIM_STATE_BUSY; 800499a: 2302 movs r3, #2 800499c: f884 303d strb.w r3, [r4, #61] ; 0x3d if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80049a0: 428a cmp r2, r1 tmpcr1 = TIMx->CR1; 80049a2: 6813 ldr r3, [r2, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80049a4: d051 beq.n 8004a4a 80049a6: f1b2 4f80 cmp.w r2, #1073741824 ; 0x40000000 80049aa: d021 beq.n 80049f0 80049ac: f5a1 3194 sub.w r1, r1, #75776 ; 0x12800 80049b0: 428a cmp r2, r1 80049b2: d01d beq.n 80049f0 80049b4: f501 6180 add.w r1, r1, #1024 ; 0x400 80049b8: 428a cmp r2, r1 80049ba: d019 beq.n 80049f0 80049bc: f501 3196 add.w r1, r1, #76800 ; 0x12c00 80049c0: 428a cmp r2, r1 80049c2: d042 beq.n 8004a4a if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80049c4: f501 6140 add.w r1, r1, #3072 ; 0xc00 80049c8: 428a cmp r2, r1 80049ca: d057 beq.n 8004a7c 80049cc: f501 6180 add.w r1, r1, #1024 ; 0x400 80049d0: 428a cmp r2, r1 80049d2: d053 beq.n 8004a7c 80049d4: f501 6180 add.w r1, r1, #1024 ; 0x400 80049d8: 428a cmp r2, r1 80049da: d04f beq.n 8004a7c MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80049dc: 69a0 ldr r0, [r4, #24] TIMx->ARR = (uint32_t)Structure->Period ; 80049de: 68e1 ldr r1, [r4, #12] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80049e0: f023 0380 bic.w r3, r3, #128 ; 0x80 80049e4: 4303 orrs r3, r0 TIMx->CR1 = tmpcr1; 80049e6: 6013 str r3, [r2, #0] TIMx->PSC = Structure->Prescaler; 80049e8: 6863 ldr r3, [r4, #4] TIMx->ARR = (uint32_t)Structure->Period ; 80049ea: 62d1 str r1, [r2, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 80049ec: 6293 str r3, [r2, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80049ee: e010 b.n 8004a12 tmpcr1 |= Structure->CounterMode; 80049f0: 68a1 ldr r1, [r4, #8] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80049f2: 6920 ldr r0, [r4, #16] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80049f4: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 80049f8: 430b orrs r3, r1 tmpcr1 &= ~TIM_CR1_CKD; 80049fa: f423 7340 bic.w r3, r3, #768 ; 0x300 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80049fe: 69a1 ldr r1, [r4, #24] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004a00: 4303 orrs r3, r0 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004a02: f023 0380 bic.w r3, r3, #128 ; 0x80 TIMx->ARR = (uint32_t)Structure->Period ; 8004a06: 68e0 ldr r0, [r4, #12] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004a08: 430b orrs r3, r1 TIMx->PSC = Structure->Prescaler; 8004a0a: 6861 ldr r1, [r4, #4] TIMx->CR1 = tmpcr1; 8004a0c: 6013 str r3, [r2, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8004a0e: 62d0 str r0, [r2, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 8004a10: 6291 str r1, [r2, #40] ; 0x28 TIMx->EGR = TIM_EGR_UG; 8004a12: 2301 movs r3, #1 8004a14: 6153 str r3, [r2, #20] htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8004a16: f884 3048 strb.w r3, [r4, #72] ; 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004a1a: f884 303e strb.w r3, [r4, #62] ; 0x3e 8004a1e: f884 303f strb.w r3, [r4, #63] ; 0x3f 8004a22: f884 3040 strb.w r3, [r4, #64] ; 0x40 8004a26: f884 3041 strb.w r3, [r4, #65] ; 0x41 8004a2a: f884 3042 strb.w r3, [r4, #66] ; 0x42 8004a2e: f884 3043 strb.w r3, [r4, #67] ; 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004a32: f884 3044 strb.w r3, [r4, #68] ; 0x44 8004a36: f884 3045 strb.w r3, [r4, #69] ; 0x45 8004a3a: f884 3046 strb.w r3, [r4, #70] ; 0x46 8004a3e: f884 3047 strb.w r3, [r4, #71] ; 0x47 htim->State = HAL_TIM_STATE_READY; 8004a42: f884 303d strb.w r3, [r4, #61] ; 0x3d return HAL_OK; 8004a46: 2000 movs r0, #0 } 8004a48: bd10 pop {r4, pc} tmpcr1 |= Structure->CounterMode; 8004a4a: 68a0 ldr r0, [r4, #8] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004a4c: 6921 ldr r1, [r4, #16] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8004a4e: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 8004a52: 4303 orrs r3, r0 tmpcr1 &= ~TIM_CR1_CKD; 8004a54: f423 7340 bic.w r3, r3, #768 ; 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004a58: 430b orrs r3, r1 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004a5a: 69a1 ldr r1, [r4, #24] 8004a5c: f023 0380 bic.w r3, r3, #128 ; 0x80 8004a60: 430b orrs r3, r1 TIMx->CR1 = tmpcr1; 8004a62: 6013 str r3, [r2, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8004a64: 68e3 ldr r3, [r4, #12] 8004a66: 62d3 str r3, [r2, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 8004a68: 6863 ldr r3, [r4, #4] 8004a6a: 6293 str r3, [r2, #40] ; 0x28 TIMx->RCR = Structure->RepetitionCounter; 8004a6c: 6963 ldr r3, [r4, #20] 8004a6e: 6313 str r3, [r2, #48] ; 0x30 8004a70: e7cf b.n 8004a12 htim->Lock = HAL_UNLOCKED; 8004a72: f880 203c strb.w r2, [r0, #60] ; 0x3c HAL_TIM_Base_MspInit(htim); 8004a76: f7fd ffaf bl 80029d8 8004a7a: e78c b.n 8004996 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004a7c: 6920 ldr r0, [r4, #16] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004a7e: 69a1 ldr r1, [r4, #24] tmpcr1 &= ~TIM_CR1_CKD; 8004a80: f423 7340 bic.w r3, r3, #768 ; 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004a84: 4303 orrs r3, r0 8004a86: e7e9 b.n 8004a5c return HAL_ERROR; 8004a88: 2001 movs r0, #1 } 8004a8a: 4770 bx lr 8004a8c: 40012c00 .word 0x40012c00 08004a90 : if (htim->State != HAL_TIM_STATE_READY) 8004a90: f890 303d ldrb.w r3, [r0, #61] ; 0x3d 8004a94: 2b01 cmp r3, #1 8004a96: d122 bne.n 8004ade __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8004a98: 6803 ldr r3, [r0, #0] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8004a9a: 4917 ldr r1, [pc, #92] ; (8004af8 ) htim->State = HAL_TIM_STATE_BUSY; 8004a9c: 2202 movs r2, #2 8004a9e: f880 203d strb.w r2, [r0, #61] ; 0x3d __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8004aa2: 68da ldr r2, [r3, #12] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8004aa4: 428b cmp r3, r1 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8004aa6: f042 0201 orr.w r2, r2, #1 8004aaa: 60da str r2, [r3, #12] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8004aac: d019 beq.n 8004ae2 8004aae: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004ab2: d016 beq.n 8004ae2 8004ab4: 4a11 ldr r2, [pc, #68] ; (8004afc ) 8004ab6: 4293 cmp r3, r2 8004ab8: d013 beq.n 8004ae2 8004aba: f502 6280 add.w r2, r2, #1024 ; 0x400 8004abe: 4293 cmp r3, r2 8004ac0: d00f beq.n 8004ae2 8004ac2: f502 3296 add.w r2, r2, #76800 ; 0x12c00 8004ac6: 4293 cmp r3, r2 8004ac8: d00b beq.n 8004ae2 8004aca: f502 6240 add.w r2, r2, #3072 ; 0xc00 8004ace: 4293 cmp r3, r2 8004ad0: d007 beq.n 8004ae2 __HAL_TIM_ENABLE(htim); 8004ad2: 681a ldr r2, [r3, #0] 8004ad4: f042 0201 orr.w r2, r2, #1 return HAL_OK; 8004ad8: 2000 movs r0, #0 __HAL_TIM_ENABLE(htim); 8004ada: 601a str r2, [r3, #0] 8004adc: 4770 bx lr return HAL_ERROR; 8004ade: 2001 movs r0, #1 8004ae0: 4770 bx lr tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8004ae2: 6899 ldr r1, [r3, #8] 8004ae4: 4a06 ldr r2, [pc, #24] ; (8004b00 ) 8004ae6: 400a ands r2, r1 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8004ae8: 2a06 cmp r2, #6 8004aea: d002 beq.n 8004af2 8004aec: f5b2 3f80 cmp.w r2, #65536 ; 0x10000 8004af0: d1ef bne.n 8004ad2 return HAL_OK; 8004af2: 2000 movs r0, #0 } 8004af4: 4770 bx lr 8004af6: bf00 nop 8004af8: 40012c00 .word 0x40012c00 8004afc: 40000400 .word 0x40000400 8004b00: 00010007 .word 0x00010007 08004b04 : 8004b04: 4770 bx lr 8004b06: bf00 nop 08004b08 : if (htim == NULL) 8004b08: 2800 cmp r0, #0 8004b0a: f000 8081 beq.w 8004c10 { 8004b0e: b510 push {r4, lr} if (htim->State == HAL_TIM_STATE_RESET) 8004b10: f890 303d ldrb.w r3, [r0, #61] ; 0x3d 8004b14: 4604 mov r4, r0 8004b16: f003 02ff and.w r2, r3, #255 ; 0xff 8004b1a: 2b00 cmp r3, #0 8004b1c: d06d beq.n 8004bfa TIM_Base_SetConfig(htim->Instance, &htim->Init); 8004b1e: 6822 ldr r2, [r4, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8004b20: 493c ldr r1, [pc, #240] ; (8004c14 ) htim->State = HAL_TIM_STATE_BUSY; 8004b22: 2302 movs r3, #2 8004b24: f884 303d strb.w r3, [r4, #61] ; 0x3d if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8004b28: 428a cmp r2, r1 tmpcr1 = TIMx->CR1; 8004b2a: 6813 ldr r3, [r2, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8004b2c: d051 beq.n 8004bd2 8004b2e: f1b2 4f80 cmp.w r2, #1073741824 ; 0x40000000 8004b32: d021 beq.n 8004b78 8004b34: f5a1 3194 sub.w r1, r1, #75776 ; 0x12800 8004b38: 428a cmp r2, r1 8004b3a: d01d beq.n 8004b78 8004b3c: f501 6180 add.w r1, r1, #1024 ; 0x400 8004b40: 428a cmp r2, r1 8004b42: d019 beq.n 8004b78 8004b44: f501 3196 add.w r1, r1, #76800 ; 0x12c00 8004b48: 428a cmp r2, r1 8004b4a: d042 beq.n 8004bd2 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8004b4c: f501 6140 add.w r1, r1, #3072 ; 0xc00 8004b50: 428a cmp r2, r1 8004b52: d057 beq.n 8004c04 8004b54: f501 6180 add.w r1, r1, #1024 ; 0x400 8004b58: 428a cmp r2, r1 8004b5a: d053 beq.n 8004c04 8004b5c: f501 6180 add.w r1, r1, #1024 ; 0x400 8004b60: 428a cmp r2, r1 8004b62: d04f beq.n 8004c04 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004b64: 69a0 ldr r0, [r4, #24] TIMx->ARR = (uint32_t)Structure->Period ; 8004b66: 68e1 ldr r1, [r4, #12] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004b68: f023 0380 bic.w r3, r3, #128 ; 0x80 8004b6c: 4303 orrs r3, r0 TIMx->CR1 = tmpcr1; 8004b6e: 6013 str r3, [r2, #0] TIMx->PSC = Structure->Prescaler; 8004b70: 6863 ldr r3, [r4, #4] TIMx->ARR = (uint32_t)Structure->Period ; 8004b72: 62d1 str r1, [r2, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 8004b74: 6293 str r3, [r2, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8004b76: e010 b.n 8004b9a tmpcr1 |= Structure->CounterMode; 8004b78: 68a1 ldr r1, [r4, #8] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004b7a: 6920 ldr r0, [r4, #16] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8004b7c: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 8004b80: 430b orrs r3, r1 tmpcr1 &= ~TIM_CR1_CKD; 8004b82: f423 7340 bic.w r3, r3, #768 ; 0x300 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004b86: 69a1 ldr r1, [r4, #24] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004b88: 4303 orrs r3, r0 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004b8a: f023 0380 bic.w r3, r3, #128 ; 0x80 TIMx->ARR = (uint32_t)Structure->Period ; 8004b8e: 68e0 ldr r0, [r4, #12] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004b90: 430b orrs r3, r1 TIMx->PSC = Structure->Prescaler; 8004b92: 6861 ldr r1, [r4, #4] TIMx->CR1 = tmpcr1; 8004b94: 6013 str r3, [r2, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8004b96: 62d0 str r0, [r2, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 8004b98: 6291 str r1, [r2, #40] ; 0x28 TIMx->EGR = TIM_EGR_UG; 8004b9a: 2301 movs r3, #1 8004b9c: 6153 str r3, [r2, #20] htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8004b9e: f884 3048 strb.w r3, [r4, #72] ; 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004ba2: f884 303e strb.w r3, [r4, #62] ; 0x3e 8004ba6: f884 303f strb.w r3, [r4, #63] ; 0x3f 8004baa: f884 3040 strb.w r3, [r4, #64] ; 0x40 8004bae: f884 3041 strb.w r3, [r4, #65] ; 0x41 8004bb2: f884 3042 strb.w r3, [r4, #66] ; 0x42 8004bb6: f884 3043 strb.w r3, [r4, #67] ; 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8004bba: f884 3044 strb.w r3, [r4, #68] ; 0x44 8004bbe: f884 3045 strb.w r3, [r4, #69] ; 0x45 8004bc2: f884 3046 strb.w r3, [r4, #70] ; 0x46 8004bc6: f884 3047 strb.w r3, [r4, #71] ; 0x47 htim->State = HAL_TIM_STATE_READY; 8004bca: f884 303d strb.w r3, [r4, #61] ; 0x3d return HAL_OK; 8004bce: 2000 movs r0, #0 } 8004bd0: bd10 pop {r4, pc} tmpcr1 |= Structure->CounterMode; 8004bd2: 68a0 ldr r0, [r4, #8] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004bd4: 6921 ldr r1, [r4, #16] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8004bd6: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr1 |= Structure->CounterMode; 8004bda: 4303 orrs r3, r0 tmpcr1 &= ~TIM_CR1_CKD; 8004bdc: f423 7340 bic.w r3, r3, #768 ; 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004be0: 430b orrs r3, r1 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004be2: 69a1 ldr r1, [r4, #24] 8004be4: f023 0380 bic.w r3, r3, #128 ; 0x80 8004be8: 430b orrs r3, r1 TIMx->CR1 = tmpcr1; 8004bea: 6013 str r3, [r2, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8004bec: 68e3 ldr r3, [r4, #12] 8004bee: 62d3 str r3, [r2, #44] ; 0x2c TIMx->PSC = Structure->Prescaler; 8004bf0: 6863 ldr r3, [r4, #4] 8004bf2: 6293 str r3, [r2, #40] ; 0x28 TIMx->RCR = Structure->RepetitionCounter; 8004bf4: 6963 ldr r3, [r4, #20] 8004bf6: 6313 str r3, [r2, #48] ; 0x30 8004bf8: e7cf b.n 8004b9a htim->Lock = HAL_UNLOCKED; 8004bfa: f880 203c strb.w r2, [r0, #60] ; 0x3c HAL_TIM_PWM_MspInit(htim); 8004bfe: f7ff ff81 bl 8004b04 8004c02: e78c b.n 8004b1e tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004c04: 6920 ldr r0, [r4, #16] MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004c06: 69a1 ldr r1, [r4, #24] tmpcr1 &= ~TIM_CR1_CKD; 8004c08: f423 7340 bic.w r3, r3, #768 ; 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004c0c: 4303 orrs r3, r0 8004c0e: e7e9 b.n 8004be4 return HAL_ERROR; 8004c10: 2001 movs r0, #1 } 8004c12: 4770 bx lr 8004c14: 40012c00 .word 0x40012c00 08004c18 : 8004c18: 2910 cmp r1, #16 8004c1a: d80a bhi.n 8004c32 8004c1c: e8df f001 tbb [pc, r1] 8004c20: 09090955 .word 0x09090955 8004c24: 0909095b .word 0x0909095b 8004c28: 09090963 .word 0x09090963 8004c2c: 09090968 .word 0x09090968 8004c30: 71 .byte 0x71 8004c31: 00 .byte 0x00 8004c32: f890 3043 ldrb.w r3, [r0, #67] ; 0x43 8004c36: 2b01 cmp r3, #1 8004c38: d14b bne.n 8004cd2 8004c3a: 2910 cmp r1, #16 8004c3c: d80a bhi.n 8004c54 8004c3e: e8df f001 tbb [pc, r1] 8004c42: 0987 .short 0x0987 8004c44: 094e0909 .word 0x094e0909 8004c48: 09700909 .word 0x09700909 8004c4c: 096c0909 .word 0x096c0909 8004c50: 0909 .short 0x0909 8004c52: 68 .byte 0x68 8004c53: 00 .byte 0x00 8004c54: 2302 movs r3, #2 8004c56: f880 3043 strb.w r3, [r0, #67] ; 0x43 8004c5a: 6803 ldr r3, [r0, #0] 8004c5c: 2201 movs r2, #1 8004c5e: 6a18 ldr r0, [r3, #32] 8004c60: f001 011f and.w r1, r1, #31 8004c64: fa02 f101 lsl.w r1, r2, r1 8004c68: ea20 0001 bic.w r0, r0, r1 8004c6c: 6218 str r0, [r3, #32] 8004c6e: 6a18 ldr r0, [r3, #32] 8004c70: 4a39 ldr r2, [pc, #228] ; (8004d58 ) 8004c72: 4301 orrs r1, r0 8004c74: 4293 cmp r3, r2 8004c76: 6219 str r1, [r3, #32] 8004c78: d057 beq.n 8004d2a 8004c7a: f502 6200 add.w r2, r2, #2048 ; 0x800 8004c7e: 4293 cmp r3, r2 8004c80: d061 beq.n 8004d46 8004c82: f502 6240 add.w r2, r2, #3072 ; 0xc00 8004c86: 4293 cmp r3, r2 8004c88: d05d beq.n 8004d46 8004c8a: f502 6280 add.w r2, r2, #1024 ; 0x400 8004c8e: 4293 cmp r3, r2 8004c90: d059 beq.n 8004d46 8004c92: f502 6280 add.w r2, r2, #1024 ; 0x400 8004c96: 4293 cmp r3, r2 8004c98: d055 beq.n 8004d46 8004c9a: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004c9e: d048 beq.n 8004d32 8004ca0: 4a2e ldr r2, [pc, #184] ; (8004d5c ) 8004ca2: 4293 cmp r3, r2 8004ca4: d045 beq.n 8004d32 8004ca6: f502 6280 add.w r2, r2, #1024 ; 0x400 8004caa: 4293 cmp r3, r2 8004cac: d041 beq.n 8004d32 8004cae: f502 3296 add.w r2, r2, #76800 ; 0x12c00 8004cb2: 4293 cmp r3, r2 8004cb4: d03d beq.n 8004d32 8004cb6: f502 6240 add.w r2, r2, #3072 ; 0xc00 8004cba: 4293 cmp r3, r2 8004cbc: d039 beq.n 8004d32 8004cbe: 681a ldr r2, [r3, #0] 8004cc0: f042 0201 orr.w r2, r2, #1 8004cc4: 2000 movs r0, #0 8004cc6: 601a str r2, [r3, #0] 8004cc8: 4770 bx lr 8004cca: f890 303e ldrb.w r3, [r0, #62] ; 0x3e 8004cce: 2b01 cmp r3, #1 8004cd0: d03e beq.n 8004d50 8004cd2: 2001 movs r0, #1 8004cd4: 4770 bx lr 8004cd6: f890 303f ldrb.w r3, [r0, #63] ; 0x3f 8004cda: 2b01 cmp r3, #1 8004cdc: d1f9 bne.n 8004cd2 8004cde: 2302 movs r3, #2 8004ce0: f880 303f strb.w r3, [r0, #63] ; 0x3f 8004ce4: e7b9 b.n 8004c5a 8004ce6: f890 3040 ldrb.w r3, [r0, #64] ; 0x40 8004cea: 2b01 cmp r3, #1 8004cec: d0a5 beq.n 8004c3a 8004cee: e7f0 b.n 8004cd2 8004cf0: f890 3041 ldrb.w r3, [r0, #65] ; 0x41 8004cf4: 3b01 subs r3, #1 8004cf6: bf18 it ne 8004cf8: 2301 movne r3, #1 8004cfa: 2b00 cmp r3, #0 8004cfc: d09d beq.n 8004c3a 8004cfe: 2001 movs r0, #1 8004d00: 4770 bx lr 8004d02: f890 3042 ldrb.w r3, [r0, #66] ; 0x42 8004d06: 3b01 subs r3, #1 8004d08: bf18 it ne 8004d0a: 2301 movne r3, #1 8004d0c: 2b00 cmp r3, #0 8004d0e: d094 beq.n 8004c3a 8004d10: e7f5 b.n 8004cfe 8004d12: 2302 movs r3, #2 8004d14: f880 3042 strb.w r3, [r0, #66] ; 0x42 8004d18: e79f b.n 8004c5a 8004d1a: 2302 movs r3, #2 8004d1c: f880 3041 strb.w r3, [r0, #65] ; 0x41 8004d20: e79b b.n 8004c5a 8004d22: 2302 movs r3, #2 8004d24: f880 3040 strb.w r3, [r0, #64] ; 0x40 8004d28: e797 b.n 8004c5a 8004d2a: 6c5a ldr r2, [r3, #68] ; 0x44 8004d2c: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8004d30: 645a str r2, [r3, #68] ; 0x44 8004d32: 6899 ldr r1, [r3, #8] 8004d34: 4a0a ldr r2, [pc, #40] ; (8004d60 ) 8004d36: 400a ands r2, r1 8004d38: 2a06 cmp r2, #6 8004d3a: d002 beq.n 8004d42 8004d3c: f5b2 3f80 cmp.w r2, #65536 ; 0x10000 8004d40: d1bd bne.n 8004cbe 8004d42: 2000 movs r0, #0 8004d44: 4770 bx lr 8004d46: 6c5a ldr r2, [r3, #68] ; 0x44 8004d48: f442 4200 orr.w r2, r2, #32768 ; 0x8000 8004d4c: 645a str r2, [r3, #68] ; 0x44 8004d4e: e7a4 b.n 8004c9a 8004d50: 2302 movs r3, #2 8004d52: f880 303e strb.w r3, [r0, #62] ; 0x3e 8004d56: e780 b.n 8004c5a 8004d58: 40012c00 .word 0x40012c00 8004d5c: 40000400 .word 0x40000400 8004d60: 00010007 .word 0x00010007 08004d64 : __HAL_LOCK(htim); 8004d64: f890 303c ldrb.w r3, [r0, #60] ; 0x3c 8004d68: 2b01 cmp r3, #1 8004d6a: f000 8088 beq.w 8004e7e 8004d6e: 4602 mov r2, r0 { 8004d70: b430 push {r4, r5} htim->State = HAL_TIM_STATE_BUSY; 8004d72: 2302 movs r3, #2 tmpsmcr = htim->Instance->SMCR; 8004d74: 6804 ldr r4, [r0, #0] htim->State = HAL_TIM_STATE_BUSY; 8004d76: f882 303d strb.w r3, [r2, #61] ; 0x3d __HAL_LOCK(htim); 8004d7a: 2001 movs r0, #1 8004d7c: f882 003c strb.w r0, [r2, #60] ; 0x3c tmpsmcr = htim->Instance->SMCR; 8004d80: 68a5 ldr r5, [r4, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8004d82: 4b5e ldr r3, [pc, #376] ; (8004efc ) 8004d84: 402b ands r3, r5 htim->Instance->SMCR = tmpsmcr; 8004d86: 60a3 str r3, [r4, #8] switch (sClockSourceConfig->ClockSource) 8004d88: 680b ldr r3, [r1, #0] 8004d8a: 2b70 cmp r3, #112 ; 0x70 8004d8c: f000 80a5 beq.w 8004eda 8004d90: d827 bhi.n 8004de2 8004d92: 2b50 cmp r3, #80 ; 0x50 8004d94: d075 beq.n 8004e82 8004d96: d93d bls.n 8004e14 8004d98: 2b60 cmp r3, #96 ; 0x60 8004d9a: d11a bne.n 8004dd2 { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8004d9c: 6a23 ldr r3, [r4, #32] TIM_TI2_ConfigInputStage(htim->Instance, 8004d9e: 6848 ldr r0, [r1, #4] 8004da0: 68cd ldr r5, [r1, #12] TIMx->CCER &= ~TIM_CCER_CC2E; 8004da2: f023 0310 bic.w r3, r3, #16 8004da6: 6223 str r3, [r4, #32] tmpccmr1 = TIMx->CCMR1; 8004da8: 69a1 ldr r1, [r4, #24] tmpccer = TIMx->CCER; 8004daa: 6a23 ldr r3, [r4, #32] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8004dac: f421 4170 bic.w r1, r1, #61440 ; 0xf000 tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8004db0: f023 03a0 bic.w r3, r3, #160 ; 0xa0 tmpccer |= (TIM_ICPolarity << 4U); 8004db4: ea43 1300 orr.w r3, r3, r0, lsl #4 tmpccmr1 |= (TIM_ICFilter << 12U); 8004db8: ea41 3105 orr.w r1, r1, r5, lsl #12 /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8004dbc: 61a1 str r1, [r4, #24] TIMx->CCER = tmpccer; 8004dbe: 6223 str r3, [r4, #32] static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8004dc0: 68a3 ldr r3, [r4, #8] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8004dc2: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 8004dc6: f023 0370 bic.w r3, r3, #112 ; 0x70 /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8004dca: f043 0367 orr.w r3, r3, #103 ; 0x67 HAL_StatusTypeDef status = HAL_OK; 8004dce: 2000 movs r0, #0 /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8004dd0: 60a3 str r3, [r4, #8] htim->State = HAL_TIM_STATE_READY; 8004dd2: 2101 movs r1, #1 __HAL_UNLOCK(htim); 8004dd4: 2300 movs r3, #0 htim->State = HAL_TIM_STATE_READY; 8004dd6: f882 103d strb.w r1, [r2, #61] ; 0x3d __HAL_UNLOCK(htim); 8004dda: f882 303c strb.w r3, [r2, #60] ; 0x3c } 8004dde: bc30 pop {r4, r5} 8004de0: 4770 bx lr switch (sClockSourceConfig->ClockSource) 8004de2: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8004de6: d067 beq.n 8004eb8 8004de8: d938 bls.n 8004e5c 8004dea: 4945 ldr r1, [pc, #276] ; (8004f00 ) 8004dec: 428b cmp r3, r1 8004dee: d006 beq.n 8004dfe 8004df0: d92d bls.n 8004e4e 8004df2: 4944 ldr r1, [pc, #272] ; (8004f04 ) 8004df4: 428b cmp r3, r1 8004df6: d002 beq.n 8004dfe 8004df8: 3130 adds r1, #48 ; 0x30 8004dfa: 428b cmp r3, r1 8004dfc: d1e9 bne.n 8004dd2 tmpsmcr = TIMx->SMCR; 8004dfe: 68a1 ldr r1, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 8004e00: f421 1140 bic.w r1, r1, #3145728 ; 0x300000 8004e04: f021 0170 bic.w r1, r1, #112 ; 0x70 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8004e08: 4319 orrs r1, r3 8004e0a: f041 0107 orr.w r1, r1, #7 HAL_StatusTypeDef status = HAL_OK; 8004e0e: 2000 movs r0, #0 TIMx->SMCR = tmpsmcr; 8004e10: 60a1 str r1, [r4, #8] } 8004e12: e7de b.n 8004dd2 switch (sClockSourceConfig->ClockSource) 8004e14: 2b40 cmp r3, #64 ; 0x40 8004e16: d126 bne.n 8004e66 TIM_TI1_ConfigInputStage(htim->Instance, 8004e18: 684b ldr r3, [r1, #4] 8004e1a: 68cd ldr r5, [r1, #12] tmpccer = TIMx->CCER; 8004e1c: 6a21 ldr r1, [r4, #32] tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8004e1e: f021 010a bic.w r1, r1, #10 tmpccer |= TIM_ICPolarity; 8004e22: 4319 orrs r1, r3 TIMx->CCER &= ~TIM_CCER_CC1E; 8004e24: 6a23 ldr r3, [r4, #32] 8004e26: f023 0301 bic.w r3, r3, #1 8004e2a: 6223 str r3, [r4, #32] tmpccmr1 = TIMx->CCMR1; 8004e2c: 69a3 ldr r3, [r4, #24] tmpccmr1 &= ~TIM_CCMR1_IC1F; 8004e2e: f023 03f0 bic.w r3, r3, #240 ; 0xf0 tmpccmr1 |= (TIM_ICFilter << 4U); 8004e32: ea43 1305 orr.w r3, r3, r5, lsl #4 TIMx->CCMR1 = tmpccmr1; 8004e36: 61a3 str r3, [r4, #24] TIMx->CCER = tmpccer; 8004e38: 6221 str r1, [r4, #32] tmpsmcr = TIMx->SMCR; 8004e3a: 68a3 ldr r3, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 8004e3c: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 8004e40: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8004e44: f043 0347 orr.w r3, r3, #71 ; 0x47 HAL_StatusTypeDef status = HAL_OK; 8004e48: 2000 movs r0, #0 TIMx->SMCR = tmpsmcr; 8004e4a: 60a3 str r3, [r4, #8] } 8004e4c: e7c1 b.n 8004dd2 switch (sClockSourceConfig->ClockSource) 8004e4e: f1b3 1f10 cmp.w r3, #1048592 ; 0x100010 8004e52: d0d4 beq.n 8004dfe 8004e54: 3910 subs r1, #16 8004e56: 428b cmp r3, r1 8004e58: d0d1 beq.n 8004dfe 8004e5a: e7ba b.n 8004dd2 HAL_StatusTypeDef status = HAL_OK; 8004e5c: f5b3 5080 subs.w r0, r3, #4096 ; 0x1000 8004e60: bf18 it ne 8004e62: 2001 movne r0, #1 8004e64: e7b5 b.n 8004dd2 switch (sClockSourceConfig->ClockSource) 8004e66: d8b4 bhi.n 8004dd2 8004e68: 2b20 cmp r3, #32 8004e6a: d0c8 beq.n 8004dfe 8004e6c: d903 bls.n 8004e76 8004e6e: 2b30 cmp r3, #48 ; 0x30 8004e70: d0c5 beq.n 8004dfe 8004e72: 2001 movs r0, #1 8004e74: e7ad b.n 8004dd2 8004e76: f033 0110 bics.w r1, r3, #16 8004e7a: d1aa bne.n 8004dd2 8004e7c: e7bf b.n 8004dfe __HAL_LOCK(htim); 8004e7e: 2002 movs r0, #2 } 8004e80: 4770 bx lr TIM_TI1_ConfigInputStage(htim->Instance, 8004e82: 684b ldr r3, [r1, #4] 8004e84: 68cd ldr r5, [r1, #12] tmpccer = TIMx->CCER; 8004e86: 6a21 ldr r1, [r4, #32] tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8004e88: f021 010a bic.w r1, r1, #10 tmpccer |= TIM_ICPolarity; 8004e8c: 4319 orrs r1, r3 TIMx->CCER &= ~TIM_CCER_CC1E; 8004e8e: 6a23 ldr r3, [r4, #32] 8004e90: f023 0301 bic.w r3, r3, #1 8004e94: 6223 str r3, [r4, #32] tmpccmr1 = TIMx->CCMR1; 8004e96: 69a3 ldr r3, [r4, #24] tmpccmr1 &= ~TIM_CCMR1_IC1F; 8004e98: f023 03f0 bic.w r3, r3, #240 ; 0xf0 tmpccmr1 |= (TIM_ICFilter << 4U); 8004e9c: ea43 1305 orr.w r3, r3, r5, lsl #4 TIMx->CCMR1 = tmpccmr1; 8004ea0: 61a3 str r3, [r4, #24] TIMx->CCER = tmpccer; 8004ea2: 6221 str r1, [r4, #32] tmpsmcr = TIMx->SMCR; 8004ea4: 68a3 ldr r3, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 8004ea6: f423 1340 bic.w r3, r3, #3145728 ; 0x300000 8004eaa: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8004eae: f043 0357 orr.w r3, r3, #87 ; 0x57 HAL_StatusTypeDef status = HAL_OK; 8004eb2: 2000 movs r0, #0 TIMx->SMCR = tmpsmcr; 8004eb4: 60a3 str r3, [r4, #8] } 8004eb6: e78c b.n 8004dd2 /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8004eb8: e9d1 5301 ldrd r5, r3, [r1, #4] tmpsmcr = TIMx->SMCR; 8004ebc: 68a0 ldr r0, [r4, #8] tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8004ebe: 432b orrs r3, r5 8004ec0: 68cd ldr r5, [r1, #12] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8004ec2: f420 417f bic.w r1, r0, #65280 ; 0xff00 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8004ec6: ea43 2305 orr.w r3, r3, r5, lsl #8 8004eca: 430b orrs r3, r1 /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8004ecc: 60a3 str r3, [r4, #8] htim->Instance->SMCR |= TIM_SMCR_ECE; 8004ece: 68a3 ldr r3, [r4, #8] 8004ed0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 HAL_StatusTypeDef status = HAL_OK; 8004ed4: 2000 movs r0, #0 htim->Instance->SMCR |= TIM_SMCR_ECE; 8004ed6: 60a3 str r3, [r4, #8] break; 8004ed8: e77b b.n 8004dd2 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8004eda: e9d1 5301 ldrd r5, r3, [r1, #4] tmpsmcr = TIMx->SMCR; 8004ede: 68a0 ldr r0, [r4, #8] tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8004ee0: 432b orrs r3, r5 8004ee2: 68cd ldr r5, [r1, #12] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8004ee4: f420 417f bic.w r1, r0, #65280 ; 0xff00 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8004ee8: ea43 2305 orr.w r3, r3, r5, lsl #8 8004eec: 430b orrs r3, r1 TIMx->SMCR = tmpsmcr; 8004eee: 60a3 str r3, [r4, #8] tmpsmcr = htim->Instance->SMCR; 8004ef0: 68a3 ldr r3, [r4, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8004ef2: f043 0377 orr.w r3, r3, #119 ; 0x77 HAL_StatusTypeDef status = HAL_OK; 8004ef6: 2000 movs r0, #0 htim->Instance->SMCR = tmpsmcr; 8004ef8: 60a3 str r3, [r4, #8] break; 8004efa: e76a b.n 8004dd2 8004efc: ffce0088 .word 0xffce0088 8004f00: 00100030 .word 0x00100030 8004f04: 00100040 .word 0x00100040 08004f08 : TIMx->CCER &= ~TIM_CCER_CC2E; 8004f08: 6a03 ldr r3, [r0, #32] 8004f0a: f023 0310 bic.w r3, r3, #16 8004f0e: 6203 str r3, [r0, #32] tmpccer = TIMx->CCER; 8004f10: 6a03 ldr r3, [r0, #32] { 8004f12: b470 push {r4, r5, r6} tmpcr2 = TIMx->CR2; 8004f14: 6844 ldr r4, [r0, #4] tmpccmrx = TIMx->CCMR1; 8004f16: 6982 ldr r2, [r0, #24] tmpccmrx |= (OC_Config->OCMode << 8U); 8004f18: 680d ldr r5, [r1, #0] tmpccmrx &= ~TIM_CCMR1_CC2S; 8004f1a: f022 7280 bic.w r2, r2, #16777216 ; 0x1000000 8004f1e: f422 42e6 bic.w r2, r2, #29440 ; 0x7300 tmpccmrx |= (OC_Config->OCMode << 8U); 8004f22: ea42 2205 orr.w r2, r2, r5, lsl #8 tmpccer |= (OC_Config->OCPolarity << 4U); 8004f26: 688d ldr r5, [r1, #8] tmpccer &= ~TIM_CCER_CC2P; 8004f28: f023 0320 bic.w r3, r3, #32 tmpccer |= (OC_Config->OCPolarity << 4U); 8004f2c: ea43 1305 orr.w r3, r3, r5, lsl #4 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8004f30: 4d14 ldr r5, [pc, #80] ; (8004f84 ) 8004f32: 42a8 cmp r0, r5 8004f34: d010 beq.n 8004f58 8004f36: f505 6500 add.w r5, r5, #2048 ; 0x800 8004f3a: 42a8 cmp r0, r5 8004f3c: d00c beq.n 8004f58 if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004f3e: f505 6540 add.w r5, r5, #3072 ; 0xc00 8004f42: 42a8 cmp r0, r5 8004f44: d00f beq.n 8004f66 8004f46: f505 6580 add.w r5, r5, #1024 ; 0x400 8004f4a: 42a8 cmp r0, r5 8004f4c: d00b beq.n 8004f66 8004f4e: f505 6580 add.w r5, r5, #1024 ; 0x400 8004f52: 42a8 cmp r0, r5 8004f54: d10f bne.n 8004f76 8004f56: e006 b.n 8004f66 tmpccer |= (OC_Config->OCNPolarity << 4U); 8004f58: 68cd ldr r5, [r1, #12] tmpccer &= ~TIM_CCER_CC2NP; 8004f5a: f023 0380 bic.w r3, r3, #128 ; 0x80 tmpccer |= (OC_Config->OCNPolarity << 4U); 8004f5e: ea43 1305 orr.w r3, r3, r5, lsl #4 tmpccer &= ~TIM_CCER_CC2NE; 8004f62: f023 0340 bic.w r3, r3, #64 ; 0x40 tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8004f66: e9d1 6505 ldrd r6, r5, [r1, #20] tmpcr2 &= ~TIM_CR2_OIS2N; 8004f6a: f424 6440 bic.w r4, r4, #3072 ; 0xc00 tmpcr2 |= (OC_Config->OCNIdleState << 2U); 8004f6e: ea46 0c05 orr.w ip, r6, r5 8004f72: ea44 048c orr.w r4, r4, ip, lsl #2 TIMx->CCR2 = OC_Config->Pulse; 8004f76: 6849 ldr r1, [r1, #4] TIMx->CR2 = tmpcr2; 8004f78: 6044 str r4, [r0, #4] TIMx->CCMR1 = tmpccmrx; 8004f7a: 6182 str r2, [r0, #24] } 8004f7c: bc70 pop {r4, r5, r6} TIMx->CCR2 = OC_Config->Pulse; 8004f7e: 6381 str r1, [r0, #56] ; 0x38 TIMx->CCER = tmpccer; 8004f80: 6203 str r3, [r0, #32] } 8004f82: 4770 bx lr 8004f84: 40012c00 .word 0x40012c00 08004f88 : __HAL_LOCK(htim); 8004f88: f890 303c ldrb.w r3, [r0, #60] ; 0x3c 8004f8c: 2b01 cmp r3, #1 8004f8e: f000 80f7 beq.w 8005180 8004f92: 2301 movs r3, #1 { 8004f94: b570 push {r4, r5, r6, lr} 8004f96: 4604 mov r4, r0 8004f98: 460d mov r5, r1 __HAL_LOCK(htim); 8004f9a: f880 303c strb.w r3, [r0, #60] ; 0x3c switch (Channel) 8004f9e: 2a14 cmp r2, #20 8004fa0: d80c bhi.n 8004fbc 8004fa2: e8df f002 tbb [pc, r2] 8004fa6: 0b55 .short 0x0b55 8004fa8: 0b6a0b0b .word 0x0b6a0b0b 8004fac: 0b800b0b .word 0x0b800b0b 8004fb0: 0b950b0b .word 0x0b950b0b 8004fb4: 0bab0b0b .word 0x0bab0b0b 8004fb8: 0b0b .short 0x0b0b 8004fba: 11 .byte 0x11 8004fbb: 00 .byte 0x00 __HAL_UNLOCK(htim); 8004fbc: 2200 movs r2, #0 switch (Channel) 8004fbe: 2301 movs r3, #1 __HAL_UNLOCK(htim); 8004fc0: f884 203c strb.w r2, [r4, #60] ; 0x3c } 8004fc4: 4618 mov r0, r3 8004fc6: bd70 pop {r4, r5, r6, pc} TIM_OC6_SetConfig(htim->Instance, sConfig); 8004fc8: 6802 ldr r2, [r0, #0] tmpccmrx |= (OC_Config->OCMode << 8U); 8004fca: 682e ldr r6, [r5, #0] TIMx->CCER &= ~TIM_CCER_CC6E; 8004fcc: 6a13 ldr r3, [r2, #32] 8004fce: f423 1380 bic.w r3, r3, #1048576 ; 0x100000 8004fd2: 6213 str r3, [r2, #32] tmpccer = TIMx->CCER; 8004fd4: 6a13 ldr r3, [r2, #32] tmpcr2 = TIMx->CR2; 8004fd6: 6850 ldr r0, [r2, #4] tmpccmrx = TIMx->CCMR3; 8004fd8: 6d11 ldr r1, [r2, #80] ; 0x50 tmpccmrx &= ~(TIM_CCMR3_OC6M); 8004fda: f021 7180 bic.w r1, r1, #16777216 ; 0x1000000 8004fde: f421 41e0 bic.w r1, r1, #28672 ; 0x7000 tmpccmrx |= (OC_Config->OCMode << 8U); 8004fe2: ea41 2106 orr.w r1, r1, r6, lsl #8 tmpccer |= (OC_Config->OCPolarity << 20U); 8004fe6: 68ae ldr r6, [r5, #8] tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8004fe8: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 tmpccer |= (OC_Config->OCPolarity << 20U); 8004fec: ea43 5306 orr.w r3, r3, r6, lsl #20 if (IS_TIM_BREAK_INSTANCE(TIMx)) 8004ff0: 4e65 ldr r6, [pc, #404] ; (8005188 ) 8004ff2: 42b2 cmp r2, r6 8004ff4: d00f beq.n 8005016 8004ff6: f506 6600 add.w r6, r6, #2048 ; 0x800 8004ffa: 42b2 cmp r2, r6 8004ffc: d00b beq.n 8005016 8004ffe: f506 6640 add.w r6, r6, #3072 ; 0xc00 8005002: 42b2 cmp r2, r6 8005004: d007 beq.n 8005016 8005006: f506 6680 add.w r6, r6, #1024 ; 0x400 800500a: 42b2 cmp r2, r6 800500c: d003 beq.n 8005016 800500e: f506 6680 add.w r6, r6, #1024 ; 0x400 8005012: 42b2 cmp r2, r6 8005014: d104 bne.n 8005020 tmpcr2 |= (OC_Config->OCIdleState << 10U); 8005016: 696e ldr r6, [r5, #20] tmpcr2 &= ~TIM_CR2_OIS6; 8005018: f420 2080 bic.w r0, r0, #262144 ; 0x40000 tmpcr2 |= (OC_Config->OCIdleState << 10U); 800501c: ea40 2086 orr.w r0, r0, r6, lsl #10 TIMx->CR2 = tmpcr2; 8005020: 6050 str r0, [r2, #4] TIMx->CCMR3 = tmpccmrx; 8005022: 6511 str r1, [r2, #80] ; 0x50 TIMx->CCR6 = OC_Config->Pulse; 8005024: 6869 ldr r1, [r5, #4] 8005026: 64d1 str r1, [r2, #76] ; 0x4c TIMx->CCER = tmpccer; 8005028: 6213 str r3, [r2, #32] htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800502a: 6d13 ldr r3, [r2, #80] ; 0x50 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800502c: 6928 ldr r0, [r5, #16] htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800502e: f443 6300 orr.w r3, r3, #2048 ; 0x800 8005032: 6513 str r3, [r2, #80] ; 0x50 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 8005034: 6d11 ldr r1, [r2, #80] ; 0x50 8005036: f421 6180 bic.w r1, r1, #1024 ; 0x400 800503a: 6511 str r1, [r2, #80] ; 0x50 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800503c: 6d11 ldr r1, [r2, #80] ; 0x50 800503e: ea41 2100 orr.w r1, r1, r0, lsl #8 8005042: 6511 str r1, [r2, #80] ; 0x50 __HAL_UNLOCK(htim); 8005044: 2200 movs r2, #0 HAL_StatusTypeDef status = HAL_OK; 8005046: 2300 movs r3, #0 __HAL_UNLOCK(htim); 8005048: f884 203c strb.w r2, [r4, #60] ; 0x3c } 800504c: 4618 mov r0, r3 800504e: bd70 pop {r4, r5, r6, pc} TIM_OC1_SetConfig(htim->Instance, sConfig); 8005050: 6800 ldr r0, [r0, #0] 8005052: f7ff fbd9 bl 8004808 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8005056: 6983 ldr r3, [r0, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8005058: 6929 ldr r1, [r5, #16] htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800505a: f043 0308 orr.w r3, r3, #8 800505e: 6183 str r3, [r0, #24] htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8005060: 6982 ldr r2, [r0, #24] 8005062: f022 0204 bic.w r2, r2, #4 8005066: 6182 str r2, [r0, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8005068: 6982 ldr r2, [r0, #24] 800506a: 430a orrs r2, r1 800506c: 6182 str r2, [r0, #24] __HAL_UNLOCK(htim); 800506e: 2200 movs r2, #0 HAL_StatusTypeDef status = HAL_OK; 8005070: 2300 movs r3, #0 __HAL_UNLOCK(htim); 8005072: f884 203c strb.w r2, [r4, #60] ; 0x3c } 8005076: 4618 mov r0, r3 8005078: bd70 pop {r4, r5, r6, pc} TIM_OC2_SetConfig(htim->Instance, sConfig); 800507a: 6800 ldr r0, [r0, #0] 800507c: f7ff ff44 bl 8004f08 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8005080: 6983 ldr r3, [r0, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8005082: 6929 ldr r1, [r5, #16] htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8005084: f443 6300 orr.w r3, r3, #2048 ; 0x800 8005088: 6183 str r3, [r0, #24] htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800508a: 6982 ldr r2, [r0, #24] 800508c: f422 6280 bic.w r2, r2, #1024 ; 0x400 8005090: 6182 str r2, [r0, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8005092: 6982 ldr r2, [r0, #24] 8005094: ea42 2201 orr.w r2, r2, r1, lsl #8 8005098: 6182 str r2, [r0, #24] __HAL_UNLOCK(htim); 800509a: 2200 movs r2, #0 HAL_StatusTypeDef status = HAL_OK; 800509c: 2300 movs r3, #0 __HAL_UNLOCK(htim); 800509e: f884 203c strb.w r2, [r4, #60] ; 0x3c } 80050a2: 4618 mov r0, r3 80050a4: bd70 pop {r4, r5, r6, pc} TIM_OC3_SetConfig(htim->Instance, sConfig); 80050a6: 6800 ldr r0, [r0, #0] 80050a8: f7ff fbea bl 8004880 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80050ac: 69c3 ldr r3, [r0, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80050ae: 6929 ldr r1, [r5, #16] htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 80050b0: f043 0308 orr.w r3, r3, #8 80050b4: 61c3 str r3, [r0, #28] htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 80050b6: 69c2 ldr r2, [r0, #28] 80050b8: f022 0204 bic.w r2, r2, #4 80050bc: 61c2 str r2, [r0, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 80050be: 69c2 ldr r2, [r0, #28] 80050c0: 430a orrs r2, r1 80050c2: 61c2 str r2, [r0, #28] __HAL_UNLOCK(htim); 80050c4: 2200 movs r2, #0 HAL_StatusTypeDef status = HAL_OK; 80050c6: 2300 movs r3, #0 __HAL_UNLOCK(htim); 80050c8: f884 203c strb.w r2, [r4, #60] ; 0x3c } 80050cc: 4618 mov r0, r3 80050ce: bd70 pop {r4, r5, r6, pc} TIM_OC4_SetConfig(htim->Instance, sConfig); 80050d0: 6800 ldr r0, [r0, #0] 80050d2: f7ff fc15 bl 8004900 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80050d6: 69c3 ldr r3, [r0, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80050d8: 6929 ldr r1, [r5, #16] htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80050da: f443 6300 orr.w r3, r3, #2048 ; 0x800 80050de: 61c3 str r3, [r0, #28] htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80050e0: 69c2 ldr r2, [r0, #28] 80050e2: f422 6280 bic.w r2, r2, #1024 ; 0x400 80050e6: 61c2 str r2, [r0, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80050e8: 69c2 ldr r2, [r0, #28] 80050ea: ea42 2201 orr.w r2, r2, r1, lsl #8 80050ee: 61c2 str r2, [r0, #28] __HAL_UNLOCK(htim); 80050f0: 2200 movs r2, #0 HAL_StatusTypeDef status = HAL_OK; 80050f2: 2300 movs r3, #0 __HAL_UNLOCK(htim); 80050f4: f884 203c strb.w r2, [r4, #60] ; 0x3c } 80050f8: 4618 mov r0, r3 80050fa: bd70 pop {r4, r5, r6, pc} TIM_OC5_SetConfig(htim->Instance, sConfig); 80050fc: 6802 ldr r2, [r0, #0] tmpccmrx |= OC_Config->OCMode; 80050fe: 682e ldr r6, [r5, #0] TIMx->CCER &= ~TIM_CCER_CC5E; 8005100: 6a13 ldr r3, [r2, #32] 8005102: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8005106: 6213 str r3, [r2, #32] tmpccer = TIMx->CCER; 8005108: 6a13 ldr r3, [r2, #32] tmpcr2 = TIMx->CR2; 800510a: 6850 ldr r0, [r2, #4] tmpccmrx = TIMx->CCMR3; 800510c: 6d11 ldr r1, [r2, #80] ; 0x50 tmpccmrx &= ~(TIM_CCMR3_OC5M); 800510e: f421 3180 bic.w r1, r1, #65536 ; 0x10000 8005112: f021 0170 bic.w r1, r1, #112 ; 0x70 tmpccmrx |= OC_Config->OCMode; 8005116: 4331 orrs r1, r6 tmpccer |= (OC_Config->OCPolarity << 16U); 8005118: 68ae ldr r6, [r5, #8] tmpccer &= ~TIM_CCER_CC5P; 800511a: f423 3300 bic.w r3, r3, #131072 ; 0x20000 tmpccer |= (OC_Config->OCPolarity << 16U); 800511e: ea43 4306 orr.w r3, r3, r6, lsl #16 if (IS_TIM_BREAK_INSTANCE(TIMx)) 8005122: 4e19 ldr r6, [pc, #100] ; (8005188 ) 8005124: 42b2 cmp r2, r6 8005126: d00f beq.n 8005148 8005128: f506 6600 add.w r6, r6, #2048 ; 0x800 800512c: 42b2 cmp r2, r6 800512e: d00b beq.n 8005148 8005130: f506 6640 add.w r6, r6, #3072 ; 0xc00 8005134: 42b2 cmp r2, r6 8005136: d007 beq.n 8005148 8005138: f506 6680 add.w r6, r6, #1024 ; 0x400 800513c: 42b2 cmp r2, r6 800513e: d003 beq.n 8005148 8005140: f506 6680 add.w r6, r6, #1024 ; 0x400 8005144: 42b2 cmp r2, r6 8005146: d104 bne.n 8005152 tmpcr2 |= (OC_Config->OCIdleState << 8U); 8005148: 696e ldr r6, [r5, #20] tmpcr2 &= ~TIM_CR2_OIS5; 800514a: f420 3080 bic.w r0, r0, #65536 ; 0x10000 tmpcr2 |= (OC_Config->OCIdleState << 8U); 800514e: ea40 2006 orr.w r0, r0, r6, lsl #8 TIMx->CR2 = tmpcr2; 8005152: 6050 str r0, [r2, #4] TIMx->CCMR3 = tmpccmrx; 8005154: 6511 str r1, [r2, #80] ; 0x50 TIMx->CCR5 = OC_Config->Pulse; 8005156: 6869 ldr r1, [r5, #4] 8005158: 6491 str r1, [r2, #72] ; 0x48 TIMx->CCER = tmpccer; 800515a: 6213 str r3, [r2, #32] htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800515c: 6d13 ldr r3, [r2, #80] ; 0x50 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800515e: 6928 ldr r0, [r5, #16] htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 8005160: f043 0308 orr.w r3, r3, #8 8005164: 6513 str r3, [r2, #80] ; 0x50 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 8005166: 6d11 ldr r1, [r2, #80] ; 0x50 8005168: f021 0104 bic.w r1, r1, #4 800516c: 6511 str r1, [r2, #80] ; 0x50 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800516e: 6d11 ldr r1, [r2, #80] ; 0x50 8005170: 4301 orrs r1, r0 8005172: 6511 str r1, [r2, #80] ; 0x50 __HAL_UNLOCK(htim); 8005174: 2200 movs r2, #0 HAL_StatusTypeDef status = HAL_OK; 8005176: 2300 movs r3, #0 __HAL_UNLOCK(htim); 8005178: f884 203c strb.w r2, [r4, #60] ; 0x3c } 800517c: 4618 mov r0, r3 800517e: bd70 pop {r4, r5, r6, pc} __HAL_LOCK(htim); 8005180: 2302 movs r3, #2 } 8005182: 4618 mov r0, r3 8005184: 4770 bx lr 8005186: bf00 nop 8005188: 40012c00 .word 0x40012c00 0800518c : assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800518c: f890 303c ldrb.w r3, [r0, #60] ; 0x3c 8005190: 2b01 cmp r3, #1 8005192: d03e beq.n 8005212 { 8005194: b470 push {r4, r5, r6} /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005196: 6802 ldr r2, [r0, #0] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 8005198: 4d1f ldr r5, [pc, #124] ; (8005218 ) htim->State = HAL_TIM_STATE_BUSY; 800519a: 2302 movs r3, #2 800519c: f880 303d strb.w r3, [r0, #61] ; 0x3d if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80051a0: 42aa cmp r2, r5 tmpcr2 = htim->Instance->CR2; 80051a2: 6853 ldr r3, [r2, #4] tmpsmcr = htim->Instance->SMCR; 80051a4: 6894 ldr r4, [r2, #8] if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80051a6: d028 beq.n 80051fa 80051a8: f505 6500 add.w r5, r5, #2048 ; 0x800 80051ac: 42aa cmp r2, r5 80051ae: d024 beq.n 80051fa } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80051b0: 680e ldr r6, [r1, #0] tmpcr2 &= ~TIM_CR2_MMS; 80051b2: f023 7300 bic.w r3, r3, #33554432 ; 0x2000000 80051b6: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80051ba: 4333 orrs r3, r6 /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80051bc: f1b2 4f80 cmp.w r2, #1073741824 ; 0x40000000 htim->Instance->CR2 = tmpcr2; 80051c0: 6053 str r3, [r2, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80051c2: d00c beq.n 80051de 80051c4: 4b15 ldr r3, [pc, #84] ; (800521c ) 80051c6: 429a cmp r2, r3 80051c8: d009 beq.n 80051de 80051ca: f503 6380 add.w r3, r3, #1024 ; 0x400 80051ce: 429a cmp r2, r3 80051d0: d005 beq.n 80051de 80051d2: 42aa cmp r2, r5 80051d4: d003 beq.n 80051de 80051d6: f503 339c add.w r3, r3, #79872 ; 0x13800 80051da: 429a cmp r2, r3 80051dc: d104 bne.n 80051e8 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80051de: 688b ldr r3, [r1, #8] tmpsmcr &= ~TIM_SMCR_MSM; 80051e0: f024 0480 bic.w r4, r4, #128 ; 0x80 tmpsmcr |= sMasterConfig->MasterSlaveMode; 80051e4: 431c orrs r4, r3 /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80051e6: 6094 str r4, [r2, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); 80051e8: 2300 movs r3, #0 htim->State = HAL_TIM_STATE_READY; 80051ea: 2201 movs r2, #1 80051ec: f880 203d strb.w r2, [r0, #61] ; 0x3d __HAL_UNLOCK(htim); 80051f0: f880 303c strb.w r3, [r0, #60] ; 0x3c return HAL_OK; } 80051f4: bc70 pop {r4, r5, r6} return HAL_OK; 80051f6: 4618 mov r0, r3 } 80051f8: 4770 bx lr tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 80051fa: 684d ldr r5, [r1, #4] tmpcr2 &= ~TIM_CR2_MMS2; 80051fc: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8005200: 432b orrs r3, r5 tmpcr2 &= ~TIM_CR2_MMS; 8005202: f023 7300 bic.w r3, r3, #33554432 ; 0x2000000 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005206: 680d ldr r5, [r1, #0] tmpcr2 &= ~TIM_CR2_MMS; 8005208: f023 0370 bic.w r3, r3, #112 ; 0x70 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800520c: 432b orrs r3, r5 htim->Instance->CR2 = tmpcr2; 800520e: 6053 str r3, [r2, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005210: e7e5 b.n 80051de __HAL_LOCK(htim); 8005212: 2002 movs r0, #2 } 8005214: 4770 bx lr 8005216: bf00 nop 8005218: 40012c00 .word 0x40012c00 800521c: 40000400 .word 0x40000400 08005220 : assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); /* Check input state */ __HAL_LOCK(htim); 8005220: f890 303c ldrb.w r3, [r0, #60] ; 0x3c 8005224: 2b01 cmp r3, #1 8005226: d045 beq.n 80052b4 { 8005228: b410 push {r4} /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 800522a: e9d1 4302 ldrd r4, r3, [r1, #8] 800522e: f423 7340 bic.w r3, r3, #768 ; 0x300 8005232: 4602 mov r2, r0 8005234: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 8005236: 6848 ldr r0, [r1, #4] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 8005238: 680c ldr r4, [r1, #0] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 800523a: f423 6380 bic.w r3, r3, #1024 ; 0x400 800523e: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 8005240: f423 6300 bic.w r3, r3, #2048 ; 0x800 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 8005244: 6908 ldr r0, [r1, #16] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 8005246: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 8005248: f423 5380 bic.w r3, r3, #4096 ; 0x1000 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 800524c: 694c ldr r4, [r1, #20] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 800524e: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 8005250: f423 5300 bic.w r3, r3, #8192 ; 0x2000 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8005254: 6b08 ldr r0, [r1, #48] ; 0x30 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 8005256: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8005258: f423 4380 bic.w r3, r3, #16384 ; 0x4000 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 800525c: 698c ldr r4, [r1, #24] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 800525e: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8005260: f423 2370 bic.w r3, r3, #983040 ; 0xf0000 if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) 8005264: 6810 ldr r0, [r2, #0] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8005266: ea43 4304 orr.w r3, r3, r4, lsl #16 if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) 800526a: 4c13 ldr r4, [pc, #76] ; (80052b8 ) 800526c: 42a0 cmp r0, r4 800526e: d00b beq.n 8005288 8005270: f504 6400 add.w r4, r4, #2048 ; 0x800 8005274: 42a0 cmp r0, r4 8005276: d007 beq.n 8005288 } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; __HAL_UNLOCK(htim); 8005278: 2100 movs r1, #0 htim->Instance->BDTR = tmpbdtr; 800527a: 6443 str r3, [r0, #68] ; 0x44 __HAL_UNLOCK(htim); 800527c: f882 103c strb.w r1, [r2, #60] ; 0x3c return HAL_OK; 8005280: 4608 mov r0, r1 } 8005282: f85d 4b04 ldr.w r4, [sp], #4 8005286: 4770 bx lr MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); 8005288: 69cc ldr r4, [r1, #28] 800528a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800528e: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 8005290: 6a8c ldr r4, [r1, #40] ; 0x28 8005292: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000 8005296: ea43 5304 orr.w r3, r3, r4, lsl #20 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 800529a: 6a0c ldr r4, [r1, #32] 800529c: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 80052a0: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 80052a2: 6a4c ldr r4, [r1, #36] ; 0x24 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); 80052a4: 6ac9 ldr r1, [r1, #44] ; 0x2c MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 80052a6: f023 7300 bic.w r3, r3, #33554432 ; 0x2000000 80052aa: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); 80052ac: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 80052b0: 430b orrs r3, r1 80052b2: e7e1 b.n 8005278 __HAL_LOCK(htim); 80052b4: 2002 movs r0, #2 } 80052b6: 4770 bx lr 80052b8: 40012c00 .word 0x40012c00 80052bc: 00000000 .word 0x00000000 080052c0 : 80052c0: b51f push {r0, r1, r2, r3, r4, lr} 80052c2: ec53 2b10 vmov r2, r3, d0 80052c6: 4816 ldr r0, [pc, #88] ; (8005320 ) 80052c8: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000 80052cc: 4281 cmp r1, r0 80052ce: dc07 bgt.n 80052e0 80052d0: ed9f 1b11 vldr d1, [pc, #68] ; 8005318 80052d4: 2001 movs r0, #1 80052d6: b005 add sp, #20 80052d8: f85d eb04 ldr.w lr, [sp], #4 80052dc: f000 bd7c b.w 8005dd8 <__kernel_tan> 80052e0: 4810 ldr r0, [pc, #64] ; (8005324 ) 80052e2: 4281 cmp r1, r0 80052e4: dd09 ble.n 80052fa 80052e6: ee10 0a10 vmov r0, s0 80052ea: 4619 mov r1, r3 80052ec: f7fa ff98 bl 8000220 <__aeabi_dsub> 80052f0: ec41 0b10 vmov d0, r0, r1 80052f4: b005 add sp, #20 80052f6: f85d fb04 ldr.w pc, [sp], #4 80052fa: 4668 mov r0, sp 80052fc: f000 f814 bl 8005328 <__ieee754_rem_pio2> 8005300: 0040 lsls r0, r0, #1 8005302: f000 0002 and.w r0, r0, #2 8005306: ed9d 1b02 vldr d1, [sp, #8] 800530a: ed9d 0b00 vldr d0, [sp] 800530e: f1c0 0001 rsb r0, r0, #1 8005312: f000 fd61 bl 8005dd8 <__kernel_tan> 8005316: e7ed b.n 80052f4 ... 8005320: 3fe921fb .word 0x3fe921fb 8005324: 7fefffff .word 0x7fefffff 08005328 <__ieee754_rem_pio2>: 8005328: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800532c: ed2d 8b02 vpush {d8} 8005330: ec55 4b10 vmov r4, r5, d0 8005334: 4bca ldr r3, [pc, #808] ; (8005660 <__ieee754_rem_pio2+0x338>) 8005336: b08b sub sp, #44 ; 0x2c 8005338: f025 4800 bic.w r8, r5, #2147483648 ; 0x80000000 800533c: 4598 cmp r8, r3 800533e: 4682 mov sl, r0 8005340: 9502 str r5, [sp, #8] 8005342: dc08 bgt.n 8005356 <__ieee754_rem_pio2+0x2e> 8005344: 2200 movs r2, #0 8005346: 2300 movs r3, #0 8005348: ed80 0b00 vstr d0, [r0] 800534c: e9c0 2302 strd r2, r3, [r0, #8] 8005350: f04f 0b00 mov.w fp, #0 8005354: e028 b.n 80053a8 <__ieee754_rem_pio2+0x80> 8005356: 4bc3 ldr r3, [pc, #780] ; (8005664 <__ieee754_rem_pio2+0x33c>) 8005358: 4598 cmp r8, r3 800535a: dc78 bgt.n 800544e <__ieee754_rem_pio2+0x126> 800535c: 9b02 ldr r3, [sp, #8] 800535e: 4ec2 ldr r6, [pc, #776] ; (8005668 <__ieee754_rem_pio2+0x340>) 8005360: 2b00 cmp r3, #0 8005362: ee10 0a10 vmov r0, s0 8005366: a3b0 add r3, pc, #704 ; (adr r3, 8005628 <__ieee754_rem_pio2+0x300>) 8005368: e9d3 2300 ldrd r2, r3, [r3] 800536c: 4629 mov r1, r5 800536e: dd39 ble.n 80053e4 <__ieee754_rem_pio2+0xbc> 8005370: f7fa ff56 bl 8000220 <__aeabi_dsub> 8005374: 45b0 cmp r8, r6 8005376: 4604 mov r4, r0 8005378: 460d mov r5, r1 800537a: d01b beq.n 80053b4 <__ieee754_rem_pio2+0x8c> 800537c: a3ac add r3, pc, #688 ; (adr r3, 8005630 <__ieee754_rem_pio2+0x308>) 800537e: e9d3 2300 ldrd r2, r3, [r3] 8005382: f7fa ff4d bl 8000220 <__aeabi_dsub> 8005386: 4602 mov r2, r0 8005388: 460b mov r3, r1 800538a: e9ca 2300 strd r2, r3, [sl] 800538e: 4620 mov r0, r4 8005390: 4629 mov r1, r5 8005392: f7fa ff45 bl 8000220 <__aeabi_dsub> 8005396: a3a6 add r3, pc, #664 ; (adr r3, 8005630 <__ieee754_rem_pio2+0x308>) 8005398: e9d3 2300 ldrd r2, r3, [r3] 800539c: f7fa ff40 bl 8000220 <__aeabi_dsub> 80053a0: e9ca 0102 strd r0, r1, [sl, #8] 80053a4: f04f 0b01 mov.w fp, #1 80053a8: 4658 mov r0, fp 80053aa: b00b add sp, #44 ; 0x2c 80053ac: ecbd 8b02 vpop {d8} 80053b0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80053b4: a3a0 add r3, pc, #640 ; (adr r3, 8005638 <__ieee754_rem_pio2+0x310>) 80053b6: e9d3 2300 ldrd r2, r3, [r3] 80053ba: f7fa ff31 bl 8000220 <__aeabi_dsub> 80053be: a3a0 add r3, pc, #640 ; (adr r3, 8005640 <__ieee754_rem_pio2+0x318>) 80053c0: e9d3 2300 ldrd r2, r3, [r3] 80053c4: 4604 mov r4, r0 80053c6: 460d mov r5, r1 80053c8: f7fa ff2a bl 8000220 <__aeabi_dsub> 80053cc: 4602 mov r2, r0 80053ce: 460b mov r3, r1 80053d0: e9ca 2300 strd r2, r3, [sl] 80053d4: 4620 mov r0, r4 80053d6: 4629 mov r1, r5 80053d8: f7fa ff22 bl 8000220 <__aeabi_dsub> 80053dc: a398 add r3, pc, #608 ; (adr r3, 8005640 <__ieee754_rem_pio2+0x318>) 80053de: e9d3 2300 ldrd r2, r3, [r3] 80053e2: e7db b.n 800539c <__ieee754_rem_pio2+0x74> 80053e4: f7fa ff1e bl 8000224 <__adddf3> 80053e8: 45b0 cmp r8, r6 80053ea: 4604 mov r4, r0 80053ec: 460d mov r5, r1 80053ee: d016 beq.n 800541e <__ieee754_rem_pio2+0xf6> 80053f0: a38f add r3, pc, #572 ; (adr r3, 8005630 <__ieee754_rem_pio2+0x308>) 80053f2: e9d3 2300 ldrd r2, r3, [r3] 80053f6: f7fa ff15 bl 8000224 <__adddf3> 80053fa: 4602 mov r2, r0 80053fc: 460b mov r3, r1 80053fe: e9ca 2300 strd r2, r3, [sl] 8005402: 4620 mov r0, r4 8005404: 4629 mov r1, r5 8005406: f7fa ff0b bl 8000220 <__aeabi_dsub> 800540a: a389 add r3, pc, #548 ; (adr r3, 8005630 <__ieee754_rem_pio2+0x308>) 800540c: e9d3 2300 ldrd r2, r3, [r3] 8005410: f7fa ff08 bl 8000224 <__adddf3> 8005414: f04f 3bff mov.w fp, #4294967295 ; 0xffffffff 8005418: e9ca 0102 strd r0, r1, [sl, #8] 800541c: e7c4 b.n 80053a8 <__ieee754_rem_pio2+0x80> 800541e: a386 add r3, pc, #536 ; (adr r3, 8005638 <__ieee754_rem_pio2+0x310>) 8005420: e9d3 2300 ldrd r2, r3, [r3] 8005424: f7fa fefe bl 8000224 <__adddf3> 8005428: a385 add r3, pc, #532 ; (adr r3, 8005640 <__ieee754_rem_pio2+0x318>) 800542a: e9d3 2300 ldrd r2, r3, [r3] 800542e: 4604 mov r4, r0 8005430: 460d mov r5, r1 8005432: f7fa fef7 bl 8000224 <__adddf3> 8005436: 4602 mov r2, r0 8005438: 460b mov r3, r1 800543a: e9ca 2300 strd r2, r3, [sl] 800543e: 4620 mov r0, r4 8005440: 4629 mov r1, r5 8005442: f7fa feed bl 8000220 <__aeabi_dsub> 8005446: a37e add r3, pc, #504 ; (adr r3, 8005640 <__ieee754_rem_pio2+0x318>) 8005448: e9d3 2300 ldrd r2, r3, [r3] 800544c: e7e0 b.n 8005410 <__ieee754_rem_pio2+0xe8> 800544e: 4b87 ldr r3, [pc, #540] ; (800566c <__ieee754_rem_pio2+0x344>) 8005450: 4598 cmp r8, r3 8005452: f300 80d8 bgt.w 8005606 <__ieee754_rem_pio2+0x2de> 8005456: f000 fec9 bl 80061ec 800545a: ec55 4b10 vmov r4, r5, d0 800545e: ee10 0a10 vmov r0, s0 8005462: a379 add r3, pc, #484 ; (adr r3, 8005648 <__ieee754_rem_pio2+0x320>) 8005464: e9d3 2300 ldrd r2, r3, [r3] 8005468: 4629 mov r1, r5 800546a: f7fb f891 bl 8000590 <__aeabi_dmul> 800546e: 4b80 ldr r3, [pc, #512] ; (8005670 <__ieee754_rem_pio2+0x348>) 8005470: 2200 movs r2, #0 8005472: f7fa fed7 bl 8000224 <__adddf3> 8005476: f7fb fb25 bl 8000ac4 <__aeabi_d2iz> 800547a: 4683 mov fp, r0 800547c: f7fb f81e bl 80004bc <__aeabi_i2d> 8005480: 4602 mov r2, r0 8005482: 460b mov r3, r1 8005484: ec43 2b18 vmov d8, r2, r3 8005488: a367 add r3, pc, #412 ; (adr r3, 8005628 <__ieee754_rem_pio2+0x300>) 800548a: e9d3 2300 ldrd r2, r3, [r3] 800548e: f7fb f87f bl 8000590 <__aeabi_dmul> 8005492: 4602 mov r2, r0 8005494: 460b mov r3, r1 8005496: 4620 mov r0, r4 8005498: 4629 mov r1, r5 800549a: f7fa fec1 bl 8000220 <__aeabi_dsub> 800549e: a364 add r3, pc, #400 ; (adr r3, 8005630 <__ieee754_rem_pio2+0x308>) 80054a0: e9d3 2300 ldrd r2, r3, [r3] 80054a4: 4606 mov r6, r0 80054a6: 460f mov r7, r1 80054a8: ec51 0b18 vmov r0, r1, d8 80054ac: f7fb f870 bl 8000590 <__aeabi_dmul> 80054b0: f1bb 0f1f cmp.w fp, #31 80054b4: 4604 mov r4, r0 80054b6: 460d mov r5, r1 80054b8: dc0d bgt.n 80054d6 <__ieee754_rem_pio2+0x1ae> 80054ba: 4b6e ldr r3, [pc, #440] ; (8005674 <__ieee754_rem_pio2+0x34c>) 80054bc: f10b 32ff add.w r2, fp, #4294967295 ; 0xffffffff 80054c0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 80054c4: 4543 cmp r3, r8 80054c6: d006 beq.n 80054d6 <__ieee754_rem_pio2+0x1ae> 80054c8: 4622 mov r2, r4 80054ca: 462b mov r3, r5 80054cc: 4630 mov r0, r6 80054ce: 4639 mov r1, r7 80054d0: f7fa fea6 bl 8000220 <__aeabi_dsub> 80054d4: e00e b.n 80054f4 <__ieee754_rem_pio2+0x1cc> 80054d6: 462b mov r3, r5 80054d8: 4622 mov r2, r4 80054da: 4630 mov r0, r6 80054dc: 4639 mov r1, r7 80054de: f7fa fe9f bl 8000220 <__aeabi_dsub> 80054e2: ea4f 5328 mov.w r3, r8, asr #20 80054e6: 9303 str r3, [sp, #12] 80054e8: f3c1 530a ubfx r3, r1, #20, #11 80054ec: ebc3 5318 rsb r3, r3, r8, lsr #20 80054f0: 2b10 cmp r3, #16 80054f2: dc02 bgt.n 80054fa <__ieee754_rem_pio2+0x1d2> 80054f4: e9ca 0100 strd r0, r1, [sl] 80054f8: e039 b.n 800556e <__ieee754_rem_pio2+0x246> 80054fa: a34f add r3, pc, #316 ; (adr r3, 8005638 <__ieee754_rem_pio2+0x310>) 80054fc: e9d3 2300 ldrd r2, r3, [r3] 8005500: ec51 0b18 vmov r0, r1, d8 8005504: f7fb f844 bl 8000590 <__aeabi_dmul> 8005508: 4604 mov r4, r0 800550a: 460d mov r5, r1 800550c: 4602 mov r2, r0 800550e: 460b mov r3, r1 8005510: 4630 mov r0, r6 8005512: 4639 mov r1, r7 8005514: f7fa fe84 bl 8000220 <__aeabi_dsub> 8005518: 4602 mov r2, r0 800551a: 460b mov r3, r1 800551c: 4680 mov r8, r0 800551e: 4689 mov r9, r1 8005520: 4630 mov r0, r6 8005522: 4639 mov r1, r7 8005524: f7fa fe7c bl 8000220 <__aeabi_dsub> 8005528: 4622 mov r2, r4 800552a: 462b mov r3, r5 800552c: f7fa fe78 bl 8000220 <__aeabi_dsub> 8005530: a343 add r3, pc, #268 ; (adr r3, 8005640 <__ieee754_rem_pio2+0x318>) 8005532: e9d3 2300 ldrd r2, r3, [r3] 8005536: 4604 mov r4, r0 8005538: 460d mov r5, r1 800553a: ec51 0b18 vmov r0, r1, d8 800553e: f7fb f827 bl 8000590 <__aeabi_dmul> 8005542: 4622 mov r2, r4 8005544: 462b mov r3, r5 8005546: f7fa fe6b bl 8000220 <__aeabi_dsub> 800554a: 4602 mov r2, r0 800554c: 460b mov r3, r1 800554e: 4604 mov r4, r0 8005550: 460d mov r5, r1 8005552: 4640 mov r0, r8 8005554: 4649 mov r1, r9 8005556: f7fa fe63 bl 8000220 <__aeabi_dsub> 800555a: 9a03 ldr r2, [sp, #12] 800555c: f3c1 530a ubfx r3, r1, #20, #11 8005560: 1ad3 subs r3, r2, r3 8005562: 2b31 cmp r3, #49 ; 0x31 8005564: dc24 bgt.n 80055b0 <__ieee754_rem_pio2+0x288> 8005566: e9ca 0100 strd r0, r1, [sl] 800556a: 4646 mov r6, r8 800556c: 464f mov r7, r9 800556e: e9da 8900 ldrd r8, r9, [sl] 8005572: 4630 mov r0, r6 8005574: 4642 mov r2, r8 8005576: 464b mov r3, r9 8005578: 4639 mov r1, r7 800557a: f7fa fe51 bl 8000220 <__aeabi_dsub> 800557e: 462b mov r3, r5 8005580: 4622 mov r2, r4 8005582: f7fa fe4d bl 8000220 <__aeabi_dsub> 8005586: 9b02 ldr r3, [sp, #8] 8005588: 2b00 cmp r3, #0 800558a: e9ca 0102 strd r0, r1, [sl, #8] 800558e: f6bf af0b bge.w 80053a8 <__ieee754_rem_pio2+0x80> 8005592: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 8005596: f8ca 3004 str.w r3, [sl, #4] 800559a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 800559e: f8ca 8000 str.w r8, [sl] 80055a2: f8ca 0008 str.w r0, [sl, #8] 80055a6: f8ca 300c str.w r3, [sl, #12] 80055aa: f1cb 0b00 rsb fp, fp, #0 80055ae: e6fb b.n 80053a8 <__ieee754_rem_pio2+0x80> 80055b0: a327 add r3, pc, #156 ; (adr r3, 8005650 <__ieee754_rem_pio2+0x328>) 80055b2: e9d3 2300 ldrd r2, r3, [r3] 80055b6: ec51 0b18 vmov r0, r1, d8 80055ba: f7fa ffe9 bl 8000590 <__aeabi_dmul> 80055be: 4604 mov r4, r0 80055c0: 460d mov r5, r1 80055c2: 4602 mov r2, r0 80055c4: 460b mov r3, r1 80055c6: 4640 mov r0, r8 80055c8: 4649 mov r1, r9 80055ca: f7fa fe29 bl 8000220 <__aeabi_dsub> 80055ce: 4602 mov r2, r0 80055d0: 460b mov r3, r1 80055d2: 4606 mov r6, r0 80055d4: 460f mov r7, r1 80055d6: 4640 mov r0, r8 80055d8: 4649 mov r1, r9 80055da: f7fa fe21 bl 8000220 <__aeabi_dsub> 80055de: 4622 mov r2, r4 80055e0: 462b mov r3, r5 80055e2: f7fa fe1d bl 8000220 <__aeabi_dsub> 80055e6: a31c add r3, pc, #112 ; (adr r3, 8005658 <__ieee754_rem_pio2+0x330>) 80055e8: e9d3 2300 ldrd r2, r3, [r3] 80055ec: 4604 mov r4, r0 80055ee: 460d mov r5, r1 80055f0: ec51 0b18 vmov r0, r1, d8 80055f4: f7fa ffcc bl 8000590 <__aeabi_dmul> 80055f8: 4622 mov r2, r4 80055fa: 462b mov r3, r5 80055fc: f7fa fe10 bl 8000220 <__aeabi_dsub> 8005600: 4604 mov r4, r0 8005602: 460d mov r5, r1 8005604: e760 b.n 80054c8 <__ieee754_rem_pio2+0x1a0> 8005606: 4b1c ldr r3, [pc, #112] ; (8005678 <__ieee754_rem_pio2+0x350>) 8005608: 4598 cmp r8, r3 800560a: dd37 ble.n 800567c <__ieee754_rem_pio2+0x354> 800560c: ee10 2a10 vmov r2, s0 8005610: 462b mov r3, r5 8005612: 4620 mov r0, r4 8005614: 4629 mov r1, r5 8005616: f7fa fe03 bl 8000220 <__aeabi_dsub> 800561a: e9ca 0102 strd r0, r1, [sl, #8] 800561e: e9ca 0100 strd r0, r1, [sl] 8005622: e695 b.n 8005350 <__ieee754_rem_pio2+0x28> 8005624: f3af 8000 nop.w 8005628: 54400000 .word 0x54400000 800562c: 3ff921fb .word 0x3ff921fb 8005630: 1a626331 .word 0x1a626331 8005634: 3dd0b461 .word 0x3dd0b461 8005638: 1a600000 .word 0x1a600000 800563c: 3dd0b461 .word 0x3dd0b461 8005640: 2e037073 .word 0x2e037073 8005644: 3ba3198a .word 0x3ba3198a 8005648: 6dc9c883 .word 0x6dc9c883 800564c: 3fe45f30 .word 0x3fe45f30 8005650: 2e000000 .word 0x2e000000 8005654: 3ba3198a .word 0x3ba3198a 8005658: 252049c1 .word 0x252049c1 800565c: 397b839a .word 0x397b839a 8005660: 3fe921fb .word 0x3fe921fb 8005664: 4002d97b .word 0x4002d97b 8005668: 3ff921fb .word 0x3ff921fb 800566c: 413921fb .word 0x413921fb 8005670: 3fe00000 .word 0x3fe00000 8005674: 08007d40 .word 0x08007d40 8005678: 7fefffff .word 0x7fefffff 800567c: ea4f 5628 mov.w r6, r8, asr #20 8005680: f2a6 4616 subw r6, r6, #1046 ; 0x416 8005684: eba8 5106 sub.w r1, r8, r6, lsl #20 8005688: 4620 mov r0, r4 800568a: 460d mov r5, r1 800568c: f7fb fa1a bl 8000ac4 <__aeabi_d2iz> 8005690: f7fa ff14 bl 80004bc <__aeabi_i2d> 8005694: 4602 mov r2, r0 8005696: 460b mov r3, r1 8005698: 4620 mov r0, r4 800569a: 4629 mov r1, r5 800569c: e9cd 2304 strd r2, r3, [sp, #16] 80056a0: f7fa fdbe bl 8000220 <__aeabi_dsub> 80056a4: 4b21 ldr r3, [pc, #132] ; (800572c <__ieee754_rem_pio2+0x404>) 80056a6: 2200 movs r2, #0 80056a8: f7fa ff72 bl 8000590 <__aeabi_dmul> 80056ac: 460d mov r5, r1 80056ae: 4604 mov r4, r0 80056b0: f7fb fa08 bl 8000ac4 <__aeabi_d2iz> 80056b4: f7fa ff02 bl 80004bc <__aeabi_i2d> 80056b8: 4602 mov r2, r0 80056ba: 460b mov r3, r1 80056bc: 4620 mov r0, r4 80056be: 4629 mov r1, r5 80056c0: e9cd 2306 strd r2, r3, [sp, #24] 80056c4: f7fa fdac bl 8000220 <__aeabi_dsub> 80056c8: 4b18 ldr r3, [pc, #96] ; (800572c <__ieee754_rem_pio2+0x404>) 80056ca: 2200 movs r2, #0 80056cc: f7fa ff60 bl 8000590 <__aeabi_dmul> 80056d0: e9cd 0108 strd r0, r1, [sp, #32] 80056d4: f10d 0828 add.w r8, sp, #40 ; 0x28 80056d8: 2703 movs r7, #3 80056da: 2400 movs r4, #0 80056dc: 2500 movs r5, #0 80056de: e978 0102 ldrd r0, r1, [r8, #-8]! 80056e2: 4622 mov r2, r4 80056e4: 462b mov r3, r5 80056e6: 46b9 mov r9, r7 80056e8: 3f01 subs r7, #1 80056ea: f7fb f9b9 bl 8000a60 <__aeabi_dcmpeq> 80056ee: 2800 cmp r0, #0 80056f0: d1f5 bne.n 80056de <__ieee754_rem_pio2+0x3b6> 80056f2: 4b0f ldr r3, [pc, #60] ; (8005730 <__ieee754_rem_pio2+0x408>) 80056f4: 9301 str r3, [sp, #4] 80056f6: 2302 movs r3, #2 80056f8: 9300 str r3, [sp, #0] 80056fa: 4632 mov r2, r6 80056fc: 464b mov r3, r9 80056fe: 4651 mov r1, sl 8005700: a804 add r0, sp, #16 8005702: f000 f819 bl 8005738 <__kernel_rem_pio2> 8005706: 9b02 ldr r3, [sp, #8] 8005708: 2b00 cmp r3, #0 800570a: 4683 mov fp, r0 800570c: f6bf ae4c bge.w 80053a8 <__ieee754_rem_pio2+0x80> 8005710: e9da 2100 ldrd r2, r1, [sl] 8005714: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 8005718: e9ca 2300 strd r2, r3, [sl] 800571c: e9da 2102 ldrd r2, r1, [sl, #8] 8005720: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 8005724: e9ca 2302 strd r2, r3, [sl, #8] 8005728: e73f b.n 80055aa <__ieee754_rem_pio2+0x282> 800572a: bf00 nop 800572c: 41700000 .word 0x41700000 8005730: 08007dc0 .word 0x08007dc0 8005734: 00000000 .word 0x00000000 08005738 <__kernel_rem_pio2>: 8005738: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800573c: ed2d 8b02 vpush {d8} 8005740: f5ad 7d19 sub.w sp, sp, #612 ; 0x264 8005744: f112 0f14 cmn.w r2, #20 8005748: 9306 str r3, [sp, #24] 800574a: 9104 str r1, [sp, #16] 800574c: 4bc2 ldr r3, [pc, #776] ; (8005a58 <__kernel_rem_pio2+0x320>) 800574e: 99a4 ldr r1, [sp, #656] ; 0x290 8005750: 9009 str r0, [sp, #36] ; 0x24 8005752: f853 3021 ldr.w r3, [r3, r1, lsl #2] 8005756: 9300 str r3, [sp, #0] 8005758: 9b06 ldr r3, [sp, #24] 800575a: f103 33ff add.w r3, r3, #4294967295 ; 0xffffffff 800575e: bfa8 it ge 8005760: 1ed4 subge r4, r2, #3 8005762: 9305 str r3, [sp, #20] 8005764: bfb2 itee lt 8005766: 2400 movlt r4, #0 8005768: 2318 movge r3, #24 800576a: fb94 f4f3 sdivge r4, r4, r3 800576e: f06f 0317 mvn.w r3, #23 8005772: fb04 3303 mla r3, r4, r3, r3 8005776: eb03 0a02 add.w sl, r3, r2 800577a: 9b00 ldr r3, [sp, #0] 800577c: 9a05 ldr r2, [sp, #20] 800577e: ed9f 8bb2 vldr d8, [pc, #712] ; 8005a48 <__kernel_rem_pio2+0x310> 8005782: eb03 0802 add.w r8, r3, r2 8005786: 9ba5 ldr r3, [sp, #660] ; 0x294 8005788: 1aa7 subs r7, r4, r2 800578a: ae20 add r6, sp, #128 ; 0x80 800578c: eb03 0987 add.w r9, r3, r7, lsl #2 8005790: 2500 movs r5, #0 8005792: 4545 cmp r5, r8 8005794: dd13 ble.n 80057be <__kernel_rem_pio2+0x86> 8005796: 9b06 ldr r3, [sp, #24] 8005798: aa20 add r2, sp, #128 ; 0x80 800579a: eb02 05c3 add.w r5, r2, r3, lsl #3 800579e: f50d 7be0 add.w fp, sp, #448 ; 0x1c0 80057a2: f04f 0800 mov.w r8, #0 80057a6: 9b00 ldr r3, [sp, #0] 80057a8: 4598 cmp r8, r3 80057aa: dc31 bgt.n 8005810 <__kernel_rem_pio2+0xd8> 80057ac: ed9f 7ba6 vldr d7, [pc, #664] ; 8005a48 <__kernel_rem_pio2+0x310> 80057b0: f8dd 9024 ldr.w r9, [sp, #36] ; 0x24 80057b4: ed8d 7b02 vstr d7, [sp, #8] 80057b8: 462f mov r7, r5 80057ba: 2600 movs r6, #0 80057bc: e01b b.n 80057f6 <__kernel_rem_pio2+0xbe> 80057be: 42ef cmn r7, r5 80057c0: d407 bmi.n 80057d2 <__kernel_rem_pio2+0x9a> 80057c2: f859 0025 ldr.w r0, [r9, r5, lsl #2] 80057c6: f7fa fe79 bl 80004bc <__aeabi_i2d> 80057ca: e8e6 0102 strd r0, r1, [r6], #8 80057ce: 3501 adds r5, #1 80057d0: e7df b.n 8005792 <__kernel_rem_pio2+0x5a> 80057d2: ec51 0b18 vmov r0, r1, d8 80057d6: e7f8 b.n 80057ca <__kernel_rem_pio2+0x92> 80057d8: e9d7 2300 ldrd r2, r3, [r7] 80057dc: e8f9 0102 ldrd r0, r1, [r9], #8 80057e0: f7fa fed6 bl 8000590 <__aeabi_dmul> 80057e4: 4602 mov r2, r0 80057e6: 460b mov r3, r1 80057e8: e9dd 0102 ldrd r0, r1, [sp, #8] 80057ec: f7fa fd1a bl 8000224 <__adddf3> 80057f0: e9cd 0102 strd r0, r1, [sp, #8] 80057f4: 3601 adds r6, #1 80057f6: 9b05 ldr r3, [sp, #20] 80057f8: 429e cmp r6, r3 80057fa: f1a7 0708 sub.w r7, r7, #8 80057fe: ddeb ble.n 80057d8 <__kernel_rem_pio2+0xa0> 8005800: ed9d 7b02 vldr d7, [sp, #8] 8005804: f108 0801 add.w r8, r8, #1 8005808: ecab 7b02 vstmia fp!, {d7} 800580c: 3508 adds r5, #8 800580e: e7ca b.n 80057a6 <__kernel_rem_pio2+0x6e> 8005810: 9b00 ldr r3, [sp, #0] 8005812: aa0c add r2, sp, #48 ; 0x30 8005814: eb02 0383 add.w r3, r2, r3, lsl #2 8005818: 930b str r3, [sp, #44] ; 0x2c 800581a: 9ba5 ldr r3, [sp, #660] ; 0x294 800581c: eb03 0384 add.w r3, r3, r4, lsl #2 8005820: 9c00 ldr r4, [sp, #0] 8005822: 930a str r3, [sp, #40] ; 0x28 8005824: 00e3 lsls r3, r4, #3 8005826: 9308 str r3, [sp, #32] 8005828: ab98 add r3, sp, #608 ; 0x260 800582a: eb03 03c4 add.w r3, r3, r4, lsl #3 800582e: e953 6728 ldrd r6, r7, [r3, #-160] ; 0xa0 8005832: f10d 0830 add.w r8, sp, #48 ; 0x30 8005836: ab70 add r3, sp, #448 ; 0x1c0 8005838: eb03 05c4 add.w r5, r3, r4, lsl #3 800583c: 46c3 mov fp, r8 800583e: 46a1 mov r9, r4 8005840: f1b9 0f00 cmp.w r9, #0 8005844: f1a5 0508 sub.w r5, r5, #8 8005848: dc77 bgt.n 800593a <__kernel_rem_pio2+0x202> 800584a: ec47 6b10 vmov d0, r6, r7 800584e: 4650 mov r0, sl 8005850: f000 fcd6 bl 8006200 8005854: ec57 6b10 vmov r6, r7, d0 8005858: 2200 movs r2, #0 800585a: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000 800585e: ee10 0a10 vmov r0, s0 8005862: 4639 mov r1, r7 8005864: f7fa fe94 bl 8000590 <__aeabi_dmul> 8005868: ec41 0b10 vmov d0, r0, r1 800586c: f000 fd48 bl 8006300 8005870: 4b7a ldr r3, [pc, #488] ; (8005a5c <__kernel_rem_pio2+0x324>) 8005872: ec51 0b10 vmov r0, r1, d0 8005876: 2200 movs r2, #0 8005878: f7fa fe8a bl 8000590 <__aeabi_dmul> 800587c: 4602 mov r2, r0 800587e: 460b mov r3, r1 8005880: 4630 mov r0, r6 8005882: 4639 mov r1, r7 8005884: f7fa fccc bl 8000220 <__aeabi_dsub> 8005888: 460f mov r7, r1 800588a: 4606 mov r6, r0 800588c: f7fb f91a bl 8000ac4 <__aeabi_d2iz> 8005890: 9002 str r0, [sp, #8] 8005892: f7fa fe13 bl 80004bc <__aeabi_i2d> 8005896: 4602 mov r2, r0 8005898: 460b mov r3, r1 800589a: 4630 mov r0, r6 800589c: 4639 mov r1, r7 800589e: f7fa fcbf bl 8000220 <__aeabi_dsub> 80058a2: f1ba 0f00 cmp.w sl, #0 80058a6: 4606 mov r6, r0 80058a8: 460f mov r7, r1 80058aa: dd6d ble.n 8005988 <__kernel_rem_pio2+0x250> 80058ac: 1e61 subs r1, r4, #1 80058ae: ab0c add r3, sp, #48 ; 0x30 80058b0: 9d02 ldr r5, [sp, #8] 80058b2: f853 3021 ldr.w r3, [r3, r1, lsl #2] 80058b6: f1ca 0018 rsb r0, sl, #24 80058ba: fa43 f200 asr.w r2, r3, r0 80058be: 4415 add r5, r2 80058c0: 4082 lsls r2, r0 80058c2: 1a9b subs r3, r3, r2 80058c4: aa0c add r2, sp, #48 ; 0x30 80058c6: 9502 str r5, [sp, #8] 80058c8: f842 3021 str.w r3, [r2, r1, lsl #2] 80058cc: f1ca 0217 rsb r2, sl, #23 80058d0: fa43 fb02 asr.w fp, r3, r2 80058d4: f1bb 0f00 cmp.w fp, #0 80058d8: dd65 ble.n 80059a6 <__kernel_rem_pio2+0x26e> 80058da: 9b02 ldr r3, [sp, #8] 80058dc: 2200 movs r2, #0 80058de: 3301 adds r3, #1 80058e0: 9302 str r3, [sp, #8] 80058e2: 4615 mov r5, r2 80058e4: f06f 417f mvn.w r1, #4278190080 ; 0xff000000 80058e8: 4294 cmp r4, r2 80058ea: f300 809f bgt.w 8005a2c <__kernel_rem_pio2+0x2f4> 80058ee: f1ba 0f00 cmp.w sl, #0 80058f2: dd07 ble.n 8005904 <__kernel_rem_pio2+0x1cc> 80058f4: f1ba 0f01 cmp.w sl, #1 80058f8: f000 80c1 beq.w 8005a7e <__kernel_rem_pio2+0x346> 80058fc: f1ba 0f02 cmp.w sl, #2 8005900: f000 80c7 beq.w 8005a92 <__kernel_rem_pio2+0x35a> 8005904: f1bb 0f02 cmp.w fp, #2 8005908: d14d bne.n 80059a6 <__kernel_rem_pio2+0x26e> 800590a: 4632 mov r2, r6 800590c: 463b mov r3, r7 800590e: 4954 ldr r1, [pc, #336] ; (8005a60 <__kernel_rem_pio2+0x328>) 8005910: 2000 movs r0, #0 8005912: f7fa fc85 bl 8000220 <__aeabi_dsub> 8005916: 4606 mov r6, r0 8005918: 460f mov r7, r1 800591a: 2d00 cmp r5, #0 800591c: d043 beq.n 80059a6 <__kernel_rem_pio2+0x26e> 800591e: 4650 mov r0, sl 8005920: ed9f 0b4b vldr d0, [pc, #300] ; 8005a50 <__kernel_rem_pio2+0x318> 8005924: f000 fc6c bl 8006200 8005928: 4630 mov r0, r6 800592a: 4639 mov r1, r7 800592c: ec53 2b10 vmov r2, r3, d0 8005930: f7fa fc76 bl 8000220 <__aeabi_dsub> 8005934: 4606 mov r6, r0 8005936: 460f mov r7, r1 8005938: e035 b.n 80059a6 <__kernel_rem_pio2+0x26e> 800593a: 4b4a ldr r3, [pc, #296] ; (8005a64 <__kernel_rem_pio2+0x32c>) 800593c: 2200 movs r2, #0 800593e: 4630 mov r0, r6 8005940: 4639 mov r1, r7 8005942: f7fa fe25 bl 8000590 <__aeabi_dmul> 8005946: f7fb f8bd bl 8000ac4 <__aeabi_d2iz> 800594a: f7fa fdb7 bl 80004bc <__aeabi_i2d> 800594e: 4602 mov r2, r0 8005950: 460b mov r3, r1 8005952: ec43 2b18 vmov d8, r2, r3 8005956: 4b44 ldr r3, [pc, #272] ; (8005a68 <__kernel_rem_pio2+0x330>) 8005958: 2200 movs r2, #0 800595a: f7fa fe19 bl 8000590 <__aeabi_dmul> 800595e: 4602 mov r2, r0 8005960: 460b mov r3, r1 8005962: 4630 mov r0, r6 8005964: 4639 mov r1, r7 8005966: f7fa fc5b bl 8000220 <__aeabi_dsub> 800596a: f7fb f8ab bl 8000ac4 <__aeabi_d2iz> 800596e: e9d5 2300 ldrd r2, r3, [r5] 8005972: f84b 0b04 str.w r0, [fp], #4 8005976: ec51 0b18 vmov r0, r1, d8 800597a: f7fa fc53 bl 8000224 <__adddf3> 800597e: f109 39ff add.w r9, r9, #4294967295 ; 0xffffffff 8005982: 4606 mov r6, r0 8005984: 460f mov r7, r1 8005986: e75b b.n 8005840 <__kernel_rem_pio2+0x108> 8005988: d106 bne.n 8005998 <__kernel_rem_pio2+0x260> 800598a: 1e63 subs r3, r4, #1 800598c: aa0c add r2, sp, #48 ; 0x30 800598e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8005992: ea4f 5be3 mov.w fp, r3, asr #23 8005996: e79d b.n 80058d4 <__kernel_rem_pio2+0x19c> 8005998: 4b34 ldr r3, [pc, #208] ; (8005a6c <__kernel_rem_pio2+0x334>) 800599a: 2200 movs r2, #0 800599c: f7fb f87e bl 8000a9c <__aeabi_dcmpge> 80059a0: 2800 cmp r0, #0 80059a2: d140 bne.n 8005a26 <__kernel_rem_pio2+0x2ee> 80059a4: 4683 mov fp, r0 80059a6: 2200 movs r2, #0 80059a8: 2300 movs r3, #0 80059aa: 4630 mov r0, r6 80059ac: 4639 mov r1, r7 80059ae: f7fb f857 bl 8000a60 <__aeabi_dcmpeq> 80059b2: 2800 cmp r0, #0 80059b4: f000 80c1 beq.w 8005b3a <__kernel_rem_pio2+0x402> 80059b8: 1e65 subs r5, r4, #1 80059ba: 462b mov r3, r5 80059bc: 2200 movs r2, #0 80059be: 9900 ldr r1, [sp, #0] 80059c0: 428b cmp r3, r1 80059c2: da6d bge.n 8005aa0 <__kernel_rem_pio2+0x368> 80059c4: 2a00 cmp r2, #0 80059c6: f000 808a beq.w 8005ade <__kernel_rem_pio2+0x3a6> 80059ca: ab0c add r3, sp, #48 ; 0x30 80059cc: f1aa 0a18 sub.w sl, sl, #24 80059d0: f853 3025 ldr.w r3, [r3, r5, lsl #2] 80059d4: 2b00 cmp r3, #0 80059d6: f000 80ae beq.w 8005b36 <__kernel_rem_pio2+0x3fe> 80059da: 4650 mov r0, sl 80059dc: ed9f 0b1c vldr d0, [pc, #112] ; 8005a50 <__kernel_rem_pio2+0x318> 80059e0: f000 fc0e bl 8006200 80059e4: 1c6b adds r3, r5, #1 80059e6: 00da lsls r2, r3, #3 80059e8: 9205 str r2, [sp, #20] 80059ea: ec57 6b10 vmov r6, r7, d0 80059ee: aa70 add r2, sp, #448 ; 0x1c0 80059f0: f8df 9070 ldr.w r9, [pc, #112] ; 8005a64 <__kernel_rem_pio2+0x32c> 80059f4: eb02 0ac3 add.w sl, r2, r3, lsl #3 80059f8: 462c mov r4, r5 80059fa: f04f 0800 mov.w r8, #0 80059fe: 2c00 cmp r4, #0 8005a00: f280 80d4 bge.w 8005bac <__kernel_rem_pio2+0x474> 8005a04: 462c mov r4, r5 8005a06: 2c00 cmp r4, #0 8005a08: f2c0 8102 blt.w 8005c10 <__kernel_rem_pio2+0x4d8> 8005a0c: 4b18 ldr r3, [pc, #96] ; (8005a70 <__kernel_rem_pio2+0x338>) 8005a0e: 461e mov r6, r3 8005a10: ab70 add r3, sp, #448 ; 0x1c0 8005a12: eb03 08c4 add.w r8, r3, r4, lsl #3 8005a16: 1b2b subs r3, r5, r4 8005a18: f04f 0900 mov.w r9, #0 8005a1c: f04f 0a00 mov.w sl, #0 8005a20: 2700 movs r7, #0 8005a22: 9306 str r3, [sp, #24] 8005a24: e0e6 b.n 8005bf4 <__kernel_rem_pio2+0x4bc> 8005a26: f04f 0b02 mov.w fp, #2 8005a2a: e756 b.n 80058da <__kernel_rem_pio2+0x1a2> 8005a2c: f8d8 3000 ldr.w r3, [r8] 8005a30: bb05 cbnz r5, 8005a74 <__kernel_rem_pio2+0x33c> 8005a32: b123 cbz r3, 8005a3e <__kernel_rem_pio2+0x306> 8005a34: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000 8005a38: f8c8 3000 str.w r3, [r8] 8005a3c: 2301 movs r3, #1 8005a3e: 3201 adds r2, #1 8005a40: f108 0804 add.w r8, r8, #4 8005a44: 461d mov r5, r3 8005a46: e74f b.n 80058e8 <__kernel_rem_pio2+0x1b0> ... 8005a54: 3ff00000 .word 0x3ff00000 8005a58: 08007f08 .word 0x08007f08 8005a5c: 40200000 .word 0x40200000 8005a60: 3ff00000 .word 0x3ff00000 8005a64: 3e700000 .word 0x3e700000 8005a68: 41700000 .word 0x41700000 8005a6c: 3fe00000 .word 0x3fe00000 8005a70: 08007ec8 .word 0x08007ec8 8005a74: 1acb subs r3, r1, r3 8005a76: f8c8 3000 str.w r3, [r8] 8005a7a: 462b mov r3, r5 8005a7c: e7df b.n 8005a3e <__kernel_rem_pio2+0x306> 8005a7e: 1e62 subs r2, r4, #1 8005a80: ab0c add r3, sp, #48 ; 0x30 8005a82: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8005a86: f3c3 0316 ubfx r3, r3, #0, #23 8005a8a: a90c add r1, sp, #48 ; 0x30 8005a8c: f841 3022 str.w r3, [r1, r2, lsl #2] 8005a90: e738 b.n 8005904 <__kernel_rem_pio2+0x1cc> 8005a92: 1e62 subs r2, r4, #1 8005a94: ab0c add r3, sp, #48 ; 0x30 8005a96: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8005a9a: f3c3 0315 ubfx r3, r3, #0, #22 8005a9e: e7f4 b.n 8005a8a <__kernel_rem_pio2+0x352> 8005aa0: a90c add r1, sp, #48 ; 0x30 8005aa2: f851 1023 ldr.w r1, [r1, r3, lsl #2] 8005aa6: 3b01 subs r3, #1 8005aa8: 430a orrs r2, r1 8005aaa: e788 b.n 80059be <__kernel_rem_pio2+0x286> 8005aac: 3301 adds r3, #1 8005aae: f852 1d04 ldr.w r1, [r2, #-4]! 8005ab2: 2900 cmp r1, #0 8005ab4: d0fa beq.n 8005aac <__kernel_rem_pio2+0x374> 8005ab6: 9a08 ldr r2, [sp, #32] 8005ab8: f502 7218 add.w r2, r2, #608 ; 0x260 8005abc: 446a add r2, sp 8005abe: 3a98 subs r2, #152 ; 0x98 8005ac0: 9208 str r2, [sp, #32] 8005ac2: 9a06 ldr r2, [sp, #24] 8005ac4: a920 add r1, sp, #128 ; 0x80 8005ac6: 18a2 adds r2, r4, r2 8005ac8: 18e3 adds r3, r4, r3 8005aca: f104 0801 add.w r8, r4, #1 8005ace: eb01 05c2 add.w r5, r1, r2, lsl #3 8005ad2: 9302 str r3, [sp, #8] 8005ad4: 9b02 ldr r3, [sp, #8] 8005ad6: 4543 cmp r3, r8 8005ad8: da04 bge.n 8005ae4 <__kernel_rem_pio2+0x3ac> 8005ada: 461c mov r4, r3 8005adc: e6a2 b.n 8005824 <__kernel_rem_pio2+0xec> 8005ade: 9a0b ldr r2, [sp, #44] ; 0x2c 8005ae0: 2301 movs r3, #1 8005ae2: e7e4 b.n 8005aae <__kernel_rem_pio2+0x376> 8005ae4: 9b0a ldr r3, [sp, #40] ; 0x28 8005ae6: f853 0028 ldr.w r0, [r3, r8, lsl #2] 8005aea: f7fa fce7 bl 80004bc <__aeabi_i2d> 8005aee: e8e5 0102 strd r0, r1, [r5], #8 8005af2: 9b09 ldr r3, [sp, #36] ; 0x24 8005af4: 46ab mov fp, r5 8005af6: 461c mov r4, r3 8005af8: f04f 0900 mov.w r9, #0 8005afc: 2600 movs r6, #0 8005afe: 2700 movs r7, #0 8005b00: 9b05 ldr r3, [sp, #20] 8005b02: 4599 cmp r9, r3 8005b04: dd06 ble.n 8005b14 <__kernel_rem_pio2+0x3dc> 8005b06: 9b08 ldr r3, [sp, #32] 8005b08: e8e3 6702 strd r6, r7, [r3], #8 8005b0c: f108 0801 add.w r8, r8, #1 8005b10: 9308 str r3, [sp, #32] 8005b12: e7df b.n 8005ad4 <__kernel_rem_pio2+0x39c> 8005b14: e97b 2302 ldrd r2, r3, [fp, #-8]! 8005b18: e8f4 0102 ldrd r0, r1, [r4], #8 8005b1c: f7fa fd38 bl 8000590 <__aeabi_dmul> 8005b20: 4602 mov r2, r0 8005b22: 460b mov r3, r1 8005b24: 4630 mov r0, r6 8005b26: 4639 mov r1, r7 8005b28: f7fa fb7c bl 8000224 <__adddf3> 8005b2c: f109 0901 add.w r9, r9, #1 8005b30: 4606 mov r6, r0 8005b32: 460f mov r7, r1 8005b34: e7e4 b.n 8005b00 <__kernel_rem_pio2+0x3c8> 8005b36: 3d01 subs r5, #1 8005b38: e747 b.n 80059ca <__kernel_rem_pio2+0x292> 8005b3a: ec47 6b10 vmov d0, r6, r7 8005b3e: f1ca 0000 rsb r0, sl, #0 8005b42: f000 fb5d bl 8006200 8005b46: ec57 6b10 vmov r6, r7, d0 8005b4a: 4ba0 ldr r3, [pc, #640] ; (8005dcc <__kernel_rem_pio2+0x694>) 8005b4c: ee10 0a10 vmov r0, s0 8005b50: 2200 movs r2, #0 8005b52: 4639 mov r1, r7 8005b54: f7fa ffa2 bl 8000a9c <__aeabi_dcmpge> 8005b58: b1f8 cbz r0, 8005b9a <__kernel_rem_pio2+0x462> 8005b5a: 4b9d ldr r3, [pc, #628] ; (8005dd0 <__kernel_rem_pio2+0x698>) 8005b5c: 2200 movs r2, #0 8005b5e: 4630 mov r0, r6 8005b60: 4639 mov r1, r7 8005b62: f7fa fd15 bl 8000590 <__aeabi_dmul> 8005b66: f7fa ffad bl 8000ac4 <__aeabi_d2iz> 8005b6a: 4680 mov r8, r0 8005b6c: f7fa fca6 bl 80004bc <__aeabi_i2d> 8005b70: 4b96 ldr r3, [pc, #600] ; (8005dcc <__kernel_rem_pio2+0x694>) 8005b72: 2200 movs r2, #0 8005b74: f7fa fd0c bl 8000590 <__aeabi_dmul> 8005b78: 460b mov r3, r1 8005b7a: 4602 mov r2, r0 8005b7c: 4639 mov r1, r7 8005b7e: 4630 mov r0, r6 8005b80: f7fa fb4e bl 8000220 <__aeabi_dsub> 8005b84: f7fa ff9e bl 8000ac4 <__aeabi_d2iz> 8005b88: 1c65 adds r5, r4, #1 8005b8a: ab0c add r3, sp, #48 ; 0x30 8005b8c: f10a 0a18 add.w sl, sl, #24 8005b90: f843 0024 str.w r0, [r3, r4, lsl #2] 8005b94: f843 8025 str.w r8, [r3, r5, lsl #2] 8005b98: e71f b.n 80059da <__kernel_rem_pio2+0x2a2> 8005b9a: 4630 mov r0, r6 8005b9c: 4639 mov r1, r7 8005b9e: f7fa ff91 bl 8000ac4 <__aeabi_d2iz> 8005ba2: ab0c add r3, sp, #48 ; 0x30 8005ba4: 4625 mov r5, r4 8005ba6: f843 0024 str.w r0, [r3, r4, lsl #2] 8005baa: e716 b.n 80059da <__kernel_rem_pio2+0x2a2> 8005bac: ab0c add r3, sp, #48 ; 0x30 8005bae: f853 0024 ldr.w r0, [r3, r4, lsl #2] 8005bb2: f7fa fc83 bl 80004bc <__aeabi_i2d> 8005bb6: 4632 mov r2, r6 8005bb8: 463b mov r3, r7 8005bba: f7fa fce9 bl 8000590 <__aeabi_dmul> 8005bbe: 4642 mov r2, r8 8005bc0: e96a 0102 strd r0, r1, [sl, #-8]! 8005bc4: 464b mov r3, r9 8005bc6: 4630 mov r0, r6 8005bc8: 4639 mov r1, r7 8005bca: f7fa fce1 bl 8000590 <__aeabi_dmul> 8005bce: 3c01 subs r4, #1 8005bd0: 4606 mov r6, r0 8005bd2: 460f mov r7, r1 8005bd4: e713 b.n 80059fe <__kernel_rem_pio2+0x2c6> 8005bd6: e8f8 2302 ldrd r2, r3, [r8], #8 8005bda: e8f6 0102 ldrd r0, r1, [r6], #8 8005bde: f7fa fcd7 bl 8000590 <__aeabi_dmul> 8005be2: 4602 mov r2, r0 8005be4: 460b mov r3, r1 8005be6: 4648 mov r0, r9 8005be8: 4651 mov r1, sl 8005bea: f7fa fb1b bl 8000224 <__adddf3> 8005bee: 3701 adds r7, #1 8005bf0: 4681 mov r9, r0 8005bf2: 468a mov sl, r1 8005bf4: 9b00 ldr r3, [sp, #0] 8005bf6: 429f cmp r7, r3 8005bf8: dc02 bgt.n 8005c00 <__kernel_rem_pio2+0x4c8> 8005bfa: 9b06 ldr r3, [sp, #24] 8005bfc: 429f cmp r7, r3 8005bfe: ddea ble.n 8005bd6 <__kernel_rem_pio2+0x49e> 8005c00: 9a06 ldr r2, [sp, #24] 8005c02: ab48 add r3, sp, #288 ; 0x120 8005c04: eb03 06c2 add.w r6, r3, r2, lsl #3 8005c08: e9c6 9a00 strd r9, sl, [r6] 8005c0c: 3c01 subs r4, #1 8005c0e: e6fa b.n 8005a06 <__kernel_rem_pio2+0x2ce> 8005c10: 9ba4 ldr r3, [sp, #656] ; 0x290 8005c12: 2b02 cmp r3, #2 8005c14: dc0b bgt.n 8005c2e <__kernel_rem_pio2+0x4f6> 8005c16: 2b00 cmp r3, #0 8005c18: dc39 bgt.n 8005c8e <__kernel_rem_pio2+0x556> 8005c1a: d05d beq.n 8005cd8 <__kernel_rem_pio2+0x5a0> 8005c1c: 9b02 ldr r3, [sp, #8] 8005c1e: f003 0007 and.w r0, r3, #7 8005c22: f50d 7d19 add.w sp, sp, #612 ; 0x264 8005c26: ecbd 8b02 vpop {d8} 8005c2a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8005c2e: 9ba4 ldr r3, [sp, #656] ; 0x290 8005c30: 2b03 cmp r3, #3 8005c32: d1f3 bne.n 8005c1c <__kernel_rem_pio2+0x4e4> 8005c34: 9b05 ldr r3, [sp, #20] 8005c36: 9500 str r5, [sp, #0] 8005c38: f503 7318 add.w r3, r3, #608 ; 0x260 8005c3c: eb0d 0403 add.w r4, sp, r3 8005c40: f5a4 74a4 sub.w r4, r4, #328 ; 0x148 8005c44: 46a2 mov sl, r4 8005c46: 9b00 ldr r3, [sp, #0] 8005c48: 2b00 cmp r3, #0 8005c4a: f1aa 0a08 sub.w sl, sl, #8 8005c4e: dc69 bgt.n 8005d24 <__kernel_rem_pio2+0x5ec> 8005c50: 46aa mov sl, r5 8005c52: f1ba 0f01 cmp.w sl, #1 8005c56: f1a4 0408 sub.w r4, r4, #8 8005c5a: f300 8083 bgt.w 8005d64 <__kernel_rem_pio2+0x62c> 8005c5e: 9c05 ldr r4, [sp, #20] 8005c60: ab48 add r3, sp, #288 ; 0x120 8005c62: 441c add r4, r3 8005c64: 2000 movs r0, #0 8005c66: 2100 movs r1, #0 8005c68: 2d01 cmp r5, #1 8005c6a: f300 809a bgt.w 8005da2 <__kernel_rem_pio2+0x66a> 8005c6e: e9dd 7848 ldrd r7, r8, [sp, #288] ; 0x120 8005c72: e9dd 564a ldrd r5, r6, [sp, #296] ; 0x128 8005c76: f1bb 0f00 cmp.w fp, #0 8005c7a: f040 8098 bne.w 8005dae <__kernel_rem_pio2+0x676> 8005c7e: 9b04 ldr r3, [sp, #16] 8005c80: e9c3 7800 strd r7, r8, [r3] 8005c84: e9c3 5602 strd r5, r6, [r3, #8] 8005c88: e9c3 0104 strd r0, r1, [r3, #16] 8005c8c: e7c6 b.n 8005c1c <__kernel_rem_pio2+0x4e4> 8005c8e: 9e05 ldr r6, [sp, #20] 8005c90: ab48 add r3, sp, #288 ; 0x120 8005c92: 441e add r6, r3 8005c94: 462c mov r4, r5 8005c96: 2000 movs r0, #0 8005c98: 2100 movs r1, #0 8005c9a: 2c00 cmp r4, #0 8005c9c: da33 bge.n 8005d06 <__kernel_rem_pio2+0x5ce> 8005c9e: f1bb 0f00 cmp.w fp, #0 8005ca2: d036 beq.n 8005d12 <__kernel_rem_pio2+0x5da> 8005ca4: 4602 mov r2, r0 8005ca6: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 8005caa: 9c04 ldr r4, [sp, #16] 8005cac: e9c4 2300 strd r2, r3, [r4] 8005cb0: 4602 mov r2, r0 8005cb2: 460b mov r3, r1 8005cb4: e9dd 0148 ldrd r0, r1, [sp, #288] ; 0x120 8005cb8: f7fa fab2 bl 8000220 <__aeabi_dsub> 8005cbc: ae4a add r6, sp, #296 ; 0x128 8005cbe: 2401 movs r4, #1 8005cc0: 42a5 cmp r5, r4 8005cc2: da29 bge.n 8005d18 <__kernel_rem_pio2+0x5e0> 8005cc4: f1bb 0f00 cmp.w fp, #0 8005cc8: d002 beq.n 8005cd0 <__kernel_rem_pio2+0x598> 8005cca: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 8005cce: 4619 mov r1, r3 8005cd0: 9b04 ldr r3, [sp, #16] 8005cd2: e9c3 0102 strd r0, r1, [r3, #8] 8005cd6: e7a1 b.n 8005c1c <__kernel_rem_pio2+0x4e4> 8005cd8: 9c05 ldr r4, [sp, #20] 8005cda: ab48 add r3, sp, #288 ; 0x120 8005cdc: 441c add r4, r3 8005cde: 2000 movs r0, #0 8005ce0: 2100 movs r1, #0 8005ce2: 2d00 cmp r5, #0 8005ce4: da09 bge.n 8005cfa <__kernel_rem_pio2+0x5c2> 8005ce6: f1bb 0f00 cmp.w fp, #0 8005cea: d002 beq.n 8005cf2 <__kernel_rem_pio2+0x5ba> 8005cec: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 8005cf0: 4619 mov r1, r3 8005cf2: 9b04 ldr r3, [sp, #16] 8005cf4: e9c3 0100 strd r0, r1, [r3] 8005cf8: e790 b.n 8005c1c <__kernel_rem_pio2+0x4e4> 8005cfa: e974 2302 ldrd r2, r3, [r4, #-8]! 8005cfe: f7fa fa91 bl 8000224 <__adddf3> 8005d02: 3d01 subs r5, #1 8005d04: e7ed b.n 8005ce2 <__kernel_rem_pio2+0x5aa> 8005d06: e976 2302 ldrd r2, r3, [r6, #-8]! 8005d0a: f7fa fa8b bl 8000224 <__adddf3> 8005d0e: 3c01 subs r4, #1 8005d10: e7c3 b.n 8005c9a <__kernel_rem_pio2+0x562> 8005d12: 4602 mov r2, r0 8005d14: 460b mov r3, r1 8005d16: e7c8 b.n 8005caa <__kernel_rem_pio2+0x572> 8005d18: e8f6 2302 ldrd r2, r3, [r6], #8 8005d1c: f7fa fa82 bl 8000224 <__adddf3> 8005d20: 3401 adds r4, #1 8005d22: e7cd b.n 8005cc0 <__kernel_rem_pio2+0x588> 8005d24: e9da 8900 ldrd r8, r9, [sl] 8005d28: e9da 6702 ldrd r6, r7, [sl, #8] 8005d2c: 9b00 ldr r3, [sp, #0] 8005d2e: 3b01 subs r3, #1 8005d30: 9300 str r3, [sp, #0] 8005d32: 4632 mov r2, r6 8005d34: 463b mov r3, r7 8005d36: 4640 mov r0, r8 8005d38: 4649 mov r1, r9 8005d3a: f7fa fa73 bl 8000224 <__adddf3> 8005d3e: e9cd 0106 strd r0, r1, [sp, #24] 8005d42: 4602 mov r2, r0 8005d44: 460b mov r3, r1 8005d46: 4640 mov r0, r8 8005d48: 4649 mov r1, r9 8005d4a: f7fa fa69 bl 8000220 <__aeabi_dsub> 8005d4e: 4632 mov r2, r6 8005d50: 463b mov r3, r7 8005d52: f7fa fa67 bl 8000224 <__adddf3> 8005d56: ed9d 7b06 vldr d7, [sp, #24] 8005d5a: e9ca 0102 strd r0, r1, [sl, #8] 8005d5e: ed8a 7b00 vstr d7, [sl] 8005d62: e770 b.n 8005c46 <__kernel_rem_pio2+0x50e> 8005d64: e9d4 8900 ldrd r8, r9, [r4] 8005d68: e9d4 6702 ldrd r6, r7, [r4, #8] 8005d6c: 4640 mov r0, r8 8005d6e: 4632 mov r2, r6 8005d70: 463b mov r3, r7 8005d72: 4649 mov r1, r9 8005d74: f7fa fa56 bl 8000224 <__adddf3> 8005d78: e9cd 0100 strd r0, r1, [sp] 8005d7c: 4602 mov r2, r0 8005d7e: 460b mov r3, r1 8005d80: 4640 mov r0, r8 8005d82: 4649 mov r1, r9 8005d84: f7fa fa4c bl 8000220 <__aeabi_dsub> 8005d88: 4632 mov r2, r6 8005d8a: 463b mov r3, r7 8005d8c: f7fa fa4a bl 8000224 <__adddf3> 8005d90: ed9d 7b00 vldr d7, [sp] 8005d94: e9c4 0102 strd r0, r1, [r4, #8] 8005d98: ed84 7b00 vstr d7, [r4] 8005d9c: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff 8005da0: e757 b.n 8005c52 <__kernel_rem_pio2+0x51a> 8005da2: e974 2302 ldrd r2, r3, [r4, #-8]! 8005da6: f7fa fa3d bl 8000224 <__adddf3> 8005daa: 3d01 subs r5, #1 8005dac: e75c b.n 8005c68 <__kernel_rem_pio2+0x530> 8005dae: 9b04 ldr r3, [sp, #16] 8005db0: 9a04 ldr r2, [sp, #16] 8005db2: 601f str r7, [r3, #0] 8005db4: f108 4400 add.w r4, r8, #2147483648 ; 0x80000000 8005db8: 605c str r4, [r3, #4] 8005dba: 609d str r5, [r3, #8] 8005dbc: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 8005dc0: 60d3 str r3, [r2, #12] 8005dc2: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 8005dc6: 6110 str r0, [r2, #16] 8005dc8: 6153 str r3, [r2, #20] 8005dca: e727 b.n 8005c1c <__kernel_rem_pio2+0x4e4> 8005dcc: 41700000 .word 0x41700000 8005dd0: 3e700000 .word 0x3e700000 8005dd4: 00000000 .word 0x00000000 08005dd8 <__kernel_tan>: 8005dd8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005ddc: ed2d 8b06 vpush {d8-d10} 8005de0: ec5b ab10 vmov sl, fp, d0 8005de4: 4be0 ldr r3, [pc, #896] ; (8006168 <__kernel_tan+0x390>) 8005de6: b083 sub sp, #12 8005de8: f02b 4700 bic.w r7, fp, #2147483648 ; 0x80000000 8005dec: 429f cmp r7, r3 8005dee: ec59 8b11 vmov r8, r9, d1 8005df2: 4606 mov r6, r0 8005df4: f8cd b000 str.w fp, [sp] 8005df8: dc61 bgt.n 8005ebe <__kernel_tan+0xe6> 8005dfa: ee10 0a10 vmov r0, s0 8005dfe: 4659 mov r1, fp 8005e00: f7fa fe60 bl 8000ac4 <__aeabi_d2iz> 8005e04: 4605 mov r5, r0 8005e06: 2800 cmp r0, #0 8005e08: f040 8083 bne.w 8005f12 <__kernel_tan+0x13a> 8005e0c: 1c73 adds r3, r6, #1 8005e0e: 4652 mov r2, sl 8005e10: 4313 orrs r3, r2 8005e12: 433b orrs r3, r7 8005e14: d112 bne.n 8005e3c <__kernel_tan+0x64> 8005e16: ec4b ab10 vmov d0, sl, fp 8005e1a: f000 f9e7 bl 80061ec 8005e1e: 49d3 ldr r1, [pc, #844] ; (800616c <__kernel_tan+0x394>) 8005e20: ec53 2b10 vmov r2, r3, d0 8005e24: 2000 movs r0, #0 8005e26: f7fa fcdd bl 80007e4 <__aeabi_ddiv> 8005e2a: 4682 mov sl, r0 8005e2c: 468b mov fp, r1 8005e2e: ec4b ab10 vmov d0, sl, fp 8005e32: b003 add sp, #12 8005e34: ecbd 8b06 vpop {d8-d10} 8005e38: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8005e3c: 2e01 cmp r6, #1 8005e3e: d0f6 beq.n 8005e2e <__kernel_tan+0x56> 8005e40: 4642 mov r2, r8 8005e42: 464b mov r3, r9 8005e44: 4650 mov r0, sl 8005e46: 4659 mov r1, fp 8005e48: f7fa f9ec bl 8000224 <__adddf3> 8005e4c: 4602 mov r2, r0 8005e4e: 460b mov r3, r1 8005e50: 460f mov r7, r1 8005e52: 2000 movs r0, #0 8005e54: 49c6 ldr r1, [pc, #792] ; (8006170 <__kernel_tan+0x398>) 8005e56: f7fa fcc5 bl 80007e4 <__aeabi_ddiv> 8005e5a: e9cd 0100 strd r0, r1, [sp] 8005e5e: e9dd 2300 ldrd r2, r3, [sp] 8005e62: 462e mov r6, r5 8005e64: 4652 mov r2, sl 8005e66: 462c mov r4, r5 8005e68: 4630 mov r0, r6 8005e6a: 461d mov r5, r3 8005e6c: 4639 mov r1, r7 8005e6e: 465b mov r3, fp 8005e70: f7fa f9d6 bl 8000220 <__aeabi_dsub> 8005e74: 4602 mov r2, r0 8005e76: 460b mov r3, r1 8005e78: 4640 mov r0, r8 8005e7a: 4649 mov r1, r9 8005e7c: f7fa f9d0 bl 8000220 <__aeabi_dsub> 8005e80: 4632 mov r2, r6 8005e82: 462b mov r3, r5 8005e84: f7fa fb84 bl 8000590 <__aeabi_dmul> 8005e88: 4632 mov r2, r6 8005e8a: 4680 mov r8, r0 8005e8c: 4689 mov r9, r1 8005e8e: 462b mov r3, r5 8005e90: 4630 mov r0, r6 8005e92: 4639 mov r1, r7 8005e94: f7fa fb7c bl 8000590 <__aeabi_dmul> 8005e98: 4bb4 ldr r3, [pc, #720] ; (800616c <__kernel_tan+0x394>) 8005e9a: 2200 movs r2, #0 8005e9c: f7fa f9c2 bl 8000224 <__adddf3> 8005ea0: 4602 mov r2, r0 8005ea2: 460b mov r3, r1 8005ea4: 4640 mov r0, r8 8005ea6: 4649 mov r1, r9 8005ea8: f7fa f9bc bl 8000224 <__adddf3> 8005eac: e9dd 2300 ldrd r2, r3, [sp] 8005eb0: f7fa fb6e bl 8000590 <__aeabi_dmul> 8005eb4: 4622 mov r2, r4 8005eb6: 462b mov r3, r5 8005eb8: f7fa f9b4 bl 8000224 <__adddf3> 8005ebc: e7b5 b.n 8005e2a <__kernel_tan+0x52> 8005ebe: 4bad ldr r3, [pc, #692] ; (8006174 <__kernel_tan+0x39c>) 8005ec0: 429f cmp r7, r3 8005ec2: dd26 ble.n 8005f12 <__kernel_tan+0x13a> 8005ec4: 9b00 ldr r3, [sp, #0] 8005ec6: 2b00 cmp r3, #0 8005ec8: da09 bge.n 8005ede <__kernel_tan+0x106> 8005eca: f10b 4300 add.w r3, fp, #2147483648 ; 0x80000000 8005ece: 469b mov fp, r3 8005ed0: ee10 aa10 vmov sl, s0 8005ed4: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 8005ed8: ee11 8a10 vmov r8, s2 8005edc: 4699 mov r9, r3 8005ede: 4652 mov r2, sl 8005ee0: 465b mov r3, fp 8005ee2: a183 add r1, pc, #524 ; (adr r1, 80060f0 <__kernel_tan+0x318>) 8005ee4: e9d1 0100 ldrd r0, r1, [r1] 8005ee8: f7fa f99a bl 8000220 <__aeabi_dsub> 8005eec: 4642 mov r2, r8 8005eee: 464b mov r3, r9 8005ef0: 4604 mov r4, r0 8005ef2: 460d mov r5, r1 8005ef4: a180 add r1, pc, #512 ; (adr r1, 80060f8 <__kernel_tan+0x320>) 8005ef6: e9d1 0100 ldrd r0, r1, [r1] 8005efa: f7fa f991 bl 8000220 <__aeabi_dsub> 8005efe: 4622 mov r2, r4 8005f00: 462b mov r3, r5 8005f02: f7fa f98f bl 8000224 <__adddf3> 8005f06: f04f 0800 mov.w r8, #0 8005f0a: 4682 mov sl, r0 8005f0c: 468b mov fp, r1 8005f0e: f04f 0900 mov.w r9, #0 8005f12: 4652 mov r2, sl 8005f14: 465b mov r3, fp 8005f16: 4650 mov r0, sl 8005f18: 4659 mov r1, fp 8005f1a: f7fa fb39 bl 8000590 <__aeabi_dmul> 8005f1e: 4602 mov r2, r0 8005f20: 460b mov r3, r1 8005f22: ec43 2b18 vmov d8, r2, r3 8005f26: f7fa fb33 bl 8000590 <__aeabi_dmul> 8005f2a: ec53 2b18 vmov r2, r3, d8 8005f2e: 4604 mov r4, r0 8005f30: 460d mov r5, r1 8005f32: 4650 mov r0, sl 8005f34: 4659 mov r1, fp 8005f36: f7fa fb2b bl 8000590 <__aeabi_dmul> 8005f3a: a371 add r3, pc, #452 ; (adr r3, 8006100 <__kernel_tan+0x328>) 8005f3c: e9d3 2300 ldrd r2, r3, [r3] 8005f40: ec41 0b19 vmov d9, r0, r1 8005f44: 4620 mov r0, r4 8005f46: 4629 mov r1, r5 8005f48: f7fa fb22 bl 8000590 <__aeabi_dmul> 8005f4c: a36e add r3, pc, #440 ; (adr r3, 8006108 <__kernel_tan+0x330>) 8005f4e: e9d3 2300 ldrd r2, r3, [r3] 8005f52: f7fa f967 bl 8000224 <__adddf3> 8005f56: 4622 mov r2, r4 8005f58: 462b mov r3, r5 8005f5a: f7fa fb19 bl 8000590 <__aeabi_dmul> 8005f5e: a36c add r3, pc, #432 ; (adr r3, 8006110 <__kernel_tan+0x338>) 8005f60: e9d3 2300 ldrd r2, r3, [r3] 8005f64: f7fa f95e bl 8000224 <__adddf3> 8005f68: 4622 mov r2, r4 8005f6a: 462b mov r3, r5 8005f6c: f7fa fb10 bl 8000590 <__aeabi_dmul> 8005f70: a369 add r3, pc, #420 ; (adr r3, 8006118 <__kernel_tan+0x340>) 8005f72: e9d3 2300 ldrd r2, r3, [r3] 8005f76: f7fa f955 bl 8000224 <__adddf3> 8005f7a: 4622 mov r2, r4 8005f7c: 462b mov r3, r5 8005f7e: f7fa fb07 bl 8000590 <__aeabi_dmul> 8005f82: a367 add r3, pc, #412 ; (adr r3, 8006120 <__kernel_tan+0x348>) 8005f84: e9d3 2300 ldrd r2, r3, [r3] 8005f88: f7fa f94c bl 8000224 <__adddf3> 8005f8c: 4622 mov r2, r4 8005f8e: 462b mov r3, r5 8005f90: f7fa fafe bl 8000590 <__aeabi_dmul> 8005f94: a364 add r3, pc, #400 ; (adr r3, 8006128 <__kernel_tan+0x350>) 8005f96: e9d3 2300 ldrd r2, r3, [r3] 8005f9a: f7fa f943 bl 8000224 <__adddf3> 8005f9e: ec53 2b18 vmov r2, r3, d8 8005fa2: f7fa faf5 bl 8000590 <__aeabi_dmul> 8005fa6: a362 add r3, pc, #392 ; (adr r3, 8006130 <__kernel_tan+0x358>) 8005fa8: e9d3 2300 ldrd r2, r3, [r3] 8005fac: ec41 0b1a vmov d10, r0, r1 8005fb0: 4620 mov r0, r4 8005fb2: 4629 mov r1, r5 8005fb4: f7fa faec bl 8000590 <__aeabi_dmul> 8005fb8: a35f add r3, pc, #380 ; (adr r3, 8006138 <__kernel_tan+0x360>) 8005fba: e9d3 2300 ldrd r2, r3, [r3] 8005fbe: f7fa f931 bl 8000224 <__adddf3> 8005fc2: 4622 mov r2, r4 8005fc4: 462b mov r3, r5 8005fc6: f7fa fae3 bl 8000590 <__aeabi_dmul> 8005fca: a35d add r3, pc, #372 ; (adr r3, 8006140 <__kernel_tan+0x368>) 8005fcc: e9d3 2300 ldrd r2, r3, [r3] 8005fd0: f7fa f928 bl 8000224 <__adddf3> 8005fd4: 4622 mov r2, r4 8005fd6: 462b mov r3, r5 8005fd8: f7fa fada bl 8000590 <__aeabi_dmul> 8005fdc: a35a add r3, pc, #360 ; (adr r3, 8006148 <__kernel_tan+0x370>) 8005fde: e9d3 2300 ldrd r2, r3, [r3] 8005fe2: f7fa f91f bl 8000224 <__adddf3> 8005fe6: 4622 mov r2, r4 8005fe8: 462b mov r3, r5 8005fea: f7fa fad1 bl 8000590 <__aeabi_dmul> 8005fee: a358 add r3, pc, #352 ; (adr r3, 8006150 <__kernel_tan+0x378>) 8005ff0: e9d3 2300 ldrd r2, r3, [r3] 8005ff4: f7fa f916 bl 8000224 <__adddf3> 8005ff8: 4622 mov r2, r4 8005ffa: 462b mov r3, r5 8005ffc: f7fa fac8 bl 8000590 <__aeabi_dmul> 8006000: a355 add r3, pc, #340 ; (adr r3, 8006158 <__kernel_tan+0x380>) 8006002: e9d3 2300 ldrd r2, r3, [r3] 8006006: f7fa f90d bl 8000224 <__adddf3> 800600a: 4602 mov r2, r0 800600c: 460b mov r3, r1 800600e: ec51 0b1a vmov r0, r1, d10 8006012: f7fa f907 bl 8000224 <__adddf3> 8006016: ec53 2b19 vmov r2, r3, d9 800601a: f7fa fab9 bl 8000590 <__aeabi_dmul> 800601e: 4642 mov r2, r8 8006020: 464b mov r3, r9 8006022: f7fa f8ff bl 8000224 <__adddf3> 8006026: ec53 2b18 vmov r2, r3, d8 800602a: f7fa fab1 bl 8000590 <__aeabi_dmul> 800602e: 4642 mov r2, r8 8006030: 464b mov r3, r9 8006032: f7fa f8f7 bl 8000224 <__adddf3> 8006036: a34a add r3, pc, #296 ; (adr r3, 8006160 <__kernel_tan+0x388>) 8006038: e9d3 2300 ldrd r2, r3, [r3] 800603c: 4604 mov r4, r0 800603e: 460d mov r5, r1 8006040: ec51 0b19 vmov r0, r1, d9 8006044: f7fa faa4 bl 8000590 <__aeabi_dmul> 8006048: 4622 mov r2, r4 800604a: 462b mov r3, r5 800604c: f7fa f8ea bl 8000224 <__adddf3> 8006050: 460b mov r3, r1 8006052: ec41 0b18 vmov d8, r0, r1 8006056: 4602 mov r2, r0 8006058: 4659 mov r1, fp 800605a: 4650 mov r0, sl 800605c: f7fa f8e2 bl 8000224 <__adddf3> 8006060: 4b44 ldr r3, [pc, #272] ; (8006174 <__kernel_tan+0x39c>) 8006062: 429f cmp r7, r3 8006064: 4604 mov r4, r0 8006066: 460d mov r5, r1 8006068: f340 8086 ble.w 8006178 <__kernel_tan+0x3a0> 800606c: 4630 mov r0, r6 800606e: f7fa fa25 bl 80004bc <__aeabi_i2d> 8006072: 4622 mov r2, r4 8006074: 4680 mov r8, r0 8006076: 4689 mov r9, r1 8006078: 462b mov r3, r5 800607a: 4620 mov r0, r4 800607c: 4629 mov r1, r5 800607e: f7fa fa87 bl 8000590 <__aeabi_dmul> 8006082: 4642 mov r2, r8 8006084: 4606 mov r6, r0 8006086: 460f mov r7, r1 8006088: 464b mov r3, r9 800608a: 4620 mov r0, r4 800608c: 4629 mov r1, r5 800608e: f7fa f8c9 bl 8000224 <__adddf3> 8006092: 4602 mov r2, r0 8006094: 460b mov r3, r1 8006096: 4630 mov r0, r6 8006098: 4639 mov r1, r7 800609a: f7fa fba3 bl 80007e4 <__aeabi_ddiv> 800609e: ec53 2b18 vmov r2, r3, d8 80060a2: f7fa f8bd bl 8000220 <__aeabi_dsub> 80060a6: 4602 mov r2, r0 80060a8: 460b mov r3, r1 80060aa: 4650 mov r0, sl 80060ac: 4659 mov r1, fp 80060ae: f7fa f8b7 bl 8000220 <__aeabi_dsub> 80060b2: 4602 mov r2, r0 80060b4: 460b mov r3, r1 80060b6: f7fa f8b5 bl 8000224 <__adddf3> 80060ba: 4602 mov r2, r0 80060bc: 460b mov r3, r1 80060be: 4640 mov r0, r8 80060c0: 4649 mov r1, r9 80060c2: f7fa f8ad bl 8000220 <__aeabi_dsub> 80060c6: 9b00 ldr r3, [sp, #0] 80060c8: ea4f 7aa3 mov.w sl, r3, asr #30 80060cc: f00a 0a02 and.w sl, sl, #2 80060d0: 4604 mov r4, r0 80060d2: f1ca 0001 rsb r0, sl, #1 80060d6: 460d mov r5, r1 80060d8: f7fa f9f0 bl 80004bc <__aeabi_i2d> 80060dc: 4602 mov r2, r0 80060de: 460b mov r3, r1 80060e0: 4620 mov r0, r4 80060e2: 4629 mov r1, r5 80060e4: f7fa fa54 bl 8000590 <__aeabi_dmul> 80060e8: e69f b.n 8005e2a <__kernel_tan+0x52> 80060ea: bf00 nop 80060ec: f3af 8000 nop.w 80060f0: 54442d18 .word 0x54442d18 80060f4: 3fe921fb .word 0x3fe921fb 80060f8: 33145c07 .word 0x33145c07 80060fc: 3c81a626 .word 0x3c81a626 8006100: 74bf7ad4 .word 0x74bf7ad4 8006104: 3efb2a70 .word 0x3efb2a70 8006108: 32f0a7e9 .word 0x32f0a7e9 800610c: 3f12b80f .word 0x3f12b80f 8006110: 1a8d1068 .word 0x1a8d1068 8006114: 3f3026f7 .word 0x3f3026f7 8006118: fee08315 .word 0xfee08315 800611c: 3f57dbc8 .word 0x3f57dbc8 8006120: e96e8493 .word 0xe96e8493 8006124: 3f8226e3 .word 0x3f8226e3 8006128: 1bb341fe .word 0x1bb341fe 800612c: 3faba1ba .word 0x3faba1ba 8006130: db605373 .word 0xdb605373 8006134: bef375cb .word 0xbef375cb 8006138: a03792a6 .word 0xa03792a6 800613c: 3f147e88 .word 0x3f147e88 8006140: f2f26501 .word 0xf2f26501 8006144: 3f4344d8 .word 0x3f4344d8 8006148: c9560328 .word 0xc9560328 800614c: 3f6d6d22 .word 0x3f6d6d22 8006150: 8406d637 .word 0x8406d637 8006154: 3f9664f4 .word 0x3f9664f4 8006158: 1110fe7a .word 0x1110fe7a 800615c: 3fc11111 .word 0x3fc11111 8006160: 55555563 .word 0x55555563 8006164: 3fd55555 .word 0x3fd55555 8006168: 3e2fffff .word 0x3e2fffff 800616c: 3ff00000 .word 0x3ff00000 8006170: bff00000 .word 0xbff00000 8006174: 3fe59427 .word 0x3fe59427 8006178: 2e01 cmp r6, #1 800617a: d02f beq.n 80061dc <__kernel_tan+0x404> 800617c: 460f mov r7, r1 800617e: 4602 mov r2, r0 8006180: 460b mov r3, r1 8006182: 4689 mov r9, r1 8006184: 2000 movs r0, #0 8006186: 4917 ldr r1, [pc, #92] ; (80061e4 <__kernel_tan+0x40c>) 8006188: f7fa fb2c bl 80007e4 <__aeabi_ddiv> 800618c: 2600 movs r6, #0 800618e: e9cd 0100 strd r0, r1, [sp] 8006192: 4652 mov r2, sl 8006194: 465b mov r3, fp 8006196: 4630 mov r0, r6 8006198: 4639 mov r1, r7 800619a: f7fa f841 bl 8000220 <__aeabi_dsub> 800619e: e9dd 4500 ldrd r4, r5, [sp] 80061a2: 4602 mov r2, r0 80061a4: 460b mov r3, r1 80061a6: ec51 0b18 vmov r0, r1, d8 80061aa: f7fa f839 bl 8000220 <__aeabi_dsub> 80061ae: 4632 mov r2, r6 80061b0: 462b mov r3, r5 80061b2: f7fa f9ed bl 8000590 <__aeabi_dmul> 80061b6: 46b0 mov r8, r6 80061b8: 460f mov r7, r1 80061ba: 4642 mov r2, r8 80061bc: 462b mov r3, r5 80061be: 4634 mov r4, r6 80061c0: 4649 mov r1, r9 80061c2: 4606 mov r6, r0 80061c4: 4640 mov r0, r8 80061c6: f7fa f9e3 bl 8000590 <__aeabi_dmul> 80061ca: 4b07 ldr r3, [pc, #28] ; (80061e8 <__kernel_tan+0x410>) 80061cc: 2200 movs r2, #0 80061ce: f7fa f829 bl 8000224 <__adddf3> 80061d2: 4602 mov r2, r0 80061d4: 460b mov r3, r1 80061d6: 4630 mov r0, r6 80061d8: 4639 mov r1, r7 80061da: e665 b.n 8005ea8 <__kernel_tan+0xd0> 80061dc: 4682 mov sl, r0 80061de: 468b mov fp, r1 80061e0: e625 b.n 8005e2e <__kernel_tan+0x56> 80061e2: bf00 nop 80061e4: bff00000 .word 0xbff00000 80061e8: 3ff00000 .word 0x3ff00000 080061ec : 80061ec: ec51 0b10 vmov r0, r1, d0 80061f0: ee10 2a10 vmov r2, s0 80061f4: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 80061f8: ec43 2b10 vmov d0, r2, r3 80061fc: 4770 bx lr ... 08006200 : 8006200: b570 push {r4, r5, r6, lr} 8006202: ec55 4b10 vmov r4, r5, d0 8006206: f3c5 510a ubfx r1, r5, #20, #11 800620a: 4606 mov r6, r0 800620c: 462b mov r3, r5 800620e: b999 cbnz r1, 8006238 8006210: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 8006214: 4323 orrs r3, r4 8006216: d03f beq.n 8006298 8006218: 4b35 ldr r3, [pc, #212] ; (80062f0 ) 800621a: 4629 mov r1, r5 800621c: ee10 0a10 vmov r0, s0 8006220: 2200 movs r2, #0 8006222: f7fa f9b5 bl 8000590 <__aeabi_dmul> 8006226: 4b33 ldr r3, [pc, #204] ; (80062f4 ) 8006228: 429e cmp r6, r3 800622a: 4604 mov r4, r0 800622c: 460d mov r5, r1 800622e: da10 bge.n 8006252 8006230: a327 add r3, pc, #156 ; (adr r3, 80062d0 ) 8006232: e9d3 2300 ldrd r2, r3, [r3] 8006236: e01f b.n 8006278 8006238: f240 72ff movw r2, #2047 ; 0x7ff 800623c: 4291 cmp r1, r2 800623e: d10c bne.n 800625a 8006240: ee10 2a10 vmov r2, s0 8006244: 4620 mov r0, r4 8006246: 4629 mov r1, r5 8006248: f7f9 ffec bl 8000224 <__adddf3> 800624c: 4604 mov r4, r0 800624e: 460d mov r5, r1 8006250: e022 b.n 8006298 8006252: 460b mov r3, r1 8006254: f3c1 510a ubfx r1, r1, #20, #11 8006258: 3936 subs r1, #54 ; 0x36 800625a: f24c 3250 movw r2, #50000 ; 0xc350 800625e: 4296 cmp r6, r2 8006260: dd0d ble.n 800627e 8006262: 2d00 cmp r5, #0 8006264: a11c add r1, pc, #112 ; (adr r1, 80062d8 ) 8006266: e9d1 0100 ldrd r0, r1, [r1] 800626a: da02 bge.n 8006272 800626c: a11c add r1, pc, #112 ; (adr r1, 80062e0 ) 800626e: e9d1 0100 ldrd r0, r1, [r1] 8006272: a319 add r3, pc, #100 ; (adr r3, 80062d8 ) 8006274: e9d3 2300 ldrd r2, r3, [r3] 8006278: f7fa f98a bl 8000590 <__aeabi_dmul> 800627c: e7e6 b.n 800624c 800627e: 1872 adds r2, r6, r1 8006280: f240 71fe movw r1, #2046 ; 0x7fe 8006284: 428a cmp r2, r1 8006286: dcec bgt.n 8006262 8006288: 2a00 cmp r2, #0 800628a: dd08 ble.n 800629e 800628c: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 8006290: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 8006294: ea43 5502 orr.w r5, r3, r2, lsl #20 8006298: ec45 4b10 vmov d0, r4, r5 800629c: bd70 pop {r4, r5, r6, pc} 800629e: f112 0f35 cmn.w r2, #53 ; 0x35 80062a2: da08 bge.n 80062b6 80062a4: 2d00 cmp r5, #0 80062a6: a10a add r1, pc, #40 ; (adr r1, 80062d0 ) 80062a8: e9d1 0100 ldrd r0, r1, [r1] 80062ac: dac0 bge.n 8006230 80062ae: a10e add r1, pc, #56 ; (adr r1, 80062e8 ) 80062b0: e9d1 0100 ldrd r0, r1, [r1] 80062b4: e7bc b.n 8006230 80062b6: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 80062ba: 3236 adds r2, #54 ; 0x36 80062bc: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 80062c0: ea43 5102 orr.w r1, r3, r2, lsl #20 80062c4: 4620 mov r0, r4 80062c6: 4b0c ldr r3, [pc, #48] ; (80062f8 ) 80062c8: 2200 movs r2, #0 80062ca: e7d5 b.n 8006278 80062cc: f3af 8000 nop.w 80062d0: c2f8f359 .word 0xc2f8f359 80062d4: 01a56e1f .word 0x01a56e1f 80062d8: 8800759c .word 0x8800759c 80062dc: 7e37e43c .word 0x7e37e43c 80062e0: 8800759c .word 0x8800759c 80062e4: fe37e43c .word 0xfe37e43c 80062e8: c2f8f359 .word 0xc2f8f359 80062ec: 81a56e1f .word 0x81a56e1f 80062f0: 43500000 .word 0x43500000 80062f4: ffff3cb0 .word 0xffff3cb0 80062f8: 3c900000 .word 0x3c900000 80062fc: 00000000 .word 0x00000000 08006300 : 8006300: ec51 0b10 vmov r0, r1, d0 8006304: f3c1 530a ubfx r3, r1, #20, #11 8006308: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800630c: f2a3 36ff subw r6, r3, #1023 ; 0x3ff 8006310: 2e13 cmp r6, #19 8006312: ee10 5a10 vmov r5, s0 8006316: ee10 8a10 vmov r8, s0 800631a: 460c mov r4, r1 800631c: dc31 bgt.n 8006382 800631e: 2e00 cmp r6, #0 8006320: da14 bge.n 800634c 8006322: a333 add r3, pc, #204 ; (adr r3, 80063f0 ) 8006324: e9d3 2300 ldrd r2, r3, [r3] 8006328: f7f9 ff7c bl 8000224 <__adddf3> 800632c: 2200 movs r2, #0 800632e: 2300 movs r3, #0 8006330: f7fa fbbe bl 8000ab0 <__aeabi_dcmpgt> 8006334: b138 cbz r0, 8006346 8006336: 2c00 cmp r4, #0 8006338: da53 bge.n 80063e2 800633a: f024 4400 bic.w r4, r4, #2147483648 ; 0x80000000 800633e: 4325 orrs r5, r4 8006340: d052 beq.n 80063e8 8006342: 4c2d ldr r4, [pc, #180] ; (80063f8 ) 8006344: 2500 movs r5, #0 8006346: 4621 mov r1, r4 8006348: 4628 mov r0, r5 800634a: e024 b.n 8006396 800634c: 4f2b ldr r7, [pc, #172] ; (80063fc ) 800634e: 4137 asrs r7, r6 8006350: ea01 0307 and.w r3, r1, r7 8006354: 4303 orrs r3, r0 8006356: d01e beq.n 8006396 8006358: a325 add r3, pc, #148 ; (adr r3, 80063f0 ) 800635a: e9d3 2300 ldrd r2, r3, [r3] 800635e: f7f9 ff61 bl 8000224 <__adddf3> 8006362: 2200 movs r2, #0 8006364: 2300 movs r3, #0 8006366: f7fa fba3 bl 8000ab0 <__aeabi_dcmpgt> 800636a: 2800 cmp r0, #0 800636c: d0eb beq.n 8006346 800636e: 2c00 cmp r4, #0 8006370: bfbe ittt lt 8006372: f44f 1380 movlt.w r3, #1048576 ; 0x100000 8006376: 4133 asrlt r3, r6 8006378: 18e4 addlt r4, r4, r3 800637a: ea24 0407 bic.w r4, r4, r7 800637e: 2500 movs r5, #0 8006380: e7e1 b.n 8006346 8006382: 2e33 cmp r6, #51 ; 0x33 8006384: dd0b ble.n 800639e 8006386: f5b6 6f80 cmp.w r6, #1024 ; 0x400 800638a: d104 bne.n 8006396 800638c: ee10 2a10 vmov r2, s0 8006390: 460b mov r3, r1 8006392: f7f9 ff47 bl 8000224 <__adddf3> 8006396: ec41 0b10 vmov d0, r0, r1 800639a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800639e: f2a3 4313 subw r3, r3, #1043 ; 0x413 80063a2: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff 80063a6: 40df lsrs r7, r3 80063a8: 4238 tst r0, r7 80063aa: d0f4 beq.n 8006396 80063ac: a310 add r3, pc, #64 ; (adr r3, 80063f0 ) 80063ae: e9d3 2300 ldrd r2, r3, [r3] 80063b2: f7f9 ff37 bl 8000224 <__adddf3> 80063b6: 2200 movs r2, #0 80063b8: 2300 movs r3, #0 80063ba: f7fa fb79 bl 8000ab0 <__aeabi_dcmpgt> 80063be: 2800 cmp r0, #0 80063c0: d0c1 beq.n 8006346 80063c2: 2c00 cmp r4, #0 80063c4: da0a bge.n 80063dc 80063c6: 2e14 cmp r6, #20 80063c8: d101 bne.n 80063ce 80063ca: 3401 adds r4, #1 80063cc: e006 b.n 80063dc 80063ce: f1c6 0634 rsb r6, r6, #52 ; 0x34 80063d2: 2301 movs r3, #1 80063d4: 40b3 lsls r3, r6 80063d6: 441d add r5, r3 80063d8: 45a8 cmp r8, r5 80063da: d8f6 bhi.n 80063ca 80063dc: ea25 0507 bic.w r5, r5, r7 80063e0: e7b1 b.n 8006346 80063e2: 2500 movs r5, #0 80063e4: 462c mov r4, r5 80063e6: e7ae b.n 8006346 80063e8: f04f 4400 mov.w r4, #2147483648 ; 0x80000000 80063ec: e7ab b.n 8006346 80063ee: bf00 nop 80063f0: 8800759c .word 0x8800759c 80063f4: 7e37e43c .word 0x7e37e43c 80063f8: bff00000 .word 0xbff00000 80063fc: 000fffff .word 0x000fffff 08006400 : 8006400: 4402 add r2, r0 8006402: 4603 mov r3, r0 8006404: 4293 cmp r3, r2 8006406: d100 bne.n 800640a 8006408: 4770 bx lr 800640a: f803 1b01 strb.w r1, [r3], #1 800640e: e7f9 b.n 8006404 08006410 <__errno>: 8006410: 4b01 ldr r3, [pc, #4] ; (8006418 <__errno+0x8>) 8006412: 6818 ldr r0, [r3, #0] 8006414: 4770 bx lr 8006416: bf00 nop 8006418: 20000058 .word 0x20000058 0800641c <__libc_init_array>: 800641c: b570 push {r4, r5, r6, lr} 800641e: 4d0d ldr r5, [pc, #52] ; (8006454 <__libc_init_array+0x38>) 8006420: 4c0d ldr r4, [pc, #52] ; (8006458 <__libc_init_array+0x3c>) 8006422: 1b64 subs r4, r4, r5 8006424: 10a4 asrs r4, r4, #2 8006426: 2600 movs r6, #0 8006428: 42a6 cmp r6, r4 800642a: d109 bne.n 8006440 <__libc_init_array+0x24> 800642c: 4d0b ldr r5, [pc, #44] ; (800645c <__libc_init_array+0x40>) 800642e: 4c0c ldr r4, [pc, #48] ; (8006460 <__libc_init_array+0x44>) 8006430: f000 f872 bl 8006518 <_init> 8006434: 1b64 subs r4, r4, r5 8006436: 10a4 asrs r4, r4, #2 8006438: 2600 movs r6, #0 800643a: 42a6 cmp r6, r4 800643c: d105 bne.n 800644a <__libc_init_array+0x2e> 800643e: bd70 pop {r4, r5, r6, pc} 8006440: f855 3b04 ldr.w r3, [r5], #4 8006444: 4798 blx r3 8006446: 3601 adds r6, #1 8006448: e7ee b.n 8006428 <__libc_init_array+0xc> 800644a: f855 3b04 ldr.w r3, [r5], #4 800644e: 4798 blx r3 8006450: 3601 adds r6, #1 8006452: e7f2 b.n 800643a <__libc_init_array+0x1e> 8006454: 08008014 .word 0x08008014 8006458: 08008014 .word 0x08008014 800645c: 08008014 .word 0x08008014 8006460: 08008018 .word 0x08008018 08006464 : 8006464: b508 push {r3, lr} 8006466: 2006 movs r0, #6 8006468: f000 f82c bl 80064c4 800646c: 2001 movs r0, #1 800646e: f7fc f983 bl 8002778 <_exit> 08006472 <_raise_r>: 8006472: 291f cmp r1, #31 8006474: b538 push {r3, r4, r5, lr} 8006476: 4604 mov r4, r0 8006478: 460d mov r5, r1 800647a: d904 bls.n 8006486 <_raise_r+0x14> 800647c: 2316 movs r3, #22 800647e: 6003 str r3, [r0, #0] 8006480: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8006484: bd38 pop {r3, r4, r5, pc} 8006486: 6bc2 ldr r2, [r0, #60] ; 0x3c 8006488: b112 cbz r2, 8006490 <_raise_r+0x1e> 800648a: f852 3021 ldr.w r3, [r2, r1, lsl #2] 800648e: b94b cbnz r3, 80064a4 <_raise_r+0x32> 8006490: 4620 mov r0, r4 8006492: f000 f831 bl 80064f8 <_getpid_r> 8006496: 462a mov r2, r5 8006498: 4601 mov r1, r0 800649a: 4620 mov r0, r4 800649c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80064a0: f000 b818 b.w 80064d4 <_kill_r> 80064a4: 2b01 cmp r3, #1 80064a6: d00a beq.n 80064be <_raise_r+0x4c> 80064a8: 1c59 adds r1, r3, #1 80064aa: d103 bne.n 80064b4 <_raise_r+0x42> 80064ac: 2316 movs r3, #22 80064ae: 6003 str r3, [r0, #0] 80064b0: 2001 movs r0, #1 80064b2: e7e7 b.n 8006484 <_raise_r+0x12> 80064b4: 2400 movs r4, #0 80064b6: f842 4025 str.w r4, [r2, r5, lsl #2] 80064ba: 4628 mov r0, r5 80064bc: 4798 blx r3 80064be: 2000 movs r0, #0 80064c0: e7e0 b.n 8006484 <_raise_r+0x12> ... 080064c4 : 80064c4: 4b02 ldr r3, [pc, #8] ; (80064d0 ) 80064c6: 4601 mov r1, r0 80064c8: 6818 ldr r0, [r3, #0] 80064ca: f7ff bfd2 b.w 8006472 <_raise_r> 80064ce: bf00 nop 80064d0: 20000058 .word 0x20000058 080064d4 <_kill_r>: 80064d4: b538 push {r3, r4, r5, lr} 80064d6: 4d07 ldr r5, [pc, #28] ; (80064f4 <_kill_r+0x20>) 80064d8: 2300 movs r3, #0 80064da: 4604 mov r4, r0 80064dc: 4608 mov r0, r1 80064de: 4611 mov r1, r2 80064e0: 602b str r3, [r5, #0] 80064e2: f7fc f941 bl 8002768 <_kill> 80064e6: 1c43 adds r3, r0, #1 80064e8: d102 bne.n 80064f0 <_kill_r+0x1c> 80064ea: 682b ldr r3, [r5, #0] 80064ec: b103 cbz r3, 80064f0 <_kill_r+0x1c> 80064ee: 6023 str r3, [r4, #0] 80064f0: bd38 pop {r3, r4, r5, pc} 80064f2: bf00 nop 80064f4: 200077c4 .word 0x200077c4 080064f8 <_getpid_r>: 80064f8: f7fc b934 b.w 8002764 <_getpid> 080064fc : 80064fc: 440a add r2, r1 80064fe: 4291 cmp r1, r2 8006500: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 8006504: d100 bne.n 8006508 8006506: 4770 bx lr 8006508: b510 push {r4, lr} 800650a: f811 4b01 ldrb.w r4, [r1], #1 800650e: f803 4f01 strb.w r4, [r3, #1]! 8006512: 4291 cmp r1, r2 8006514: d1f9 bne.n 800650a 8006516: bd10 pop {r4, pc} 08006518 <_init>: 8006518: b5f8 push {r3, r4, r5, r6, r7, lr} 800651a: bf00 nop 800651c: bcf8 pop {r3, r4, r5, r6, r7} 800651e: bc08 pop {r3} 8006520: 469e mov lr, r3 8006522: 4770 bx lr 08006524 <_fini>: 8006524: b5f8 push {r3, r4, r5, r6, r7, lr} 8006526: bf00 nop 8006528: bcf8 pop {r3, r4, r5, r6, r7} 800652a: bc08 pop {r3} 800652c: 469e mov lr, r3 800652e: 4770 bx lr ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/makefile ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (11.3.rel1) ################################################################################ -include ../makefile.init RM := rm -rf # All of the sources participating in the build are defined here -include sources.mk -include Drivers/STM32G4xx_HAL_Driver/Src/subdir.mk -include Core/Startup/subdir.mk -include Core/Src/subdir.mk -include Core/Inc/subdir.mk -include objects.mk ifneq ($(MAKECMDGOALS),clean) ifneq ($(strip $(CC_DEPS)),) -include $(CC_DEPS) endif ifneq ($(strip $(C++_DEPS)),) -include $(C++_DEPS) endif ifneq ($(strip $(CCM_DEPS)),) -include $(CCM_DEPS) endif ifneq ($(strip $(C_UPPER_DEPS)),) -include $(C_UPPER_DEPS) endif ifneq ($(strip $(CXX_DEPS)),) -include $(CXX_DEPS) endif ifneq ($(strip $(S_DEPS)),) -include $(S_DEPS) endif ifneq ($(strip $(S_UPPER_DEPS)),) -include $(S_UPPER_DEPS) endif ifneq ($(strip $(CXXM_DEPS)),) -include $(CXXM_DEPS) endif ifneq ($(strip $(C++M_DEPS)),) -include $(C++M_DEPS) endif ifneq ($(strip $(C_DEPS)),) -include $(C_DEPS) endif ifneq ($(strip $(CPP_DEPS)),) -include $(CPP_DEPS) endif endif -include ../makefile.defs OPTIONAL_TOOL_DEPS := \ $(wildcard ../makefile.defs) \ $(wildcard ../makefile.init) \ $(wildcard ../makefile.targets) \ BUILD_ARTIFACT_NAME := chorus_G431 BUILD_ARTIFACT_EXTENSION := elf BUILD_ARTIFACT_PREFIX := BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) # Add inputs and outputs from these tool invocations to the build variables EXECUTABLES += \ chorus_G431.elf \ MAP_FILES += \ chorus_G431.map \ SIZE_OUTPUT += \ default.size.stdout \ OBJDUMP_LIST += \ chorus_G431.list \ # All Target all: main-build # Main-build Target main-build: chorus_G431.elf secondary-outputs # Tool invocations chorus_G431.elf chorus_G431.map: $(OBJS) $(USER_OBJS) /Users/chrismcdowell/Desktop/Super/super_fw_2023/chorus_G431/STM32G431KBUX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-g++ -o "chorus_G431.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/Users/chrismcdowell/Desktop/Super/super_fw_2023/chorus_G431/STM32G431KBUX_FLASH.ld" --specs=nosys.specs -Wl,-Map="chorus_G431.map" -Wl,--gc-sections -static -fcommon --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group @echo 'Finished building target: $@' @echo ' ' default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-size $(EXECUTABLES) @echo 'Finished building: $@' @echo ' ' chorus_G431.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) arm-none-eabi-objdump -h -S $(EXECUTABLES) > "chorus_G431.list" @echo 'Finished building: $@' @echo ' ' # Other Targets clean: -$(RM) chorus_G431.elf chorus_G431.list chorus_G431.map default.size.stdout -@echo ' ' secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) fail-specified-linker-script-missing: @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' @exit 2 warn-no-linker-script-specified: @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' .PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified -include ../makefile.targets ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/objects.list ================================================ "./Core/Src/adc.o" "./Core/Src/c_filters.o" "./Core/Src/chorus.o" "./Core/Src/dac.o" "./Core/Src/dma.o" "./Core/Src/dynamic_smooth.o" "./Core/Src/float_expo_table.o" "./Core/Src/gpio.o" "./Core/Src/lerp.o" "./Core/Src/main.o" "./Core/Src/stm32g4xx_hal_msp.o" "./Core/Src/stm32g4xx_it.o" "./Core/Src/super_filters.o" "./Core/Src/syscalls.o" "./Core/Src/sysmem.o" "./Core/Src/system_stm32g4xx.o" "./Core/Src/tim.o" "./Core/Startup/startup_stm32g431kbux.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o" "./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.o" ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/objects.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (11.3.rel1) ################################################################################ USER_OBJS := LIBS := ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Debug/sources.mk ================================================ ################################################################################ # Automatically-generated file. Do not edit! # Toolchain: GNU Tools for STM32 (11.3.rel1) ################################################################################ C++M_SRCS := CPP_SRCS := S_UPPER_SRCS := O_SRCS := ELF_SRCS := C_UPPER_SRCS := CXX_SRCS := CCM_SRCS := C++_SRCS := OBJ_SRCS := S_SRCS := CC_SRCS := C_SRCS := CXXM_SRCS := CYCLO_FILES := OBJDUMP_LIST := CCM_DEPS := C_UPPER_DEPS := S_DEPS := CXXM_DEPS := C_DEPS := CC_DEPS := SIZE_OUTPUT := C++_DEPS := SU_FILES := EXECUTABLES := OBJS := CXX_DEPS := MAP_FILES := S_UPPER_DEPS := C++M_DEPS := CPP_DEPS := # Every subdirectory with source files must be described here SUBDIRS := \ Core/Inc \ Core/Src \ Core/Startup \ Drivers/STM32G4xx_HAL_Driver/Src \ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h ================================================ /** ****************************************************************************** * @file stm32g431xx.h * @author MCD Application Team * @brief CMSIS STM32G431xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32g431xx * @{ */ #ifndef __STM32G431xx_H #define __STM32G431xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /*!< FPU present */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32G4XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers ***************************************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ USB_HP_IRQn = 19, /*!< USB HP Interrupt */ USB_LP_IRQn = 20, /*!< USB LP Interrupt */ FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupts */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ COMP4_IRQn = 65, /*!< COMP4 */ CRS_IRQn = 75, /*!< CRS global interrupt */ SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ RNG_IRQn = 90, /*!< RNG global interrupt */ LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ FMAC_IRQn = 101 /*!< FMAC global Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32g4xx.h" #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved, 0x1C */ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x2C */ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ uint32_t RESERVED3; /*!< Reserved, 0x44 */ uint32_t RESERVED4; /*!< Reserved, 0x48 */ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ uint32_t RESERVED9; /*!< Reserved, 0x0AC */ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ } ADC_Common_TypeDef; /** * @brief FD Controller Area Network */ typedef struct { __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ uint32_t RESERVED1; /*!< Reserved, 0x008 */ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ uint32_t RESERVED3; /*!< Reserved, 0x04C */ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ uint32_t RESERVED5; /*!< Reserved, 0x08C */ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ } FDCAN_GlobalTypeDef; /** * @brief FD Controller Area Network Configuration */ typedef struct { __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ } FDCAN_Config_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ } COMP_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED0; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ } CRS_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ __IO uint32_t RESERVED[2]; __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** * @brief DMA Multiplexer */ typedef struct { __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ }DMAMUX_Channel_TypeDef; typedef struct { __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ }DMAMUX_ChannelStatus_TypeDef; typedef struct { __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ }DMAMUX_RequestGen_TypeDef; typedef struct { __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ }DMAMUX_RequestGenStatus_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ } FLASH_TypeDef; /** * @brief FMAC */ typedef struct { __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ } FMAC_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ } IWDG_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ } LPTIM_TypeDef; /** * @brief Operational Amplifier (OPAMP) */ typedef struct { __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ } OPAMP_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ } RCC_TypeDef; /** * @brief Real-Time Clock */ /* * @brief Specific device feature definitions */ #define RTC_TAMP_INT_6_SUPPORT #define RTC_TAMP_INT_NB 4u #define RTC_TAMP_NB 3u #define RTC_BACKUP_NB 16u typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ } RTC_TypeDef; /** * @brief Tamper and backup registers */ typedef struct { __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ } TAMP_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ } SYSCFG_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ } USART_TypeDef; /** * @brief Universal Serial Bus Full Speed Device */ typedef struct { __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ __IO uint16_t RESERVED0; /*!< Reserved */ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ __IO uint16_t RESERVED1; /*!< Reserved */ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ __IO uint16_t RESERVED2; /*!< Reserved */ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ __IO uint16_t RESERVED3; /*!< Reserved */ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ __IO uint16_t RESERVED4; /*!< Reserved */ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ __IO uint16_t RESERVED5; /*!< Reserved */ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ __IO uint16_t RESERVED6; /*!< Reserved */ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ __IO uint16_t RESERVED7[17]; /*!< Reserved */ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ __IO uint16_t RESERVED8; /*!< Reserved */ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ __IO uint16_t RESERVED9; /*!< Reserved */ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ __IO uint16_t RESERVEDA; /*!< Reserved */ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ __IO uint16_t RESERVEDC; /*!< Reserved */ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ __IO uint16_t RESERVEDD; /*!< Reserved */ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ __IO uint16_t RESERVEDE; /*!< Reserved */ } USB_TypeDef; /** * @brief VREFBUF */ typedef struct { __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ } VREFBUF_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @brief CORDIC */ typedef struct { __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ } CORDIC_TypeDef; /** * @brief UCPD */ typedef struct { __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ } UCPD_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */ #define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */ #define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */ #define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */ #define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */ #define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */ #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE #define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */ #define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */ #define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) #define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) #define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ #define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ #define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) #define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) #define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) #define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) #define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) /*!< APB2 peripherals */ #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) #define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) #define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) #define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) #define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) #define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) #define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ #define DMA1_BASE (AHB1PERIPH_BASE) #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) #define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) #define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL) #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL) #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL) #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL) #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL) #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL) #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) /*!< AHB2 peripherals */ #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) #define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) #define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) #define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) #define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) #define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) #define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ #define DBGMCU_BASE (0xE0042000UL) #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) #define TAMP ((TAMP_TypeDef *) TAMP_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define USB ((USB_TypeDef *) USB_BASE) #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) #define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) #define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) #define COMP1 ((COMP_TypeDef *) COMP1_BASE) #define COMP2 ((COMP_TypeDef *) COMP2_BASE) #define COMP3 ((COMP_TypeDef *) COMP3_BASE) #define COMP4 ((COMP_TypeDef *) COMP4_BASE) #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) #define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FMAC ((FMAC_TypeDef *) FMAC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define DAC1 ((DAC_TypeDef *) DAC1_BASE) #define DAC3 ((DAC_TypeDef *) DAC3_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Hardware_Constant_Definition * @{ */ #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ /** * @} */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) */ #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ /******************** Bit definition for ADC_ISR register *******************/ #define ADC_ISR_ADRDY_Pos (0U) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOS_Pos (3U) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_JEOC_Pos (5U) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ #define ADC_ISR_JEOS_Pos (6U) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ #define ADC_ISR_AWD1_Pos (7U) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ #define ADC_ISR_AWD2_Pos (8U) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ #define ADC_ISR_AWD3_Pos (9U) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ /******************** Bit definition for ADC_IER register *******************/ #define ADC_IER_ADRDYIE_Pos (0U) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSIE_Pos (3U) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_JEOCIE_Pos (5U) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ #define ADC_IER_JEOSIE_Pos (6U) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ #define ADC_IER_AWD1IE_Pos (7U) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ #define ADC_IER_AWD2IE_Pos (8U) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ #define ADC_IER_AWD3IE_Pos (9U) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ #define ADC_IER_JQOVFIE_Pos (10U) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ /******************** Bit definition for ADC_CR register ********************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADDIS_Pos (1U) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_JADSTART_Pos (3U) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_JADSTP_Pos (5U) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ #define ADC_CR_ADVREGEN_Pos (28U) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ #define ADC_CR_DEEPPWD_Pos (29U) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ #define ADC_CR_ADCALDIF_Pos (30U) #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************** Bit definition for ADC_CFGR register ******************/ #define ADC_CFGR_DMAEN_Pos (0U) #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR_DMACFG_Pos (1U) #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR_RES_Pos (3U) #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ #define ADC_CFGR_EXTSEL_Pos (5U) #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ #define ADC_CFGR_EXTEN_Pos (10U) #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR_OVRMOD_Pos (12U) #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR_CONT_Pos (13U) #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR_AUTDLY_Pos (14U) #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ #define ADC_CFGR_ALIGN_Pos (15U) #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR_DISCEN_Pos (16U) #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR_DISCNUM_Pos (17U) #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ #define ADC_CFGR_JDISCEN_Pos (20U) #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ #define ADC_CFGR_JQM_Pos (21U) #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ #define ADC_CFGR_AWD1SGL_Pos (22U) #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR_AWD1EN_Pos (23U) #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR_JAWD1EN_Pos (24U) #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ #define ADC_CFGR_JAUTO_Pos (25U) #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ #define ADC_CFGR_AWD1CH_Pos (26U) #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ #define ADC_CFGR_JQDIS_Pos (31U) #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ /******************** Bit definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ #define ADC_CFGR2_JOVSE_Pos (1U) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ #define ADC_CFGR2_OVSR_Pos (2U) #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ #define ADC_CFGR2_OVSS_Pos (5U) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ #define ADC_CFGR2_TROVS_Pos (9U) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ #define ADC_CFGR2_ROVSM_Pos (10U) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ #define ADC_CFGR2_GCOMP_Pos (16U) #define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ #define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ #define ADC_CFGR2_SWTRIG_Pos (25U) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ #define ADC_CFGR2_BULB_Pos (26U) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ #define ADC_CFGR2_SMPTRIG_Pos (27U) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP1_Pos (3U) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP2_Pos (6U) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP3_Pos (9U) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP4_Pos (12U) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP5_Pos (15U) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP6_Pos (18U) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP7_Pos (21U) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP8_Pos (24U) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR1_SMP9_Pos (27U) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ #define ADC_SMPR1_SMPPLUS_Pos (31U) #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ /******************** Bit definition for ADC_SMPR2 register *****************/ #define ADC_SMPR2_SMP10_Pos (0U) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP11_Pos (3U) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP12_Pos (6U) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP13_Pos (9U) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP14_Pos (12U) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP15_Pos (15U) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP16_Pos (18U) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP17_Pos (21U) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP18_Pos (24U) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ /******************** Bit definition for ADC_TR1 register *******************/ #define ADC_TR1_LT1_Pos (0U) #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR1_AWDFILT_Pos (12U) #define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ #define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ #define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ #define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ #define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ #define ADC_TR1_HT1_Pos (16U) #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ /******************** Bit definition for ADC_TR2 register *******************/ #define ADC_TR2_LT2_Pos (0U) #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_TR2_HT2_Pos (16U) #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ /******************** Bit definition for ADC_TR3 register *******************/ #define ADC_TR3_LT3_Pos (0U) #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_TR3_HT3_Pos (16U) #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ /******************** Bit definition for ADC_SQR1 register ******************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ1_Pos (6U) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ2_Pos (12U) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ3_Pos (18U) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ #define ADC_SQR1_SQ4_Pos (24U) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ******************/ #define ADC_SQR2_SQ5_Pos (0U) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ6_Pos (6U) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ7_Pos (12U) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ8_Pos (18U) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ9_Pos (24U) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ******************/ #define ADC_SQR3_SQ10_Pos (0U) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ11_Pos (6U) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ12_Pos (12U) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ13_Pos (18U) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ14_Pos (24U) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ******************/ #define ADC_SQR4_SQ15_Pos (0U) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ #define ADC_SQR4_SQ16_Pos (6U) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_RDATA_Pos (0U) #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ /******************** Bit definition for ADC_JSQR register ******************/ #define ADC_JSQR_JL_Pos (0U) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JEXTSEL_Pos (2U) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JEXTEN_Pos (7U) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ1_Pos (9U) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ2_Pos (15U) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ3_Pos (21U) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ #define ADC_JSQR_JSQ4_Pos (27U) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ******************/ #define ADC_OFR1_OFFSET1_Pos (0U) #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ #define ADC_OFR1_OFFSETPOS_Pos (24U) #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ #define ADC_OFR1_SATEN_Pos (25U) #define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ #define ADC_OFR1_OFFSET1_CH_Pos (26U) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR1_OFFSET1_EN_Pos (31U) #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ /******************** Bit definition for ADC_OFR2 register ******************/ #define ADC_OFR2_OFFSET2_Pos (0U) #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ #define ADC_OFR2_OFFSETPOS_Pos (24U) #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ #define ADC_OFR2_SATEN_Pos (25U) #define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ #define ADC_OFR2_OFFSET2_CH_Pos (26U) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR2_OFFSET2_EN_Pos (31U) #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ /******************** Bit definition for ADC_OFR3 register ******************/ #define ADC_OFR3_OFFSET3_Pos (0U) #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ #define ADC_OFR3_OFFSETPOS_Pos (24U) #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ #define ADC_OFR3_SATEN_Pos (25U) #define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ #define ADC_OFR3_OFFSET3_CH_Pos (26U) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR3_OFFSET3_EN_Pos (31U) #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ /******************** Bit definition for ADC_OFR4 register ******************/ #define ADC_OFR4_OFFSET4_Pos (0U) #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ #define ADC_OFR4_OFFSETPOS_Pos (24U) #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ #define ADC_OFR4_SATEN_Pos (25U) #define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ #define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ #define ADC_OFR4_OFFSET4_CH_Pos (26U) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ #define ADC_OFR4_OFFSET4_EN_Pos (31U) #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ /******************** Bit definition for ADC_JDR1 register ******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ /******************** Bit definition for ADC_JDR2 register ******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ /******************** Bit definition for ADC_JDR3 register ******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ /******************** Bit definition for ADC_JDR4 register ******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ /******************** Bit definition for ADC_AWD2CR register ****************/ #define ADC_AWD2CR_AWD2CH_Pos (0U) #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_S_Pos (0U) #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ #define ADC_CALFACT_CALFACT_D_Pos (16U) #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ /******************** Bit definition for ADC_GCOMP register *****************/ #define ADC_GCOMP_GCOMPCOEFF_Pos (0U) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ /************************* ADC Common registers *****************************/ /******************** Bit definition for ADC_CSR register *******************/ #define ADC_CSR_ADRDY_MST_Pos (0U) #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ #define ADC_CSR_EOSMP_MST_Pos (1U) #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ #define ADC_CSR_EOC_MST_Pos (2U) #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ #define ADC_CSR_EOS_MST_Pos (3U) #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ #define ADC_CSR_OVR_MST_Pos (4U) #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ #define ADC_CSR_JEOC_MST_Pos (5U) #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_MST_Pos (6U) #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_MST_Pos (7U) #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ #define ADC_CSR_AWD2_MST_Pos (8U) #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ #define ADC_CSR_AWD3_MST_Pos (9U) #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ #define ADC_CSR_JQOVF_MST_Pos (10U) #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ #define ADC_CSR_ADRDY_SLV_Pos (16U) #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ #define ADC_CSR_EOSMP_SLV_Pos (17U) #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ #define ADC_CSR_EOC_SLV_Pos (18U) #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ #define ADC_CSR_EOS_SLV_Pos (19U) #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ #define ADC_CSR_OVR_SLV_Pos (20U) #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ #define ADC_CSR_JEOC_SLV_Pos (21U) #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ #define ADC_CSR_JEOS_SLV_Pos (22U) #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ #define ADC_CSR_AWD1_SLV_Pos (23U) #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ #define ADC_CSR_AWD2_SLV_Pos (24U) #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ #define ADC_CSR_AWD3_SLV_Pos (25U) #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ #define ADC_CSR_JQOVF_SLV_Pos (26U) #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ /******************** Bit definition for ADC_CCR register *******************/ #define ADC_CCR_DUAL_Pos (0U) #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DMACFG_Pos (13U) #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ #define ADC_CCR_MDMA_Pos (14U) #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_CKMODE_Pos (16U) #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ #define ADC_CCR_PRESC_Pos (18U) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_VSENSESEL_Pos (23U) #define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ #define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ #define ADC_CCR_VBATSEL_Pos (24U) #define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ /******************** Bit definition for ADC_CDR register *******************/ #define ADC_CDR_RDATA_MST_Pos (0U) #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ #define ADC_CDR_RDATA_SLV_Pos (16U) #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ /******************************************************************************/ /* */ /* Analog Comparators (COMP) */ /* */ /******************************************************************************/ /********************** Bit definition for COMP_CSR register ****************/ #define COMP_CSR_EN_Pos (0U) #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ #define COMP_CSR_INMSEL_Pos (4U) #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ #define COMP_CSR_INPSEL_Pos (8U) #define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ #define COMP_CSR_POLARITY_Pos (15U) #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ #define COMP_CSR_HYST_Pos (16U) #define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ #define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ #define COMP_CSR_BLANKING_Pos (19U) #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ #define COMP_CSR_BRGEN_Pos (22U) #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ #define COMP_CSR_SCALEN_Pos (23U) #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ #define COMP_CSR_VALUE_Pos (30U) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ #define COMP_CSR_LOCK_Pos (31U) #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ /******************************************************************************/ /* */ /* CORDIC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CORDIC_CSR register *****************/ #define CORDIC_CSR_FUNC_Pos (0U) #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ #define CORDIC_CSR_PRECISION_Pos (4U) #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ #define CORDIC_CSR_SCALE_Pos (8U) #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ #define CORDIC_CSR_IEN_Pos (16U) #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ #define CORDIC_CSR_DMAREN_Pos (17U) #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ #define CORDIC_CSR_DMAWEN_Pos (18U) #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ #define CORDIC_CSR_NRES_Pos (19U) #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ #define CORDIC_CSR_NARGS_Pos (20U) #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ #define CORDIC_CSR_RESSIZE_Pos (21U) #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ #define CORDIC_CSR_ARGSIZE_Pos (22U) #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ #define CORDIC_CSR_RRDY_Pos (31U) #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ /******************* Bit definition for CORDIC_WDATA register ***************/ #define CORDIC_WDATA_ARG_Pos (0U) #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ /******************* Bit definition for CORDIC_RDATA register ***************/ #define CORDIC_RDATA_RES_Pos (0U) #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ #define CRC_CR_POLYSIZE_Pos (3U) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ #define CRC_CR_REV_IN_Pos (5U) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ #define CRC_CR_REV_OUT_Pos (7U) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ #define CRC_INIT_INIT_Pos (0U) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ #define CRC_POL_POL_Pos (0U) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ /******************************************************************************/ /* */ /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ #define CRS_CR_SYNCOKIE_Pos (0U) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ #define CRS_CR_SYNCWARNIE_Pos (1U) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ #define CRS_CR_ERRIE_Pos (2U) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ #define CRS_CR_ESYNCIE_Pos (3U) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ #define CRS_CR_CEN_Pos (5U) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ #define CRS_CR_AUTOTRIMEN_Pos (6U) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ #define CRS_CR_SWSYNC_Pos (7U) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ #define CRS_CR_TRIM_Pos (8U) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ #define CRS_CFGR_RELOAD_Pos (0U) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ #define CRS_CFGR_FELIM_Pos (16U) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ #define CRS_CFGR_SYNCDIV_Pos (24U) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ #define CRS_CFGR_SYNCSRC_Pos (28U) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ #define CRS_CFGR_SYNCPOL_Pos (31U) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ #define CRS_ISR_SYNCOKF_Pos (0U) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ #define CRS_ISR_SYNCWARNF_Pos (1U) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ #define CRS_ISR_ERRF_Pos (2U) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ #define CRS_ISR_ESYNCF_Pos (3U) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ #define CRS_ISR_SYNCERR_Pos (8U) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ #define CRS_ISR_SYNCMISS_Pos (9U) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ #define CRS_ISR_TRIMOVF_Pos (10U) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ #define CRS_ISR_FEDIR_Pos (15U) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ #define CRS_ISR_FECAP_Pos (16U) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ #define CRS_ICR_SYNCOKC_Pos (0U) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ #define CRS_ICR_SYNCWARNC_Pos (1U) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ #define CRS_ICR_ERRC_Pos (2U) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ #define CRS_ICR_ESYNCC_Pos (3U) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ #define DAC_CR_CEN1_Pos (14U) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ #define DAC_CR_HFSEL_Pos (15U) #define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ #define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ #define DAC_CR_CEN2_Pos (30U) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ return result; } #endif /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) #else #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) #else #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") #endif /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) #else #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") #endif /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXB(value, ptr) __strex(value, ptr) #else #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXH(value, ptr) __strex(value, ptr) #else #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) #define __STREXW(value, ptr) __strex(value, ptr) #else #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") #endif /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCC_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/cmsis_armclang.h ================================================ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V5.2.0 * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) #define __SADD8 __builtin_arm_sadd8 #define __QADD8 __builtin_arm_qadd8 #define __SHADD8 __builtin_arm_shadd8 #define __UADD8 __builtin_arm_uadd8 #define __UQADD8 __builtin_arm_uqadd8 #define __UHADD8 __builtin_arm_uhadd8 #define __SSUB8 __builtin_arm_ssub8 #define __QSUB8 __builtin_arm_qsub8 #define __SHSUB8 __builtin_arm_shsub8 #define __USUB8 __builtin_arm_usub8 #define __UQSUB8 __builtin_arm_uqsub8 #define __UHSUB8 __builtin_arm_uhsub8 #define __SADD16 __builtin_arm_sadd16 #define __QADD16 __builtin_arm_qadd16 #define __SHADD16 __builtin_arm_shadd16 #define __UADD16 __builtin_arm_uadd16 #define __UQADD16 __builtin_arm_uqadd16 #define __UHADD16 __builtin_arm_uhadd16 #define __SSUB16 __builtin_arm_ssub16 #define __QSUB16 __builtin_arm_qsub16 #define __SHSUB16 __builtin_arm_shsub16 #define __USUB16 __builtin_arm_usub16 #define __UQSUB16 __builtin_arm_uqsub16 #define __UHSUB16 __builtin_arm_uhsub16 #define __SASX __builtin_arm_sasx #define __QASX __builtin_arm_qasx #define __SHASX __builtin_arm_shasx #define __UASX __builtin_arm_uasx #define __UQASX __builtin_arm_uqasx #define __UHASX __builtin_arm_uhasx #define __SSAX __builtin_arm_ssax #define __QSAX __builtin_arm_qsax #define __SHSAX __builtin_arm_shsax #define __USAX __builtin_arm_usax #define __UQSAX __builtin_arm_uqsax #define __UHSAX __builtin_arm_uhsax #define __USAD8 __builtin_arm_usad8 #define __USADA8 __builtin_arm_usada8 #define __SSAT16 __builtin_arm_ssat16 #define __USAT16 __builtin_arm_usat16 #define __UXTB16 __builtin_arm_uxtb16 #define __UXTAB16 __builtin_arm_uxtab16 #define __SXTB16 __builtin_arm_sxtb16 #define __SXTAB16 __builtin_arm_sxtab16 #define __SMUAD __builtin_arm_smuad #define __SMUADX __builtin_arm_smuadx #define __SMLAD __builtin_arm_smlad #define __SMLADX __builtin_arm_smladx #define __SMLALD __builtin_arm_smlald #define __SMLALDX __builtin_arm_smlaldx #define __SMUSD __builtin_arm_smusd #define __SMUSDX __builtin_arm_smusdx #define __SMLSD __builtin_arm_smlsd #define __SMLSDX __builtin_arm_smlsdx #define __SMLSLD __builtin_arm_smlsld #define __SMLSLDX __builtin_arm_smlsldx #define __SEL __builtin_arm_sel #define __QADD __builtin_arm_qadd #define __QSUB __builtin_arm_qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/cmsis_armclang_ltm.h ================================================ /**************************************************************************//** * @file cmsis_armclang_ltm.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file * @version V1.2.0 * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2018-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H #pragma clang system_header /* treat file as system include file */ #ifndef __ARM_COMPAT_H #include /* Compatibility header for Arm Compiler 5 intrinsics */ #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE __inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START #define __PROGRAM_START __main #endif #ifndef __INITIAL_SP #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __enable_irq(); see arm_compat.h */ /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ /* intrinsic void __disable_irq(); see arm_compat.h */ /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else #define __get_FPSCR() ((uint32_t)0U) #endif /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __set_FPSCR __builtin_arm_set_fpscr #else #define __set_FPSCR(x) ((void)(x)) #endif /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __builtin_arm_nop /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __builtin_arm_wfi /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __builtin_arm_wfe /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __builtin_arm_sev /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __builtin_arm_dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __builtin_arm_dmb(0xF) /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ #define __REV(value) __builtin_bswap32(value) /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ #define __REV16(value) __ROR(__REV(value), 16) /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ #define __REVSH(value) (int16_t)__builtin_bswap16(value) /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __builtin_arm_rbit /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB (uint8_t)__builtin_arm_ldrex /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH (uint16_t)__builtin_arm_ldrex /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW (uint32_t)__builtin_arm_ldrex /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH (uint32_t)__builtin_arm_strex /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW (uint32_t)__builtin_arm_strex /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ #define __CLREX __builtin_arm_clrex #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __builtin_arm_ssat /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __builtin_arm_usat /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDAEXB (uint8_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDAEXH (uint16_t)__builtin_arm_ldaex /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDAEX (uint32_t)__builtin_arm_ldaex /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXB (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEXH (uint32_t)__builtin_arm_stlex /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STLEX (uint32_t)__builtin_arm_stlex #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CMSIS_ARMCLANG_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/cmsis_compiler.h ================================================ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file * @version V5.1.0 * @date 09. October 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H #include /* * Arm Compiler 4/5 */ #if defined ( __CC_ARM ) #include "cmsis_armcc.h" /* * Arm Compiler 6.6 LTM (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) #include "cmsis_armclang_ltm.h" /* * Arm Compiler above 6.10.1 (armclang) */ #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #include "cmsis_armclang.h" /* * GNU Compiler */ #elif defined ( __GNUC__ ) #include "cmsis_gcc.h" /* * IAR Compiler */ #elif defined ( __ICCARM__ ) #include /* * TI Arm Compiler */ #elif defined ( __TI_ARM__ ) #include #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed)) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed)) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif /* * TASKING Compiler */ #elif defined ( __TASKING__ ) /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((noreturn)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __packed__ #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __packed__ #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif /* * COSMIC Compiler */ #elif defined ( __CSMC__ ) #include #ifndef __ASM #define __ASM _asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __STATIC_INLINE #endif #ifndef __NO_RETURN // NO RETURN is automatically detected hence no warning here #define __NO_RETURN #endif #ifndef __USED #warning No compiler specific solution for __USED. __USED is ignored. #define __USED #endif #ifndef __WEAK #define __WEAK __weak #endif #ifndef __PACKED #define __PACKED @packed #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif #ifndef __PACKED_UNION #define __PACKED_UNION @packed union #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif #ifndef __RESTRICT #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif #ifndef __COMPILER_BARRIER #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #define __COMPILER_BARRIER() (void)0 #endif #else #error Unknown compiler. #endif #endif /* __CMSIS_COMPILER_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/cmsis_gcc.h ================================================ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file * @version V5.2.0 * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef __CMSIS_GCC_H #define __CMSIS_GCC_H /* ignore some GCC warnings */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wsign-conversion" #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" /* Fallback for __has_builtin */ #ifndef __has_builtin #define __has_builtin(x) (0) #endif /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline #endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif #ifndef __USED #define __USED __attribute__((used)) #endif #ifndef __WEAK #define __WEAK __attribute__((weak)) #endif #ifndef __PACKED #define __PACKED __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif #ifndef __PACKED_UNION #define __PACKED_UNION union __attribute__((packed, aligned(1))) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT16_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif #ifndef __UNALIGNED_UINT32_READ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" #pragma GCC diagnostic ignored "-Wattributes" __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma GCC diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT #define __RESTRICT __restrict #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif /* ######################### Startup and Lowlevel Init ######################## */ #ifndef __PROGRAM_START /** \brief Initializes data and bss sections \details This default implementations initialized all data and additional bss sections relying on .copy.table and .zero.table specified properly in the used linker script. */ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) { extern void _start(void) __NO_RETURN; typedef struct { uint32_t const* src; uint32_t* dest; uint32_t wlen; } __copy_table_t; typedef struct { uint32_t* dest; uint32_t wlen; } __zero_table_t; extern const __copy_table_t __copy_table_start__; extern const __copy_table_t __copy_table_end__; extern const __zero_table_t __zero_table_start__; extern const __zero_table_t __zero_table_end__; for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = pTable->src[i]; } } for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = 0u; } } _start(); } #define __PROGRAM_START __cmsis_start #endif #ifndef __INITIAL_SP #define __INITIAL_SP __StackTop #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT __StackLimit #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __Vectors #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) #endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ /** \brief Enable IRQ Interrupts \details Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Get Control Register \details Returns the content of the Control Register. \return Control Register value */ __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Control Register (non-secure) \details Returns the content of the non-secure Control Register when in secure mode. \return non-secure Control Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) { uint32_t result; __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Control Register \details Writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Control Register (non-secure) \details Writes the given value to the non-secure Control Register when in secure state. \param [in] control Control Register value to set */ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) { __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); } #endif /** \brief Get IPSR Register \details Returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register \details Returns the content of the APSR Register. \return APSR Register value */ __STATIC_FORCEINLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register \details Returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_FORCEINLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer \details Returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __get_PSP(void) { uint32_t result; __ASM volatile ("MRS %0, psp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer (non-secure) \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. \return PSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Process Stack Pointer \details Assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) { __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); } #endif /** \brief Get Main Stack Pointer \details Returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __get_MSP(void) { uint32_t result; __ASM volatile ("MRS %0, msp" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer (non-secure) \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. \return MSP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Main Stack Pointer \details Assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer (non-secure) \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) { __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); } #endif #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Stack Pointer (non-secure) \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. \return SP Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) { uint32_t result; __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); return(result); } /** \brief Set Stack Pointer (non-secure) \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. \param [in] topOfStack Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) { __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); } #endif /** \brief Get Priority Mask \details Returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Priority Mask (non-secure) \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. \return Priority Mask value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); return(result); } #endif /** \brief Set Priority Mask \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Priority Mask (non-secure) \details Assigns the given value to the non-secure Priority Mask Register when in secure state. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) { __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); } #endif #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Enable FIQ \details Enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ \details Disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority \details Returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Base Priority (non-secure) \details Returns the current value of the non-secure Base Priority register when in secure state. \return Base Priority register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Base Priority \details Assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) { __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Base Priority (non-secure) \details Assigns the given value to the non-secure Base Priority register when in secure state. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) { __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); } #endif /** \brief Set Base Priority with condition \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. \param [in] basePri Base Priority value to set */ __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) { __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); } /** \brief Get Fault Mask \details Returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Fault Mask (non-secure) \details Returns the current value of the non-secure Fault Mask register when in secure state. \return Fault Mask register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); return(result); } #endif /** \brief Set Fault Mask \details Assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Fault Mask (non-secure) \details Assigns the given value to the non-secure Fault Mask register when in secure state. \param [in] faultMask Fault Mask value to set */ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) { __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); } #endif #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Get Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Process Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \return PSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Process Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Process Stack Pointer (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)ProcStackPtrLimit; #else __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); #endif } #endif /** \brief Get Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim" : "=r" (result) ); return result; #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Get Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. \return MSPLIM Register value */ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI return 0U; #else uint32_t result; __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); return result; #endif } #endif /** \brief Set Main Stack Pointer Limit Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set */ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); #endif } #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) /** \brief Set Main Stack Pointer Limit (non-secure) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. \param [in] MainStackPtrLimit Main Stack Pointer value to set */ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)MainStackPtrLimit; #else __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); #endif } #endif #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /** \brief Get FPSCR \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ return __builtin_arm_get_fpscr(); #else uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); #endif #else return(0U); #endif } /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #if __has_builtin(__builtin_arm_set_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ __builtin_arm_set_fpscr(fpscr); #else __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); #endif #else (void)fpscr; #endif } /*@} end of CMSIS_Core_RegAccFunctions */ /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constraint "l" * Otherwise, use general registers, specified by constraint "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_RW_REG(r) "+l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_RW_REG(r) "+r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP() __ASM volatile ("nop") /** \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI() __ASM volatile ("wfi") /** \brief Wait For Event \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE() __ASM volatile ("wfe") /** \brief Send Event \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV() __ASM volatile ("sev") /** \brief Instruction Synchronization Barrier \details Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __STATIC_FORCEINLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Reverse byte order (16 bit) \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; } /** \brief Reverse byte order (16 bit) \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (int16_t)__builtin_bswap16(value); #else int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } /** \brief Rotate Right in unsigned value (32 bit) \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] op1 Value to rotate \param [in] op2 Number of Bits to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { op2 %= 32U; if (op2 == 0U) { return op1; } return (op1 >> op2) | (op1 << (32U - op2)); } /** \brief Breakpoint \details Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value \details Reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; } /** \brief Count leading zeros \details Counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) { /* Even though __builtin_clz produces a CLZ instruction on ARM, formally __builtin_clz(0) is undefined behaviour, so handle this case specially. This guarantees ARM-compatible results if happening to compile on a non-ARM target, and ensures the compiler doesn't decide to activate any optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) { return 32U; } return __builtin_clz(value); } #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief LDR Exclusive (8 bit) \details Executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) \details Executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) \details Executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) \details Executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) \details Executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) \details Executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock \details Removes the exclusive lock which is created by LDREX. */ __STATIC_FORCEINLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) /** \brief Signed Saturate \details Saturates a signed value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] ARG1 Value to be saturated \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) \details Moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) \details Executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) \details Executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) \details Executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief STRT Unprivileged (8 bit) \details Executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) \details Executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) \details Executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ /** \brief Signed Saturate \details Saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } /** \brief Unsigned Saturate \details Saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) /** \brief Load-Acquire (8 bit) \details Executes a LDAB instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire (16 bit) \details Executes a LDAH instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire (32 bit) \details Executes a LDA instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release (8 bit) \details Executes a STLB instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (16 bit) \details Executes a STLH instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Store-Release (32 bit) \details Executes a STL instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); } /** \brief Load-Acquire Exclusive (8 bit) \details Executes a LDAB exclusive instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint8_t) result); } /** \brief Load-Acquire Exclusive (16 bit) \details Executes a LDAH exclusive instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); return ((uint16_t) result); } /** \brief Load-Acquire Exclusive (32 bit) \details Executes a LDA exclusive instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); return(result); } /** \brief Store-Release Exclusive (8 bit) \details Executes a STLB exclusive instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (16 bit) \details Executes a STLH exclusive instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } /** \brief Store-Release Exclusive (32 bit) \details Executes a STL exclusive instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); return(result); } #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) { union llreg_u{ uint32_t w32[2]; uint64_t w64; } llr; llr.w64 = acc; #ifndef __ARMEB__ /* Little endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); #else /* Big endian */ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); #endif return(llr.w64); } __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) { int32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #if 0 #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #endif #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } #endif /* (__ARM_FEATURE_DSP == 1) */ /*@} end of group CMSIS_SIMD_intrinsics */ #pragma GCC diagnostic pop #endif /* __CMSIS_GCC_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/cmsis_iccarm.h ================================================ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file * @version V5.1.0 * @date 08. May 2019 ******************************************************************************/ //------------------------------------------------------------------------------ // // Copyright (c) 2017-2019 IAR Systems // Copyright (c) 2017-2019 Arm Limited. All rights reserved. // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // //------------------------------------------------------------------------------ #ifndef __CMSIS_ICCARM_H__ #define __CMSIS_ICCARM_H__ #ifndef __ICCARM__ #error This file should only be compiled by ICCARM #endif #pragma system_include #define __IAR_FT _Pragma("inline=forced") __intrinsic #if (__VER__ >= 8000000) #define __ICCARM_V8 1 #else #define __ICCARM_V8 0 #endif #ifndef __ALIGNED #if __ICCARM_V8 #define __ALIGNED(x) __attribute__((aligned(x))) #elif (__VER__ >= 7080000) /* Needs IAR language extensions */ #define __ALIGNED(x) __attribute__((aligned(x))) #else #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. #define __ALIGNED(x) #endif #endif /* Define compiler macros for CPU architecture, used in CMSIS 5. */ #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ /* Macros already defined */ #else #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' #if __ARM_ARCH == 6 #define __ARM_ARCH_6M__ 1 #elif __ARM_ARCH == 7 #if __ARM_FEATURE_DSP #define __ARM_ARCH_7EM__ 1 #else #define __ARM_ARCH_7M__ 1 #endif #endif /* __ARM_ARCH */ #endif /* __ARM_ARCH_PROFILE == 'M' */ #endif /* Alternativ core deduction for older ICCARM's */ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) #define __ARM_ARCH_6M__ 1 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) #define __ARM_ARCH_7M__ 1 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) #define __ARM_ARCH_7EM__ 1 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) #define __ARM_ARCH_8M_BASE__ 1 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) #define __ARM_ARCH_8M_MAIN__ 1 #else #error "Unknown target." #endif #endif #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 #define __IAR_M0_FAMILY 1 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 #define __IAR_M0_FAMILY 1 #else #define __IAR_M0_FAMILY 0 #endif #ifndef __ASM #define __ASM __asm #endif #ifndef __COMPILER_BARRIER #define __COMPILER_BARRIER() __ASM volatile("":::"memory") #endif #ifndef __INLINE #define __INLINE inline #endif #ifndef __NO_RETURN #if __ICCARM_V8 #define __NO_RETURN __attribute__((__noreturn__)) #else #define __NO_RETURN _Pragma("object_attribute=__noreturn") #endif #endif #ifndef __PACKED #if __ICCARM_V8 #define __PACKED __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED __packed #endif #endif #ifndef __PACKED_STRUCT #if __ICCARM_V8 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_STRUCT __packed struct #endif #endif #ifndef __PACKED_UNION #if __ICCARM_V8 #define __PACKED_UNION union __attribute__((packed, aligned(1))) #else /* Needs IAR language extensions */ #define __PACKED_UNION __packed union #endif #endif #ifndef __RESTRICT #if __ICCARM_V8 #define __RESTRICT __restrict #else /* Needs IAR language extensions */ #define __RESTRICT restrict #endif #endif #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif #ifndef __FORCEINLINE #define __FORCEINLINE _Pragma("inline=forced") #endif #ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE #endif #ifndef __UNALIGNED_UINT16_READ #pragma language=save #pragma language=extended __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { return *(__packed uint16_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) #endif #ifndef __UNALIGNED_UINT16_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { *(__packed uint16_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32_READ #pragma language=save #pragma language=extended __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { return *(__packed uint32_t*)(ptr); } #pragma language=restore #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) #endif #ifndef __UNALIGNED_UINT32_WRITE #pragma language=save #pragma language=extended __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { *(__packed uint32_t*)(ptr) = val;; } #pragma language=restore #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma language=save #pragma language=extended __packed struct __iar_u32 { uint32_t v; }; #pragma language=restore #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) #endif #ifndef __USED #if __ICCARM_V8 #define __USED __attribute__((used)) #else #define __USED _Pragma("__root") #endif #endif #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) #else #define __WEAK _Pragma("__weak") #endif #endif #ifndef __PROGRAM_START #define __PROGRAM_START __iar_program_start #endif #ifndef __INITIAL_SP #define __INITIAL_SP CSTACK$$Limit #endif #ifndef __STACK_LIMIT #define __STACK_LIMIT CSTACK$$Base #endif #ifndef __VECTOR_TABLE #define __VECTOR_TABLE __vector_table #endif #ifndef __VECTOR_TABLE_ATTRIBUTE #define __VECTOR_TABLE_ATTRIBUTE @".intvec" #endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 #endif #if __ICCARM_INTRINSICS_VERSION__ == 2 #if defined(__CLZ) #undef __CLZ #endif #if defined(__REVSH) #undef __REVSH #endif #if defined(__RBIT) #undef __RBIT #endif #if defined(__SSAT) #undef __SSAT #endif #if defined(__USAT) #undef __USAT #endif #include "iccarm_builtin.h" #define __disable_fault_irq __iar_builtin_disable_fiq #define __disable_irq __iar_builtin_disable_interrupt #define __enable_fault_irq __iar_builtin_enable_fiq #define __enable_irq __iar_builtin_enable_interrupt #define __arm_rsr __iar_builtin_rsr #define __arm_wsr __iar_builtin_wsr #define __get_APSR() (__arm_rsr("APSR")) #define __get_BASEPRI() (__arm_rsr("BASEPRI")) #define __get_CONTROL() (__arm_rsr("CONTROL")) #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) #define __get_FPSCR() (__arm_rsr("FPSCR")) #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) #else #define __get_FPSCR() ( 0 ) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #define __get_IPSR() (__arm_rsr("IPSR")) #define __get_MSP() (__arm_rsr("MSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __get_MSPLIM() (0U) #else #define __get_MSPLIM() (__arm_rsr("MSPLIM")) #endif #define __get_PRIMASK() (__arm_rsr("PRIMASK")) #define __get_PSP() (__arm_rsr("PSP")) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __get_PSPLIM() (0U) #else #define __get_PSPLIM() (__arm_rsr("PSPLIM")) #endif #define __get_xPSR() (__arm_rsr("xPSR")) #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI #define __set_MSPLIM(VALUE) ((void)(VALUE)) #else #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) #endif #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __set_PSPLIM(VALUE) ((void)(VALUE)) #else #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI #define __TZ_get_PSPLIM_NS() (0U) #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) #else #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) #endif #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) #define __NOP __iar_builtin_no_operation #define __CLZ __iar_builtin_CLZ #define __CLREX __iar_builtin_CLREX #define __DMB __iar_builtin_DMB #define __DSB __iar_builtin_DSB #define __ISB __iar_builtin_ISB #define __LDREXB __iar_builtin_LDREXB #define __LDREXH __iar_builtin_LDREXH #define __LDREXW __iar_builtin_LDREX #define __RBIT __iar_builtin_RBIT #define __REV __iar_builtin_REV #define __REV16 __iar_builtin_REV16 __IAR_FT int16_t __REVSH(int16_t val) { return (int16_t) __iar_builtin_REVSH(val); } #define __ROR __iar_builtin_ROR #define __RRX __iar_builtin_RRX #define __SEV __iar_builtin_SEV #if !__IAR_M0_FAMILY #define __SSAT __iar_builtin_SSAT #endif #define __STREXB __iar_builtin_STREXB #define __STREXH __iar_builtin_STREXH #define __STREXW __iar_builtin_STREX #if !__IAR_M0_FAMILY #define __USAT __iar_builtin_USAT #endif #define __WFE __iar_builtin_WFE #define __WFI __iar_builtin_WFI #if __ARM_MEDIA__ #define __SADD8 __iar_builtin_SADD8 #define __QADD8 __iar_builtin_QADD8 #define __SHADD8 __iar_builtin_SHADD8 #define __UADD8 __iar_builtin_UADD8 #define __UQADD8 __iar_builtin_UQADD8 #define __UHADD8 __iar_builtin_UHADD8 #define __SSUB8 __iar_builtin_SSUB8 #define __QSUB8 __iar_builtin_QSUB8 #define __SHSUB8 __iar_builtin_SHSUB8 #define __USUB8 __iar_builtin_USUB8 #define __UQSUB8 __iar_builtin_UQSUB8 #define __UHSUB8 __iar_builtin_UHSUB8 #define __SADD16 __iar_builtin_SADD16 #define __QADD16 __iar_builtin_QADD16 #define __SHADD16 __iar_builtin_SHADD16 #define __UADD16 __iar_builtin_UADD16 #define __UQADD16 __iar_builtin_UQADD16 #define __UHADD16 __iar_builtin_UHADD16 #define __SSUB16 __iar_builtin_SSUB16 #define __QSUB16 __iar_builtin_QSUB16 #define __SHSUB16 __iar_builtin_SHSUB16 #define __USUB16 __iar_builtin_USUB16 #define __UQSUB16 __iar_builtin_UQSUB16 #define __UHSUB16 __iar_builtin_UHSUB16 #define __SASX __iar_builtin_SASX #define __QASX __iar_builtin_QASX #define __SHASX __iar_builtin_SHASX #define __UASX __iar_builtin_UASX #define __UQASX __iar_builtin_UQASX #define __UHASX __iar_builtin_UHASX #define __SSAX __iar_builtin_SSAX #define __QSAX __iar_builtin_QSAX #define __SHSAX __iar_builtin_SHSAX #define __USAX __iar_builtin_USAX #define __UQSAX __iar_builtin_UQSAX #define __UHSAX __iar_builtin_UHSAX #define __USAD8 __iar_builtin_USAD8 #define __USADA8 __iar_builtin_USADA8 #define __SSAT16 __iar_builtin_SSAT16 #define __USAT16 __iar_builtin_USAT16 #define __UXTB16 __iar_builtin_UXTB16 #define __UXTAB16 __iar_builtin_UXTAB16 #define __SXTB16 __iar_builtin_SXTB16 #define __SXTAB16 __iar_builtin_SXTAB16 #define __SMUAD __iar_builtin_SMUAD #define __SMUADX __iar_builtin_SMUADX #define __SMMLA __iar_builtin_SMMLA #define __SMLAD __iar_builtin_SMLAD #define __SMLADX __iar_builtin_SMLADX #define __SMLALD __iar_builtin_SMLALD #define __SMLALDX __iar_builtin_SMLALDX #define __SMUSD __iar_builtin_SMUSD #define __SMUSDX __iar_builtin_SMUSDX #define __SMLSD __iar_builtin_SMLSD #define __SMLSDX __iar_builtin_SMLSDX #define __SMLSLD __iar_builtin_SMLSLD #define __SMLSLDX __iar_builtin_SMLSLDX #define __SEL __iar_builtin_SEL #define __QADD __iar_builtin_QADD #define __QSUB __iar_builtin_QSUB #define __PKHBT __iar_builtin_PKHBT #define __PKHTB __iar_builtin_PKHTB #endif #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #define __CLZ __cmsis_iar_clz_not_active #define __SSAT __cmsis_iar_ssat_not_active #define __USAT __cmsis_iar_usat_not_active #define __RBIT __cmsis_iar_rbit_not_active #define __get_APSR __cmsis_iar_get_APSR_not_active #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #define __get_FPSCR __cmsis_iar_get_FPSR_not_active #define __set_FPSCR __cmsis_iar_set_FPSR_not_active #endif #ifdef __INTRINSICS_INCLUDED #error intrinsics.h is already included previously! #endif #include #if __IAR_M0_FAMILY /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ #undef __CLZ #undef __SSAT #undef __USAT #undef __RBIT #undef __get_APSR __STATIC_INLINE uint8_t __CLZ(uint32_t data) { if (data == 0U) { return 32U; } uint32_t count = 0U; uint32_t mask = 0x80000000U; while ((data & mask) == 0U) { count += 1U; mask = mask >> 1U; } return count; } __STATIC_INLINE uint32_t __RBIT(uint32_t v) { uint8_t sc = 31U; uint32_t r = v; for (v >>= 1U; v; v >>= 1U) { r <<= 1U; r |= v & 1U; sc--; } return (r << sc); } __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t res; __asm("MRS %0,APSR" : "=r" (res)); return res; } #endif #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) #undef __get_FPSCR #undef __set_FPSCR #define __get_FPSCR() (0) #define __set_FPSCR(VALUE) ((void)VALUE) #endif #pragma diag_suppress=Pe940 #pragma diag_suppress=Pe177 #define __enable_irq __enable_interrupt #define __disable_irq __disable_interrupt #define __NOP __no_operation #define __get_xPSR __get_PSR #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { return __LDREX((unsigned long *)ptr); } __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { return __STREX(value, (unsigned long *)ptr); } #endif /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ #if (__CORTEX_M >= 0x03) __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); return(result); } __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); } #define __enable_fault_irq __enable_fiq #define __disable_fault_irq __disable_fiq #endif /* (__CORTEX_M >= 0x03) */ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); } #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint32_t __get_MSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,MSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_MSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure MSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR MSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __get_PSPLIM(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM" : "=r" (res)); #endif return res; } __IAR_FT void __set_PSPLIM(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { uint32_t res; __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) { uint32_t res; __asm volatile("MRS %0,PSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { __asm volatile("MSR PSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_MSP_NS(void) { uint32_t res; __asm volatile("MRS %0,MSP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { __asm volatile("MSR MSP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_SP_NS(void) { uint32_t res; __asm volatile("MRS %0,SP_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_SP_NS(uint32_t value) { __asm volatile("MSR SP_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { uint32_t res; __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { uint32_t res; __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); } __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI res = 0U; #else __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); #endif return res; } __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) // without main extensions, the non-secure PSPLIM is RAZ/WI (void)value; #else __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { uint32_t res; __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); return res; } __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) #if __IAR_M0_FAMILY __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { if ((sat >= 1U) && (sat <= 32U)) { const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); const int32_t min = -1 - max ; if (val > max) { return max; } else if (val < min) { return min; } } return val; } __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { if (sat <= 31U) { const uint32_t max = ((1U << sat) - 1U); if (val > (int32_t)max) { return max; } else if (val < 0) { return 0U; } } return (uint32_t)val; } #endif #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t res; __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t res; __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { uint32_t res; __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ #undef __IAR_FT #undef __IAR_M0_FAMILY #undef __ICCARM_V8 #pragma diag_default=Pe940 #pragma diag_default=Pe177 #endif /* __CMSIS_ICCARM_H__ */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/cmsis_version.h ================================================ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions * @version V5.0.3 * @date 24. June 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CMSIS_VERSION_H #define __CMSIS_VERSION_H /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_armv81mml.h ================================================ /**************************************************************************//** * @file core_armv81mml.h * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File * @version V1.0.0 * @date 15. March 2019 ******************************************************************************/ /* * Copyright (c) 2018-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV81MML_H_GENERIC #define __CORE_ARMV81MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMV81MML @{ */ #include "cmsis_version.h" #define __ARM_ARCH_8M_MAIN__ 1 // patching for now /* CMSIS ARMV81MML definitions */ #define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV81MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV81MML_H_DEPENDANT #define __CORE_ARMV81MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv81MML_REV #define __ARMv81MML_REV 0x0000U #warning "__ARMv81MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv81MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29U]; __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ #define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV81MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_armv8mbl.h ================================================ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File * @version V5.0.8 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MBL_H_GENERIC #define __CORE_ARMV8MBL_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MBL @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MBL_H_DEPENDANT #define __CORE_ARMV8MBL_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MBL_REV #define __ARMv8MBL_REV 0x0000U #warning "__ARMv8MBL_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MBL */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_armv8mml.h ================================================ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File * @version V5.1.0 * @date 12. September 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_ARMV8MML_H_GENERIC #define __CORE_ARMV8MML_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_ARMv8MML @{ */ #include "cmsis_version.h" /* CMSIS Armv8MML definitions */ #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined(__ARM_FEATURE_DSP) #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_ARMV8MML_H_DEPENDANT #define __CORE_ARMV8MML_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __ARMv8MML_REV #define __ARMv8MML_REV 0x0000U #warning "__ARMv8MML_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group ARMv8MML */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[809U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ uint32_t RESERVED4[4U]; __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI Periodic Synchronization Control Register Definitions */ #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ /* TPI Software Lock Status Register Definitions */ #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_ARMV8MML_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm0.h ================================================ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V5.0.6 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ #include "cmsis_version.h" /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000U #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = 0x0U; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = 0x0U; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm0plus.h ================================================ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V5.0.7 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ #include "cmsis_version.h" /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000U #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0+ header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t vectors = SCB->VTOR; #else uint32_t vectors = 0x0U; #endif (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t vectors = SCB->VTOR; #else uint32_t vectors = 0x0U; #endif return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm1.h ================================================ /**************************************************************************//** * @file core_cm1.h * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File * @version V1.0.1 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM1_H_GENERIC #define __CORE_CM1_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M1 @{ */ #include "cmsis_version.h" /* CMSIS CM1 definitions */ #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (1U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM1_H_DEPENDANT #define __CORE_CM1_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM1_REV #define __CM1_REV 0x0100U #warning "__CM1_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M1 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M1 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. Address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)0x0U; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM1_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm23.h ================================================ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM23_H_GENERIC #define __CORE_CM23_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M23 @{ */ #include "cmsis_version.h" /* CMSIS definitions */ #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (23U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM23_H_DEPENDANT #define __CORE_CM23_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM23_REV #define __CM23_REV 0x0000U #warning "__CM23_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #ifndef __ETM_PRESENT #define __ETM_PRESENT 0U #warning "__ETM_PRESENT not defined in device header file; using default!" #endif #ifndef __MTB_PRESENT #define __MTB_PRESENT 0U #warning "__MTB_PRESENT not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M23 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ uint32_t RESERVED0[6U]; __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 1U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #endif } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define __NVIC_SetPriorityGrouping(X) (void)(X) #define __NVIC_GetPriorityGrouping() (0U) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. If VTOR is not present address 0 must be mapped to SRAM. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) uint32_t *vectors = (uint32_t *)SCB->VTOR; #else uint32_t *vectors = (uint32_t *)0x0U; #endif return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM23_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm3.h ================================================ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ #include "cmsis_version.h" /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ #endif /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm33.h ================================================ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM33_H_GENERIC #define __CORE_CM33_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M33 @{ */ #include "cmsis_version.h" /* CMSIS CM33 definitions */ #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM33_H_DEPENDANT #define __CORE_CM33_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM33_REV #define __CM33_REV 0x0000U #warning "__CM33_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M33 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM33_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm35p.h ================================================ /**************************************************************************//** * @file core_cm35p.h * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File * @version V1.0.0 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM35P_H_GENERIC #define __CORE_CM35P_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M35P @{ */ #include "cmsis_version.h" /* CMSIS CM35P definitions */ #define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (35U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined (__TARGET_FPU_VFP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined (__ARMVFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined (__TI_VFP_SUPPORT__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined (__FPU_VFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM35P_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM35P_H_DEPENDANT #define __CORE_CM35P_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM35P_REV #define __CM35P_REV 0x0000U #warning "__CM35P_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __SAUREGION_PRESENT #define __SAUREGION_PRESENT 0U #warning "__SAUREGION_PRESENT not defined in device header file; using default!" #endif #ifndef __DSP_PRESENT #define __DSP_PRESENT 0U #warning "__DSP_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M35P */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core SAU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[16U]; __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[16U]; __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[16U]; __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[16U]; __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[16U]; __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ uint32_t RESERVED5[16U]; __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED6[580U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ uint32_t RESERVED3[92U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Non-Secure Access Control Register Definitions */ #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ uint32_t RESERVED6[4U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Stimulus Port Register Definitions */ #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ uint32_t RESERVED1[1U]; __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ uint32_t RESERVED3[1U]; __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED4[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ uint32_t RESERVED5[1U]; __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED6[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ uint32_t RESERVED7[1U]; __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED8[1U]; __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ uint32_t RESERVED9[1U]; __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ uint32_t RESERVED10[1U]; __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ uint32_t RESERVED11[1U]; __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ uint32_t RESERVED12[1U]; __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ uint32_t RESERVED13[1U]; __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ uint32_t RESERVED14[1U]; __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ uint32_t RESERVED15[1U]; __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ uint32_t RESERVED16[1U]; __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ uint32_t RESERVED17[1U]; __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ uint32_t RESERVED18[1U]; __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ uint32_t RESERVED19[1U]; __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ uint32_t RESERVED20[1U]; __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ uint32_t RESERVED21[1U]; __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ uint32_t RESERVED22[1U]; __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ uint32_t RESERVED23[1U]; __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ uint32_t RESERVED24[1U]; __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ uint32_t RESERVED25[1U]; __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ uint32_t RESERVED26[1U]; __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ uint32_t RESERVED27[1U]; __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ uint32_t RESERVED28[1U]; __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ uint32_t RESERVED29[1U]; __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ uint32_t RESERVED30[1U]; __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ uint32_t RESERVED31[1U]; __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ uint32_t RESERVED32[934U]; __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ uint32_t RESERVED33[1U]; __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration Test FIFO Test Data 0 Register Definitions */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ /* TPI Integration Test ATB Control Register 2 Register Definitions */ #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ /* TPI Integration Test FIFO Test Data 1 Register Definitions */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ /* TPI Integration Test ATB Control Register 0 Definitions */ #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; union { __IOM uint32_t MAIR[2]; struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ }; }; } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ /* MPU Region Limit Address Register Definitions */ #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ /* MPU Memory Attribute Indirection Register 0 Definitions */ #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ /* MPU Memory Attribute Indirection Register 1 Definitions */ #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ /*@} end of group CMSIS_MPU */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \ingroup CMSIS_core_register \defgroup CMSIS_SAU Security Attribution Unit (SAU) \brief Type definitions for the Security Attribution Unit (SAU) @{ */ /** \brief Structure type to access the Security Attribution Unit (SAU). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ #else uint32_t RESERVED0[3]; #endif __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ } SAU_Type; /* SAU Control Register Definitions */ #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ /* SAU Type Register Definitions */ #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) /* SAU Region Number Register Definitions */ #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ /* SAU Region Base Address Register Definitions */ #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ /* SAU Region Limit Address Register Definitions */ #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ /* Secure Fault Status Register Definitions */ #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ /*@} end of group CMSIS_SAU */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ uint32_t RESERVED4[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ #endif #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* Special LR values for Secure/Non-Secure call handling and exception handling */ /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ #else #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ #endif /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Get Interrupt Target State \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure \return 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Target State \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Clear Interrupt Target State \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 if interrupt is assigned to Secure 1 if interrupt is assigned to Non Secure \note IRQn must not be negative. */ __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Set Priority Grouping (non-secure) \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB_NS->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB_NS->AIRCR = reg_value; } /** \brief Get Priority Grouping (non-secure) \details Reads the priority grouping field from the non-secure NVIC when in secure state. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) { return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt (non-secure) \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Interrupt Enable status (non-secure) \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt (non-secure) \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Pending Interrupt (non-secure) \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt (non-secure) \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt (non-secure) \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt (non-secure) \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority (non-secure) \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every non-secure processor exception. */ __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority (non-secure) \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv8.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## SAU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SAUFunctions SAU Functions \brief Functions that configure the SAU. @{ */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief Enable SAU \details Enables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Enable(void) { SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); } /** \brief Disable SAU \details Disables the Security Attribution Unit (SAU). */ __STATIC_INLINE void TZ_SAU_Disable(void) { SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /*@} end of CMSIS_Core_SAUFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** \brief System Tick Configuration (non-secure) \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function TZ_SysTick_Config_NS is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM35P_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm4.h ================================================ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V5.1.0 * @date 13. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ #include "cmsis_version.h" /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (4U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000U #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = FPU->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_cm7.h ================================================ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File * @version V5.1.1 * @date 28. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM7_H_GENERIC #define __CORE_CM7_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M7 @{ */ #include "cmsis_version.h" /* CMSIS CM7 definitions */ #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (7U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0U #endif #else #define __FPU_USED 0U #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM7_H_DEPENDANT #define __CORE_CM7_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM7_REV #define __CM7_REV 0x0000U #warning "__CM7_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __ICACHE_PRESENT #define __ICACHE_PRESENT 0U #warning "__ICACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DCACHE_PRESENT #define __DCACHE_PRESENT 0U #warning "__DCACHE_PRESENT not defined in device header file; using default!" #endif #ifndef __DTCM_PRESENT #define __DTCM_PRESENT 0U #warning "__DTCM_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M7 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ #define APSR_GE_Pos 16U /*!< APSR: GE Position */ #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[1U]; __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED3[93U]; __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ uint32_t RESERVED7[6U]; __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ uint32_t RESERVED8[1U]; __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* SCB Cache Level ID Register Definitions */ #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ /* SCB Cache Type Register Definitions */ #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* SCB Cache Size ID Register Definitions */ #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* SCB Cache Size Selection Register Definitions */ #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register Definitions */ #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* SCB D-Cache Invalidate by Set-way Register Definitions */ #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ /* SCB D-Cache Clean by Set-way Register Definitions */ #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ /* Instruction Tightly-Coupled Memory Control Register Definitions */ #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Register Definitions */ #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register Definitions */ #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register Definitions */ #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS Control Register Definitions */ #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register Definitions */ #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ #define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ #define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ #define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ #define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ #define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ #define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ #define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ #define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ #define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ uint32_t RESERVED3[981U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; #define MPU_TYPE_RALIASES 4U /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1U]; __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register Definitions */ #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register Definitions */ #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 Definitions */ #define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ #define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ /*@} end of group CMSIS_FPU */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; __DSB(); } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## MPU functions #################################### */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #include "mpu_armv7.h" #endif /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { uint32_t mvfr0; mvfr0 = SCB->MVFR0; if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { return 2U; /* Double + Single precision FPU */ } else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { return 1U; /* Single precision FPU */ } else { return 0U; /* No FPU */ } } /*@} end of CMSIS_Core_FpuFunctions */ /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions \brief Functions that configure Instruction and Data cache. @{ */ /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ #define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ /** \brief Enable I-Cache \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable I-Cache \details Turns off I-Cache */ __STATIC_FORCEINLINE void SCB_DisableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ SCB->ICIALLU = 0UL; /* invalidate I-Cache */ __DSB(); __ISB(); #endif } /** \brief Invalidate I-Cache \details Invalidates I-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) __DSB(); __ISB(); SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif } /** \brief I-Cache Invalidate by address \details Invalidates I-Cache for the given address. I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. I-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] isize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if ( isize > 0 ) { int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_ICACHE_LINE_SIZE; op_size -= __SCB_ICACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief Enable D-Cache \details Turns on D-Cache */ __STATIC_FORCEINLINE void SCB_EnableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ __DSB(); __ISB(); #endif } /** \brief Disable D-Cache \details Turns off D-Cache */ __STATIC_FORCEINLINE void SCB_DisableDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Invalidate D-Cache \details Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_InvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean D-Cache \details Cleans D-Cache */ __STATIC_FORCEINLINE void SCB_CleanDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief Clean & Invalidate D-Cache \details Cleans and Invalidates D-Cache */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; SCB->CSSELR = 0U; /* select Level 1 data cache */ __DSB(); ccsidr = SCB->CCSIDR; /* clean & invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); do { SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); } while(sets-- != 0U); __DSB(); __ISB(); #endif } /** \brief D-Cache Invalidate by address \details Invalidates D-Cache for the given address. D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are invalidated. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean by address \details Cleans D-Cache for the given address D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned. \param[in] addr address \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /** \brief D-Cache Clean and Invalidate by address \details Cleans and invalidates D_Cache for the given address D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. \param[in] addr address (aligned to 32-byte boundary) \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; __DSB(); do { SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ op_addr += __SCB_DCACHE_LINE_SIZE; op_size -= __SCB_DCACHE_LINE_SIZE; } while ( op_size > 0 ); __DSB(); __ISB(); } #endif } /*@} end of CMSIS_Core_CacheFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_CM7_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_sc000.h ================================================ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.6 * @date 12. November 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ #include "cmsis_version.h" /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000U #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31U]; __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31U]; __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31U]; __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31U]; uint32_t RESERVED4[64U]; __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1U]; __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2U]; __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the SC000 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /* Interrupt Priorities are WORD accessible only under Armv6-M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } else { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t *vectors = (uint32_t *)SCB->VTOR; return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/core_sc300.h ================================================ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.8 * @date 31. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC #include #ifdef __cplusplus extern "C" { #endif /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ #include "cmsis_version.h" /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_FP #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __CSMC__ ) #if ( __CSMC__ & 0x400U) #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT #ifdef __cplusplus extern "C" { #endif /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000U #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /* following defines should be used for structure members */ #define __IM volatile const /*! Defines 'read only' structure member permissions */ #define __OM volatile /*! Defines 'write only' structure member permissions */ #define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /* APSR Register Definitions */ #define APSR_N_Pos 31U /*!< APSR: N Position */ #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ #define APSR_Z_Pos 30U /*!< APSR: Z Position */ #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ #define APSR_C_Pos 29U /*!< APSR: C Position */ #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ #define APSR_V_Pos 28U /*!< APSR: V Position */ #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ #define APSR_Q_Pos 27U /*!< APSR: Q Position */ #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /* IPSR Register Definitions */ #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ uint32_t T:1; /*!< bit: 24 Thumb bit */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /* xPSR Register Definitions */ #define xPSR_N_Pos 31U /*!< xPSR: N Position */ #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ #define xPSR_C_Pos 29U /*!< xPSR: C Position */ #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ #define xPSR_V_Pos 28U /*!< xPSR: V Position */ #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /* CONTROL Register Definitions */ #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24U]; __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56U]; __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644U]; __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5U]; __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ uint32_t RESERVED1[129U]; __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Register Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ /* SCB Hard Fault Status Register Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __OM union { __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864U]; __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15U]; __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6U]; __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1U]; __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1U]; __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1U]; __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55U]; __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759U]; __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1U]; __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register Definitions */ #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register Definitions */ #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register Definitions */ #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). @{ */ /** \brief Mask and shift a bit field value for use in a register bit range. \param[in] field Name of the register bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. \return Masked and shifted value. */ #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) /** \brief Mask and shift a register value to extract a bit filed value. \param[in] field Name of the register bit field. \param[in] value Value of register. This parameter is interpreted as an uint32_t type. \return Masked and shifted bit field value. */ #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) /*@} end of group CMSIS_core_bitfield */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Core Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ #ifdef CMSIS_NVIC_VIRTUAL #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" #endif #include CMSIS_NVIC_VIRTUAL_HEADER_FILE #else #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping #define NVIC_EnableIRQ __NVIC_EnableIRQ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ #define NVIC_DisableIRQ __NVIC_DisableIRQ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ #define NVIC_GetActive __NVIC_GetActive #define NVIC_SetPriority __NVIC_SetPriority #define NVIC_GetPriority __NVIC_GetPriority #define NVIC_SystemReset __NVIC_SystemReset #endif /* CMSIS_NVIC_VIRTUAL */ #ifdef CMSIS_VECTAB_VIRTUAL #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" #endif #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE #else #define NVIC_SetVector __NVIC_SetVector #define NVIC_GetVector __NVIC_GetVector #endif /* (CMSIS_VECTAB_VIRTUAL) */ #define NVIC_USER_IRQ_OFFSET 16 /* The following EXC_RETURN values are saved the LR on exception entry */ #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } /** \brief Enable Interrupt \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __COMPILER_BARRIER(); } } /** \brief Get Interrupt Enable status \details Returns a device specific interrupt enable status from the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt is not enabled. \return 1 Interrupt is enabled. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Disable Interrupt \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); __DSB(); __ISB(); } } /** \brief Get Pending Interrupt \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Pending Interrupt \details Sets the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Clear Pending Interrupt \details Clears the pending bit of a device specific interrupt in the NVIC pending register. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); } } /** \brief Get Active Interrupt \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. \param [in] IRQn Device specific interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. \note IRQn must not be negative. */ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } else { return(0U); } } /** \brief Set Interrupt Priority \details Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if ((int32_t)(IRQn) >= 0) { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } /** \brief Get Interrupt Priority \details Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); } else { return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); } } /** \brief Encode Priority \details Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } /** \brief Decode Priority \details Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } /** \brief Set Interrupt Vector \details Sets an interrupt vector in SRAM based interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. VTOR must been relocated to SRAM before. \param [in] IRQn Interrupt number \param [in] vector Address of interrupt handler function */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } /** \brief Get Interrupt Vector \details Reads an interrupt vector from interrupt vector table. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception. \param [in] IRQn Interrupt number. \return Address of interrupt handler function */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { uint32_t vectors = (uint32_t )SCB->VTOR; return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); } /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); } } /*@} end of CMSIS_Core_NVICFunctions */ /* ########################## FPU functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_FpuFunctions FPU Functions \brief Function that provides FPU type. @{ */ /** \brief get FPU type \details returns the FPU type \returns - \b 0: No FPU - \b 1: Single precision FPU - \b 2: Double + Single precision FPU */ __STATIC_INLINE uint32_t SCB_GetFPUType(void) { return 0U; /* No FPU */ } /*@} end of CMSIS_Core_FpuFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) /** \brief System Tick Configuration \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); /* Reload value impossible */ } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character \details Transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); } ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } /** \brief ITM Receive Character \details Inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #ifdef __cplusplus } #endif #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/mpu_armv7.h ================================================ /****************************************************************************** * @file mpu_armv7.h * @brief CMSIS MPU API for Armv7-M MPU * @version V5.1.0 * @date 08. March 2019 ******************************************************************************/ /* * Copyright (c) 2017-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access /** MPU Region Base Address Register Value * * \param Region The region to be configured, number 0 to 15. * \param BaseAddress The base address for the region. */ #define ARM_MPU_RBAR(Region, BaseAddress) \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \ (MPU_RBAR_VALID_Msk)) /** * MPU Memory Access Attributes * * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. */ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ (((MPU_RASR_ENABLE_Msk)))) /** * MPU Region Attribute and Size Register Value * * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. */ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) /** * MPU Memory Access Attribute for strongly ordered memory. * - TEX: 000b * - Shareable * - Non-cacheable * - Non-bufferable */ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** * MPU Memory Access Attribute for device memory. * - TEX: 000b (if shareable) or 010b (if non-shareable) * - Shareable or non-shareable * - Non-cacheable * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** * MPU Memory Access Attribute for normal memory. * - TEX: 1BBb (reflecting outer cacheability rules) * - Shareable or non-shareable * - Cacheable or non-cacheable (reflecting inner cacheability rules) * - Bufferable or non-bufferable (reflecting inner cacheability rules) * * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. */ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) /** * MPU Memory Access Attribute non-cacheable policy. */ #define ARM_MPU_CACHEP_NOCACHE 0U /** * MPU Memory Access Attribute write-back, write and read allocate policy. */ #define ARM_MPU_CACHEP_WB_WRA 1U /** * MPU Memory Access Attribute write-through, no write allocate policy. */ #define ARM_MPU_CACHEP_WT_NWA 2U /** * MPU Memory Access Attribute write-back, no write allocate policy. */ #define ARM_MPU_CACHEP_WB_NWA 3U /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { MPU->RNR = rnr; MPU->RASR = 0U; } /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; MPU->RASR = rasr; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; MPU->RBAR = rbar; MPU->RASR = rasr; } /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); table += MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES; } ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); } #endif ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/mpu_armv8.h ================================================ /****************************************************************************** * @file mpu_armv8.h * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU * @version V5.1.0 * @date 08. March 2019 ******************************************************************************/ /* * Copyright (c) 2017-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H /** \brief Attribute for device memory (outer only) */ #define ARM_MPU_ATTR_DEVICE ( 0U ) /** \brief Attribute for non-cacheable, normal memory */ #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) /** \brief Attribute for normal memory (outer and inner) * \param NT Non-Transient: Set to 1 for non-transient data. * \param WB Write-Back: Set to 1 to use write-back update policy. * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. */ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGRE (2U) /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_GRE (3U) /** \brief Memory Attribute * \param O Outer memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes */ #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) /** \brief Normal memory non-shareable */ #define ARM_MPU_SH_NON (0U) /** \brief Normal memory outer shareable */ #define ARM_MPU_SH_OUTER (2U) /** \brief Normal memory inner shareable */ #define ARM_MPU_SH_INNER (3U) /** \brief Memory access permissions * \param RO Read-Only: Set to 1 for read-only memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory. */ #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) /** \brief Region Base Address Register value * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. * \param SH Defines the Shareability domain for this memory region. * \param RO Read-Only: Set to 1 for a read-only memory region. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ ((BASE & MPU_RBAR_BASE_Msk) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) /** \brief Region Limit Address Register value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR(LIMIT, IDX) \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) #if defined(MPU_RLAR_PXN_Pos) /** \brief Region Limit Address Register with PXN value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) #endif /** * Struct for a single MPU Region */ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #ifdef MPU_NS /** Enable the Non-secure MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif __DSB(); __ISB(); } /** Disable the Non-secure MPU. */ __STATIC_INLINE void ARM_MPU_Disable_NS(void) { __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; } #endif /** Set the memory attribute encoding to the given MPU. * \param mpu Pointer to the MPU to be configured. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) { const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } /** Set the memory attribute encoding. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU, idx, attr); } #ifdef MPU_NS /** Set the memory attribute encoding to the Non-secure MPU. * \param idx The attribute index to be set [0-7] * \param attr The attribute value to be set. */ __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) { ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); } #endif /** Clear and disable the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) { mpu->RNR = rnr; mpu->RLAR = 0U; } /** Clear and disable the given MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU, rnr); } #ifdef MPU_NS /** Clear and disable the given Non-secure MPU region. * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) { ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif /** Configure the given MPU region of the given MPU. * \param mpu Pointer to MPU to be used. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; mpu->RBAR = rbar; mpu->RLAR = rlar; } /** Configure the given MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); } #ifdef MPU_NS /** Configure the given Non-secure MPU region. * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. */ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif /** Memcopy with strictly ordered memory access, e.g. for register targets. * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) { dst[i] = src[i]; } } /** Load the given number of MPU regions from a table to the given MPU. * \param mpu Pointer to the MPU registers to be used. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); table += c; cnt -= c; rnrOffset = 0U; rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } /** Load the given number of MPU regions from a table. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } #ifdef MPU_NS /** Load the given number of MPU regions from a table to the Non-secure MPU. * \param rnr First region number to be configured. * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } #endif #endif ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/Include/tz_context.h ================================================ /****************************************************************************** * @file tz_context.h * @brief Context Management for Armv8-M TrustZone * @version V1.0.1 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H #include #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); #endif // TZ_CONTEXT_H ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/CMSIS/LICENSE.txt ================================================ Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 1. 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See the License for the specific language governing permissions and limitations under the License. ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h ================================================ /** ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32_HAL_LEGACY #define STM32_HAL_LEGACY #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose * @{ */ #define AES_FLAG_RDERR CRYP_FLAG_RDERR #define AES_FLAG_WRERR CRYP_FLAG_WRERR #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR #if defined(STM32U5) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF #endif /* STM32U5 */ /** * @} */ /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose * @{ */ #define ADC_RESOLUTION12b ADC_RESOLUTION_12B #define ADC_RESOLUTION10b ADC_RESOLUTION_10B #define ADC_RESOLUTION8b ADC_RESOLUTION_8B #define ADC_RESOLUTION6b ADC_RESOLUTION_6B #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV #define REGULAR_GROUP ADC_REGULAR_GROUP #define INJECTED_GROUP ADC_INJECTED_GROUP #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP #define AWD_EVENT ADC_AWD_EVENT #define AWD1_EVENT ADC_AWD1_EVENT #define AWD2_EVENT ADC_AWD2_EVENT #define AWD3_EVENT ADC_AWD3_EVENT #define OVR_EVENT ADC_OVR_EVENT #define JQOVF_EVENT ADC_JQOVF_EVENT #define ALL_CHANNELS ADC_ALL_CHANNELS #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG /** * @} */ /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose * @{ */ #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR #endif /* STM32F373xC || STM32F378xx */ #if defined(STM32L0) || defined(STM32L4) #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 #if defined(STM32L0) /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ /* to the second dedicated IO (only for COMP2). */ #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 #else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 #endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ #if defined(COMP_CSR_LOCK) #define COMP_FLAG_LOCK COMP_CSR_LOCK #elif defined(COMP_CSR_COMP1LOCK) #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK #elif defined(COMP_CSR_COMPxLOCK) #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK #endif #if defined(STM32L4) #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE #endif #if defined(STM32L0) #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER #else #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER #endif #endif /** * @} */ /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig #if defined(STM32U5) #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE #endif /* STM32U5 */ /** * @} */ /** @defgroup CRC_Aliases CRC API aliases * @{ */ #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ /** * @} */ /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE /** * @} */ /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose * @{ */ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 #define DAC_WAVE_NONE 0x00000000U #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif #if defined(STM32U5) #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #endif #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif /** * @} */ /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose * @{ */ #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 #define IS_HAL_REMAPDMA IS_DMA_REMAP #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE #if defined(STM32L4) #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI #endif #endif /* STM32L4 */ #if defined(STM32G0) #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM #endif #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose * @{ */ #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE #define OBEX_PCROP OPTIONBYTE_PCROP #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD #define PAGESIZE FLASH_PAGE_SIZE #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS #define OB_WDG_SW OB_IWDG_SW #define OB_WDG_HW OB_IWDG_HW #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 #if defined(STM32G0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 #define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U5 */ /** * @} */ /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose * @{ */ #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 #if defined(STM32G4) #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ /** * @} */ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 #endif /** * @} */ /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose * @{ */ #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef /** * @} */ /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose * @{ */ #define GET_GPIO_SOURCE GPIO_GET_INDEX #define GET_GPIO_INDEX GPIO_GET_INDEX #if defined(STM32F4) #define GPIO_AF12_SDMMC GPIO_AF12_SDIO #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO #endif #if defined(STM32F7) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32L4) #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 #endif #if defined(STM32H7) #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 #if defined(STM32U5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ #endif /* STM32U5 */ /** * @} */ /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose * @{ */ #if defined(STM32U5) #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI #endif /* STM32U5 */ /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 #endif /* STM32H7 */ #if defined(STM32F3) /** @brief Constants defining available sources associated to external events. */ #define HRTIM_EVENTSRC_1 (0x00000000U) #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) #endif /* STM32F3 */ /** * @} */ /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose * @{ */ #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose * @{ */ #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose * @{ */ #define KR_KEY_RELOAD IWDG_KEY_RELOAD #define KR_KEY_ENABLE IWDG_KEY_ENABLE #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS /* The following 3 definition have also been present in a temporary version of lptim.h */ /* They need to be renamed also to the right name, just in case */ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for legacy purpose * @{ */ #define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 #define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 #define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 #define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /** * @} */ #if defined(STM32U5) #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF #define LPTIM_CHANNEL_ALL 0x00000000U #endif /* STM32U5 */ /** * @} */ /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose * @{ */ #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b #define NAND_AddressTypedef NAND_AddressTypeDef #define __ARRAY_ADDRESS ARRAY_ADDRESS #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE /** * @} */ /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose * @{ */ #define NOR_StatusTypedef HAL_NOR_StatusTypeDef #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS #define NOR_ONGOING HAL_NOR_STATUS_ONGOING #define NOR_ERROR HAL_NOR_STATUS_ERROR #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT #define __NOR_WRITE NOR_WRITE #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose * @{ */ #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif #if defined(STM32L4) || defined(STM32L5) #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER #elif defined(STM32G4) #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED #endif /** * @} */ /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose * @{ */ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) #define I2S_IT_TXE I2S_IT_TXP #define I2S_IT_RXNE I2S_IT_RXP #define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} */ /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose * @{ */ /* Compact Flash-ATA registers description */ #define CF_DATA ATA_DATA #define CF_SECTOR_COUNT ATA_SECTOR_COUNT #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER #define CF_CYLINDER_LOW ATA_CYLINDER_LOW #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH #define CF_CARD_HEAD ATA_CARD_HEAD #define CF_STATUS_CMD ATA_STATUS_CMD #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA /* Compact Flash-ATA commands */ #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT /** * @} */ /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ #define FORMAT_BIN RTC_FORMAT_BIN #define FORMAT_BCD RTC_FORMAT_BCD #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose * @{ */ #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose * @{ */ #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN /** * @} */ /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose * @{ */ #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE #if defined(STM32H7) #define SPI_FLAG_TXE SPI_FLAG_TXP #define SPI_FLAG_RXNE SPI_FLAG_RXP #define SPI_IT_TXE SPI_IT_TXP #define SPI_IT_RXNE SPI_IT_RXP #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ /** * @} */ /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose * @{ */ #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK #define TIM_DMABase_CR1 TIM_DMABASE_CR1 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR #define TIM_DMABase_DIER TIM_DMABASE_DIER #define TIM_DMABase_SR TIM_DMABASE_SR #define TIM_DMABase_EGR TIM_DMABASE_EGR #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 #define TIM_DMABase_CCER TIM_DMABASE_CCER #define TIM_DMABase_CNT TIM_DMABASE_CNT #define TIM_DMABase_PSC TIM_DMABASE_PSC #define TIM_DMABase_ARR TIM_DMABASE_ARR #define TIM_DMABase_RCR TIM_DMABASE_RCR #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR #define TIM_DMABase_DCR TIM_DMABASE_DCR #define TIM_DMABase_DMAR TIM_DMABASE_DMAR #define TIM_DMABase_OR1 TIM_DMABASE_OR1 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 #define TIM_DMABase_OR TIM_DMABASE_OR #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS #if defined(STM32L0) #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO #endif #if defined(STM32F3) #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #endif #if defined(STM32H7) #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif /** * @} */ /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose * @{ */ #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING /** * @} */ /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose * @{ */ #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 #define __DIV_LPUART UART_DIV_LPUART #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK /** * @} */ /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose * @{ */ #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE #define USARTNACK_ENABLED USART_NACK_ENABLE #define USARTNACK_DISABLED USART_NACK_DISABLE /** * @} */ /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose * @{ */ #define CFR_BASE WWDG_CFR_BASE /** * @} */ /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose * @{ */ #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) #define CAN_TXSTATUS_OK ((uint8_t)0x01U) #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) /** * @} */ /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose * @{ */ #define VLAN_TAG ETH_VLAN_TAG #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK #define ETH_MMCCR 0x00000100U #define ETH_MMCRIR 0x00000104U #define ETH_MMCTIR 0x00000108U #define ETH_MMCRIMR 0x0000010CU #define ETH_MMCTIMR 0x00000110U #define ETH_MMCTGFSCCR 0x0000014CU #define ETH_MMCTGFMSCCR 0x00000150U #define ETH_MMCTGFCR 0x00000168U #define ETH_MMCRFCECR 0x00000194U #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} */ /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose * @{ */ #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR #define DCMI_IT_OVF DCMI_IT_OVR #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop /** * @} */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ || defined(STM32H7) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ */ #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 #define CM_RGB888 DMA2D_INPUT_RGB888 #define CM_RGB565 DMA2D_INPUT_RGB565 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 #define CM_L8 DMA2D_INPUT_L8 #define CM_AL44 DMA2D_INPUT_AL44 #define CM_AL88 DMA2D_INPUT_AL88 #define CM_L4 DMA2D_INPUT_L4 #define CM_A8 DMA2D_INPUT_A8 #define CM_A4 DMA2D_INPUT_A4 /** * @} */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ || defined(STM32H7) || defined(STM32U5) /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ /** * @} */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback /** * @} */ /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose * @{ */ #if defined(STM32U5) #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT #endif /* STM32U5 */ /** * @} */ #if !defined(STM32F2) /** @defgroup HASH_alias HASH API alias * @{ */ #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ /** * * @} */ #endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish /*HASH Algorithm Selection*/ #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose * @{ */ #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) #else #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ /** * @} */ /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose * @{ */ #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program /** * @} */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ */ #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ #if defined(STM32G0) #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING #define CR_OFFSET_BB PWR_CR_OFFSET_BB #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB #define PMODE_BIT_NUMBER VOS_BIT_NUMBER #define CR_PMODE_BB CR_VOS_BB #define DBP_BitNumber DBP_BIT_NUMBER #define PVDE_BitNumber PVDE_BIT_NUMBER #define PMODE_BitNumber PMODE_BIT_NUMBER #define EWUP_BitNumber EWUP_BIT_NUMBER #define FPDS_BitNumber FPDS_BIT_NUMBER #define ODEN_BitNumber ODEN_BIT_NUMBER #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER #define BRE_BitNumber BRE_BIT_NUMBER #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback /** * @} */ /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose * @{ */ #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo /** * @} */ /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose * @{ */ #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose * @{ */ #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /** * @} */ /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose * @{ */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback #define HAL_LTDC_Relaod HAL_LTDC_Reload #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} */ /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose * @{ */ /** * @} */ /* Exported macros ------------------------------------------------------------*/ /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose * @{ */ #define AES_IT_CC CRYP_IT_CC #define AES_IT_ERR CRYP_IT_ERR #define AES_FLAG_CCF CRYP_FLAG_CCF /** * @} */ /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER /** * @} */ /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose * @{ */ #define __ADC_ENABLE __HAL_ADC_ENABLE #define __ADC_DISABLE __HAL_ADC_DISABLE #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE #define __ADC_IS_ENABLED ADC_IS_ENABLE #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION #define __HAL_ADC_JSQR_RK ADC_JSQR_RK #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER #define __HAL_ADC_SQR1 ADC_SQR1 #define __HAL_ADC_SMPR1 ADC_SMPR1 #define __HAL_ADC_SMPR2 ADC_SMPR2 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK #define __HAL_ADC_SQR2_RK ADC_SQR2_RK #define __HAL_ADC_SQR1_RK ADC_SQR1_RK #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq #define __HAL_ADC_JSQR ADC_JSQR #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ /** * @} */ /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE /** * @} */ /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 /** * @} */ /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32F3) #define COMP_START __HAL_COMP_ENABLE #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP6_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP6_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ __HAL_COMP_COMP6_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP7_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP7_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ __HAL_COMP_COMP7_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) # endif # if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) # endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ __HAL_COMP_COMP2_EXTI_ENABLE_IT()) #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ __HAL_COMP_COMP2_EXTI_DISABLE_IT()) #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) #endif #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE #if defined(STM32L0) || defined(STM32L4) /* Note: On these STM32 families, the only argument of this macro */ /* is COMP_FLAG_LOCK. */ /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ /* argument. */ #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) #endif /** * @} */ #if defined(STM32L0) || defined(STM32L4) /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ /** * @} */ #endif /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose * @{ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ ((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} */ /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose * @{ */ #define IS_WRPAREA IS_OB_WRPAREA #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM #define IS_TYPEERASE IS_FLASH_TYPEERASE #define IS_NBSECTORS IS_FLASH_NBSECTORS #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE /** * @} */ /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START #if defined(STM32F1) #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE #else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE #endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST #define __HAL_I2C_SPEED I2C_SPEED #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB #define __HAL_I2C_FREQRANGE I2C_FREQRANGE /** * @} */ /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose * @{ */ #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** * @} */ /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose * @{ */ #define __IRDA_DISABLE __HAL_IRDA_DISABLE #define __IRDA_ENABLE __HAL_IRDA_ENABLE #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS /** * @} */ /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE /** * @} */ /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose * @{ */ #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET /** * @} */ /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB #if defined (STM32F4) #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() #else #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG #endif /* STM32F4 */ /** * @} */ /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose * @{ */ #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET #if defined(STM32WB) #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED #define QSPI_IRQHandler QUADSPI_IRQHandler #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET #if defined(STM32H7) #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE /* alias define maintained for legacy */ #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED #if defined(STM32L1) #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET #endif /* STM32L1 */ #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED #define Sdmmc1ClockSelection SdioClockSelection #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE #endif #if defined(STM32F7) || defined(STM32L4) #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED #define SdioClockSelection Sdmmc1ClockSelection #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif #if defined(STM32F7) #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK #endif #if defined(STM32H7) #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() #endif #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK #define IS_RCC_HCLK_DIV IS_RCC_PCLK #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK #define RCC_IT_HSI14 RCC_IT_HSI14RDY #define RCC_IT_CSSLSE RCC_IT_LSECSS #define RCC_IT_CSSHSE RCC_IT_CSS #define RCC_PLLMUL_3 RCC_PLL_MUL3 #define RCC_PLLMUL_4 RCC_PLL_MUL4 #define RCC_PLLMUL_6 RCC_PLL_MUL6 #define RCC_PLLMUL_8 RCC_PLL_MUL8 #define RCC_PLLMUL_12 RCC_PLL_MUL12 #define RCC_PLLMUL_16 RCC_PLL_MUL16 #define RCC_PLLMUL_24 RCC_PLL_MUL24 #define RCC_PLLMUL_32 RCC_PLL_MUL32 #define RCC_PLLMUL_48 RCC_PLL_MUL48 #define RCC_PLLDIV_2 RCC_PLL_DIV2 #define RCC_PLLDIV_3 RCC_PLL_DIV3 #define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG #define RCC_MCO_NODIV RCC_MCODIV_1 #define RCC_MCO_DIV1 RCC_MCODIV_1 #define RCC_MCO_DIV2 RCC_MCODIV_2 #define RCC_MCO_DIV4 RCC_MCODIV_4 #define RCC_MCO_DIV8 RCC_MCODIV_8 #define RCC_MCO_DIV16 RCC_MCODIV_16 #define RCC_MCO_DIV32 RCC_MCODIV_32 #define RCC_MCO_DIV64 RCC_MCODIV_64 #define RCC_MCO_DIV128 RCC_MCODIV_128 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 #define HSION_BitNumber RCC_HSION_BIT_NUMBER #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER #define LSION_BitNumber RCC_LSION_BIT_NUMBER #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE #define CR_HSION_BB RCC_CR_HSION_BB #define CR_CSSON_BB RCC_CR_CSSON_BB #define CR_PLLON_BB RCC_CR_PLLON_BB #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB #define CR_MSION_BB RCC_CR_MSION_BB #define CSR_LSION_BB RCC_CSR_LSION_BB #define CSR_LSEON_BB RCC_CSR_LSEON_BB #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB #define CR_HSEON_BB RCC_CR_HSEON_BB #define CSR_RMVF_BB RCC_CSR_RMVF_BB #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #if defined(STM32U5) #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET #endif /** * @} */ /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose * @{ */ #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) /** * @} */ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT #if defined (STM32F1) #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE /** * @} */ /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV #endif #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND /* alias CMSIS */ #define SDMMC1_IRQn SDIO_IRQn #define SDMMC1_IRQHandler SDIO_IRQHandler #endif #if defined(STM32F7) || defined(STM32L4) #define SD_SDIO_DISABLED SD_SDMMC_DISABLED #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif #if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback #endif /** * @} */ /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose * @{ */ #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED /** * @} */ /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_SPI_1LINE_TX SPI_1LINE_TX #define __HAL_SPI_1LINE_RX SPI_1LINE_RX #define __HAL_SPI_RESET_CRC SPI_RESET_CRC /** * @} */ /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE /** * @} */ /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose * @{ */ #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT #define __USART_ENABLE __HAL_USART_ENABLE #define __USART_DISABLE __HAL_USART_DISABLE #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) #define USART_OVERSAMPLING_16 0x00000000U #define USART_OVERSAMPLING_8 USART_CR1_OVER8 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ ((__SAMPLING__) == USART_OVERSAMPLING_8)) #endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose * @{ */ #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo /** * @} */ /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 /** * @} */ /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE /** * @} */ /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose * @{ */ #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE #define SAI_STREOMODE SAI_STEREOMODE #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE /** * @} */ /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose * @{ */ #if defined(STM32H7) #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA #endif /** * @} */ /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose * @{ */ #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} */ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE #endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose * @{ */ #if defined (STM32F7) #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE #endif /* STM32F7 */ /** * @} */ /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32_HAL_LEGACY */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal.h * @author MCD Application Team * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_H #define STM32G4xx_HAL_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_conf.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup HAL HAL * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup HAL_Exported_Constants HAL Exported Constants * @{ */ /** @defgroup HAL_TICK_FREQ Tick Frequency * @{ */ #define HAL_TICK_FREQ_10HZ 100U #define HAL_TICK_FREQ_100HZ 10U #define HAL_TICK_FREQ_1KHZ 1U #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ /** * @} */ /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants * @{ */ /** @defgroup SYSCFG_BootMode Boot Mode * @{ */ #define SYSCFG_BOOT_MAINFLASH 0x00000000U #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0 #if defined (FMC_BANK1) #define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1 #endif /* FMC_BANK1 */ #define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0) #if defined (QUADSPI) #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1) #endif /* QUADSPI */ /** * @} */ /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts * @{ */ #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ /** * @} */ /** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection * @{ */ #define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */ #define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */ #define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */ #define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */ #define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */ #define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */ #define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */ #define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */ #define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */ #define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */ #define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */ #define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */ #define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */ #define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */ #define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */ #define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */ #define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */ #define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */ #define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */ #define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */ #define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */ #define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */ #define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */ #define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */ #define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */ #define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */ #define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */ #define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */ #define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */ #define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */ #define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */ #define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */ /** * @} */ #if defined(VREFBUF) /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale * @{ */ #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */ #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */ #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */ /** * @} */ /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance * @{ */ #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ /** * @} */ #endif /* VREFBUF */ /** @defgroup SYSCFG_flags_definition Flags * @{ */ #define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */ #define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */ /** * @} */ /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO * @{ */ /** @brief Fast-mode Plus driving capability on a specific GPIO */ #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ /** * @} */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros * @{ */ /** @brief Freeze/Unfreeze Peripherals in Debug mode */ #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) #endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) #endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */ #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) #endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */ #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */ #if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP) #define __HAL_DBGMCU_FREEZE_TIM20() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM20() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP) #endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */ #if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP) #define __HAL_DBGMCU_FREEZE_HRTIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_HRTIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP) #endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */ /** * @} */ /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros * @{ */ /** @brief Main Flash memory mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) /** @brief System Flash memory mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) /** @brief Embedded SRAM mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) #if defined (FMC_BANK1) /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) #endif /* FMC_BANK1 */ #if defined (QUADSPI) /** @brief QUADSPI mapped at 0x00000000. */ #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) #endif /* QUADSPI */ /** * @brief Return the boot mode as configured by user. * @retval The boot mode as configured by user. The returned value can be one * of the following values: * @arg @ref SYSCFG_BOOT_MAINFLASH * @arg @ref SYSCFG_BOOT_SYSTEMFLASH * @arg @ref SYSCFG_BOOT_FMC (*) * @arg @ref SYSCFG_BOOT_QUADSPI (*) * @arg @ref SYSCFG_BOOT_SRAM * @note (*) availability depends on devices */ #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) /** @brief CCMSRAM page write protection enable macro * @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP * @note write protection can only be disabled by a system reset * @retval None */ /* Legacy define */ #define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE #define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\ SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\ }while(0) /** @brief CCMSRAM page write protection unlock prior to erase * @note Writing a wrong key reactivates the write protection */ #define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ SYSCFG->SKR = 0x53;\ }while(0) /** @brief CCMSRAM erase * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase */ #define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER) /** @brief Floating Point Unit interrupt enable/disable macros * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts */ #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ }while(0) #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ }while(0) /** @brief SYSCFG Break ECC lock. * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. * @note The selected configuration is locked and can be unlocked only by system reset. */ #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) /** @brief SYSCFG Break Cortex-M4 Lockup lock. * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. * @note The selected configuration is locked and can be unlocked only by system reset. */ #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) /** @brief SYSCFG Break PVD lock. * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. * @note The selected configuration is locked and can be unlocked only by system reset. */ #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) /** @brief SYSCFG Break SRAM parity lock. * Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input. * @note The selected configuration is locked and can be unlocked by system reset. */ #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) /** @brief Check SYSCFG flag is set or not. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag * @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ & (__FLAG__))!= 0U) ? 1U : 0U) /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. */ #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) /** @brief Fast-mode Plus driving capability enable/disable macros * @param __FASTMODEPLUS__: This parameter can be a value of : * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 */ #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0) #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ }while(0) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros * @{ */ #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \ ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) #if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL) #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U) #elif (CCMSRAM_SIZE == 0x00002800UL) #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU)) #endif /* CCMSRAM_SIZE */ #if defined(VREFBUF) #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2)) #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) #endif /* VREFBUF */ #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) #elif defined(SYSCFG_FASTMODEPLUS_PB8) #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) #elif defined(SYSCFG_FASTMODEPLUS_PB9) #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) #else #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) #endif /* SYSCFG_FASTMODEPLUS_PB */ /** * @} */ /** @defgroup HAL_Private_Macros HAL Private Macros * @{ */ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ ((FREQ) == HAL_TICK_FREQ_100HZ) || \ ((FREQ) == HAL_TICK_FREQ_1KHZ)) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup HAL_Exported_Functions * @{ */ /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ /* Initialization and Configuration functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); /** * @} */ /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions * @{ */ /* Peripheral Control functions ************************************************/ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); uint32_t HAL_GetTickPrio(void); HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); uint32_t HAL_GetTickFreq(void); void HAL_SuspendTick(void); void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); /** * @} */ /** @addtogroup HAL_Exported_Functions_Group3 * @{ */ /* DBGMCU Peripheral Control functions *****************************************/ void HAL_DBGMCU_EnableDBGSleepMode(void); void HAL_DBGMCU_DisableDBGSleepMode(void); void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} */ /* Exported variables ---------------------------------------------------------*/ /** @addtogroup HAL_Exported_Variables * @{ */ extern __IO uint32_t uwTick; extern uint32_t uwTickPrio; extern uint32_t uwTickFreq; /** * @} */ /** @addtogroup HAL_Exported_Functions_Group4 * @{ */ /* SYSCFG Control functions ****************************************************/ void HAL_SYSCFG_CCMSRAMErase(void); void HAL_SYSCFG_EnableMemorySwappingBank(void); void HAL_SYSCFG_DisableMemorySwappingBank(void); #if defined(VREFBUF) void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); void HAL_SYSCFG_DisableVREFBUF(void); #endif /* VREFBUF */ void HAL_SYSCFG_EnableIOSwitchBooster(void); void HAL_SYSCFG_DisableIOSwitchBooster(void); void HAL_SYSCFG_EnableIOSwitchVDD(void); void HAL_SYSCFG_DisableIOSwitchVDD(void); void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc.h * @author MCD Application Team * @brief Header file of ADC HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_ADC_H #define STM32G4xx_HAL_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /* Include low level driver */ #include "stm32g4xx_ll_adc.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ /** * @brief ADC group regular oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. The oversampling is either temporary stopped or reset upon an injected sequence interruption. If oversampling is enabled on both regular and injected groups, this parameter is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ } ADC_OversamplingTypeDef; /** * @brief Structure definition of ADC instance and ADC group regular. * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait. * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode. * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another parameter * (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock configuration is common to all ADC instances. Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled. */ uint32_t Resolution; /*!< Configure the ADC resolution. This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). Refer to reference manual for alignments formats versus resolutions. This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula: DATA = DATA(raw) * (gain compensation coef) / 4096 2.12 bit format, unsigned: 2 bits exponents / 12 bits mantissa Gain step is 1/4096 = 0.000244 Gain range is 0.0000 to 3.999756 This parameter value can be 0 Gain compensation will be disabled and coefficient set to 0 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value Note: Gain compensation when enabled is applied to all channels. */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). Scan direction is upward: from rank 1 to rank 'n'. This parameter can be a value of @ref ADC_Scan_mode */ uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. This parameter can be a value of @ref ADC_EOCSelection. */ FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. */ uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_regular_external_trigger_source. Caution: external trigger source is common to all ADC instances. */ uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. This parameter can be a value of @ref ADC_regular_sampling_mode */ FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) or in continuous mode (DMA transfer unlimited, whatever number of conversions). This parameter can be set to ENABLE or DISABLE. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode: - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ } ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) * on the fly). */ typedef struct { uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t Rank; /*!< Specify the rank in the regular group sequencer. This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME Caution: This parameter applies to a channel that can be used into regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values. */ uint32_t SingleDiff; /*!< Select single-ended or differential input. In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t OffsetNumber; /*!< Select the offset number This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ } ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC analog watchdog * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. * ADC state can be either: * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups. */ typedef struct { uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. This parameter can be a value of @ref ADC_analog_watchdog_mode. */ uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. Before setting flag or raising interrupt, analog watchdog can wait to have several consecutive out-of-window samples. This parameter allows to configure this number. This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ } ADC_AnalogWDGConfTypeDef; /** * @brief ADC group injected contexts queue configuration * @note Structure intended to be used only through structure "ADC_HandleTypeDef" */ typedef struct { uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ } ADC_InjectionConfigTypeDef; /** @defgroup ADC_States ADC States * @{ */ /** * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ /* States of ADC global scope */ #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ /* States of ADC group regular */ #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ /* States of ADC multi-mode */ #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ /** * @} */ /** * @brief ADC handle Structure definition */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) typedef struct __ADC_HandleTypeDef #else typedef struct #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ HAL_LockTypeDef Lock; /*!< ADC locking object */ __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ __IO uint32_t ErrorCode; /*!< ADC Error code */ ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief HAL ADC Callback ID enumeration definition */ typedef enum { HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ } HAL_ADC_CallbackIDTypeDef; /** * @brief HAL ADC Callback pointer definition */ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants ADC Exported Constants * @{ */ /** @defgroup ADC_Error_Code ADC Error Code * @{ */ #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, enable/disable, erroneous state, ...) */ #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ /** * @} */ /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution * @{ */ #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ /** * @} */ /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ /** @defgroup ADC_Scan_mode ADC sequencer scan mode * @{ */ #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ /** * @} */ /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source * @{ */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** * @} */ /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ /** * @} */ /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode * @{ */ #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: Trigger rising edge = start sampling Trigger falling edge = stop sampling and start conversion */ /** * @} */ /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions * @{ */ #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ /** * @} */ /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} */ /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ /** * @} */ /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ /** * @} */ /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number * @{ */ /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ /* all ADC instances (refer to Reference Manual). */ #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ #define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ #define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ #define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ #define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ #define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ #define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ #define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ /** * @} */ /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number * @{ */ #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ /** * @} */ /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration * @{ */ #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ #define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ #define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ #define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ #define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ #define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ #define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ #define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ /** * @} */ /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode * @{ */ #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio * @{ */ #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular * @{ */ #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ /** * @} */ /** @defgroup ADC_Event_type ADC Event type * @{ */ #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ /** * @} */ #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ /** @defgroup ADC_interrupts_definition ADC interrupts definition * @{ */ #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ /** * @} */ /** @defgroup ADC_flags_definition ADC flags definition * @{ */ #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ /** * @} */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief Return resolution bits in CFGR register RES[1:0] field. * @param __HANDLE__ ADC handle * @retval Value of bitfield RES in CFGR register. */ #define ADC_GET_RESOLUTION(__HANDLE__) \ (LL_ADC_GetResolution((__HANDLE__)->Instance)) /** * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Simultaneously clear and set specific bits of the handle State. * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), * the first parameter is the ADC handle State, the second parameter is the * bit field to clear, the third and last parameter is the bit field to set. * @retval None */ #define ADC_STATE_CLR_SET MODIFY_REG /** * @brief Verify that a given value is aligned with the ADC resolution range. * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) /** * @brief Verify the length of the scheduled regular conversions group. * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. * @param NUMBER number of scheduled regular conversions in discontinuous mode. * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) /** * @brief Verify the ADC clock setting. * @param __ADC_CLOCK__ programmed ADC clock. * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) */ #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) /** * @brief Verify the ADC resolution setting. * @param __RESOLUTION__ programmed ADC resolution. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) /** * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) */ #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) /** * @brief Verify the ADC converted data alignment. * @param __ALIGN__ programmed ADC converted data alignment. * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) */ #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) /** * @brief Verify the ADC gain compensation. * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient. * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid) */ #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL) /** * @brief Verify the ADC scan mode. * @param __SCAN_MODE__ programmed ADC scan mode. * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) */ #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) /** * @brief Verify the ADC edge trigger setting for regular group. * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) */ #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) /** * @brief Verify the ADC regular conversions external trigger. * @param __HANDLE__ ADC handle * @param __REGTRIG__ programmed ADC regular conversions external trigger. * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G471xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ (((__HANDLE__)->Instance == ADC3) && \ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #endif /** * @brief Verify the ADC regular conversions external trigger. * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) */ #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) /** * @brief Verify the ADC regular conversions check for converted data availability. * @param __EOC_SELECTION__ converted data availability check. * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) */ #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) /** * @brief Verify the ADC regular conversions overrun handling. * @param __OVR__ ADC regular conversions overrun handling. * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) */ #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) /** * @brief Verify the ADC conversions sampling time. * @param __TIME__ ADC conversions sampling time. * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) */ #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) /** * @brief Verify the ADC regular channel setting. * @param __CHANNEL__ programmed ADC regular channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @defgroup ADC_Private_Constants ADC Private Constants * @{ */ /* Fixed timeout values for ADC conversion (including sampling time) */ /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ /* Maximum conversion time is 12.5 + Maximum sampling time */ /* or 12.5 + 640.5 = 653 ADC clock cycles */ /* Minimum ADC Clock frequency is 0.14 MHz */ /* Maximum conversion time is */ /* 653 / 0.14 MHz = 4.66 ms */ #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ /* Unit: us */ #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros * @{ */ /* Macro for internal HAL driver usage, and possibly can be used into code of */ /* final user. */ /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. * @{ */ /** @brief Reset ADC handle state. * @param __HANDLE__ ADC handle * @retval None */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ do{ \ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @brief Enable ADC interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be one of the following values: * @arg @ref ADC_IT_RDY ADC Ready interrupt source * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable ADC interrupt. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC Interrupt * This parameter can be one of the following values: * @arg @ref ADC_IT_RDY ADC Ready interrupt source * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) /** @brief Checks if the specified ADC interrupt source is enabled or disabled. * @param __HANDLE__ ADC handle * @param __INTERRUPT__ ADC interrupt source to check * This parameter can be one of the following values: * @arg @ref ADC_IT_RDY ADC Ready interrupt source * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source * @arg @ref ADC_IT_OVR ADC overrun interrupt source * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Check whether the specified ADC flag is set or not. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: * @arg @ref ADC_FLAG_RDY ADC Ready flag * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_OVR ADC overrun flag * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) /** * @brief Clear the specified ADC flag. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: * @arg @ref ADC_FLAG_RDY ADC Ready flag * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_OVR ADC overrun flag * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ (((__HANDLE__)->Instance->ISR) = (__FLAG__)) /** * @} */ /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro * @{ */ /** * @brief Helper macro to get ADC channel number in decimal format * from literals ADC_CHANNEL_x. * @note Example: * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) * will return decimal number "4". * @note The input can be a value from functions where a channel * number is returned, either defined with number * or with bitfield (only one bit must be set). * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 */ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) /** * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x * from number in decimal format. * @note Example: * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "ADC_CHANNEL_4". * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) /** * @brief Helper macro to determine whether the selected channel * corresponds to literal definitions of driver. * @note The different literal definitions of ADC channels are: * - ADC internal channel: * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... * - ADC external channel (channel connected to a GPIO pin): * ADC_CHANNEL_1, ADC_CHANNEL_2, ... * @note The channel parameter must be a value defined from literal * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, * ADC_CHANNEL_TEMPSENSOR, ...), * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), * must not be a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) /** * @brief Helper macro to convert a channel defined from parameter * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, * ADC_CHANNEL_TEMPSENSOR, ...), * to its equivalent parameter definition of a ADC external channel * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). * @note The channel parameter can be, additionally to a value * defined from parameter definition of a ADC internal channel * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), * a value defined from parameter definition of * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) * or a value from functions where a channel number is returned * from ADC registers. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 (8) * @arg @ref ADC_CHANNEL_2 (8) * @arg @ref ADC_CHANNEL_3 (8) * @arg @ref ADC_CHANNEL_4 (8) * @arg @ref ADC_CHANNEL_5 (8) * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref ADC_CHANNEL_0 * @arg @ref ADC_CHANNEL_1 * @arg @ref ADC_CHANNEL_2 * @arg @ref ADC_CHANNEL_3 * @arg @ref ADC_CHANNEL_4 * @arg @ref ADC_CHANNEL_5 * @arg @ref ADC_CHANNEL_6 * @arg @ref ADC_CHANNEL_7 * @arg @ref ADC_CHANNEL_8 * @arg @ref ADC_CHANNEL_9 * @arg @ref ADC_CHANNEL_10 * @arg @ref ADC_CHANNEL_11 * @arg @ref ADC_CHANNEL_12 * @arg @ref ADC_CHANNEL_13 * @arg @ref ADC_CHANNEL_14 * @arg @ref ADC_CHANNEL_15 * @arg @ref ADC_CHANNEL_16 * @arg @ref ADC_CHANNEL_17 * @arg @ref ADC_CHANNEL_18 */ #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) /** * @brief Helper macro to determine whether the internal channel * selected is available on the ADC instance selected. * @note The channel parameter must be a value defined from parameter * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, * ADC_CHANNEL_TEMPSENSOR, ...), * must not be a value defined from parameter definition of * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) * or a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __ADC_INSTANCE__ ADC instance * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref ADC_CHANNEL_VREFINT (7) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref ADC_CHANNEL_VBAT (6) * @arg @ref ADC_CHANNEL_VOPAMP1 (1) * @arg @ref ADC_CHANNEL_VOPAMP2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref ADC_CHANNEL_VOPAMP4 (5) * @arg @ref ADC_CHANNEL_VOPAMP5 (5) * @arg @ref ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Helper macro to get the ADC multimode conversion data of ADC master * or ADC slave from raw value with both ADC conversion data concatenated. * @note This macro is intended to be used when multimode transfer by DMA * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). * In this case the transferred data need to processed with this macro * to separate the conversion data of ADC master and ADC slave. * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_MASTER * @arg @ref LL_ADC_MULTI_SLAVE * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance * to which is belonging the selected ADC instance. * @note ADC common register instance can be used for: * - Set parameters common to several ADC instances * - Multimode (for devices with several ADC instances) * Refer to functions having argument "ADCxy_COMMON" as parameter. * @param __ADCx__ ADC instance * @retval ADC common register instance */ #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ __LL_ADC_COMMON_INSTANCE((__ADCx__)) /** * @brief Helper macro to check if all ADC instances sharing the same * ADC common instance are disabled. * @note This check is required by functions with setting conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * Refer to functions having argument "ADCxy_COMMON" as parameter. * @note On devices with only 1 ADC common instance, parameter of this macro * is useless and can be ignored (parameter kept for compatibility * with devices featuring several ADC common instances). * @param __ADCXY_COMMON__ ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Value "0" if all ADC instances sharing the same ADC common instance * are disabled. * Value "1" if at least one ADC instance sharing the same ADC common instance * is enabled. */ #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) /** * @brief Helper macro to define the ADC conversion data full-scale digital * value corresponding to the selected ADC resolution. * @note ADC conversion data full-scale corresponds to voltage range * determined by analog voltage references Vref+ and Vref- * (refer to reference manual). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval ADC conversion data full-scale digital value */ #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval ADC conversion data to the requested resolution */ #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ (__ADC_RESOLUTION_CURRENT__),\ (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ (__ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage * reference VrefInt. * @note Computation is using VrefInt calibration value * stored in system memory for each device during production. * @note This voltage depends on user board environment: voltage level * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval Analog reference voltage (unit: mV) */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor calibration values * stored in system memory for each device during production. * @note Calculation formula: * Temperature = ((TS_ADC_DATA - TS_CAL1) * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * Avg_Slope = (TS_CAL2 - TS_CAL1) * / (TS_CAL2_TEMP - TS_CAL1_TEMP) * TS_CAL1 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL1 (calibrated in factory) * TS_CAL2 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL2 (calibrated in factory) * Caution: Calculation relevancy under reserve that calibration * parameters are correct (address and data). * To calculate temperature using temperature sensor * datasheet typical values (generic values less, therefore * less accurate than calibrated values), * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal * temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature * sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) */ #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ (__TEMPSENSOR_ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor typical values * (refer to device datasheet). * @note Calculation formula: * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) * / Avg_Slope + CALx_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * (unit: digital value) * Avg_Slope = temperature sensor slope * (unit: uV/Degree Celsius) * TS_TYP_CALx_VOLT = temperature sensor digital value at * temperature CALx_TEMP (unit: mV) * Caution: Calculation relevancy under reserve the temperature sensor * of the current device has characteristics in line with * datasheet typical values. * If temperature sensor calibration values are available on * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), * temperature calculation will be more accurate using * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). * On STM32G4, refer to device datasheet parameter "Avg_Slope". * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_10B * @arg @ref ADC_RESOLUTION_8B * @arg @ref ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) */ #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ __TEMPSENSOR_TYP_CALX_V__,\ __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ (__TEMPSENSOR_TYP_CALX_V__),\ (__TEMPSENSOR_CALX_TEMP__),\ (__VREFANALOG_VOLTAGE__),\ (__TEMPSENSOR_ADC_DATA__),\ (__ADC_RESOLUTION__)) /** * @} */ /** * @} */ /* Include ADC HAL Extended module */ #include "stm32g4xx_hal_adc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_Exported_Functions * @{ */ /** @addtogroup ADC_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @{ */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup ADC_Exported_Functions_Group2 * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); /* Non-blocking mode: DMA */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); /* ADC sampling control */ HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} */ /* Peripheral State functions *************************************************/ /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /* Private functions -----------------------------------------------------------*/ /** @addtogroup ADC_Private_Functions ADC Private Functions * @{ */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_ADC_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc_ex.h * @author MCD Application Team * @brief Header file of ADC HAL extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_ADC_EX_H #define STM32G4xx_HAL_ADC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup ADCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types * @{ */ /** * @brief ADC Injected Conversion Oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ } ADC_InjOversamplingTypeDef; /** * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. * ADC state can be either: * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going * on ADC groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. This parameter can be a value of @ref ADC_HAL_EC_CHANNEL Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. Unit: ADC clock cycles. Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values. */ uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). Only channel 'i' has to be configured, channel 'i+1' is configured automatically. This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. Caution: This parameter applies to a channel that can be used in a regular and/or injected group. It overwrites the last setting. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. This parameter value can be ENABLE or DISABLE. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_injected_external_trigger_source. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADC_injected_external_trigger_edge. If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ } ADC_InjectionConfTypeDef; #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). * Both Master and Slave ADCs must be disabled. */ typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ } ADC_MultiModeTypeDef; #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants * @{ */ /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source * @{ */ /* ADC group regular trigger sources for all ADC instances */ #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** * @} */ /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ /** * @} */ /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number * @{ */ #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ /** * @} */ /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign * @{ */ #define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ #define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ /** * @} */ /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ /** * @} */ #if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode * @{ */ #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution * @{ */ #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ /** * @} */ /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ /** * @} */ /** * @} */ #endif /* ADC_MULTIMODE_SUPPORT */ /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups * @{ */ #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ /** * @} */ /** @defgroup ADC_CFGR_fields ADCx CFGR fields * @{ */ #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) /** * @} */ /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields * @{ */ #if defined(ADC_SMPR1_SMPPLUS) #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) #else #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ ADC_SMPR1_SMP0) #endif /* ADC_SMPR1_SMPPLUS */ /** * @} */ /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields * @{ */ /* ADC_CFGR fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */ #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ #if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros * @{ */ /** @brief Force ADC instance in multimode mode independent (multimode disable). * @note This macro must be used only in case of transition from multimode * to mode independent and in case of unknown previous state, * to ensure ADC configuration is in mode independent. * @note Standard way of multimode configuration change is done from * HAL ADC handle of ADC master using function * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". * Usage of this macro is not the Standard way of multimode * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases * mentioned above. * @param __HANDLE__ ADC handle. * @retval None */ #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) /** * @} */ #endif /* ADC_MULTIMODE_SUPPORT */ /* Private macros ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros * @{ */ /* Macro reserved for internal HAL driver usage, not intended to be used in */ /* code of final user. */ /** * @brief Test if conversion trigger of injected group is software start * or external trigger. * @param __HANDLE__ ADC handle. * @retval SET (software start) or RESET (external trigger). */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) /** * @brief Check whether or not ADC is independent. * @param __HANDLE__ ADC handle. * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC5) \ )? \ SET \ : \ RESET \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC3) \ )? \ SET \ : \ RESET \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Set the selected injected Channel rank. * @param __CHANNELNB__ Channel number. * @param __RANKNB__ Rank number. * @retval None */ #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. * @retval None */ #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) /** * @brief Configure ADC discontinuous conversion mode for injected group * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. * @retval None */ #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) /** * @brief Configure ADC discontinuous conversion mode for regular group * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. * @retval None */ #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) /** * @brief Configure the number of discontinuous conversions for regular group. * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. * @retval None */ #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) /** * @brief Configure the ADC auto delay mode. * @param __AUTOWAIT__ Auto delay bit enable or disable. * @retval None */ #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) /** * @brief Configure ADC continuous conversion mode. * @param __CONTINUOUS_MODE__ Continuous mode. * @retval None */ #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) /** * @brief Configure the ADC DMA continuous request. * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None */ #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Configure the ADC DMA continuous request for ADC multimode. * @param __DMACONTREQ_MODE__ DMA continuous request mode. * @retval None */ #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Shift the offset with respect to the selected ADC resolution. * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). * @param __HANDLE__ ADC handle * @param __OFFSET__ Value to be shifted * @retval None */ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. * If resolution 12 bits, no shift. * If resolution 10 bits, shift of 2 ranks on the left. * If resolution 8 bits, shift of 4 ranks on the left. * If resolution 6 bits, shift of 6 ranks on the left. * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). * @param __HANDLE__ ADC handle * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) /** * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. * @note Thresholds have to be left-aligned on bit 7. * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). * If resolution 8 bits, no shift. * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). * @param __HANDLE__ ADC handle * @param __THRESHOLD__ Value to be shifted * @retval None */ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ ((__THRESHOLD__) << 2UL) \ ) /** * @brief Clear Common Control Register. * @param __HANDLE__ ADC handle. * @retval None */ #if defined(ADC_MULTIMODE_SUPPORT) #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ ADC_CCR_CKMODE | \ ADC_CCR_PRESC | \ ADC_CCR_VBATSEL | \ ADC_CCR_VSENSESEL | \ ADC_CCR_VREFEN | \ ADC_CCR_MDMA | \ ADC_CCR_DMACFG | \ ADC_CCR_DELAY | \ ADC_CCR_DUAL) #endif /* ADC_MULTIMODE_SUPPORT */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. * @param __HANDLE_SLAVE__ ADC slave handle. * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ ((__HANDLE_SLAVE__)->Instance = ADC2) \ : \ ((__HANDLE_MASTER__)->Instance == ADC3) ? \ ((__HANDLE_SLAVE__)->Instance = ADC4) \ : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. * @param __HANDLE_SLAVE__ ADC slave handle. * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. * @retval None */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( ((__HANDLE_MASTER__)->Instance == ADC1) ? \ ((__HANDLE_SLAVE__)->Instance = ADC2) \ : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) #endif /** * @brief Verify the ADC instance connected to the temperature sensor. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC instance connected to the battery voltage VBAT. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /** * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. * @param __HANDLE__ ADC handle. * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) */ #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) /** * @brief Verify the length of scheduled injected conversions group. * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) /** * @brief Calibration factor size verification (7 bits maximum). * @param __CALIBRATION_FACTOR__ Calibration factor value. * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) */ #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) /** * @brief Verify the ADC channel setting. * @param __HANDLE__ ADC handle. * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC4) && \ (((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC5) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #elif defined(STM32G471xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC channel setting in differential mode. * @param __HANDLE__ ADC handle. * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_14)) || \ ((((__HANDLE__)->Instance) == ADC1) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5))) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) || \ ((((__HANDLE__)->Instance) == ADC4) && \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) || \ ((((__HANDLE__)->Instance) == ADC5) && \ (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) #elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_14)) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ ((__CHANNEL__) == ADC_CHANNEL_4) || \ ((__CHANNEL__) == ADC_CHANNEL_5) || \ ((__CHANNEL__) == ADC_CHANNEL_6) || \ ((__CHANNEL__) == ADC_CHANNEL_7) || \ ((__CHANNEL__) == ADC_CHANNEL_8) || \ ((__CHANNEL__) == ADC_CHANNEL_9) || \ ((__CHANNEL__) == ADC_CHANNEL_10) || \ ((__CHANNEL__) == ADC_CHANNEL_11) || \ ((__CHANNEL__) == ADC_CHANNEL_14)) || \ ((((__HANDLE__)->Instance) == ADC2) && \ (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13))) ) #endif /** * @brief Verify the ADC single-ended input or differential mode setting. * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) */ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) /** * @brief Verify the ADC offset management setting. * @param __OFFSET_NUMBER__ ADC offset management. * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) */ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) /** * @brief Verify the ADC offset sign setting. * @param __OFFSET_SIGN__ ADC offset sign. * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) */ #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \ ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) ) /** * @brief Verify the ADC injected channel setting. * @param __CHANNEL__ programmed ADC injected channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) /** * @brief Verify the ADC injected conversions external trigger. * @param __HANDLE__ ADC handle. * @param __INJTRIG__ programmed ADC injected conversions external trigger. * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G471xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ (((__HANDLE__)->Instance == ADC3) && \ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #endif /** * @brief Verify the ADC edge trigger setting for injected group. * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) */ #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Verify the ADC multimode setting. * @param __MODE__ programmed ADC multimode setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ ((__MODE__) == ADC_DUALMODE_INTERL) || \ ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) /** * @brief Verify the ADC multimode DMA access setting. * @param __MODE__ programmed ADC multimode DMA access setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) /** * @brief Verify the ADC multimode delay setting. * @param __DELAY__ programmed ADC multimode delay setting. * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) */ #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Verify the ADC analog watchdog setting. * @param __WATCHDOG__ programmed ADC analog watchdog setting. * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) /** * @brief Verify the ADC analog watchdog mode setting. * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) /** * @brief Verify the ADC analog watchdog filtering setting. * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) */ #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \ ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) ) /** * @brief Verify the ADC conversion (regular or injected or both). * @param __CONVERSION__ ADC conversion group. * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) */ #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) /** * @brief Verify the ADC event type. * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ ((__EVENT__) == ADC_AWD_EVENT) || \ ((__EVENT__) == ADC_AWD2_EVENT) || \ ((__EVENT__) == ADC_AWD3_EVENT) || \ ((__EVENT__) == ADC_OVR_EVENT) || \ ((__EVENT__) == ADC_JQOVF_EVENT) ) /** * @brief Verify the ADC oversampling ratio. * @param __RATIO__ programmed ADC oversampling ratio. * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) */ #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) /** * @brief Verify the ADC oversampling shift. * @param __SHIFT__ programmed ADC oversampling shift. * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) */ #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) /** * @brief Verify the ADC oversampling triggered mode. * @param __MODE__ programmed ADC oversampling triggered mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) /** * @brief Verify the ADC oversampling regular conversion resumed or continued mode. * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) /** * @brief Verify the DFSDM mode configuration. * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) */ #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) /** * @brief Return the DFSDM configuration mode. * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * For this reason, the input parameter is the ADC handle and not the configuration parameter * directly. * @retval DFSDM configuration mode */ #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions * @{ */ /** @addtogroup ADCEx_Exported_Functions_Group1 * @{ */ /* IO operation functions *****************************************************/ /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); /* ADC group regular conversions stop */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @addtogroup ADCEx_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* ADC_MULTIMODE_SUPPORT */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_ADC_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_cortex.h * @author MCD Application Team * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_CORTEX_H #define __STM32G4xx_HAL_CORTEX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup CORTEX CORTEX * @brief CORTEX HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types CORTEX Exported Types * @{ */ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @brief MPU Region initialization structure * @{ */ typedef struct { uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority, 4 bits for subpriority */ #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority, 3 bits for subpriority */ #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority, 2 bits for subpriority */ #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority, 1 bit for subpriority */ #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority, 0 bit for subpriority */ /** * @} */ /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U #define SYSTICK_CLKSOURCE_HCLK 0x00000004U /** * @} */ #if (__MPU_PRESENT == 1) /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /** * @} */ /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ #define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_DISABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) /** * @} */ /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable * @{ */ #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable * @{ */ #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) /** * @} */ /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels * @{ */ #define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL2 ((uint8_t)0x02) #define MPU_TEX_LEVEL4 ((uint8_t)0x04) /** * @} */ /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) /** * @} */ /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} */ /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ #define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) /** * @} */ #endif /* __MPU_PRESENT */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions * @{ */ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @{ */ /* Initialization and Configuration functions *****************************/ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); /** * @} */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions * @brief Cortex control functions * @{ */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ ((GROUP) == NVIC_PRIORITYGROUP_1) || \ ((GROUP) == NVIC_PRIORITYGROUP_2) || \ ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) #if (__MPU_PRESENT == 1) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ ((TYPE) == MPU_TEX_LEVEL1) || \ ((TYPE) == MPU_TEX_LEVEL2) || \ ((TYPE) == MPU_TEX_LEVEL4)) #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ ((TYPE) == MPU_REGION_FULL_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RO) || \ ((TYPE) == MPU_REGION_PRIV_RO_URO)) #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ ((NUMBER) == MPU_REGION_NUMBER1) || \ ((NUMBER) == MPU_REGION_NUMBER2) || \ ((NUMBER) == MPU_REGION_NUMBER3) || \ ((NUMBER) == MPU_REGION_NUMBER4) || \ ((NUMBER) == MPU_REGION_NUMBER5) || \ ((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER7)) #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ ((SIZE) == MPU_REGION_SIZE_64B) || \ ((SIZE) == MPU_REGION_SIZE_128B) || \ ((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \ ((SIZE) == MPU_REGION_SIZE_1KB) || \ ((SIZE) == MPU_REGION_SIZE_2KB) || \ ((SIZE) == MPU_REGION_SIZE_4KB) || \ ((SIZE) == MPU_REGION_SIZE_8KB) || \ ((SIZE) == MPU_REGION_SIZE_16KB) || \ ((SIZE) == MPU_REGION_SIZE_32KB) || \ ((SIZE) == MPU_REGION_SIZE_64KB) || \ ((SIZE) == MPU_REGION_SIZE_128KB) || \ ((SIZE) == MPU_REGION_SIZE_256KB) || \ ((SIZE) == MPU_REGION_SIZE_512KB) || \ ((SIZE) == MPU_REGION_SIZE_1MB) || \ ((SIZE) == MPU_REGION_SIZE_2MB) || \ ((SIZE) == MPU_REGION_SIZE_4MB) || \ ((SIZE) == MPU_REGION_SIZE_8MB) || \ ((SIZE) == MPU_REGION_SIZE_16MB) || \ ((SIZE) == MPU_REGION_SIZE_32MB) || \ ((SIZE) == MPU_REGION_SIZE_64MB) || \ ((SIZE) == MPU_REGION_SIZE_128MB) || \ ((SIZE) == MPU_REGION_SIZE_256MB) || \ ((SIZE) == MPU_REGION_SIZE_512MB) || \ ((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #endif /* __MPU_PRESENT */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_HAL_CORTEX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac.h * @author MCD Application Team * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_DAC_H #define STM32G4xx_HAL_DAC_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @addtogroup DAC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Types DAC Exported Types * @{ */ /** * @brief HAL State structures definition */ typedef enum { HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ } HAL_DAC_StateTypeDef; /** * @brief DAC handle Structure definition */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) typedef struct __DAC_HandleTypeDef #else typedef struct #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ { DAC_TypeDef *Instance; /*!< Register base address */ __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ HAL_LockTypeDef Lock; /*!< DAC locking object */ DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; /** * @brief DAC Configuration sample and hold Channel structure definition */ typedef struct { uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ } DAC_SampleAndHoldConfTypeDef; /** * @brief DAC Configuration regular Channel structure definition */ typedef struct { uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode This parameter can be a value of @ref DAC_HighFrequency */ FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel. This parameter can be ENABLE or DISABLE */ FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel. This parameter can be ENABLE or DISABLE */ uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. This parameter can be a value of @ref DAC_SampleAndHold */ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection. Note: In case of sawtooth wave generation, this trigger corresponds to the reset trigger. */ uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection. Note: In case of sawtooth wave generation, this trigger corresponds to the step trigger.*/ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode This parameter must be a value of @ref DAC_UserTrimming DAC_UserTrimming is either factory or user trimming */ uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ } DAC_ChannelConfTypeDef; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief HAL DAC Callback ID enumeration definition */ typedef enum { HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ } HAL_DAC_CallbackIDTypeDef; /** * @brief HAL DAC Callback pointer definition */ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DAC_Exported_Constants DAC Exported Constants * @{ */ /** @defgroup DAC_Error_Code DAC Error Code * @{ */ #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup DAC_trigger_selection DAC trigger selection * @{ */ #define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */ #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */ #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */ #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */ #define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */ #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ #define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */ #define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ /** * @} */ /** @defgroup DAC_output_buffer DAC output buffer * @{ */ #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) /** * @} */ /** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ #define DAC_CHANNEL_1 0x00000000U #define DAC_CHANNEL_2 0x00000010U /** * @} */ /** @defgroup DAC_data_alignment DAC data alignment * @{ */ #define DAC_ALIGN_12B_R 0x00000000U #define DAC_ALIGN_12B_L 0x00000004U #define DAC_ALIGN_8B_R 0x00000008U /** * @} */ /** @defgroup DAC_flags_definition DAC flags definition * @{ */ #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) #define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) #define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /** * @} */ /** @defgroup DAC_IT_definition DAC IT definition * @{ */ #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) /** * @} */ /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ #define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) #define DAC_CHIPCONNECT_INTERNAL (1UL << 1) #define DAC_CHIPCONNECT_BOTH (1UL << 2) /** * @} */ /** @defgroup DAC_UserTrimming DAC User Trimming * @{ */ #define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */ #define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */ /** * @} */ /** @defgroup DAC_SampleAndHold DAC power mode * @{ */ #define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL) #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) /** * @} */ /** @defgroup DAC_HighFrequency DAC high frequency interface mode * @{ */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Macros DAC Exported Macros * @{ */ /** @brief Reset DAC handle state. * @param __HANDLE__ specifies the DAC handle. * @retval None */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** @brief Enable the DAC channel. * @param __HANDLE__ specifies the DAC handle. * @param __DAC_Channel__ specifies the DAC channel * @retval None */ #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Disable the DAC channel. * @param __HANDLE__ specifies the DAC handle * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) /** @brief Set DHR12R1 alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) /** @brief Set DHR12R2 alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) /** @brief Set DHR12RD alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) /** @brief Enable the DAC interrupt. * @param __HANDLE__ specifies the DAC handle * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) /** @brief Disable the DAC interrupt. * @param __HANDLE__ specifies the DAC handle * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified DAC interrupt source is enabled or not. * @param __HANDLE__ DAC handle * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of interruption (SET or RESET) */ #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. * @param __HANDLE__ specifies the DAC handle. * @param __FLAG__ specifies the DAC flag to get. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) * @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag * @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. * @param __HANDLE__ specifies the DAC handle. * @param __FLAG__ specifies the DAC flag to clear. * This parameter can be any combination of the following values: * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup DAC_Private_Macros DAC Private Macros * @{ */ #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((DACX) == DAC2) ? \ ((CHANNEL) == DAC_CHANNEL_1) \ : \ (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2))) #else #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) #endif #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL) /** * @} */ /* Include DAC HAL Extended module */ #include "stm32g4xx_hal_dac_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DAC_Exported_Functions * @{ */ /** @addtogroup DAC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); /** * @} */ /** @addtogroup DAC_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* DAC callback registering/unregistering */ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup DAC_Exported_Functions_Group3 * @{ */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ /** @addtogroup DAC_Exported_Functions_Group4 * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); /** * @} */ /** * @} */ /** @defgroup DAC_Private_Functions DAC Private Functions * @{ */ void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_DAC_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac_ex.h * @author MCD Application Team * @brief Header file of DAC HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_DAC_EX_H #define STM32G4xx_HAL_DAC_EX_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @addtogroup DACEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief HAL State structures definition */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ */ /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude * @{ */ #define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ #define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */ #define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ #define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ #define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ #define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ #define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ #define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ #define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ #define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ #define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ #define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ #define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ /** * @} */ /** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode * @{ */ #define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */ #define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup DACEx_Private_Macros DACEx Private Macros * @{ */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_DAC_TRIGGER(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG1) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG2) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG3) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG4) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG5) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG6) || \ (((DACX) == DAC1) && \ (((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \ ) || \ (((DACX) == DAC2) && \ (((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG02)) \ ) || \ (((DACX) == DAC3) && \ (((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG03)) \ ) || \ (((DACX) == DAC4) && \ (((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \ ) \ ) #else #define IS_DAC_TRIGGER(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ (((DACX) == DAC3) ? \ ((TRIGGER) == DAC_TRIGGER_T1_TRGO) \ : ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) #endif #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_DAC_TRIGGER2(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG1) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG2) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG3) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG4) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG5) || \ ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG6) || \ (((DACX) == DAC1) && \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) || \ (((DACX) == DAC2) && \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) || \ (((DACX) == DAC3) && \ ((TRIGGER) == DAC_TRIGGER_T1_TRGO) \ ) || \ (((DACX) == DAC4) && \ ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) #else #define IS_DAC_TRIGGER2(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ (((DACX) == DAC3) ? \ ((TRIGGER) == DAC_TRIGGER_T1_TRGO) \ :((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) #endif #define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC)) #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU) #define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU) #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \ ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \ ((CONNECT) == DAC_CHIPCONNECT_BOTH)) #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \ ((TRIMMING) == DAC_TRIMMING_USER)) #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) #define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \ ((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT)) #define IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL) #define IS_DAC_STEP_DATA(DATA) ((DATA) <= 0x0000FFFFUL) /** * @} */ /* Exported functions --------------------------------------------------------*/ /* Extended features functions ***********************************************/ /** @addtogroup DACEx_Exported_Functions * @{ */ /** @addtogroup DACEx_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData); HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); /** * @} */ /** @addtogroup DACEx_Exported_Functions_Group3 * @{ */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); /** * @} */ /** * @} */ /** @addtogroup DACEx_Private_Functions * @{ */ /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */ /* are called by HAL_DAC_Start_DMA */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_DAC_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_def.h * @author MCD Application Team * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_DEF #define __STM32G4xx_HAL_DEF #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx.h" #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ #include /* Exported types ------------------------------------------------------------*/ /** * @brief HAL Status structures definition */ typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, HAL_BUSY = 0x02U, HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** * @brief HAL Lock structures definition */ typedef enum { HAL_UNLOCKED = 0x00U, HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macros -----------------------------------------------------------*/ #define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ do{ \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \ } while(0) #define UNUSED(X) (void)X /** @brief Reset the Handle's State field. * @param __HANDLE__: specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * In this later function, when the Handle's "State" field is set to 0, it will execute the function * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) #if (USE_RTOS == 1U) /* Reserved for future use */ #error " USE_RTOS should be 0 in the current HAL release " #else #define __HAL_LOCK(__HANDLE__) \ do{ \ if((__HANDLE__)->Lock == HAL_LOCKED) \ { \ return HAL_BUSY; \ } \ else \ { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ }while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do{ \ (__HANDLE__)->Lock = HAL_UNLOCKED; \ }while (0U) #endif /* USE_RTOS */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #ifndef __weak #define __weak __attribute__((weak)) #endif #ifndef __packed #define __packed __attribute__((packed)) #endif #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ #ifndef __packed #define __packed __attribute__((__packed__)) #endif /* __packed */ #endif /* __GNUC__ */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4U))) #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4U) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ /** * @brief __RAM_FUNC definition */ #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler V4/V5 and V6 -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' dialog. */ #define __RAM_FUNC #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc #elif defined ( __GNUC__ ) /* GNU Compiler ------------ RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC __attribute__((section(".RamFunc"))) #endif /* __CC_ARM */ /** * @brief __NOINLINE definition */ #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM V4/V5 and V6 & GNU Compiler ------------------------------- */ #define __NOINLINE __attribute__ ( (noinline) ) #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- */ #define __NOINLINE _Pragma("optimize = no_inline") #endif /* __CC_ARM || __GNUC__ */ #ifdef __cplusplus } #endif #endif /* ___STM32G4xx_HAL_DEF */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma.h * @author MCD Application Team * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_DMA_H #define __STM32G4xx_HAL_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ /** * @brief DMA Configuration Structure definition */ typedef struct { uint32_t Request; /*!< Specifies the request selected for the specified channel. This parameter can be a value of @ref DMA_request */ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; /** * @brief HAL DMA State structures definition */ typedef enum { HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ } HAL_DMA_StateTypeDef; /** * @brief HAL DMA Error Code structure definition */ typedef enum { HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ } HAL_DMA_LevelCompleteTypeDef; /** * @brief HAL DMA Callback ID structure definition */ typedef enum { HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ } HAL_DMA_CallbackIDTypeDef; /** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_InitTypeDef Init; /*!< DMA communication parameters */ HAL_LockTypeDef Lock; /*!< DMA locking object */ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ void *Parent; /*!< Parent object state */ void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ uint32_t ChannelIndex; /*!< DMA Channel Index */ DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ } DMA_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ /** @defgroup DMA_Error_Code DMA Error Code * @{ */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ /** * @} */ /** @defgroup DMA_request DMA request * @{ */ #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ #define DMA_REQUEST_GENERATOR0 1U #define DMA_REQUEST_GENERATOR1 2U #define DMA_REQUEST_GENERATOR2 3U #define DMA_REQUEST_GENERATOR3 4U #define DMA_REQUEST_ADC1 5U #define DMA_REQUEST_DAC1_CHANNEL1 6U #define DMA_REQUEST_DAC1_CHANNEL2 7U #define DMA_REQUEST_TIM6_UP 8U #define DMA_REQUEST_TIM7_UP 9U #define DMA_REQUEST_SPI1_RX 10U #define DMA_REQUEST_SPI1_TX 11U #define DMA_REQUEST_SPI2_RX 12U #define DMA_REQUEST_SPI2_TX 13U #define DMA_REQUEST_SPI3_RX 14U #define DMA_REQUEST_SPI3_TX 15U #define DMA_REQUEST_I2C1_RX 16U #define DMA_REQUEST_I2C1_TX 17U #define DMA_REQUEST_I2C2_RX 18U #define DMA_REQUEST_I2C2_TX 19U #define DMA_REQUEST_I2C3_RX 20U #define DMA_REQUEST_I2C3_TX 21U #if defined (I2C4) #define DMA_REQUEST_I2C4_RX 22U #define DMA_REQUEST_I2C4_TX 23U #endif /* I2C4 */ #define DMA_REQUEST_USART1_RX 24U #define DMA_REQUEST_USART1_TX 25U #define DMA_REQUEST_USART2_RX 26U #define DMA_REQUEST_USART2_TX 27U #define DMA_REQUEST_USART3_RX 28U #define DMA_REQUEST_USART3_TX 29U #define DMA_REQUEST_UART4_RX 30U #define DMA_REQUEST_UART4_TX 31U #if defined (UART5) #define DMA_REQUEST_UART5_RX 32U #define DMA_REQUEST_UART5_TX 33U #endif /* UART5 */ #define DMA_REQUEST_LPUART1_RX 34U #define DMA_REQUEST_LPUART1_TX 35U #define DMA_REQUEST_ADC2 36U #if defined (ADC3) #define DMA_REQUEST_ADC3 37U #endif /* ADC3 */ #if defined (ADC4) #define DMA_REQUEST_ADC4 38U #endif /* ADC4 */ #if defined (ADC5) #define DMA_REQUEST_ADC5 39U #endif /* ADC5 */ #if defined (QUADSPI) #define DMA_REQUEST_QUADSPI 40U #endif /* QUADSPI */ #if defined (DAC2) #define DMA_REQUEST_DAC2_CHANNEL1 41U #endif /* DAC2 */ #define DMA_REQUEST_TIM1_CH1 42U #define DMA_REQUEST_TIM1_CH2 43U #define DMA_REQUEST_TIM1_CH3 44U #define DMA_REQUEST_TIM1_CH4 45U #define DMA_REQUEST_TIM1_UP 46U #define DMA_REQUEST_TIM1_TRIG 47U #define DMA_REQUEST_TIM1_COM 48U #define DMA_REQUEST_TIM8_CH1 49U #define DMA_REQUEST_TIM8_CH2 50U #define DMA_REQUEST_TIM8_CH3 51U #define DMA_REQUEST_TIM8_CH4 52U #define DMA_REQUEST_TIM8_UP 53U #define DMA_REQUEST_TIM8_TRIG 54U #define DMA_REQUEST_TIM8_COM 55U #define DMA_REQUEST_TIM2_CH1 56U #define DMA_REQUEST_TIM2_CH2 57U #define DMA_REQUEST_TIM2_CH3 58U #define DMA_REQUEST_TIM2_CH4 59U #define DMA_REQUEST_TIM2_UP 60U #define DMA_REQUEST_TIM3_CH1 61U #define DMA_REQUEST_TIM3_CH2 62U #define DMA_REQUEST_TIM3_CH3 63U #define DMA_REQUEST_TIM3_CH4 64U #define DMA_REQUEST_TIM3_UP 65U #define DMA_REQUEST_TIM3_TRIG 66U #define DMA_REQUEST_TIM4_CH1 67U #define DMA_REQUEST_TIM4_CH2 68U #define DMA_REQUEST_TIM4_CH3 69U #define DMA_REQUEST_TIM4_CH4 70U #define DMA_REQUEST_TIM4_UP 71U #if defined (TIM5) #define DMA_REQUEST_TIM5_CH1 72U #define DMA_REQUEST_TIM5_CH2 73U #define DMA_REQUEST_TIM5_CH3 74U #define DMA_REQUEST_TIM5_CH4 75U #define DMA_REQUEST_TIM5_UP 76U #define DMA_REQUEST_TIM5_TRIG 77U #endif /* TIM5 */ #define DMA_REQUEST_TIM15_CH1 78U #define DMA_REQUEST_TIM15_UP 79U #define DMA_REQUEST_TIM15_TRIG 80U #define DMA_REQUEST_TIM15_COM 81U #define DMA_REQUEST_TIM16_CH1 82U #define DMA_REQUEST_TIM16_UP 83U #define DMA_REQUEST_TIM17_CH1 84U #define DMA_REQUEST_TIM17_UP 85U #if defined (TIM20) #define DMA_REQUEST_TIM20_CH1 86U #define DMA_REQUEST_TIM20_CH2 87U #define DMA_REQUEST_TIM20_CH3 88U #define DMA_REQUEST_TIM20_CH4 89U #define DMA_REQUEST_TIM20_UP 90U #endif /* TIM20 */ #define DMA_REQUEST_AES_IN 91U #define DMA_REQUEST_AES_OUT 92U #if defined (TIM20) #define DMA_REQUEST_TIM20_TRIG 93U #define DMA_REQUEST_TIM20_COM 94U #endif /* TIM20 */ #if defined (HRTIM1) #define DMA_REQUEST_HRTIM1_M 95U #define DMA_REQUEST_HRTIM1_A 96U #define DMA_REQUEST_HRTIM1_B 97U #define DMA_REQUEST_HRTIM1_C 98U #define DMA_REQUEST_HRTIM1_D 99U #define DMA_REQUEST_HRTIM1_E 100U #define DMA_REQUEST_HRTIM1_F 101U #endif /* HRTIM1 */ #define DMA_REQUEST_DAC3_CHANNEL1 102U #define DMA_REQUEST_DAC3_CHANNEL2 103U #if defined (DAC4) #define DMA_REQUEST_DAC4_CHANNEL1 104U #define DMA_REQUEST_DAC4_CHANNEL2 105U #endif /* DAC4 */ #if defined (SPI4) #define DMA_REQUEST_SPI4_RX 106U #define DMA_REQUEST_SPI4_TX 107U #endif /* SPI4 */ #define DMA_REQUEST_SAI1_A 108U #define DMA_REQUEST_SAI1_B 109U #define DMA_REQUEST_FMAC_READ 110U #define DMA_REQUEST_FMAC_WRITE 111U #define DMA_REQUEST_CORDIC_READ 112U #define DMA_REQUEST_CORDIC_WRITE 113U #define DMA_REQUEST_UCPD1_RX 114U #define DMA_REQUEST_UCPD1_TX 115U /** * @} */ /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ /** * @} */ /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ */ #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ */ #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ */ #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ /** * @} */ /** @defgroup DMA_Memory_data_size DMA Memory data size * @{ */ #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ /** * @} */ /** @defgroup DMA_mode DMA mode * @{ */ #define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ /** * @} */ /** @defgroup DMA_Priority_level DMA Priority level * @{ */ #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ /** * @} */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions * @{ */ #define DMA_IT_TC DMA_CCR_TCIE #define DMA_IT_HT DMA_CCR_HTIE #define DMA_IT_TE DMA_CCR_TEIE /** * @} */ /** @defgroup DMA_flag_definitions DMA flag definitions * @{ */ #define DMA_FLAG_GL1 0x00000001U #define DMA_FLAG_TC1 0x00000002U #define DMA_FLAG_HT1 0x00000004U #define DMA_FLAG_TE1 0x00000008U #define DMA_FLAG_GL2 0x00000010U #define DMA_FLAG_TC2 0x00000020U #define DMA_FLAG_HT2 0x00000040U #define DMA_FLAG_TE2 0x00000080U #define DMA_FLAG_GL3 0x00000100U #define DMA_FLAG_TC3 0x00000200U #define DMA_FLAG_HT3 0x00000400U #define DMA_FLAG_TE3 0x00000800U #define DMA_FLAG_GL4 0x00001000U #define DMA_FLAG_TC4 0x00002000U #define DMA_FLAG_HT4 0x00004000U #define DMA_FLAG_TE4 0x00008000U #define DMA_FLAG_GL5 0x00010000U #define DMA_FLAG_TC5 0x00020000U #define DMA_FLAG_HT5 0x00040000U #define DMA_FLAG_TE5 0x00080000U #define DMA_FLAG_GL6 0x00100000U #define DMA_FLAG_TC6 0x00200000U #define DMA_FLAG_HT6 0x00400000U #define DMA_FLAG_TE6 0x00800000U #if defined (DMA1_Channel7) #define DMA_FLAG_GL7 0x01000000U #define DMA_FLAG_TC7 0x02000000U #define DMA_FLAG_HT7 0x04000000U #define DMA_FLAG_TE7 0x08000000U #endif /* DMA1_Channel7 */ #if defined (DMA1_Channel8) #define DMA_FLAG_GL8 0x10000000U #define DMA_FLAG_TC8 0x20000000U #define DMA_FLAG_HT8 0x40000000U #define DMA_FLAG_TE8 0x80000000U #endif /* DMA1_Channel8 */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ /** @brief Reset DMA handle state. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Enable the specified DMA Channel. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) /* Interrupt & Flag management */ /** * @brief Return the current DMA Channel transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\ DMA_FLAG_TC8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ DMA_FLAG_TC6) #endif /* DMA1_Channel8 */ /** * @brief Return the current DMA Channel half transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\ DMA_FLAG_HT8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ DMA_FLAG_HT6) #endif /* DMA1_Channel8 */ /** * @brief Return the current DMA Channel transfer error flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\ DMA_FLAG_TE8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ DMA_FLAG_TE6) #endif /* DMA1_Channel8 */ /** * @brief Return the current DMA Channel Global interrupt flag. * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\ DMA_ISR_GIF8) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ DMA_ISR_GIF6) #endif /* DMA1_Channel8 */ /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx Transfer complete flag * @arg DMA_FLAG_HTx Half transfer complete flag * @arg DMA_FLAG_TEx Transfer error flag * @arg DMA_FLAG_GLx Global interrupt flag * Where x can be from 1 to 8 to select the DMA Channel x flag. * @retval The state of FLAG (SET or RESET). */ #if defined (DMA1_Channel8) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) #elif defined (DMA1_Channel6) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) #endif /* DMA1_Channel8 */ /** * @brief Clear the DMA Channel pending flags. * @param __HANDLE__ DMA handle * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx Transfer complete flag * @arg DMA_FLAG_HTx Half transfer complete flag * @arg DMA_FLAG_TEx Transfer error flag * @arg DMA_FLAG_GLx Global interrupt flag * Where x can be from 1 to 8 to select the DMA Channel x flag. * @retval None */ #if defined (DMA1_Channel8) #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) #else #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) #endif /* DMA1_Channel8 */ /** * @brief Enable the specified DMA Channel interrupts. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC Transfer complete interrupt mask * @arg DMA_IT_HT Half transfer complete interrupt mask * @arg DMA_IT_TE Transfer error interrupt mask * @retval None */ #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) /** * @brief Disable the specified DMA Channel interrupts. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC Transfer complete interrupt mask * @arg DMA_IT_HT Half transfer complete interrupt mask * @arg DMA_IT_TE Transfer error interrupt mask * @retval None */ #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) /** * @brief Check whether the specified DMA Channel interrupt is enabled or not. * @param __HANDLE__ DMA handle * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC Transfer complete interrupt mask * @arg DMA_IT_HT Half transfer complete interrupt mask * @arg DMA_IT_TE Transfer error interrupt mask * @retval The state of DMA_IT (SET or RESET). */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) /** * @brief Return the number of remaining data units in the current DMA Channel transfer. * @param __HANDLE__ DMA handle * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) /** * @} */ /* Include DMA HAL Extension module */ #include "stm32g4xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions * @{ */ /** @addtogroup DMA_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); /** * @} */ /** @addtogroup DMA_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros * @{ */ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ ((STATE) == DMA_MINC_DISABLE)) #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_PDATAALIGN_WORD)) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_MDATAALIGN_WORD )) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_HAL_DMA_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma_ex.h * @author MCD Application Team * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32G4xx_HAL_DMA_EX_H #define __STM32G4xx_HAL_DMA_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup DMAEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Types DMAEx Exported Types * @{ */ /** * @brief HAL DMA Synchro definition */ /** * @brief HAL DMAMUX Synchronization configuration structure definition */ typedef struct { uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled This parameter can take the value ENABLE or DISABLE*/ FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. This parameter can take the value ENABLE or DISABLE */ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ } HAL_DMA_MuxSyncConfigTypeDef; /** * @brief HAL DMAMUX request generator parameters structure definition */ typedef struct { uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ } HAL_DMA_MuxRequestGeneratorConfigTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants * @{ */ /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection * @{ */ #define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ #define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ #define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ #define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ #define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ #define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ #define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ #define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ #define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ #define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ #define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ #define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ #define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ #define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ #define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ #define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ #define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ /** * @} */ /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection * @{ */ #define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ #define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ #define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ #define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ /** * @} */ /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection * @{ */ #define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ /** * @} */ /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection * @{ */ #define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */ #define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ #define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ #define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup DMAEx_Exported_Functions * @{ */ /* IO operation functions *****************************************************/ /** @addtogroup DMAEx_Exported_Functions_Group1 * @{ */ /* ------------------------- REQUEST -----------------------------------------*/ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); /* -------------------------------------------------------------------------- */ /* ------------------------- SYNCHRO -----------------------------------------*/ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); /* -------------------------------------------------------------------------- */ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMAEx_Private_Macros DMAEx Private Macros * @brief DMAEx private macros * @{ */ #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT) #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ ((EVENT) == ENABLE)) #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT) #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* __STM32G4xx_HAL_DMA_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_exti.h * @author MCD Application Team * @brief Header file of EXTI HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_EXTI_H #define STM32G4xx_HAL_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup EXTI EXTI * @brief EXTI HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Types EXTI Exported Types * @{ */ typedef enum { HAL_EXTI_COMMON_CB_ID = 0x00UL } EXTI_CallbackIDTypeDef; /** * @brief EXTI Handle structure definition */ typedef struct { uint32_t Line; /*!< Exti line number */ void (* PendingCallback)(void); /*!< Exti pending callback */ } EXTI_HandleTypeDef; /** * @brief EXTI Configuration structure definition */ typedef struct { uint32_t Line; /*!< The Exti line to be configured. This parameter can be a value of @ref EXTI_Line */ uint32_t Mode; /*!< The Exit Mode to be configured for a core. This parameter can be a combination of @ref EXTI_Mode */ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter can be a value of @ref EXTI_Trigger */ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. This parameter is only possible for line 0 to 15. It can be a value of @ref EXTI_GPIOSel */ } EXTI_ConfigTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Constants EXTI Exported Constants * @{ */ /** @defgroup EXTI_Line EXTI Line * @{ */ #define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) #define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) #define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) #define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) #define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) #define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) #define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) #define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) #define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) #define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) #define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) #define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) #define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) #define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) #define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) #define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) #define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) #define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) #define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u) #define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u) #define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) #define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u) #define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u) #define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) #define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) #define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) #define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) #define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du) #define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu) #define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) #define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u) #define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) #define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u) #define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) #define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) #define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u) #define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u) #define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u) #define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u) #define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) /** * @} */ /** @defgroup EXTI_Mode EXTI Mode * @{ */ #define EXTI_MODE_NONE 0x00000000U #define EXTI_MODE_INTERRUPT 0x00000001U #define EXTI_MODE_EVENT 0x00000002U /** * @} */ /** @defgroup EXTI_Trigger EXTI Trigger * @{ */ #define EXTI_TRIGGER_NONE 0x00000000U #define EXTI_TRIGGER_RISING 0x00000001U #define EXTI_TRIGGER_FALLING 0x00000002U #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @} */ /** @defgroup EXTI_GPIOSel EXTI GPIOSel * @brief * @{ */ #define EXTI_GPIOA 0x00000000U #define EXTI_GPIOB 0x00000001U #define EXTI_GPIOC 0x00000002U #define EXTI_GPIOD 0x00000003U #define EXTI_GPIOE 0x00000004U #define EXTI_GPIOF 0x00000005U #define EXTI_GPIOG 0x00000006U /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup EXTI_Exported_Macros EXTI Exported Macros * @{ */ /** * @} */ /* Private constants --------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ /** * @brief EXTI Line property definition */ #define EXTI_PROPERTY_SHIFT 24U #define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) #define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) #define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI Register and bit usage */ #define EXTI_REG_SHIFT 16U #define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) #define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) #define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) #define EXTI_PIN_MASK 0x0000001FU /** * @brief EXTI Mask for interrupt & event mode */ #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) /** * @brief EXTI Mask for trigger possibilities */ #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @brief EXTI Line number */ #define EXTI_LINE_NB 44UL /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ #define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) #define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOF) || \ ((__PORT__) == EXTI_GPIOG)) #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) #define IS_EXTI_PENDING_EDGE(__EDGE__) (((__EDGE__) == EXTI_TRIGGER_RISING) || \ ((__EDGE__) == EXTI_TRIGGER_FALLING)|| \ ((__EDGE__) == EXTI_TRIGGER_RISING_FALLING)) #define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID) /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Functions EXTI Exported Functions * @brief EXTI Exported Functions * @{ */ /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions * @brief Configuration functions * @{ */ /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); /** * @} */ /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_EXTI_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash.h * @author MCD Application Team * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_FLASH_H #define STM32G4xx_HAL_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup FLASH * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup FLASH_Exported_Types FLASH Exported Types * @{ */ /** * @brief FLASH Erase structure definition */ typedef struct { uint32_t TypeErase; /*!< Mass erase or page erase. This parameter can be a value of @ref FLASH_Type_Erase */ uint32_t Banks; /*!< Select bank to erase. This parameter must be a value of @ref FLASH_Banks (FLASH_BANK_BOTH should be used only for mass erase) */ uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled. This parameter must be a value between 0 and (max number of pages in the bank - 1) (eg : 127 for 512KB dual bank) */ uint32_t NbPages; /*!< Number of pages to be erased. This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ } FLASH_EraseInitTypeDef; /** * @brief FLASH Option Bytes Program structure definition */ typedef struct { uint32_t OptionType; /*!< Option byte to be configured. This parameter can be a combination of the values of @ref FLASH_OB_Type */ uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). Only one WRP area could be programmed at the same time. This parameter can be value of @ref FLASH_OB_WRP_Area */ uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). This parameter must be a value between 0 and (max number of pages in the bank - 1) */ uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). This parameter can be a value of @ref FLASH_OB_Read_Protection */ uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_Type */ uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST @note (*) availability depends on devices */ uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) and @ref FLASH_OB_PCROP_RDP */ uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). This parameter must be a value between begin and end of bank => Be careful of the bank swapping for the address */ uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). This parameter must be a value between PCROP Start address and end of bank */ uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK). This parameter can be a value of @ref FLASH_OB_Boot_Lock */ uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC). Only one securable memory area could be programmed at the same time. This parameter can be one of the following values: FLASH_BANK_1: Securable memory area to be programmed in bank 1 FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*) @note (*) availability depends on devices */ uint32_t SecSize; /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC), in number of pages. Securable memory area is starting from first page of the bank. Only one securable memory could be programmed at the same time. This parameter must be a value between 0 and (max number of pages in the bank - 1) */ } FLASH_OBProgramInitTypeDef; /** * @brief FLASH Procedure structure definition */ typedef enum { FLASH_PROC_NONE = 0, FLASH_PROC_PAGE_ERASE, FLASH_PROC_MASS_ERASE, FLASH_PROC_PROGRAM, FLASH_PROC_PROGRAM_LAST } FLASH_ProcedureTypeDef; /** * @brief FLASH Cache structure definition */ typedef enum { FLASH_CACHE_DISABLED = 0, FLASH_CACHE_ICACHE_ENABLED, FLASH_CACHE_DCACHE_ENABLED, FLASH_CACHE_ICACHE_DCACHE_ENABLED } FLASH_CacheTypeDef; /** * @brief FLASH handle Structure definition */ typedef struct { HAL_LockTypeDef Lock; /* FLASH locking object */ __IO uint32_t ErrorCode; /* FLASH error code */ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ } FLASH_ProcessTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants FLASH Exported Constants * @{ */ /** @defgroup FLASH_Error FLASH Error * @{ */ #define HAL_FLASH_ERROR_NONE 0x00000000U #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD #if defined (FLASH_OPTR_DBANK) #define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2 #define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2 #endif /** * @} */ /** @defgroup FLASH_Type_Erase FLASH Erase Type * @{ */ #define FLASH_TYPEERASE_PAGES 0x00U /*!> 24U) /*!< ECC Correction Interrupt source */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup FLASH_Exported_Macros FLASH Exported Macros * @brief macros to control FLASH features * @{ */ /** * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency. * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states * @arg FLASH_LATENCY_5: FLASH Five wait states * @arg FLASH_LATENCY_6: FLASH Six wait states * @arg FLASH_LATENCY_7: FLASH Seven wait states * @arg FLASH_LATENCY_8: FLASH Eight wait states * @arg FLASH_LATENCY_9: FLASH Nine wait states * @arg FLASH_LATENCY_10: FLASH Ten wait state * @arg FLASH_LATENCY_11: FLASH Eleven wait state * @arg FLASH_LATENCY_12: FLASH Twelve wait states * @arg FLASH_LATENCY_13: FLASH Thirteen wait states * @arg FLASH_LATENCY_14: FLASH Fourteen wait states * @arg FLASH_LATENCY_15: FLASH Fifteen wait states * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) /** * @brief Get the FLASH Latency. * @retval FLASH_Latency. * This parameter can be one of the following values : * @arg FLASH_LATENCY_0: FLASH Zero wait state * @arg FLASH_LATENCY_1: FLASH One wait state * @arg FLASH_LATENCY_2: FLASH Two wait states * @arg FLASH_LATENCY_3: FLASH Three wait states * @arg FLASH_LATENCY_4: FLASH Four wait states * @arg FLASH_LATENCY_5: FLASH Five wait states * @arg FLASH_LATENCY_6: FLASH Six wait states * @arg FLASH_LATENCY_7: FLASH Seven wait states * @arg FLASH_LATENCY_8: FLASH Eight wait states * @arg FLASH_LATENCY_9: FLASH Nine wait states * @arg FLASH_LATENCY_10: FLASH Ten wait state * @arg FLASH_LATENCY_11: FLASH Eleven wait state * @arg FLASH_LATENCY_12: FLASH Twelve wait states * @arg FLASH_LATENCY_13: FLASH Thirteen wait states * @arg FLASH_LATENCY_14: FLASH Fourteen wait states * @arg FLASH_LATENCY_15: FLASH Fifteen wait states */ #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) /** * @brief Enable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) /** * @brief Disable the FLASH prefetch buffer. * @retval None */ #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) /** * @brief Enable the FLASH instruction cache. * @retval none */ #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Disable the FLASH instruction cache. * @retval none */ #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) /** * @brief Enable the FLASH data cache. * @retval none */ #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Disable the FLASH data cache. * @retval none */ #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) /** * @brief Reset the FLASH instruction Cache. * @note This function must be used only when the Instruction Cache is disabled. * @retval None */ #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ } while (0) /** * @brief Reset the FLASH data Cache. * @note This function must be used only when the data Cache is disabled. * @retval None */ #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ } while (0) /** * @brief Enable the FLASH power down during Low-power run mode. * @note Writing this bit to 1, automatically the keys are * lost and a new unlock sequence is necessary to re-write it to 0. */ #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ } while (0) /** * @brief Disable the FLASH power down during Low-power run mode. * @note Writing this bit to 0, automatically the keys are * lost and a new unlock sequence is necessary to re-write it to 1. */ #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ } while (0) /** * @brief Enable the FLASH power down during Low-Power sleep mode * @retval none */ #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @brief Disable the FLASH power down during Low-Power sleep mode * @retval none */ #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** * @} */ /** @defgroup FLASH_Interrupt FLASH Interrupts Macros * @brief macros to handle FLASH interrupts * @{ */ /** * @brief Enable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none */ #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while (0) /** * @brief Disable the specified FLASH interrupt. * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_OPERR: Error Interrupt * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt * @arg FLASH_IT_ECCC: ECC Correction Interrupt * @retval none */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ } while (0) /** * @brief Check whether the specified FLASH flag is set or not. * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) * @note (*) availability depends on devices * @retval The new state of FLASH_FLAG (SET or RESET). */ #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) /** * @brief Clear the FLASH's pending flags. * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH Operation error flag * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag * @arg FLASH_FLAG_SIZERR: FLASH Size error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only) * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only) * @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags * @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags * @note (*) availability depends on devices * @retval None */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ } while (0) /** * @} */ /* Include FLASH HAL Extended module */ #include "stm32g4xx_hal_flash_ex.h" #include "stm32g4xx_hal_flash_ramfunc.h" /* Exported variables --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Variables FLASH Exported Variables * @{ */ extern FLASH_ProcessTypeDef pFlash; /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_Exported_Functions * @{ */ /* Program operation functions ***********************************************/ /** @addtogroup FLASH_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); /* FLASH IRQ handler method */ void HAL_FLASH_IRQHandler(void); /* Callbacks in non blocking modes */ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); /** * @} */ /* Peripheral Control functions **********************************************/ /** @addtogroup FLASH_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); /* Option bytes control */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); /** * @} */ /* Peripheral State functions ************************************************/ /** @addtogroup FLASH_Exported_Functions_Group3 * @{ */ uint32_t HAL_FLASH_GetError(void); /** * @} */ /** * @} */ /** @addtogroup FLASH_Private_Functions * @{ */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @} */ /* Private constants --------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ #define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE #if defined (FLASH_OPTR_DBANK) #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) #define FLASH_PAGE_NB 128U #define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */ #else #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) #define FLASH_BANK_SIZE (FLASH_SIZE) #define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \ ((FLASH_SIZE == 0x00040000U) ? 128U : 64U)) #endif #define FLASH_PAGE_SIZE 0x800U /* 2 KB */ #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros * @{ */ #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ ((VALUE) == FLASH_TYPEERASE_MASSERASE)) #if defined (FLASH_OPTR_DBANK) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ ((BANK) == FLASH_BANK_2) || \ ((BANK) == FLASH_BANK_BOTH)) #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ ((BANK) == FLASH_BANK_2)) #else #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) #endif #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU)) #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) #define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC))) #if defined (FLASH_OPTR_DBANK) #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) #else #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) #endif #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ ((LEVEL) == OB_RDP_LEVEL_1) ||\ ((LEVEL) == OB_RDP_LEVEL_2)) #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U)) #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ ((LEVEL) == OB_BOR_LEVEL_4)) #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) #if defined (FLASH_OPTR_DBANK) #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) #endif #if defined (FLASH_OPTR_PB4_PUPEN) #define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE)) #endif #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE)) #define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE)) #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) #define IS_OB_USER_NRST_MODE(VALUE) (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \ ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT)) #define IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE)) #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) #define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB) #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_FLASH_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ex.h * @author MCD Application Team * @brief Header file of FLASH HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_FLASH_EX_H #define STM32G4xx_HAL_FLASH_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup FLASHEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions * @{ */ /* Extended Program operation functions *************************************/ /** @addtogroup FLASHEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank); void HAL_FLASHEx_EnableDebugger(void); void HAL_FLASHEx_DisableDebugger(void); /** * @} */ /** * @} */ /** @addtogroup FLASHEx_Private_Functions * @{ */ void FLASH_PageErase(uint32_t Page, uint32_t Banks); void FLASH_FlushCaches(void); /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_FLASH_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ramfunc.h * @author MCD Application Team * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_FLASH_RAMFUNC_H #define STM32G4xx_FLASH_RAMFUNC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup FLASH_RAMFUNC * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASH_RAMFUNC_Exported_Functions * @{ */ /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 * @{ */ /* Peripheral Control functions ************************************************/ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void); __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void); #if defined (FLASH_OPTR_DBANK) __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); #endif /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_FLASH_RAMFUNC_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_gpio.h * @author MCD Application Team * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_GPIO_H #define STM32G4xx_HAL_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup GPIO GPIO * @brief GPIO HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ */ /** * @brief GPIO Init structure definition */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode */ uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull */ uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed */ uint32_t Alternate; /*!< Peripheral to be connected to the selected pins This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ } GPIO_InitTypeDef; /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { GPIO_PIN_RESET = 0U, GPIO_PIN_SET } GPIO_PinState; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ */ /** @defgroup GPIO_pins GPIO pins * @{ */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ /** * @} */ /** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode * Elements values convention: 0x00WX00YZ * - W : EXTI trigger detection on 3 bits * - X : EXTI mode (IT or Event) on 2 bits * - Y : Output type (Push Pull or Open Drain) on 1 bit * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ */ #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ #define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ #define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup GPIO_speed GPIO speed * @brief GPIO Output Maximum frequency * @{ */ #define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ #define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */ /** * @} */ /** @defgroup GPIO_pull GPIO pull * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ #define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ #define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ */ /** * @brief Check whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) /** * @brief Clear the EXTI's line pending flags. * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) /** * @brief Check whether the specified EXTI line is asserted or not. * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) /** * @brief Clear the EXTI's line pending bits. * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) /** * @brief Generate a Software interrupt on selected EXTI line. * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ #define GPIO_MODE_Pos 0U #define GPIO_MODE (0x3UL << GPIO_MODE_Pos) #define MODE_INPUT (0x0UL << GPIO_MODE_Pos) #define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) #define MODE_AF (0x2UL << GPIO_MODE_Pos) #define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) #define OUTPUT_TYPE_Pos 4U #define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) #define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) #define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) #define EXTI_MODE_Pos 16U #define EXTI_MODE (0x3UL << EXTI_MODE_Pos) #define EXTI_IT (0x1UL << EXTI_MODE_Pos) #define EXTI_EVT (0x2UL << EXTI_MODE_Pos) #define TRIGGER_MODE_Pos 20U #define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) #define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) #define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) /** * @} */ /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ ((__MODE__) == GPIO_MODE_AF_PP) ||\ ((__MODE__) == GPIO_MODE_AF_OD) ||\ ((__MODE__) == GPIO_MODE_IT_RISING) ||\ ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ ((__MODE__) == GPIO_MODE_ANALOG)) #define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) #define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ ((__PULL__) == GPIO_PULLUP) || \ ((__PULL__) == GPIO_PULLDOWN)) /** * @} */ /* Include GPIO HAL Extended module */ #include "stm32g4xx_hal_gpio_ex.h" /* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Functions GPIO Exported Functions * @brief GPIO Exported Functions * @{ */ /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @{ */ /* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} */ /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @{ */ /* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_GPIO_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_gpio_ex.h * @author MCD Application Team * @brief Header file of GPIO HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_GPIO_EX_H #define STM32G4xx_HAL_GPIO_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup GPIOEx GPIOEx * @brief GPIO Extended HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ /** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection * @{ */ /** * @brief AF 0 selection */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ #if defined(TIM5) #define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ #define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ #define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ #define GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */ #define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */ #define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #if defined(TIM5) #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ #define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */ #define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */ #define GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF2_TIM20_COMP1 ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */ #define GPIO_AF2_TIM20_COMP2 ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */ #define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */ #define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */ #if defined(I2C4) #define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ #endif /* I2C4 */ #if defined(HRTIM1) #define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */ #endif /* HRTIM1 */ #if defined(QUADSPI) #define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */ #endif /* QUADSPI */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ #define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */ #define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */ #define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */ #define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */ #define GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ #if defined(I2C4) #define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ #endif /* I2C4 */ /** * @brief AF 5 selection */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ #if defined(SPI4) #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #endif /* SPI4 */ #define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */ #define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */ #define GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */ #if defined(UART5) #define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */ #endif /* UART5 */ #define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ #define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */ #if defined(TIM5) #define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */ #endif /* TIM5 */ #define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ #define GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */ #define GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */ #define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */ #define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #if defined(COMP5) #define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */ #endif /* COMP5 */ #if defined(COMP6) #define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */ #endif /* COMP6 */ #if defined(COMP7) #define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */ #endif /* COMP7 */ /** * @brief AF 8 selection */ #define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */ #define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */ #define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */ #define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */ #if defined(COMP5) #define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */ #endif /* COMP5 */ #if defined(COMP6) #define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */ #endif /* COMP6 */ #if defined(COMP7) #define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */ #endif /* COMP7 */ #define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */ #if defined(I2C4) #define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */ #endif /* I2C4 */ #define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #if defined(UART5) #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #endif /* UART5 */ /** * @brief AF 9 selection */ #define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */ #define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */ #define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ #if defined(FDCAN2) #define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ #endif /* FDCAN2 */ /** * @brief AF 10 selection */ #define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */ #define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */ #define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */ #define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ #define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */ #define GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */ #define GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */ #if defined(QUADSPI) #define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */ #endif /* QUADSPI */ /** * @brief AF 11 selection */ #define GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */ #if defined(FDCAN3) #define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */ #endif /* FDCAN3 */ #define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ #define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ #define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */ /** * @brief AF 12 selection */ #define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */ #define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ #if defined(HRTIM1) #define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */ #endif /* HRTIM1 */ #if defined(FMC_BANK1) #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #endif /* FMC_BANK1 */ #define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */ /** * @brief AF 13 selection */ #if defined(HRTIM1) #define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */ #endif /* HRTIM1 */ #define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ #define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ #define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */ #define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */ #define GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */ #if defined(UART5) #define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ #endif /* UART5 */ /** * @brief AF 15 selection */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros * @{ */ /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index * @{ */ #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ ((__GPIOx__) == (GPIOB))? 1UL :\ ((__GPIOx__) == (GPIOC))? 2UL :\ ((__GPIOx__) == (GPIOD))? 3UL :\ ((__GPIOx__) == (GPIOE))? 4UL :\ ((__GPIOx__) == (GPIOF))? 5UL : 6UL) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_GPIO_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr.h * @author MCD Application Team * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_PWR_H #define STM32G4xx_HAL_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ */ /** * @brief PWR PVD configuration structure definition */ typedef struct { uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This parameter can be a value of @ref PWR_PVD_detection_level. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWR_PVD_Mode. */ }PWR_PVDTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels * @{ */ #define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ #define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ #define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ #define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ #define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ #define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ #define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ #define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ /** * @} */ /** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode * @{ */ #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} */ /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode * @{ */ #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ /** * @} */ /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ /** * @} */ /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ #define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ /** * @} */ /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line * @{ */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** * @} */ /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line * @{ */ #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup PWR_Exported_Macros PWR Exported Macros * @{ */ /** @brief Check whether or not a specific PWR flag is set. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event * was received from the WKUP pin 1. * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event * was received from the WKUP pin 2. * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event * was received from the WKUP pin 3. * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event * was received from the WKUP pin 4. * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event * was received from the WKUP pin 5. * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system * entered StandBy mode. * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on * the internal wakeup line. * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the * low-power regulator is ready. * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the * regulator is ready in main mode or is in low-power mode. * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready * in the selected voltage range or is still changing to the required voltage level. * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is * below or above the selected PVD threshold. @if PWR_CR2_PVME1 * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is * is below or above PVM1 threshold (applicable when USB feature is supported). @endif @if PWR_CR2_PVME2 * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). @endif * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is * is below or above PVM3 threshold. * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is * is below or above PVM4 threshold. * * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) /** @brief Clear a specific PWR flag. * @param __FLAG__: specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event * was received from the WKUP pin 1. * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event * was received from the WKUP pin 2. * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event * was received from the WKUP pin 3. * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event * was received from the WKUP pin 4. * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event * was received from the WKUP pin 5. * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system * entered Standby mode. * @retval None */ #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ (PWR->SCR = (__FLAG__)) :\ (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) /** * @brief Enable the PVD Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) /** * @brief Enable the PVD Event Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) /** * @brief Disable the PVD Event Line. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) /** * @brief Enable the PVD Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) /** * @brief Enable the PVD Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) /** * @brief Disable the PVD Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) /** * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) /** * @brief Check whether or not the PVD EXTI interrupt flag is set. * @retval EXTI PVD Line Status. */ #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) /** * @brief Clear the PVD EXTI interrupt flag. * @retval None */ #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) /** * @} */ /* Private macros --------------------------------------------------------*/ /** @addtogroup PWR_Private_Macros PWR Private Macros * @{ */ #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) /** * @} */ /* Include PWR HAL Extended module */ #include "stm32g4xx_hal_pwr_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *******************************/ void HAL_PWR_DeInit(void); void HAL_PWR_EnableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void); /** * @} */ /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); /* WakeUp pins configuration functions ****************************************/ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); /* Low Power modes configuration functions ************************************/ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSTANDBYMode(void); void HAL_PWR_EnableSleepOnExit(void); void HAL_PWR_DisableSleepOnExit(void); void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_PVDCallback(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_PWR_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr_ex.h * @author MCD Application Team * @brief Header file of PWR HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_PWR_EX_H #define STM32G4xx_HAL_PWR_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup PWREx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWREx_Exported_Types PWR Extended Exported Types * @{ */ /** * @brief PWR PVM configuration structure definition */ typedef struct { uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. This parameter can be a value of @ref PWREx_PVM_Type. */ uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWREx_PVM_Mode. */ }PWR_PVMTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants * @{ */ /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants * @{ */ #define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polariry */ /** * @} */ /** @defgroup PWREx_WakeUp_Pins PWR wake-up pins * @{ */ #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<IMR2, PWR_EXTI_LINE_PVM1) /** * @brief Disable the PVM1 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) /** * @brief Enable the PVM1 Event Line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) /** * @brief Disable the PVM1 Event Line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) /** * @brief Enable the PVM1 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) /** * @brief Disable the PVM1 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) /** * @brief Enable the PVM1 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) /** * @brief Disable the PVM1 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) /** * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) /** * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. * @retval EXTI PVM1 Line Status. */ #define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) /** * @brief Clear the PVM1 EXTI flag. * @retval None */ #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) /** * @brief Enable the PVM2 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) /** * @brief Disable the PVM2 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) /** * @brief Enable the PVM2 Event Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) /** * @brief Disable the PVM2 Event Line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) /** * @brief Enable the PVM2 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) /** * @brief Disable the PVM2 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) /** * @brief Enable the PVM2 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) /** * @brief Disable the PVM2 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) /** * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) /** * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. * @retval EXTI PVM2 Line Status. */ #define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) /** * @brief Clear the PVM2 EXTI flag. * @retval None */ #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) #endif /* PWR_CR2_PVME2 */ /** * @brief Enable the PVM3 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) /** * @brief Disable the PVM3 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) /** * @brief Enable the PVM3 Event Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) /** * @brief Disable the PVM3 Event Line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) /** * @brief Enable the PVM3 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) /** * @brief Disable the PVM3 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) /** * @brief Enable the PVM3 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) /** * @brief Disable the PVM3 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) /** * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) /** * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. * @retval EXTI PVM3 Line Status. */ #define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) /** * @brief Clear the PVM3 EXTI flag. * @retval None */ #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) /** * @brief Enable the PVM4 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) /** * @brief Disable the PVM4 Extended Interrupt Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) /** * @brief Enable the PVM4 Event Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) /** * @brief Disable the PVM4 Event Line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) /** * @brief Enable the PVM4 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) /** * @brief Disable the PVM4 Extended Interrupt Rising Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) /** * @brief Enable the PVM4 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) /** * @brief Disable the PVM4 Extended Interrupt Falling Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) /** * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. * @retval None */ #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Generate a Software interrupt on selected EXTI line. * @retval None */ #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) /** * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. * @retval EXTI PVM4 Line Status. */ #define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) /** * @brief Clear the PVM4 EXTI flag. * @retval None */ #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) /** * @brief Configure the main internal regulator output voltage. * @param __REGULATOR__: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST Regulator voltage output range 1 mode, * typical output voltage at 1.28 V, * system frequency up to 170 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, * typical output voltage at 1.2 V, * system frequency up to 150 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, * typical output voltage at 1.0 V, * system frequency up to 26 MHz. * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check * whether or not VOSF flag is cleared when moving from range 2 to range 1. User * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. * @retval None */ #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ __IO uint32_t tmpreg; \ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ UNUSED(tmpreg); \ } while(0) /** * @} */ /* Private macros --------------------------------------------------------*/ /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros * @{ */ #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ ((PIN) == PWR_WAKEUP_PIN2) || \ ((PIN) == PWR_WAKEUP_PIN3) || \ ((PIN) == PWR_WAKEUP_PIN4) || \ ((PIN) == PWR_WAKEUP_PIN5) || \ ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ ((PIN) == PWR_WAKEUP_PIN5_LOW)) #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ ((TYPE) == PWR_PVM_2) ||\ ((TYPE) == PWR_PVM_3) ||\ ((TYPE) == PWR_PVM_4)) #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) #if defined(PWR_CR5_R1MODE) #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) #else #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) #endif #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00U) #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ ((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_C) ||\ ((GPIO) == PWR_GPIO_D) ||\ ((GPIO) == PWR_GPIO_E) ||\ ((GPIO) == PWR_GPIO_F) ||\ ((GPIO) == PWR_GPIO_G)) /** * @} */ /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @{ */ /* Peripheral Control functions **********************************************/ uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); void HAL_PWREx_DisableBatteryCharging(void); void HAL_PWREx_EnableInternalWakeUpLine(void); void HAL_PWREx_DisableInternalWakeUpLine(void); HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); void HAL_PWREx_EnablePullUpPullDownConfig(void); void HAL_PWREx_DisablePullUpPullDownConfig(void); void HAL_PWREx_EnableSRAM2ContentRetention(void); void HAL_PWREx_DisableSRAM2ContentRetention(void); #if defined(PWR_CR2_PVME1) void HAL_PWREx_EnablePVM1(void); void HAL_PWREx_DisablePVM1(void); #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) void HAL_PWREx_EnablePVM2(void); void HAL_PWREx_DisablePVM2(void); #endif /* PWR_CR2_PVME2 */ void HAL_PWREx_EnablePVM3(void); void HAL_PWREx_DisablePVM3(void); void HAL_PWREx_EnablePVM4(void); void HAL_PWREx_DisablePVM4(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); /* Low Power modes configuration functions ************************************/ void HAL_PWREx_EnableLowPowerRunMode(void); HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); void HAL_PWREx_EnterSHUTDOWNMode(void); void HAL_PWREx_PVD_PVM_IRQHandler(void); #if defined(PWR_CR2_PVME1) void HAL_PWREx_PVM1Callback(void); #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) void HAL_PWREx_PVM2Callback(void); #endif /* PWR_CR2_PVME2 */ void HAL_PWREx_PVM3Callback(void); void HAL_PWREx_PVM4Callback(void); #if defined(PWR_CR3_UCPD_STDBY) void HAL_PWREx_EnableUCPDStandbyMode(void); void HAL_PWREx_DisableUCPDStandbyMode(void); #endif /* PWR_CR3_UCPD_STDBY */ #if defined(PWR_CR3_UCPD_DBDIS) void HAL_PWREx_EnableUCPDDeadBattery(void); void HAL_PWREx_DisableUCPDDeadBattery(void); #endif /* PWR_CR3_UCPD_DBDIS */ /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_PWR_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc.h * @author MCD Application Team * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_RCC_H #define STM32G4xx_HAL_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ /** * @brief RCC PLL configuration structure definition */ typedef struct { uint32_t PLLState; /*!< The new state of the PLL. This parameter can be a value of @ref RCC_PLL_Config */ uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. This parameter must be a value of @ref RCC_PLL_Clock_Source */ uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 8 and Max_Data = 127 */ uint32_t PLLP; /*!< PLLP: Division factor for ADC clock. This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks. This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ uint32_t PLLR; /*!< PLLR: Division for the main system clock. User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ. This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ }RCC_PLLInitTypeDef; /** * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { uint32_t OscillatorType; /*!< The oscillators to be configured. This parameter can be a value of @ref RCC_Oscillator_Type */ uint32_t HSEState; /*!< The new state of the HSE. This parameter can be a value of @ref RCC_HSE_Config */ uint32_t LSEState; /*!< The new state of the LSE. This parameter can be a value of @ref RCC_LSE_Config */ uint32_t HSIState; /*!< The new state of the HSI. This parameter can be a value of @ref RCC_HSI_Config */ uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ uint32_t HSI48State; /*!< The new state of the HSI48. This parameter can be a value of @ref RCC_HSI48_Config */ RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ }RCC_OscInitTypeDef; /** * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { uint32_t ClockType; /*!< The clock to be configured. This parameter can be a value of @ref RCC_System_Clock_Type */ uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). This parameter can be a value of @ref RCC_System_Clock_Source */ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of @ref RCC_AHB_Clock_Source */ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ }RCC_ClkInitTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants RCC Exported Constants * @{ */ /** @defgroup RCC_Timeout_Value Timeout Values * @{ */ #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /** * @} */ /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ /** * @} */ /** @defgroup RCC_HSE_Config HSE Config * @{ */ #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ /** * @} */ /** @defgroup RCC_LSE_Config LSE Config * @{ */ #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ /** * @} */ /** @defgroup RCC_HSI_Config HSI Config * @{ */ #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ /** * @} */ /** @defgroup RCC_LSI_Config LSI Config * @{ */ #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** * @} */ /** @defgroup RCC_HSI48_Config HSI48 Config * @{ */ #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ /** * @} */ /** @defgroup RCC_PLL_Config PLL Config * @{ */ #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} */ /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider * @{ */ #define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */ #define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */ #define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */ #define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */ #define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */ #define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */ #define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */ #define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */ #define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */ #define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */ #define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */ #define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */ #define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */ #define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */ #define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */ #define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */ /** * @} */ /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider * @{ */ #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ /** * @} */ /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider * @{ */ #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ /** * @} */ /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider * @{ */ #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ /** * @} */ /** @defgroup RCC_PLL_Clock_Source PLL Clock Source * @{ */ #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ /** * @} */ /** @defgroup RCC_PLL_Clock_Output PLL Clock Output * @{ */ #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */ #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ /** * @} */ /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} */ /** @defgroup RCC_System_Clock_Source System Clock Source * @{ */ #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ /** * @} */ /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status * @{ */ #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ /** * @} */ /** @defgroup RCC_AHB_Clock_Source AHB Clock Source * @{ */ #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source * @{ */ #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ /** * @} */ /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ /** * @} */ /** @defgroup RCC_MCO_Index MCO Index * @{ */ /* 32 28 20 16 0 -------------------------------- | MCO | GPIO | GPIO | GPIO | | Index | AF | Port | Pin | -------------------------------*/ #define RCC_MCO_GPIOPORT_POS 16U #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) #define RCC_MCO_GPIOAF_POS 20U #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) #define RCC_MCO_INDEX_POS 28U #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ #define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) #define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) /* Legacy Defines*/ #define RCC_MCO1 RCC_MCO_PA8 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** * @} */ /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source * @{ */ #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ /** * @} */ /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler * @{ */ #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ /** * @} */ /** @defgroup RCC_Interrupt Interrupts * @{ */ #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ /** * @} */ /** @defgroup RCC_Flag Flags * Elements values convention: XXXYYYYYb * - YYYYY : Flag position in the register * - XXX : Register index * - 001: CR register * - 010: BDCR register * - 011: CSR register * - 100: CRRCR register * @{ */ /* Flags in the CR register */ #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ /* Flags in the CSR register */ #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ /* Flags in the CRRCR register */ #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ /** * @} */ /** @defgroup RCC_LSEDrive_Config LSE Drive Config * @{ */ #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup RCC_Exported_Macros RCC Exported Macros * @{ */ /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FMAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) /** * @} */ /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable * @brief Enable or disable the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_ADC12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \ UNUSED(tmpreg); \ } while(0) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \ UNUSED(tmpreg); \ } while(0) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \ UNUSED(tmpreg); \ } while(0) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \ UNUSED(tmpreg); \ } while(0) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ UNUSED(tmpreg); \ } while(0) #endif /* AES */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); #endif /* AES */ #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) /** * @} */ /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable * @brief Enable or disable the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ UNUSED(tmpreg); \ } while(0) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ UNUSED(tmpreg); \ } while(0) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable * @brief Enable or disable the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ UNUSED(tmpreg); \ } while(0) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ UNUSED(tmpreg); \ } while(0) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_CRS_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ UNUSED(tmpreg); \ } while(0) #if defined(UART4) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ UNUSED(tmpreg); \ } while(0) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \ UNUSED(tmpreg); \ } while(0) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \ UNUSED(tmpreg); \ } while(0) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDG2EN) #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) #if defined(UART4) #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable * @brief Enable or disable the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \ UNUSED(tmpreg); \ } while(0) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ UNUSED(tmpreg); \ } while(0) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ UNUSED(tmpreg); \ } while(0) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \ UNUSED(tmpreg); \ } while(0) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ UNUSED(tmpreg); \ } while(0) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \ UNUSED(tmpreg); \ } while(0) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status * @brief Check whether the AHB1 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) /** * @} */ /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status * @brief Check whether the AHB2 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) #define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) /** * @} */ /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status * @brief Check whether the AHB3 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status * @brief Check whether the APB1 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) #if defined(USB) #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U) #endif /* USB */ #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) /** * @} */ /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status * @brief Check whether the APB2 peripheral clock is enabled or not. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @{ */ #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset * @brief Force or release AHB1 peripheral reset. * @{ */ #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) /** * @} */ /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset * @brief Force or release AHB2 peripheral reset. * @{ */ #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) #if defined(DAC2) #define __HAL_RCC_DAC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) #endif /* DAC2 */ #define __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) #if defined(DAC4) #define __HAL_RCC_DAC4_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #endif /* AES */ #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST) #if defined(DAC2) #define __HAL_RCC_DAC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST) #endif /* DAC2 */ #define __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST) #if defined(DAC4) #define __HAL_RCC_DAC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) #endif /* AES */ #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) /** * @} */ /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset * @brief Force or release AHB3 peripheral reset. * @{ */ #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) #if defined(FMC_BANK1) #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) #if defined(FMC_BANK1) #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) #if defined(TIM5) #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) #endif /* TIM5 */ #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) #if defined(UART4) #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) #endif /* UART5 */ #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) #if defined(I2C4) #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) #if defined(TIM5) #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) #endif /* TIM5 */ #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) #if defined(UART4) #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) #endif /* UART5 */ #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) #if defined(I2C4) #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) /** * @} */ /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #if defined(SPI4) #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) #endif /* SPI4 */ #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #if defined(TIM20) #define __HAL_RCC_TIM20_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) #endif /* TIM20 */ #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) #endif /* HRTIM1 */ #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) #if defined(SPI4) #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST) #endif /* SPI4 */ #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) #if defined(TIM20) #define __HAL_RCC_TIM20_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST) #endif /* TIM20 */ #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) /** * @} */ /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) #define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) #endif /* AES */ #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) #define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) #if defined(DAC2) #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) #endif /* DAC2 */ #define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) #if defined(DAC4) #define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) #endif /* AES */ #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) /** * @} */ /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) #if defined(UART4) #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) #if defined(USB) #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) #endif /* USB */ #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) #if defined(TIM5) #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) #endif /* TIM5 */ #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) #if defined(UART4) #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) #endif /* UART5 */ #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) #if defined(USB) #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) #endif /* USB */ #if defined(FDCAN1) #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) #if defined(I2C4) #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) /** * @} */ /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) #if defined(SPI4) #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) #endif /* SPI4 */ #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) #if defined(TIM20) #define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) #endif /* TIM20 */ #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U) #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U) #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U) #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U) #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) /** * @} */ /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) #define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U) #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) #define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U) #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U) #if defined(ADC345_COMMON) #define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U) #endif /* ADC345_COMMON */ #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U) #if defined(DAC2) #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U) #endif /* DAC2 */ #define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U) #if defined(DAC4) #define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U) #endif /* DAC4 */ #if defined(AES) #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) #endif /* AES */ #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) /** * @} */ /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U) #endif /* QUADSPI */ #if defined(FMC_BANK1) #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) #endif /* FMC_BANK1 */ #if defined(QUADSPI) #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U) #endif /* QUADSPI */ /** * @} */ /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U) #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) #if defined(TIM5) #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) #endif /* TIM5 */ #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) #if defined(UART4) #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) #endif /* UART4 */ #if defined(UART5) #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) #endif /* UART5 */ #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U) #if defined(FDCAN1) #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U) #endif /* FDCAN1 */ #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) #if defined(I2C4) #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) #endif /* I2C4 */ #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U) /** * @} */ /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U) #endif /* HRTIM1 */ #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) #if defined(SPI4) #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U) #endif /* SPI4 */ #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) #if defined(TIM20) #define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U) #endif /* TIM20 */ #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) #if defined(HRTIM1) #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U) #endif /* HRTIM1 */ /** * @} */ /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset * @{ */ /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. * @note The BKPSRAM is not affected by this reset. * @retval None */ #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) /** * @} */ /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration * @{ */ /** @brief Macros to enable or disable the RTC clock. * @note As the RTC is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the RTC * (to be done once after reset). * @note These macros must be used after the RTC clock source was selected. * @retval None */ #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) /** * @} */ /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. * @retval None */ #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x7F. * @retval None */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) /** * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication * speed because of the HSI startup time. * @note The enable of this function has not effect on the HSION bit. * This parameter can be: ENABLE or DISABLE. * @retval None */ #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. * @retval None */ #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) /** * @brief Macro to configure the External High Speed oscillator (HSE). * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. * @retval None */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ do { \ if((__STATE__) == RCC_HSE_ON) \ { \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } \ else if((__STATE__) == RCC_HSE_BYPASS) \ { \ SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ SET_BIT(RCC->CR, RCC_CR_HSEON); \ } \ else \ { \ CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ } while(0) /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not * supported by this macro. User should request a transition to LSE Off * first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. * @retval None */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ do { \ if((__STATE__) == RCC_LSE_ON) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ else if((__STATE__) == RCC_LSE_BYPASS) \ { \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ } \ else \ { \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0) /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. * @note After enabling the HSI48, the application software should wait on HSI48RDY * flag to be set indicating that HSI48 clock is stable. * This parameter can be: ENABLE or DISABLE. * @retval None */ #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) /** @brief Macros to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it cannot be changed unless the * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by * a Power On Reset (POR). * * @param __RTC_CLKSOURCE__ specifies the RTC clock source. * This parameter can be one of the following values: * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected * * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). * @retval None */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) /** @brief Macro to get the RTC clock source. * @retval The returned value can be one of the following: * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected */ #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) /** @brief Macros to enable or disable the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. * @retval None */ #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * @retval None * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL source division factor M. * @note This function must be used only when the main PLL is disabled. * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency * of 8 MHz to limit PLL jitter. * @retval None * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) /** * @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This macro must be used only when the main PLL is disabled. * @note This macro preserves the PLL's output clocks enable state. * * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry * * @param __PLLM__ specifies the division factor for PLL VCO input clock. * This parameter must be a value of @ref RCC_PLLM_Clock_Divider * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency * of 8 MHz to limit PLL jitter. * * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. * This parameter must be a number between 8 and 127. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 64 and 344 MHz. * * @param __PLLP__ specifies the division factor for SAI clock. * This parameter must be a number in the range (2 to 31). * * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. * This parameter must be in the range (2, 4, 6 or 8). * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work * correctly. * @param __PLLR__ specifies the division factor for the main system clock. * @note You have to set the PLLR parameter correctly to not exceed 170MHZ. * This parameter must be in the range (2, 4, 6 or 8). * @retval None */ #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ MODIFY_REG(RCC->PLLCFGR, \ (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ ((__PLLSOURCE__) | \ (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) /** @brief Macro to get the oscillator used as PLL clock source. * @retval The oscillator used as PLL clock source. The returned value can be one * of the following: * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. */ #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) /** * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK) * @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot * be stopped if used as System Clock. * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. * This parameter can be one or a combination of the following values: * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), * FDCAN (<=48 MHz) and QSPI (<=48 MHz). * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) * @retval None */ #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) /** * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. * This parameter can be one of the following values: * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC. * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz), * FDCAN (<=48 MHz) and QSPI (<=48 MHz). * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz) * @retval SET / RESET */ #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) /** * @brief Macro to configure the system clock source. * @param __SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. * @retval None */ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) /** @brief Macro to get the clock source used as system clock. * @retval The clock source used as system clock. The returned value can be one * of the following: * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. */ #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) /** * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE * (to be done once after reset). * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. * This parameter can be one of the following values: * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. * @retval None */ #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) /** @brief Macro to configure the MCO clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 * @param __MCODIV__ specifies the MCO clock prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 */ #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable * the selected interrupts). * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval None */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable * the selected interrupts). * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval None */ #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval None */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) /** @brief Check whether the RCC interrupt has occurred or not. * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_IT_LSIRDY LSI ready interrupt * @arg @ref RCC_IT_LSERDY LSE ready interrupt * @arg @ref RCC_IT_HSIRDY HSI ready interrupt * @arg @ref RCC_IT_HSERDY HSE ready interrupt * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt * @arg @ref RCC_IT_CSS HSE Clock security system interrupt * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. * @retval None */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) /** @brief Check whether the selected RCC flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready * @arg @ref RCC_FLAG_BORRST BOR reset * @arg @ref RCC_FLAG_OBLRST OBLRST reset * @arg @ref RCC_FLAG_PINRST Pin reset * @arg @ref RCC_FLAG_SFTRST Software reset * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset * @arg @ref RCC_FLAG_LPWRRST Low Power reset * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ ? 1U : 0U) /** * @} */ /** * @} */ /* Private constants ---------------------------------------------------------*/ /** @addtogroup RCC_Private_Constants * @{ */ /* Defines used for Flags */ #define CR_REG_INDEX 1U #define BDCR_REG_INDEX 2U #define CSR_REG_INDEX 3U #define CRRCR_REG_INDEX 4U #define RCC_FLAG_MASK 0x1FU /* Define used for IS_RCC_CLOCKTYPE() */ #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCC_Private_Macros * @{ */ #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ ((__HSE__) == RCC_HSE_BYPASS)) #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ ((__LSE__) == RCC_LSE_BYPASS)) #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ ((__PLL__) == RCC_PLL_ON)) #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U)) #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ ((__HCLK__) == RCC_SYSCLK_DIV512)) #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ ((__PCLK__) == RCC_HCLK_DIV16)) #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \ ((__MCOX__) == RCC_MCO_PG10)) #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ ((__DIV__) == RCC_MCODIV_16)) #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) /** * @} */ /* Include RCC HAL Extended module */ #include "stm32g4xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_Exported_Functions * @{ */ /** @addtogroup RCC_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} */ /** @addtogroup RCC_Exported_Functions_Group2 * @{ */ /* Peripheral Control functions ************************************************/ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); void HAL_RCC_EnableCSS(void); void HAL_RCC_EnableLSECSS(void); void HAL_RCC_DisableLSECSS(void); uint32_t HAL_RCC_GetSysClockFreq(void); uint32_t HAL_RCC_GetHCLKFreq(void); uint32_t HAL_RCC_GetPCLK1Freq(void); uint32_t HAL_RCC_GetPCLK2Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); /** * @} */ /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_RCC_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc_ex.h * @author MCD Application Team * @brief Header file of RCC HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_RCC_EX_H #define STM32G4xx_HAL_RCC_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup RCCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types * @{ */ /** * @brief RCC extended clocks structure definition */ typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ #if defined(UART4) uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ #endif /* UART4 */ #if defined(UART5) uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ #endif /* UART5 */ uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ #if defined(I2C4) uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ #endif /* I2C4 */ uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ uint32_t I2sClockSelection; /*!< Specifies I2S clock source. This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ #if defined(FDCAN1) uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source. This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ #endif /* FDCAN1 */ #if defined(USB) uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). This parameter can be a value of @ref RCCEx_USB_Clock_Source */ #endif /* USB */ uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB). This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source. This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ #if defined(ADC345_COMMON) uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source. This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */ #endif /* ADC345_COMMON */ #if defined(QUADSPI) uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source. This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */ #endif uint32_t RTCClockSelection; /*!< Specifies RTC clock source. This parameter can be a value of @ref RCC_RTC_Clock_Source */ }RCC_PeriphCLKInitTypeDef; /** * @brief RCC_CRS Init structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ uint32_t Source; /*!< Specifies the SYNC signal source. This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ }RCC_CRSInitTypeDef; /** * @brief RCC_CRS Synchronization structure definition */ typedef struct { uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. This parameter must be a number between 0 and 0xFFFF */ uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. This parameter must be a number between 0 and 0x7F */ uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter value latched in the time of the last SYNC event. This parameter must be a number between 0 and 0xFFFF */ uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ }RCC_CRSSynchroInfoTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants * @{ */ /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source * @{ */ #define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ /** * @} */ /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ #define RCC_PERIPHCLK_USART1 0x00000001U #define RCC_PERIPHCLK_USART2 0x00000002U #define RCC_PERIPHCLK_USART3 0x00000004U #if defined(UART4) #define RCC_PERIPHCLK_UART4 0x00000008U #endif /* UART4 */ #if defined(UART5) #define RCC_PERIPHCLK_UART5 0x00000010U #endif /* UART5 */ #define RCC_PERIPHCLK_LPUART1 0x00000020U #define RCC_PERIPHCLK_I2C1 0x00000040U #define RCC_PERIPHCLK_I2C2 0x00000080U #define RCC_PERIPHCLK_I2C3 0x00000100U #define RCC_PERIPHCLK_LPTIM1 0x00000200U #define RCC_PERIPHCLK_SAI1 0x00000400U #define RCC_PERIPHCLK_I2S 0x00000800U #if defined(FDCAN1) #define RCC_PERIPHCLK_FDCAN 0x00001000U #endif /* FDCAN1 */ #define RCC_PERIPHCLK_USB 0x00002000U #define RCC_PERIPHCLK_RNG 0x00004000U #define RCC_PERIPHCLK_ADC12 0x00008000U #if defined(ADC345_COMMON) #define RCC_PERIPHCLK_ADC345 0x00010000U #endif /* ADC345_COMMON */ #if defined(I2C4) #define RCC_PERIPHCLK_I2C4 0x00020000U #endif /* I2C4 */ #if defined(QUADSPI) #define RCC_PERIPHCLK_QSPI 0x00040000U #endif /* QUADSPI */ #define RCC_PERIPHCLK_RTC 0x00080000U /** * @} */ /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source * @{ */ #define RCC_USART1CLKSOURCE_PCLK2 0x00000000U #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /** * @} */ /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source * @{ */ #define RCC_USART2CLKSOURCE_PCLK1 0x00000000U #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) /** * @} */ /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source * @{ */ #define RCC_USART3CLKSOURCE_PCLK1 0x00000000U #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) /** * @} */ #if defined(UART4) /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source * @{ */ #define RCC_UART4CLKSOURCE_PCLK1 0x00000000U #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) /** * @} */ #endif /* UART4 */ #if defined(UART5) /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source * @{ */ #define RCC_UART5CLKSOURCE_PCLK1 0x00000000U #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) /** * @} */ #endif /* UART5 */ /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source * @{ */ #define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) /** * @} */ /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source * @{ */ #define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /** * @} */ /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source * @{ */ #define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /** * @} */ /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source * @{ */ #define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 /** * @} */ /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source * @{ */ #define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /** * @} */ /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source * @{ */ #define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 #define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1 #define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0) /** * @} */ /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source * @{ */ #define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U #define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 #define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1 #define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0) /** * @} */ #if defined(FDCAN1) /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source * @{ */ #define RCC_FDCANCLKSOURCE_HSE 0x00000000U #define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 #define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 /** * @} */ #endif /* FDCAN1 */ /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source * @{ */ #define RCC_RNGCLKSOURCE_HSI48 0x00000000U #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /** * @} */ /** @defgroup RCCEx_USB_Clock_Source USB Clock Source * @{ */ #define RCC_USBCLKSOURCE_HSI48 0x00000000U #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /** * @} */ /** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source * @{ */ #define RCC_ADC12CLKSOURCE_NONE 0x00000000U #define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0 #define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1 /** * @} */ #if defined(ADC345_COMMON) /** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source * @{ */ #define RCC_ADC345CLKSOURCE_NONE 0x00000000U #define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0 #define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1 /** * @} */ #endif /* ADC345_COMMON */ #if defined(I2C4) /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source * @{ */ #define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 /** * @} */ #endif /* I2C4 */ #if defined(QUADSPI) /** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source * @{ */ #define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U #define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 #define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 /** * @} */ #endif /* QUADSPI */ /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line * @{ */ #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ /** * @} */ /** @defgroup RCCEx_CRS_Status RCCEx CRS Status * @{ */ #define RCC_CRS_NONE 0x00000000U #define RCC_CRS_TIMEOUT 0x00000001U #define RCC_CRS_SYNCOK 0x00000002U #define RCC_CRS_SYNCWARN 0x00000004U #define RCC_CRS_SYNCERR 0x00000008U #define RCC_CRS_SYNCMISS 0x00000010U #define RCC_CRS_TRIMOVF 0x00000020U /** * @} */ /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ */ #define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** * @} */ /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider * @{ */ #define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ /** * @} */ /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity * @{ */ #define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ /** * @} */ /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault * @{ */ #define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ /** * @} */ /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault * @{ */ #define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ /** * @} */ /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault * @{ */ #define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ /** * @} */ /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection * @{ */ #define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ /** * @} */ /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources * @{ */ #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ /** * @} */ /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags * @{ */ #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ /** * @} */ /** * @} */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros * @{ */ /** @brief Macro to configure the USART1 clock (USART1CLK). * * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock * @retval None */ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ #define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) /** @brief Macro to configure the USART2 clock (USART2CLK). * * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock * @retval None */ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ #define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) /** @brief Macro to configure the USART3 clock (USART3CLK). * * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock * @retval None */ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ #define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) #if defined(UART4) /** @brief Macro to configure the UART4 clock (UART4CLK). * * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. * This parameter can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock * @retval None */ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) /** @brief Macro to get the UART4 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock */ #define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) #endif /* UART4 */ #if defined(UART5) /** @brief Macro to configure the UART5 clock (UART5CLK). * * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. * This parameter can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock * @retval None */ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) /** @brief Macro to get the UART5 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock */ #define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) #endif /* UART5 */ /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). * * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock * @retval None */ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) /** @brief Macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ #define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) /** @brief Macro to configure the I2C1 clock (I2C1CLK). * * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock * @retval None */ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ #define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) /** @brief Macro to configure the I2C2 clock (I2C2CLK). * * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock * @retval None */ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) /** @brief Macro to configure the I2C3 clock (I2C3CLK). * * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock * @retval None */ #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock */ #define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) #if defined(I2C4) /** @brief Macro to configure the I2C4 clock (I2C4CLK). * * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. * This parameter can be one of the following values: * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock * @retval None */ #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) /** @brief Macro to get the I2C4 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock */ #define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) #endif /* I2C4 */ /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). * * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. * This parameter can be one of the following values: * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock * @retval None */ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) /** @brief Macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock */ #define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) /** * @brief Macro to configure the SAI1 clock source. * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived * from the HSI, system PLL, System Clock or external clock. * This parameter can be one of the following values: * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI * * @retval None */ #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock * @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI * */ #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) /** * @brief Macro to configure the I2S clock source. * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived * from the HSI, system PLL, System Clock or external clock. * This parameter can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI * * @retval None */ #define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__)) /** @brief Macro to get the I2S clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock * @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock * @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT * @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI * */ #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL))) #if defined(FDCAN1) /** * @brief Macro to configure the FDCAN clock source. * @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived * from the HSE, system PLL or PCLK1. * This parameter can be one of the following values: * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 * * @retval None */ #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) /** @brief Macro to get the FDCAN clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE * @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1 * */ #define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL))) #endif /* FDCAN1 */ /** @brief Macro to configure the RNG clock. * * @note USB and RNG peripherals share the same 48MHz clock source. * * @param __RNG_CLKSOURCE__ specifies the RNG clock source. * This parameter can be one of the following values: * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock * @retval None */ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) /** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock */ #define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #if defined(USB) /** @brief Macro to configure the USB clock (USBCLK). * * @note USB, RNG peripherals share the same 48MHz clock source. * * @param __USB_CLKSOURCE__ specifies the USB clock source. * This parameter can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock * @retval None */ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock */ #define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) #endif /* USB */ /** @brief Macro to configure the ADC12 interface clock. * @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock * @retval None */ #define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__)) /** @brief Macro to get the ADC12 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock * @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock */ #define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL)) #if defined(ADC345_COMMON) /** @brief Macro to configure the ADC345 interface clock. * @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source. * This parameter can be one of the following values: * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock * @retval None */ #define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__) /** @brief Macro to get the ADC345 clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock * @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock */ #define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL)) #endif /* ADC345_COMMON */ #if defined(QUADSPI) /** @brief Macro to configure the QuadSPI clock. * @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source. * This parameter can be one of the following values: * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock * @retval None */ #define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \ MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__) /** @brief Macro to get the QuadSPI clock source. * @retval The clock source can be one of the following values: * @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock * @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock */ #define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL)) #endif /* QUADSPI */ /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ */ /** * @brief Enable the RCC LSE CSS Extended Interrupt Line. * @retval None */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Extended Interrupt Line. * @retval None */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Event Line. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Event Line. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ do { \ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ } while(0) /** * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ do { \ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ } while(0) /** * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. * @retval EXTI RCC LSE CSS Line Status. */ #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) /** * @brief Clear the RCC LSE CSS EXTI flag. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) /** * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. * @retval None. */ #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) /** * @brief Enable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval None */ #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) /** * @brief Disable the specified CRS interrupts. * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval None */ #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) /** @brief Check whether the CRS interrupt has occurred or not. * @param __INTERRUPT__ specifies the CRS interrupt source to check. * This parameter can be one of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) /** @brief Clear the CRS interrupt pending bits * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt */ /* CRS IT Error Mask */ #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ } \ else \ { \ WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ } \ } while(0) /** * @brief Check whether the specified CRS flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning * @arg @ref RCC_CRS_FLAG_ERR Error * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed * @retval The new state of _FLAG_ (TRUE or FALSE). */ #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) /** * @brief Clear the CRS specified FLAG. * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning * @arg @ref RCC_CRS_FLAG_ERR Error * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR * @retval None */ /* CRS Flag Error Mask */ #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ { \ WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ } \ else \ { \ WRITE_REG(CRS->ICR, (__FLAG__)); \ } \ } while(0) /** * @} */ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features * @{ */ /** * @brief Enable the oscillator clock for frequency error counter. * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) /** * @brief Disable the oscillator clock for frequency error counter. * @retval None */ #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) /** * @brief Enable the automatic hardware adjustment of TRIM bits. * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** * @brief Enable or disable the automatic hardware adjustment of TRIM bits. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency * of the synchronization source after prescaling. It is then decreased by one in order to * reach the expected synchronization on the zero value. The formula is the following: * RELOAD = (fTARGET / fSYNC) -1 * @param __FTARGET__ Target frequency (value in Hz) * @param __FSYNC__ Synchronization signal frequency (value in Hz) * @retval None */ #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCCEx_Exported_Functions * @{ */ /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** * @} */ /** @addtogroup RCCEx_Exported_Functions_Group2 * @{ */ void HAL_RCCEx_EnableLSECSS(void); void HAL_RCCEx_DisableLSECSS(void); void HAL_RCCEx_EnableLSECSS_IT(void); void HAL_RCCEx_LSECSS_IRQHandler(void); void HAL_RCCEx_LSECSS_Callback(void); void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); void HAL_RCCEx_DisableLSCO(void); /** * @} */ /** @addtogroup RCCEx_Exported_Functions_Group3 * @{ */ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); void HAL_RCCEx_CRS_IRQHandler(void); void HAL_RCCEx_CRS_SyncOkCallback(void); void HAL_RCCEx_CRS_SyncWarnCallback(void); void HAL_RCCEx_CRS_ExpectedSyncCallback(void); void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); /** * @} */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCCEx_Private_Macros * @{ */ #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G471xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G431xx) || defined(STM32G441xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32GBK1CB) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #endif /* STM32G474xx || STM32G484xx */ #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) #if defined(UART4) #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) #endif /* UART4 */ #if defined(UART5) #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) #endif /* UART5 */ #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) #if defined(I2C4) #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) #endif /* I2C4 */ #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) #define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \ ((__SOURCE__) == RCC_I2SCLKSOURCE_HSI)) #if defined(FDCAN1) #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) #endif /* FDCAN1 */ #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) #if defined(USB) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) #endif /* USB */ #define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK)) #if defined(ADC345_COMMON) #define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \ ((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK)) #endif /* ADC345_COMMON */ #if defined(QUADSPI) #define IS_RCC_QSPICLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)) #endif /* QUADSPI */ #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_RCC_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim.h * @author MCD Application Team * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_TIM_H #define STM32G4xx_HAL_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIM_Exported_Types TIM Exported Types * @{ */ /** * @brief TIM Time base Configuration Structure definition */ typedef struct { uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** * @brief TIM Output Compare Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate Pulse value */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCFastMode; /*!< Specifies the Fast mode state. This parameter can be a value of @ref TIM_Output_Fast_State @note This parameter is valid only in PWM1 and PWM2 mode. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ } TIM_OC_InitTypeDef; /** * @brief TIM One Pulse Mode Configuration Structure definition */ typedef struct { uint32_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate Pulse value */ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for timer instances supporting break feature. */ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; /** * @brief TIM Input Capture Configuration Structure definition */ typedef struct { uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_IC_InitTypeDef; /** * @brief TIM Encoder Configuration Structure definition */ typedef struct { uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC2Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; /** * @brief Clock Configuration Handle Structure definition */ typedef struct { uint32_t ClockSource; /*!< TIM clock sources This parameter can be a value of @ref TIM_Clock_Source */ uint32_t ClockPolarity; /*!< TIM clock polarity This parameter can be a value of @ref TIM_Clock_Polarity */ uint32_t ClockPrescaler; /*!< TIM clock prescaler This parameter can be a value of @ref TIM_Clock_Prescaler */ uint32_t ClockFilter; /*!< TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClockConfigTypeDef; /** * @brief TIM Clear Input Configuration Handle Structure definition */ typedef struct { uint32_t ClearInputState; /*!< TIM clear Input state This parameter can be ENABLE or DISABLE */ uint32_t ClearInputSource; /*!< TIM clear Input sources This parameter can be a value of @ref TIM_ClearInput_Source */ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; /** * @brief TIM Master configuration Structure definition * @note Advanced timers provide TRGO2 internal line which is redirected * to the ADC */ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode @note When the Master/slave mode is enabled, the effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is not mandatory in case of timer synchronization mode. */ } TIM_MasterConfigTypeDef; /** * @brief TIM Slave configuration Structure definition */ typedef struct { uint32_t SlaveMode; /*!< Slave mode selection This parameter can be a value of @ref TIM_Slave_Mode */ uint32_t InputTrigger; /*!< Input Trigger source This parameter can be a value of @ref TIM_Trigger_Selection */ uint32_t TriggerPolarity; /*!< Input Trigger polarity This parameter can be a value of @ref TIM_Trigger_Polarity */ uint32_t TriggerPrescaler; /*!< Input trigger prescaler This parameter can be a value of @ref TIM_Trigger_Prescaler */ uint32_t TriggerFilter; /*!< Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_SlaveConfigTypeDef; /** * @brief TIM Break input(s) and Dead time configuration Structure definition * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable * filter and polarity. */ typedef struct { uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BreakDeadTimeConfigTypeDef; /** * @brief HAL State structures definition */ typedef enum { HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; /** * @brief TIM Channel States definition */ typedef enum { HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ } HAL_TIM_ChannelStateTypeDef; /** * @brief DMA Burst States definition */ typedef enum { HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ } HAL_TIM_DMABurstStateTypeDef; /** * @brief HAL Active channel structures definition */ typedef enum { HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ } HAL_TIM_ActiveChannel; /** * @brief TIM Time Base Handle Structure definition */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) typedef struct __TIM_HandleTypeDef #else typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { TIM_TypeDef *Instance; /*!< Register base address */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array This array is accessed by a @ref DMA_Handle_index */ HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } TIM_HandleTypeDef; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief HAL TIM Callback ID enumeration definition */ typedef enum { HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** * @brief HAL TIM Callback pointer definition */ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_Constants TIM Exported Constants * @{ */ /** @defgroup TIM_ClearInput_Source TIM Clear Input Source * @{ */ #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ #define TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */ #define TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */ #if defined (COMP5) #define TIM_CLEARINPUTSOURCE_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_CLEARINPUTSOURCE_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_CLEARINPUTSOURCE_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */ #endif /* COMP7 */ /** * @} */ /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ #define TIM_DMABASE_CR1 0x00000000U #define TIM_DMABASE_CR2 0x00000001U #define TIM_DMABASE_SMCR 0x00000002U #define TIM_DMABASE_DIER 0x00000003U #define TIM_DMABASE_SR 0x00000004U #define TIM_DMABASE_EGR 0x00000005U #define TIM_DMABASE_CCMR1 0x00000006U #define TIM_DMABASE_CCMR2 0x00000007U #define TIM_DMABASE_CCER 0x00000008U #define TIM_DMABASE_CNT 0x00000009U #define TIM_DMABASE_PSC 0x0000000AU #define TIM_DMABASE_ARR 0x0000000BU #define TIM_DMABASE_RCR 0x0000000CU #define TIM_DMABASE_CCR1 0x0000000DU #define TIM_DMABASE_CCR2 0x0000000EU #define TIM_DMABASE_CCR3 0x0000000FU #define TIM_DMABASE_CCR4 0x00000010U #define TIM_DMABASE_BDTR 0x00000011U #define TIM_DMABASE_CCR5 0x00000012U #define TIM_DMABASE_CCR6 0x00000013U #define TIM_DMABASE_CCMR3 0x00000014U #define TIM_DMABASE_DTR2 0x00000015U #define TIM_DMABASE_ECR 0x00000016U #define TIM_DMABASE_TISEL 0x00000017U #define TIM_DMABASE_AF1 0x00000018U #define TIM_DMABASE_AF2 0x00000019U #define TIM_DMABASE_OR 0x0000001AU /** * @} */ /** @defgroup TIM_Event_Source TIM Event Source * @{ */ #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ /** * @} */ /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** * @} */ /** @defgroup TIM_ETR_Polarity TIM ETR Polarity * @{ */ #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ /** * @} */ /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ /** * @} */ /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap * @{ */ #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ /** * @} */ /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ /** * @} */ /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ /** * @} */ /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload * @{ */ #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ /** * @} */ /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ /** * @} */ /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ /** * @} */ /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State * @{ */ #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State * @{ */ #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ /** * @} */ /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity * @{ */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ /** * @} */ /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity * @{ */ #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ /** * @} */ /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ /** * @} */ /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode * @{ */ #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ /** @defgroup TIM_Encoder_Mode TIM Encoder Mode * @{ */ #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ #define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ #define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ /** * @} */ /** @defgroup TIM_Interrupt_definition TIM interrupt Definition * @{ */ #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ #define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ #define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ #define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ #define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ /** * @} */ /** @defgroup TIM_Commutation_Source TIM Commutation Source * @{ */ #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ /** * @} */ /** @defgroup TIM_DMA_sources TIM DMA Sources * @{ */ #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ /** * @} */ /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ #define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ #define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ #define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ #define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ /** * @} */ /** @defgroup TIM_Channel TIM Channel * @{ */ #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ /** * @} */ /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ #if defined (TIM5) #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ #endif /* TIM5 */ #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ #if defined (TIM20) #define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ #endif /* TIM20 */ #define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ /** * @} */ /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** * @} */ /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler * @{ */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler * @{ */ #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state * @{ */ #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state * @{ */ #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ /** * @} */ /** @defgroup TIM_Lock_level TIM Lock level * @{ */ #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ /** * @} */ /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable * @{ */ #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ /** * @} */ /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ /** * @} */ /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode * @{ */ #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ /** * @} */ /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ */ #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ /** * @} */ /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity * @{ */ #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ /** * @} */ /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode * @{ */ #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ /** * @} */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ #define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ /** * @} */ /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) * @{ */ #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ /** * @} */ /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ /** * @} */ /** @defgroup TIM_Slave_Mode TIM Slave mode * @{ */ #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ #define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ /** * @} */ /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes * @{ */ #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ /** * @} */ /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #if defined (TIM5) #define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */ #endif /* TIM5 */ #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ #if defined (TIM20) #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ #endif /* TIM20 */ #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ #define TIM_TS_NONE 0xFFFFFFFFU /*!< No trigger selected */ /** * @} */ /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity * @{ */ #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ /** * @} */ /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler * @{ */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ /** * @} */ /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ /** * @} */ /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ /** @defgroup DMA_Handle_index TIM DMA Handle Index * @{ */ #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ /** @defgroup Channel_CC_State TIM Capture/Compare Channel State * @{ */ #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ /** * @} */ /** @defgroup TIM_Break_System TIM Break System * @{ */ #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */ #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */ #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */ #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ /** @defgroup TIM_Exported_Macros TIM Exported Macros * @{ */ /** @brief Reset TIM handle state. * @param __HANDLE__ TIM handle. * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ (__HANDLE__)->Base_MspInitCallback = NULL; \ (__HANDLE__)->Base_MspDeInitCallback = NULL; \ (__HANDLE__)->IC_MspInitCallback = NULL; \ (__HANDLE__)->IC_MspDeInitCallback = NULL; \ (__HANDLE__)->OC_MspInitCallback = NULL; \ (__HANDLE__)->OC_MspDeInitCallback = NULL; \ (__HANDLE__)->PWM_MspInitCallback = NULL; \ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ (__HANDLE__)->Encoder_MspInitCallback = NULL; \ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @brief Enable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) /** * @brief Disable the TIM peripheral. * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ } while(0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ { \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ } while(0) /** * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval None */ #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) /** @brief Disable the specified TIM interrupt. * @param __HANDLE__ specifies the TIM Handle. * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval None */ #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. * @param __HANDLE__ specifies the TIM Handle. * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @arg TIM_FLAG_IDX: Index interrupt flag * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. * @param __HANDLE__ specifies the TIM Handle. * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag * @arg TIM_FLAG_CC5: Compare 5 interrupt flag * @arg TIM_FLAG_CC6: Compare 6 interrupt flag * @arg TIM_FLAG_COM: Commutation interrupt flag * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag * @arg TIM_FLAG_BREAK: Break interrupt flag * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag * @arg TIM_FLAG_IDX: Index interrupt flag * @arg TIM_FLAG_DIR: Direction change interrupt flag * @arg TIM_FLAG_IERR: Index error interrupt flag * @arg TIM_FLAG_TERR: Transition error interrupt flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** * @brief Check whether the specified TIM interrupt source is enabled or not. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval The state of TIM_IT (SET or RESET). */ #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_IDX: Index interrupt * @arg TIM_IT_DIR: Direction change interrupt * @arg TIM_IT_IERR: Index error interrupt * @arg TIM_IT_TERR: Transition error interrupt * @retval None */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read * in an atomic way. * @param __HANDLE__ TIM handle. * @retval None mode. */ #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) /** * @brief Disable update interrupt flag (UIF) remapping. * @param __HANDLE__ TIM handle. * @retval None mode. */ #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) /** * @brief Get update interrupt flag (UIF) copy status. * @param __COUNTER__ Counter value. * @retval The state of UIFCPY (TRUE or FALSE). mode. */ #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) /** * @brief Set the TIM Prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) /** * @brief Set the TIM Counter Register value on runtime. * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in * case of 32 bits counter TIM instance. * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Get the TIM Counter Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while(0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. * @param __HANDLE__ TIM handle. * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do{ \ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ } while(0) /** * @brief Get the TIM Clock Division value on runtime. * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do{ \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ } while(0) /** * @brief Get the TIM Input Capture prescaler on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval The input capture prescaler can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) /** * @brief Get the TIM Capture Compare Register value on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @arg TIM_CHANNEL_5: get capture/compare 5 register value * @arg TIM_CHANNEL_6: get capture/compare 6 register value * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__HANDLE__)->Instance->CCR6)) /** * @brief Set the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval None */ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) /** * @brief Reset the TIM Output compare preload. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) /** * @brief Enable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @note When fast mode is enabled an active edge on the trigger input acts * like a compare match on CCx output. Delay to sample the trigger * input and to activate CCx output is reduced to 3 clock cycles. * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. * @retval None */ #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) /** * @brief Disable fast mode for a given channel. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @note When fast mode is disabled CCx output behaves normally depending * on counter and CCRx values even when the trigger is ON. The minimum * delay to activate CCx output when an active edge occurs on the * trigger input is 5 clock cycles. * @retval None */ #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) * @retval None */ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @param __HANDLE__ TIM handle. * @note When the URS bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): * _ Counter overflow underflow * _ Setting the UG bit * _ Update generation through the slave mode controller * @retval None */ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ do{ \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) /** * @} */ /* End of exported macros ----------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIM_Private_Constants TIM Private Constants * @{ */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) /** * @} */ /* End of private constants --------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup TIM_Private_Macros TIM Private Macros * @{ */ #if defined(COMP5) && defined(COMP6) && defined(COMP7) #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) #else /* COMP5 && COMP6 && COMP7 */ #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) #endif /* COMP5 && COMP6 && COMP7 */ #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ ((__BASE__) == TIM_DMABASE_CR2) || \ ((__BASE__) == TIM_DMABASE_SMCR) || \ ((__BASE__) == TIM_DMABASE_DIER) || \ ((__BASE__) == TIM_DMABASE_SR) || \ ((__BASE__) == TIM_DMABASE_EGR) || \ ((__BASE__) == TIM_DMABASE_CCMR1) || \ ((__BASE__) == TIM_DMABASE_CCMR2) || \ ((__BASE__) == TIM_DMABASE_CCER) || \ ((__BASE__) == TIM_DMABASE_CNT) || \ ((__BASE__) == TIM_DMABASE_PSC) || \ ((__BASE__) == TIM_DMABASE_ARR) || \ ((__BASE__) == TIM_DMABASE_RCR) || \ ((__BASE__) == TIM_DMABASE_CCR1) || \ ((__BASE__) == TIM_DMABASE_CCR2) || \ ((__BASE__) == TIM_DMABASE_CCR3) || \ ((__BASE__) == TIM_DMABASE_CCR4) || \ ((__BASE__) == TIM_DMABASE_BDTR) || \ ((__BASE__) == TIM_DMABASE_CCMR3) || \ ((__BASE__) == TIM_DMABASE_CCR5) || \ ((__BASE__) == TIM_DMABASE_CCR6) || \ ((__BASE__) == TIM_DMABASE_AF1) || \ ((__BASE__) == TIM_DMABASE_AF2) || \ ((__BASE__) == TIM_DMABASE_TISEL) || \ ((__BASE__) == TIM_DMABASE_DTR2) || \ ((__BASE__) == TIM_DMABASE_ECR) || \ ((__BASE__) == TIM_DMABASE_OR)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ ((__MODE__) == TIM_UIFREMAP_ENALE)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ ((__STATE__) == TIM_OCFAST_ENABLE)) #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ ((__POLARITY__) == TIM_OCPOLARITY_LOW)) #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ ((__STATE__) == TIM_OCIDLESTATE_RESET)) #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ ((__SELECTION__) == TIM_ICSELECTION_TRC)) #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ ((__MODE__) == TIM_ENCODERMODE_TI2) || \ ((__MODE__) == TIM_ENCODERMODE_TI12) || \ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4) || \ ((__CHANNEL__) == TIM_CHANNEL_5) || \ ((__CHANNEL__) == TIM_CHANNEL_6) || \ ((__CHANNEL__) == TIM_CHANNEL_ALL)) #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4)) #if defined(TIM5) && defined(TIM20) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #elif defined(TIM5) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #elif defined(TIM20) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #else #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #endif /* TIM5 && TIM20 */ #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ ((__STATE__) == TIM_OSSR_DISABLE)) #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ ((__STATE__) == TIM_OSSI_DISABLE)) #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ ((__LEVEL__) == TIM_LOCKLEVEL_3)) #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ ((__STATE__) == TIM_BREAK2_DISABLE)) #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ ((__SOURCE__) == TIM_TRGO_ENABLE) || \ ((__SOURCE__) == TIM_TRGO_UPDATE) || \ ((__SOURCE__) == TIM_TRGO_OC1) || \ ((__SOURCE__) == TIM_TRGO_OC1REF) || \ ((__SOURCE__) == TIM_TRGO_OC2REF) || \ ((__SOURCE__) == TIM_TRGO_OC3REF) || \ ((__SOURCE__) == TIM_TRGO_OC4REF) || \ ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ ((__SOURCE__) == TIM_TRGO2_OC1) || \ ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ ((__MODE__) == TIM_SLAVEMODE_RESET) || \ ((__MODE__) == TIM_SLAVEMODE_GATED) || \ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_INACTIVE) || \ ((__MODE__) == TIM_OCMODE_TOGGLE) || \ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) #if defined (TIM5) && defined(TIM20) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #elif defined (TIM5) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #elif defined (TIM20) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #else #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #endif /* TIM5 && TIM20 */ #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ (__HANDLE__)->ChannelState[5]) #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ (__HANDLE__)->ChannelState[0] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[1] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[2] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[3] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[4] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelState[5] = \ (__CHANNEL_STATE__); \ } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ (__HANDLE__)->ChannelNState[3]) #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ (__HANDLE__)->ChannelNState[0] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[1] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[2] = \ (__CHANNEL_STATE__); \ (__HANDLE__)->ChannelNState[3] = \ (__CHANNEL_STATE__); \ } while(0) /** * @} */ /* End of private macros -----------------------------------------------------*/ /* Include TIM HAL Extended module */ #include "stm32g4xx_hal_tim_ex.h" /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @{ */ /* Time Base functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @{ */ /* Timer Output Compare functions *********************************************/ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @{ */ /* Timer PWM functions ********************************************************/ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @{ */ /* Timer Input Capture functions **********************************************/ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @{ */ /* Timer One Pulse functions **************************************************/ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @{ */ /* Timer Encoder functions ****************************************************/ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief IRQ handler management * @{ */ /* Interrupt Handler functions ***********************************************/ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Control functions *********************************************************/ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @{ */ /* Callback in non blocking modes (Interrupt and DMA) *************************/ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief Peripheral State functions * @{ */ /* Peripheral State functions ************************************************/ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_TIM_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim_ex.h * @author MCD Application Team * @brief Header file of TIM HAL Extended module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_HAL_TIM_EX_H #define STM32G4xx_HAL_TIM_EX_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup TIMEx * @{ */ /* Exported types ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types * @{ */ /** * @brief TIM Hall sensor Configuration Structure definition */ typedef struct { uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; /** * @brief TIM Break/Break2 input configuration */ typedef struct { uint32_t Source; /*!< Specifies the source of the timer break input. This parameter can be a value of @ref TIMEx_Break_Input_Source */ uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ } TIMEx_BreakInputConfigTypeDef; /** * @brief TIM Encoder index configuration */ typedef struct { uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */ uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */ uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */ uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ } TIMEx_EncoderIndexConfigTypeDef; /** * @} */ /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants * @{ */ /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM1_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM1_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM1_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC1 analog watchdog 1 */ #define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC1 analog watchdog 2 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC1 analog watchdog 3 */ #if defined (ADC4) #define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 1 */ #define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC4 analog watchdog 2 */ #define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 3 */ #endif /* ADC4 */ #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ #define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ #define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM2_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM2_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM2_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/* !< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */ #define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */ #if defined (TIM5) #define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ #define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to LSE */ #define TIM_TIM3_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ #define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ #define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM3_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM3_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM3_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */ #define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */ #define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 1 */ #define TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC2 analog watchdog 2 */ #define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 3 */ #define TIM_TIM4_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ #define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ #define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM4_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM4_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM4_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */ #if defined (TIM5) #define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM5 ETR */ #endif /* TIM5 */ #if defined (TIM5) #define TIM_TIM5_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ #define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ #define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM5_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM5_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM5_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM5_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM5_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */ #define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM3 ETR */ #endif /* TIM5 */ #define TIM_TIM8_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ #define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ #define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM8_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM8_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM8_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC2 analog watchdog 1 */ #define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 2 */ #define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC2 analog watchdog 3 */ #if defined (ADC3) #define TIM_TIM8_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 1 */ #define TIM_TIM8_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC3 analog watchdog 2 */ #define TIM_TIM8_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 3 */ #endif /* ADC3 */ #if defined (TIM20) #define TIM_TIM20_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ #define TIM_TIM20_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ #define TIM_TIM20_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM20_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM20_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM20_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM20_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM20_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM20_ETR_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC3 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC3 analog watchdog 3 */ #if defined (ADC5) #define TIM_TIM20_ETR_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC5 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 3 */ #endif /* ADC5 */ #endif /* TIM20 */ /** * @} */ /** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ #define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ #define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ /** * @} */ /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP4 0x00000010U /* !< The COMP4 output is connected to the break input */ #if defined(COMP5) #define TIM_BREAKINPUTSOURCE_COMP5 0x00000020U /* !< The COMP5 output is connected to the break input */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_BREAKINPUTSOURCE_COMP6 0x00000040U /* !< The COMP6 output is connected to the break input */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_BREAKINPUTSOURCE_COMP7 0x00000080U /* !< The COMP7 output is connected to the break input */ #endif /* COMP7 */ /** * @} */ /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ #define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ #define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ /** * @} */ /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ #define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ /** * @} */ /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection * @{ */ #define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */ #define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */ #define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */ #define TIM_TIM1_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */ #define TIM_TIM1_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */ #define TIM_TIM2_TI1_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */ #define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */ #define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */ #define TIM_TIM2_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */ #define TIM_TIM2_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM2_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #define TIM_TIM2_TI2_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */ #define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */ #define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */ #define TIM_TIM2_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */ #define TIM_TIM2_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */ #if defined (COMP6) #define TIM_TIM2_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #define TIM_TIM2_TI3_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */ #define TIM_TIM2_TI3_COMP4 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */ #define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */ #define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */ #define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */ #define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */ #define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */ #define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */ #define TIM_TIM3_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */ #define TIM_TIM3_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM3_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM3_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM3_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM3_TI2_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */ #define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */ #define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */ #define TIM_TIM3_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */ #define TIM_TIM3_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM3_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM3_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM3_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM3_TI3_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */ #define TIM_TIM3_TI3_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */ #define TIM_TIM4_TI1_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */ #define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */ #define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */ #define TIM_TIM4_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */ #define TIM_TIM4_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM4_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM4_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM4_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM4_TI2_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */ #define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */ #define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */ #define TIM_TIM4_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */ #define TIM_TIM4_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */ #if defined (COMP5) #define TIM_TIM4_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined (COMP6) #define TIM_TIM4_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined (COMP7) #define TIM_TIM4_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM4_TI3_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */ #if defined (COMP5) #define TIM_TIM4_TI3_COMP5 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */ #endif /* COMP5 */ #define TIM_TIM4_TI4_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */ #if defined (COMP6) #define TIM_TIM4_TI4_COMP6 TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(TIM5) #define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */ #define TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */ #define TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */ #define TIM_TIM5_TI1_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */ #define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */ #define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */ #define TIM_TIM5_TI1_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */ #define TIM_TIM5_TI1_COMP4 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM5_TI1_COMP5 TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM5_TI1_COMP6 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM5_TI1_COMP7 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM5_TI2_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */ #define TIM_TIM5_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */ #define TIM_TIM5_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */ #define TIM_TIM5_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */ #define TIM_TIM5_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */ #if defined(COMP5) #define TIM_TIM5_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP6) #define TIM_TIM5_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM5_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #endif /* TIM5 */ #define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */ #define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */ #define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */ #define TIM_TIM8_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */ #define TIM_TIM8_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */ #define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */ #define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */ #define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */ #define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */ #if defined (COMP5) #define TIM_TIM15_TI1_COMP5 TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #if defined(COMP7) #define TIM_TIM15_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */ #define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */ #define TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */ #if defined (COMP6) #define TIM_TIM15_TI2_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */ #endif /* COMP6 */ #if defined(COMP7) #define TIM_TIM15_TI2_COMP7 TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */ #endif /* COMP7 */ #define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */ #if defined (COMP6) #define TIM_TIM16_TI1_COMP6 TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */ #endif /* COMP6 */ #define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */ #define TIM_TIM16_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */ #define TIM_TIM16_TI1_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */ #define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */ #define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */ #define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */ #if defined (COMP5) #define TIM_TIM17_TI1_COMP5 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */ #endif /* COMP5 */ #define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */ #define TIM_TIM17_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */ #define TIM_TIM17_TI1_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */ #define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */ #define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */ #if defined (TIM20) #define TIM_TIM20_TI1_GPIO 0x00000000U /*!< TIM20 input 1 is connected to GPIO */ #define TIM_TIM20_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */ #define TIM_TIM20_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */ #define TIM_TIM20_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */ #define TIM_TIM20_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */ #endif /* TIM20 */ /** * @} */ /** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling * @{ */ #define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */ #define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position * @{ */ #define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */ #define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */ #define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */ #define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */ #define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */ #define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction * @{ */ #define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */ #define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */ #define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity * @{ */ #define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ /** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler * @{ */ #define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ /** * @} */ /** * @} */ /* End of exported constants -------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros * @{ */ /** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __CNTCLK__ counter clock frequency (in Hz) * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __FREQ__ output signal frequency (in Hz) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U /** * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required * output signal frequency. * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __FREQ__ output signal frequency (in Hz) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) */ #define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U /** * @brief HELPER macro calculating the compare value required to achieve the required timer output compare * active/inactive delay. * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @retval Compare value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer * output compare active/inactive delay. * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @retval Compare value (between Min_Data=0 and Max_Data=65519) */ #define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration * (when the timer operates in one pulse mode). * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @param __PULSE__ pulse duration (in us) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \ + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required * pulse duration (when the timer operates in one pulse mode). * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) * @param __PULSE__ pulse duration (in us) * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) */ #define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @} */ /* End of exported macro -----------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros * @{ */ #define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) #if defined (COMP5) && defined (COMP6) && defined (COMP7) #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP5) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP6) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP7)) #else #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4)) #endif /* COMP5 && COMP6 && COMP7 */ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) #define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) #define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) #if defined(TIM5) && defined(TIM20) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ || \ (((INSTANCE) == TIM20) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR10)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE)))) #elif defined(TIM5) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) #elif defined(TIM20) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM20) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR9) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM20) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) #else #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ ((__SELECTION__) == TIM_TS_TI1FP1) || \ ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ (((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM3) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_NONE)))) #endif /* TIM5 && TIM20 */ #define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ (IS_TIM_OC_MODE(__MODE__) \ && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1))) #define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_3) || \ ((__CHANNEL__) == TIM_CHANNEL_4)) #define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE) #define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU) #define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U) #define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \ || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX)) #define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \ ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED)) #define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \ ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8)) #define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL) #define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \ ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1)) #define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \ ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN)) /** * @} */ /* End of private macro ------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @{ */ /* Timer Hall Sensor functions **********************************************/ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @{ */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @{ */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @{ */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @{ */ /* Extended Control functions ************************************************/ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth); HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source); HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime); HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime); HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig); HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @{ */ /* Extended Callback **********************************************************/ void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); /** * @} */ /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @{ */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ /** * @} */ /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ /** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); /** * @} */ /* End of private functions --------------------------------------------------*/ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_TIM_EX_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h ================================================ /** ****************************************************************************** * @file stm32g4xx_ll_adc.h * @author MCD Application Team * @brief Header file of ADC LL module. ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32G4xx_LL_ADC_H #define STM32G4xx_LL_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx.h" /** @addtogroup STM32G4xx_LL_Driver * @{ */ #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) /** @defgroup ADC_LL ADC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Constants ADC Private Constants * @{ */ /* Internal mask for ADC group regular sequencer: */ /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ /* - sequencer register offset */ /* - sequencer rank bits position into the selected register */ /* Internal register offset for ADC group regular sequencer configuration */ /* (offset placed into a spare area of literal definition) */ #define ADC_SQR1_REGOFFSET (0x00000000UL) #define ADC_SQR2_REGOFFSET (0x00000100UL) #define ADC_SQR3_REGOFFSET (0x00000200UL) #define ADC_SQR4_REGOFFSET (0x00000300UL) #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos) #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos) #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos) #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos) #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos) #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos) #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos) #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos) #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos) #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos) #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos) #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos) #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos) #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos) #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos) #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos) /* Internal mask for ADC group injected sequencer: */ /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ /* - data register offset */ /* - sequencer rank bits position into the selected register */ /* Internal register offset for ADC group injected data register */ /* (offset placed into a spare area of literal definition) */ #define ADC_JDR1_REGOFFSET (0x00000000UL) #define ADC_JDR2_REGOFFSET (0x00000100UL) #define ADC_JDR3_REGOFFSET (0x00000200UL) #define ADC_JDR4_REGOFFSET (0x00000300UL) #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ /* Definition of ADC group injected sequencer bits information to be inserted */ /* into ADC group injected sequencer ranks literals definition. */ #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos) #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos) #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos) #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos) /* Internal mask for ADC group regular trigger: */ /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ /* - regular trigger edge */ #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \ ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \ ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \ ((ADC_CFGR_EXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos) #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos) /* Internal mask for ADC group injected trigger: */ /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ /* - injected trigger source */ /* - injected trigger edge */ #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group injected trigger bits information. */ #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos) #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos) /* Internal mask for ADC channel: */ /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ /* - channel identifier defined by number */ /* - channel identifier defined by bitfield */ /* - channel differentiation between external channels (connected to */ /* GPIO pins) and internal channels (connected to internal paths) */ /* - channel sampling time defined by SMPRx register offset */ /* and SMPx bits positions into SMPRx register */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos) #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ /* Channel differentiation between external and internal channels */ #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /* Internal register offset for ADC channel sampling time configuration */ /* (offset placed into a spare area of literal definition) */ #define ADC_SMPR1_REGOFFSET (0x00000000UL) #define ADC_SMPR2_REGOFFSET (0x02000000UL) #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */ #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL) #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */ /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_NUMBER (0x00000000UL) #define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2) #define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3) #define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2) #define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) #define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \ ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4) #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1) /* Definition of channels ID bitfield information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0) #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1) #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2) #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3) #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4) #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5) #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6) #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7) #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8) #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9) #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10) #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11) #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12) #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13) #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14) #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15) #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16) #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17) #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18) /* Definition of channels sampling time information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */ #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */ #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */ #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */ #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */ #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */ #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */ #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */ #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */ #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */ #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */ #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */ #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */ #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */ #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */ #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */ #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */ #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */ #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */ /* Internal mask for ADC mode single or differential ended: */ /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */ /* the relevant bits for: */ /* (concatenation of multiple bits used in different registers) */ /* - ADC calibration: calibration start, calibration factor get or set */ /* - ADC channels: set each ADC channel ending mode */ #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF) #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S) #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */ #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */ #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */ #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */ #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */ /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ /* (concatenation of multiple bits used in different analog watchdogs, */ /* (feature of several watchdogs not available on all STM32 families)). */ /* - analog watchdog 1: monitored channel defined by number, */ /* selection of ADC group (ADC groups regular and-or injected). */ /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ /* selection on groups. */ /* Internal register offset for ADC analog watchdog channel configuration */ #define ADC_AWD_CR1_REGOFFSET (0x00000000UL) #define ADC_AWD_CR2_REGOFFSET (0x00100000UL) #define ADC_AWD_CR3_REGOFFSET (0x00200000UL) /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ /* Internal register offset for ADC analog watchdog threshold configuration */ #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ /* Internal mask for ADC offset: */ /* Internal register offset for ADC offset number configuration */ #define ADC_OFR1_REGOFFSET (0x00000000UL) #define ADC_OFR2_REGOFFSET (0x00000001UL) #define ADC_OFR3_REGOFFSET (0x00000002UL) #define ADC_OFR4_REGOFFSET (0x00000003UL) #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \ | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) /* ADC registers bits positions */ #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos) #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos) #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos) #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos) #define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos) /* ADC registers bits groups */ #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Macros ADC Private Macros * @{ */ /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure * @{ */ /** * @brief Structure definition of some features of ADC common parameters * and multimode * (all ADC instances belonging to the same ADC common instance). * @note The setting of these parameters by function @ref LL_ADC_CommonInit() * is conditioned to ADC instances state (all ADC instances * sharing the same ADC common instance): * All ADC instances sharing the same ADC common instance must be * disabled. */ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE @note On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ #if defined(ADC_MULTIMODE_SUPPORT) uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ #endif /* ADC_MULTIMODE_SUPPORT */ } LL_ADC_CommonInitTypeDef; /** * @brief Structure definition of some features of ADC instance. * @note These parameters have an impact on ADC scope: ADC instance. * Affects both group regular and group injected (availability * of ADC group injected depends on STM32 families). * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Instance . * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 families. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. */ typedef struct { uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ uint32_t DataAlignment; /*!< Set ADC conversion data alignment. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ uint32_t LowPowerMode; /*!< Set ADC low power mode. This parameter can be a value of @ref ADC_LL_EC_LP_MODE This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ } LL_ADC_InitTypeDef; /** * @brief Structure definition of some features of ADC group regular. * @note These parameters have an impact on ADC scope: ADC group regular. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "REG"). * @note The setting of these parameters by function @ref LL_ADC_REG_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 families. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. */ typedef struct { uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE @note This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more). This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: data preserved or overwritten. This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ } LL_ADC_REG_InitTypeDef; /** * @brief Structure definition of some features of ADC group injected. * @note These parameters have an impact on ADC scope: ADC group injected. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "INJ"). * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 families. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. */ typedef struct { uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE @note This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more). This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ } LL_ADC_INJ_InitTypeDef; /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants * @{ */ /** @defgroup ADC_LL_EC_FLAG ADC flags * @brief Flags defines which can be used with LL_ADC_ReadReg function * @{ */ #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */ #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */ #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */ #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */ #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */ #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */ #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */ #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */ #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */ #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */ #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */ #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */ #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */ #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */ #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */ #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */ #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */ #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */ #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */ #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions * @{ */ #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */ #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */ #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */ #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ /** * @} */ /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose * @{ */ /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */ #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */ #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */ #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */ #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */ #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */ #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */ #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */ #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */ #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */ /** * @} */ /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels * @{ */ /* Note: Other measurement paths to internal channels may be available */ /* (connections to other peripherals). */ /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */ /** * @} */ /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution * @{ */ #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */ #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */ #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */ /** * @} */ /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number * @{ */ #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state * @{ */ #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */ #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign * @{ */ #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */ #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */ /** * @} */ /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode * @{ */ #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */ #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */ /** * @} */ /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/ #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */ /** * @} */ /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number * @{ */ #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ #define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ #define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ #define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ #define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ /** * @} */ /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** * @} */ /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge * @{ */ #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode * @{ */ #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */ #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */ #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: Trigger rising edge = start sampling Trigger falling edge = stop sampling and start conversion */ /** * @} */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** * @} */ /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ #if defined(ADC_SMPR1_SMPPLUS) /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration * @{ */ #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */ #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */ /** * @} */ #endif /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ /** * @} */ /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source * @{ */ #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */ #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge * @{ */ #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode * @{ */ #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode * @{ */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */ #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */ #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length * @{ */ #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode * @{ */ #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */ #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ /** * @} */ /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks * @{ */ #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */ #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */ #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */ #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */ /** * @} */ /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */ #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */ /** * @} */ /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending * @{ */ #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number * @{ */ #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group regular only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group injected only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by either group regular or injected */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group regular only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group injected only */ #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */ #define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */ #define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */ #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds * @{ */ #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */ #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ /** * @} */ /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config * @{ */ #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */ #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */ #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */ #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ /** * @} */ /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ /** * @} */ #if defined(ADC_MULTIMODE_SUPPORT) /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode * @{ */ #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */ #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */ #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ /** * @} */ /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer * @{ */ #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */ #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */ /** * @} */ /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases * @{ */ #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ /** * @} */ /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave * @{ */ #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ /** * @} */ #endif /* ADC_MULTIMODE_SUPPORT */ /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. * @{ */ /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values. */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Indications for estimation of ADC timeout delays, for this */ /* STM32 series: */ /* - ADC calibration time: maximum delay is 112/fADC. */ /* (refer to device datasheet, parameter "tCAL") */ /* - ADC enable time: maximum delay is 1 conversion cycle. */ /* (refer to device datasheet, parameter "tSTAB") */ /* - ADC disable time: maximum delay should be a few ADC clock cycles */ /* - ADC stop conversion time: maximum delay should be a few ADC clock */ /* cycles */ /* - ADC conversion time: duration depending on ADC clock and ADC */ /* configuration. */ /* (refer to device reference manual, section "Timing") */ /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 series, a minimum number of ADC clock cycles */ /* are required between ADC end of calibration and ADC enable. */ /* Wait time can be computed in user application by waiting for the */ /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros * @{ */ /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros * @{ */ /** * @brief Write a value in ADC register * @param __INSTANCE__ ADC Instance * @param __REG__ Register to be written * @param __VALUE__ Value to be written in the register * @retval None */ #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) /** * @brief Read a value in ADC register * @param __INSTANCE__ ADC Instance * @param __REG__ Register to be read * @retval Register value */ #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) /** * @} */ /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro * @{ */ /** * @brief Helper macro to get ADC channel number in decimal format * from literals LL_ADC_CHANNEL_x. * @note Example: * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) * will return decimal number "4". * @note The input can be a value from functions where a channel * number is returned, either defined with number * or with bitfield (only one bit must be set). * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ ) \ : \ ( \ (uint32_t)POSITION_VAL((__CHANNEL__)) \ ) \ ) /** * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x * from number in decimal format. * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) <= 9UL) ? \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ : \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ ) \ ) /** * @brief Helper macro to determine whether the selected channel * corresponds to literal definitions of driver. * @note The different literal definitions of ADC channels are: * - ADC internal channel: * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... * - ADC external channel (channel connected to a GPIO pin): * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... * @note The channel parameter must be a value defined from literal * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, * LL_ADC_CHANNEL_TEMPSENSOR, ...), * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), * must not be a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) /** * @brief Helper macro to convert a channel defined from parameter * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, * LL_ADC_CHANNEL_TEMPSENSOR, ...), * to its equivalent parameter definition of a ADC external channel * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). * @note The channel parameter can be, additionally to a value * defined from parameter definition of a ADC internal channel * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), * a value defined from parameter definition of * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) * or a value from functions where a channel number is returned * from ADC registers. * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 * @arg @ref LL_ADC_CHANNEL_4 * @arg @ref LL_ADC_CHANNEL_5 * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 */ #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) /** * @brief Helper macro to determine whether the internal channel * selected is available on the ADC instance selected. * @note The channel parameter must be a value defined from parameter * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, * LL_ADC_CHANNEL_TEMPSENSOR, ...), * must not be a value defined from parameter definition of * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) * or a value from functions where a channel number is * returned from ADC registers, * because internal and external channels share the same channel * number in ADC registers. The differentiation is made only with * parameters definitions of driver. * @param __ADC_INSTANCE__ ADC instance * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC3) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC4) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC5) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ ) #elif defined(STM32G471xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC3) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC2) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ ) \ ) \ || \ (((__ADC_INSTANCE__) == ADC3) \ &&( \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ ) \ ) \ ) #endif /** * @brief Helper macro to define ADC analog watchdog parameter: * define a single channel to monitor with analog watchdog * from sequencer channel and groups definition. * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). * Example: * LL_ADC_SetAnalogWDMonitChannels( * ADC1, LL_ADC_AWD1, * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) * @param __CHANNEL__ This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). * @param __GROUP__ This parameter can be one of the following values: * @arg @ref LL_ADC_GROUP_REGULAR * @arg @ref LL_ADC_GROUP_INJECTED * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4) * * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ : \ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ : \ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ ) /** * @brief Helper macro to set the value of ADC analog watchdog threshold high * or low in function of ADC resolution, when ADC resolution is * different of 12 bits. * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() * or @ref LL_ADC_SetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to set the value of * analog watchdog threshold high (on 8 bits): * LL_ADC_SetAnalogWDThresholds * (< ADCx param >, * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) * ); * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) /** * @brief Helper macro to get the value of ADC analog watchdog threshold high * or low in function of ADC resolution, when ADC resolution is * different of 12 bits. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to get the value of * analog watchdog threshold high (on 8 bits): * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION * (LL_ADC_RESOLUTION_8B, * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) * ); * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U ))) /** * @brief Helper macro to get the ADC analog watchdog threshold high * or low from raw value containing both thresholds concatenated. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, to get analog watchdog threshold high from the register raw value: * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) /** * @brief Helper macro to set the ADC calibration value with both single ended * and differential modes calibration factors concatenated. * @note To be used with function @ref LL_ADC_SetCalibrationFactor(). * Example, to set calibration factors single ended to 0x55 * and differential ended to 0x2A: * LL_ADC_SetCalibrationFactor( * ADC1, * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A)) * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \ (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__)) #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Helper macro to get the ADC multimode conversion data of ADC master * or ADC slave from raw value with both ADC conversion data concatenated. * @note This macro is intended to be used when multimode transfer by DMA * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). * In this case the transferred data need to processed with this macro * to separate the conversion data of ADC master and ADC slave. * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_MASTER * @arg @ref LL_ADC_MULTI_SLAVE * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) #endif /* ADC_MULTIMODE_SUPPORT */ #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Helper macro to select, from a ADC instance, to which ADC instance * it has a dependence in multimode (ADC master of the corresponding * ADC common instance). * @note In case of device with multimode available and a mix of * ADC instances compliant and not compliant with multimode feature, * ADC instances not compliant with multimode feature are * considered as master instances (do not depend to * any other ADC instance). * @param __ADCx__ ADC instance * @retval __ADCx__ ADC instance master of the corresponding ADC common instance */ #if defined(ADC5) #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ ( ( ((__ADCx__) == ADC2) \ )? \ (ADC1) \ : \ ( ( ((__ADCx__) == ADC4) \ )? \ (ADC3) \ : \ (__ADCx__) \ ) \ ) #else #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \ ( ( ((__ADCx__) == ADC2) \ )? \ (ADC1) \ : \ (__ADCx__) \ ) #endif /* ADC5 */ #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance * to which is belonging the selected ADC instance. * @note ADC common register instance can be used for: * - Set parameters common to several ADC instances * - Multimode (for devices with several ADC instances) * Refer to functions having argument "ADCxy_COMMON" as parameter. * @param __ADCx__ ADC instance * @retval ADC common register instance */ #if defined(ADC345_COMMON) #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ ? ( \ (ADC12_COMMON) \ ) \ : \ ( \ (ADC345_COMMON) \ ) \ ) #else #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON) #endif /* ADC345_COMMON */ /** * @brief Helper macro to check if all ADC instances sharing the same * ADC common instance are disabled. * @note This check is required by functions with setting conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * Refer to functions having argument "ADCxy_COMMON" as parameter. * @note On devices with only 1 ADC common instance, parameter of this macro * is useless and can be ignored (parameter kept for compatibility * with devices featuring several ADC common instances). * @param __ADCXY_COMMON__ ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Value "0" if all ADC instances sharing the same ADC common instance * are disabled. * Value "1" if at least one ADC instance sharing the same ADC common instance * is enabled. */ #if defined(ADC345_COMMON) #if defined(ADC4) && defined(ADC5) #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (((__ADCXY_COMMON__) == ADC12_COMMON) \ ? ( \ (LL_ADC_IsEnabled(ADC1) | \ LL_ADC_IsEnabled(ADC2) ) \ ) \ : \ ( \ (LL_ADC_IsEnabled(ADC3) | \ LL_ADC_IsEnabled(ADC4) | \ LL_ADC_IsEnabled(ADC5) ) \ ) \ ) #else #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (((__ADCXY_COMMON__) == ADC12_COMMON) \ ? ( \ (LL_ADC_IsEnabled(ADC1) | \ LL_ADC_IsEnabled(ADC2) ) \ ) \ : \ (LL_ADC_IsEnabled(ADC3)) \ ) #endif /* ADC4 && ADC5 */ #else #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2)) #endif /** * @brief Helper macro to define the ADC conversion data full-scale digital * value corresponding to the selected ADC resolution. * @note ADC conversion data full-scale corresponds to voltage range * determined by analog voltage references Vref+ and Vref- * (refer to reference manual). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) */ #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data to the requested resolution */ #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ (((__DATA__) \ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ ) /** * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ ) /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage * reference VrefInt. * @note Computation is using VrefInt calibration value * stored in system memory for each device during production. * @note This voltage depends on user board environment: voltage level * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval Analog reference voltage (unit: mV) */ #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ (__ADC_RESOLUTION__), \ LL_ADC_RESOLUTION_12B) \ ) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor calibration values * stored in system memory for each device during production. * @note Calculation formula: * Temperature = ((TS_ADC_DATA - TS_CAL1) * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * Avg_Slope = (TS_CAL2 - TS_CAL1) * / (TS_CAL2_TEMP - TS_CAL1_TEMP) * TS_CAL1 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL1 (calibrated in factory) * TS_CAL2 = equivalent TS_ADC_DATA at temperature * TEMP_DEGC_CAL2 (calibrated in factory) * Caution: Calculation relevancy under reserve that calibration * parameters are correct (address and data). * To calculate temperature using temperature sensor * datasheet typical values (generic values less, therefore * less accurate than calibrated values), * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal * temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature * sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) */ #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ (__ADC_RESOLUTION__), \ LL_ADC_RESOLUTION_12B) \ * (__VREFANALOG_VOLTAGE__)) \ / TEMPSENSOR_CAL_VREFANALOG) \ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ ) + TEMPSENSOR_CAL1_TEMP \ ) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) * from ADC conversion data of internal temperature sensor. * @note Computation is using temperature sensor typical values * (refer to device datasheet). * @note Calculation formula: * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) * / Avg_Slope + CALx_TEMP * with TS_ADC_DATA = temperature sensor raw data measured by ADC * (unit: digital value) * Avg_Slope = temperature sensor slope * (unit: uV/Degree Celsius) * TS_TYP_CALx_VOLT = temperature sensor digital value at * temperature CALx_TEMP (unit: mV) * Caution: Calculation relevancy under reserve the temperature sensor * of the current device has characteristics in line with * datasheet typical values. * If temperature sensor calibration values are available on * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), * temperature calculation will be more accurate using * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). * @note As calculation input, the analog reference voltage (Vref+) must be * defined as it impacts the ADC LSB equivalent voltage. * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @note ADC measurement data must correspond to a resolution of 12 bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). * On STM32G4, refer to device datasheet parameter "Avg_Slope". * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval Temperature (unit: degree Celsius) */ #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ __TEMPSENSOR_TYP_CALX_V__,\ __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ * 1000UL) \ - \ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ * 1000UL) \ ) \ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ ) /** * @} */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management * @{ */ /* Note: LL ADC functions to set DMA transfer are located into sections of */ /* configuration of ADC instance, groups and multimode (if available): */ /* @ref LL_ADC_REG_SetDMATransfer(), ... */ /** * @brief Function to help to configure DMA transfer from ADC: retrieve the * ADC register address from ADC instance and a list of ADC registers * intended to be used (most commonly) with DMA transfer. * @note These ADC registers are data registers: * when ADC conversion data is available in ADC data registers, * ADC generates a DMA transfer request. * @note This macro is intended to be used with LL DMA driver, refer to * function "LL_DMA_ConfigAddresses()". * Example: * LL_DMA_ConfigAddresses(DMA1, * LL_DMA_CHANNEL_1, * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), * (uint32_t)&< array or variable >, * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); * @note For devices with several ADC: in multimode, some devices * use a different data register outside of ADC instance scope * (common data register). This macro manages this register difference, * only ADC instance has to be set as parameter. * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr * @param ADCx ADC instance * @param Register This parameter can be one of the following values: * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) * * (1) Available on devices with several ADC instances. * @retval ADC register address */ #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { /* Retrieve address of register DR */ data_reg_addr = (uint32_t) &(ADCx->DR); } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ { /* Retrieve address of register CDR */ data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); } return data_reg_addr; } #else __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { /* Prevent unused argument(s) compilation warning */ (void)(Register); /* Retrieve address of register DR */ return (uint32_t) &(ADCx->DR); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances * @{ */ /** * @brief Set parameter common to several ADC: Clock source and prescaler. * @note On this STM32 series, if ADC group injected is used, some * clock ratio constraints between ADC clock and AHB clock * must be respected. * Refer to reference manual. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n * CCR PRESC LL_ADC_SetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param CommonClock This parameter can be one of the following values: * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); } /** * @brief Get parameter common to several ADC: Clock source and prescaler. * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n * CCR PRESC LL_ADC_GetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); } /** * @brief Set parameter common to several ADC: measurement path to * internal channels (VrefInt, temperature sensor, ...). * Configure all paths (overwrite current configuration). * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * The values not selected are removed from configuration. * @note Stabilization time of measurement path to internal channel: * After enabling internal paths, before starting ADC conversion, * a delay is required for internal voltage reference and * temperature sensor stabilization time. * Refer to device datasheet. * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. * @note ADC internal channel sampling time constraint: * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n * CCR VBATSEL LL_ADC_SetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param PathInternal This parameter can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); } /** * @brief Set parameter common to several ADC: measurement path to * internal channels (VrefInt, temperature sensor, ...). * Add paths to the current configuration. * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * @note Stabilization time of measurement path to internal channel: * After enabling internal paths, before starting ADC conversion, * a delay is required for internal voltage reference and * temperature sensor stabilization time. * Refer to device datasheet. * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. * @note ADC internal channel sampling time constraint: * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param PathInternal This parameter can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { SET_BIT(ADCxy_COMMON->CCR, PathInternal); } /** * @brief Set parameter common to several ADC: measurement path to * internal channels (VrefInt, temperature sensor, ...). * Remove paths to the current configuration. * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param PathInternal This parameter can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); } /** * @brief Get parameter common to several ADC: measurement path to internal * channels (VrefInt, temperature sensor, ...). * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n * CCR VBATSEL LL_ADC_GetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be a combination of the following values: * @arg @ref LL_ADC_PATH_INTERNAL_NONE * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance * @{ */ /** * @brief Set ADC calibration factor in the mode single-ended * or differential (for devices with differential mode available). * @note This function is intended to set calibration parameters * without having to perform a new calibration using * @ref LL_ADC_StartCalibration(). * @note For devices with differential mode available: * Calibration of offset is specific to each of * single-ended and differential modes * (calibration factor must be specified for each of these * differential modes, if used afterwards and if the application * requires their calibration). * @note In case of setting calibration factors of both modes single ended * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED): * both calibration factors must be concatenated. * To perform this processing, use helper macro * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F * @retval None */ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor) { MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); } /** * @brief Get ADC calibration factor in the mode single-ended * or differential (for devices with differential mode available). * @note Calibration factors are set by hardware after performing * a calibration run using function @ref LL_ADC_StartCalibration(). * @note For devices with differential mode available: * Calibration of offset is specific to each of * single-ended and differential modes * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Retrieve bits with position in register depending on parameter */ /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); } /** * @brief Set ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR RES LL_ADC_SetResolution * @param ADCx ADC instance * @param Resolution This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B * @retval None */ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); } /** * @brief Get ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @rmtoll CFGR RES LL_ADC_GetResolution * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B */ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); } /** * @brief Set ADC conversion data alignment. * @note Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment * @param ADCx ADC instance * @param DataAlignment This parameter can be one of the following values: * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT * @retval None */ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment); } /** * @brief Get ADC conversion data alignment. * @note Refer to reference manual for alignments formats * dependencies to ADC resolutions. * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT */ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN)); } /** * @brief Set ADC low power mode. * @note Description of ADC low power modes: * - ADC low power mode "auto wait": Dynamic low power mode, * ADC conversions occurrences are limited to the minimum necessary * in order to reduce power consumption. * New ADC conversion starts only when the previous * unitary conversion data (for ADC group regular) * or previous sequence conversions data (for ADC group injected) * has been retrieved by user software. * In the meantime, ADC remains idle: does not performs any * other conversion. * This mode allows to automatically adapt the ADC conversions * triggers to the speed of the software that reads the data. * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: * - It is not recommended to use with interruption or DMA * since these modes have to clear immediately the EOC flag * (by CPU to free the IRQ pending event or by DMA). * Auto wait will work but fort a very short time, discarding * its intended benefit (except specific case of high load of CPU * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and * retrieve ADC conversion data. This will trig another * ADC conversion start. * - ADC low power mode "auto power-off" (feature available on * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): * the ADC automatically powers-off after a conversion and * automatically wakes up when a new conversion is triggered * (with startup time between trigger and start of sampling). * This feature can be combined with low power mode "auto wait". * @note With ADC low power mode "auto wait", the ADC conversion data read * is corresponding to previous ADC conversion start, independently * of delay during which ADC was idle. * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode * @param ADCx ADC instance * @param LowPowerMode This parameter can be one of the following values: * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT * @retval None */ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode); } /** * @brief Get ADC low power mode: * @note Description of ADC low power modes: * - ADC low power mode "auto wait": Dynamic low power mode, * ADC conversions occurrences are limited to the minimum necessary * in order to reduce power consumption. * New ADC conversion starts only when the previous * unitary conversion data (for ADC group regular) * or previous sequence conversions data (for ADC group injected) * has been retrieved by user software. * In the meantime, ADC remains idle: does not performs any * other conversion. * This mode allows to automatically adapt the ADC conversions * triggers to the speed of the software that reads the data. * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: * - It is not recommended to use with interruption or DMA * since these modes have to clear immediately the EOC flag * (by CPU to free the IRQ pending event or by DMA). * Auto wait will work but fort a very short time, discarding * its intended benefit (except specific case of high load of CPU * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and * retrieve ADC conversion data. This will trig another * ADC conversion start. * - ADC low power mode "auto power-off" (feature available on * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): * the ADC automatically powers-off after a conversion and * automatically wakes up when a new conversion is triggered * (with startup time between trigger and start of sampling). * This feature can be combined with low power mode "auto wait". * @note With ADC low power mode "auto wait", the ADC conversion data read * is corresponding to previous ADC conversion start, independently * of delay during which ADC was idle. * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); } /** * @brief Set ADC selected offset number 1, 2, 3 or 4. * @note This function set the 2 items of offset configuration: * - ADC channel to which the offset programmed will be applied * (independently of channel mapped on ADC group regular * or group injected) * - Offset level (offset to be subtracted from the raw * converted data). * @note Caution: Offset format is dependent to ADC resolution: * offset has to be left-aligned on bit 11, the LSB (right bits) * are set to 0. * @note This function enables the offset, by default. It can be forced * to disable state using function LL_ADC_SetOffsetState(). * @note If a channel is mapped on several offsets numbers, only the offset * with the lowest value is considered for the subtraction. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n * OFR1 OFFSET1 LL_ADC_SetOffset\n * OFR1 OFFSET1_EN LL_ADC_SetOffset\n * OFR2 OFFSET2_CH LL_ADC_SetOffset\n * OFR2 OFFSET2 LL_ADC_SetOffset\n * OFR2 OFFSET2_EN LL_ADC_SetOffset\n * OFR3 OFFSET3_CH LL_ADC_SetOffset\n * OFR3 OFFSET3 LL_ADC_SetOffset\n * OFR3 OFFSET3_EN LL_ADC_SetOffset\n * OFR4 OFFSET4_CH LL_ADC_SetOffset\n * OFR4 OFFSET4 LL_ADC_SetOffset\n * OFR4 OFFSET4_EN LL_ADC_SetOffset * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } /** * @brief Get for the ADC selected offset number 1, 2, 3 or 4: * Channel to which the offset programmed will be applied * (independently of channel mapped on ADC group regular * or group injected) * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } /** * @brief Get for the ADC selected offset number 1, 2, 3 or 4: * Offset level (offset to be subtracted from the raw * converted data). * @note Caution: Offset format is dependent to ADC resolution: * offset has to be left-aligned on bit 11, the LSB (right bits) * are set to 0. * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n * OFR4 OFFSET4 LL_ADC_GetOffsetLevel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * force offset state disable or enable * without modifying offset channel or offset value. * @note This function should be needed only in case of offset to be * enabled-disabled dynamically, and should not be needed in other cases: * function LL_ADC_SetOffset() automatically enables the offset. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n * OFR4 OFFSET4_EN LL_ADC_SetOffsetState * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param OffsetState This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, OffsetState); } /** * @brief Get for the ADC selected offset number 1, 2, 3 or 4: * offset state disabled or enabled. * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n * OFR4 OFFSET4_EN LL_ADC_GetOffsetState * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset sign. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_SetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param OffsetSign This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, OffsetSign); } /** * @brief Get for the ADC selected offset number 1, 2, 3 or 4: * offset sign if positive or negative. * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_GetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS); } /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset saturation mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n * OFR2 SATEN LL_ADC_SetOffsetSaturation\n * OFR3 SATEN LL_ADC_SetOffsetSaturation\n * OFR4 SATEN LL_ADC_SetOffsetSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @param OffsetSaturation This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_SATEN, OffsetSaturation); } /** * @brief Get for the ADC selected offset number 1, 2, 3 or 4: * offset saturation if enabled or disabled. * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n * OFR2 SATEN LL_ADC_GetOffsetSaturation\n * OFR3 SATEN LL_ADC_GetOffsetSaturation\n * OFR4 SATEN LL_ADC_GetOffsetSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: * @arg @ref LL_ADC_OFFSET_1 * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN); } /** * @brief Set ADC gain compensation. * @note This function set the gain compensation coefficient * that is applied to raw converted data using the formula: * DATA = DATA(raw) * (gain compensation coef) / 4096 * @note This function enables the gain compensation if given * coefficient is above 0, otherwise it disables it. * @note Gain compensation when enabled is applied to all channels. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n * CFGR2 GCOMP LL_ADC_SetGainCompensation * @param ADCx ADC instance * @param GainCompensation This parameter can be: * 0 Gain compensation will be disabled and value set to 0 * 1 -> 16393 Gain compensation will be enabled with specified value * @retval None */ __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation) { MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation); MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos); } /** * @brief Get the ADC gain compensation value * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n * CFGR2 GCOMP LL_ADC_GetGainCompensation * @param ADCx ADC instance * @retval Returned value can be: * 0 Gain compensation is disabled * 1 -> 16393 Gain compensation is enabled with returned value */ __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL); } #if defined(ADC_SMPR1_SMPPLUS) /** * @brief Set ADC sampling time common configuration impacting * settings of sampling time channel wise. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig * @param ADCx ADC instance * @param SamplingTimeCommonConfig This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) { MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); } /** * @brief Get ADC sampling time common configuration impacting * settings of sampling time channel wise. * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 */ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS)); } #endif /* ADC_SMPR1_SMPPLUS */ /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular * @{ */ /** * @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n * CFGR EXTEN LL_ADC_REG_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_SOFTWARE * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource); } /** * @brief Get ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note To determine whether group regular trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, * (equivalent to * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n * CFGR EXTEN LL_ADC_REG_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_SOFTWARE * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL) | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN) ); } /** * @brief Get ADC group regular conversion trigger source internal (SW start) * or external. * @note In case of group regular trigger source set to external trigger, * to determine which peripheral is selected as external trigger, * use function @ref LL_ADC_REG_GetTriggerSource(). * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } /** * @brief Set ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge * @param ADCx ADC instance * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_EXT_RISING * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge); } /** * @brief Get ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_TRIG_EXT_RISING * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } /** * @brief Set ADC sampling mode. * @note This function set the ADC conversion sampling mode * @note This mode applies to regular group only. * @note Set sampling mode is applied to all conversion of regular group. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode * @param ADCx ADC instance * @param SamplingMode This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode) { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode); } /** * @brief Get the ADC sampling mode * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG)); } /** * @brief Set ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: * - For devices with sequencer fully configurable * (function "LL_ADC_REG_SetSequencerRanks()" available): * sequencer length and each rank affectation to a channel * are configurable. * This function performs configuration of: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerRanks()". * - For devices with sequencer not fully configurable * (function "LL_ADC_REG_SetSequencerChannels()" available): * sequencer length and each rank affectation to a channel * are defined by channel number. * This function performs configuration of: * - Sequence length: Number of ranks in the scan sequence is * defined by number of channels set in the sequence, * rank of each channel is fixed by channel HW number. * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from lowest channel number to * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength * @param ADCx ADC instance * @param SequencerNbRanks This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) { MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); } /** * @brief Get ADC group regular sequencer length and scan direction. * @note Description of ADC group regular sequencer features: * - For devices with sequencer fully configurable * (function "LL_ADC_REG_SetSequencerRanks()" available): * sequencer length and each rank affectation to a channel * are configurable. * This function retrieves: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerRanks()". * - For devices with sequencer not fully configurable * (function "LL_ADC_REG_SetSequencerChannels()" available): * sequencer length and each rank affectation to a channel * are defined by channel number. * This function retrieves: * - Sequence length: Number of ranks in the scan sequence is * defined by number of channels set in the sequence, * rank of each channel is fixed by channel HW number. * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from lowest channel number to * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); } /** * @brief Set ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont * @param ADCx ADC instance * @param SeqDiscont This parameter can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont); } /** * @brief Get ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); } /** * @brief Set ADC group regular sequence: channel on the selected * scan sequence rank. * @note This function performs configuration of: * - Channels ordering into each rank of scan sequence: * whatever channel can be placed into whatever rank. * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_REG_RANK_1 * @arg @ref LL_ADC_REG_RANK_2 * @arg @ref LL_ADC_REG_RANK_3 * @arg @ref LL_ADC_REG_RANK_4 * @arg @ref LL_ADC_REG_RANK_5 * @arg @ref LL_ADC_REG_RANK_6 * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 * @arg @ref LL_ADC_REG_RANK_9 * @arg @ref LL_ADC_REG_RANK_10 * @arg @ref LL_ADC_REG_RANK_11 * @arg @ref LL_ADC_REG_RANK_12 * @arg @ref LL_ADC_REG_RANK_13 * @arg @ref LL_ADC_REG_RANK_14 * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** * @brief Get ADC group regular sequence: channel on the selected * scan sequence rank. * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_REG_RANK_1 * @arg @ref LL_ADC_REG_RANK_2 * @arg @ref LL_ADC_REG_RANK_3 * @arg @ref LL_ADC_REG_RANK_4 * @arg @ref LL_ADC_REG_RANK_5 * @arg @ref LL_ADC_REG_RANK_6 * @arg @ref LL_ADC_REG_RANK_7 * @arg @ref LL_ADC_REG_RANK_8 * @arg @ref LL_ADC_REG_RANK_9 * @arg @ref LL_ADC_REG_RANK_10 * @arg @ref LL_ADC_REG_RANK_11 * @arg @ref LL_ADC_REG_RANK_12 * @arg @ref LL_ADC_REG_RANK_13 * @arg @ref LL_ADC_REG_RANK_14 * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } /** * @brief Set ADC continuous conversion mode on ADC group regular. * @note Description of ADC continuous conversion mode: * - single mode: one conversion per trigger * - continuous mode: after the first trigger, following * conversions launched successively automatically. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode * @param ADCx ADC instance * @param Continuous This parameter can be one of the following values: * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous); } /** * @brief Get ADC continuous conversion mode on ADC group regular. * @note Description of ADC continuous conversion mode: * - single mode: one conversion per trigger * - continuous mode: after the first trigger, following * conversions launched successively automatically. * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); } /** * @brief Set ADC group regular conversion data transfer: no transfer or * transfer by DMA, and DMA requests mode. * @note If transfer by DMA selected, specifies the DMA requests * mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note For devices with several ADC instances: ADC multimode DMA * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n * CFGR DMACFG LL_ADC_REG_SetDMATransfer * @param ADCx ADC instance * @param DMATransfer This parameter can be one of the following values: * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer); } /** * @brief Get ADC group regular conversion data transfer: no transfer or * transfer by DMA, and DMA requests mode. * @note If transfer by DMA selected, specifies the DMA requests * mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note For devices with several ADC instances: ADC multimode DMA * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n * CFGR DMACFG LL_ADC_REG_GetDMATransfer * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED */ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG)); } /** * @brief Set ADC group regular behavior in case of overrun: * data preserved or overwritten. * @note Compatibility with devices without feature overrun: * other devices without this feature have a behavior * equivalent to data overwritten. * The default setting of overrun is data preserved. * Therefore, for compatibility with all devices, parameter * overrun should be set to data overwritten. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun * @param ADCx ADC instance * @param Overrun This parameter can be one of the following values: * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun); } /** * @brief Get ADC group regular behavior in case of overrun: * data preserved or overwritten. * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected * @{ */ /** * @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_INJ_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource); } /** * @brief Get ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). * @note To determine whether group injected trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, * (equivalent to * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL) | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN) ); } /** * @brief Get ADC group injected conversion trigger source internal (SW start) or external * @note In case of group injected trigger source set to external trigger, * to determine which peripheral is selected as external trigger, * use function @ref LL_ADC_INJ_GetTriggerSource. * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } /** * @brief Set ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge * @param ADCx ADC instance * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) { MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge); } /** * @brief Get ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } /** * @brief Set ADC group injected sequencer length and scan direction. * @note This function performs configuration of: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength * @param ADCx ADC instance * @param SequencerNbRanks This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) { MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); } /** * @brief Get ADC group injected sequencer length and scan direction. * @note This function retrieves: * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } /** * @brief Set ADC group injected sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont * @param ADCx ADC instance * @param SeqDiscont This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont); } /** * @brief Get ADC group injected sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); } /** * @brief Set ADC group injected sequence: channel on the selected * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { /* Set bits with content of parameter "Channel" with bits position */ /* in register depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ MODIFY_REG(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)); } /** * @brief Get ADC group injected sequence: channel on the selected * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } /** * @brief Set ADC group injected conversion trigger: * independent or from ADC group regular. * @note This mode can be used to extend number of data registers * updated after one ADC conversion trigger and with data * permanently kept (not erased by successive conversions of scan of * ADC sequencer ranks), up to 5 data registers: * 1 data register on ADC group regular, 4 data registers * on ADC group injected. * @note If ADC group injected injected trigger source is set to an * external trigger, this feature must be must be set to * independent trigger. * ADC group injected automatic trigger is compliant only with * group injected trigger source set to SW start, without any * further action on ADC group injected conversion start or stop: * in this case, ADC group injected is controlled only * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto * @param ADCx ADC instance * @param TrigAuto This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto); } /** * @brief Get ADC group injected conversion trigger: * independent or from ADC group regular. * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); } /** * @brief Set ADC group injected contexts queue mode. * @note A context is a setting of group injected sequencer: * - group injected trigger * - sequencer length * - sequencer ranks * If contexts queue is disabled: * - only 1 sequence can be configured * and is active perpetually. * If contexts queue is enabled: * - up to 2 contexts can be queued * and are checked in and out as a FIFO stack (first-in, first-out). * - If a new context is set when queues is full, error is triggered * by interruption "Injected Queue Overflow". * - Two behaviors are possible when all contexts have been processed: * the contexts queue can maintain the last context active perpetually * or can be empty and injected group triggers are disabled. * - Triggers can be only external (not internal SW start) * - Caution: The sequence must be fully configured in one time * (one write of register JSQR makes a check-in of a new context * into the queue). * Therefore functions to set separately injected trigger and * sequencer channels cannot be used, register JSQR must be set * using function @ref LL_ADC_INJ_ConfigQueueContext(). * @note This parameter can be modified only when no conversion is on going * on either groups regular or injected. * @note A modification of the context mode (bit JQDIS) causes the contexts * queue to be flushed and the register JSQR is cleared. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n * CFGR JQDIS LL_ADC_INJ_SetQueueMode * @param ADCx ADC instance * @param QueueMode This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_QUEUE_DISABLE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode); } /** * @brief Get ADC group injected context queue mode. * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n * CFGR JQDIS LL_ADC_INJ_GetQueueMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_INJ_QUEUE_DISABLE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); } /** * @brief Set one context on ADC group injected that will be checked in * contexts queue. * @note A context is a setting of group injected sequencer: * - group injected trigger * - sequencer length * - sequencer ranks * This function is intended to be used when contexts queue is enabled, * because the sequence must be fully configured in one time * (functions to set separately injected trigger and sequencer channels * cannot be used): * Refer to function @ref LL_ADC_INJ_SetQueueMode(). * @note In the contexts queue, only the active context can be read. * The parameters of this function can be read using functions: * @arg @ref LL_ADC_INJ_GetTriggerSource() * @arg @ref LL_ADC_INJ_GetTriggerEdge() * @arg @ref LL_ADC_INJ_GetSequencerRanks() * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n * JSQR JL LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING * * Note: This parameter is discarded in case of SW start: * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE". * @param SequencerNbRanks This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS * @param Rank1_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank2_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank3_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank4_Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, uint32_t TriggerSource, uint32_t ExternalTriggerEdge, uint32_t SequencerNbRanks, uint32_t Rank1_Channel, uint32_t Rank2_Channel, uint32_t Rank3_Channel, uint32_t Rank4_Channel) { /* Set bits with content of parameter "Rankx_Channel" with bits position */ /* in register depending on literal "LL_ADC_INJ_RANK_x". */ /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */ /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | ADC_JSQR_JL, (TriggerSource & ADC_JSQR_JEXTSEL) | (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) | SequencerNbRanks ); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels * @{ */ /** * @brief Set sampling time of the selected ADC channel * Unit: ADC clock cycles. * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note In case of internal channel (VrefInt, TempSensor, ...) to be * converted: * sampling time constraints must be respected (sampling time can be * adjusted in function of ADC clock frequency and sampling time * setting). * Refer to device datasheet for timings values (parameters TS_vrefint, * TS_temp, ...). * @note Conversion time is the addition of sampling time and processing time. * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits * - 6.5 ADC clock cycles at ADC resolution 6 bits * @note In case of ADC conversion of internal channel (VrefInt, * temperature sensor, ...), a sampling time minimum value * is required. * Refer to device datasheet. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param SamplingTime This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 * * (1) On some devices, ADC sampling time 2.5 ADC clock cycles * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } /** * @brief Get sampling time of the selected ADC channel * Unit: ADC clock cycles. * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note Conversion time is the addition of sampling time and processing time. * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits * - 6.5 ADC clock cycles at ADC resolution 6 bits * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 (8) * @arg @ref LL_ADC_CHANNEL_2 (8) * @arg @ref LL_ADC_CHANNEL_3 (8) * @arg @ref LL_ADC_CHANNEL_4 (8) * @arg @ref LL_ADC_CHANNEL_5 (8) * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @arg @ref LL_ADC_CHANNEL_16 * @arg @ref LL_ADC_CHANNEL_17 * @arg @ref LL_ADC_CHANNEL_18 * @arg @ref LL_ADC_CHANNEL_VREFINT (7) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5) * @arg @ref LL_ADC_CHANNEL_VBAT (6) * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1) * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3) * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5) * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4) * * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1) * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5 * * (1) On some devices, ADC sampling time 2.5 ADC clock cycles * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS) ); } /** * @brief Set mode single-ended or differential input of the selected * ADC channel. * @note Channel ending is on channel scope: independently of channel mapped * on ADC group regular or injected. * In differential mode: Differential measurement is carried out * between the selected channel 'i' (positive input) and * channel 'i+1' (negative input). Only channel 'i' has to be * configured, channel 'i+1' is configured automatically. * @note Refer to Reference Manual to ensure the selected channel is * available in differential mode. * For example, internal channels (VrefInt, TempSensor, ...) are * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. * @note On STM32G4, some channels are internally fixed to single-ended inputs * configuration: * - ADC1: Channels 12, 15, 16, 17 and 18 * - ADC2: Channels 15, 17 and 18 * - ADC3: Channels 12, 16, 17 and 18 (1) * - ADC4: Channels 16, 17 and 18 (1) * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) * (1) ADC3/4/5 are not available on all devices, refer to device datasheet * for more details. * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. * (Vref+ is the analog voltage reference) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 * @arg @ref LL_ADC_CHANNEL_4 * @arg @ref LL_ADC_CHANNEL_5 * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @param SingleDiff This parameter can be a combination of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { /* Bits for single or differential mode selection for each channel are set */ /* to 1 only when the differential mode is selected, and to 0 when the */ /* single mode is selected. */ if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED) { SET_BIT(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK); } else { CLEAR_BIT(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK); } } /** * @brief Get mode single-ended or differential input of the selected * ADC channel. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. * Therefore, to ensure a channel is configured in single-ended mode, * the configuration of channel itself and the channel 'i-1' must be * read back (to ensure that the selected channel channel has not been * configured in differential mode by the previous channel). * @note Refer to Reference Manual to ensure the selected channel is * available in differential mode. * For example, internal channels (VrefInt, TempSensor, ...) are * not available in differential mode. * @note When configuring a channel 'i' in differential mode, * the channel 'i+1' is not usable separately. * @note On STM32G4, some channels are internally fixed to single-ended inputs * configuration: * - ADC1: Channels 12, 15, 16, 17 and 18 * - ADC2: Channels 15, 17 and 18 * - ADC3: Channels 12, 16, 17 and 18 (1) * - ADC4: Channels 16, 17 and 18 (1) * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1) * (1) ADC3/4/5 are not available on all devices, refer to device datasheet * for more details. * @note One or several values can be selected. In this case, the value * returned is null if all channels are in single ended-mode. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: * @arg @ref LL_ADC_CHANNEL_1 * @arg @ref LL_ADC_CHANNEL_2 * @arg @ref LL_ADC_CHANNEL_3 * @arg @ref LL_ADC_CHANNEL_4 * @arg @ref LL_ADC_CHANNEL_5 * @arg @ref LL_ADC_CHANNEL_6 * @arg @ref LL_ADC_CHANNEL_7 * @arg @ref LL_ADC_CHANNEL_8 * @arg @ref LL_ADC_CHANNEL_9 * @arg @ref LL_ADC_CHANNEL_10 * @arg @ref LL_ADC_CHANNEL_11 * @arg @ref LL_ADC_CHANNEL_12 * @arg @ref LL_ADC_CHANNEL_13 * @arg @ref LL_ADC_CHANNEL_14 * @arg @ref LL_ADC_CHANNEL_15 * @retval 0: channel in single-ended mode, else: channel in differential mode */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) { return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog * @{ */ /** * @brief Set ADC analog watchdog monitored channels: * a single channel, multiple channels or all channels, * on ADC groups regular and-or injected. * @note Once monitored channels are selected, analog watchdog * is enabled. * @note In case of need to define a single channel to monitor * with analog watchdog from sequencer channel definition, * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDChannelGroup This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0) * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1) * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3) * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5) * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4) * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4) * * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) { /* Set bits with content of parameter "AWDChannelGroup" with bits position */ /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), AWDChannelGroup & AWDy); } /** * @brief Get ADC analog watchdog monitored channel. * @note Usage of the returned channel number: * - To reinject this channel into another function LL_ADC_xxx: * the returned channel number is only partly formatted on definition * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared * with parts of literals LL_ADC_CHANNEL_x or using * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Then the selected literal LL_ADC_CHANNEL_x can be used * as parameter for another function. * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Applicable only when the analog watchdog is set to monitor * one channel. * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 (1) * @arg @ref LL_ADC_AWD3 (1) * * (1) On this AWD number, monitored channel can be retrieved * if only 1 channel is programmed (or none or all channels). * This function cannot retrieve monitored channel if * multiple channels are programmed simultaneously * by bitfield. * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_AWD_DISABLE * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0) * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ * * (0) On STM32G4, parameter available only on analog watchdog number: AWD1. */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK); /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ if (AnalogWDMonitChannels != 0UL) { if (AWDy == LL_ADC_AWD1) { if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ AnalogWDMonitChannels = ((AnalogWDMonitChannels | (ADC_AWD_CR23_CHANNEL_MASK) ) & (~(ADC_CFGR_AWD1CH)) ); } else { /* AWD monitoring a single channel */ AnalogWDMonitChannels = (AnalogWDMonitChannels | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos)) ); } } else { if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) ); } else { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ AnalogWDMonitChannels = (AnalogWDMonitChannels | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) ); } } } return AnalogWDMonitChannels; } /** * @brief Set ADC analog watchdog thresholds value of both thresholds * high and low. * @note If value of only one threshold high or low must be set, * use function @ref LL_ADC_SetAnalogWDThresholds(). * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) { /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ /* position in register and register position depending on parameter */ /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); } /** * @brief Set ADC analog watchdog threshold value of threshold * high or low. * @note If values of both thresholds high or low must be set, * use function @ref LL_ADC_ConfigAnalogWDThresholds(). * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. * - groups monitored: ADC groups regular and-or injected. * - resolution: resolution is not limited (corresponds to * ADC resolution configured). * - AWD flexible (instances AWD2, AWD3): * - channels monitored: flexible on channels monitored, selection is * channel wise, from from 1 to all channels. * Specificity of this analog watchdog: Multiple channels can * be selected. For example: * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) * - groups monitored: not selection possible (monitoring on both * groups regular and injected). * Channels selected are monitored on groups regular and injected: * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). * @note On this STM32 series, setting of this feature is not conditioned to * ADC state: * ADC can be disabled, enabled with or without conversion on going * on either ADC groups regular or injected. * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n * TR3 LT3 LL_ADC_SetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, AWDThresholdsHighLow, AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); } /** * @brief Get ADC analog watchdog threshold value of threshold high, * threshold low or raw data with ADC thresholds high and low * concatenated. * @note If raw data with ADC thresholds high and low is retrieved, * the data of each threshold high or low can be isolated * using helper macro: * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n * TR3 LT3 LL_ADC_GetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @arg @ref LL_ADC_AWD2 * @arg @ref LL_ADC_AWD3 * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); } /** * @brief Set ADC analog watchdog filtering configuration * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @param FilteringConfig This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_FILTERING_NONE * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES * @retval None */ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig) { /* Prevent unused argument(s) compilation warning */ (void)(AWDy); MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig); } /** * @brief Get ADC analog watchdog filtering configuration * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: * @arg @ref LL_ADC_AWD1 * @retval Returned value can be: * @arg @ref LL_ADC_AWD_FILTERING_NONE * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) { /* Prevent unused argument(s) compilation warning */ (void)(AWDy); return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling * @{ */ /** * @brief Set ADC oversampling scope: ADC groups regular and-or injected * (availability of ADC group injected depends on STM32 families). * @note If both groups regular and injected are selected, * specify behavior of ADC group injected interrupting * group regular: when ADC group injected is triggered, * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_SetOverSamplingScope * @param ADCx ADC instance * @param OvsScope This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED * @retval None */ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope); } /** * @brief Get ADC oversampling scope: ADC groups regular and-or injected * (availability of ADC group injected depends on STM32 families). * @note If both groups regular and injected are selected, * specify behavior of ADC group injected interrupting * group regular: when ADC group injected is triggered, * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_GetOverSamplingScope * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } /** * @brief Set ADC oversampling discontinuous mode (triggered mode) * on the selected ADC group. * @note Number of oversampled conversions are done either in: * - continuous mode (all conversions of oversampling ratio * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. * @note On this STM32 series, oversampling discontinuous mode * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont * @param ADCx ADC instance * @param OverSamplingDiscont This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT * @retval None */ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) { MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont); } /** * @brief Get ADC oversampling discontinuous mode (triggered mode) * on the selected ADC group. * @note Number of oversampled conversions are done either in: * - continuous mode (all conversions of oversampling ratio * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } /** * @brief Set ADC oversampling * (impacting both ADC groups regular and injected) * @note This function set the 2 items of oversampling configuration: * - ratio * - shift * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift * @param ADCx ADC instance * @param Ratio This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_RATIO_2 * @arg @ref LL_ADC_OVS_RATIO_4 * @arg @ref LL_ADC_OVS_RATIO_8 * @arg @ref LL_ADC_OVS_RATIO_16 * @arg @ref LL_ADC_OVS_RATIO_32 * @arg @ref LL_ADC_OVS_RATIO_64 * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 * @param Shift This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_SHIFT_NONE * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 * @retval None */ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) { MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); } /** * @brief Get ADC oversampling ratio * (impacting both ADC groups regular and injected) * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio * @param ADCx ADC instance * @retval Ratio This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_RATIO_2 * @arg @ref LL_ADC_OVS_RATIO_4 * @arg @ref LL_ADC_OVS_RATIO_8 * @arg @ref LL_ADC_OVS_RATIO_16 * @arg @ref LL_ADC_OVS_RATIO_32 * @arg @ref LL_ADC_OVS_RATIO_64 * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); } /** * @brief Get ADC oversampling shift * (impacting both ADC groups regular and injected) * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift * @param ADCx ADC instance * @retval Shift This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_SHIFT_NONE * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } /** * @} */ /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode * @{ */ #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Set ADC multimode configuration to operate in independent mode * or multimode (for devices with several ADC instances). * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR DUAL LL_ADC_SetMultimode * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param Multimode This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_INDEPENDENT * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM * @retval None */ __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode); } /** * @brief Get ADC multimode configuration to operate in independent mode * or multimode (for devices with several ADC instances). * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. * @rmtoll CCR DUAL LL_ADC_GetMultimode * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_MULTI_INDEPENDENT * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); } /** * @brief Set ADC multimode conversion data transfer: no transfer * or transfer by DMA. * @note If ADC multimode transfer by DMA is not selected: * each ADC uses its own DMA channel, with its individual * DMA transfer settings. * If ADC multimode transfer by DMA is selected: * One DMA channel is used for both ADC (DMA of ADC master) * Specifies the DMA requests mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note How to retrieve multimode conversion data: * Whatever multimode transfer by DMA setting: using function * @ref LL_ADC_REG_ReadMultiConversionData32(). * If ADC multimode transfer by DMA is selected: conversion data * is a raw data with ADC master and slave concatenated. * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled * or enabled without conversion on going on group regular. * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n * CCR DMACFG LL_ADC_SetMultiDMATransfer * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param MultiDMATransfer This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B * @retval None */ __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer); } /** * @brief Get ADC multimode conversion data transfer: no transfer * or transfer by DMA. * @note If ADC multimode transfer by DMA is not selected: * each ADC uses its own DMA channel, with its individual * DMA transfer settings. * If ADC multimode transfer by DMA is selected: * One DMA channel is used for both ADC (DMA of ADC master) * Specifies the DMA requests mode: * - Limited mode (One shot mode): DMA transfer requests are stopped * when number of DMA data transfers (number of * ADC conversions) is reached. * This ADC mode is intended to be used with DMA mode non-circular. * - Unlimited mode: DMA transfer requests are unlimited, * whatever number of DMA data transfers (number of * ADC conversions). * This ADC mode is intended to be used with DMA mode circular. * @note If ADC DMA requests mode is set to unlimited and DMA is set to * mode non-circular: * when DMA transfers size will be reached, DMA will stop transfers of * ADC conversions data ADC will raise an overrun error * (overrun flag and interruption if enabled). * @note How to retrieve multimode conversion data: * Whatever multimode transfer by DMA setting: using function * @ref LL_ADC_REG_ReadMultiConversionData32(). * If ADC multimode transfer by DMA is selected: conversion data * is a raw data with ADC master and slave concatenated. * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n * CCR DMACFG LL_ADC_GetMultiDMATransfer * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B */ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); } /** * @brief Set ADC multimode delay between 2 sampling phases. * @note The sampling delay range depends on ADC resolution: * - ADC resolution 12 bits can have maximum delay of 12 cycles. * - ADC resolution 10 bits can have maximum delay of 10 cycles. * - ADC resolution 8 bits can have maximum delay of 8 cycles. * - ADC resolution 6 bits can have maximum delay of 6 cycles. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param MultiTwoSamplingDelay This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) * * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n * (3) Parameter available only if ADC resolution is 12 bits. * @retval None */ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); } /** * @brief Get ADC multimode delay between 2 sampling phases. * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3) * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3) * * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n * (3) Parameter available only if ADC resolution is 12 bits. */ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance * @{ */ /** * @brief Put ADC instance in deep power down state. * @note In case of ADC calibration necessary: When ADC is in deep-power-down * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_DEEPPWD); } /** * @brief Disable ADC deep power down mode. * @note In case of ADC calibration necessary: When ADC is in deep-power-down * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); } /** * @brief Get the selected ADC instance deep power down state. * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } /** * @brief Enable ADC instance internal voltage regulator. * @note On this STM32 series, after ADC internal voltage regulator enable, * a delay for ADC internal voltage regulator stabilization * is required before performing a ADC calibration or ADC enable. * Refer to device datasheet, parameter tADCVREG_STUP. * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } /** * @brief Disable ADC internal voltage regulator. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); } /** * @brief Get the selected ADC instance internal voltage regulator state. * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } /** * @brief Enable the selected ADC instance. * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled and ADC internal voltage regulator enabled. * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } /** * @brief Disable the selected ADC instance. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be not disabled. Must be enabled without conversion on going * on either groups regular or injected. * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } /** * @brief Get the selected ADC instance enable state. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } /** * @brief Get the selected ADC instance disable state. * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } /** * @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). * @note On this STM32 series, a minimum number of ADC clock cycles * are required between ADC end of calibration and ADC enable. * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. * @note For devices with differential mode available: * Calibration of offset is specific to each of * single-ended and differential modes * (calibration run must be performed for each of these * differential modes, if used afterwards and if the application * requires their calibration). * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADCAL LL_ADC_StartCalibration\n * CR ADCALDIF LL_ADC_StartCalibration * @param ADCx ADC instance * @param SingleDiff This parameter can be one of the following values: * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK)); } /** * @brief Get ADC calibration state. * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } /** * @} */ /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular * @{ */ /** * @brief Start ADC group regular conversion. * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, * without ADC disable command on going. * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } /** * @brief Stop ADC group regular conversion. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group regular, * without ADC disable command on going. * @rmtoll CR ADSTP LL_ADC_REG_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTP); } /** * @brief Get ADC group regular conversion state. * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } /** * @brief Get ADC group regular command of conversion stop state * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } /** * @brief Start ADC sampling phase for sampling time trigger mode * @note This function is relevant only when * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set * using @ref LL_ADC_REG_SetSamplingMode * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, * without ADC disable command on going. * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) { SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); } /** * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion * @note This function is relevant only when * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set * using @ref LL_ADC_REG_SetSamplingMode * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source * - @ref LL_ADC_REG_StartSamplingPhase has been called to start * the sampling phase * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, * without ADC disable command on going. * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); } /** * @brief Get ADC group regular conversion data, range fit for * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 12 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 10 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 8 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } /** * @brief Get ADC group regular conversion data, range fit for * ADC resolution 6 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_REG_ReadConversionData32. * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Get ADC multimode conversion data of ADC master, ADC slave * or raw data with ADC master and slave concatenated. * @note If raw data with ADC master and slave concatenated is retrieved, * a macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). * (however this macro is mainly intended for multimode * transfer by DMA, because this function can do the same * by getting multimode conversion data of ADC master or ADC slave * separately). * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param ConversionData This parameter can be one of the following values: * @arg @ref LL_ADC_MULTI_MASTER * @arg @ref LL_ADC_MULTI_SLAVE * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) >> (POSITION_VAL(ConversionData) & 0x1FUL) ); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected * @{ */ /** * @brief Start ADC group injected conversion. * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group injected, * without conversion stop command on going on group injected, * without ADC disable command on going. * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTART); } /** * @brief Stop ADC group injected conversion. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group injected, * without ADC disable command on going. * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) { /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP); } /** * @brief Get ADC group injected conversion state. * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } /** * @brief Get ADC group injected command of conversion stop state * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } /** * @brief Get ADC group injected conversion data, range fit for * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 12 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 10 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 8 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @brief Get ADC group injected conversion data, range fit for * ADC resolution 6 bits. * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_RANK_1 * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); } /** * @} */ /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management * @{ */ /** * @brief Get flag ADC ready. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular end of sequence conversions. * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular overrun. * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } /** * @brief Get flag ADC group regular end of sampling phase. * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } /** * @brief Get flag ADC group injected end of unitary conversion. * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } /** * @brief Get flag ADC group injected end of sequence conversions. * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } /** * @brief Get flag ADC group injected contexts queue overflow. * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } /** * @brief Get flag ADC analog watchdog 1 flag * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } /** * @brief Get flag ADC analog watchdog 2. * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } /** * @brief Get flag ADC analog watchdog 3. * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } /** * @brief Clear flag ADC ready. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); } /** * @brief Clear flag ADC group regular end of unitary conversion. * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); } /** * @brief Clear flag ADC group regular end of sequence conversions. * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); } /** * @brief Clear flag ADC group regular overrun. * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); } /** * @brief Clear flag ADC group regular end of sampling phase. * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); } /** * @brief Clear flag ADC group injected end of unitary conversion. * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC); } /** * @brief Clear flag ADC group injected end of sequence conversions. * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS); } /** * @brief Clear flag ADC group injected contexts queue overflow. * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF); } /** * @brief Clear flag ADC analog watchdog 1. * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); } /** * @brief Clear flag ADC analog watchdog 2. * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); } /** * @brief Clear flag ADC analog watchdog 3. * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) { WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Get flag multimode ADC ready of the ADC master. * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC ready of the ADC slave. * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master. * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave. * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular overrun of the ADC master. * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular overrun of the ADC slave. * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sampling of the ADC master. * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group regular end of sampling of the ADC slave. * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master. * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave. * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected context queue overflow of the ADC master. * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave. * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode analog watchdog 1 of the ADC slave. * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 2 of the ADC master. * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave. * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 3 of the ADC master. * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } /** * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave. * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADC_LL_EF_IT_Management ADC IT management * @{ */ /** * @brief Enable ADC ready. * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); } /** * @brief Enable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_EOC); } /** * @brief Enable interruption ADC group regular end of sequence conversions. * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_EOS); } /** * @brief Enable ADC group regular interruption overrun. * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_OVR); } /** * @brief Enable interruption ADC group regular end of sampling. * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); } /** * @brief Enable interruption ADC group injected end of unitary conversion. * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_JEOC); } /** * @brief Enable interruption ADC group injected end of sequence conversions. * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_JEOS); } /** * @brief Enable interruption ADC group injected context queue overflow. * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF); } /** * @brief Enable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); } /** * @brief Enable interruption ADC analog watchdog 2. * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); } /** * @brief Enable interruption ADC analog watchdog 3. * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) { SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); } /** * @brief Disable interruption ADC ready. * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); } /** * @brief Disable interruption ADC group regular end of unitary conversion. * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); } /** * @brief Disable interruption ADC group regular end of sequence conversions. * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); } /** * @brief Disable interruption ADC group regular overrun. * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); } /** * @brief Disable interruption ADC group regular end of sampling. * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); } /** * @brief Disable interruption ADC group regular end of unitary conversion. * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC); } /** * @brief Disable interruption ADC group injected end of sequence conversions. * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS); } /** * @brief Disable interruption ADC group injected context queue overflow. * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF); } /** * @brief Disable interruption ADC analog watchdog 1. * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); } /** * @brief Disable interruption ADC analog watchdog 2. * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); } /** * @brief Disable interruption ADC analog watchdog 3. * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) { CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); } /** * @brief Get state of interruption ADC ready * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular end of unitary conversion * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular end of sequence conversions * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular overrun * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group regular end of sampling * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group injected end of unitary conversion * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group injected end of sequence conversions * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC group injected context queue overflow interrupt state * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } /** * @brief Get state of interruption ADC analog watchdog 1 * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } /** * @brief Get state of interruption Get ADC analog watchdog 2 * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } /** * @brief Get state of interruption Get ADC analog watchdog 3 * (0: interrupt disabled, 1: interrupt enabled). * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } /** * @} */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions * @{ */ /* Initialization of some features of ADC common parameters and multimode */ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); /* De-initialization of ADC instance, ADC group regular and ADC group injected */ /* (availability of ADC group injected depends on STM32 families) */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); /* Initialization of some features of ADC instance and ADC group injected */ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); /** * @} */ #endif /* USE_FULL_LL_DRIVER */ /** * @} */ /** * @} */ #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */ /** * @} */ #ifdef __cplusplus } #endif #endif /* STM32G4xx_LL_ADC_H */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/LICENSE.txt ================================================ This software component is provided to you as part of a software package and applicable license terms are in the Package_license file. If you received this software component outside of a package or without applicable license terms, the terms of the BSD-3-Clause license shall apply. You may obtain a copy of the BSD-3-Clause at: https://opensource.org/licenses/BSD-3-Clause ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal.c * @author MCD Application Team * @brief HAL module driver. * This is the common part of the HAL initialization ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be used by the PPP peripheral drivers and the user to start using the HAL. [..] The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup HAL HAL * @brief HAL module driver * @{ */ #ifdef HAL_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** * @brief STM32G4xx HAL Driver version number V1.2.2 */ #define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32G4xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32G4xx_HAL_VERSION_SUB2 << 8U )\ |(__STM32G4xx_HAL_VERSION_RC)) #if defined(VREFBUF) #define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ #endif /* VREFBUF */ /* ------------ SYSCFG registers bit address in the alias region ------------ */ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) /* --- MEMRMP Register ---*/ /* Alias word address of FB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET #define FB_MODE_BitNumber ((uint8_t)0x8) #define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4)) /* --- GPC Register ---*/ /* Alias word address of CCMER bit */ #define SCSR_OFFSET (SYSCFG_OFFSET + 0x18) #define CCMER_BitNumber ((uint8_t)0x0) #define SCSR_CCMER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (CCMER_BitNumber * 4)) /* Private macro -------------------------------------------------------------*/ /* Exported variables ---------------------------------------------------------*/ /** @defgroup HAL_Exported_Variables HAL Exported Variables * @{ */ __IO uint32_t uwTick; uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup HAL_Exported_Functions HAL Exported Functions * @{ */ /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief HAL Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize the Flash interface the NVIC allocation and initial time base clock configuration. (+) De-Initialize common part of the HAL. (+) Configure the time base source to have 1ms time base with a dedicated Tick interrupt priority. (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. (++) Time base configuration function (HAL_InitTick ()) is called automatically at the beginning of the program after reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). (++) Source of time base is configured to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. (++) functions affecting time base configurations are declared as __weak to make override possible in case of other implementations in user file. @endverbatim * @{ */ /** * @brief This function is used to configure the Flash prefetch, the Instruction and Data caches, * the time base source, NVIC and any required global low level hardware * by calling the HAL_MspInit() callback function to be optionally defined in user file * stm32g4xx_hal_msp.c. * * @note HAL_Init() function is called at the beginning of program after reset and before * the clock configuration. * * @note In the default implementation the System Timer (Systick) is used as source of time base. * The Systick configuration is based on HSI clock, as HSI is the clock * used after a system Reset and the NVIC configuration is set to Priority group 4. * Once done, time base tick starts incrementing: the tick variable counter is incremented * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { HAL_StatusTypeDef status = HAL_OK; /* Configure Flash prefetch, Instruction cache, Data cache */ /* Default configuration at reset is: */ /* - Prefetch disabled */ /* - Instruction cache enabled */ /* - Data cache enabled */ #if (INSTRUCTION_CACHE_ENABLE == 0U) __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE == 0U) __HAL_FLASH_DATA_CACHE_DISABLE(); #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) { status = HAL_ERROR; } else { /* Init the low level hardware */ HAL_MspInit(); } /* Return function status */ return status; } /** * @brief This function de-initializes common part of the HAL and stops the source of time base. * @note This function is optional. * @retval HAL status */ HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ __HAL_RCC_APB1_FORCE_RESET(); __HAL_RCC_APB1_RELEASE_RESET(); __HAL_RCC_APB2_FORCE_RESET(); __HAL_RCC_APB2_RELEASE_RESET(); __HAL_RCC_AHB1_FORCE_RESET(); __HAL_RCC_AHB1_RELEASE_RESET(); __HAL_RCC_AHB2_FORCE_RESET(); __HAL_RCC_AHB2_RELEASE_RESET(); __HAL_RCC_AHB3_FORCE_RESET(); __HAL_RCC_AHB3_RELEASE_RESET(); /* De-Init the low level hardware */ HAL_MspDeInit(); /* Return function status */ return HAL_OK; } /** * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } /** * @brief DeInitializes the MSP. * @retval None */ __weak void HAL_MspDeInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } /** * @brief This function configures the source of the time base: * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { HAL_StatusTypeDef status = HAL_OK; if (uwTickFreq != 0U) { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); uwTickPrio = TickPriority; } else { status = HAL_ERROR; } } else { status = HAL_ERROR; } } else { status = HAL_ERROR; } /* Return function status */ return status; } /** * @} */ /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim =============================================================================== ##### HAL Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Provide a tick value in millisecond (+) Provide a blocking delay in millisecond (+) Suspend the time base source interrupt (+) Resume the time base source interrupt (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier @endverbatim * @{ */ /** * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += uwTickFreq; } /** * @brief Provides a tick value in millisecond. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; } /** * @brief This function returns a tick priority. * @retval tick priority */ uint32_t HAL_GetTickPrio(void) { return uwTickPrio; } /** * @brief Set new tick Freq. * @retval status */ HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) { HAL_StatusTypeDef status = HAL_OK; uint32_t prevTickFreq; assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { /* Back up uwTickFreq frequency */ prevTickFreq = uwTickFreq; /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); if (status != HAL_OK) { /* Restore previous tick frequency */ uwTickFreq = prevTickFreq; } } return status; } /** * @brief Returns tick frequency. * @retval tick period in Hz */ uint32_t HAL_GetTickFreq(void) { return uwTickFreq; } /** * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { wait += (uint32_t)(uwTickFreq); } while ((HAL_GetTick() - tickstart) < wait) { } } /** * @brief Suspends Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_SuspendTick(void) { /* Disable SysTick Interrupt */ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_ResumeTick(void) { /* Enable SysTick Interrupt */ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); } /** * @brief Returns the HAL revision. * @retval version : 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) { return __STM32G4xx_HAL_VERSION; } /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16U); } /** * @brief Returns the device identifier. * @retval Device identifier */ uint32_t HAL_GetDEVID(void) { return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } /** * @} */ /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions * @brief HAL Debug functions * @verbatim =============================================================================== ##### HAL Debug functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Enable/Disable Debug module during SLEEP mode (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes (+) Enable/Disable Debug module during STANDBY mode @endverbatim * @{ */ /** * @brief Enable the Debug Module during SLEEP mode. * @retval None */ void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Disable the Debug Module during SLEEP mode. * @retval None */ void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } /** * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. * @retval None */ void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. * @retval None */ void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } /** * @brief Enable the Debug Module during STANDBY mode. * @retval None */ void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @brief Disable the Debug Module during STANDBY mode. * @retval None */ void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** * @} */ /** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions * @brief HAL SYSCFG configuration functions * @verbatim =============================================================================== ##### HAL SYSCFG configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start a hardware CCMSRAM erase operation (+) Enable/Disable the Internal FLASH Bank Swapping (+) Configure the Voltage reference buffer (+) Enable/Disable the Voltage reference buffer (+) Enable/Disable the I/O analog switch voltage booster @endverbatim * @{ */ /** * @brief Start a hardware CCMSRAM erase operation. * @note As long as CCMSRAM is not erased the CCMER bit will be set. * This bit is automatically reset at the end of the CCMSRAM erase operation. * @retval None */ void HAL_SYSCFG_CCMSRAMErase(void) { /* unlock the write protection of the CCMER bit */ SYSCFG->SKR = 0xCA; SYSCFG->SKR = 0x53; /* Starts a hardware CCMSRAM erase operation*/ SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER); } /** * @brief Enable the Internal FLASH Bank Swapping. * * @note This function can be used only for STM32G4xx devices. * * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) * and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00040000) * * @retval None */ void HAL_SYSCFG_EnableMemorySwappingBank(void) { SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE); } /** * @brief Disable the Internal FLASH Bank Swapping. * * @note This function can be used only for STM32G4xx devices. * * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) * and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00040000) * * @retval None */ void HAL_SYSCFG_DisableMemorySwappingBank(void) { CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE); } #if defined(VREFBUF) /** * @brief Configure the internal voltage reference buffer voltage scale. * @param VoltageScaling: specifies the output voltage to achieve * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREFBUF_OUT around 2.048 V. * This requires VDDA equal to or higher than 2.4 V. * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREFBUF_OUT around 2.5 V. * This requires VDDA equal to or higher than 2.8 V. * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V. * This requires VDDA equal to or higher than 3.15 V. * @retval None */ void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); } /** * @brief Configure the internal voltage reference buffer high impedance mode. * @param Mode: specifies the high impedance mode * This parameter can be one of the following values: * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); } /** * @brief Tune the Internal Voltage Reference buffer (VREFBUF). * @param TrimmingValue specifies trimming code for VREFBUF calibration * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F * @retval None */ void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); } /** * @brief Enable the Internal Voltage Reference buffer (VREFBUF). * @retval HAL_OK/HAL_TIMEOUT */ HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) { uint32_t tickstart; SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait for VRR bit */ while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) { if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } return HAL_OK; } /** * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); } #endif /* VREFBUF */ /** * @brief Enable the I/O analog switch voltage booster * * @retval None */ void HAL_SYSCFG_EnableIOSwitchBooster(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } /** * @brief Disable the I/O analog switch voltage booster * * @retval None */ void HAL_SYSCFG_DisableIOSwitchBooster(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } /** * @brief Enable the I/O analog switch voltage by VDD * * @retval None */ void HAL_SYSCFG_EnableIOSwitchVDD(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } /** * @brief Disable the I/O analog switch voltage by VDD * * @retval None */ void HAL_SYSCFG_DisableIOSwitchVDD(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } /** @brief CCMSRAM page write protection enable * @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP * @note write protection can only be disabled by a system reset * @retval None */ void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page) { assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE(Page)); SET_BIT(SYSCFG->SWPR, (uint32_t)(Page)); } /** * @} */ /** * @} */ #endif /* HAL_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * + Peripheral State functions * Other functions (extended functions) are available in file * "stm32g4xx_hal_adc_ex.c". * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### ADC peripheral features ##### ============================================================================== [..] (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. (+) Interrupt generation at the end of regular conversion and in case of analog watchdog or overrun events. (+) Single and continuous conversion modes. (+) Scan mode for conversion of several channels sequentially. (+) Data alignment with in-built data coherency. (+) Programmable sampling time (channel wise) (+) External trigger (timer or EXTI) with configurable polarity (+) DMA request generation for transfer of conversions data of regular group. (+) Configurable delay between conversions in Dual interleaved mode. (+) ADC channels selectable single/differential input. (+) ADC offset shared on 4 offset instances. (+) ADC gain compensation (+) ADC calibration (+) ADC conversion of regular group. (+) ADC supply requirements: 1.62 V to 3.6 V. (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). ##### How to use this driver ##### ============================================================================== [..] *** Configuration of top level parameters related to ADC *** ============================================================ [..] (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. (++) Two clock settings are mandatory: (+++) ADC clock (core clock, also possibly conversion clock). (+++) ADC clock (conversions clock). Two possible clock sources: synchronous clock derived from AHB clock or asynchronous clock derived from system clock or PLL (output divider P) running up to 75MHz. (+++) Example: Into HAL_ADC_MspInit() (recommended code location) or with other device clock parameters configuration: (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory) RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected) (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit; (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL; (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); (++) ADC clock source and clock prescaler are configured at ADC level with parameter "ClockPrescaler" using function HAL_ADC_Init(). (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_ENABLE() (++) Configure these ADC pins in analog mode using function HAL_GPIO_Init() (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: (++) Configure the DMA (DMA channel, mode normal or circular, ...) using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, group regular, channels parameters *** ================================================================ [..] (#) Configure the ADC parameters (resolution, data alignment, ...) and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). (#) Optionally, configure the analog watchdog parameters (channels monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). *** Execution of ADC conversions *** ==================================== [..] (#) Optionally, perform an automatic ADC calibration to improve the conversion accuracy using function HAL_ADCEx_Calibration_Start(). (#) ADC driver can be used among three modes: polling, interruption, transfer by DMA. (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() (+++) Retrieve conversion results using function HAL_ADC_GetValue() (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) (+++) Retrieve conversion results using function HAL_ADC_GetValue() (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_DMA() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() [..] (@) Callback functions must be implemented in user program: (+@) HAL_ADC_ErrorCallback() (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) (+@) HAL_ADC_ConvCpltCallback() (+@) HAL_ADC_ConvHalfCpltCallback *** Deinitialization of ADC *** ============================================================ [..] (#) Disable the ADC interface (++) ADC clock can be hard reset and disabled at RCC top level. (++) Hard reset of ADC peripherals using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). (++) ADC clock disable using the equivalent macro/functions as configuration step. (+++) Example: Into HAL_ADC_MspDeInit() (recommended code location) or with other device clock parameters configuration: (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); (#) ADC pins configuration (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() (#) Optionally, in case of usage of ADC with interruptions: (++) Disable the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA using function HAL_DMA_Init(). (++) Disable the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. Use Functions HAL_ADC_RegisterCallback() to register an interrupt callback. [..] Function HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback (+) EndOfSamplingCallback : ADC end of sampling callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) ErrorCallback : ADC error callback (+) InjectedConvCpltCallback : ADC group injected conversion complete callback (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback (+) EndOfSamplingCallback : ADC end of sampling callback (+) MspInitCallback : ADC Msp Init callback (+) MspDeInitCallback : ADC Msp DeInit callback [..] By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() or HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup ADC ADC * @brief ADC HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADC_Private_Constants ADC Private Constants * @{ */ #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ /* - maximum sampling time (640.5 adc_clk) */ /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ /* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */ /* - ADC oversampling ratio 256 */ /* Calculation: 653 * 4096 * 256 CPU clock cycles max */ /* Unit: cycles of CPU clock. */ #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADC_Exported_Functions ADC Exported Functions * @{ */ /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief ADC Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** * @brief Initialize the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (refer to description of RCC configuration for ADC * in header of this file). * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can * be used to reconfigure some parameters of ADC_InitTypeDef * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_InitTypeDef". * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". * @note Parameters related to common ADC registers (ADC clock mode) are set * only if all ADCs are disabled. * If this is not the case, these common parameters setting are * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation)); assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv)); assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); if (hadc->Init.DiscontinuousConvMode == ENABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) && (tmp_adc_reg_is_conversion_on_going == 0UL) ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { /* Reset configuration of ADC common register CCR: */ /* */ /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ /* according to adc->Init.ClockPrescaler. It selects the clock */ /* source and sets the clock division factor. */ /* */ /* Some parameters of this register are not reset, since they are set */ /* by other functions and must be kept in case of usage of this */ /* function on the fly (update of a parameter of ADC_InitTypeDef */ /* without needing to reconfigure all other ADC groups/channels */ /* parameters): */ /* - when multimode feature is available, multimode-related */ /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); } } /* Configuration of ADC: */ /* - resolution Init.Resolution */ /* - data alignment Init.DataAlign */ /* - external trigger to start conversion Init.ExternalTrigConv */ /* - external trigger polarity Init.ExternalTrigConvEdge */ /* - continuous conversion mode Init.ContinuousConvMode */ /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | hadc->Init.Overrun | hadc->Init.DataAlign | hadc->Init.Resolution | ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); if (hadc->Init.DiscontinuousConvMode == ENABLE) { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); } /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) | hadc->Init.ExternalTrigConvEdge ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Gain Compensation Init.GainCompensation */ /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { tmpCFGR = (ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); if (hadc->Init.GainCompensation != 0UL) { SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); } else { CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); } if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TROVS | ADC_CFGR2_ROVSM, ADC_CFGR2_ROVSE | hadc->Init.Oversampling.Ratio | hadc->Init.Oversampling.RightBitShift | hadc->Init.Oversampling.TriggeredMode | hadc->Init.Oversampling.OversamplingStopReset ); } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } } /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "NbrOfConversion" is discarded. */ /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); tmp_hal_status = HAL_ERROR; } /* Return function status */ return tmp_hal_status; } /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: * all ADC instances use the same core clock at RCC level, disabling * the core clock reset all ADC instances). * If this is not the case, reset of these common parameters reset is * bypassed without error reporting: it can be the intended behavior in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: * this saves more power by reducing leakage currents * and is particularly interesting before entering MCU low-power modes. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check ADC handle */ if (hadc == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); /* Stop potential conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ /* Flush register JSQR: reset the queue sequencer when injected */ /* queue sequencer is enabled and ADC disabled. */ /* The software and hardware triggers of the injected sequence are both */ /* internally disabled just after the completion of the last valid */ /* injected sequence. */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; } } /* Note: HAL ADC deInit is done independently of ADC conversion stop */ /* and disable return status. In case of status fail, attempt to */ /* perform deinitialization anyway and it is up user code in */ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ /* system RCC hard reset. */ /* ========== Reset ADC registers ========== */ /* Reset register IER */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF | ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC | ADC_IT_EOSMP | ADC_IT_RDY)); /* Reset register ISR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF | ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); /* Reset register CR */ /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": no direct reset applicable. Update CR register to reset value where doable by software */ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); /* Reset register CFGR */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); /* Reset register CFGR2 */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); /* Reset register SMPR1 */ CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); /* Reset register SMPR2 */ CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); /* Reset register TR1 */ CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); /* Reset register TR2 */ CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); /* Reset register TR3 */ CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); /* Reset register SQR1 */ CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L); /* Reset register SQR2 */ CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5); /* Reset register SQR3 */ CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10); /* Reset register SQR4 */ CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); /* Register JSQR was reset when the ADC was disabled */ /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ /* Reset register OFR1 */ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); /* Reset register OFR3 */ CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); /* Reset register OFR4 */ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ /* Reset register AWD2CR */ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); /* Reset register AWD3CR */ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); /* Reset register DIFSEL */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); /* Reset register CALFACT */ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); /* ========== Reset common ADC registers ========== */ /* Software is allowed to change common parameters only when all the other ADCs are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { /* Reset configuration of ADC common register CCR: - clock mode: CKMODE, PRESCEN - multimode related parameters (when this feature is available): MDMA, DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API) - internal measurement paths: Vbat, temperature sensor, Vref (set into HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripherals instances */ /* sharing the same common ADC instance: ADC state is forced to */ /* a similar state as after device power-on. */ /* Note: A possible implementation is to add RCC bus reset of ADC */ /* (for example, using macro */ /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } /* DeInit the low level hardware */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Reset injected channel configuration parameters */ hadc->InjectionConfig.ContextQueue = 0; hadc->InjectionConfig.ChannelCount = 0; /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Initialize the ADC MSP. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. */ } /** * @brief DeInitialize the ADC MSP. * @param hadc ADC handle * @note All ADC instances use the same core clock at RCC level, disabling * the core clock reset all ADC instances). * @retval None */ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. */ } #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** * @brief Register a User ADC Callback * To be used instead of the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; return HAL_ERROR; } if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = pCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = pCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = pCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = pCallback; break; case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = pCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = pCallback; break; case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = pCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } /** * @brief Unregister a ADC Callback * ADC callback is redirected to the weak predefined callback * @param hadc Pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) { case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; break; case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; break; case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; break; case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; break; case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; break; case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else if (HAL_ADC_STATE_RESET == hadc->State) { switch (CallbackID) { case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } return status; } #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions * @brief ADC IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular group. (+) Stop conversion of regular group. (+) Poll for conversion complete on regular group. (+) Poll for conversion event. (+) Get result of regular channel conversion. (+) Start conversion of regular group and enable interruptions. (+) Stop conversion of regular group and disable interruptions. (+) Handle ADC interrupt request (+) Start conversion of regular group and enable DMA transfer. (+) Stop conversion of regular group and disable ADC DMA transfer. @endverbatim * @{ */ /** * @brief Enable ADC, start conversion of regular group. * @note Interruptions enabled in this function: None. * @note Case of multimode enabled (when multimode feature is available): * if ADC is Slave, ADC is enabled but conversion is not started, * if ADC is master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* if Master ADC JAUTO bit is set, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } } #else if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); #endif } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for regular group conversion to be completed. * @note ADC conversion flags EOS (end of sequence) and EOC (end of * conversion) are cleared by this function, with an exception: * if low power feature "LowPowerAutoWait" is enabled, flags are * not cleared to not interfere with this feature until data register * is read using function HAL_ADC_GetValue(). * @note This function cannot be used in a particular setup: ADC configured * in DMA mode and polling for end of each conversion (ADC init * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_End; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_Flag_End = ADC_FLAG_EOS; } /* If end of conversion selected to end of unitary conversion */ else /* ADC_EOC_SINGLE_CONV */ { /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* Check ADC DMA mode in independent mode on ADC group regular */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } else { tmp_Flag_End = (ADC_FLAG_EOC); } } else { /* Check ADC DMA mode in multimode on ADC group regular */ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } else { tmp_Flag_End = (ADC_FLAG_EOC); } } #else /* Check ADC DMA mode */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } else { tmp_Flag_End = (ADC_FLAG_EOC); } #endif } /* Get tick count */ tickstart = HAL_GetTick(); /* Wait until End of unitary conversion or sequence conversions flag is raised */ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) && (hadc->Init.ContinuousConvMode == DISABLE) ) { /* Check whether end of sequence is reached */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* Retrieve Master ADC CFGR register */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); } else { /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } } /* Return function status */ return HAL_OK; } /** * @brief Poll for ADC event. * @param hadc ADC handle * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) * @arg @ref ADC_OVR_EVENT ADC Overrun event * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. * Indeed, the latter is reset only if hadc->Init.Overrun field is set * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten * by a new converted data as soon as OVR is cleared. * To reset OVR flag once the preserved data is retrieved, the user can resort * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); /* Get tick count */ tickstart = HAL_GetTick(); /* Check selected event flag */ while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } switch (EventType) { /* End Of Sampling event */ case ADC_EOSMP_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); /* Clear the End Of Sampling flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); break; /* Analog watchdog (level out of window) event */ /* Note: In case of several analog watchdog enabled, if needed to know */ /* which one triggered and on which ADCx, test ADC state of analog watchdog */ /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ /* For example: */ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ /* Check analog watchdog 1 flag */ case ADC_AWD_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); break; /* Check analog watchdog 2 flag */ case ADC_AWD2_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); break; /* Check analog watchdog 3 flag */ case ADC_AWD3_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); break; /* Injected context queue overflow event */ case ADC_JQOVF_EVENT: /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); /* Clear ADC Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); break; /* Overrun event */ default: /* Case ADC_OVR_EVENT */ /* If overrun is set to overwrite previous data, overrun event is not */ /* considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and without */ /* overrun ") */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); } else { /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN otherwise, data register is potentially overwritten by new converted data as soon as OVR is cleared. */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } break; } /* Return function status */ return HAL_OK; } /** * @brief Enable ADC, start conversion of regular group with interruption. * @note Interruptions enabled in this function according to initialization * setting : EOC (end of conversion), EOS (end of sequence), * OVR overrun. * Each of these interruptions has its dedicated callback function. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Start_IT() must be called for ADC Slave first, then for * ADC Master. * For ADC Slave, ADC is enabled only (conversion is not started). * For ADC Master, ADC is enabled and multimode conversion is started. * @note To guarantee a proper reset of all interruptions once all the needed * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure * a correct stop of the IT-based conversions. * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling * interruption. If required (e.g. in case of oversampling with trigger * mode), the user must: * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) * before calling HAL_ADC_Start_IT(). * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Disable all interruptions before enabling the desired ones */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* Enable ADC end of conversion interrupt */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); break; } /* Enable ADC overrun interrupt */ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is ADC_IT_OVR enabled; otherwise data overwrite is considered as normal behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); } /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Enable as well injected interruptions in case HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This allows to start regular and injected conversions when JAUTO is set with a single call to HAL_ADC_Start_IT() */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); /* if Master ADC JAUTO bit is set, Slave injected interruptions are enabled nevertheless (for same reason as above) */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Next, set Slave injected interruptions */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } } } #else /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Enable as well injected interruptions in case HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This allows to start regular and injected conversions when JAUTO is set with a single call to HAL_ADC_Start_IT() */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); #endif } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enable ADC, start conversion of regular group and transfer result through DMA. * @note Interruptions enabled in this function: * overrun (if applicable), DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() * is designed for single-ADC mode only. For multimode, the dedicated * HAL_ADCEx_MultiModeStart_DMA() function must be used. * @param hadc ADC handle * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); #if defined(ADC_MULTIMODE_SUPPORT) /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((ADC_IS_INDEPENDENT(hadc) != RESET) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) #endif /* ADC_MULTIMODE_SUPPORT */ { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } } #if defined(ADC_MULTIMODE_SUPPORT) else { tmp_hal_status = HAL_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); } #endif } else { tmp_hal_status = HAL_BUSY; } /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on ADC group injected. If ADC group injected is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential ADC group regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent * to flag EOC. * - If sequencer is composed of several ranks, during the scan * sequence flag EOC only is raised, at the end of the scan sequence * both flags EOC and EOS are raised. * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADC_PollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; } /** * @brief Start ADC conversion sampling phase of regular group * @note: This function should only be called to start sampling when * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling * mode has been selected * - @ref ADC_SOFTWARE_START has been selected as trigger source * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Start sampling */ SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); /* Return function status */ return HAL_OK; } /** * @brief Stop ADC conversion sampling phase of regular group and start conversion * @note: This function should only be called to stop sampling when * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling * mode has been selected * - @ref ADC_SOFTWARE_START has been selected as trigger source * - after sampling has been started using @ref HAL_ADC_StartSampling. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Start sampling */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG); /* Return function status */ return HAL_OK; } /** * @brief Handle ADC interrupt request. * @param hadc ADC handle * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ uint32_t tmp_isr = hadc->Instance->ISR; uint32_t tmp_ier = hadc->Instance->IER; uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); /* ========== Check End of Sampling flag for ADC group regular ========== */ if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); } /* End Of Sampling callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->EndOfSamplingCallback(hadc); #else HAL_ADCEx_EndOfSamplingCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); } /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* check CONT bit directly in handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { /* else need to check Master ADC CONT bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* Carry on if continuous mode is disabled */ if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } /* Conversion complete callback */ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ /* to determine if conversion has been triggered from EOC or EOS, */ /* possibility to use: */ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved data.*/ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) { if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) { /* If End of Sequence is reached, disable interrupts */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } } /* Injected Conversion complete callback */ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether interruption has been triggered by end of conversion or end of sequence. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } /* ========== Check Analog watchdog 1 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); } /* ========== Check analog watchdog 2 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Level out of window 2 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow2Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow2Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); } /* ========== Check analog watchdog 3 flag ========== */ if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Level out of window 3 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow3Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow3Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); } /* ========== Check Overrun flag ========== */ if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) { /* If overrun is set to overwrite previous data (default setting), */ /* overrun event is not considered as an error. */ /* (cf ref manual "Managing conversions without using the DMA and without */ /* overrun ") */ /* Exception for usage with DMA overrun event always considered as an */ /* error. */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { overrun_error = 1UL; } else { /* Check DMA configuration */ #if defined(ADC_MULTIMODE_SUPPORT) if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) { /* Multimode (when feature is available) is enabled, Common Control Register MDMA bits must be checked. */ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { overrun_error = 1UL; } } else #endif { /* Multimode not set or feature not available or ADC independent */ if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL) { overrun_error = 1UL; } } } if (overrun_error == 1UL) { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); /* Error callback */ /* Note: In case of overrun, ADC conversion data is preserved until */ /* flag OVR is reset. */ /* Therefore, old ADC conversion data can be retrieved in */ /* function "HAL_ADC_ErrorCallback()". */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } /* ========== Check Injected context queue overflow flag ========== */ if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { /* Change ADC state to overrun state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); /* Injected context queue overflow callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedQueueOverflowCallback(hadc); #else HAL_ADCEx_InjectedQueueOverflowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } } /** * @brief Conversion complete callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvCpltCallback must be implemented in the user file. */ } /** * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } /** * @brief Analog watchdog 1 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. */ } /** * @brief ADC error callback in non-blocking mode * (ADC conversion with interruption or transfer by DMA). * @note In case of error due to overrun when using ADC with DMA transfer * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } /** * @} */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog @endverbatim * @{ */ /** * @brief Configure a channel to be assigned to ADC group regular. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * These internal paths can be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into ADC group regular, * following calls to this function can be used to reconfigure * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, * without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0UL; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); } else { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); } /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); if (sConfig->OffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign)); assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation)); /* Set ADC selected offset sign & saturation */ LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign); LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), sConfig->SamplingTime); } } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } else { /* nothing to do */ } } } /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Configure the analog watchdog. * @note Possibility to update parameters on the fly: * This function initializes the selected analog watchdog, successive * calls to this function can be used to reconfigure some parameters * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting * the ADC. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". * @note On this STM32 series, analog watchdog thresholds can be modified * while ADC conversion is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next * ADC EOC (end of unitary conversion). * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc ADC handle * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpAWDHighThresholdShifted; uint32_t tmpAWDLowThresholdShifted; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); } /* Verify thresholds range */ if (hadc->Init.OversamplingMode == ENABLE) { /* Case of oversampling enabled: depending on ratio and shift configuration, analog watchdog thresholds can be higher than ADC resolution. Verify if thresholds are within maximum thresholds range. */ assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); } else { /* Verify if thresholds are within the selected ADC resolution */ assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); } /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on ADC groups regular and injected: */ /* - Analog watchdog channels */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Analog watchdog configuration */ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels, on groups regular and-or injected. */ switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); break; case ADC_ANALOGWATCHDOG_SINGLE_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); break; case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); break; case ADC_ANALOGWATCHDOG_ALL_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); break; case ADC_ANALOGWATCHDOG_ALL_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); break; case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); break; } /* Set the filtering configuration */ MODIFY_REG(hadc->Instance->TR1, ADC_TR1_AWDFILT, AnalogWDGConfig->FilteringConfig); /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD1(hadc->Instance); /* Configure ADC analog watchdog interrupt */ if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } else { LL_ADC_DisableIT_AWD1(hadc->Instance); } } /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: case ADC_ANALOGWATCHDOG_SINGLE_INJEC: case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } else { SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } break; case ADC_ANALOGWATCHDOG_ALL_REG: case ADC_ANALOGWATCHDOG_ALL_INJEC: case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD2(hadc->Instance); /* Configure ADC analog watchdog interrupt */ if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } else { LL_ADC_DisableIT_AWD2(hadc->Instance); } } /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { /* Update state, clear previous result related to AWD3 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD3(hadc->Instance); /* Configure ADC analog watchdog interrupt */ if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } else { LL_ADC_DisableIT_AWD3(hadc->Instance); } } } } /* Analog watchdog thresholds configuration */ if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0. */ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); } /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ else { /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */ /* are set to 0. */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); } /* Set ADC analog watchdog thresholds value of both thresholds high and low */ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @} */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions * @brief ADC Peripheral State functions * @verbatim =============================================================================== ##### Peripheral state and errors functions ##### =============================================================================== [..] This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @endverbatim * @{ */ /** * @brief Return the ADC handle state. * @note ADC state machine is managed by bitfields, ADC status must be * compared with states bits. * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Return ADC handle state */ return hadc->State; } /** * @brief Return the ADC error code. * @param hadc ADC handle * @retval ADC error code (bitfield on 32 bits) */ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); return hadc->ErrorCode; } /** * @} */ /** * @} */ /** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ /** * @brief Stop ADC conversion. * @param hadc ADC handle * @param ConversionGroup ADC group regular and/or injected. * This parameter can be one of the following values: * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { uint32_t tickstart; uint32_t Conversion_Timeout_CPU_cycles = 0UL; uint32_t conversion_group_reassigned = ConversionGroup; uint32_t tmp_ADC_CR_ADSTART_JADSTART; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular != 0UL) || (tmp_adc_is_conversion_on_going_injected != 0UL) ) { /* Particular case of continuous auto-injection mode combined with */ /* auto-delay mode. */ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) && (hadc->Init.ContinuousConvMode == ENABLE) && (hadc->Init.LowPowerAutoWait == ENABLE) ) { /* Use stop of regular group */ conversion_group_reassigned = ADC_REGULAR_GROUP; /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) { if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } Conversion_Timeout_CPU_cycles ++; } /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); } /* Stop potential conversion on going on ADC group regular */ if (conversion_group_reassigned != ADC_INJECTED_GROUP) { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) { /* Stop ADC group regular conversion */ LL_ADC_REG_StopConversion(hadc->Instance); } } } /* Stop potential conversion on going on ADC group injected */ if (conversion_group_reassigned != ADC_REGULAR_GROUP) { /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) { /* Stop ADC group injected conversion */ LL_ADC_INJ_StopConversion(hadc->Instance); } } } /* Selection of start and stop bits with respect to the regular or injected group */ switch (conversion_group_reassigned) { case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); break; case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; break; /* Case ADC_REGULAR_GROUP only*/ default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; break; } /* Wait for conversion effectively stopped */ tickstart = HAL_GetTick(); while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit has been cleared (after a calibration), ADEN bit is reset by the calibration logic. The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_Enable(hadc->Instance); } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief Disable the selected ADC. * @note Prerequisite condition to use this function: ADC conversions must be * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_disable_on_going == 0UL) ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); return HAL_ERROR; } } } } /* Return HAL status */ return HAL_OK; } /** * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else /* DMA and-or internal error occurred */ { if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) { /* Call HAL ADC Error Callback function */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } else { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } /** * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Peripheral Control functions * Other functions (generic functions) are available in file * "stm32g4xx_hal_adc.c". * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32g4xx_hal_adc.c". [..] @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup ADCEx ADCEx * @brief ADC Extended HAL module driver * @{ */ #ifdef HAL_ADC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants * @{ */ #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ /* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value */ /* considering both possible ADC clocking scheme: */ /* - ADC clock from synchronous clock with AHB prescaler 512, */ /* ADC prescaler 4. */ /* Ratio max = 512 *4 = 2048 */ /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ /* Highest CPU clock PLL (PLLR). */ /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ /* = 3968 ) */ /* Calibration_time MAX = 81 / f_ADC */ /* = 81 / (f_CPU/3938) = 318978 CPU cycles */ #define ADC_CALIBRATION_TIMEOUT (318978UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions * @{ */ /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions * @brief Extended IO operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. (+) Start conversion of ADC group injected. (+) Stop conversion of ADC group injected. (+) Poll for conversion complete on ADC group injected. (+) Get result of ADC group injected channel conversion. (+) Start conversion of ADC group injected and enable interruptions. (+) Stop conversion of ADC group injected and disable interruptions. (+) When multimode feature is available, start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. @endverbatim * @{ */ /** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @param hadc ADC handle * @param SingleDiff Selection of single-ended or differential input * This parameter can be one of the following values: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, SingleDiff); /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { wait_loop_index++; if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Get the calibration factor. * @param hadc ADC handle. * @param SingleDiff This parameter can be only: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Return the selected ADC calibration value */ return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff); } /** * @brief Set the calibration factor to overwrite automatic conversion result. * ADC must be enabled and no conversion is ongoing. * @param hadc ADC handle * @param SingleDiff This parameter can be only: * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); /* Process locked */ __HAL_LOCK(hadc); /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Set the selected ADC calibration value */ LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor); } else { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Update ADC error code */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); /* Update ADC state machine to error */ tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Enable ADC, start conversion of injected group. * @note Interruptions enabled in this function: None. * @note Case of multimode enabled when multimode feature is available: * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Check if a regular conversion is ongoing */ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* if ADC is slave, */ /* - ADC is enabled only (conversion is not started), */ /* - if multimode only concerns regular conversion, ADC is enabled */ /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { LL_ADC_INJ_StartConversion(hadc->Instance); } } else { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #else if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { /* Start ADC group injected conversion */ LL_ADC_INJ_StartConversion(hadc->Instance); } #endif } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } } /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of multimode enabled (when multimode feature is available), * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @param hadc ADC handle. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on regular group is on-going */ if (tmp_hal_status == HAL_OK) { if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Wait for injected group conversion to be completed. * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @note Depending on hadc->Init.EOCSelection, JEOS or JEOC is * checked and cleared depending on AUTDLY bit status. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_End; uint32_t tmp_adc_inj_is_trigger_source_sw_start; uint32_t tmp_adc_reg_is_trigger_source_sw_start; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of sequence selected */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_Flag_End = ADC_FLAG_JEOS; } else /* end of conversion selected */ { tmp_Flag_End = ADC_FLAG_JEOC; } /* Get timeout */ tickstart = HAL_GetTick(); /* Wait until End of Conversion or Sequence flag is raised */ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; } } } } /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); } else { tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } #else tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) { /* Check whether end of sequence is reached */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ /* by the hardware. Even if no injected conversion is planned to come */ /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } } /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_JEOS) { /* Clear end of sequence JEOS flag of injected group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ /* For injected groups, no new conversion will start before JEOS is */ /* cleared. */ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); } } else { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); } /* Return API HAL status */ return HAL_OK; } /** * @brief Enable ADC, start conversion of injected group with interruption. * @note Interruptions enabled in this function according to initialization * setting : JEOC (end of conversion) or JEOS (end of sequence) * @note Case of multimode enabled (when multimode feature is enabled): * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, * then for ADC master. * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle. * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; #if defined(ADC_MULTIMODE_SUPPORT) uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); #endif /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { /* Check if a regular conversion is ongoing */ if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #endif /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) { __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); } /* Enable ADC end of conversion interrupt */ switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Case of multimode enabled (when multimode feature is available): */ /* if ADC is slave, */ /* - ADC is enabled only (conversion is not started), */ /* - if multimode only concerns regular conversion, ADC is enabled */ /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { LL_ADC_INJ_StartConversion(hadc->Instance); } } else { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } #else if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { /* Start ADC group injected conversion */ LL_ADC_INJ_StartConversion(hadc->Instance); } #endif } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } } /** * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note Case of multimode enabled (when multimode feature is available): * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, * then for ADC slave. * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on the other group (regular group) is intended to */ /* continue. */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. * @note Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: * overrun, DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. * @note State field of Slave ADC handle is not updated in this configuration: * user should not rely on it for information related to Slave regular * conversions. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @param pData Destination Buffer address. * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmphadcSlave; ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { /* Process locked */ __HAL_LOCK(hadc); /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); ADC_CLEAR_ERRORCODE(&tmphadcSlave); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Enable(&tmphadcSlave); } /* Start multimode conversion of ADCs pair */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; } } /** * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral. * @note Multimode is kept enabled after this function. MultiMode DMA bits * (MDMA and DMACFG bits of common CCR register) are maintained. To disable * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can * resort to HAL_ADCEx_DisableMultiMode() API. * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; HAL_StatusTypeDef tmphadcSlave_disable_status; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential multimode conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); ADC_CLEAR_ERRORCODE(&tmphadcSlave); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmphadcSlave_conversion_on_going == 1UL) ) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmphadcSlave_conversion_on_going == 1UL) ) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADC_Stop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_ERROR) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripherals: master and slave */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave); if ((ADC_Disable(hadc) == HAL_OK) && (tmphadcSlave_disable_status == HAL_OK)) { tmp_hal_status = HAL_OK; } } else { /* In case of error, attempt to disable ADC master and slave without status assert */ (void) ADC_Disable(hadc); (void) ADC_Disable(&tmphadcSlave); } /* Set ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Return the last ADC Master and Slave regular conversions results when in multimode configuration. * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmpADC_Common; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Prevent unused argument(s) compilation warning if no assert_param check */ /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ UNUSED(hadc); /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* Return the multi mode conversion value */ return tmpADC_Common->CDR; } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent * to flag JEOC. * - If sequencer is composed of several ranks, during the scan * sequence flag JEOC only is raised, at the end of the scan sequence * both flags JEOC and EOS are raised. * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc ADC handle * @param InjectedRank the converted ADC injected rank. * This parameter can be one of the following values: * @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1 * @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2 * @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3 * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); /* Get ADC converted value */ switch (InjectedRank) { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: default: tmp_jdr = hadc->Instance->JDR1; break; } /* Return ADC converted value */ return tmp_jdr; } /** * @brief Injected conversion complete callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. */ } /** * @brief Injected context queue overflow callback. * @note This callback is called if injected context queue is enabled (parameter "QueueInjectedContext" in injected channel configuration) and if a new injected context is set when queue is full (maximum 2 contexts). * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ } /** * @brief Analog watchdog 2 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. */ } /** * @brief Analog watchdog 3 callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. */ } /** * @brief End Of Sampling callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. */ } /** * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral if no * conversion is on going on injected group. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if regular conversions are effectively stopped and if no injected conversions are on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } /* Conversion on injected group is stopped, but ADC not disabled since */ /* conversion on regular group is still running. */ else { SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of ADC groups regular and injected, * disable interrution of end-of-conversion, * disable ADC peripheral if no conversion is on going * on injected group. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Disable all regular-related interrupts */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* 2. Disable ADC peripheral if no injected conversions are on-going */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { tmp_hal_status = ADC_Disable(hadc); /* if no issue reported */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } /** * @brief Stop ADC conversion of regular group (and injected group in * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral if no conversion is on going * on injected group. * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. * For multimode (when multimode feature is available), * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { if (tmp_hal_status == HAL_OK) { tmp_hal_status = ADC_Disable(hadc); } else { (void)ADC_Disable(hadc); } /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } } else { SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. * @note Multimode is kept enabled after this function. Multimode DMA bits * (MDMA and DMACFG bits of common CCR register) are maintained. To disable * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can * resort to HAL_ADCEx_DisableMultiMode() API. * @note In case of DMA configured in circular mode, function * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential multimode conversion on going, on regular groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); ADC_CLEAR_ERRORCODE(&tmphadcSlave); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ tickstart = HAL_GetTick(); tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmphadcSlave_conversion_on_going == 1UL) ) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmphadcSlave_conversion_on_going == 1UL) ) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADCEx_RegularStop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* 2. Disable the ADC peripherals: master and slave if no injected */ /* conversion is on-going. */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { tmp_hal_status = ADC_Disable(hadc); if (tmp_hal_status == HAL_OK) { if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL) { tmp_hal_status = ADC_Disable(&tmphadcSlave); } } } if (tmp_hal_status == HAL_OK) { /* Both Master and Slave ADC's could be disabled. Update Master State */ /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } else { /* injected (Master or Slave) conversions are still on-going, no Master State change */ } } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions * @brief ADC Extended Peripheral Control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on injected group (+) Configure multimode when multimode feature is available (+) Enable or Disable Injected Queue (+) Disable ADC voltage regulator (+) Enter ADC deep-power-down mode @endverbatim * @{ */ /** * @brief Configure a channel to be assigned to ADC group injected. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_InjectionConfTypeDef". * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. * These internal paths can be disabled using function * HAL_ADC_DeInit(). * @note Caution: For Injected Context Queue use, a context must be fully * defined before start of injected conversion. All channels are configured * consecutively for the same ADC instance. Therefore, the number of calls to * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter * InjectedNbrOfConversion for each context. * - Example 1: If 1 context is intended to be used (or if there is no use of the * Injected Queue Context feature) and if the context contains 3 injected ranks * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be * called once for each channel (i.e. 3 times) before starting a conversion. * This function must not be called to configure a 4th injected channel: * it would start a new context into context queue. * - Example 2: If 2 contexts are intended to be used and each of them contains * 3 injected ranks (InjectedNbrOfConversion = 3), * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and * for each context (3 channels x 2 contexts = 6 calls). Conversion can * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. * @param hadc ADC handle * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0; uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext)); assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); assert_param(IS_ADC_EXTTRIGINJEC(hadc, sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedOffsetSaturation)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); /* JDISCEN and JAUTO bits can't be set at the same time */ assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); /* DISCEN and JAUTO bits can't be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); /* Verification of channel number */ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel)); } else { assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* Hardware constraint: Must fully define injected context register JSQR */ /* before make it entering into injected sequencer queue. */ /* */ /* - if scan mode is disabled: */ /* * Injected channels sequence length is set to 0x00: 1 channel */ /* converted (channel on injected rank 1) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* * Injected context register JSQR setting is simple: register is fully */ /* defined on one call of this function (for injected rank 1) and can */ /* be entered into queue directly. */ /* - if scan mode is enabled: */ /* * Injected channels sequence length is set to parameter */ /* "InjectedNbrOfConversion". */ /* * Injected context register JSQR setting more complex: register is */ /* fully defined over successive calls of this function, for each */ /* injected channel rank. It is entered into queue only when all */ /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || (sConfigInjected->InjectedNbrOfConversion == 1U)) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ /* (scan mode disabled, only rank 1 used) */ /* - external trigger to start conversion */ /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) | sConfigInjected->ExternalTrigInjecConvEdge ); } else { tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); } MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; } } else { /* Case of scan mode enabled, several channels to set into injected group */ /* sequencer. */ /* */ /* Procedure to define injected context register JSQR over successive */ /* calls of this function, for each injected channel rank: */ /* 1. Start new context and set parameters related to all injected */ /* channels: injected sequence length and trigger. */ /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ /* call of the context under setting */ if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion; /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ hadc->InjectionConfig.ContextQueue = 0x00000000U; /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ /* - external trigger to start conversion */ /* - external trigger polarity */ /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */ /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) | sConfigInjected->ExternalTrigInjecConvEdge ); } else { tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)); } } /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); /* Set the JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel() call, aggregate the setting to those already built during the previous HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt; /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ if (hadc->InjectionConfig.ChannelCount == 0U) { MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on injected group: */ /* - Injected context queue: Queue disable (active context is kept) or */ /* enable (context decremented, up to 2 contexts queued) */ /* - Injected discontinuous mode: can be enabled only if auto-injected */ /* mode is disabled. */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* If auto-injected mode is disabled: no constraint */ if (sConfigInjected->AutoInjectedConv == DISABLE) { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode)); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)); } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Automatic injected conversion: can be enabled if injected group */ /* external triggers are disabled. */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) { if (sConfigInjected->AutoInjectedConv == ENABLE) { SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } else { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } } /* If Automatic injected conversion was intended to be set and could not */ /* due to injected group external triggers enabled, error is reported. */ else { if (sConfigInjected->AutoInjectedConv == ENABLE) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } else { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } } if (sConfigInjected->InjecOversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); /* JOVSE must be reset in case of triggered regular mode */ assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); /* Configuration of Injected Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* Enable OverSampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS, ADC_CFGR2_JOVSE | sConfigInjected->InjecOversampling.Ratio | sConfigInjected->InjecOversampling.RightBitShift ); } else { /* Disable Regular OverSampling */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); } /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ if (sConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); } else { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); } /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted); /* Set ADC selected offset sign & saturation */ LL_ADC_SetOffsetSign(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedOffsetSign); LL_ADC_SetOffsetSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE); } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } } } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); /* Configuration of differential mode */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); } } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5)) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); } } else { /* nothing to do */ } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #if defined(ADC_MULTIMODE_SUPPORT) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: * This function initializes multimode parameters, following * calls to this function can be used to reconfigure some parameters * of structure "ADC_MultiModeTypeDef" on the fly, without resetting * the ADCs. * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MULTIMODE(multimode->Mode)); if (multimode->Mode != ADC_MODE_INDEPENDENT) { assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); ADC_CLEAR_ERRORCODE(&tmphadcSlave); ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) && (tmphadcSlave_conversion_on_going == 0UL)) { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, multimode->DMAAccessMode | ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ /* Note: Delay range depends on selected resolution: */ /* from 1 to 12 clock cycles for 12 bits */ /* from 1 to 10 clock cycles for 10 bits, */ /* from 1 to 8 clock cycles for 8 bits */ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, multimode->Mode | multimode->TwoSamplingDelay ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); } } } /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } #endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Enable Injected Queue * @note This function resets CFGR register JQDIS bit in order to enable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); /* Parameter can be set only if no conversion is on-going */ if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); /* Update state, clear previous result related to injected queue overflow */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @brief Disable Injected Queue * @note This function sets CFGR register JQDIS bit in order to disable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART * are both equal to 0 to ensure that no regular nor injected * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); /* Parameter can be set only if no conversion is on-going */ if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @brief Disable ADC voltage regulator. * @note Disabling voltage regulator allows to save power. This operation can * be carried out only when ADC is disabled. * @note To enable again the voltage regulator, the user is expected to * resort to HAL_ADC_Init() API. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_DisableInternalRegulator(hadc->Instance); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @brief Enter ADC deep-power-down mode * @note This mode is achieved in setting DEEPPWD bit and allows to save power * in reducing leakage currents. It is particularly interesting before * entering stop modes. * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the * ADC voltage regulator. This means that this API encompasses * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal * calibration is lost. * @note To exit the ADC deep-power-down mode, the user is expected to * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously * saved calibration factor. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { LL_ADC_EnableDeepPowerDown(hadc->Instance); tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } return tmp_hal_status; } /** * @} */ /** * @} */ #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_cortex.c * @author MCD Application Team * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: * + Initialization and Configuration functions * + Peripheral Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== [..] This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. The pending IRQ priority will be managed only by the sub priority. -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest pre-emption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) [..] *** How to configure SysTick using CORTEX HAL driver *** ======================================================== [..] Setup SysTick Timer for time base. (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. (++) Configures the SysTick IRQ priority to the lowest value (0x0F). (++) Resets the SysTick Counter register. (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined inside the stm32g4xx_hal_cortex.h file. (+) You can change the SysTick IRQ priority by calling the HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF @endverbatim ****************************************************************************** The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. ========================================================================================================================== NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description ========================================================================================================================== NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority | | | 4 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority | | | 3 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority | | | 2 bits for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority | | | 1 bit for subpriority -------------------------------------------------------------------------------------------------------------------------- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority | | | 0 bit for subpriority ========================================================================================================================== */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup CORTEX * @{ */ #ifdef HAL_CORTEX_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions * @{ */ /** @addtogroup CORTEX_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and Configuration functions ##### ============================================================================== [..] This section provides the CORTEX HAL driver functions allowing to configure Interrupts SysTick functionalities @endverbatim * @{ */ /** * @brief Set the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, * 1 bit for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, * 0 bit for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } /** * @brief Set the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @param PreemptPriority: The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority * @param SubPriority: the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t prioritygroup; /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enable a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } /** * @brief Disable a device specific interrupt in the NVIC interrupt controller. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } /** * @brief Initiate a system reset request to reset the MCU. * @retval None */ void HAL_NVIC_SystemReset(void) { /* System Reset */ NVIC_SystemReset(); } /** * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): * Counter is in free running mode to generate periodic interrupts. * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { return SysTick_Config(TicksNumb); } /** * @} */ /** @addtogroup CORTEX_Exported_Functions_Group2 * @brief Cortex control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX (NVIC, SYSTICK, MPU) functionalities. @endverbatim * @{ */ /** * @brief Get the priority grouping field from the NVIC Interrupt Controller. * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) */ uint32_t HAL_NVIC_GetPriorityGrouping(void) { /* Get the PRIGROUP[10:8] field value */ return NVIC_GetPriorityGrouping(); } /** * @brief Get the priority of an interrupt. * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, * 4 bits for subpriority * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, * 3 bits for subpriority * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, * 2 bits for subpriority * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, * 1 bit for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, * 0 bit for subpriority * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). * @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Get priority for Cortex-M system or device specific interrupts */ NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); } /** * @brief Set Pending bit of an external interrupt. * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** * @brief Get Pending Interrupt (read the pending register in the NVIC * and return the pending bit for the specified interrupt). * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } /** * @brief Clear the pending bit of an external interrupt. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } /** * @brief Get active interrupt (read the active register in NVIC and return the active bit). * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) { /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } /** * @brief Configure the SysTick clock source. * @param CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); if (CLKSource == SYSTICK_CLKSOURCE_HCLK) { SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; } else { SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; } } /** * @brief Handle SYSTICK interrupt request. * @retval None */ void HAL_SYSTICK_IRQHandler(void) { HAL_SYSTICK_Callback(); } /** * @brief SYSTICK callback. * @retval None */ __weak void HAL_SYSTICK_Callback(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_SYSTICK_Callback could be implemented in the user file */ } #if (__MPU_PRESENT == 1) /** * @brief Enable the MPU. * @param MPU_Control: Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged accessto the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); /* Ensure MPU setting take effects */ __DSB(); __ISB(); } /** * @brief Disable the MPU. * @retval None */ void HAL_MPU_Disable(void) { /* Make sure outstanding transfers are done */ __DMB(); /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; } /** * @brief Initialize and configure the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; if ((MPU_Init->Enable) != 0U) { /* Check the parameters */ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); MPU->RBAR = MPU_Init->BaseAddress; MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } else { MPU->RBAR = 0x00; MPU->RASR = 0x00; } } #endif /* __MPU_PRESENT */ /** * @} */ /** * @} */ #endif /* HAL_CORTEX_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac.c * @author MCD Application Team * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions * * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### ============================================================================== [..] *** DAC Channels *** ==================== [..] STM32G4 devices integrate up to seven 12-bit Digital Analog Converters, up to six of them grouped by pair forming a DAC instance. The 2 converters of an single instance (i.e. channel1 & channel2) can be used independently or simultaneously (dual mode): (#) DAC channel1 with DAC_OUT1 as output (not for all) or connected to on-chip peripherals (ex. comparators, operational amplifier). (#) DAC channel2 with DAC_OUT2 as output (not for all) or connected to on-chip peripherals (ex. comparators, operational amplifier). Note: when an instance only includes one converter, only independent mode is supported by this converter. STM32G4 instances & converters availability and output PIO mapping (DAC_OUTx): ---------------------------------------------------------------------------- | DAC1 | DAC2 | DAC3 | DAC4 | ---------------------------------------------------------------------------- Channel 1 | | YES | YES | YES | YES | DAC_OUT1 | PA4 | PA6 | - | - ---------------------------------------------------------------------------- Channel 2 | | YES | NO | YES | YES | DAC_OUT2 | PA5 | - | - | - ---------------------------------------------------------------------------- Note: On this STM32 series, all devices do not include each DAC instances listed above. Refer to device datasheet for DACx instance availability. *** DAC Triggers *** ==================== [..] Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. [..] Digital to Analog conversion can be triggered by: (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. The used pin (GPIOx_PIN_9) must be configured in input mode. (#) Timers TRGO: TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM8 and TIM15 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) (#) Software using DAC_TRIGGER_SOFTWARE (#) HRTimer TRGO: HRTIM1 (1) (DAC_TRIGGER_HRTIM_TRG01, DAC_TRIGGER_HRTIM_TRG02...) [..] Specific triggers for sawtooth generation: (#) External event: EXTI Line 10 (any GPIOx_PIN_10) using DAC_TRIGGER_EXT_IT10. The used pin (GPIOx_PIN_10) must be configured in input mode. (#) HRTimer Step & Reset: HRTIM1 (1) (DAC_TRIGGER_HRTIM_RST_TRG1, DAC_TRIGGER_HRTIM_STEP_TRG1...) Note: On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) *** DAC Buffer mode feature *** =============================== [..] Each DAC channel integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. To enable, the output buffer use sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; [..] (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. *** DAC connect feature *** =============================== [..] Each DAC channel can be connected internally. To connect, use sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL; or sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH; *** GPIO configurations guidelines *** ===================== [..] When a DAC channel is used (ex channel1 on PA4) and the other is not (ex channel2 on PA5 is configured in Analog and disabled). Channel1 may disturb channel2 as coupling effect. Note that there is no coupling on channel2 as soon as channel2 is turned on. Coupling on adjacent channel could be avoided as follows: when unused PA5 is configured as INPUT PULL-UP or DOWN. PA5 is configured in ANALOG just before it is turned on. *** DAC Sample and Hold feature *** ======================== [..] For each converter, 2 modes are supported: normal mode and "sample and hold" mode (i.e. low power mode). In the sample and hold mode, the DAC core converts data, then holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is tri-stated, therefore reducing the overall power consumption. A new stabilization period is needed before each new conversion. The sample and hold allow setting internal or external voltage @ low power consumption cost (output value can be at any given rate either by CPU or DMA). The Sample and hold block and registers uses either LSI & run in several power modes: run mode, sleep mode, low power run, low power sleep mode & stop1 mode. Low power stop1 mode allows only static conversion. To enable Sample and Hold mode Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI & RCC_LSI_ON parameters. Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE; & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime, DAC_HoldTime & DAC_RefreshTime; *** DAC calibration feature *** =================================== [..] (#) The 2 converters (channel1 & channel2) provide calibration capabilities. (++) Calibration aims at correcting some offset of output buffer. (++) The DAC uses either factory calibration settings OR user defined calibration (trimming) settings (i.e. trimming mode). (++) The user defined settings can be figured out using self calibration handled by HAL_DACEx_SelfCalibrate. (++) HAL_DACEx_SelfCalibrate: (+++) Runs automatically the calibration. (+++) Enables the user trimming mode (+++) Updates a structure with trimming values with fresh calibration results. The user may store the calibration results for larger (ex monitoring the trimming as a function of temperature for instance) *** DAC wave generation feature *** =================================== [..] Both DAC channels can be used to generate (#) Noise wave (#) Triangle wave (#) Sawtooth wave *** DAC data format *** ======================= [..] The DAC data format can be: (#) 8-bit right alignment using DAC_ALIGN_8B_R (#) 12-bit left alignment using DAC_ALIGN_12B_L (#) 12-bit right alignment using DAC_ALIGN_12B_R *** DAC data value to voltage correspondence *** ================================================ [..] The analog output voltage on each DAC channel pin is determined by the following equation: [..] DAC_OUTx = VREF+ * DOR / 4095 (+) with DOR is the Data Output Register [..] VREF+ is the input voltage reference (refer to the device datasheet) [..] e.g. To set DAC_OUT1 to 0.7V, use (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V *** DMA requests *** ===================== [..] A DMAMUX request can be generated when an external trigger (but not a software trigger) occurs if DMAMUX requests are enabled using HAL_DAC_Start_DMA(). DMAMUX requests are mapped as following: ---------------------------------------------------------------------------- | DAC1 | DAC2 | DAC3 | DAC4 | ---------------------------------------------------------------------------- Channel 1 | | 6 | 41 | 102 | 104 ---------------------------------------------------------------------------- Channel 2 | | 7 | - | 103 | 105 ---------------------------------------------------------------------------- Note: On this STM32 series, all devices do not include each DAC instances listed above. Refer to device datasheet for DACx instance availability. *** High frequency interface mode *** ===================================== [..] The high frequency interface informs DAC instance about the bus frequency in use. It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent) provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function. Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended function figured out the correct setting. The high frequency mode is same for all converters of a same DAC instance. Either same parameter DAC_HighFrequency is used for all DAC converters or again self DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter. [..] (@) For Dual mode and specific signal (Sawtooth, triangle and noise) generation please refer to Extended Features Driver description ##### How to use this driver ##### ============================================================================== [..] (+) DAC APB clock must be enabled to get write access to DAC registers using HAL_DAC_Init() (+) If available & needed, configure DAC_OUTx (DAC_OUT1, DAC_OUT2) in analog mode. (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. *** Calibration mode IO operation *** ====================================== [..] (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset() (+) Run the calibration using HAL_DACEx_SelfCalibrate() (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming() *** Polling mode IO operation *** ================================= [..] (+) Start the DAC peripheral using HAL_DAC_Start() (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. (+) Stop the DAC peripheral using HAL_DAC_Stop() *** DMA mode IO operation *** ============================== [..] (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length of data to be transferred at each end of conversion First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() function is executed and user can add his own code by customization of function pointer HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() *** Callback registration *** ============================================= [..] The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. (+) MspInitCallback : DAC MspInit. (+) MspDeInitCallback : DAC MspdeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. (+) MspInitCallback : DAC MspInit. (+) MspDeInitCallback : DAC MspdeInit. (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively reset to the legacy weak (surcharged) functions in the HAL_DAC_Init and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit or HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. *** DAC HAL driver macros list *** ============================================= [..] Below the list of most used macros in DAC HAL driver. (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status [..] (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ #ifdef HAL_DAC_MODULE_ENABLED #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @defgroup DAC DAC * @brief DAC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup DAC_Private_Constants DAC Private Constants * @{ */ #define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */ #define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */ #define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions -------------------------------------------------------*/ /** @defgroup DAC_Exported_Functions DAC Exported Functions * @{ */ /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DAC. (+) De-initialize the DAC. @endverbatim * @{ */ /** * @brief Initialize the DAC peripheral according to the specified parameters * in the DAC_InitStruct and initialize the associated handle. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { /* Check DAC handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) { #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the DAC Callback settings */ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; if (hdac->MspInitCallback == NULL) { hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Deinitialize the DAC peripheral registers to their default reset values. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { /* Check DAC handle */ if (hdac == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) if (hdac->MspDeInitCallback == NULL) { hdac->MspDeInitCallback = HAL_DAC_MspDeInit; } /* DeInit the low level hardware */ hdac->MspDeInitCallback(hdac); #else /* DeInit the low level hardware */ HAL_DAC_MspDeInit(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; /* Change DAC state */ hdac->State = HAL_DAC_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Initialize the DAC MSP. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file */ } /** * @brief DeInitialize the DAC MSP. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file */ } /** * @} */ /** @defgroup DAC_Exported_Functions_Group2 IO operation functions * @brief IO operation functions * @verbatim ============================================================================== ##### IO operation functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. @endverbatim * @{ */ /** * @brief Enables DAC and starts conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ HAL_Delay(1); if (Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Disables DAC and stop conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); /* Ensure minimum wait before enabling peripheral after disabling it */ HAL_Delay(1); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Enables DAC and starts conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); /* Case of use of channel 1 */ switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R1; break; case DAC_ALIGN_12B_L: /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; case DAC_ALIGN_8B_R: /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; default: break; } } else { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); /* Case of use of channel 2 */ switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12R2; break; case DAC_ALIGN_12B_L: /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; case DAC_ALIGN_8B_R: /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; default: break; } } /* Enable the DMA channel */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Process Unlocked */ __HAL_UNLOCK(hdac); if (status == HAL_OK) { /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); /* Ensure minimum wait before using peripheral after enabling it */ HAL_Delay(1); } else { hdac->ErrorCode |= HAL_DAC_ERROR_DMA; } /* Return function status */ return status; } /** * @brief Disables DAC and stop conversion of channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Disable the selected DAC channel DMA request */ hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); /* Ensure minimum wait before enabling peripheral after disabling it */ HAL_Delay(1); /* Disable the DMA channel */ /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { /* Disable the DMA channel */ (void)HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } else /* Channel2 is used for */ { /* Disable the DMA channel */ (void)HAL_DMA_Abort(hdac->DMA_Handle2); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Handles DAC interrupt request * This function uses the interruption of DMA * underrun. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) { /* Check underrun flag of DAC channel 1 */ if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); /* Disable the selected DAC channel1 DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { /* Check underrun flag of DAC channel 2 */ if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); /* Disable the selected DAC channel2 DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } /** * @brief Set the specified data holding register value for DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { __IO uint32_t tmp = 0UL; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_ALIGN(Alignment)); /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */ if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL) { assert_param(IS_DAC_DATA(Data)); } tmp = (uint32_t)hdac->Instance; if (Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; /* Return function status */ return HAL_OK; } /** * @brief Conversion complete callback in non-blocking mode for Channel1 * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file */ } /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file */ } /** * @brief Error DAC callback for Channel1. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file */ } /** * @brief DMA underrun DAC callback for channel1. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } /** * @} */ /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure channels. (+) Set the specified data holding register value for DAC channel. @endverbatim * @{ */ /** * @brief Returns the last data output value of the selected DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval The selected DAC channel data output value. */ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) { uint32_t result; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); if (Channel == DAC_CHANNEL_1) { result = hdac->Instance->DOR1; } else { result = hdac->Instance->DOR2; } /* Returns the DAC channel data output register value */ return result; } /** * @brief Configures the selected DAC channel. * @note By calling this function, the high frequency interface mode (HFSEL bits) * will be set. This parameter scope is the DAC instance. As the function * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig * must be the same at each call. * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect). * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig DAC configuration structure. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { uint32_t tmpreg1; uint32_t tmpreg2; uint32_t tickstart; uint32_t hclkfreq; uint32_t connectOnChip; /* Check the DAC parameters */ assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger)); assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger2)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) { assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); } assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) { assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) { /* Get timeout */ tickstart = HAL_GetTick(); if (Channel == DAC_CHANNEL_1) { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } else /* Channel 2 */ { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } HAL_Delay(1U); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) { connectOnChip = 0x00000000UL; } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) { connectOnChip = DAC_MCR_MODE1_0; } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) { connectOnChip = DAC_MCR_MODE1_0; } else { connectOnChip = 0x00000000UL; } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); /* Clear DAC_MCR_DMADOUBLEx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: DMA double data mode */ tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; /* Clear DAC_MCR_SINFORMATx */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: Signed format */ tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; /* Clear DAC_MCR_HFSEL bits */ tmpreg1 &= ~(DAC_MCR_HFSEL); /* Configure for both DAC channels: high frequency mode */ if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency) { hclkfreq = HAL_RCC_GetHCLKFreq(); if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ) { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ; } else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ; } else { tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE; } } else { tmpreg1 |= sConfig->DAC_HighFrequency; } /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */ tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; /* Modify STMODR register value depending on DAC_Channel */ MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * @verbatim ============================================================================== ##### Peripheral State and Errors functions ##### ============================================================================== [..] This subsection provides functions allowing to (+) Check the DAC state. (+) Check the DAC Errors. @endverbatim * @{ */ /** * @brief return the DAC handle state * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) { /* Return DAC handle state */ return hdac->State; } /** * @brief Return the DAC error code * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) { return hdac->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup DAC_Exported_Functions * @{ */ /** @addtogroup DAC_Exported_Functions_Group1 * @{ */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** * @brief Register a User DAC Callback * To be used instead of the weak (surcharged) predefined callback * @param hdac DAC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hdac); if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) { case HAL_DAC_CH1_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh1 = pCallback; break; case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh1 = pCallback; break; case HAL_DAC_CH1_ERROR_ID : hdac->ErrorCallbackCh1 = pCallback; break; case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = pCallback; break; case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = pCallback; break; case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh2 = pCallback; break; case HAL_DAC_CH2_ERROR_ID : hdac->ErrorCallbackCh2 = pCallback; break; case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = pCallback; break; case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else if (hdac->State == HAL_DAC_STATE_RESET) { switch (CallbackID) { case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = pCallback; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdac); return status; } /** * @brief Unregister a User DAC Callback * DAC Callback is redirected to the weak (surcharged) predefined callback * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks * @retval status */ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdac); if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) { case HAL_DAC_CH1_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; break; case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; break; case HAL_DAC_CH1_ERROR_ID : hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; break; case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; break; case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; break; case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; break; case HAL_DAC_CH2_ERROR_ID : hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; break; case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; break; case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; case HAL_DAC_ALL_CB_ID : hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; hdac->MspInitCallback = HAL_DAC_MspInit; hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else if (hdac->State == HAL_DAC_STATE_RESET) { switch (CallbackID) { case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; case HAL_DAC_MSPDEINIT_CB_ID : hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; default : /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; break; } } else { /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; /* update return status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdac); return status; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ /** * @} */ /** @addtogroup DAC_Private_Functions * @{ */ /** * @brief DMA conversion complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvCpltCallbackCh1(hdac); #else HAL_DAC_ConvCpltCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @brief DMA half transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Conversion complete callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvHalfCpltCallbackCh1(hdac); #else HAL_DAC_ConvHalfCpltCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ErrorCallbackCh1(hdac); #else HAL_DAC_ErrorCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ #endif /* HAL_DAC_MODULE_ENABLED */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dac_ex.c * @author MCD Application Team * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. * * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] *** Dual mode IO operation *** ============================== [..] (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion for dual mode operation. If software trigger is selected, using HAL_DACEx_DualStart() will start the conversion of the value previously set by HAL_DACEx_DualSetValue(). (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion for dual mode operation. (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion for dual mode operation using DMA to feed DAC converters. First issued trigger will start the conversion of the value previously set by HAL_DACEx_DualSetValue(). The same callbacks that are used in single mode are called in dual mode to notify transfer completion (half complete or complete), errors or underrun. (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion for dual mode operation using DMA to feed DAC converters. (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : Use HAL_DACEx_DualGetValue() to get digital data to be converted and use HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. *** Signal generation operation *** =================================== [..] (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. (+) Use HAL_DACEx_SawtoothWaveGenerate() to generate sawtooth signal. (+) Use HAL_DACEx_SawtoothWaveDataReset() to reset sawtooth wave. (+) Use HAL_DACEx_SawtoothWaveDataStep() to step sawtooth wave. (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel. (+) HAL_DACEx_SetUserTrimming to set user trimming value. (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting after reset, user setting if HAL_DACEx_SetUserTrimming have been used at least one time after reset). @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ #ifdef HAL_DAC_MODULE_ENABLED #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4) /** @defgroup DACEx DACEx * @brief DAC Extended HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup DACEx_Exported_Functions DACEx Exported Functions * @{ */ /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions * @brief Extended IO operation functions * @verbatim ============================================================================== ##### Extended features functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. (+) Get result of dual mode conversion. @endverbatim * @{ */ /** * @brief Enables DAC and starts conversion of both channels. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { uint32_t tmp_swtrig = 0UL; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ HAL_Delay(1); /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG1; } if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL))) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG2; } /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Disables DAC and stop conversion of both channels. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before enabling peripheral after disabling it */ HAL_Delay(1); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The DAC channel that will request data from DMA. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @param pData The destination peripheral Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) { HAL_StatusTypeDef status; uint32_t tmpreg = 0UL; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Ensure Channel 2 exists for this particular DAC instance */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); assert_param(IS_DAC_ALIGN(Alignment)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; /* Set the DMA half transfer complete callback for channel1 */ hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; /* Set the DMA error callback for channel1 */ hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); } else { /* Set the DMA transfer complete callback for channel2 */ hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; /* Set the DMA half transfer complete callback for channel2 */ hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; /* Set the DMA error callback for channel2 */ hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); } switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12RD; break; case DAC_ALIGN_12B_L: /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12LD; break; case DAC_ALIGN_8B_R: /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8RD; break; default: break; } /* Enable the DMA channel */ if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } /* Process Unlocked */ __HAL_UNLOCK(hdac); if (status == HAL_OK) { /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before using peripheral after enabling it */ HAL_Delay(1); } else { hdac->ErrorCode |= HAL_DAC_ERROR_DMA; } /* Return function status */ return status; } /** * @brief Disables DAC and stop conversion both channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The DAC channel that requests data from DMA. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { HAL_StatusTypeDef status; /* Ensure Channel 2 exists for this particular DAC instance */ assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2)); /* Disable the selected DAC channel DMA request */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1); /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); /* Ensure minimum wait before enabling peripheral after disabling it */ HAL_Delay(1); /* Disable the DMA channel */ /* Channel1 is used */ if (Channel == DAC_CHANNEL_1) { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } else { /* Disable the DMA channel */ status = HAL_DMA_Abort(hdac->DMA_Handle2); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } /* Check if DMA Channel effectively disabled */ if (status != HAL_OK) { /* Update DAC state machine to error */ hdac->State = HAL_DAC_STATE_ERROR; } else { /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } /* Return function status */ return status; } /** * @brief Enable or disable the selected DAC channel wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the triangle wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Enable or disable the selected DAC channel wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the noise wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Enable or disable the selected DAC channel sawtooth wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Polarity polarity to be used for wave generation. * This parameter can be one of the following values: * @arg DAC_SAWTOOTH_POLARITY_DECREMENT * @arg DAC_SAWTOOTH_POLARITY_INCREMENT * @param ResetData Sawtooth wave reset value. * Range is from 0 to DAC full range 4095 (0xFFF) * @param StepData Sawtooth wave step value. * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa * Step value step is 1/16 = 0.0625 * Step value range is 0.0000 to 4095.9375 (0xFFF.F) * @note Sawtooth reset and step triggers are configured by calling @ref HAL_DAC_ConfigChannel * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_SAWTOOTH_POLARITY(Polarity)); assert_param(IS_DAC_RESET_DATA(ResetData)); assert_param(IS_DAC_STEP_DATA(StepData)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Configure the sawtooth wave generation data parameters */ MODIFY_REG(hdac->Instance->STR1, DAC_STR1_STINCDATA1 | DAC_STR1_STDIR1 | DAC_STR1_STRSTDATA1, (StepData << DAC_STR1_STINCDATA1_Pos) | Polarity | (ResetData << DAC_STR1_STRSTDATA1_Pos)); } else { /* Configure the sawtooth wave generation data parameters */ MODIFY_REG(hdac->Instance->STR2, DAC_STR2_STINCDATA2 | DAC_STR2_STDIR2 | DAC_STR2_STRSTDATA2, (StepData << DAC_STR2_STINCDATA2_Pos) | Polarity | (ResetData << DAC_STR2_STRSTDATA2_Pos)); } /* Enable the sawtooth wave generation for the selected DAC channel */ MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1) << (Channel & 0x10UL), (uint32_t)(DAC_CR_WAVE1_1 | DAC_CR_WAVE1_0) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; } /** * @brief Trig sawtooth wave reset * @note This function allows to reset sawtooth wave in case of SW trigger * has been configured for this usage. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0UL /* SW TRIGGER */) { /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } else { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } else { status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return status; } /** * @brief Trig sawtooth wave step * @note This function allows to generate step in sawtooth wave in case of * SW trigger has been configured for this usage. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Process locked */ __HAL_LOCK(hdac); if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0UL /* SW TRIGGER */) { /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if (Channel == DAC_CHANNEL_1) { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB1); } else { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB2); } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; } else { status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return status; } /** * @brief Set the specified data holding register value for dual DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) { uint32_t data; uint32_t tmp; /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { data = ((uint32_t)Data2 << 8U) | Data1; } else { data = ((uint32_t)Data2 << 16U) | Data1; } tmp = (uint32_t)hdac->Instance; tmp += DAC_DHR12RD_ALIGNMENT(Alignment); /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; /* Return function status */ return HAL_OK; } /** * @brief Conversion complete callback in non-blocking mode for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file */ } /** * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file */ } /** * @brief Error DAC callback for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file */ } /** * @brief DMA underrun DAC callback for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } /** * @brief Run the self calibration of one DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig DAC channel configuration structure. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming * @retval HAL status * @note Calibration runs about 7 ms. */ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; __IO uint32_t tmp; uint32_t trimmingvalue; uint32_t delta; /* store/restore channel configuration structure purpose */ uint32_t oldmodeconfiguration; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Check the DAC handle allocation */ /* Check if DAC running */ if (hdac == NULL) { status = HAL_ERROR; } else if (hdac->State == HAL_DAC_STATE_BUSY) { status = HAL_ERROR; } else { /* Process locked */ __HAL_LOCK(hdac); /* Store configuration */ oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL))); /* Disable the selected DAC channel */ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); /* Wait for ready bit to be de-asserted */ HAL_Delay(1); /* Set mode in MCR for calibration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); /* Set DAC Channel1 DHR register to the middle value */ tmp = (uint32_t)hdac->Instance; if (Channel == DAC_CHANNEL_1) { tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); } else { tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); } *(__IO uint32_t *) tmp = 0x0800UL; /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); /* Init trimming counter */ /* Medium value */ trimmingvalue = 16UL; delta = 8UL; while (delta != 0UL) { /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ /* i.e. minimum time needed between two calibration steps */ HAL_Delay(1); if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) { /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */ trimmingvalue -= delta; } else { /* DAC_SR_CAL_FLAGx is LOW try lower trimming */ trimmingvalue += delta; } delta >>= 1UL; } /* Still need to check if right calibration is current value or one step below */ /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */ /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ /* i.e. minimum time needed between two calibration steps */ HAL_Delay(1U); if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { /* Trimming is actually one value more */ trimmingvalue++; /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } /* Disable the selected DAC channel calibration */ /* i.e. clear DAC_CR_CENx bit */ CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); sConfig->DAC_TrimmingValue = trimmingvalue; sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; /* Restore configuration */ MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration); /* Process unlocked */ __HAL_UNLOCK(hdac); } return status; } /** * @brief Set the trimming mode and trimming value (user trimming mode applied). * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig DAC configuration structure updated with new DAC trimming value. * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param NewTrimmingValue DAC new trimming value * @retval HAL status */ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); /* Check the DAC handle allocation */ if (hdac == NULL) { status = HAL_ERROR; } else { /* Process locked */ __HAL_LOCK(hdac); /* Set new trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL))); /* Update trimming mode */ sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; sConfig->DAC_TrimmingValue = NewTrimmingValue; /* Process unlocked */ __HAL_UNLOCK(hdac); } return status; } /** * @brief Return the DAC trimming value. * @param hdac DAC handle * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Trimming value : range: 0->31 * */ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); /* Retrieve trimming */ return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); } /** * @} */ /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Set the specified data holding register value for DAC channel. @endverbatim * @{ */ /** * @brief Return the last data output value of the selected DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) { uint32_t tmp = 0UL; tmp |= hdac->Instance->DOR1; tmp |= hdac->Instance->DOR2 << 16UL; /* Returns the DAC channel data output register value */ return tmp; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions * @brief Extended private functions * @{ */ /** * @brief DMA conversion complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvCpltCallbackCh2(hdac); #else HAL_DACEx_ConvCpltCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @brief DMA half transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Conversion complete callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvHalfCpltCallbackCh2(hdac); #else HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** * @brief DMA error callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) { DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ErrorCallbackCh2(hdac); #else HAL_DACEx_ErrorCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ hdac->State = HAL_DAC_STATE_READY; } /** * @} */ /** * @} */ #endif /* DAC1 || DAC2 || DAC3 || DAC4 */ #endif /* HAL_DAC_MODULE_ENABLED */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma.c * @author MCD Application Team * @brief DMA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. (#) For a given Channel, program the required configuration through the following parameters: Channel request, Transfer Direction, Source and Destination data formats, Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX thanks to: (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. (#) Use HAL_DMA_Abort() function to abort the current transfer -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** ================================= [..] (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. *** Interrupt mode IO operation *** =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. In this case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can add his own function to register callbacks with HAL_DMA_RegisterCallback(). *** DMA HAL driver macros list *** ============================================= [..] Below the list of macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @endverbatim */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup DMA DMA * @brief DMA HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions * @{ */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); /** * @} */ /* Exported functions ---------------------------------------------------------*/ /** @defgroup DMA_Exported_Functions DMA Exported Functions * @{ */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Channel priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in reference manual. @endverbatim * @{ */ /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and initialize the associated handle. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp; /* Check the DMA handle allocation */ if (hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ hdma->Instance->CCR = tmp; /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } else { hdma->DMAmuxRequestGen = 0U; hdma->DMAmuxRequestGenStatus = 0U; hdma->DMAmuxRequestGenStatusMask = 0U; } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; /* Allocate lock resource and initialize it */ hdma->Lock = HAL_UNLOCKED; return HAL_OK; } /** * @brief DeInitialize the DMA peripheral. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if (NULL == hdma) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Compute the channel index */ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) { /* DMA1 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->DmaBaseAddress = DMA1; } else { /* DMA2 */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->DmaBaseAddress = DMA2; } /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); /* Reset the DMAMUX channel that corresponds to the DMA channel */ hdma->DMAmuxChannel->CCR = 0; /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Reset Request generator parameters if any */ if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } hdma->DMAmuxRequestGen = 0U; hdma->DMAmuxRequestGenStatus = 0U; hdma->DMAmuxRequestGenStatusMask = 0U; /* Clean callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions * @brief Input and Output operation functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete (+) Handle DMA interrupt request @endverbatim * @{ */ /** * @brief Start the DMA Transfer. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); status = HAL_BUSY; } return status; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; } if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Remain BUSY */ status = HAL_BUSY; } return status; } /** * @brief Abort the DMA Transfer. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if(hdma->State != HAL_DMA_STATE_BUSY) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return status; } /** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } } return status; } /** * @brief Polling for transfer complete. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CompleteLevel Specifies the DMA level complete. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart; if (HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Polling mode not supported in circular mode */ if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC)) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } /* Get the level transfer complete flag */ if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Transfer Complete flag */ temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU); } else { /* Half Transfer Complete flag */ temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU); } /* Get tick */ tickstart = HAL_GetTick(); while (0U == (hdma->DmaBaseAddress->ISR & temp)) { if ((0U != (hdma->DmaBaseAddress->ISR & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } } } /*Check for DMAMUX Request generator (if used) overrun status */ if (hdma->DMAmuxRequestGen != 0U) { /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) { /* Disable the request gen overrun interrupt */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; } } /* Check for DMAMUX Synchronization overrun */ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; } if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)); } /* Process unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; } /** * @brief Handle DMA interrupt request. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { uint32_t flag_it = hdma->DmaBaseAddress->ISR; uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT))) { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); } /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU)); /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_TC))) { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; } /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU)); /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); } } /* Transfer Error Interrupt management **************************************/ else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_TE))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Clear all flags */ hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } else { /* Nothing To Do */ } return; } /** * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = pCallback; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = pCallback; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = pCallback; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = pCallback; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma); if (HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) { case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; break; case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; break; case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; break; case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; break; default: status = HAL_ERROR; break; } } else { status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(hdma); return status; } /** * @} */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state (+) Get error code @endverbatim * @{ */ /** * @brief Return the DMA hande state. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { /* Return DMA handle state */ return hdma->State; } /** * @brief Return the DMA error code. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code */ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) { return hdma->ErrorCode; } /** * @} */ /** * @} */ /** @addtogroup DMA_Private_Functions * @{ */ /** * @brief Sets the DMA Transfer parameter. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; if (hdma->DMAmuxRequestGen != 0U) { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; } /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; /* Memory to Peripheral */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } /* Peripheral to Memory */ else { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } /** * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t dmamux_base_addr; uint32_t channel_number; DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; /* check if instance is not outside the DMA channel range */ if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) { /* DMA1 */ DMAMUX1_ChannelBase = DMAMUX1_Channel0; } else { /* DMA2 */ #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) DMAMUX1_ChannelBase = DMAMUX1_Channel8; #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) DMAMUX1_ChannelBase = DMAMUX1_Channel6; #else DMAMUX1_ChannelBase = DMAMUX1_Channel7; #endif /* STM32G4x1xx) */ } dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); } /** * @brief Updates the DMA handle with the DMAMUX request generator params * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU); } /** * @} */ /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_dma_ex.c * @author MCD Application Team * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: * + Extended features functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The DMA Extension HAL driver can be used as follows: (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used to respectively enable/disable the request generator. (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) @endverbatim */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup DMAEx DMAEx * @brief DMA Extended HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private Constants ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions * @{ */ /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions * @brief Extended features functions * @verbatim =============================================================================== ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used to respectively enable/disable the request generator. @endverbatim * @{ */ /** * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); /*Check if the DMA state is ready */ if (hdma->State == HAL_DMA_STATE_READY) { /* Process Locked */ __HAL_LOCK(hdma); /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ MODIFY_REG(hdma->DMAmuxChannel->CCR, \ (~DMAMUX_CxCR_DMAREQ_ID), \ ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); /* Process UnLocked */ __HAL_UNLOCK(hdma); return HAL_OK; } else { /*DMA State not Ready*/ return HAL_ERROR; } } /** * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : * contains the request generator parameters. * * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) { /* Process Locked */ __HAL_LOCK(hdma); /* Set the request generator new parameters */ hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ ((pRequestGeneratorConfig->RequestNumber - 1U) << (POSITION_VAL(DMAMUX_RGxCR_GNBREQ) & 0x1FU)) | \ pRequestGeneratorConfig->Polarity; /* Process UnLocked */ __HAL_UNLOCK(hdma); return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) { /* Enable the request generator*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) { /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* check if the DMA state is ready and DMA is using a DMAMUX request generator block */ if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) { /* Disable the request generator*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Handles DMAMUX interrupt request. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA channel. * @retval None */ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) { /* Check for DMAMUX Synchronization overrun */ if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) { /* Disable the synchro overrun interrupt */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } if (hdma->DMAmuxRequestGen != 0) { /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) { /* Disable the request gen overrun interrupt */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); } } } } /** * @} */ /** * @} */ #endif /* HAL_DMA_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_exti.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_exti.c * @author MCD Application Team * @brief EXTI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: * functionalities of the General Purpose Input/Output (EXTI) peripheral: * + Initialization and de-initialization functions * + IO operation functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### EXTI Peripheral features ##### ============================================================================== [..] (+) Each Exti line can be configured within this driver. (+) Exti line can be configured in 3 different modes (++) Interrupt (++) Event (++) Both of them (+) Configurable Exti lines can be configured with 3 different triggers (++) Rising (++) Falling (++) Both of them (+) When set in interrupt mode, configurable Exti lines have two different interrupt pending registers which allow to distinguish which transition occurs: (++) Rising edge pending interrupt (++) Falling (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can be selected through multiplexer. ##### How to use this driver ##### ============================================================================== [..] (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). (++) Choose the interrupt line number by setting "Line" member from EXTI_ConfigTypeDef structure. (++) Configure the interrupt and/or event mode using "Mode" member from EXTI_ConfigTypeDef structure. (++) For configurable lines, configure rising and/or falling trigger "Trigger" member from EXTI_ConfigTypeDef structure. (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" member from GPIO_InitTypeDef structure. (#) Get current Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). (++) Provide exiting handle as first parameter. (++) Provide which callback will be registered using one value from EXTI_CallbackIDTypeDef. (++) Provide callback function pointer. (#) Get interrupt pending bit using HAL_EXTI_GetPending(). (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup EXTI * @{ */ /** MISRA C:2012 deviation rule has been granted for following rule: * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out * of bounds [0,3] in following API : * HAL_EXTI_SetConfigLine * HAL_EXTI_GetConfigLine * HAL_EXTI_ClearConfigLine */ #ifdef HAL_EXTI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines ------------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ #define EXTI_MODE_OFFSET 0x08U /* 0x20: offset between MCU IMR/EMR registers */ #define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between MCU Rising/Falling configuration registers */ /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup EXTI_Exported_Functions * @{ */ /** @addtogroup EXTI_Exported_Functions_Group1 * @brief Configuration functions * @verbatim =============================================================================== ##### Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Set configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on EXTI configuration to be set. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check parameters */ assert_param(IS_EXTI_LINE(pExtiConfig->Line)); assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); /* Assign line number to handle */ hexti->Line = pExtiConfig->Line; /* Compute line register offset */ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line position */ linepos = (pExtiConfig->Line & EXTI_PIN_MASK); /* Compute line mask */ maskline = (1uL << linepos); /* Configure triggers for configurable lines */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); /* Configure rising trigger */ regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store rising trigger mode */ *regaddr = regval; /* Configure falling trigger */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store falling trigger mode */ *regaddr = regval; /* Configure gpio port selection in case of gpio exti line */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); SYSCFG->EXTICR[linepos >> 2u] = regval; } } /* Configure interrupt mode : read current mode */ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store interrupt mode */ *regaddr = regval; /* Configure event mode : read current mode */ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Mask or set line */ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) { regval |= maskline; } else { regval &= ~maskline; } /* Store event mode */ *regaddr = regval; return HAL_OK; } /** * @brief Get configuration of a dedicated Exti line. * @param hexti Exti handle. * @param pExtiConfig Pointer on structure to store Exti configuration. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* Store handle line number to configuration structure */ pExtiConfig->Line = hexti->Line; /* Compute line register offset and line mask */ offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line position */ linepos = (pExtiConfig->Line & EXTI_PIN_MASK); /* Compute mask */ maskline = (1uL << linepos); /* 1] Get core mode : interrupt */ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Check if selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Mode = EXTI_MODE_INTERRUPT; } else { pExtiConfig->Mode = EXTI_MODE_NONE; } /* Get event mode */ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); regval = *regaddr; /* Check if selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Mode |= EXTI_MODE_EVENT; } /* Get default Trigger and GPIOSel configuration */ pExtiConfig->Trigger = EXTI_TRIGGER_NONE; pExtiConfig->GPIOSel = 0x00u; /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } /* Get falling configuration */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = *regaddr; /* Check if configuration of selected line is enable */ if ((regval & maskline) != 0x00u) { pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; } /* Get Gpio port selection for gpio lines */ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval >> (SYSCFG_EXTICR1_EXTI1_Pos * ((linepos & 0x03u))))); } } return HAL_OK; } /** * @brief Clear whole configuration of a dedicated Exti line. * @param hexti Exti handle. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); /* compute line register offset and line mask */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* compute line position */ linepos = (hexti->Line & EXTI_PIN_MASK); /* compute line mask */ maskline = (1uL << linepos); /* 1] Clear interrupt mode */ regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* 2] Clear event mode */ regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* 3] Clear triggers in case of configurable lines */ if ((hexti->Line & EXTI_CONFIG) != 0x00u) { regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & ~maskline); *regaddr = regval; /* Get Gpio port selection for gpio lines */ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) { assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); SYSCFG->EXTICR[linepos >> 2u] = regval; } } return HAL_OK; } /** * @brief Register callback for a dedicated Exti line. * @param hexti Exti handle. * @param CallbackID User callback identifier. * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. * @param pPendingCbfn function pointer to be stored as callback. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_EXTI_CB(CallbackID)); switch (CallbackID) { /* set common callback */ case HAL_EXTI_COMMON_CB_ID: hexti->PendingCallback = pPendingCbfn; break; default: hexti->PendingCallback = NULL; status = HAL_ERROR; break; } return status; } /** * @brief Store line number as handle private field. * @param hexti Exti handle. * @param ExtiLine Exti line number. * This parameter can be from 0 to @ref EXTI_LINE_NB. * @retval HAL Status. */ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) { /* Check the parameters */ assert_param(IS_EXTI_LINE(ExtiLine)); /* Check null pointer */ if (hexti == NULL) { return HAL_ERROR; } else { /* Store line number as handle private field */ hexti->Line = ExtiLine; return HAL_OK; } } /** * @} */ /** @addtogroup EXTI_Exported_Functions_Group2 * @brief EXTI IO functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Handle EXTI interrupt request. * @param hexti Exti handle. * @retval none. */ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; uint32_t maskline; uint32_t offset; /* Compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Get pending bit */ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); regval = (*regaddr & maskline); if (regval != 0x00u) { /* Clear pending bit */ *regaddr = maskline; /* Call pending callback */ if (hexti->PendingCallback != NULL) { hexti->PendingCallback(); } } } /** * @brief Get interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge unused * @retval 1 if interrupt is pending else 0. */ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; uint32_t offset; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); UNUSED(Edge); /* Compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line position */ linepos = (hexti->Line & EXTI_PIN_MASK); /* Compute line mask */ maskline = (1uL << linepos); /* Get pending bit */ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); /* return 1 if bit is set else 0 */ regval = ((*regaddr & maskline) >> linepos); return regval; } /** * @brief Clear interrupt pending bit of a dedicated line. * @param hexti Exti handle. * @param Edge unused * @retval None. */ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; uint32_t offset; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); UNUSED(Edge); /* Compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* Compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); /* Get pending register address */ regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset)); /* Clear Pending bit */ *regaddr = maskline; } /** * @brief Generate a software interrupt for a dedicated line. * @param hexti Exti handle. * @retval None. */ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; uint32_t offset; /* Check parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); /* compute line register offset */ offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); /* compute line mask */ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); *regaddr = maskline; } /** * @} */ /** * @} */ #endif /* HAL_EXTI_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash.c * @author MCD Application Team * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + Program operations functions * + Memory Control functions * + Peripheral Errors functions * @verbatim ============================================================================== ##### FLASH peripheral features ##### ============================================================================== [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. [..] The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines. [..] The FLASH main features are: (+) Flash memory read operations (+) Flash memory program/erase operations (+) Read / write protections (+) Option bytes programming (+) Prefetch on I-Code (+) 32 cache lines of 4*64 or 2*128 bits on I-Code (+) 8 cache lines of 4*64 or 2*128 bits on D-Code (+) Error code correction (ECC) : Data in flash are 72-bits word (8 bits added per double word) ##### How to use this driver ##### ============================================================================== [..] This driver provides functions and macros to configure and program the FLASH memory of all STM32G4xx devices. (#) Flash Memory IO Programming functions: (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Program functions: double word and fast program (full row programming) (++) There are two modes of programming : (+++) Polling mode using HAL_FLASH_Program() function (+++) Interrupt mode using HAL_FLASH_Program_IT() function (#) Interrupts and flags management functions: (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() (++) Callback functions are called when the flash operations are finished : HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise HAL_FLASH_OperationErrorCallback() (++) Get error flag status by calling HAL_GetError() (#) Option bytes management functions: (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and HAL_FLASH_OB_Lock() functions (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. In this case, a reset is generated [..] In addition to these functions, this driver includes a set of macros allowing to handle the following operations: (+) Set the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the Instruction cache and the Data cache (+) Reset the Instruction cache and the Data cache (+) Enable/Disable the Flash power-down during low-power run and sleep modes (+) Enable/Disable the Flash interrupts (+) Monitor the Flash flags status @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup FLASH FLASH * @brief FLASH HAL module driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup FLASH_Private_Constants FLASH Private Constants * @{ */ #define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables * @{ */ /** * @brief Variable used for Program/Erase sectors under interruption */ FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, .ErrorCode = HAL_FLASH_ERROR_NONE, .ProcedureOnGoing = FLASH_PROC_NONE, .Address = 0U, .Bank = FLASH_BANK_1, .Page = 0U, .NbPagesToErase = 0U, .CacheToReactivate = FLASH_CACHE_DISABLED}; /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions * @{ */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Functions FLASH Exported Functions * @{ */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions * @brief Programming operation functions * @verbatim =============================================================================== ##### Programming operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the FLASH program operations. @endverbatim * @{ */ /** * @brief Program double word or fast program of a row at a specified address. * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program. * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * This parameter is the data for the double word program and the address where * are stored the data for the row fast program. * * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status; uint32_t prog_bit = 0; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Process Locked */ __HAL_LOCK(&pFlash); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) { /* Program double-word (64-bit) at a specified address */ FLASH_Program_DoubleWord(Address, Data); prog_bit = FLASH_CR_PG; } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) { /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); /* If it is the last row, the bit will be cleared at the end of the operation */ if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) { prog_bit = FLASH_CR_FSTPG; } } else { /* Nothing to do */ } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG or FSTPG Bit */ if (prog_bit != 0U) { CLEAR_BIT(FLASH->CR, prog_bit); } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); /* return status */ return status; } /** * @brief Program double word or fast program of a row at a specified address with interrupt enabled. * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program. * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * This parameter is the data for the double word program and the address where * are stored the data for the row fast program. * * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Process Locked */ __HAL_LOCK(&pFlash); /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if (status != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } else { /* Set internal variables used by the IRQ handler */ if (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; } pFlash.Address = Address; /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) { /* Program double-word (64-bit) at a specified address */ FLASH_Program_DoubleWord(Address, Data); } else if ((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) { /* Fast program a 32 row double-word (64-bit) at a specified address */ FLASH_Program_Fast(Address, (uint32_t)Data); } else { /* Nothing to do */ } } return status; } /** * @brief Handle FLASH interrupt request. * @retval None */ void HAL_FLASH_IRQHandler(void) { uint32_t tmp_page; uint32_t error; FLASH_ProcedureTypeDef procedure; /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); #if defined (FLASH_OPTR_DBANK) CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); #endif /* Disable the FSTPG Bit only if it is the last row programmed */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) { CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG); } /* Check FLASH operation error flags */ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); if (error != 0U) { /* Save the error code */ pFlash.ErrorCode |= error; /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(error); /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; /* FLASH error interrupt user callback */ procedure = pFlash.ProcedureOnGoing; if (procedure == FLASH_PROC_PAGE_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Page); } else if (procedure == FLASH_PROC_MASS_ERASE) { HAL_FLASH_OperationErrorCallback(pFlash.Bank); } else if ((procedure == FLASH_PROC_PROGRAM) || (procedure == FLASH_PROC_PROGRAM_LAST)) { HAL_FLASH_OperationErrorCallback(pFlash.Address); } else { /* Nothing to do */ } /*Stop the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); if (pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) { /* Nb of pages to erased can be decreased */ pFlash.NbPagesToErase--; /* Check if there are still pages to erase*/ if (pFlash.NbPagesToErase != 0U) { /* Indicate user which page has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Page); /* Increment page number */ pFlash.Page++; tmp_page = pFlash.Page; FLASH_PageErase(tmp_page, pFlash.Bank); } else { /* No more pages to Erase */ /* Reset Address and stop Erase pages procedure */ pFlash.Page = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Page); } } else { /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches() ; procedure = pFlash.ProcedureOnGoing; if (procedure == FLASH_PROC_MASS_ERASE) { /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Bank); } else if ((procedure == FLASH_PROC_PROGRAM) || (procedure == FLASH_PROC_PROGRAM_LAST)) { /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(pFlash.Address); } else { /* Nothing to do */ } /*Clear the procedure ongoing*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) { /* Disable End of Operation and Error interrupts */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); /* Process Unlocked */ __HAL_UNLOCK(&pFlash); } } /** * @brief FLASH end of operation interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure: * @arg Mass Erase: Bank number which has been requested to erase * @arg Page Erase: Page which has been erased * (if 0xFFFFFFFF, it means that all the selected pages have been erased) * @arg Program: Address which was selected for data program * @retval None */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file */ } /** * @brief FLASH operation error interrupt callback. * @param ReturnValue The value saved in this parameter depends on the ongoing procedure: * @arg Mass Erase: Bank number which has been requested to erase * @arg Page Erase: Page number which returned an error * @arg Program: Address which was selected for data program * @retval None */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); /* NOTE : This function should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions * @brief Management functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the FLASH memory operations. @endverbatim * @{ */ /** * @brief Unlock the FLASH control register access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY2); /* verify Flash is unlocked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { status = HAL_ERROR; } } return status; } /** * @brief Lock the FLASH control register access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { HAL_StatusTypeDef status = HAL_ERROR; /* Set the LOCK Bit to lock the FLASH Registers access */ SET_BIT(FLASH->CR, FLASH_CR_LOCK); /* verify Flash is locked */ if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U) { status = HAL_OK; } return status; } /** * @brief Unlock the FLASH Option Bytes Registers access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { HAL_StatusTypeDef status = HAL_OK; if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { /* Authorizes the Option Byte register programming */ WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); /* verify option bytes are unlocked */ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { status = HAL_ERROR; } } return status; } /** * @brief Lock the FLASH Option Bytes Registers access. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { HAL_StatusTypeDef status = HAL_ERROR; /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); /* Verify option bytes are locked */ if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U) { status = HAL_OK; } return status; } /** * @brief Launch the option byte loading. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { /* Set the bit to force the option byte reloading */ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); /* Wait for last operation to be completed */ return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); } /** * @} */ /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral Errors functions * @verbatim =============================================================================== ##### Peripheral Errors functions ##### =============================================================================== [..] This subsection permits to get in run-time Errors of the FLASH peripheral. @endverbatim * @{ */ /** * @brief Get the specific FLASH error flag. * @retval FLASH_ErrorCode. The returned value can be: * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag * @arg HAL_FLASH_ERROR_NONE: No error set * @arg HAL_FLASH_ERROR_OP: FLASH Operation error * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error * @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error */ uint32_t HAL_FLASH_GetError(void) { return pFlash.ErrorCode; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @addtogroup FLASH_Private_Functions * @{ */ /** * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operation timeout. * @retval HAL_Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ uint32_t tickstart = HAL_GetTick(); uint32_t error; while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) { if ((HAL_GetTick() - tickstart) > Timeout) { return HAL_TIMEOUT; } } /* Check FLASH operation error flags */ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS); if (error != 0u) { /* Save the error code */ pFlash.ErrorCode |= error; /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(error); return HAL_ERROR; } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); } /* If there is an error flag set */ return HAL_OK; } /** * @brief Program double-word (64-bit) at a specified address. * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) { /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); /* Set PG bit */ SET_BIT(FLASH->CR, FLASH_CR_PG); /* Program first word */ *(uint32_t *)Address = (uint32_t)Data; /* Barrier to ensure programming is performed in 2 steps, in right order (independently of compiler optimization behavior) */ __ISB(); /* Program second word */ *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); } /** * @brief Fast program a row double-word (64-bit) at a specified address. * @param Address specifies the address to be programmed. * @param DataAddress specifies the address where the data are stored. * @retval None */ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) { uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW); uint32_t *dest_addr = (uint32_t *)Address; uint32_t *src_addr = (uint32_t *)DataAddress; uint32_t primask_bit; /* Check the parameters */ assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); /* Set FSTPG bit */ SET_BIT(FLASH->CR, FLASH_CR_FSTPG); /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ primask_bit = __get_PRIMASK(); __disable_irq(); /* Program the double words of the row */ do { *dest_addr = *src_addr; dest_addr++; src_addr++; row_index--; } while (row_index != 0U); /* Exit critical section: restore previous priority mask */ __set_PRIMASK(primask_bit); } /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ex.c * @author MCD Application Team * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extended peripheral: * + Extended programming operations functions * @verbatim ============================================================================== ##### Flash Extended features ##### ============================================================================== [..] Comparing to other previous devices, the FLASH interface for STM32G4xx devices contains the following additional features (+) Capacity up to 512 Kbytes with dual bank architecture supporting read-while-write capability (RWW) (+) Dual bank 64-bits memory organization with possibility of single bank 128-bits (+) Protected areas including WRP, PCROP and Securable memory ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure and program the FLASH memory of all STM32G4xx devices. It includes (#) Flash Memory Erase functions: (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Erase function: Erase pages, or mass erase banks (++) There are two modes of erase : (+++) Polling Mode using HAL_FLASHEx_Erase() (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to: (++) Configure the write protection areas (WRP) (++) Set the Read protection Level (RDP) (++) Program the user Option Bytes (++) Configure the Proprietary Code ReadOut protection areas (PCROP) (++) Configure the Securable memory areas (++) Configure the Boot Lock (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to: (++) Get the configuration of write protection areas (WRP) (++) Get the level of read protection (RDP) (++) Get the value of the user Option Bytes (++) Get the configuration of Proprietary Code ReadOut Protection areas (PCROP) (++) Get the configuration of Securable memory areas (++) Get the status of Boot Lock (#) Activation of Securable memory area: Use HAL_FLASHEx_EnableSecMemProtection() (++) Deny the access to securable memory area (#) Enable or disable debugger: Use HAL_FLASHEx_EnableDebugger() or HAL_FLASHEx_DisableDebugger() @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup FLASHEx FLASHEx * @brief FLASH Extended HAL module driver * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions * @{ */ static void FLASH_MassErase(uint32_t Banks); static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel); static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr); static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); static uint32_t FLASH_OB_GetRDP(void); static uint32_t FLASH_OB_GetUser(void); static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr); static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecMemBank, uint32_t SecMemSize); static void FLASH_OB_GetSecMem(uint32_t SecMemBank, uint32_t *SecMemSize); static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig); static uint32_t FLASH_OB_GetBootLock(void); /** * @} */ /* Exported functions -------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions * @{ */ /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions * @brief Extended IO operation functions * @verbatim =============================================================================== ##### Extended programming operation functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the Extended FLASH programming operations Operations. @endverbatim * @{ */ /** * @brief Perform a mass erase or erase the specified FLASH memory pages. * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * @param[out] PageError pointer to variable that contains the configuration * information on faulty page in case of error (0xFFFFFFFF means that all * the pages have been correctly erased). * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { HAL_StatusTypeDef status; uint32_t page_index; /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Process Locked */ __HAL_LOCK(&pFlash); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /* Mass erase to be done */ FLASH_MassErase(pEraseInit->Banks); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); #if defined (FLASH_OPTR_DBANK) /* If the erase operation is completed, disable the MER1 and MER2 Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); #else /* If the erase operation is completed, disable the MER1 Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1)); #endif } else { /*Initialization of PageError variable*/ *PageError = 0xFFFFFFFFU; for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) { FLASH_PageErase(page_index, pEraseInit->Banks); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); /* If the erase operation is completed, disable the PER Bit */ CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB)); if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty page */ *PageError = page_index; break; } } } /* Flush the caches to be sure of the data consistency */ FLASH_FlushCaches(); } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Deactivate the cache if they are activated to avoid data misbehavior */ if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; } } else if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; } else { pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } /* Enable End of Operation and Error interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); pFlash.Bank = pEraseInit->Banks; if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /* Mass erase to be done */ pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE; FLASH_MassErase(pEraseInit->Banks); } else { /* Erase by page to be done */ pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE; pFlash.NbPagesToErase = pEraseInit->NbPages; pFlash.Page = pEraseInit->Page; /*Erase 1st page and wait for IT */ FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); } return status; } /** * @brief Program Option bytes. * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @retval HAL_Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /* Process Locked */ __HAL_LOCK(&pFlash); pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; /* Write protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) { /* Configure of Write protection on the selected area */ if (FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK) { status = HAL_ERROR; } } /* Read protection configuration */ if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) { /* Configure the Read protection level */ if (FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) { status = HAL_ERROR; } } /* User Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) { /* Configure the user option bytes */ if (FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) { status = HAL_ERROR; } } /* PCROP Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) { if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) { /* Configure the Proprietary code readout protection */ if (FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK) { status = HAL_ERROR; } } } /* Securable memory Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0U) { /* Configure the securable memory area */ if (FLASH_OB_SecMemConfig(pOBInit->SecBank, pOBInit->SecSize) != HAL_OK) { status = HAL_ERROR; } } /* Boot Entry Point Configuration */ if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) { /* Configure the boot unique entry point option */ if (FLASH_OB_BootLockConfig(pOBInit->BootEntryPoint) != HAL_OK) { status = HAL_ERROR; } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } /** * @brief Get the Option bytes configuration. * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the * configuration information. * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate * which area is requested for the WRP and PCROP, else no information will be returned. * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) { pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); #if defined (FLASH_OPTR_DBANK) if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) #else if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB)) #endif { pOBInit->OptionType |= OPTIONBYTE_WRP; /* Get write protection on the selected area */ FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); } /* Get Read protection level */ pOBInit->RDPLevel = FLASH_OB_GetRDP(); /* Get the user option bytes */ pOBInit->USERConfig = FLASH_OB_GetUser(); #if defined (FLASH_OPTR_DBANK) if ((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) #else if (pOBInit->PCROPConfig == FLASH_BANK_1) #endif { pOBInit->OptionType |= OPTIONBYTE_PCROP; /* Get the Proprietary code readout protection */ FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr)); } pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK; /* Get the boot entry point */ pOBInit->BootEntryPoint = FLASH_OB_GetBootLock(); /* Get the securable memory area configuration */ #if defined (FLASH_OPTR_DBANK) if ((pOBInit->SecBank == FLASH_BANK_1) || (pOBInit->SecBank == FLASH_BANK_2)) #else if (pOBInit->SecBank == FLASH_BANK_1) #endif { pOBInit->OptionType |= OPTIONBYTE_SEC; FLASH_OB_GetSecMem(pOBInit->SecBank, &(pOBInit->SecSize)); } } /** * @brief Enable the FLASH Securable Memory protection. * @param Bank: Bank to be protected * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be protected * @arg FLASH_BANK_2: Bank2 to be protected (*) * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected (*) * @note (*) availability depends on devices * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank) { #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) { /* Check the parameters */ assert_param(IS_FLASH_BANK(Bank)); /* Enable the Securable Memory Protection Bit for the bank 1 if requested */ if ((Bank & FLASH_BANK_1) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1); } /* Enable the Securable Memory Protection Bit for the bank 2 if requested */ if ((Bank & FLASH_BANK_2) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT2); } } else #endif { SET_BIT(FLASH->CR, FLASH_CR_SEC_PROT1); } return HAL_OK; } /** * @brief Enable Debugger. * @note After calling this API, flash interface allow debugger intrusion. * @retval None */ void HAL_FLASHEx_EnableDebugger(void) { FLASH->ACR |= FLASH_ACR_DBG_SWEN; } /** * @brief Disable Debugger. * @note After calling this API, Debugger is disabled: it's no more possible to * break, see CPU register, etc... * @retval None */ void HAL_FLASHEx_DisableDebugger(void) { FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @addtogroup FLASHEx_Private_Functions * @{ */ /** * @brief Mass erase of FLASH memory. * @param Banks Banks to be erased. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased (*) * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased (*) * @note (*) availability depends on devices * @retval None */ static void FLASH_MassErase(uint32_t Banks) { #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U) #endif { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); /* Set the Mass Erase Bit for the bank 1 if requested */ if ((Banks & FLASH_BANK_1) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER1); } #if defined (FLASH_OPTR_DBANK) /* Set the Mass Erase Bit for the bank 2 if requested */ if ((Banks & FLASH_BANK_2) != 0U) { SET_BIT(FLASH->CR, FLASH_CR_MER2); } #endif } #if defined (FLASH_OPTR_DBANK) else { SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); } #endif /* Proceed to erase all sectors */ SET_BIT(FLASH->CR, FLASH_CR_STRT); } /** * @brief Erase the specified FLASH memory page. * @param Page FLASH page to erase. * This parameter must be a value between 0 and (max number of pages in the bank - 1). * @param Banks Bank where the page will be erased. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Page in bank 1 to be erased * @arg FLASH_BANK_2: Page in bank 2 to be erased (*) * @note (*) availability depends on devices * @retval None */ void FLASH_PageErase(uint32_t Page, uint32_t Banks) { /* Check the parameters */ assert_param(IS_FLASH_PAGE(Page)); #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } else { assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); if ((Banks & FLASH_BANK_1) != 0U) { CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); } else { SET_BIT(FLASH->CR, FLASH_CR_BKER); } } #endif /* Proceed to erase the page */ MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos)); SET_BIT(FLASH->CR, FLASH_CR_PER); SET_BIT(FLASH->CR, FLASH_CR_STRT); } /** * @brief Flush the instruction and data caches. * @retval None */ void FLASH_FlushCaches(void) { FLASH_CacheTypeDef cache = pFlash.CacheToReactivate; /* Flush instruction cache */ if ((cache == FLASH_CACHE_ICACHE_ENABLED) || (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); /* Reset instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); /* Enable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); } /* Flush data cache */ if ((cache == FLASH_CACHE_DCACHE_ENABLED) || (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) { /* Reset data cache */ __HAL_FLASH_DATA_CACHE_RESET(); /* Enable data cache */ __HAL_FLASH_DATA_CACHE_ENABLE(); } /* Reset internal variable */ pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; } /** * @brief Configure the write protection area into Option Bytes. * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase Flash memory if the CPU debug * features are connected (JTAG or single wire) or boot code is being * executed from RAM or System flash, even if WRP is not activated. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param WRPArea specifies the area to be configured. * This parameter can be one of the following values: * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (*) * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (*) * @note (*) availability depends on devices * @param WRPStartOffset specifies the start page of the write protected area. * This parameter can be page number between 0 and (max number of pages in the bank - 1). * @param WRDPEndOffset specifies the end page of the write protected area. * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1). * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_WRPAREA(WRPArea)); assert_param(IS_FLASH_PAGE(WRPStartOffset)); assert_param(IS_FLASH_PAGE(WRDPEndOffset)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Configure the write protected area */ if (WRPArea == OB_WRPAREA_BANK1_AREAA) { FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset); } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) { FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset); } #if defined (FLASH_OPTR_DBANK) else if (WRPArea == OB_WRPAREA_BANK2_AREAA) { FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset); } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) { FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset); } #endif else { /* Nothing to do */ } /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Set the read protection level into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible * to go back to level 1 or 0 !!! * @param RDPLevel specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Memory Read protection * @arg OB_RDP_LEVEL_2: Full chip protection * * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(RDPLevel)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Configure the RDP level in the option bytes register */ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Program the FLASH User Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param UserType The FLASH User Option Bytes to be modified. * This parameter can be a combination of @ref FLASH_OB_USER_Type. * @param UserConfig The selected User Option Bytes values: * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY , * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW, * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_nBOOT1, * @ref FLASH_OB_USER_SRAM_PE, @ref FLASH_OB_USER_CCMSRAM_RST, * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, * @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER * @note (*) availability depends on devices * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) { uint32_t optr_reg_val = 0; uint32_t optr_reg_mask = 0; HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_USER_TYPE(UserType)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { if ((UserType & OB_USER_BOR_LEV) != 0U) { /* BOR level option byte should be modified */ assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); /* Set value and mask for BOR level option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); optr_reg_mask |= FLASH_OPTR_BOR_LEV; } if ((UserType & OB_USER_nRST_STOP) != 0U) { /* nRST_STOP option byte should be modified */ assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); /* Set value and mask for nRST_STOP option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); optr_reg_mask |= FLASH_OPTR_nRST_STOP; } if ((UserType & OB_USER_nRST_STDBY) != 0U) { /* nRST_STDBY option byte should be modified */ assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); /* Set value and mask for nRST_STDBY option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); optr_reg_mask |= FLASH_OPTR_nRST_STDBY; } if ((UserType & OB_USER_nRST_SHDW) != 0U) { /* nRST_SHDW option byte should be modified */ assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); /* Set value and mask for nRST_SHDW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); optr_reg_mask |= FLASH_OPTR_nRST_SHDW; } if ((UserType & OB_USER_IWDG_SW) != 0U) { /* IWDG_SW option byte should be modified */ assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); /* Set value and mask for IWDG_SW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); optr_reg_mask |= FLASH_OPTR_IWDG_SW; } if ((UserType & OB_USER_IWDG_STOP) != 0U) { /* IWDG_STOP option byte should be modified */ assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); /* Set value and mask for IWDG_STOP option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); optr_reg_mask |= FLASH_OPTR_IWDG_STOP; } if ((UserType & OB_USER_IWDG_STDBY) != 0U) { /* IWDG_STDBY option byte should be modified */ assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); /* Set value and mask for IWDG_STDBY option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; } if ((UserType & OB_USER_WWDG_SW) != 0U) { /* WWDG_SW option byte should be modified */ assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); /* Set value and mask for WWDG_SW option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); optr_reg_mask |= FLASH_OPTR_WWDG_SW; } #if defined (FLASH_OPTR_BFB2) if ((UserType & OB_USER_BFB2) != 0U) { /* BFB2 option byte should be modified */ assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); /* Set value and mask for BFB2 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2); optr_reg_mask |= FLASH_OPTR_BFB2; } #endif if ((UserType & OB_USER_nBOOT1) != 0U) { /* nBOOT1 option byte should be modified */ assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); /* Set value and mask for nBOOT1 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1); optr_reg_mask |= FLASH_OPTR_nBOOT1; } if ((UserType & OB_USER_SRAM_PE) != 0U) { /* SRAM_PE option byte should be modified */ assert_param(IS_OB_USER_SRAM_PARITY(UserConfig & FLASH_OPTR_SRAM_PE)); /* Set value and mask for SRAM_PE option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE); optr_reg_mask |= FLASH_OPTR_SRAM_PE; } if ((UserType & OB_USER_CCMSRAM_RST) != 0U) { /* CCMSRAM_RST option byte should be modified */ assert_param(IS_OB_USER_CCMSRAM_RST(UserConfig & FLASH_OPTR_CCMSRAM_RST)); /* Set value and mask for CCMSRAM_RST option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST); optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST; } if ((UserType & OB_USER_nSWBOOT0) != 0U) { /* nSWBOOT0 option byte should be modified */ assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); /* Set value and mask for nSWBOOT0 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); optr_reg_mask |= FLASH_OPTR_nSWBOOT0; } if ((UserType & OB_USER_nBOOT0) != 0U) { /* nBOOT0 option byte should be modified */ assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); /* Set value and mask for nBOOT0 option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); optr_reg_mask |= FLASH_OPTR_nBOOT0; } if ((UserType & OB_USER_NRST_MODE) != 0U) { /* Reset Configuration option byte should be modified */ assert_param(IS_OB_USER_NRST_MODE(UserConfig & FLASH_OPTR_NRST_MODE)); /* Set value and mask for Reset Configuration option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_NRST_MODE); optr_reg_mask |= FLASH_OPTR_NRST_MODE; } if ((UserType & OB_USER_IRHEN) != 0U) { /* IRH option byte should be modified */ assert_param(IS_OB_USER_IRHEN(UserConfig & FLASH_OPTR_IRHEN)); /* Set value and mask for IRH option byte */ optr_reg_val |= (UserConfig & FLASH_OPTR_IRHEN); optr_reg_mask |= FLASH_OPTR_IRHEN; } /* Configure the option bytes register */ MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Configure the Proprietary code readout protection area into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option). * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 (*) * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE. * @note (*) availability depends on devices * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection. * This parameter can be an address between begin and end of the bank. * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection. * This parameter can be an address between PCROPStartAddr and end of the bank. * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) { HAL_StatusTypeDef status; uint32_t reg_value; uint32_t bank1_addr; #if defined (FLASH_OPTR_DBANK) uint32_t bank2_addr; #endif /* Check the parameters */ assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH)); assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr)); assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { #if defined (FLASH_OPTR_DBANK) /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; } else { bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; bank2_addr = FLASH_BASE; } #else bank1_addr = FLASH_BASE; #endif #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { /* Configure the Proprietary code readout protection */ if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } else { /* Nothing to do */ } } else #endif { /* Configure the Proprietary code readout protection */ if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = ((PCROPStartAddr - bank1_addr) >> 3); MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); reg_value = ((PCROPEndAddr - bank1_addr) >> 3); MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); } #if defined (FLASH_OPTR_DBANK) else if ((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = ((PCROPStartAddr - bank2_addr) >> 3); MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); reg_value = ((PCROPEndAddr - bank2_addr) >> 3); MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); } #endif else { /* Nothing to do */ } } MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Configure the Securable memory area into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param SecBank specifies bank of securable memory area to be configured. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Securable memory in Bank1 to be configured * @arg FLASH_BANK_2: Securable memory in Bank2 to be configured (*) * @note (*) availability depends on devices * @param SecSize specifies the number of pages of the Securable memory area, * starting from first page of the bank. * This parameter can be page number between 0 and (max number of pages in the bank - 1) * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_SecMemConfig(uint32_t SecBank, uint32_t SecSize) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_FLASH_BANK_EXCLUSIVE(SecBank)); assert_param(IS_OB_SECMEM_SIZE(SecSize)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { /* Configure the write protected area */ if (SecBank == FLASH_BANK_1) { MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1, SecSize); } #if defined (FLASH_OPTR_DBANK) else if (SecBank == FLASH_BANK_2) { MODIFY_REG(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2, SecSize); } else { /* Nothing to do */ } #endif /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Configure the Boot Lock into Option Bytes. * @note To configure any option bytes, the option lock bit OPTLOCK must be * cleared with the call of HAL_FLASH_OB_Unlock() function. * @note New option bytes configuration will be taken into account in two cases: * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() * - after a power reset (BOR reset or exit from Standby/Shutdown modes) * @param BootLockConfig specifies the boot lock configuration. * This parameter can be one of the following values: * @arg OB_BOOT_LOCK_ENABLE: Enable Boot Lock * @arg OB_BOOT_LOCK_DISABLE: Disable Boot Lock * * @retval HAL_Status */ static HAL_StatusTypeDef FLASH_OB_BootLockConfig(uint32_t BootLockConfig) { HAL_StatusTypeDef status; /* Check the parameters */ assert_param(IS_OB_BOOT_LOCK(BootLockConfig)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); if (status == HAL_OK) { MODIFY_REG(FLASH->SEC1R, FLASH_SEC1R_BOOT_LOCK, BootLockConfig); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); } return status; } /** * @brief Return the Securable memory area configuration into Option Bytes. * @param[in] SecBank specifies the bank where securable memory area is located. * This parameter can be one of the following values: * @arg FLASH_BANK_1: Securable memory in Bank1 * @arg FLASH_BANK_2: Securable memory in Bank2 (*) * @note (*) availability depends on devices * @param[out] SecSize specifies the number of pages used in the securable memory area of the bank. * @retval None */ static void FLASH_OB_GetSecMem(uint32_t SecBank, uint32_t *SecSize) { /* Get the configuration of the securable memory area */ if (SecBank == FLASH_BANK_1) { *SecSize = READ_BIT(FLASH->SEC1R, FLASH_SEC1R_SEC_SIZE1); } #if defined (FLASH_OPTR_DBANK) else if (SecBank == FLASH_BANK_2) { *SecSize = READ_BIT(FLASH->SEC2R, FLASH_SEC2R_SEC_SIZE2); } else { /* Nothing to do */ } #endif } /** * @brief Return the Boot Lock configuration into Option Byte. * @retval BootLockConfig. * This return value can be one of the following values: * @arg OB_BOOT_LOCK_ENABLE: Boot lock enabled * @arg OB_BOOT_LOCK_DISABLE: Boot lock disabled */ static uint32_t FLASH_OB_GetBootLock(void) { return (READ_REG(FLASH->SEC1R) & FLASH_SEC1R_BOOT_LOCK); } /** * @brief Return the Write Protection configuration into Option Bytes. * @param[in] WRPArea specifies the area to be returned. * This parameter can be one of the following values: * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32G43x/STM32G44x devices) * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32G43x/STM32G44x devices) * @param[out] WRPStartOffset specifies the address where to copied the start page * of the write protected area. * @param[out] WRDPEndOffset specifies the address where to copied the end page of * the write protected area. * @retval None */ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset) { /* Get the configuration of the write protected area */ if (WRPArea == OB_WRPAREA_BANK1_AREAA) { *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos); } else if (WRPArea == OB_WRPAREA_BANK1_AREAB) { *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos); } #if defined (FLASH_OPTR_DBANK) else if (WRPArea == OB_WRPAREA_BANK2_AREAA) { *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos); } else if (WRPArea == OB_WRPAREA_BANK2_AREAB) { *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos); } #endif else { /* Nothing to do */ } } /** * @brief Return the FLASH Read Protection level into Option Bytes. * @retval RDP_Level * This return value can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory * @arg OB_RDP_LEVEL_2: Full chip protection */ static uint32_t FLASH_OB_GetRDP(void) { uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) { return (OB_RDP_LEVEL_1); } else { return rdp_level; } } /** * @brief Return the FLASH User Option Byte value. * @retval OB_user_config * This return value is a combination of @ref FLASH_OB_USER_BOR_LEVEL, * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_WWDG_SW, * @ref FLASH_OB_USER_BFB2 (*), @ref FLASH_OB_USER_DBANK (*), * @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE, * @ref FLASH_OB_USER_CCMSRAM_RST, @ref OB_USER_nSWBOOT0,@ref FLASH_OB_USER_nBOOT0, * @ref FLASH_OB_USER_NRST_MODE, @ref FLASH_OB_USER_INTERNAL_RESET_HOLDER * @note (*) availability depends on devices */ static uint32_t FLASH_OB_GetUser(void) { uint32_t user_config = READ_REG(FLASH->OPTR); CLEAR_BIT(user_config, FLASH_OPTR_RDP); return user_config; } /** * @brief Return the FLASH PCROP configuration into Option Bytes. * @param[in,out] PCROPConfig specifies the configuration (Bank to be configured and PCROP_RDP option). * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE. * @param[out] PCROPStartAddr specifies the address where to copied the start address * of the Proprietary code readout protection. * @param[out] PCROPEndAddr specifies the address where to copied the end address of * the Proprietary code readout protection. * @retval None */ static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr) { uint32_t reg_value; uint32_t bank1_addr; #if defined (FLASH_OPTR_DBANK) uint32_t bank2_addr; /* Get the information about the bank swapping */ if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U) { bank1_addr = FLASH_BASE; bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; } else { bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; bank2_addr = FLASH_BASE; } #else bank1_addr = FLASH_BASE; #endif #if defined (FLASH_OPTR_DBANK) if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U) { if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; } else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; } else { /* Nothing to do */ } } else #endif { if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) { reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); *PCROPStartAddr = (reg_value << 3) + bank1_addr; reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); *PCROPEndAddr = (reg_value << 3) + bank1_addr; } #if defined (FLASH_OPTR_DBANK) else if (((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) { reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); *PCROPStartAddr = (reg_value << 3) + bank2_addr; reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); *PCROPEndAddr = (reg_value << 3) + bank2_addr; } #endif else { /* Nothing to do */ } } *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); } /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_flash_ramfunc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_flash_ramfunc.c * @author MCD Application Team * @brief FLASH RAMFUNC driver. * This file provides a Flash firmware functions which should be * executed from internal SRAM * + FLASH Power Down in Run mode * + FLASH DBANK User Option Byte * * @verbatim ============================================================================== ##### Flash RAM functions ##### ============================================================================== *** ARM Compiler *** -------------------- [..] RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the Options for Target' dialog. *** ICCARM Compiler *** ----------------------- [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". *** GNU Compiler *** -------------------- [..] RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC * @brief FLASH functions executed from RAM * @{ */ #ifdef HAL_FLASH_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions -------------------------------------------------------*/ /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH_RAMFUNC Exported Functions * @{ */ /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions * @brief Data transfers functions * @verbatim =============================================================================== ##### ramfunc functions ##### =============================================================================== [..] This subsection provides a set of functions that should be executed from RAM. @endverbatim * @{ */ /** * @brief Enable the Power down in Run Mode * @note This function should be called and executed from SRAM memory. * @retval None */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void) { /* Enable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_ENABLE(); return HAL_OK; } /** * @brief Disable the Power down in Run Mode * @note This function should be called and executed from SRAM memory. * @retval None */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) { /* Disable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_DISABLE(); return HAL_OK; } #if defined (FLASH_OPTR_DBANK) /** * @brief Program the FLASH DBANK User Option Byte. * * @note To configure the user option bytes, the option lock bit OPTLOCK must * be cleared with the call of the HAL_FLASH_OB_Unlock() function. * @note To modify the DBANK option byte, no PCROP region should be defined. * To deactivate PCROP, user should perform RDP changing. * * @param DBankConfig The FLASH DBANK User Option Byte value. * This parameter can be one of the following values: * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data * * @retval HAL_Status */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) { uint32_t count, reg; HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ __HAL_LOCK(&pFlash); /* Check if the PCROP is disabled */ reg = FLASH->PCROP1SR; if (reg > FLASH->PCROP1ER) { reg = FLASH->PCROP2SR; if (reg > FLASH->PCROP2ER) { /* Disable Flash prefetch */ __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) { /* Disable Flash instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); /* Flush Flash instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_RESET(); } if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) { /* Disable Flash data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); /* Flush Flash data cache */ __HAL_FLASH_DATA_CACHE_RESET(); } /* Disable WRP zone A of 1st bank if needed */ reg = FLASH->WRP1AR; if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <= ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos)) { MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); } /* Disable WRP zone B of 1st bank if needed */ reg = FLASH->WRP1BR; if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <= ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos)) { MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); } /* Disable WRP zone A of 2nd bank if needed */ reg = FLASH->WRP2AR; if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <= ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos)) { MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); } /* Disable WRP zone B of 2nd bank if needed */ reg = FLASH->WRP2BR; if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <= ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos)) { MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); } /* Modify the DBANK user option byte */ MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); /* Set OPTSTRT Bit */ SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Wait for last operation to be completed */ /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U); do { if (count == 0U) { break; } count--; } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); /* If the option byte program operation is completed, disable the OPTSTRT Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); /* Set the bit to force the option byte reloading */ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); return status; } #endif /** * @} */ /** * @} */ #endif /* HAL_FLASH_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_gpio.c * @author MCD Application Team * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### ============================================================================== [..] (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: (++) Input mode (++) Analog mode (++) Output mode (++) Alternate function mode (++) External interrupt/event lines (+) During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. (+) The microcontroller IO pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an IO pin at a time. In this way, there can be no conflict between peripherals sharing the same IO pin. (+) All ports have external interrupt/event capability. To use external interrupt lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. (+) The external interrupt/event controller consists of up to 44 edge detectors (16 lines are connected to GPIO) for generating event/interrupt requests (each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also be masked independently. ##### How to use this driver ##### ============================================================================== [..] (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure. (++) In alternate mode is selection, the alternate function connected to the IO is configured through "Alternate" member from GPIO_InitTypeDef structure. (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. (++) In case of external interrupt/event selection the "Mode" member from GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general purpose PF0 and PF1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @addtogroup GPIO * @{ */ /** MISRA C:2012 deviation rule has been granted for following rules: * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of * range of the shift operator in following API : * HAL_GPIO_Init * HAL_GPIO_DeInit */ #ifdef HAL_GPIO_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ #define GPIO_NUMBER (16U) /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions * @{ */ /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0x00U; uint32_t iocurrent; uint32_t temp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); temp |= (GPIO_Init->Speed << (position * 2U)); GPIOx->OSPEEDR = temp; /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT0 << position) ; temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; temp &= ~(0xFU << ((position & 0x07U) * 4U)); temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); GPIOx->AFR[position >> 3U] = temp; } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); GPIOx->MODER = temp; /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2U]; temp &= ~(0x0FUL << (4U * (position & 0x03U))); temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } EXTI->RTSR1 = temp; temp = EXTI->FTSR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } EXTI->FTSR1 = temp; temp = EXTI->EMR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } EXTI->EMR1 = temp; /* Clear EXTI line configuration */ temp = EXTI->IMR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } EXTI->IMR1 = temp; } } position++; } } /** * @brief De-initialize the GPIOx peripheral registers to their default reset values. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bit to be written. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { uint32_t position = 0x00U; uint32_t iocurrent; uint32_t tmp; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0U) { /* Get current io position */ iocurrent = (GPIO_Pin) & (1UL << position); if (iocurrent != 0x00u) { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = SYSCFG->EXTICR[position >> 2U]; tmp &= (0x0FUL << (4U * (position & 0x03U))); if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { /* Clear EXTI line configuration */ EXTI->IMR1 &= ~(iocurrent); EXTI->EMR1 &= ~(iocurrent); /* Clear Rising Falling edge configuration */ EXTI->FTSR1 &= ~(iocurrent); EXTI->RTSR1 &= ~(iocurrent); tmp = 0x0FUL << (4U * (position & 0x03U)); SYSCFG->EXTICR[position >> 2U] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)); /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); } position++; } } /** * @} */ /** @addtogroup GPIO_Exported_Functions_Group2 * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Read the specified input port pin. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bit to read. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) { bitstatus = GPIO_PIN_SET; } else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } /** * @brief Set or clear the selected data port bit. * * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bit to be written. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) { GPIOx->BSRR = (uint32_t)GPIO_Pin; } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } /** * @brief Toggle the specified GPIO pin. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the pin to be toggled. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { uint32_t odr; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** * @brief Lock GPIO Pins configuration registers. * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. * @param GPIOx where x can be (A..G) to select the GPIO peripheral for STM32G4xx family * @param GPIO_Pin specifies the port bits to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { __IO uint32_t tmp = GPIO_LCKR_LCKK; /* Check the parameters */ assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Apply lock key write sequence */ tmp |= GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; /* Read LCKK register. This read is mandatory to complete key lock sequence */ tmp = GPIOx->LCKR; /* read again in order to confirm lock is active */ if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) { return HAL_OK; } else { return HAL_ERROR; } } /** * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } } /** * @brief EXTI line detection callback. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* Prevent unused argument(s) compilation warning */ UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Callback could be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_GPIO_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr.c * @author MCD Application Team * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization/de-initialization functions * + Peripheral Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup PWR PWR * @brief PWR HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup PWR_Private_Defines PWR Private Defines * @{ */ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ /** * @} */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup PWR_Exported_Functions PWR Exported Functions * @{ */ /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] @endverbatim * @{ */ /** * @brief Deinitialize the HAL PWR peripheral registers to their default reset values. * @retval None */ void HAL_PWR_DeInit(void) { __HAL_RCC_PWR_FORCE_RESET(); __HAL_RCC_PWR_RELEASE_RESET(); } /** * @brief Enable access to the backup domain * (RTC registers, RTC backup data registers). * @note After reset, the backup domain is protected against * possible unwanted write accesses. * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. * In order to set or modify the RTC clock, the backup domain access must be * disabled. * @note LSEON bit that switches on and off the LSE crystal belongs as well to the * back-up domain. * @retval None */ void HAL_PWR_EnableBkUpAccess(void) { SET_BIT(PWR->CR1, PWR_CR1_DBP); } /** * @brief Disable access to the backup domain * (RTC registers, RTC backup data registers). * @retval None */ void HAL_PWR_DisableBkUpAccess(void) { CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); } /** * @} */ /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] *** PVD configuration *** ========================= [..] (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register). (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through __HAL_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. *** WakeUp pin configuration *** ================================ [..] (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. The polarity of these pins can be set to configure event detection on high level (rising edge) or low level (falling edge). *** Low Power modes configuration *** ===================================== [..] The devices feature 8 low-power modes: (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on. (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on. (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on. (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. *** Low-power run mode *** ========================== [..] (+) Entry: (from main run mode) (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. (+) Exit: (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only then can the system clock frequency be increased above 2 MHz. *** Sleep mode / Low-power sleep mode *** ========================================= [..] (+) Entry: The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction (+) WFI Exit: (++) Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) or any wake-up event. (+) WFE Exit: (++) Any wake-up event such as an EXTI line configured in event mode. [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, the MCU is in Low-power Run mode. *** Stop 0, Stop 1 modes *** =============================== [..] (+) Entry: The Stop 0, Stop 1 modes are entered through the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (++) PWR_MAINREGULATOR_ON (++) PWR_LOWPOWERREGULATOR_ON (+) Exit (interrupt or event-triggered, specified when entering STOP mode): (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction (+) WFI Exit: (++) Any EXTI Line (Internal or External) configured in Interrupt mode. (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts when programmed in wakeup mode. (+) WFE Exit: (++) Any EXTI Line (Internal or External) configured in Event mode. [..] When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode depending on the LPR bit setting. *** Standby mode *** ==================== [..] The Standby mode offers two options: (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers and Standby circuitry. (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). SRAM and register contents are lost except for the RTC registers, RTC backup registers and Standby circuitry. (++) Entry: (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API to set RRS bit. (++) Exit: (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. *** Shutdown mode *** ====================== [..] In Shutdown mode, voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. SRAM and registers contents are lost except for backup domain registers. (+) Entry: The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API. (+) Exit: (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, external reset in NRST pin. [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event or a time-stamp event, without depending on an external interrupt (Auto-wakeup mode). (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to configure the RTC to detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. @endverbatim * @{ */ /** * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD * configuration information. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each * detection level. * @retval None */ HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); /* Set PLS bits according to PVDLevel value */ MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } return HAL_OK; } /** * @brief Enable the Power Voltage Detector (PVD). * @retval None */ void HAL_PWR_EnablePVD(void) { SET_BIT(PWR->CR2, PWR_CR2_PVDE); } /** * @brief Disable the Power Voltage Detector (PVD). * @retval None */ void HAL_PWR_DisablePVD(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); } /** * @brief Enable the WakeUp PINx functionality. * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. * This parameter can be one of the following legacy values which set the default polarity * i.e. detection on high level (rising edge): * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 * * or one of the following value where the user can explicitly specify the enabled pin and * the chosen polarity: * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) { assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); /* Specifies the Wake-Up pin polarity for the event detection (rising or falling edge) */ MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); /* Enable wake-up pin */ SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); } /** * @brief Disable the WakeUp PINx functionality. * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); } /** * @brief Enter Sleep or Low-power Sleep mode. * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode. * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must * be done before calling HAL_PWR_EnterSLEEPMode() API. * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction * @note When WFI entry is used, tick interrupt have to be disabled if not desired as * the interrupt wake up source. * @retval None */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Set Regulator parameter */ if (Regulator == PWR_MAINREGULATOR_ON) { /* If in low-power run mode at this point, exit it */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) { (void)HAL_PWREx_DisableLowPowerRunMode(); } /* Regulator now in main mode. */ } else { /* If in run mode, first move to low-power run mode. The system clock frequency must be below 2 MHz at this point. */ if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == 0U) { HAL_PWREx_EnableLowPowerRunMode(); } } /* Clear SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } } /** * @brief Enter Stop mode * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running * on devices where only "Stop mode" is mentioned with main or low power regulator ON. * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note All clocks in the VCORE domain are stopped; the PLL, * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode (Stop 1), an additional * startup delay is incurred when waking up. * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption * is higher although the startup time is reduced. * @param Regulator: Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction. * @retval None */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); if(Regulator == PWR_LOWPOWERREGULATOR_ON) { HAL_PWREx_EnterSTOP1Mode(STOPEntry); } else { HAL_PWREx_EnterSTOP0Mode(STOPEntry); } } /** * @brief Enter Standby mode. * @note In Standby mode, the PLL, the HSI and the HSE oscillators are switched * off. The voltage regulator is disabled, except when SRAM2 content is preserved * in which case the regulator is in low-power mode. * SRAM1 and register contents are lost except for registers in the Backup domain and * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API * to set RRS bit. * The BOR is available. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the * same. * These states are effective in Standby mode only if APC bit is set through * HAL_PWREx_EnablePullUpPullDownConfig() API. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) { /* Set Stand-by mode */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) { /* Set SLEEPONEXIT bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) { /* Clear SLEEPONEXIT bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); } /** * @brief Enable CORTEX M4 SEVONPEND bit. * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_EnableSEVOnPend(void) { /* Set SEVONPEND bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief Disable CORTEX M4 SEVONPEND bit. * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) { /* Clear SEVONPEND bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); } /** * @brief PWR PVD interrupt callback * @retval None */ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function should not be modified; when the callback is needed, the HAL_PWR_PVDCallback can be implemented in the user file */ } /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_pwr_ex.c * @author MCD Application Team * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup PWREx PWREx * @brief PWR Extended HAL module driver * @{ */ #ifdef HAL_PWR_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) #define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */ #define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */ #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx) #define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */ #define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */ #endif /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines * @{ */ /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask * @{ */ #define PVM_MODE_IT 0x00010000U /*!< Mask for interruption yielded by PVM threshold crossing */ #define PVM_MODE_EVT 0x00020000U /*!< Mask for event yielded by PVM threshold crossing */ #define PVM_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as PVM trigger */ #define PVM_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as PVM trigger */ /** * @} */ /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value * @{ */ #define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */ /** * @} */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions * @{ */ /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Extended Peripheral Initialization and de-initialization functions ##### =============================================================================== [..] @endverbatim * @{ */ /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) */ uint32_t HAL_PWREx_GetVoltageRange(void) { if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) { return PWR_REGULATOR_VOLTAGE_SCALE2; } else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) { /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ return PWR_REGULATOR_VOLTAGE_SCALE1; } else { return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; } } /** * @brief Configure the main internal regulator output voltage. * @param VoltageScaling: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, * typical output voltage at 1.28 V, * system frequency up to 170 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, * typical output voltage at 1.2 V, * system frequency up to 150 MHz. * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, * typical output voltage at 1.0 V, * system frequency up to 26 MHz. * @note When moving from Range 1 to Range 2, the system frequency must be decreased to * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 2 to Range 1, the system frequency can be increased to * a value up to 150 MHz after calling HAL_PWREx_ControlVoltageScaling() API. * When moving from Range 1 to Boost Mode Range 1, the system frequency can be increased to * a value up to 170 MHz after calling HAL_PWREx_ControlVoltageScaling() API. * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; } } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); } } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { return HAL_TIMEOUT; } } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; } /** * @brief Enable battery charging. * When VDD is present, charge the external battery on VBAT through an internal resistor. * @param ResistorSelection: specifies the resistor impedance. * This parameter can be one of the following values: * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor * @retval None */ void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) { assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); /* Specify resistor selection */ MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); /* Enable battery charging */ SET_BIT(PWR->CR4, PWR_CR4_VBE); } /** * @brief Disable battery charging. * @retval None */ void HAL_PWREx_DisableBatteryCharging(void) { CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); } /** * @brief Enable Internal Wake-up Line. * @retval None */ void HAL_PWREx_EnableInternalWakeUpLine(void) { SET_BIT(PWR->CR3, PWR_CR3_EIWF); } /** * @brief Disable Internal Wake-up Line. * @retval None */ void HAL_PWREx_DisableInternalWakeUpLine(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); } /** * @brief Enable GPIO pull-up state in Standby and Shutdown modes. * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in * pull-up state in Standby and Shutdown modes. * @note This state is effective in Standby and Shutdown modes only if APC bit * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. * @note The configuration is lost when exiting the Shutdown mode due to the * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding * PDy bit of PWR_PDCRx register is cleared unless it is reserved. * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input * parameter at the same time are set. * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to set * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); break; case PWR_GPIO_B: SET_BIT(PWR->PUCRB, GPIONumber); CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); break; case PWR_GPIO_C: SET_BIT(PWR->PUCRC, GPIONumber); CLEAR_BIT(PWR->PDCRC, GPIONumber); break; case PWR_GPIO_D: SET_BIT(PWR->PUCRD, GPIONumber); CLEAR_BIT(PWR->PDCRD, GPIONumber); break; case PWR_GPIO_E: SET_BIT(PWR->PUCRE, GPIONumber); CLEAR_BIT(PWR->PDCRE, GPIONumber); break; case PWR_GPIO_F: SET_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: SET_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O * in pull-up state in Standby and Shutdown modes. * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input * parameter at the same time are reset. * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to reset * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); break; case PWR_GPIO_B: CLEAR_BIT(PWR->PUCRB, GPIONumber); break; case PWR_GPIO_C: CLEAR_BIT(PWR->PUCRC, GPIONumber); break; case PWR_GPIO_D: CLEAR_BIT(PWR->PUCRD, GPIONumber); break; case PWR_GPIO_E: CLEAR_BIT(PWR->PUCRE, GPIONumber); break; case PWR_GPIO_F: CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Enable GPIO pull-down state in Standby and Shutdown modes. * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in * pull-down state in Standby and Shutdown modes. * @note This state is effective in Standby and Shutdown modes only if APC bit * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. * @note The configuration is lost when exiting the Shutdown mode due to the * power-on reset, maintained when exiting the Standby mode. * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding * PUy bit of PWR_PUCRx register is cleared unless it is reserved. * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input * parameter at the same time are set. * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to set * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); break; case PWR_GPIO_B: SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); CLEAR_BIT(PWR->PUCRB, GPIONumber); break; case PWR_GPIO_C: SET_BIT(PWR->PDCRC, GPIONumber); CLEAR_BIT(PWR->PUCRC, GPIONumber); break; case PWR_GPIO_D: SET_BIT(PWR->PDCRD, GPIONumber); CLEAR_BIT(PWR->PUCRD, GPIONumber); break; case PWR_GPIO_E: SET_BIT(PWR->PDCRE, GPIONumber); CLEAR_BIT(PWR->PUCRE, GPIONumber); break; case PWR_GPIO_F: SET_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); CLEAR_BIT(PWR->PUCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: SET_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); CLEAR_BIT(PWR->PUCRG, (GPIONumber & PWR_PORTG_AVAILABLE_PINS)); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Disable GPIO pull-down state in Standby and Shutdown modes. * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O * in pull-down state in Standby and Shutdown modes. * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input * parameter at the same time are reset. * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_G * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. * @param GPIONumber: Specify the I/O pins numbers. * This parameter can be one of the following values: * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less * I/O pins are available) or the logical OR of several of them to reset * several bits for a given port in a single API call. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_PWR_GPIO(GPIO)); assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); switch (GPIO) { case PWR_GPIO_A: CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); break; case PWR_GPIO_B: CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); break; case PWR_GPIO_C: CLEAR_BIT(PWR->PDCRC, GPIONumber); break; case PWR_GPIO_D: CLEAR_BIT(PWR->PDCRD, GPIONumber); break; case PWR_GPIO_E: CLEAR_BIT(PWR->PDCRE, GPIONumber); break; case PWR_GPIO_F: CLEAR_BIT(PWR->PDCRF, (GPIONumber & PWR_PORTF_AVAILABLE_PINS)); break; case PWR_GPIO_G: CLEAR_BIT(PWR->PDCRG, ((GPIONumber & PWR_PORTG_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_10)))); break; default: status = HAL_ERROR; break; } return status; } /** * @brief Enable pull-up and pull-down configuration. * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there * is no conflict when setting PUy or PDy bit. * @retval None */ void HAL_PWREx_EnablePullUpPullDownConfig(void) { SET_BIT(PWR->CR3, PWR_CR3_APC); } /** * @brief Disable pull-up and pull-down configuration. * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. * @retval None */ void HAL_PWREx_DisablePullUpPullDownConfig(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_APC); } /** * @brief Enable SRAM2 content retention in Standby mode. * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in * Standby mode and its content is kept. * @retval None */ void HAL_PWREx_EnableSRAM2ContentRetention(void) { SET_BIT(PWR->CR3, PWR_CR3_RRS); } /** * @brief Disable SRAM2 content retention in Standby mode. * @note When RRS bit is reset, SRAM2 is powered off in Standby mode * and its content is lost. * @retval None */ void HAL_PWREx_DisableSRAM2ContentRetention(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); } #if defined(PWR_CR2_PVME1) /** * @brief Enable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage. * @retval None */ void HAL_PWREx_EnablePVM1(void) { SET_BIT(PWR->CR2, PWR_PVM_1); } /** * @brief Disable the Power Voltage Monitoring 1: VDDA versus FASTCOMP minimum voltage. * @retval None */ void HAL_PWREx_DisablePVM1(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_1); } #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) /** * @brief Enable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage. * @retval None */ void HAL_PWREx_EnablePVM2(void) { SET_BIT(PWR->CR2, PWR_PVM_2); } /** * @brief Disable the Power Voltage Monitoring 2: VDDA versus FASTDAC minimum voltage. * @retval None */ void HAL_PWREx_DisablePVM2(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_2); } #endif /* PWR_CR2_PVME2 */ /** * @brief Enable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V. * @retval None */ void HAL_PWREx_EnablePVM3(void) { SET_BIT(PWR->CR2, PWR_PVM_3); } /** * @brief Disable the Power Voltage Monitoring 3: VDDA versus ADC minimum voltage 1.62V. * @retval None */ void HAL_PWREx_DisablePVM3(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_3); } /** * @brief Enable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V. * @retval None */ void HAL_PWREx_EnablePVM4(void) { SET_BIT(PWR->CR2, PWR_PVM_4); } /** * @brief Disable the Power Voltage Monitoring 4: VDDA versus OPAMP/DAC minimum voltage 1.8V. * @retval None */ void HAL_PWREx_DisablePVM4(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_4); } /** * @brief Configure the Peripheral Voltage Monitoring (PVM). * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the * PVM configuration information. * @note The API configures a single PVM according to the information contained * in the input structure. To configure several PVMs, the API must be singly * called for each PVM used. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage thresholds corresponding to each * detection level and to each monitored supply. * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); /* Configure EXTI 35 to 38 interrupts if so required: scan through PVMType to detect which PVMx is set and configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { #if defined(PWR_CR2_PVME1) case PWR_PVM_1: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM1_EXTI_DISABLE_IT(); __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM1_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); } break; #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) case PWR_PVM_2: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM2_EXTI_DISABLE_IT(); __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM2_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); } break; #endif /* PWR_CR2_PVME2 */ case PWR_PVM_3: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM3_EXTI_DISABLE_IT(); __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM3_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); } break; case PWR_PVM_4: /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM4_EXTI_DISABLE_IT(); __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM4_EXTI_ENABLE_IT(); } /* Configure event mode */ if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); } /* Configure the edge */ if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); } if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); } break; default: status = HAL_ERROR; break; } return status; } /** * @brief Enter Low-power Run mode * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. * Additionally, the clock frequency must be reduced below 2 MHz. * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. * @retval None */ void HAL_PWREx_EnableLowPowerRunMode(void) { /* Set Regulator parameter */ SET_BIT(PWR->CR1, PWR_CR1_LPR); } /** * @brief Exit Low-power Run mode. * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode * returns HAL_TIMEOUT status). The system clock frequency can then be * increased above 2 MHz. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { uint32_t wait_loop_index; /* Clear LPR bit */ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); /* Wait until REGLPF is reset */ wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000U)); while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) { return HAL_TIMEOUT; } return HAL_OK; } /** * @brief Enter Stop 0 mode. * @note In Stop 0 mode, main and low voltage regulators are ON. * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. * @note All clocks in the VCORE domain are stopped; the PLL, the HSI * and the HSE oscillators are disabled. Some peripherals with the wakeup capability * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register * is set; the HSI oscillator is selected if STOPWUCK is cleared. * @note By keeping the internal regulator ON during Stop 0 mode, the consumption * is higher although the startup time is reduced. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction * @retval None */ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); /* Stop 0 mode with Main Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ if(STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Enter Stop 1 mode. * @note In Stop 1 mode, only low power voltage regulator is ON. * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. * @note All clocks in the VCORE domain are stopped; the PLL, the HSI * and the HSE oscillators are disabled. Some peripherals with the wakeup capability * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated * only to the peripheral requesting it. * SRAM1, SRAM2 and register contents are preserved. * The BOR is available. * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register * is set. * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction * @retval None */ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) { /* Check the parameters */ assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); /* Stop 1 mode with Low-Power Regulator */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ if(STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __SEV(); __WFE(); __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Enter Shutdown mode. * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched * off. The voltage regulator is disabled and Vcore domain is powered off. * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. * The BOR is not available. * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. * @retval None */ void HAL_PWREx_EnterSHUTDOWNMode(void) { /* Set Shutdown mode */ MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @brief This function handles the PWR PVD/PVMx interrupt request. * @note This API should be called under the PVD_PVM_IRQHandler(). * @retval None */ void HAL_PWREx_PVD_PVM_IRQHandler(void) { /* Check PWR exti flag */ if(__HAL_PWR_PVD_EXTI_GET_FLAG() != 0U) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); /* Clear PVD exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } /* Next, successively check PVMx exti flags */ #if defined(PWR_CR2_PVME1) if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) { /* PWR PVM1 interrupt user callback */ HAL_PWREx_PVM1Callback(); /* Clear PVM1 exti pending bit */ __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); } #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != 0U) { /* PWR PVM2 interrupt user callback */ HAL_PWREx_PVM2Callback(); /* Clear PVM2 exti pending bit */ __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); } #endif /* PWR_CR2_PVME2 */ if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) { /* PWR PVM3 interrupt user callback */ HAL_PWREx_PVM3Callback(); /* Clear PVM3 exti pending bit */ __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); } if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != 0U) { /* PWR PVM4 interrupt user callback */ HAL_PWREx_PVM4Callback(); /* Clear PVM4 exti pending bit */ __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); } } #if defined(PWR_CR2_PVME1) /** * @brief PWR PVM1 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM1Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM1Callback() API can be implemented in the user file */ } #endif /* PWR_CR2_PVME1 */ #if defined(PWR_CR2_PVME2) /** * @brief PWR PVM2 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM2Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM2Callback() API can be implemented in the user file */ } #endif /* PWR_CR2_PVME2 */ /** * @brief PWR PVM3 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM3Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM3Callback() API can be implemented in the user file */ } /** * @brief PWR PVM4 interrupt callback * @retval None */ __weak void HAL_PWREx_PVM4Callback(void) { /* NOTE : This function should not be modified; when the callback is needed, HAL_PWREx_PVM4Callback() API can be implemented in the user file */ } #if defined(PWR_CR3_UCPD_STDBY) /** * @brief Enable UCPD configuration memorization in Standby. * @retval None */ void HAL_PWREx_EnableUCPDStandbyMode(void) { /* Memorize UCPD configuration when entering standby mode */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } /** * @brief Disable UCPD configuration memorization in Standby. * @note This function must be called on exiting the Standby mode and before any UCPD * configuration update. * @retval None */ void HAL_PWREx_DisableUCPDStandbyMode(void) { /* Write 0 immediately after Standby exit when using UCPD, and before writing any UCPD registers */ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } #endif /* PWR_CR3_UCPD_STDBY */ #if defined(PWR_CR3_UCPD_DBDIS) /** * @brief Enable the USB Type-C dead battery pull-down behavior * on UCPDx_CC1 and UCPDx_CC2 pins * @retval None */ void HAL_PWREx_EnableUCPDDeadBattery(void) { /* Write 0 to enable the USB Type-C dead battery pull-down behavior */ CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } /** * @brief Disable the USB Type-C dead battery pull-down behavior * on UCPDx_CC1 and UCPDx_CC2 pins * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, * which may have a pull-down effect on CC1 and CC2 pins. * It is recommended to disable it in all cases, either to stop this pull-down * or to hand over control to the UCPD (which should therefore be * initialized before doing the disable). * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } #endif /* PWR_CR3_UCPD_DBDIS */ /** * @} */ /** * @} */ #endif /* HAL_PWR_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc.c * @author MCD Application Team * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions * @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== [..] After reset the device is running from High Speed Internal oscillator (16 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in analog mode, except the JTAG pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs, UCPD, I2S, I2C, LPTIM, ADC, QSPI) @endverbatim ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup RCC RCC * @brief RCC HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ #define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK) #define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS) #define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS) #define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__))) #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCC_Private_Functions RCC Private Functions * @{ */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ */ /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal and external oscillators (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC clock source. (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also optionally as RTC clock source. (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks: (++) The first output is used to generate the high speed system clock (up to 170 MHz). (++) The second output is used to generate the clock for the USB (48 MHz), the QSPI (<= 48 MHz), the FDCAN, the SAI and the I2S. (++) The third output is used to generate a clock for ADC (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs (HSE used directly or through PLL as System clock source), the System clock is automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE, main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin. [..] System, AHB and APB buses clocks configuration (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and main PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these buses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 2 to 31. You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) USB FS and RNG: USB FS requires a frequency equal to 48 MHz to work correctly, while the RNG peripheral requires a frequency equal or lower than to 48 MHz. This clock is derived of the main PLL through PLLQ divider. You have to enable the peripheral clock and use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) IWDG clock which is always the LSI clock. (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 170 MHz. The clock source frequency should be adapted depending on the device voltage range as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. @endverbatim Table 1. HCLK clock frequency for STM32G4xx devices +----------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |----------------------------------------------------------| | | voltage range 1 | voltage range 1 | voltage range 2 | | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | |-----------------|-------------------|-------------------|------------------| |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 13 | |-----------------|-------------------|-------------------|------------------| |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 26 | |-----------------|-------------------|-------------------|------------------| |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | - | |-----------------|-------------------|-------------------|------------------| |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | |-----------------|-------------------|-------------------|------------------| |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | +----------------------------------------------------------------------------+ * @{ */ /** * @brief Reset the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 OFF * - All interrupts disabled * - All interrupt and reset flags cleared * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Set HSION bit to the reset value */ SET_BIT(RCC->CR, RCC_CR_HSION); /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Set HSITRIM[6:0] bits to the reset value */ SET_BIT(RCC->ICSCR, RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Reset CFGR register (HSI is selected as system clock source) */ RCC->CFGR = 0x00000001u; /* Wait till HSI is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ RCC->CR = RCC_CR_HSION; /* Then again to HSEBYP in case bypass was enabled */ RCC->CR = RCC_CR_HSION; /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is OFF */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* once PLL is OFF, reset PLLCFGR register to default value */ RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4; /* Disable all interrupts */ CLEAR_REG(RCC->CIER); /* Clear all interrupt flags */ WRITE_REG(RCC->CICR, 0xFFFFFFFFU); /* Clear all reset flags */ SET_BIT(RCC->CSR, RCC_CSR_RMVF); return HAL_OK; } /** * @brief Initialize the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not * supported by this macro. User should request a transition to LSE Off * first and then LSE On or LSE Bypass. * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) { /* When HSI is used as system clock it will not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) { return HAL_ERROR; } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { FlagStatus pwrclkchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, RCC_OscInitStruct->PLL.PLLM, RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); /* Disable all PLL outputs to save power if no PLLs on */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) { return HAL_ERROR; } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) { return HAL_ERROR; } } } } return HAL_OK; } /** * @brief Initialize the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. * @param FLatency FLASH Latency * This parameter can be one of the following values: * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used by default as system clock source after * startup from Reset, wake-up from STANDBY mode. After restart from Reset, * the HSI frequency is set to its default value 16 MHz. * * @note The HSI can be selected as system clock source after * from STOP modes or in case of failure of the HSE used directly or indirectly * as system clock (if the Clock Security System CSS is enabled). * * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source is ready. * * @note You can use HAL_RCC_GetClockConfig() function to know which clock is * currently used as system clock source. * * @note Depending on the device voltage range, the software has to set correctly * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart; uint32_t pllfreq; uint32_t hpre = RCC_SYSCLK_DIV1; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* PLL is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) { return HAL_ERROR; } /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ pllfreq = RCC_GetSysClockFreqFromPLLSource(); /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ if(pllfreq > 80000000U) { if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); hpre = RCC_SYSCLK_DIV2; } } } else { /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) { return HAL_ERROR; } } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) { return HAL_ERROR; } } /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ pllfreq = HAL_RCC_GetSysClockFreq(); /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ if(pllfreq > 80000000U) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); hpre = RCC_SYSCLK_DIV2; } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); /* Get Start Tick*/ tickstart = HAL_GetTick(); while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } else { /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ if(hpre == RCC_SYSCLK_DIV2) { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); while (__HAL_FLASH_GET_LATENCY() != FLatency) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); } /** * @} */ /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to: (+) Output clock to MCO pin. (+) Retrieve current clock frequencies. (+) Enable the Clock Security System. @endverbatim * @{ */ /** * @brief Select the clock source to output on MCO pin(PA8/PG10). * @note PA8/PG10 should be configured in alternate function mode. * @note The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin) * and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it * as an MCO pin. * The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value. * @param RCC_MCOx specifies the output direction for the clock source. * For STM32G4xx family this parameter can have only one value: * @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8). * @arg @ref RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10). * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 * @param RCC_MCODiv specifies the MCO prescaler. * This parameter can be one of the following values: * @arg @ref RCC_MCODIV_1 no division applied to MCO clock * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock * @retval None */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio_initstruct; uint32_t mcoindex; uint32_t mco_gpio_index; GPIO_TypeDef * mco_gpio_port; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); /* Common GPIO init parameters */ gpio_initstruct.Mode = GPIO_MODE_AF_PP; gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; gpio_initstruct.Pull = GPIO_NOPULL; /* Get MCOx selection */ mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK; /* Get MCOx GPIO Port */ mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx); /* MCOx Clock Enable */ mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx); SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index )); /* Configure the MCOx pin in alternate function mode */ gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx); gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx); HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct); if (mcoindex == RCC_MCO1_INDEX) { assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); } } /** * @brief Return the SYSCLK frequency. * * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), * HSI_VALUE(*) Value multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32g4xx_hal_conf.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) { /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; } else { sysclockfreq = 0U; } return sysclockfreq; } /** * @brief Return the HCLK frequency. * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { return SystemCoreClock; } /** * @brief Return the PCLK1 frequency. * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); } /** * @brief Return the PCLK2 frequency. * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); } /** * @brief Configure the RCC_OscInitStruct according to the internal * RCC configuration registers. * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check the parameters */ assert_param(RCC_OscInitStruct != (void *)NULL); /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; /* Get the HSE configuration -----------------------------------------------*/ if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } else { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } /* Get the HSI configuration -----------------------------------------------*/ if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } else { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; /* Get the LSE configuration -----------------------------------------------*/ if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } else { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } /* Get the LSI configuration -----------------------------------------------*/ if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } else { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } /* Get the HSI48 configuration ---------------------------------------------*/ if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) { RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; } else { RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; } /* Get the PLL configuration -----------------------------------------------*/ if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } else { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; } /** * @brief Configure the RCC_ClkInitStruct according to the internal * RCC configuration registers. * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Check the parameters */ assert_param(RCC_ClkInitStruct != (void *)NULL); assert_param(pFLatency != (void *)NULL); /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = __HAL_FLASH_GET_LATENCY(); } /** * @brief Enable the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @note The Clock Security System can only be cleared by reset. * @retval None */ void HAL_RCC_EnableCSS(void) { SET_BIT(RCC->CR, RCC_CR_CSSON) ; } /** * @brief Enable the LSE Clock Security System. * @note If a failure is detected on the external 32 kHz oscillator, * the LSE clock is no longer supplied to the RTC but no hardware action * is made to the registers. If enabled, an interrupt will be generated * and handle through @ref RCCEx_EXTI_LINE_LSECSS * @note The Clock Security System can only be cleared by reset or after a LSE failure detection. * @retval None */ void HAL_RCC_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; } /** * @brief Disable the LSE Clock Security System. * @note After LSE failure detection, the software must disable LSECSSON * @note The Clock Security System can only be cleared by reset otherwise. * @retval None */ void HAL_RCC_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; } /** * @brief Handle the RCC Clock Security System interrupt request. * @note This API should be called under the NMI_Handler(). * @retval None */ void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF interrupt flag */ if(__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); } } /** * @brief RCC Clock Security System interrupt callback. * @retval none */ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_RCC_CSSCallback should be implemented in the user file */ } /** * @} */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup RCC_Private_Functions * @{ */ /** * @brief Compute SYSCLK frequency based on PLL SYSCLK source. * @retval SYSCLK frequency */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; switch (pllsource) { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); break; } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; sysclockfreq = pllvco/pllr; return sysclockfreq; } /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_rcc_ex.c * @author MCD Application Team * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extended peripheral: * + Extended Peripheral Control functions * + Extended Clock management functions * + Extended Clock Recovery System Control functions * ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file in * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup RCCEx RCCEx * @brief RCC Extended HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants * @{ */ #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ #define DIVIDER_P_UPDATE 0U #define DIVIDER_Q_UPDATE 1U #define DIVIDER_R_UPDATE 2U #define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define LSCO_GPIO_PORT GPIOA #define LSCO_PIN GPIO_PIN_2 /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions * @{ */ /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions * @{ */ /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions * @brief Extended Peripheral Control functions * @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the RCC Clocks frequencies. [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values. @endverbatim * @{ */ /** * @brief Initialize the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains a field PeriphClockSelection which can be a combination of the following values: * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN) * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5) * @arg @ref RCC_PERIPHCLK_QSPI QuadSPI peripheral clock (only for devices with QuadSPI) * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ HAL_StatusTypeDef status = HAL_OK; /* Final status */ /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) { FlagStatus pwrclkchanged = RESET; /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while((PWR->CR1 & PWR_CR1_DBP) == 0U) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { ret = HAL_TIMEOUT; break; } } if(ret == HAL_OK) { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { ret = HAL_TIMEOUT; break; } } } if(ret == HAL_OK) { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } else { /* set overall return value */ status = ret; } } else { /* set overall return value */ status = ret; } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); } /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); } #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); } #endif /* UART4 */ #if defined(UART5) /*-------------------------- UART5 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); } /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); } #if defined(I2C4) /*-------------------------- I2C4 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); } } #if defined(ADC345_COMMON) /*-------------------------- ADC345 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) { /* Check the parameters */ assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection)); /* Configure the ADC345 interface clock source */ __HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection); if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL) { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); } } #endif /* ADC345_COMMON */ #if defined(QUADSPI) /*-------------------------- QuadSPIx clock source configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) { /* Check the parameters */ assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection)); /* Configure the QuadSPI clock source */ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL) { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); } } #endif /* QUADSPI */ return status; } /** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals * clocks(USART1, USART2, USART3, UART4, UART5, LPUART1, I2C1, I2C2, I2C3, I2C4, * LPTIM1, SAI1, I2Sx, FDCANx, USB, RNG, ADCx, RTC, QSPI). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ #if defined(STM32G474xx) || defined(STM32G484xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_I2C4 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G491xx) || defined(STM32G4A1xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G473xx) || defined(STM32G483xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_I2C4 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G471xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_UART5 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_I2C4 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_RTC; #elif defined(STM32G431xx) || defined(STM32G441xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_RTC; #elif defined(STM32GBK1CB) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \ RCC_PERIPHCLK_RTC; #endif /* STM32G431xx */ /* Get the USART1 clock source ---------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); /* Get the USART2 clock source ---------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); /* Get the USART3 clock source ---------------------------------------------*/ PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); #if defined(UART4) /* Get the UART4 clock source ----------------------------------------------*/ PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); #endif /* UART4 */ #if defined(UART5) /* Get the UART5 clock source ----------------------------------------------*/ PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); #endif /* UART5 */ /* Get the LPUART1 clock source --------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); /* Get the I2C1 clock source -----------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); /* Get the I2C2 clock source ----------------------------------------------*/ PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); /* Get the I2C3 clock source -----------------------------------------------*/ PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); #if defined(I2C4) /* Get the I2C4 clock source -----------------------------------------------*/ PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); #endif /* I2C4 */ /* Get the LPTIM1 clock source ---------------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); /* Get the SAI1 clock source -----------------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); /* Get the I2S clock source -----------------------------------------------*/ PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); #if defined(FDCAN1) /* Get the FDCAN clock source -----------------------------------------------*/ PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); #endif /* FDCAN1 */ #if defined(USB) /* Get the USB clock source ------------------------------------------------*/ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); #endif /* USB */ /* Get the RNG clock source ------------------------------------------------*/ PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); /* Get the ADC12 clock source -----------------------------------------------*/ PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE(); #if defined(ADC345_COMMON) /* Get the ADC345 clock source ----------------------------------------------*/ PeriphClkInit->Adc345ClockSelection = __HAL_RCC_GET_ADC345_SOURCE(); #endif /* ADC345_COMMON */ #if defined(QUADSPI) /* Get the QuadSPIclock source --------------------------------------------*/ PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); #endif /* QUADSPI */ /* Get the RTC clock source ------------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); } /** * @brief Return the peripheral clock frequency for peripherals with clock source from PLL * @note Return 0 if peripheral clock identifier not managed by this API * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock * @arg @ref RCC_PERIPHCLK_I2S SPI peripheral clock * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (only for devices with FDCAN) * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) * @arg @ref RCC_PERIPHCLK_ADC12 ADC1 and ADC2 peripheral clock * @arg @ref RCC_PERIPHCLK_ADC345 ADC3, ADC4 and ADC5 peripheral clock (only for devices with ADC3, ADC4, ADC5) * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock (only for devices with QSPI) * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { uint32_t frequency = 0U; uint32_t srcclk; uint32_t pllvco, plln, pllp; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); if(PeriphClk == RCC_PERIPHCLK_RTC) { /* Get the current RTC source */ srcclk = __HAL_RCC_GET_RTC_SOURCE(); /* Check if LSE is ready and if RTC clock selection is LSE */ if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Check if LSI is ready and if RTC clock selection is LSI */ else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) { frequency = LSI_VALUE; } /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) { frequency = HSE_VALUE / 32U; } /* Clock not enabled for RTC*/ else { /* nothing to do: frequency already initialized to 0 */ } } else { /* Other external peripheral clock source than RTC */ /* Compute PLL clock input */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { pllvco = HSI_VALUE; } else { pllvco = 0U; } } else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ { if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) { pllvco = HSE_VALUE; } else { pllvco = 0U; } } else /* No source */ { pllvco = 0U; } /* f(PLL Source) / PLLM */ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); switch(PeriphClk) { case RCC_PERIPHCLK_USART1: /* Get the current USART1 source */ srcclk = __HAL_RCC_GET_USART1_SOURCE(); if(srcclk == RCC_USART1CLKSOURCE_PCLK2) { frequency = HAL_RCC_GetPCLK2Freq(); } else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI) ) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for USART1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_USART2: /* Get the current USART2 source */ srcclk = __HAL_RCC_GET_USART2_SOURCE(); if(srcclk == RCC_USART2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for USART2 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_USART3: /* Get the current USART3 source */ srcclk = __HAL_RCC_GET_USART3_SOURCE(); if(srcclk == RCC_USART3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for USART3 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(UART4) case RCC_PERIPHCLK_UART4: /* Get the current UART4 source */ srcclk = __HAL_RCC_GET_UART4_SOURCE(); if(srcclk == RCC_UART4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for UART4 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* UART4 */ #if defined(UART5) case RCC_PERIPHCLK_UART5: /* Get the current UART5 source */ srcclk = __HAL_RCC_GET_UART5_SOURCE(); if(srcclk == RCC_UART5CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for UART5 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* UART5 */ case RCC_PERIPHCLK_LPUART1: /* Get the current LPUART1 source */ srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for LPUART1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2C1: /* Get the current I2C1 source */ srcclk = __HAL_RCC_GET_I2C1_SOURCE(); if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2C2: /* Get the current I2C2 source */ srcclk = __HAL_RCC_GET_I2C2_SOURCE(); if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C2 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2C3: /* Get the current I2C3 source */ srcclk = __HAL_RCC_GET_I2C3_SOURCE(); if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C3CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C3 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(I2C4) case RCC_PERIPHCLK_I2C4: /* Get the current I2C4 source */ srcclk = __HAL_RCC_GET_I2C4_SOURCE(); if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2C4 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* I2C4 */ case RCC_PERIPHCLK_LPTIM1: /* Get the current LPTIM1 source */ srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) { frequency = LSI_VALUE; } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) { frequency = LSE_VALUE; } /* Clock not enabled for LPTIM1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_SAI1: /* Get the current SAI1 source */ srcclk = __HAL_RCC_GET_SAI1_SOURCE(); if(srcclk == RCC_SAI1CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if(srcclk == RCC_SAI1CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } } else if(srcclk == RCC_SAI1CLKSOURCE_EXT) { /* External clock used.*/ frequency = EXTERNAL_CLOCK_VALUE; } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_SAI1CLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for SAI1 */ else { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_I2S: /* Get the current I2Sx source */ srcclk = __HAL_RCC_GET_I2S_SOURCE(); if(srcclk == RCC_I2SCLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else if(srcclk == RCC_I2SCLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } } else if(srcclk == RCC_I2SCLKSOURCE_EXT) { /* External clock used.*/ frequency = EXTERNAL_CLOCK_VALUE; } else if((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2SCLKSOURCE_HSI)) { frequency = HSI_VALUE; } /* Clock not enabled for I2S */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(FDCAN1) case RCC_PERIPHCLK_FDCAN: /* Get the current FDCANx source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); if(srcclk == RCC_FDCANCLKSOURCE_PCLK1) { frequency = HAL_RCC_GetPCLK1Freq(); } else if(srcclk == RCC_FDCANCLKSOURCE_HSE) { frequency = HSE_VALUE; } else if(srcclk == RCC_FDCANCLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_48M1CLK) != 0U) { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } } /* Clock not enabled for FDCAN */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* FDCAN1 */ #if defined(USB) case RCC_PERIPHCLK_USB: /* Get the current USB source */ srcclk = __HAL_RCC_GET_USB_SOURCE(); if(srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */ { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else if((HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) /* HSI48 ? */ { frequency = HSI48_VALUE; } else /* No clock source */ { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* USB */ case RCC_PERIPHCLK_RNG: /* Get the current RNG source */ srcclk = __HAL_RCC_GET_RNG_SOURCE(); if(srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */ { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else if( (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) /* HSI48 ? */ { frequency = HSI48_VALUE; } else /* No clock source */ { /* nothing to do: frequency already initialized to 0 */ } break; case RCC_PERIPHCLK_ADC12: /* Get the current ADC12 source */ srcclk = __HAL_RCC_GET_ADC12_SOURCE(); if(srcclk == RCC_ADC12CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) { /* f(PLLP) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) { pllp = 17U; } else { pllp = 7U; } } frequency = (pllvco * plln) / pllp; } } else if(srcclk == RCC_ADC12CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Clock not enabled for ADC12 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #if defined(ADC345_COMMON) case RCC_PERIPHCLK_ADC345: /* Get the current ADC345 source */ srcclk = __HAL_RCC_GET_ADC345_SOURCE(); if(srcclk == RCC_ADC345CLKSOURCE_PLL) { if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_ADCCLK) != 0U) { /* f(PLLP) = f(VCO input) * PLLN / PLLP */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; if(pllp == 0U) { if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != 0U) { pllp = 17U; } else { pllp = 7U; } } frequency = (pllvco * plln) / pllp; } } else if(srcclk == RCC_ADC345CLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } /* Clock not enabled for ADC345 */ else { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* ADC345_COMMON */ #if defined(QUADSPI) case RCC_PERIPHCLK_QSPI: /* Get the current QSPI source */ srcclk = __HAL_RCC_GET_QSPI_SOURCE(); if(srcclk == RCC_QSPICLKSOURCE_PLL) /* PLL ? */ { /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); } else if(srcclk == RCC_QSPICLKSOURCE_HSI) { frequency = HSI_VALUE; } else if(srcclk == RCC_QSPICLKSOURCE_SYSCLK) { frequency = HAL_RCC_GetSysClockFreq(); } else /* No clock source */ { /* nothing to do: frequency already initialized to 0 */ } break; #endif /* QUADSPI */ default: break; } } return(frequency); } /** * @} */ /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions * @brief Extended Clock management functions * @verbatim =============================================================================== ##### Extended clock management functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the activation or deactivation of LSE CSS, Low speed clock output and clock after wake-up from STOP mode. @endverbatim * @{ */ /** * @brief Enable the LSE Clock Security System. * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC * clock with HAL_RCCEx_PeriphCLKConfig(). * @retval None */ void HAL_RCCEx_EnableLSECSS(void) { SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; } /** * @brief Disable the LSE Clock Security System. * @note LSE Clock Security System can only be disabled after a LSE failure detection. * @retval None */ void HAL_RCCEx_DisableLSECSS(void) { CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; /* Disable LSE CSS IT if any */ __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); } /** * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19 * @retval None */ void HAL_RCCEx_EnableLSECSS_IT(void) { /* Enable LSE CSS */ SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; /* Enable LSE CSS IT */ __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); /* Enable IT on EXTI Line 19 */ __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); } /** * @brief Handle the RCC LSE Clock Security System interrupt request. * @retval None */ void HAL_RCCEx_LSECSS_IRQHandler(void) { /* Check RCC LSE CSSF flag */ if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) { /* RCC LSE Clock Security System interrupt user callback */ HAL_RCCEx_LSECSS_Callback(); /* Clear RCC LSE CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); } } /** * @brief RCCEx LSE Clock Security System interrupt callback. * @retval none */ __weak void HAL_RCCEx_LSECSS_Callback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file */ } /** * @brief Select the Low Speed clock source to output on LSCO pin (PA2). * @param LSCOSource specifies the Low Speed clock source to output. * This parameter can be one of the following values: * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source * @retval None */ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) { GPIO_InitTypeDef GPIO_InitStruct; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; /* Check the parameters */ assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); /* LSCO Pin Clock Enable */ __LSCO_CLK_ENABLE(); /* Configure the LSCO pin in analog mode */ GPIO_InitStruct.Pin = LSCO_PIN; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); /* Update LSCOSEL clock source in Backup Domain control register */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); if(backupchanged == SET) { HAL_PWR_DisableBkUpAccess(); } if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /** * @brief Disable the Low Speed clock output. * @retval None */ void HAL_RCCEx_DisableLSCO(void) { FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; /* Update LSCOEN bit in Backup Domain control register */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable access to the backup domain */ HAL_PWR_EnableBkUpAccess(); backupchanged = SET; } CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); /* Restore previous configuration */ if(backupchanged == SET) { /* Disable access to the backup domain */ HAL_PWR_DisableBkUpAccess(); } if(pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } } /** * @} */ #if defined(CRS) /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions * @verbatim =============================================================================== ##### Extended Clock Recovery System Control functions ##### =============================================================================== [..] For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: (#) In System clock config, HSI48 needs to be enabled (#) Enable CRS clock in IP MSP init which will use CRS functions (#) Call CRS functions as follows: (##) Prepare synchronization configuration necessary for HSI48 calibration (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate directly reload value with target and sychronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. (+++) Configures CRS registers with synchronization configuration (+++) Enables automatic calibration and frequency error counter feature Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. (##) A polling function is provided to wait for complete synchronization (+++) Call function HAL_RCCEx_CRSWaitSynchronization() (+++) According to CRS status, user can decide to adjust again the calibration or continue application if synchronization is OK (#) User can retrieve information related to synchronization in calling function HAL_RCCEx_CRSGetSynchronizationInfo() (#) Regarding synchronization status and synchronization information, user can try a new calibration in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), it means that the actual frequency is lower than the target (and so, that the TRIM value should be incremented), while when it is detected during the upcounting phase it means that the actual frequency is higher (and that the TRIM value should be decremented). (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go through CRS Handler (CRS_IRQn/CRS_IRQHandler) (++) Call function HAL_RCCEx_CRSConfig() (++) Enable CRS_IRQn (thanks to NVIC functions) (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) (++) Implement CRS status management in the following user callbacks called from HAL_RCCEx_CRS_IRQHandler(): (+++) HAL_RCCEx_CRS_SyncOkCallback() (+++) HAL_RCCEx_CRS_SyncWarnCallback() (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() (+++) HAL_RCCEx_CRS_ErrorCallback() (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) @endverbatim * @{ */ /** * @brief Start automatic synchronization for polling mode * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) { uint32_t value; /* Check the parameters */ assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); /* CONFIGURATION */ /* Before configuration, reset CRS registers to their default values*/ __HAL_RCC_CRS_FORCE_RESET(); __HAL_RCC_CRS_RELEASE_RESET(); /* Set the SYNCDIV[2:0] bits according to Prescaler value */ /* Set the SYNCSRC[1:0] bits according to Source value */ /* Set the SYNCSPOL bit according to Polarity value */ value = (pInit->Prescaler | pInit->Source | pInit->Polarity); /* Set the RELOAD[15:0] bits according to ReloadValue value */ value |= pInit->ReloadValue; /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); WRITE_REG(CRS->CFGR, value); /* Adjust HSI48 oscillator smooth trimming */ /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); /* START AUTOMATIC SYNCHRONIZATION*/ /* Enable Automatic trimming & Frequency error counter */ SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); } /** * @brief Generate the software synchronization event * @retval None */ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) { SET_BIT(CRS->CR, CRS_CR_SWSYNC); } /** * @brief Return synchronization info * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure * @retval None */ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) { /* Check the parameter */ assert_param(pSynchroInfo != (void *)NULL); /* Get the reload value */ pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); /* Get HSI48 oscillator smooth trimming */ pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); /* Get Frequency error capture */ pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); /* Get Frequency error direction */ pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); } /** * @brief Wait for CRS Synchronization status. * @param Timeout Duration of the timeout * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization * frequency. * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. * @retval Combination of Synchronization status * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_TIMEOUT * @arg @ref RCC_CRS_SYNCOK * @arg @ref RCC_CRS_SYNCWARN * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS * @arg @ref RCC_CRS_TRIMOVF */ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; uint32_t tickstart; /* Get timeout */ tickstart = HAL_GetTick(); /* Wait for CRS flag or timeout detection */ do { if(Timeout != HAL_MAX_DELAY) { if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { crsstatus = RCC_CRS_TIMEOUT; } } /* Check CRS SYNCOK flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) { /* CRS SYNC event OK */ crsstatus |= RCC_CRS_SYNCOK; /* Clear CRS SYNC event OK bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); } /* Check CRS SYNCWARN flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ crsstatus |= RCC_CRS_SYNCWARN; /* Clear CRS SYNCWARN bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); } /* Check CRS TRIM overflow flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_TRIMOVF; /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); } /* Check CRS Error flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_SYNCERR; /* Clear CRS Error bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); } /* Check CRS SYNC Missed flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) { /* CRS SYNC Missed */ crsstatus |= RCC_CRS_SYNCMISS; /* Clear CRS SYNC Missed bit */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); } /* Check CRS Expected SYNC flag */ if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) { /* frequency error counter reached a zero value */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); } } while(RCC_CRS_NONE == crsstatus); return crsstatus; } /** * @brief Handle the Clock Recovery System interrupt request. * @retval None */ void HAL_RCCEx_CRS_IRQHandler(void) { uint32_t crserror = RCC_CRS_NONE; /* Get current IT flags and IT sources values */ uint32_t itflags = READ_REG(CRS->ISR); uint32_t itsources = READ_REG(CRS->CR); /* Check CRS SYNCOK flag */ if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) { /* Clear CRS SYNC event OK flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); /* user callback */ HAL_RCCEx_CRS_SyncOkCallback(); } /* Check CRS SYNCWARN flag */ else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) { /* Clear CRS SYNCWARN flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); /* user callback */ HAL_RCCEx_CRS_SyncWarnCallback(); } /* Check CRS Expected SYNC flag */ else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) { /* frequency error counter reached a zero value */ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); /* user callback */ HAL_RCCEx_CRS_ExpectedSyncCallback(); } /* Check CRS Error flags */ else { if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) { if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) { crserror |= RCC_CRS_SYNCERR; } if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) { crserror |= RCC_CRS_SYNCMISS; } if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) { crserror |= RCC_CRS_TRIMOVF; } /* Clear CRS Error flags */ WRITE_REG(CRS->ICR, CRS_ICR_ERRC); /* user error callback */ HAL_RCCEx_CRS_ErrorCallback(crserror); } } } /** * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. * @retval none */ __weak void HAL_RCCEx_CRS_SyncOkCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file */ } /** * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. * @retval none */ __weak void HAL_RCCEx_CRS_SyncWarnCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file */ } /** * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. * @retval none */ __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) { /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file */ } /** * @brief RCCEx Clock Recovery System Error interrupt callback. * @param Error Combination of Error status. * This parameter can be a combination of the following values: * @arg @ref RCC_CRS_SYNCERR * @arg @ref RCC_CRS_SYNCMISS * @arg @ref RCC_CRS_TRIMOVF * @retval none */ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) { /* Prevent unused argument(s) compilation warning */ UNUSED(Error); /* NOTE : This function should not be modified, when the callback is needed, the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file */ } /** * @} */ #endif /* CRS */ /** * @} */ /** @addtogroup RCCEx_Private_Functions * @{ */ /** * @} */ /** * @} */ #endif /* HAL_RCC_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: * + TIM Time Base Initialization * + TIM Time Base Start * + TIM Time Base Start Interruption * + TIM Time Base Start DMA * + TIM Output Compare/PWM Initialization * + TIM Output Compare/PWM Channel Configuration * + TIM Output Compare/PWM Start * + TIM Output Compare/PWM Start Interruption * + TIM Output Compare/PWM Start DMA * + TIM Input Capture Initialization * + TIM Input Capture Channel Configuration * + TIM Input Capture Start * + TIM Input Capture Start Interruption * + TIM Input Capture Start DMA * + TIM One Pulse Initialization * + TIM One Pulse Channel Configuration * + TIM One Pulse Start * + TIM Encoder Interface Initialization * + TIM Encoder Interface Start * + TIM Encoder Interface Start Interruption * + TIM Encoder Interface Start DMA * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### TIMER Generic features ##### ============================================================================== [..] The Timer features include: (#) 16-bit up, down, up/down auto-reload counter. (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock frequency either by any factor between 1 and 65536. (#) Up to 4 independent channels for: (++) Input Capture (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Supports incremental encoder for positioning purposes ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Time Base : HAL_TIM_Base_MspInit() (++) Input Capture : HAL_TIM_IC_MspInit() (++) Output Compare : HAL_TIM_OC_MspInit() (++) PWM generation : HAL_TIM_PWM_MspInit() (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() (++) Encoder mode output : HAL_TIM_Encoder_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the Initialization function of this driver: (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare: to use the Timer to generate an Output Compare signal. (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a PWM signal. (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an external signal. (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode. (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. (#) Activate the TIM peripheral using one of the start functions depending from the feature used: (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). (#) The DMA Burst is managed with the two following functions: HAL_TIM_DMABurst_WriteStart() HAL_TIM_DMABurst_ReadStart() *** Callback registration *** ============================================= [..] The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] Use Function HAL_TIM_RegisterCallback() to register a callback. HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: (+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. (+) IC_MspInitCallback : TIM IC Msp Init Callback. (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. (+) OC_MspInitCallback : TIM OC Msp Init Callback. (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. (+) PeriodElapsedCallback : TIM Period Elapsed Callback. (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. (+) TriggerCallback : TIM Trigger Callback. (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. (+) IC_CaptureCallback : TIM Input Capture Callback. (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. (+) ErrorCallback : TIM Error Callback. (+) CommutationCallback : TIM Commutation Callback. (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. (+) BreakCallback : TIM Break Callback. (+) Break2Callback : TIM Break2 Callback. (+) EncoderIndexCallback : TIM Encoder Index Callback. (+) DirectionChangeCallback : TIM Direction Change Callback (+) IndexErrorCallback : TIM Index Error Callback. (+) TransitionErrorCallback : TIM Transition Error Callback [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init / DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered beforehand) [..] Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Exception done MspInit / MspDeInit that can be registered / unregistered in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks using HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup TIM TIM * @brief TIM HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup TIM_Private_Constants * @{ */ #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions * @{ */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ /* Exported functions --------------------------------------------------------*/ /** @defgroup TIM_Exported_Functions TIM Exported Functions * @{ */ /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions * @brief Time Base functions * @verbatim ============================================================================== ##### Time Base functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM base. (+) De-initialize the TIM base. (+) Start the Time Base. (+) Stop the Time Base. (+) Start the Time Base and enable interrupt. (+) Stop the Time Base and disable interrupt. (+) Start the Time Base and enable DMA transfer. (+) Stop the Time Base and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Base_MspInitCallback == NULL) { htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Base peripheral * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Base_MspDeInitCallback == NULL) { htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; } /* DeInit the low level hardware */ htim->Base_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) { return HAL_ERROR; } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Base generation in DMA mode. * @param htim TIM Base handle * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } } else { return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Update DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Base generation in DMA mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions * @brief TIM Output Compare functions * @verbatim ============================================================================== ##### TIM Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Output Compare. (+) De-initialize the TIM Output Compare. (+) Start the TIM Output Compare. (+) Stop the TIM Output Compare. (+) Start the TIM Output Compare and enable interrupt. (+) Stop the TIM Output Compare and disable interrupt. (+) Start the TIM Output Compare and enable DMA transfer. (+) Stop the TIM Output Compare and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OC_MspInitCallback == NULL) { htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Output Compare handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OC_MspDeInitCallback == NULL) { htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; } /* DeInit the low level hardware */ htim->OC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Output Compare MSP. * @param htim TIM Output Compare handle * @retval None */ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions * @brief TIM PWM functions * @verbatim ============================================================================== ##### TIM PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM PWM. (+) De-initialize the TIM PWM. (+) Start the TIM PWM. (+) Stop the TIM PWM. (+) Start the TIM PWM and enable interrupt. (+) Stop the TIM PWM and disable interrupt. (+) Start the TIM PWM and enable DMA transfer. (+) Stop the TIM PWM and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->PWM_MspInitCallback == NULL) { htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->PWM_MspDeInitCallback == NULL) { htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; } /* DeInit the low level hardware */ htim->PWM_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspDeInit could be implemented in the user file */ } /** * @brief Starts the PWM signal generation. * @param htim TIM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the PWM signal generation in interrupt mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Set the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM PWM signal generation in DMA mode. * @param htim TIM PWM handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions * @brief TIM Input Capture functions * @verbatim ============================================================================== ##### TIM Input Capture functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Input Capture. (+) De-initialize the TIM Input Capture. (+) Start the TIM Input Capture. (+) Stop the TIM Input Capture. (+) Start the TIM Input Capture and enable interrupt. (+) Stop the TIM Input Capture and disable interrupt. (+) Start the TIM Input Capture and enable DMA transfer. (+) Stop the TIM Input Capture and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->IC_MspInitCallback == NULL) { htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM peripheral * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->IC_MspDeInitCallback == NULL) { htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; } /* DeInit the low level hardware */ htim->IC_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Input Capture MSP. * @param htim TIM handle * @retval None */ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Input Capture measurement. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Input Capture measurement in interrupt mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return status; } /** * @brief Stops the TIM Input Capture measurement in DMA mode. * @param htim TIM Input Capture handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions * @brief TIM One Pulse functions * @verbatim ============================================================================== ##### TIM One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM One Pulse. (+) De-initialize the TIM One Pulse. (+) Start the TIM One Pulse. (+) Stop the TIM One Pulse. (+) Start the TIM One Pulse and enable interrupt. (+) Stop the TIM One Pulse and disable interrupt. (+) Start the TIM One Pulse and enable DMA transfer. (+) Stop the TIM One Pulse and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and initializes the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() * @note When the timer instance is initialized in One Pulse mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) { /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->OnePulse_MspInitCallback == NULL) { htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->OnePulse_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the One Pulse Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Reset the OPM Bit */ htim->Instance->CR1 &= ~TIM_CR1_OPM; /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM One Pulse * @param htim TIM One Pulse handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->OnePulse_MspDeInitCallback == NULL) { htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; } /* DeInit the low level hardware */ htim->OnePulse_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM One Pulse MSP. * @param htim TIM One Pulse handle * @retval None */ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. * @note The pulse output channel is determined when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions * @brief TIM Encoder functions * @verbatim ============================================================================== ##### TIM Encoder functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the TIM Encoder. (+) De-initialize the TIM Encoder. (+) Start the TIM Encoder. (+) Stop the TIM Encoder. (+) Start the TIM Encoder and enable interrupt. (+) Stop the TIM Encoder and disable interrupt. (+) Start the TIM Encoder and enable DMA transfer. (+) Stop the TIM Encoder and disable DMA transfer. @endverbatim * @{ */ /** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa * @note When the timer instance is initialized in Encoder mode, timer * channels 1 and channel 2 are reserved and cannot be used for other * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy weak callbacks */ TIM_ResetCallback(htim); if (htim->Encoder_MspInitCallback == NULL) { htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Encoder interface * @param htim TIM Encoder Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->Encoder_MspDeInitCallback == NULL) { htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; } /* DeInit the low level hardware */ htim->Encoder_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Encoder Interface MSP. * @param htim TIM Encoder Interface handle * @retval None */ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Encoder_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); break; } } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in interrupt mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 and 2 */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @param pData1 The destination Buffer address for IC1. * @param pData2 The destination Buffer address for IC2. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData1 == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData2 == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); break; } case TIM_CHANNEL_2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); break; } default: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); break; } } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Encoder Interface in DMA mode. * @param htim TIM Encoder Interface handle * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ if (Channel == TIM_CHANNEL_1) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); } else if (Channel == TIM_CHANNEL_2) { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } else { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); /* Disable the capture compare DMA Request 1 and 2 */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel(s) state */ if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) { TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management * @brief TIM IRQ handler management * @verbatim ============================================================================== ##### IRQ handler management ##### ============================================================================== [..] This section provides Timer IRQ handler function. @endverbatim * @{ */ /** * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Output compare event */ else { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Encoder index event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else HAL_TIMEx_EncoderIndexCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Direction change event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else HAL_TIMEx_DirectionChangeCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Index error event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else HAL_TIMEx_IndexErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Transition error event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET) { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET) { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else HAL_TIMEx_TransitionErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } /** * @} */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions * @brief TIM Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. (+) Configure External Clock source. (+) Configure Complementary channels, break features and dead time. (+) Configure Master and the Slave synchronization. (+) Configure the DMA Burst Mode. @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM Output Compare handle * @param sConfig TIM Output Compare configuration structure * @param Channel TIM Channels to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the TIM Channel 1 in Output Compare */ TIM_OC1_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the TIM Channel 2 in Output Compare */ TIM_OC2_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the TIM Channel 3 in Output Compare */ TIM_OC3_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the TIM Channel 4 in Output Compare */ TIM_OC4_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the TIM Channel 5 in Output Compare */ TIM_OC5_SetConfig(htim->Instance, sConfig); break; } case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the TIM Channel 6 in Output Compare */ TIM_OC6_SetConfig(htim->Instance, sConfig); break; } default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. * @param htim TIM IC handle * @param sConfig TIM Input Capture configuration structure * @param Channel TIM Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; } else if (Channel == TIM_CHANNEL_2) { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } else if (Channel == TIM_CHANNEL_4) { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } else { status = HAL_ERROR; } __HAL_UNLOCK(htim); return status; } /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. * @param htim TIM PWM handle * @param sConfig TIM PWM configuration structure * @param Channel TIM Channels to be configured * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; htim->Instance->CCMR2 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; break; } case TIM_CHANNEL_5: { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; htim->Instance->CCMR3 |= sConfig->OCFastMode; break; } case TIM_CHANNEL_6: { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; break; } default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. * @param htim TIM One Pulse handle * @param sConfig TIM One Pulse configuration structure * @param OutputChannel TIM output channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @param InputChannel TIM input Channel to configure * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @note To output a waveform with a minimum delay user can enable the fast * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx * output is forced in response to the edge detection on TIx input, * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { HAL_StatusTypeDef status = HAL_OK; TIM_OC_InitTypeDef temp1; /* Check the parameters */ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); if (OutputChannel != InputChannel) { /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Extract the Output compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; temp1.OCPolarity = sConfig->OCPolarity; temp1.OCNPolarity = sConfig->OCNPolarity; temp1.OCIdleState = sConfig->OCIdleState; temp1.OCNIdleState = sConfig->OCNIdleState; switch (OutputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_OC1_SetConfig(htim->Instance, &temp1); break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_OC2_SetConfig(htim->Instance, &temp1); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { switch (InputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1FP1; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI2FP2; /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; break; } default: status = HAL_ERROR; break; } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return status; } else { return HAL_ERROR; } } /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status; status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); return status; } /** * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ return status; } /** * @brief Stops the TIM DMA Burst mode * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; } /* Return function status */ return status; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status; status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U); return status; } /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory * @param htim TIM handle * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read * This parameter can be one of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 * @arg TIM_DMABASE_SMCR * @arg TIM_DMABASE_DIER * @arg TIM_DMABASE_SR * @arg TIM_DMABASE_EGR * @arg TIM_DMABASE_CCMR1 * @arg TIM_DMABASE_CCMR2 * @arg TIM_DMABASE_CCER * @arg TIM_DMABASE_CNT * @arg TIM_DMABASE_PSC * @arg TIM_DMABASE_ARR * @arg TIM_DMABASE_RCR * @arg TIM_DMABASE_CCR1 * @arg TIM_DMABASE_CCR2 * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_CCMR3 * @arg TIM_DMABASE_CCR5 * @arg TIM_DMABASE_CCR6 * @arg TIM_DMABASE_DTR2 * @arg TIM_DMABASE_ECR * @arg TIM_DMABASE_TISEL * @arg TIM_DMABASE_AF1 * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_OR * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer The Buffer address. * @param BurstLength DMA Burst length. This parameter can be one value * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. * @param DataLength Data length. This parameter can be one value * between 1 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { return HAL_ERROR; } else { htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else { /* nothing to do */ } switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { /* Set the DMA Period elapsed callbacks */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC1: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC3: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC4: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_COM: { /* Set the DMA commutation callbacks */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_TRIGGER: { /* Set the DMA trigger callbacks */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; } break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); } /* Return function status */ return status; } /** * @brief Stop the DMA burst reading * @param htim TIM handle * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); /* Abort the DMA transfer (at least disable the DMA channel) */ switch (BurstRequestSrc) { case TIM_DMA_UPDATE: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; } /* Return function status */ return status; } /** * @brief Generate a software event * @param htim TIM handle * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source * @arg TIM_EVENTSOURCE_COM: Timer COM event source * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source * @note Basic timers can only generate an update event. * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant * only for timer instances supporting break input(s). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_EVENT_SOURCE(EventSource)); /* Process Locked */ __HAL_LOCK(htim); /* Change the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the event sources */ htim->Instance->EGR = EventSource; /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); /* Return function status */ return HAL_OK; } /** * @brief Configures the OCRef clear feature * @param htim TIM handle * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; switch (sClearInputConfig->ClearInputSource) { case TIM_CLEARINPUTSOURCE_NONE: { /* Clear the OCREF clear selection bit and the the ETR Bits */ if (IS_TIM_OCCS_INSTANCE(htim->Instance)) { CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); /* Clear TIMx_AF2_OCRSEL (reset value) */ CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); } else { CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); } break; } case TIM_CLEARINPUTSOURCE_COMP1: case TIM_CLEARINPUTSOURCE_COMP2: case TIM_CLEARINPUTSOURCE_COMP3: case TIM_CLEARINPUTSOURCE_COMP4: #if defined (COMP5) case TIM_CLEARINPUTSOURCE_COMP5: #endif /* COMP5 */ #if defined (COMP6) case TIM_CLEARINPUTSOURCE_COMP6: #endif /* COMP6 */ #if defined (COMP7) case TIM_CLEARINPUTSOURCE_COMP7: #endif /* COMP7 */ { if (IS_TIM_OCCS_INSTANCE(htim->Instance)) { /* Clear the OCREF clear selection bit */ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); /* Clear TIM1_AF2_OCRSEL (reset value) */ MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); } break; } case TIM_CLEARINPUTSOURCE_ETR: { /* Check the parameters */ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); if (IS_TIM_OCCS_INSTANCE(htim->Instance)) { /* Set the OCREF clear selection bit */ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); /* Clear TIMx_AF2_OCRSEL (reset value) */ CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); } break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { switch (Channel) { case TIM_CHANNEL_1: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 1 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } else { /* Disable the OCREF clear feature for Channel 1 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); } break; } case TIM_CHANNEL_2: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 2 */ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } else { /* Disable the OCREF clear feature for Channel 2 */ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); } break; } case TIM_CHANNEL_3: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 3 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } else { /* Disable the OCREF clear feature for Channel 3 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); } break; } case TIM_CHANNEL_4: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 4 */ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } else { /* Disable the OCREF clear feature for Channel 4 */ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); } break; } case TIM_CHANNEL_5: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 5 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } else { /* Disable the OCREF clear feature for Channel 5 */ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); } break; } case TIM_CHANNEL_6: { if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) { /* Enable the OCREF clear feature for Channel 6 */ SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } else { /* Disable the OCREF clear feature for Channel 6 */ CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); } break; } default: break; } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return status; } /** * @brief Configures the clock source to be used * @param htim TIM handle * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); htim->Instance->SMCR = tmpsmcr; switch (sClockSourceConfig->ClockSource) { case TIM_CLOCKSOURCE_INTERNAL: { assert_param(IS_TIM_INSTANCE(htim->Instance)); break; } case TIM_CLOCKSOURCE_ETRMODE1: { /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; break; } case TIM_CLOCKSOURCE_ETRMODE2: { /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); /* Check ETR input conditioning related parameters */ assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, sClockSourceConfig->ClockPrescaler, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; break; } case TIM_CLOCKSOURCE_TI1: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); break; } case TIM_CLOCKSOURCE_TI2: { /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); break; } case TIM_CLOCKSOURCE_TI1ED: { /* Check whether or not the timer instance supports external clock mode 1 */ assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, sClockSourceConfig->ClockPolarity, sClockSourceConfig->ClockFilter); TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); break; } case TIM_CLOCKSOURCE_ITR0: case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: #if defined (TIM5) case TIM_CLOCKSOURCE_ITR4: #endif /* TIM5 */ case TIM_CLOCKSOURCE_ITR5: case TIM_CLOCKSOURCE_ITR6: case TIM_CLOCKSOURCE_ITR7: case TIM_CLOCKSOURCE_ITR8: #if defined (TIM20) case TIM_CLOCKSOURCE_ITR9: #endif /* TIM20 */ #if defined (HRTIM1) case TIM_CLOCKSOURCE_ITR10: #endif /* HRTIM1 */ case TIM_CLOCKSOURCE_ITR11: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); break; } default: status = HAL_ERROR; break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return status; } /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input * @param htim TIM handle. * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 * pins are connected to the TI1 input (XOR combination) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { uint32_t tmpcr2; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Reset the TI1 selection */ tmpcr2 &= ~TIM_CR2_TI1S; /* Set the TI1 selection */ tmpcr2 |= TI1_Selection; /* Write to TIMxCR2 */ htim->Instance->CR2 = tmpcr2; return HAL_OK; } /** * @brief Configures the TIM in Slave mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Disable Trigger Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in Slave mode in interrupt mode * @param htim TIM handle. * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the Slave mode * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } /* Enable Trigger Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); /* Disable Trigger DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Read the captured value from Capture Compare unit * @param htim TIM handle. * @param Channel TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; switch (Channel) { case TIM_CHANNEL_1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; break; } case TIM_CHANNEL_2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; break; } case TIM_CHANNEL_3: { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; break; } case TIM_CHANNEL_4: { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; break; } default: break; } return tmpreg; } /** * @} */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions * @brief TIM Callbacks functions * @verbatim ============================================================================== ##### TIM Callbacks functions ##### ============================================================================== [..] This section provides TIM callback functions: (+) TIM Period elapsed callback (+) TIM Output Compare callback (+) TIM Input capture callback (+) TIM Trigger callback (+) TIM Error callback (+) TIM Index callback (+) TIM Direction change callback (+) TIM Index error callback (+) TIM Transition error callback @endverbatim * @{ */ /** * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } /** * @brief Period elapsed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file */ } /** * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } /** * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } /** * @brief Input Capture half complete callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } /** * @brief PWM Pulse finished half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } /** * @brief Hall Trigger detection half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file */ } /** * @brief Timer error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_ErrorCallback could be implemented in the user file */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Register a User TIM callback to be used instead of the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID * @param pCallback pointer to the callback function * @retval status */ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : htim->PeriodElapsedCallback = pCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : htim->PeriodElapsedHalfCpltCallback = pCallback; break; case HAL_TIM_TRIGGER_CB_ID : htim->TriggerCallback = pCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : htim->TriggerHalfCpltCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : htim->IC_CaptureCallback = pCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : htim->IC_CaptureHalfCpltCallback = pCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : htim->OC_DelayElapsedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : htim->PWM_PulseFinishedCallback = pCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : htim->PWM_PulseFinishedHalfCpltCallback = pCallback; break; case HAL_TIM_ERROR_CB_ID : htim->ErrorCallback = pCallback; break; case HAL_TIM_COMMUTATION_CB_ID : htim->CommutationCallback = pCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : htim->CommutationHalfCpltCallback = pCallback; break; case HAL_TIM_BREAK_CB_ID : htim->BreakCallback = pCallback; break; case HAL_TIM_BREAK2_CB_ID : htim->Break2Callback = pCallback; break; case HAL_TIM_ENCODER_INDEX_CB_ID : htim->EncoderIndexCallback = pCallback; break; case HAL_TIM_DIRECTION_CHANGE_CB_ID : htim->DirectionChangeCallback = pCallback; break; case HAL_TIM_INDEX_ERROR_CB_ID : htim->IndexErrorCallback = pCallback; break; case HAL_TIM_TRANSITION_ERROR_CB_ID : htim->TransitionErrorCallback = pCallback; break; default : /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : htim->Base_MspInitCallback = pCallback; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : htim->Base_MspDeInitCallback = pCallback; break; case HAL_TIM_IC_MSPINIT_CB_ID : htim->IC_MspInitCallback = pCallback; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : htim->IC_MspDeInitCallback = pCallback; break; case HAL_TIM_OC_MSPINIT_CB_ID : htim->OC_MspInitCallback = pCallback; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : htim->OC_MspDeInitCallback = pCallback; break; case HAL_TIM_PWM_MSPINIT_CB_ID : htim->PWM_MspInitCallback = pCallback; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : htim->PWM_MspDeInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : htim->OnePulse_MspInitCallback = pCallback; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : htim->OnePulse_MspDeInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : htim->Encoder_MspInitCallback = pCallback; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : htim->Encoder_MspDeInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : htim->HallSensor_MspInitCallback = pCallback; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : htim->HallSensor_MspDeInitCallback = pCallback; break; default : /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } /** * @brief Unregister a TIM callback * TIM callback is redirected to the weak predefined callback * @param htim tim handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : /* Legacy weak Base MspInit Callback */ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : /* Legacy weak Base Msp DeInit Callback */ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : /* Legacy weak IC Msp Init Callback */ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : /* Legacy weak IC Msp DeInit Callback */ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : /* Legacy weak OC Msp Init Callback */ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : /* Legacy weak OC Msp DeInit Callback */ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : /* Legacy weak PWM Msp Init Callback */ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : /* Legacy weak PWM Msp DeInit Callback */ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : /* Legacy weak One Pulse Msp Init Callback */ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : /* Legacy weak One Pulse Msp DeInit Callback */ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : /* Legacy weak Encoder Msp Init Callback */ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : /* Legacy weak Encoder Msp DeInit Callback */ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : /* Legacy weak Hall Sensor Msp Init Callback */ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : /* Legacy weak Hall Sensor Msp DeInit Callback */ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : /* Legacy weak Period Elapsed Callback */ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : /* Legacy weak Period Elapsed half complete Callback */ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : /* Legacy weak Trigger Callback */ htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : /* Legacy weak Trigger half complete Callback */ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : /* Legacy weak IC Capture Callback */ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : /* Legacy weak IC Capture half complete Callback */ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : /* Legacy weak OC Delay Elapsed Callback */ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : /* Legacy weak PWM Pulse Finished Callback */ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : /* Legacy weak PWM Pulse Finished half complete Callback */ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : /* Legacy weak Error Callback */ htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : /* Legacy weak Commutation Callback */ htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : /* Legacy weak Commutation half complete Callback */ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : /* Legacy weak Break Callback */ htim->BreakCallback = HAL_TIMEx_BreakCallback; break; case HAL_TIM_BREAK2_CB_ID : /* Legacy weak Break2 Callback */ htim->Break2Callback = HAL_TIMEx_Break2Callback; break; case HAL_TIM_ENCODER_INDEX_CB_ID : /* Legacy weak Encoder Index Callback */ htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; break; case HAL_TIM_DIRECTION_CHANGE_CB_ID : /* Legacy weak Direction Change Callback */ htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; break; case HAL_TIM_INDEX_ERROR_CB_ID : /* Legacy weak Index Error Callback */ htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; break; case HAL_TIM_TRANSITION_ERROR_CB_ID : /* Legacy weak Transition Error Callback */ htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; break; default : /* Return error status */ status = HAL_ERROR; break; } } else if (htim->State == HAL_TIM_STATE_RESET) { switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : /* Legacy weak Base MspInit Callback */ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : /* Legacy weak Base Msp DeInit Callback */ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : /* Legacy weak IC Msp Init Callback */ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : /* Legacy weak IC Msp DeInit Callback */ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : /* Legacy weak OC Msp Init Callback */ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : /* Legacy weak OC Msp DeInit Callback */ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : /* Legacy weak PWM Msp Init Callback */ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : /* Legacy weak PWM Msp DeInit Callback */ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : /* Legacy weak One Pulse Msp Init Callback */ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : /* Legacy weak One Pulse Msp DeInit Callback */ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : /* Legacy weak Encoder Msp Init Callback */ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : /* Legacy weak Encoder Msp DeInit Callback */ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : /* Legacy weak Hall Sensor Msp Init Callback */ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : /* Legacy weak Hall Sensor Msp DeInit Callback */ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : /* Return error status */ status = HAL_ERROR; break; } } else { /* Return error status */ status = HAL_ERROR; } /* Release Lock */ __HAL_UNLOCK(htim); return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions * @brief TIM Peripheral State functions * @verbatim ============================================================================== ##### Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Base handle state. * @param htim TIM Base handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM OC handle state. * @param htim TIM Output Compare handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM PWM handle state. * @param htim TIM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Input Capture handle state. * @param htim TIM IC handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM One Pulse Mode handle state. * @param htim TIM OPM handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM Encoder Interface handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return the TIM Encoder Mode handle state. * @param htim TIM handle * @retval Active channel */ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) { return htim->Channel; } /** * @brief Return actual state of the TIM channel. * @param htim TIM handle * @param Channel TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); return channel_state; } /** * @brief Return actual state of a DMA burst operation. * @param htim TIM handle * @retval DMA burst state */ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); return htim->DMABurstState; } /** * @} */ /** * @} */ /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ /** * @brief TIM DMA error callback * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } else { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Delay Pulse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedHalfCpltCallback(htim); #else HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureHalfCpltCallback(htim); #else HAL_TIM_IC_CaptureHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Period Elapse complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Period Elapse half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else HAL_TIM_PeriodElapsedHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) { htim->State = HAL_TIM_STATE_READY; } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Trigger half complete callback. * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else HAL_TIM_TriggerHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief Time Base configuration * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); tmpcr1 |= Structure->CounterMode; } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; tmpcr1 |= (uint32_t)Structure->ClockDivision; } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; } /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; tmpcr2 &= ~TIM_CR2_OIS2N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC4NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 12U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC4NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; /* Reset the Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4N; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 6U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); if (IS_TIM_BREAK_INSTANCE(TIMx)) { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Slave Timer configuration function * @param htim TIM handle * @param sSlaveConfig Slave timer configuration * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* Reset the Trigger Selection Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source */ tmpsmcr |= sSlaveConfig->InputTrigger; /* Reset the slave mode Bits */ tmpsmcr &= ~TIM_SMCR_SMS; /* Set the slave mode */ tmpsmcr |= sSlaveConfig->SlaveMode; /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; /* Configure the trigger prescaler, filter, and polarity */ switch (sSlaveConfig->InputTrigger) { case TIM_TS_ETRF: { /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure the ETR Trigger source */ TIM_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI1F_ED: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \ (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) { return HAL_ERROR; } /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = htim->Instance->CCER; htim->Instance->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = htim->Instance->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; htim->Instance->CCER = tmpccer; break; } case TIM_TS_TI1FP1: { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI1 Filter and Polarity */ TIM_TI1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_TI2FP2: { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); /* Configure TI2 Filter and Polarity */ TIM_TI2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); break; } case TIM_TS_ITR0: case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: #if defined (TIM5) case TIM_TS_ITR4: #endif /* TIM5 */ case TIM_TS_ITR5: case TIM_TS_ITR6: case TIM_TS_ITR7: case TIM_TS_ITR8: #if defined (TIM20) case TIM_TS_ITR9: #endif /* TIM20 */ #if defined (HRTIM1) case TIM_TS_ITR10: #endif /* HRTIM1 */ case TIM_TS_ITR11: { /* Check the parameter */ assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); break; } default: status = HAL_ERROR; break; } return status; } /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) { tmpccmr1 &= ~TIM_CCMR1_CC1S; tmpccmr1 |= TIM_ICSelection; } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= TIM_ICPolarity; /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; tmpccmr2 |= TIM_ICSelection; /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer ; } /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral * @param InputTriggerSource The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @arg TIM_TS_ITR4: Internal Trigger 4 (*) * @arg TIM_TS_ITR5: Internal Trigger 5 * @arg TIM_TS_ITR6: Internal Trigger 6 * @arg TIM_TS_ITR7: Internal Trigger 7 * @arg TIM_TS_ITR8: Internal Trigger 8 * @arg TIM_TS_ITR9: Internal Trigger 9 (*) * @arg TIM_TS_ITR10: Internal Trigger 10 * @arg TIM_TS_ITR11: Internal Trigger 11 * * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { uint32_t tmp; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /** * @brief Reset interrupt callbacks to the legacy weak callbacks. * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; htim->TriggerCallback = HAL_TIM_TriggerCallback; htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; htim->ErrorCallback = HAL_TIM_ErrorCallback; htim->CommutationCallback = HAL_TIMEx_CommutCallback; htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; htim->BreakCallback = HAL_TIMEx_BreakCallback; htim->Break2Callback = HAL_TIMEx_Break2Callback; htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c ================================================ /** ****************************************************************************** * @file stm32g4xx_hal_tim_ex.c * @author MCD Application Team * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: * + Time Hall Sensor Interface Initialization * + Time Hall Sensor Interface Start * + Time Complementary signal break and dead time configuration * + Time Master and Slave synchronization configuration * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) * + Time OCRef clear configuration * + Timer remapping capabilities configuration * + Timer encoder index configuration ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** @verbatim ============================================================================== ##### TIMER Extended features ##### ============================================================================== [..] The Timer Extended features include: (#) Complementary outputs with programmable dead-time for : (++) Output Compare (++) PWM generation (Edge and Center-aligned Mode) (++) One-pulse mode output (#) Synchronization circuit to control the timer with external signals and to interconnect several timers together. (#) Break input to put the timer output signals in reset state or in a known state. (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes (#) In case of Pulse on compare, configure pulse length and delay (#) Encoder index configuration ##### How to use this driver ##### ============================================================================== [..] (#) Initialize the TIM low level resources by implementing the following functions depending on the selected feature: (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() (#) Initialize the TIM low level resources : (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); (##) TIM pins configuration (+++) Enable the clock for the TIM GPIOs using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function. (#) Configure the TIM in the desired functioning mode using one of the initialization function of this driver: (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the Timer Hall Sensor Interface and the commutation event with the corresponding Interrupt and DMA request if needed (Note that One Timer is used to interface with the Hall sensor Interface and another Timer should be used to use the commutation event). (#) In case of Pulse On Compare: (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler (#) Activate the TIM peripheral using one of the start functions: (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ */ /** @defgroup TIMEx TIMEx * @brief TIM Extended HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup TIMEx_Private_Constants TIM Extended Private Constants * @{ */ /* Timeout for break input rearm */ #define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ /** * @} */ /* End of private constants --------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions * @{ */ /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions * @brief Timer Hall Sensor functions * @verbatim ============================================================================== ##### Timer Hall Sensor functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure TIM HAL Sensor. (+) De-initialize TIM HAL Sensor. (+) Start the Hall Sensor Interface. (+) Stop the Hall Sensor Interface. (+) Start the Hall Sensor Interface and enable interrupts. (+) Stop the Hall Sensor Interface and disable interrupts. (+) Start the Hall Sensor Interface and enable DMA transfers. (+) Stop the Hall Sensor Interface and disable DMA transfers. @endverbatim * @{ */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. * @note When the timer instance is initialized in Hall Sensor Interface mode, * timer channels 1 and channel 2 are reserved and cannot be used for * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; /* Check the TIM handle allocation */ if (htim == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); if (htim->State == HAL_TIM_STATE_RESET) { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) /* Reset interrupt callbacks to legacy week callbacks */ TIM_ResetCallback(htim); if (htim->HallSensor_MspInitCallback == NULL) { htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->HallSensor_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIMEx_HallSensor_MspInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->IC1Prescaler; /* Enable the Hall sensor interface (XOR function of the three inputs) */ htim->Instance->CR2 |= TIM_CR2_TI1S; /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1F_ED; /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ OC_Config.OCFastMode = TIM_OCFAST_DISABLE; OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; OC_Config.OCMode = TIM_OCMODE_PWM2; OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; OC_Config.Pulse = sConfig->Commutation_Delay; TIM_OC2_SetConfig(htim->Instance, &OC_Config); /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to 101 */ htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the TIM Hall Sensor interface * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); htim->State = HAL_TIM_STATE_BUSY; /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) if (htim->HallSensor_MspDeInitCallback == NULL) { htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; } /* DeInit the low level hardware */ htim->HallSensor_MspDeInitCallback(htim); #else /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; /* Change the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Initializes the TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file */ } /** * @brief DeInitializes TIM Hall Sensor MSP. * @param htim TIM Hall Sensor Interface handle * @retval None */ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file */ } /** * @brief Starts the TIM Hall Sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall sensor Interface. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @param pData The destination Buffer address. * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel state */ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. * @param htim TIM Hall Sensor Interface handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts 1 event */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions * @verbatim ============================================================================== ##### Timer Complementary Output Compare functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary Output Compare/PWM. (+) Stop the Complementary Output Compare/PWM. (+) Start the Complementary Output Compare/PWM and enable interrupts. (+) Stop the Complementary Output Compare/PWM and disable interrupts. (+) Start the Complementary Output Compare/PWM and enable DMA transfers. (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. @endverbatim * @{ */ /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM OC handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Output Compare interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. * @param htim TIM Output Compare handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Output Compare DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Output Compare interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions * @brief Timer Complementary PWM functions * @verbatim ============================================================================== ##### Timer Complementary PWM functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary PWM. (+) Stop the Complementary PWM. (+) Start the Complementary PWM and enable interrupts. (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. (+) Start the Complementary Input Capture measurement. (+) Stop the Complementary Input Capture. (+) Start the Complementary Input Capture and enable interrupts. (+) Stop the Complementary Input Capture and disable interrupts. (+) Start the Complementary Input Capture and enable DMA transfers. (+) Stop the Complementary Input Capture and disable DMA transfers. (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } /* Return function status */ return HAL_OK; } /** * @brief Stops the PWM signal generation on the complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Check the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) { return HAL_ERROR; } /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); switch (Channel) { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the TIM Break interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output * @param htim TIM handle * @param Channel TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); /* Set the TIM complementary channel state */ if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { return HAL_ERROR; } switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); break; } case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); break; } case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); break; } case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) { __HAL_TIM_ENABLE(htim); } } else { __HAL_TIM_ENABLE(htim); } } /* Return function status */ return status; } /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output * @param htim TIM handle * @param Channel TIM Channel to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); switch (Channel) { case TIM_CHANNEL_1: { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } default: status = HAL_ERROR; break; } if (status == HAL_OK) { /* Disable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } /* Return function status */ return status; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions * @verbatim ============================================================================== ##### Timer Complementary One Pulse functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Start the Complementary One Pulse generation. (+) Stop the Complementary One Pulse. (+) Start the Complementary One Pulse and enable interrupts. (+) Stop the Complementary One Pulse and disable interrupts. @endverbatim * @{ */ /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. * @note OutputChannel must match the pulse output channel chosen when calling * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions * @brief Peripheral Control functions * @verbatim ============================================================================== ##### Peripheral Control functions ##### ============================================================================== [..] This section provides functions allowing to: (+) Configure the commutation event in case of use of the Hall sensor interface. (+) Configure Output channels for OC and PWM mode. (+) Configure Complementary channels, break features and dead time. (+) Configure Master synchronization. (+) Configure timer remapping capabilities. (+) Select timer input source. (+) Enable or disable channel grouping. (+) Configure Pulse on compare. (+) Configure Encoder index. @endverbatim * @{ */ /** * @brief Configure the TIM commutation event sequence. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_ITR4: Internal trigger 4 selected (*) * @arg TIM_TS_ITR5: Internal trigger 5 selected * @arg TIM_TS_ITR6: Internal trigger 6 selected * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_ITR9: Internal trigger 9 selected (*) * @arg TIM_TS_ITR10: Internal trigger 10 selected * @arg TIM_TS_ITR11: Internal trigger 11 selected * @arg TIM_TS_NONE: No trigger is needed * * (*) Value not defined in all devices. * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); __HAL_LOCK(htim); #if defined(TIM5) && defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM5) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with interrupt. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_ITR4: Internal trigger 4 selected (*) * @arg TIM_TS_ITR5: Internal trigger 5 selected * @arg TIM_TS_ITR6: Internal trigger 6 selected * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_ITR9: Internal trigger 9 selected (*) * @arg TIM_TS_ITR10: Internal trigger 10 selected * @arg TIM_TS_ITR11: Internal trigger 11 selected * @arg TIM_TS_NONE: No trigger is needed * * (*) Value not defined in all devices. * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); __HAL_LOCK(htim); #if defined(TIM5) && defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM5) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Disable Commutation DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); /* Enable the Commutation Interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure the TIM commutation event sequence with DMA. * @note This function is mandatory to use the commutation event in order to * update the configuration at each commutation detection on the TRGI input of the Timer, * the typical use of this feature is with the use of another Timer(interface Timer) * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set * @param htim TIM handle * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_ITR4: Internal trigger 4 selected (*) * @arg TIM_TS_ITR5: Internal trigger 5 selected * @arg TIM_TS_ITR6: Internal trigger 6 selected * @arg TIM_TS_ITR7: Internal trigger 7 selected * @arg TIM_TS_ITR8: Internal trigger 8 selected * @arg TIM_TS_ITR9: Internal trigger 9 selected (*) * @arg TIM_TS_ITR10: Internal trigger 10 selected * @arg TIM_TS_ITR11: Internal trigger 11 selected * @arg TIM_TS_NONE: No trigger is needed * * (*) Value not defined in all devices. * * @param CommutationSource the Commutation Event source * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); __HAL_LOCK(htim); #if defined(TIM5) && defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM5) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #elif defined(TIM20) if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= InputTrigger; } /* Select the Capture Compare preload feature */ htim->Instance->CR2 |= TIM_CR2_CCPC; /* Select the Commutation event source */ htim->Instance->CR2 &= ~TIM_CR2_CCUS; htim->Instance->CR2 |= CommutationSource; /* Enable the Commutation DMA Request */ /* Set the DMA Commutation Callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; /* Disable Commutation Interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); /* Enable the Commutation DMA Request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the TIM in master mode. * @param htim TIM handle. * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @note Interrupts can be generated when an active level is detected on the * break input, the break 2 input or the system break input. Break * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); /* Check input state */ __HAL_LOCK(htim); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Set BREAK AF mode */ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); } if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) { /* Check the parameters */ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set BREAK2 AF mode */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configures the break input source. * @param htim TIM handle. * @param BreakInput Break input to configure * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input * @param sBreakInputConfig Break input source configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; uint32_t bkin_enable_mask; uint32_t bkin_polarity_mask; uint32_t bkin_enable_bitpos; uint32_t bkin_polarity_bitpos; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); /* Check input state */ __HAL_LOCK(htim); switch (sBreakInputConfig->Source) { case TIM_BREAKINPUTSOURCE_BKIN: { bkin_enable_mask = TIM1_AF1_BKINE; bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; bkin_polarity_mask = TIM1_AF1_BKINP; bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP1: { bkin_enable_mask = TIM1_AF1_BKCMP1E; bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP1P; bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP2: { bkin_enable_mask = TIM1_AF1_BKCMP2E; bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP2P; bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP3: { bkin_enable_mask = TIM1_AF1_BKCMP3E; bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP3P; bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos; break; } case TIM_BREAKINPUTSOURCE_COMP4: { bkin_enable_mask = TIM1_AF1_BKCMP4E; bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos; bkin_polarity_mask = TIM1_AF1_BKCMP4P; bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos; break; } #if defined (COMP5) case TIM_BREAKINPUTSOURCE_COMP5: { bkin_enable_mask = TIM1_AF1_BKCMP5E; bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; } #endif /* COMP5 */ #if defined (COMP6) case TIM_BREAKINPUTSOURCE_COMP6: { bkin_enable_mask = TIM1_AF1_BKCMP6E; bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; } #endif /* COMP7 */ #if defined (COMP7) case TIM_BREAKINPUTSOURCE_COMP7: { bkin_enable_mask = TIM1_AF1_BKCMP7E; bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos; /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; } #endif /* COMP7 */ default: { bkin_enable_mask = 0U; bkin_polarity_mask = 0U; bkin_enable_bitpos = 0U; bkin_polarity_bitpos = 0U; break; } } switch (BreakInput) { case TIM_BREAKINPUT_BRK: { /* Get the TIMx_AF1 register value */ tmporx = htim->Instance->AF1; /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; /* Set the break input polarity */ tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; /* Set TIMx_AF1 */ htim->Instance->AF1 = tmporx; break; } case TIM_BREAKINPUT_BRK2: { /* Get the TIMx_AF2 register value */ tmporx = htim->Instance->AF2; /* Enable the break input */ tmporx &= ~bkin_enable_mask; tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; /* Set the break input polarity */ tmporx &= ~bkin_polarity_mask; tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; /* Set TIMx_AF2 */ htim->Instance->AF2 = tmporx; break; } default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Configures the TIMx Remapping input capabilities. * @param htim TIM handle. * @param Remap specifies the TIM remapping source. * For TIM1, the parameter can take one of the following values: * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output * @arg TIM_TIM1_ETR_COMP3 TIM1 ETR is connected to COMP3 output * @arg TIM_TIM1_ETR_COMP4 TIM1 ETR is connected to COMP4 output * @arg TIM_TIM1_ETR_COMP5 TIM1 ETR is connected to COMP5 output (*) * @arg TIM_TIM1_ETR_COMP6 TIM1 ETR is connected to COMP6 output (*) * @arg TIM_TIM1_ETR_COMP7 TIM1 ETR is connected to COMP7 output (*) * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 (*) * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 (*) * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 (*) * * For TIM2, the parameter can take one of the following values: * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output * @arg TIM_TIM2_ETR_COMP3 TIM2 ETR is connected to COMP3 output * @arg TIM_TIM2_ETR_COMP4 TIM2 ETR is connected to COMP4 output * @arg TIM_TIM2_ETR_COMP5 TIM2 ETR is connected to COMP5 output (*) * @arg TIM_TIM2_ETR_COMP6 TIM2 ETR is connected to COMP6 output (*) * @arg TIM_TIM2_ETR_COMP7 TIM2 ETR is connected to COMP7 output (*) * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin (*) * @arg TIM_TIM2_ETR_LSE * * For TIM3, the parameter can take one of the following values: * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output * @arg TIM_TIM3_ETR_COMP3 TIM3 ETR is connected to COMP3 output * @arg TIM_TIM3_ETR_COMP4 TIM3 ETR is connected to COMP4 output * @arg TIM_TIM3_ETR_COMP5 TIM3 ETR is connected to COMP5 output (*) * @arg TIM_TIM3_ETR_COMP6 TIM3 ETR is connected to COMP6 output (*) * @arg TIM_TIM3_ETR_COMP7 TIM3 ETR is connected to COMP7 output (*) * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin * @arg TIM_TIM3_ETR_ADC2_AWD1 TIM3 ETR is connected to ADC2 AWD1 * @arg TIM_TIM3_ETR_ADC2_AWD2 TIM3 ETR is connected to ADC2 AWD2 * @arg TIM_TIM3_ETR_ADC2_AWD3 TIM3 ETR is connected to ADC2 AWD3 * * For TIM4, the parameter can take one of the following values: * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output * @arg TIM_TIM4_ETR_COMP3 TIM4 ETR is connected to COMP3 output * @arg TIM_TIM4_ETR_COMP4 TIM4 ETR is connected to COMP4 output * @arg TIM_TIM4_ETR_COMP5 TIM4 ETR is connected to COMP5 output (*) * @arg TIM_TIM4_ETR_COMP6 TIM4 ETR is connected to COMP6 output (*) * @arg TIM_TIM4_ETR_COMP7 TIM4 ETR is connected to COMP7 output (*) * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin (*) * * For TIM5, the parameter can take one of the following values: (**) * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO (*) * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output (*) * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*) * @arg TIM_TIM5_ETR_COMP3 TIM5 ETR is connected to COMP3 output (*) * @arg TIM_TIM5_ETR_COMP4 TIM5 ETR is connected to COMP4 output (*) * @arg TIM_TIM5_ETR_COMP5 TIM5 ETR is connected to COMP5 output (*) * @arg TIM_TIM5_ETR_COMP6 TIM5 ETR is connected to COMP6 output (*) * @arg TIM_TIM5_ETR_COMP7 TIM5 ETR is connected to COMP7 output (*) * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin (*) * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin (*) * * For TIM8, the parameter can take one of the following values: * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output * @arg TIM_TIM8_ETR_COMP3 TIM8 ETR is connected to COMP3 output * @arg TIM_TIM8_ETR_COMP4 TIM8 ETR is connected to COMP4 output * @arg TIM_TIM8_ETR_COMP5 TIM8 ETR is connected to COMP5 output (*) * @arg TIM_TIM8_ETR_COMP6 TIM8 ETR is connected to COMP6 output (*) * @arg TIM_TIM8_ETR_COMP7 TIM8 ETR is connected to COMP7 output (*) * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8 ETR is connected to ADC2 AWD1 * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8 ETR is connected to ADC2 AWD2 * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8 ETR is connected to ADC2 AWD3 * @arg TIM_TIM8_ETR_ADC3_AWD1 TIM8 ETR is connected to ADC3 AWD1 (*) * @arg TIM_TIM8_ETR_ADC3_AWD2 TIM8 ETR is connected to ADC3 AWD2 (*) * @arg TIM_TIM8_ETR_ADC3_AWD3 TIM8 ETR is connected to ADC3 AWD3 (*) * * For TIM20, the parameter can take one of the following values: (**) * @arg TIM_TIM20_ETR_GPIO TIM20 ETR is connected to GPIO * @arg TIM_TIM20_ETR_COMP1 TIM20 ETR is connected to COMP1 output (*) * @arg TIM_TIM20_ETR_COMP2 TIM20 ETR is connected to COMP2 output (*) * @arg TIM_TIM20_ETR_COMP3 TIM20 ETR is connected to COMP3 output (*) * @arg TIM_TIM20_ETR_COMP4 TIM20 ETR is connected to COMP4 output (*) * @arg TIM_TIM20_ETR_COMP5 TIM20 ETR is connected to COMP5 output (*) * @arg TIM_TIM20_ETR_COMP6 TIM20 ETR is connected to COMP6 output (*) * @arg TIM_TIM20_ETR_COMP7 TIM20 ETR is connected to COMP7 output (*) * @arg TIM_TIM20_ETR_ADC3_AWD1 TIM20 ETR is connected to ADC3 AWD1 (*) * @arg TIM_TIM20_ETR_ADC3_AWD2 TIM20 ETR is connected to ADC3 AWD2 (*) * @arg TIM_TIM20_ETR_ADC3_AWD3 TIM20 ETR is connected to ADC3 AWD3 (*) * @arg TIM_TIM20_ETR_ADC5_AWD1 TIM20 ETR is connected to ADC5 AWD1 (*) * @arg TIM_TIM20_ETR_ADC5_AWD2 TIM20 ETR is connected to ADC5 AWD2 (*) * @arg TIM_TIM20_ETR_ADC5_AWD3 TIM20 ETR is connected to ADC5 AWD3 (*) * * (*) Value not defined in all devices. \n * (**) Register not available in all devices. * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { /* Check parameters */ assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); assert_param(IS_TIM_REMAP(Remap)); __HAL_LOCK(htim); MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Select the timer input source * @param htim TIM handle. * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TI1 input channel * @arg TIM_CHANNEL_2: TI2 input channel * @arg TIM_CHANNEL_3: TI3 input channel * @arg TIM_CHANNEL_4: TI4 input channel * @param TISelection specifies the timer input source * For TIM1 this parameter can be one of the following values: * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output * @arg TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to COMP3 output * @arg TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to COMP4 output * * For TIM2 this parameter can be one of the following values: * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output * @arg TIM_TIM2_TI1_COMP3: TIM2 TI1 is connected to COMP3 output * @arg TIM_TIM2_TI1_COMP4: TIM2 TI1 is connected to COMP4 output * @arg TIM_TIM2_TI1_COMP5: TIM2 TI1 is connected to COMP5 output (*) * * @arg TIM_TIM2_TI2_GPIO: TIM1 TI2 is connected to GPIO * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output * @arg TIM_TIM2_TI2_COMP3: TIM2 TI2 is connected to COMP3 output * @arg TIM_TIM2_TI2_COMP4: TIM2 TI2 is connected to COMP4 output * @arg TIM_TIM2_TI2_COMP6: TIM2 TI2 is connected to COMP6 output (*) * * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO * @arg TIM_TIM2_TI3_COMP4: TIM2 TI3 is connected to COMP4 output * * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output * * For TIM3 this parameter can be one of the following values: * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output * @arg TIM_TIM3_TI1_COMP3: TIM3 TI1 is connected to COMP3 output * @arg TIM_TIM3_TI1_COMP4: TIM3 TI1 is connected to COMP4 output * @arg TIM_TIM3_TI1_COMP5: TIM3 TI1 is connected to COMP5 output (*) * @arg TIM_TIM3_TI1_COMP6: TIM3 TI1 is connected to COMP6 output (*) * @arg TIM_TIM3_TI1_COMP7: TIM3 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output * @arg TIM_TIM3_TI2_COMP3: TIM3 TI2 is connected to COMP3 output * @arg TIM_TIM3_TI2_COMP4: TIM3 TI2 is connected to COMP4 output * @arg TIM_TIM3_TI2_COMP5: TIM3 TI2 is connected to COMP5 output (*) * @arg TIM_TIM3_TI2_COMP6: TIM3 TI2 is connected to COMP6 output (*) * @arg TIM_TIM3_TI2_COMP7: TIM3 TI2 is connected to COMP7 output (*) * * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output * For TIM4 this parameter can be one of the following values: * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output * @arg TIM_TIM4_TI1_COMP3: TIM4 TI1 is connected to COMP3 output * @arg TIM_TIM4_TI1_COMP4: TIM4 TI1 is connected to COMP4 output * @arg TIM_TIM4_TI1_COMP5: TIM4 TI1 is connected to COMP5 output (*) * @arg TIM_TIM4_TI1_COMP6: TIM4 TI1 is connected to COMP6 output (*) * @arg TIM_TIM4_TI1_COMP7: TIM4 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output * @arg TIM_TIM4_TI2_COMP3: TIM4 TI2 is connected to COMP3 output * @arg TIM_TIM4_TI2_COMP4: TIM4 TI2 is connected to COMP4 output * @arg TIM_TIM4_TI2_COMP5: TIM4 TI2 is connected to COMP5 output (*) * @arg TIM_TIM4_TI2_COMP6: TIM4 TI2 is connected to COMP6 output (*) * @arg TIM_TIM4_TI2_COMP7: TIM4 TI2 is connected to COMP7 output (*) * * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO * @arg TIM_TIM4_TI3_COMP5: TIM4 TI3 is connected to COMP5 output (*) * * @arg TIM_TIM4_TI4_GPIO: TIM4 TI4 is connected to GPIO * @arg TIM_TIM4_TI4_COMP6: TIM4 TI4 is connected to COMP6 output (*) * * For TIM5 this parameter can be one of the following values: (**) * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI clock (*) * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE clock (*) * @arg TIM_TIM5_TI1_RTC_WK: TIM5 TI1 is connected to RTC Wakeup (*) * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output (*) * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*) * @arg TIM_TIM5_TI1_COMP3: TIM5 TI1 is connected to COMP3 output (*) * @arg TIM_TIM5_TI1_COMP4: TIM5 TI1 is connected to COMP4 output (*) * @arg TIM_TIM5_TI1_COMP5: TIM5 TI1 is connected to COMP5 output (*) * @arg TIM_TIM5_TI1_COMP6: TIM5 TI1 is connected to COMP6 output (*) * @arg TIM_TIM5_TI1_COMP7: TIM5 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output * @arg TIM_TIM5_TI2_COMP3: TIM5 TI2 is connected to COMP3 output * @arg TIM_TIM5_TI2_COMP4: TIM5 TI2 is connected to COMP4 output * @arg TIM_TIM5_TI2_COMP5: TIM5 TI2 is connected to COMP5 output (*) * @arg TIM_TIM5_TI2_COMP6: TIM5 TI2 is connected to COMP6 output (*) * @arg TIM_TIM5_TI2_COMP7: TIM5 TI2 is connected to COMP7 output (*) * * For TIM8 this parameter can be one of the following values: * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output * @arg TIM_TIM8_TI1_COMP3: TIM8 TI1 is connected to COMP3 output * @arg TIM_TIM8_TI1_COMP4: TIM8 TI1 is connected to COMP4 output * * For TIM15 this parameter can be one of the following values: * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE clock * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output * @arg TIM_TIM15_TI1_COMP5: TIM15 TI1 is connected to COMP5 output (*) * @arg TIM_TIM15_TI1_COMP7: TIM15 TI1 is connected to COMP7 output (*) * * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output * @arg TIM_TIM15_TI2_COMP3: TIM15 TI2 is connected to COMP3 output * @arg TIM_TIM15_TI2_COMP6: TIM15 TI2 is connected to COMP6 output (*) * @arg TIM_TIM15_TI2_COMP7: TIM15 TI2 is connected to COMP7 output (*) * * For TIM16 this parameter can be one of the following values: * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO * @arg TIM_TIM16_TI1_COMP6: TIM16 TI1 is connected to COMP6 output (*) * @arg TIM_TIM16_TI1_MCO: TIM15 TI1 is connected to MCO output * @arg TIM_TIM16_TI1_HSE_32: TIM15 TI1 is connected to HSE div 32 * @arg TIM_TIM16_TI1_RTC_WK: TIM15 TI1 is connected to RTC wakeup * @arg TIM_TIM16_TI1_LSE: TIM15 TI1 is connected to LSE clock * @arg TIM_TIM16_TI1_LSI: TIM15 TI1 is connected to LSI clock * * For TIM17 this parameter can be one of the following values: * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO * @arg TIM_TIM17_TI1_COMP5: TIM17 TI1 is connected to COMP5 output (*) * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO output * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 * @arg TIM_TIM17_TI1_RTC_WK: TIM17 TI1 is connected to RTC wakeup * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE clock * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI clock * For TIM20 this parameter can be one of the following values: (**) * @arg TIM_TIM20_TI1_GPIO: TIM20 TI1 is connected to GPIO * @arg TIM_TIM20_TI1_COMP1: TIM20 TI1 is connected to COMP1 output (*) * @arg TIM_TIM20_TI1_COMP2: TIM20 TI1 is connected to COMP2 output (*) * @arg TIM_TIM20_TI1_COMP3: TIM20 TI1 is connected to COMP3 output (*) * @arg TIM_TIM20_TI1_COMP4: TIM20 TI1 is connected to COMP4 output (*) * * (*) Value not defined in all devices. \n * (**) Register not available in all devices. * * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; /* Check parameters */ assert_param(IS_TIM_TISEL_TIX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_TISEL(TISelection)); __HAL_LOCK(htim); switch (Channel) { case TIM_CHANNEL_1: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); /* If required, set OR bit to request HSE/32 clock */ if (IS_TIM_HSE32_INSTANCE(htim->Instance)) { SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN); } else { CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN); } break; case TIM_CHANNEL_2: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); break; case TIM_CHANNEL_3: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); break; case TIM_CHANNEL_4: MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); break; default: status = HAL_ERROR; break; } __HAL_UNLOCK(htim); return status; } /** * @brief Group channel 5 and channel 1, 2 or 3 * @param htim TIM handle. * @param Channels specifies the reference signal(s) the OC5REF is combined with. * This parameter can be any combination of the following values: * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) { /* Check parameters */ assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); assert_param(IS_TIM_GROUPCH5(Channels)); /* Process Locked */ __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; /* Clear GC5Cx bit fields */ htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); /* Set GC5Cx bit fields */ htim->Instance->CCR5 |= Channels; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Disarm the designated break input (when it operates in bidirectional mode). * @param htim TIM handle. * @param BreakInput Break input to disarm * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input * @note The break input can be disarmed only when it is configured in * bidirectional mode and when when MOE is reset. * @note Purpose is to be able to have the input voltage back to high-state, * whatever the time constant on the output . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpbdtr; /* Check the parameters */ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) { case TIM_BREAKINPUT_BRK: { /* Check initial conditions */ tmpbdtr = READ_REG(htim->Instance->BDTR); if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) { /* Break input BRK is disarmed */ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); } break; } case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ tmpbdtr = READ_REG(htim->Instance->BDTR); if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) { /* Break input BRK is disarmed */ SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); } break; } default: status = HAL_ERROR; break; } return status; } /** * @brief Arm the designated break input (when it operates in bidirectional mode). * @param htim TIM handle. * @param BreakInput Break input to arm * This parameter can be one of the following values: * @arg TIM_BREAKINPUT_BRK: Timer break input * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input * @note Arming is possible at anytime, even if fault is present. * @note Break input is automatically armed as soon as MOE bit is set. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; /* Check the parameters */ assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAKINPUT(BreakInput)); switch (BreakInput) { case TIM_BREAKINPUT_BRK: { /* Check initial conditions */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) { /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { return HAL_TIMEOUT; } } } } break; } case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) { /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { /* New check to avoid false timeout detection in case of preemption */ if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { return HAL_TIMEOUT; } } } } break; } default: status = HAL_ERROR; break; } return status; } /** * @brief Enable dithering * @param htim TIM handle * @note Main usage is PWM mode * @note This function must be called when timer is stopped or disabled (CEN =0) * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers * (corresponds to 4094 for the integer part and 15 for the dithered part). * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() * can be used to calculate period (ARR) and delay (CCRx) value. * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); return HAL_OK; } /** * @brief Disable dithering * @param htim TIM handle * @note This function must be called when timer is stopped or disabled (CEN =0) * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers * - ARR and CCRx values are limited to 0xFFEF in dithering mode * (corresponds to 4094 for the integer part and 15 for the dithered part). * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); return HAL_OK; } /** * @brief Initializes the pulse on compare pulse width and pulse prescaler * @param htim TIM Output Compare handle * @param PulseWidthPrescaler Pulse width prescaler * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7 * @param PulseWidth Pulse width * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, uint32_t PulseWidth) { uint32_t tmpecr; /* Check the parameters */ assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance)); assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth)); assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler)); /* Process Locked */ __HAL_LOCK(htim); /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx ECR register value */ tmpecr = htim->Instance->ECR; /* Reset the Pulse width prescaler and the Pulse width */ tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW); /* Set the Pulse width prescaler and Pulse width*/ tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos; tmpecr |= PulseWidth << TIM_ECR_PW_Pos; /* Write to TIMx ECR */ htim->Instance->ECR = tmpecr; /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Release Lock */ __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register) * @param htim TIM handle * @param Source Source of slave mode selection preload * This parameter can be one of the following values: * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source)); MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source); return HAL_OK; } /** * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register) * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); return HAL_OK; } /** * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register) * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); return HAL_OK; } /** * @brief Enable deadtime preload * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); return HAL_OK; } /** * @brief Disable deadtime preload * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); return HAL_OK; } /** * @brief Configure deadtime * @param htim TIM handle * @param Deadtime Deadtime value * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_DEADTIME(Deadtime)); MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime); return HAL_OK; } /** * @brief Configure asymmetrical deadtime * @param htim TIM handle * @param FallingDeadtime Falling edge deadtime value * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_DEADTIME(FallingDeadtime)); MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); return HAL_OK; } /** * @brief Enable asymmetrical deadtime * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); return HAL_OK; } /** * @brief Disable asymmetrical deadtime * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); return HAL_OK; } /** * @brief Configures the encoder index. * @note warning in case of encoder mode clock plus direction * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN * @param htim TIM handle. * @param sEncoderIndexConfig Encoder index configuration * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity)); assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler)); assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter)); assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable)); assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position)); assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction)); /* Process Locked */ __HAL_LOCK(htim); /* Configures the TIMx External Trigger (ETR) which is used as Index input */ TIM_ETR_SetConfig(htim->Instance, sEncoderIndexConfig->Prescaler, sEncoderIndexConfig->Polarity, sEncoderIndexConfig->Filter); /* Configures the encoder index */ MODIFY_REG(htim->Instance->ECR, TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, (sEncoderIndexConfig->Direction | ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | sEncoderIndexConfig->Position | TIM_ECR_IE)); __HAL_UNLOCK(htim); return HAL_OK; } /** * @brief Enable encoder index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->ECR, TIM_ECR_IE); return HAL_OK; } /** * @brief Disable encoder index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); return HAL_OK; } /** * @brief Enable encoder first index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); return HAL_OK; } /** * @brief Disable encoder first index * @param htim TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); return HAL_OK; } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions * @brief Extended Callbacks functions * @verbatim ============================================================================== ##### Extended Callbacks functions ##### ============================================================================== [..] This section provides Extended TIM callback functions: (+) Timer Commutation callback (+) Timer Break callback @endverbatim * @{ */ /** * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } /** * @brief Hall commutation changed half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file */ } /** * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } /** * @brief Hall Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } /** * @brief Encoder index callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file */ } /** * @brief Direction change callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file */ } /** * @brief Index error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_IndexErrorCallback could be implemented in the user file */ } /** * @brief Transition error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) { /* Prevent unused argument(s) compilation warning */ UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file */ } /** * @} */ /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions * @brief Extended Peripheral State functions * @verbatim ============================================================================== ##### Extended Peripheral State functions ##### ============================================================================== [..] This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim * @{ */ /** * @brief Return the TIM Hall Sensor interface handle state. * @param htim TIM Hall Sensor handle * @retval HAL state */ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) { return htim->State; } /** * @brief Return actual state of the TIM complementary channel. * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); return channel_state; } /** * @} */ /** * @} */ /* Private functions ---------------------------------------------------------*/ /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ /** * @brief TIM DMA Commutation callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Commutation half complete callback. * @param hdma pointer to DMA handle. * @retval None */ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationHalfCpltCallback(htim); #else HAL_TIMEx_CommutHalfCpltCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /** * @brief TIM DMA Delay Pulse complete callback (complementary channel). * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); } } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_PWM_PulseFinishedCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA error callback (complementary channel) * @param hdma pointer to DMA handle. * @retval None */ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } else { /* nothing to do */ } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 * @arg TIM_CHANNEL_2: TIM Channel 2 * @arg TIM_CHANNEL_3: TIM Channel 3 * @arg TIM_CHANNEL_4: TIM Channel 4 * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) { uint32_t tmp; tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ /* Reset the CCxNE Bit */ TIMx->CCER &= ~tmp; /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ } /** * @} */ #endif /* HAL_TIM_MODULE_ENABLED */ /** * @} */ /** * @} */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c ================================================ /** ****************************************************************************** * @file stm32g4xx_ll_adc.c * @author MCD Application Team * @brief ADC LL module driver ****************************************************************************** * @attention * * Copyright (c) 2019 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_ll_adc.h" #include "stm32g4xx_ll_bus.h" #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32G4xx_LL_Driver * @{ */ #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5) /** @addtogroup ADC_LL ADC * @{ */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @addtogroup ADC_LL_Private_Constants * @{ */ /* Definitions of ADC hardware constraints delays */ /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ /* not timeout values: */ /* Timeout values for ADC operations are dependent to device clock */ /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ /* values definition. */ /* Note: ADC timeout values are defined here in CPU cycles to be independent */ /* of device clock setting. */ /* In user application, ADC timeout values should be defined with */ /* temporal values, in function of device clock settings. */ /* Highest ratio CPU clock frequency vs ADC clock frequency: */ /* - ADC clock from synchronous clock with AHB prescaler 512, */ /* ADC prescaler 4. */ /* Ratio max = 512 *4 = 2048 */ /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */ /* Highest CPU clock PLL (PLLR). */ /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */ /* = 3968 */ /* Unit: CPU cycles. */ #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL) #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) /** * @} */ /* Private macros ------------------------------------------------------------*/ /** @addtogroup ADC_LL_Private_Macros * @{ */ /* Check of parameters for configuration of ADC hierarchical scope: */ /* common to several ADC instances. */ #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ ) /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC instance. */ #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ ) #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ ) #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ ) /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC group regular */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) \ ) \ ) \ ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ ) \ ) \ ) #elif defined(STM32G471xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || (((__ADC_INSTANCE__) == ADC3) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ ) \ ) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) \ ) \ || (((__ADC_INSTANCE__) == ADC3) \ && ( \ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ ) \ ) \ ) #endif #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ ) #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ ) #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ ) #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ ) #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ ) /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC group injected */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #elif defined(STM32G471xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) \ ) \ || ((((__ADC_INSTANCE__) == ADC3)) \ && ( \ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ ) \ ) \ ) #endif #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ ) #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ ) #if defined(ADC_MULTIMODE_SUPPORT) /* Check of parameters for configuration of ADC hierarchical scope: */ /* multimode. */ #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ ) #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \ ) #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ ) #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ ) #endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADC_LL_Exported_Functions * @{ */ /** @addtogroup ADC_LL_EF_Init * @{ */ /** * @brief De-initialize registers of all ADC instances belonging to * the same ADC common instance to their default reset values. * @note This function is performing a hard reset, using high level * clock source RCC ADC reset. * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * To de-initialize only 1 ADC instance, use * function @ref LL_ADC_DeInit(). * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are de-initialized * - ERROR: not applicable */ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); if (ADCxy_COMMON == ADC12_COMMON) { /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12); /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12); } #if defined(ADC345_COMMON) else { /* Force reset of ADC clock (core clock) */ LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345); /* Release reset of ADC clock (core clock) */ LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345); } #endif return SUCCESS; } /** * @brief Initialize some features of ADC common parameters * (all ADC instances belonging to the same ADC common instance) * and multimode (for devices with several ADC instances available). * @note The setting of ADC common parameters is conditioned to * ADC instances state: * All ADC instances belonging to the same ADC common instance * must be disabled. * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); #if defined(ADC_MULTIMODE_SUPPORT) assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); } #endif /* ADC_MULTIMODE_SUPPORT */ /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ /* (all ADC instances belonging to the same ADC common instance) */ /* - Set ADC clock (conversion clock) */ /* - multimode (if several ADC instances available on the */ /* selected device) */ /* - Set ADC multimode configuration */ /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY , ADC_CommonInitStruct->CommonClock | ADC_CommonInitStruct->Multimode | ADC_CommonInitStruct->MultiDMATransfer | ADC_CommonInitStruct->MultiTwoSamplingDelay ); } else { MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_MDMA | ADC_CCR_DELAY , ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } #else LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); #endif } else { /* Initialization error: One or several ADC instances belonging to */ /* the same ADC common instance are not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) { /* Set ADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; #endif /* ADC_MULTIMODE_SUPPORT */ } /** * @brief De-initialize registers of the selected ADC instance * to their default reset values. * @note To reset all ADC instances quickly (perform a hard reset), * use function @ref LL_ADC_CommonDeInit(). * @note If this functions returns error status, it means that ADC instance * is in an unknown state. * In this case, perform a hard reset using high level * clock source RCC ADC reset. * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * Refer to function @ref LL_ADC_CommonDeInit(). * @param ADCx ADC instance * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are de-initialized * - ERROR: ADC registers are not de-initialized */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { ErrorStatus status = SUCCESS; __IO uint32_t timeout_cpu_cycles = 0UL; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); /* Disable ADC instance if not already disabled. */ if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); /* Stop potential ADC conversion on going on ADC group regular. */ if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_REG_StopConversion(ADCx); } } /* Set ADC group injected trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); /* Stop potential ADC conversion on going on ADC group injected. */ if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_INJ_StopConversion(ADCx); } } /* Wait for ADC conversions are effectively stopped */ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) { timeout_cpu_cycles--; if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; break; } } /* Flush group injected contexts queue (register JSQR): */ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ /* contexts queue is maintained with the last active context). */ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); /* Disable the ADC instance */ LL_ADC_Disable(ADCx); /* Wait for ADC instance is effectively disabled */ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) { timeout_cpu_cycles--; if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; break; } } } /* Check whether ADC state is compliant with expected state */ if (READ_BIT(ADCx->CR, (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) ) == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ CLEAR_BIT(ADCx->IER, (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR | LL_ADC_IT_EOSMP | LL_ADC_IT_JEOC | LL_ADC_IT_JEOS | LL_ADC_IT_JQOVF | LL_ADC_IT_AWD1 | LL_ADC_IT_AWD2 | LL_ADC_IT_AWD3 ) ); /* Reset register ISR */ SET_BIT(ADCx->ISR, (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_EOSMP | LL_ADC_FLAG_JEOC | LL_ADC_FLAG_JEOS | LL_ADC_FLAG_JQOVF | LL_ADC_FLAG_AWD1 | LL_ADC_FLAG_AWD2 | LL_ADC_FLAG_AWD3 ) ); /* Reset register CR */ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ /* access mode "read-set": no direct reset applicable. */ /* - Reset Calibration mode to default setting (single ended). */ /* - Disable ADC internal voltage regulator. */ /* - Enable ADC deep power down. */ /* Note: ADC internal voltage regulator disable and ADC deep power */ /* down enable are conditioned to ADC state disabled: */ /* already done above. */ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); /* Reset register CFGR */ MODIFY_REG(ADCx->CFGR, (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN), ADC_CFGR_JQDIS ); /* Reset register CFGR2 */ CLEAR_BIT(ADCx->CFGR2, (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG | ADC_CFGR2_GCOMP | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) ); /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) ); /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) ); /* Reset register TR1 */ MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); /* Reset register TR2 */ MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); /* Reset register TR3 */ MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L) ); /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) ); /* Reset register SQR3 */ CLEAR_BIT(ADCx->SQR3, (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) ); /* Reset register SQR4 */ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); /* Reset register DR */ /* Note: bits in access mode read only, no direct reset applicable */ /* Reset register OFR1 */ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS); /* Reset register OFR2 */ CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS); /* Reset register OFR3 */ CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); /* Reset register OFR4 */ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ /* Reset register AWD2CR */ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); /* Reset register AWD3CR */ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); /* Reset register DIFSEL */ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); /* Reset register CALFACT */ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); /* Reset register GCOMP */ CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF); } else { /* ADC instance is in an unknown state */ /* Need to performing a hard reset of ADC instance, using high level */ /* clock source RCC ADC reset. */ /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ status = ERROR; } return status; } /** * @brief Initialize some features of ADC instance. * @note These parameters have an impact on ADC scope: ADC instance. * Affects both group regular and group injected (availability * of ADC group injected depends on STM32 families). * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Instance . * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 families. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. * @note After using this function, some other features must be configured * using LL unitary functions. * The minimum configuration remaining to be done is: * - Set ADC group regular or group injected sequencer: * map channel on the selected sequencer rank. * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ /* - Set ADC data resolution */ /* - Set ADC conversion data alignment */ /* - Set ADC low power mode */ MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES | ADC_CFGR_ALIGN | ADC_CFGR_AUTDLY , ADC_InitStruct->Resolution | ADC_InitStruct->DataAlignment | ADC_InitStruct->LowPowerMode ); } else { /* Initialization error: ADC instance is not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_InitTypeDef field to default value. * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) { /* Set ADC_InitStruct fields to default values */ /* Set fields of ADC instance */ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; } /** * @brief Initialize some features of ADC group regular. * @note These parameters have an impact on ADC scope: ADC group regular. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "REG"). * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 families. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. * @note After using this function, other features must be configured * using LL unitary functions. * The minimum configuration remaining to be done is: * - Set ADC group regular or group injected sequencer: * map channel on the selected sequencer rank. * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); /* ADC group regular continuous mode and discontinuous mode */ /* can not be enabled simultenaeously */ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ /* - Set ADC group regular trigger source */ /* - Set ADC group regular sequencer length */ /* - Set ADC group regular sequencer discontinuous mode */ /* - Set ADC group regular continuous mode */ /* - Set ADC group regular conversion data transfer: no transfer or */ /* transfer by DMA, and DMA requests mode */ /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD , ADC_REG_InitStruct->TriggerSource | ADC_REG_InitStruct->SequencerDiscont | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer | ADC_REG_InitStruct->Overrun ); } else { MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMAEN | ADC_CFGR_DMACFG | ADC_CFGR_OVRMOD , ADC_REG_InitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer | ADC_REG_InitStruct->Overrun ); } /* Set ADC group regular sequencer length and scan direction */ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); } else { /* Initialization error: ADC instance is not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { /* Set ADC_REG_InitStruct fields to default values */ /* Set fields of ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; } /** * @brief Initialize some features of ADC group injected. * @note These parameters have an impact on ADC scope: ADC group injected. * Refer to corresponding unitary functions into * @ref ADC_LL_EF_Configuration_ADC_Group_Regular * (functions with prefix "INJ"). * @note The setting of these parameters by function @ref LL_ADC_Init() * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency * and compatibility over all STM32 families. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) * Each feature can be updated afterwards with a unitary function * and potentially with ADC in a different state than disabled, * refer to description of each function for setting * conditioned to ADC state. * @note After using this function, other features must be configured * using LL unitary functions. * The minimum configuration remaining to be done is: * - Set ADC group injected sequencer: * map channel on the selected sequencer rank. * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); * @note Caution if feature ADC group injected contexts queue is enabled * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): * using successively several times this function will appear as * having no effect. * To set several features of ADC group injected, use * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ /* - Set ADC group injected trigger source */ /* - Set ADC group injected sequencer length */ /* - Set ADC group injected sequencer discontinuous mode */ /* - Set ADC group injected conversion trigger: independent or */ /* from ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO , ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO , LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto ); } MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL , ADC_INJ_InitStruct->TriggerSource | ADC_INJ_InitStruct->SequencerLength ); } else { /* Initialization error: ADC instance is not disabled. */ status = ERROR; } return status; } /** * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * whose fields will be set to default values. * @retval None */ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) { /* Set ADC_INJ_InitStruct fields to default values */ /* Set fields of ADC group injected */ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; } /** * @} */ /** * @} */ /** * @} */ #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */ /** * @} */ #endif /* USE_FULL_LL_DRIVER */ ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/STM32G431KBUX_FLASH.ld ================================================ /* ****************************************************************************** ** ** @file : LinkerScript.ld ** ** @author : Auto-generated by STM32CubeIDE ** ** @brief : Linker script for STM32G431KBUx Device from STM32G4 series ** 128Kbytes FLASH ** 32Kbytes RAM ** ** Set heap size, stack size and stack location according ** to application requirements. ** ** Set memory bank area and size if external memory is used ** ** Target : STMicroelectronics STM32 ** ** Distribution: The file is distributed as is, without any warranty ** of any kind. ** ****************************************************************************** ** @attention ** ** Copyright (c) 2022 STMicroelectronics. ** All rights reserved. ** ** This software is licensed under terms that can be found in the LICENSE file ** in the root directory of this software component. ** If no LICENSE file comes with this software, it is provided AS-IS. ** ****************************************************************************** */ /* Entry Point */ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ _Min_Heap_Size = 0x0; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K } /* Sections */ SECTIONS { /* The startup code into "FLASH" Rom type memory */ .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); } >FLASH /* The program code and other data into "FLASH" Rom type memory */ .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ *(.glue_7) /* glue arm to thumb code */ *(.glue_7t) /* glue thumb to arm code */ *(.eh_frame) KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ } >FLASH /* Constant data into "FLASH" Rom type memory */ .rodata : { . = ALIGN(4); *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); } >FLASH .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); } >FLASH .ARM : { . = ALIGN(4); __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; . = ALIGN(4); } >FLASH .preinit_array : { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); } >FLASH .init_array : { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); } >FLASH .fini_array : { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); . = ALIGN(4); } >FLASH /* Used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections into "RAM" Ram type memory */ .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.data) /* .data sections */ *(.data*) /* .data* sections */ *(.RamFunc) /* .RamFunc sections */ *(.RamFunc*) /* .RamFunc* sections */ . = ALIGN(4); _edata = .; /* define a global symbol at data end */ } >RAM AT> FLASH /* Uninitialized data section into "RAM" Ram type memory */ . = ALIGN(4); .bss : { /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) *(.bss*) *(COMMON) . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; } >RAM /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ ._user_heap_stack : { . = ALIGN(8); PROVIDE ( end = . ); PROVIDE ( _end = . ); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); } >RAM /* Remove information from the compiler libraries */ /DISCARD/ : { libc.a ( * ) libm.a ( * ) libgcc.a ( * ) } .ARM.attributes 0 : { *(.ARM.attributes) } } ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/chorus_G431.ioc ================================================ #MicroXplorer Configuration settings - do not modify ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3 ADC1.ContinuousConvMode=DISABLE ADC1.DMAContinuousRequests=ENABLE ADC1.ExternalTrigConv=ADC_EXTERNALTRIG_T3_TRGO ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode,DMAContinuousRequests,ExternalTrigConv,NbrOfConversion ADC1.NbrOfConversion=1 ADC1.NbrOfConversionFlag=1 ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_24CYCLES_5 ADC1.master=1 ADC2.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_1 ADC2.ContinuousConvMode=DISABLE ADC2.DMAContinuousRequests=ENABLE ADC2.ExternalTrigConv=ADC_EXTERNALTRIG_T2_TRGO ADC2.IPParameters=Rank-1\#ChannelRegularConversion,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,OffsetNumber-1\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode,ExternalTrigConv,DMAContinuousRequests ADC2.NbrOfConversionFlag=1 ADC2.OffsetNumber-1\#ChannelRegularConversion=ADC_OFFSET_NONE ADC2.Rank-1\#ChannelRegularConversion=1 ADC2.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5 CAD.formats= CAD.pinconfig= CAD.provider= DAC1.DAC_Channel-DAC_OUT2=DAC_CHANNEL_2 DAC1.DAC_SampleAndHold-DAC_OUT1=DAC_SAMPLEANDHOLD_DISABLE DAC1.DAC_SampleAndHold-DAC_OUT2=DAC_SAMPLEANDHOLD_DISABLE DAC1.IPParameters=DAC_Channel-DAC_OUT2,DAC_SampleAndHold-DAC_OUT1,DAC_SampleAndHold-DAC_OUT2 Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY Dma.ADC1.0.EventEnable=DISABLE Dma.ADC1.0.Instance=DMA1_Channel2 Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.ADC1.0.MemInc=DMA_MINC_DISABLE Dma.ADC1.0.Mode=DMA_CIRCULAR Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE Dma.ADC1.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING Dma.ADC1.0.Priority=DMA_PRIORITY_LOW Dma.ADC1.0.RequestNumber=1 Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber Dma.ADC1.0.SignalID=NONE Dma.ADC1.0.SyncEnable=DISABLE Dma.ADC1.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.ADC1.0.SyncRequestNumber=1 Dma.ADC1.0.SyncSignalID=NONE Dma.ADC2.1.Direction=DMA_PERIPH_TO_MEMORY Dma.ADC2.1.EventEnable=DISABLE Dma.ADC2.1.Instance=DMA1_Channel1 Dma.ADC2.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.ADC2.1.MemInc=DMA_MINC_DISABLE Dma.ADC2.1.Mode=DMA_CIRCULAR Dma.ADC2.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD Dma.ADC2.1.PeriphInc=DMA_PINC_DISABLE Dma.ADC2.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING Dma.ADC2.1.Priority=DMA_PRIORITY_LOW Dma.ADC2.1.RequestNumber=1 Dma.ADC2.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber Dma.ADC2.1.SignalID=NONE Dma.ADC2.1.SyncEnable=DISABLE Dma.ADC2.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.ADC2.1.SyncRequestNumber=1 Dma.ADC2.1.SyncSignalID=NONE Dma.Request0=ADC1 Dma.Request1=ADC2 Dma.RequestsNb=2 File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.CPN=STM32G431KBU3 Mcu.Family=STM32G4 Mcu.IP0=ADC1 Mcu.IP1=ADC2 Mcu.IP2=DAC1 Mcu.IP3=DMA Mcu.IP4=NVIC Mcu.IP5=RCC Mcu.IP6=SYS Mcu.IP7=TIM1 Mcu.IP8=TIM2 Mcu.IP9=TIM3 Mcu.IPNb=10 Mcu.Name=STM32G431K(6-8-B)Ux Mcu.Package=UFQFPN32 Mcu.Pin0=PA0 Mcu.Pin1=PA2 Mcu.Pin10=VP_TIM1_VS_ClockSourceINT Mcu.Pin11=VP_TIM2_VS_ClockSourceINT Mcu.Pin12=VP_TIM3_VS_ClockSourceINT Mcu.Pin2=PA4 Mcu.Pin3=PA5 Mcu.Pin4=PA6 Mcu.Pin5=PA7 Mcu.Pin6=PB0 Mcu.Pin7=PA8 Mcu.Pin8=VP_SYS_VS_Systick Mcu.Pin9=VP_SYS_VS_DBSignals Mcu.PinsNb=13 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32G431KBUx MxCube.Version=6.4.0 MxDb.Version=DB.6.0.40 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DMA1_Channel1_IRQn=true\:1\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Channel2_IRQn=true\:2\:0\:true\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.TIM3_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false PA0.Locked=true PA0.Mode=IN1-Single-Ended PA0.Signal=ADC2_IN1 PA2.Locked=true PA2.Mode=IN3-Single-Ended PA2.Signal=ADC1_IN3 PA4.Locked=true PA4.Signal=COMP_DAC11_group PA5.Locked=true PA5.Signal=COMP_DAC12_group PA6.GPIOParameters=GPIO_Label PA6.GPIO_Label=MUX_C PA6.Locked=true PA6.Signal=GPIO_Output PA7.GPIOParameters=GPIO_Label PA7.GPIO_Label=MUX_B PA7.Locked=true PA7.Signal=GPIO_Output PA8.Locked=true PA8.Signal=S_TIM1_CH1 PB0.GPIOParameters=GPIO_Label PB0.GPIO_Label=MUX_A PB0.Locked=true PB0.Signal=GPIO_Output PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=true ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32G431KBUx ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x00 ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Core/Src ProjectManager.NoMain=false ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=chorus_G431.ioc ProjectManager.ProjectName=chorus_G431 ProjectManager.ProjectStructure= ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_DAC1_Init-DAC1-false-HAL-true,7-MX_TIM2_Init-TIM2-false-HAL-true,8-MX_TIM1_Init-TIM1-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true RCC.ADC12Freq_Value=48000000 RCC.AHBFreq_Value=48000000 RCC.APB1Freq_Value=48000000 RCC.APB1TimFreq_Value=48000000 RCC.APB2Freq_Value=48000000 RCC.APB2TimFreq_Value=48000000 RCC.CRSFreq_Value=48000000 RCC.CortexFreq_Value=48000000 RCC.EXTERNAL_CLOCK_VALUE=12288000 RCC.FCLKCortexFreq_Value=48000000 RCC.FDCANFreq_Value=48000000 RCC.FamilyName=M RCC.HCLKFreq_Value=48000000 RCC.HSE_VALUE=8000000 RCC.HSI48_VALUE=48000000 RCC.HSI_VALUE=16000000 RCC.I2C1Freq_Value=48000000 RCC.I2C2Freq_Value=48000000 RCC.I2C3Freq_Value=48000000 RCC.I2SFreq_Value=48000000 RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLR,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USART2Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value RCC.LPTIM1Freq_Value=48000000 RCC.LPUART1Freq_Value=48000000 RCC.LSCOPinFreq_Value=32000 RCC.LSE_VALUE=32768 RCC.LSI_VALUE=32000 RCC.MCO1PinFreq_Value=16000000 RCC.PLLN=12 RCC.PLLPoutputFreq_Value=96000000 RCC.PLLQoutputFreq_Value=96000000 RCC.PLLR=RCC_PLLR_DIV4 RCC.PLLRCLKFreq_Value=48000000 RCC.PWRFreq_Value=48000000 RCC.RNGFreq_Value=96000000 RCC.SAI1Freq_Value=48000000 RCC.SYSCLKFreq_VALUE=48000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.USART1Freq_Value=48000000 RCC.USART2Freq_Value=48000000 RCC.USBFreq_Value=96000000 RCC.VCOInputFreq_Value=16000000 RCC.VCOOutputFreq_Value=192000000 SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1 SH.COMP_DAC11_group.ConfNb=1 SH.COMP_DAC12_group.0=DAC1_OUT2,DAC_OUT2 SH.COMP_DAC12_group.ConfNb=1 SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1 SH.S_TIM1_CH1.ConfNb=1 TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM1.IPParameters=Channel-PWM Generation1 CH1,Prescaler,PeriodNoDither,PulseNoDither_1 TIM1.PeriodNoDither=4096 TIM1.Prescaler=200 TIM1.PulseNoDither_1=512 TIM2.IPParameters=PeriodNoDither,TIM_MasterOutputTrigger TIM2.PeriodNoDither=960 TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM3.IPParameters=PeriodNoDither,TIM_MasterOutputTrigger TIM3.PeriodNoDither=6400 TIM3.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM1_VS_ClockSourceINT.Mode=Internal VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT VP_TIM2_VS_ClockSourceINT.Mode=Internal VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT VP_TIM3_VS_ClockSourceINT.Mode=Internal VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT board=custom isbadioc=false ================================================ FILE: Production Modules/CHORUS/firmware/chorus_G431/chorus_G431.launch ================================================ ================================================ FILE: Production Modules/CHORUS/jlcpcb/chorus_REV1_JLCBOM.csv ================================================ Comment,Designator,Footprint,LCSC Part #（optional） "100nF, 0603, 50V","C1, C2, C3, C4, C6, C7, C9, C11, C12, C13, C15, C16, C18, C19",0603 CAP, "10uF, 1206","C5, C8, C21",CAP_1206, "510pF, 0603",C10,0603 CAP, "100pF, 0603",C14,0603 CAP, "1nF, 0603",C17,0603 CAP, CJ431,D1,SOT23, 1N4148WS,"D2, D6, D7",SOD-323, VAOL-3MAE2,"D3, D5",LEDT1, C37208,J3,HDR-1x6T/2.54/15x2, WQP-WQP518MA,"J4, J5, J6",Thonkiconn Jack, "10kΩ,0603,1%","R1, R2, R3, R8, R25",0603 RES, "100kΩ,0603,1%","R4, R5, R10, R11, R13, R14, R16",0603 RES, "2kΩ,0603,1%","R6, R19",0603 RES, "1kΩ,0603,1%","R7, R9, R12",0603 RES, "33kΩ,0603,1%","R15, R24",0603 RES, "200kΩ,0603,1%",R17,0603 RES, "52kΩ,0603,1%","R20, R26",0603 RES, TL072D,"U1, U3, U6",SOIC-8/150mil, EUROPWR-10p,U2,10P_euro_power, STM32G431KBU3,U4,QFN50P500X500X60-33N, CD4051,U5,SOIC-16/150mil, MCP6002,U10,SOIC-8/150mil, AMS1117-3.3,U15,SOT223-4, P0915N-EC15BR100K,VR1,P09x5N, RV9012NO-PA25B7.0 Tall Trimmer 10k,"VR2, VR3, VR4, VR5, VR6",EVUF, ================================================ FILE: Production Modules/CHORUS/jlcpcb/chorus_REV1_JLCXY.csv ================================================ Designator,Mid X,Mid Y,Layer,Rotation C1,26.405,105.72,Bottom,180.0 C2,23.865,47.3,Bottom,90.0 C3,33.072,53.65,Bottom,270.0 C4,25.453,16.82,Bottom,180.0 C5,26.087,27.933,Bottom,270.0 C6,34.977,99.37,Bottom,90.0 C7,15.927,37.775,Bottom,0.0 C8,29.58,24.44,Bottom,270.0 C9,13.705,63.175,Bottom,180.0 C10,24.074,96.115,Bottom,90.0 C11,31.167,37.775,Bottom,0.0 C12,27.04,68.255,Bottom,90.0 C13,29.262,75.558,Bottom,0.0 C14,22.913,56.825,Bottom,270.0 C15,30.85,68.255,Bottom,0.0 C16,25.611,92.226,Bottom,90.0 C17,25.344,84.369,Bottom,270.0 C18,20.69,81.59,Bottom,180.0 C19,21.325,59.047,Bottom,90.0 C21,18.785,31.742,Bottom,180.0 D1,31.485,86.352,Bottom,180.0 D2,32.12,93.655,Bottom,0.0 D3,16.88,49.84,Top,0.0 D5,32.12,95.56,Top,180.0 D6,29.58,29.202,Bottom,0.0 D7,29.58,19.995,Bottom,90.0 J3,36.882,56.508,Bottom,270.0 J4,32.12,102.621,Top,180.0 J5,16.88,87.381,Top,180.0 J6,16.88,102.621,Top,180.0 R1,34.025,86.353,Bottom,270.0 R2,31.189,88.893,Bottom,0.0 R3,29.263,53.65,Bottom,180.0 R4,24.183,81.59,Bottom,180.0 R5,29.263,78.732,Bottom,180.0 R6,34.977,96.195,Bottom,90.0 R7,35.295,107.942,Bottom,0.0 R8,24.5,53.333,Bottom,270.0 R9,20.69,49.84,Bottom,180.0 R10,18.785,75.875,Bottom,270.0 R11,17.833,78.732,Bottom,180.0 R12,15.928,75.24,Bottom,180.0 R13,20.69,84.765,Bottom,180.0 R14,27.992,85.003,Bottom,0.0 R15,22.486,96.115,Bottom,90.0 R16,25.77,96.037,Bottom,270.0 R17,22.595,99.37,Bottom,90.0 R19,27.993,83.495,Bottom,180.0 R20,24.5,56.825,Bottom,270.0 R24,23.756,84.369,Bottom,270.0 R25,27.993,57.619,Bottom,180.0 R26,28.945,60.635,Bottom,90.0 U1,25.135,62.54,Bottom,270.0 U2,34.342,23.805,Bottom,180.0 U3,32.12,103.815,Bottom,0.0 U4,29.263,49.84,Bottom,180.0 U5,15.928,57.143,Bottom,180.0 U6,23.548,78.097,Bottom,180.0 U10,21.929,90.163,Bottom,90.0 U15,20.055,26.028,Bottom,270.0 VR1,24.5,13.465,Top,180.0 VR2,16.88,41.028,Top,0.0 VR3,32.12,41.028,Top,0.0 VR4,16.88,71.508,Top,0.0 VR5,32.12,71.508,Top,0.0 VR6,32.12,86.747,Top,0.0 ================================================ FILE: Production Modules/EG/EG_REV1_PANEL.ai ================================================ %PDF-1.6 % 1 0 obj <>/OCGs[33 0 R 34 0 R 35 0 R 36 0 R 37 0 R 32 0 R]>>/Pages 3 0 R/Type/Catalog>> endobj 2 0 obj <>stream application/pdf EG_REV1_PANEL 2024-11-29T11:38:57-06:00 2024-11-29T11:38:57-06:00 2024-11-29T11:38:57-06:00 Adobe Illustrator 28.0 (Macintosh) 60 256 JPEG /9j/4AAQSkZJRgABAgEASABIAAD/7QAsUGhvdG9zaG9wIDMuMAA4QklNA+0AAAAAABAASAAAAAEA AQBIAAAAAQAB/+4ADkFkb2JlAGTAAAAAAf/bAIQABgQEBAUEBgUFBgkGBQYJCwgGBggLDAoKCwoK DBAMDAwMDAwQDA4PEA8ODBMTFBQTExwbGxscHx8fHx8fHx8fHwEHBwcNDA0YEBAYGhURFRofHx8f Hx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8fHx8f/8AAEQgBAAA8AwER AAIRAQMRAf/EAaIAAAAHAQEBAQEAAAAAAAAAAAQFAwIGAQAHCAkKCwEAAgIDAQEBAQEAAAAAAAAA AQACAwQFBgcICQoLEAACAQMDAgQCBgcDBAIGAnMBAgMRBAAFIRIxQVEGE2EicYEUMpGhBxWxQiPB UtHhMxZi8CRygvElQzRTkqKyY3PCNUQnk6OzNhdUZHTD0uIIJoMJChgZhJRFRqS0VtNVKBry4/PE 1OT0ZXWFlaW1xdXl9WZ2hpamtsbW5vY3R1dnd4eXp7fH1+f3OEhYaHiImKi4yNjo+Ck5SVlpeYmZ qbnJ2en5KjpKWmp6ipqqusra6voRAAICAQIDBQUEBQYECAMDbQEAAhEDBCESMUEFURNhIgZxgZEy obHwFMHR4SNCFVJicvEzJDRDghaSUyWiY7LCB3PSNeJEgxdUkwgJChgZJjZFGidkdFU38qOzwygp 0+PzhJSktMTU5PRldYWVpbXF1eX1RlZmdoaWprbG1ub2R1dnd4eXp7fH1+f3OEhYaHiImKi4yNjo +DlJWWl5iZmpucnZ6fkqOkpaanqKmqq6ytrq+v/aAAwDAQACEQMRAD8A8+YVfSf5Z/8AOMfk7zH5 J0zXtW1a+a61KL1+Fi8EcUasSBGfUimLMtKMajfamBWHfn1+Suhfl7b6VeaNqFxcQX7yQyW14Y2l DRgNzRo0iBXehHHbbffFXmei6Kl2kt/fym10e1IFzcgVd3O6wwqftyv2HQDc7ZGUq2HNlGPyVX1n QOben5fgEdTwD3F0zU7ciJFBPjQDBwnvWx3NfprRP+pftv8Akfd/9VseE9/3LY7nfprRP+pftv8A kfd/9VseE9/3LY7lX6lp3+KPR+rD6lx9b6rzfjT0PV4cq86V9642eFaFoY2GkQWVlNdzXHq3kTTc YkQqoE0kNKswP+6q4bJJWgmuk+cb7R7X6ppHmLXNOteRf6vaTtBHyPU8I5lFTjujZDaprltrN0lz req6tqcqAKJbpxNIErXiryyORj6k7JfrWtPqLxRxxC1061BSxsUNUiQ9ST+279Xc7k+1AGMa96JS tLcmh2KuxVkn/TVf9G//AGJ5V/D+O9n1S/V/+Ofon/ME/wD1G3OSjzPv/QEHkErybF2KuxV2KuxV 2Ksk/wCmq/6N/wDsTyr+H8d7Pql+r/8AHP0T/mCf/qNuclHmff8AoCDyCXLE7CoAA7EkKPxpkrQA 0yMpowp4fL2xQQtwq7FVQQyEA0AruASAT8gTgtPCVhBBIIoR1BxQyP8A6ar/AKN/+xPK/wCH8d7P ql+r/wDHP0T/AJgn/wCo25yUeZ9/6Ag8gl9x/fOOykqo9hsMkOSy5uXeBq/skcT7mu3049V6KeFi qQgGUVFepAPcgVA+k4CmPNYSSSSak9Tihe+8UZP2tx9ApT9ZxDI8mQf9NV/0b/8AYnlf8P4709Uv 1f8A45+if8wT/wDUbc5KPM+/9AQeQS8SIQBIvKmwYGh2+/JUi+9p35AAAKo6AY0pKzChsEg1GxHQ 4FX+pGd2T4vY0B+Y/pTGmVhazFjU7AbADoBiglkX/TVf9G//AGJ5X/D+O9l1S/V/+Ofon/ME/wD1 G3OSjzPv/QEHkGfXqflwut3IsI9L+qB0Fr9YkuTE1uZqSklHLep6dONabcqb0zGHicIu7+DaeG9q Y75sTygulRfoH6qYuUPpSFp/0gTxf1/WVv3QQPx47A0pT9rLcfFfq/Ywnw1sw/L2t2KohK8U4hSv +7CwBoanqeo2yJZhQbjyPGvGu1etMLAsj/6ar/o3/wCxPK/4fx3s+qX6v/xz9E/5gn/6jbnJR5n3 /oCDyCXiNQAXbjXotCTQ9DkrRTToVAIIZT0YdPxxtSFmFDYBJoNyegwKv9NBs0gDeG5A+ZH8K42y paylTQ/MEdCMWJDIv+mq/wCjf/sTyv8Ah/Hez6pfq/8Axz9E/wCYJ/8AqNuclHmff+gIPIJfcf3z nsTVfken4ZIcllzcu0D16FhxHuK7/RX8ceq9FPCxVICBKOx3APgSKA/fgKY81hBBodiOoxQvfaKM H7W5/wBiaU/jiGR5Mg/6ar/o3/7E8r/h/Henql+r/wDHP0T/AJgn/wCo25yUeZ9/6Ag8gqeWIorj VRBOiyw+hdOEcAgMltI6kV8GUHBk5JgUpZ2Y1Y17DwHyybEm1uFDsVVBNJSmxp3ZVJ+8jBSeIrCx Y1JqT1JxQyP/AKar/o3/AOxPK/4fx3s+qX6v/wAc/RP+YJ/+o25yUeZ9/wCgIPIK3lD/AI7Y/wCY a8/6hJcGTl8vvWHNJcsYuxVNvKmuSaF5k03V1aVUs7mKWZYWKO8SuDJHWo2dKqQdjXfK8kOKJDKE qILLo/zUWTRYdNvYri5eJWdrl5XkZpnup5ixV5DH/dzqvIJzqKFitBlP5epWPxsGzxdqS7z15w0j X7K0S0S6WaKV5fSn4+jbxuqgW1vR3/dpx2oqV/lruZYcRid2M5goD/pqv+jf/sTyf8P470dUHfxL Nb+X4mkWFZLQqZXrxUG+uByaldhhHX8dAg9FsOpLptxE1rGgurdJYZJx8SyCUMhJWQMPsPTpiRab AUhHZ3Vn8Ho2T2cLM7u0pe5cyVVRQOvPi22yrRd9+p3BRQIS7JsXYqvWJ2FQNu24BPyHfBaaKzCh kn/TVf8ARv8A9ieVfw/jvZ9VJnZR5eVWhT1bN4jJcKrRIJLy5Qu3IEfDyrXHv9/6AvclF3EyzO6n nEzHjKteJ3PSoGTBRIb2i9KL2rXFwXt45YoWKQ3aeoJQxEZVEKOvP4+S8qUoTWoGCW6RslmTYOxV VDxkIWLBoxQAd9yetduuRplYU2PJifE12wsWR/8ATVf9G/8A2J5X/D+O9n1S/V/+Ofon/ME//Ubc 5KPM+/8AQEHkERZaJ5r1TT4J7S3muLOBjb27KQKF3FVUVDEc5FqexIwGUQd0gS6IHURq0UNna3/q LFFGzWcUnRY5JGJ4jsGfkckK6MTaBySF0cbyOEQcmPQYqqNaXCqWZCFXqTTwB/jiq2WCaKnqIVrU Cvt1xVkH/TVf9G//AGJ5V/D+O9n1S/V/+Ofon/ME/wD1G3OSjzPv/QEHkFaDzPNFo0Wmm0geW2Zz Z359UTw+q6O3Di4jPxR7FlNKn6Ace92vFtSj5k8wXmv6xNql2kccswRfShXjGixoEVVXsKLhhARF BZSs2leTYqkEzQyrIoqy1pX3FMVV5NRkkiMbqDy6kEjcKF6A0/ZwKhnkkf7bFqeJr1wqyL/pqv8A o3/7E8q/h/Hez6pfq/8Axz9E/wCYJ/8AqNuclHmff+gIPIJXk2LsVdirsVdirsVZJ/01X/Rv/wBi eVfw/jvZ9Uv1f/jn6J/zBP8A9Rtzko8z7/0BB5BK8mxdirsVdirsVdirJP8Apqv+jf8A7E8q/h/H ez6pfq//ABz9E/5gn/6jbnJR5n3/AKAg8gleTYuxVH6Xoeq6ql49hbmddPt3vLwgqOEEdOb/ABEV pXoN8hKYjV9UiJPJAZNDsVdirJP+mq/6N/8AsTyr+H8d7Pql+r/8c/RP+YJ/+o25yUeZ9/6Ag8gl scbSSLGm7uQqgkDcmg3O2SYp47a/5N1u/sSYodQEMlndCkVwvpzoOQVvjWpU9RuOnjlfpyAHoz3i UljSehMYejDixUHceBplhIYgFGafrepaba6hZ2zKkOpRC3vFZFYlFcOACwJX4h2yJgCQe5QSNnXm hajZ6TYarOqCy1Myi0dXRmPoMEfkgJZaE9xiJgkjuUxIFpfk0Mk/6ar/AKN/+xPKv4fx3s+qX6v/ AMc/RP8AmCf/AKjbnJR5n3/oCDyClomj3Gr3wsoJYIZCjyc7mRYo6RqWI5N3NNhhlLhFoiLQcShn AP2RViPEKKn9WEqBu07s5qx+XgB7YqTa8ktCS25RgoPsQdvwwdU9EXZaNPd6ZqGoJNAkWnCIyxSS Kkr+sxUekh3ehHxU6YDKiB3oA2tL8mhkn/TVf9G//YnlX8P472fVL9X/AOOfon/ME/8A1G3OSjzP v/QEHkEtjTnIqcgvIgcmNFFTSpPhkmKO1nTf0Rq89it3b331ZgBd2j+pA+wb4HoK0rQ++RjLiF1T Iiig+ETbhwn+SwP4UByS0HMyheCbitWJ7kdMUEo280gW2k6fqIvbac3/AKtbOKTlcQek3H9+lBw5 9V33GRErJFclI2tLsmhkn/TVf9G//YnlX8P472fVL9X/AOOfon/ME/8A1G3OSjzPv/QEHkErybFG aZLpkcsp1CF5ozEwhEZoRKacWO69q/I70NKGMr6JFdUHkkJjp0mjx2N/+kLWaa5liC6bNG/BI5gw LM4I+Ice3+2ISuxSRXVLsmh2Ksk/6ar/AKN/+xPKv4fx3s+qX6v/AMc/RP8AmCf/AKjbnJR5n3/o CDyCV5Ni9E8s/mVpeiaXo9jDa3Ub6bdRXk1zDIqtMxkY3MTKOPwSRFV3bfgtRmLkwGRJ726OUABr QPzXu7CKxk1KW91S5sPrEkaTTlo3mndAruZPUrwiMoHw9W+eM9MDdULWOWubcf5i6Lai2jtIL1rC z9RINHnaJrIoTccXkQfEXYTqr8Svfc1AD4BPOr7+vRfEDEPM+qW2q65dajbiVI7oiT0piGMZIFY1 YHdE+yn+TTL8caFNcjZtKsmxZJ/01X/Rv/2J5V/D+O9n1S/V/wDjn6J/zBP/ANRtzko8z7/0BB5B K8mxdirsVdirsVdirJP+mq/6N/8AsTyr+H8d7Pql+r/8c/RP+YJ/+o25yUeZ9/6Ag8gleTYuxV2K uxV2KuxVkn/TVf8ARv8A9ieVfw/jvZ9Uv1f/AI5+if8AME//AFG3OSjzPv8A0BB5BK8mxTDRtJXU 5p4mvbaxEFvJcCS7k9NXMYr6SGhrI/7I75CUq6WmIt2knQgt7+lluSxtpBp31XhQXW3pmbn/ALr6 8uO+MuLalFdXadpS3tpf3Bvba1NjEJVhuH4ST1YLwhWh5N3pjKVEbc1AtL8mh2Ksk/6ar/o3/wCx PKv4fx3s+qX6v/xz9E/5gn/6jbnJR5n3/oCDyCXRmMSKZFLRgjmoNCRXcA0NMkxRmtS6RPqs76Nb y22nOw+rW87iWRRxAILACtWrT+ORjYG/NJq9kJwhGzOa9+Kgj76jJWU0GnQABlPJDtXoa+BGNoIR t5Noj6TYRWltNHqkZl/SNw8gaKUMwMXppT4eK7HIgGzfJTVJfk0Mk/6ar/o3/wCxPKv4fx3s+qX6 v/xz9E/5gn/6jbnJR5n3/oCDyCnol3pNrfibVbA6jacJFNssrQHmykI3NAT8LUNMZgkbGkRI6oOA gSr2rsD4EigP0HJFY81hBBodiOoxQvG0De7rT6Aa/rx6suiMsrvSYtM1CC6sDc39wIv0feiVkFsU YmSsY+GT1F2+LpkSDYo7IBFJfk0Mk/6ar/o3/wCxPKv4fx3s+qX6v/xz9E/5gn/6jbnJR5n3/oCD yCWxsqyKzKHVSCyGoBAPTbxyTFMdSkXV9VurnS9M+qQMPVFhbc5ViRFAY1NWp3JORj6RuWR3OwQA lNPiVXp0JG/3ilfpyVI4lSO1vbmOaaKCSWK2QPcPGhKRIWChn4iigs1N++CwF3KIvNQsZ9KsLSHT 47e6tfV+s3ys5e49RqpzUnivAbCmARNk2pOyX5NDJP8Apqv+jf8A7E8q/h/Hez6pfq//ABz9E/5g n/6jbnJR5n3/AKAg8gleTYsq8q+WtRvrCa+sdSSzuJDPbx27CTlMtvB9alHJFZRRFqOXcZTkyAGi PxybIRJRup/lk2nXF1FcavbqlpMlpJL6U5BuZTKEjCorsQfQclqZGOe625pOKuqJ0r8v/M0OmwmP VY9Pt9bsvrFzEzOitbRMkkoloKN6cEqz8e61puCMjLNG+V0fx+pIxmufNgLBQxCmqg7GlKj5ZktK 3CrJP+mq/wCjf/sTyr+H8d7Pqho9R8vzWFlDqFrdtPZxNCHt5o0RlaaSYHi8Uhr+9p1w8MrNIsdU 40nyiNYtfrekeV/MOo2vIp9YtF9ePkOo5x2rCox9XkvpVrm6m8rQyaRd2PmDRUuwZJLOeVLZpAw4 E8XtlYggUPjkTjJNmvkyEgO9a/5gq88k5u9Z9aVeMji7gBbcsCaW/UFjQ9RXI+D7vknxPehn83ae 6Mjy6uyOrIVN3CRxeIwMoHobAxHhQdsPhny+SOP3pX63k3/lk1H/AKSYP+qGTqXkx9KOk0jSI3iS TRNaR56+grOgL03PAG2+Lr2yPEe8fj4podxQP6Ut/wDEn1v6rN6FfR+q8h63H0vR48uNOf8Asevb JcPppF7pLljF9J/ln/zk55O8ueSdM0HVtJvlutNi9DnYpBJFIqkkSH1JYSrNWrCh33rgVh359fnV oX5hW+lWejafcW8Fg8k0lzeCNZS0gC8EWN5QF2qTy3222xV47hV2KuxV6ZffmbolzeySiG6SK5tm tpmjSKKWP95BICro9ZA31fi1Svwk75iDAQG85Qxr/FGn/wCPv8R+jP8AU/rX1n0fVb16daety5cq /tcq5b4Z4OHya+IcVv8A/9k= uuid:8d458433-0576-da4b-9ac2-7b69f7a15c2e xmp.did:64bac6fa-09b9-43be-ade2-a5d2a17c8cbd uuid:5D20892493BFDB11914A8590D31508C8 proof:pdf xmp.iid:ddd81e53-ea57-4e55-bd68-e667edc0f4a3 xmp.did:ddd81e53-ea57-4e55-bd68-e667edc0f4a3 uuid:5D20892493BFDB11914A8590D31508C8 proof:pdf saved xmp.iid:a055e960-0e65-4094-bb07-2d0457c53e5b 2021-09-12T22:02:29-05:00 Adobe Illustrator 24.2 (Macintosh) / saved xmp.iid:64bac6fa-09b9-43be-ade2-a5d2a17c8cbd 2022-09-21T13:24:47-05:00 Adobe Illustrator 26.0 (Macintosh) / Print AIRobin Document Adobe PDF library 17.00 1 False False 29.999913 128.500000 Millimeters Cyan Magenta Yellow Black Default Swatch Group 0 White CMYK PROCESS 0.000000 0.000000 0.000000 0.000000 Black CMYK PROCESS 0.000000 0.000000 0.000000 100.000000 CMYK Red CMYK PROCESS 0.000000 100.000000 100.000000 0.000000 CMYK Yellow CMYK PROCESS 0.000000 0.000000 100.000000 0.000000 CMYK Green CMYK PROCESS 100.000000 0.000000 100.000000 0.000000 CMYK Cyan CMYK PROCESS 100.000000 0.000000 0.000000 0.000000 CMYK Blue CMYK PROCESS 100.000000 100.000000 0.000000 0.000000 CMYK Magenta CMYK PROCESS 0.000000 100.000000 0.000000 0.000000 C=15 M=100 Y=90 K=10 CMYK PROCESS 15.000000 100.000000 90.000000 10.000000 C=0 M=90 Y=85 K=0 CMYK PROCESS 0.000000 90.000000 85.000000 0.000000 C=0 M=80 Y=95 K=0 CMYK PROCESS 0.000000 80.000000 95.000000 0.000000 C=0 M=50 Y=100 K=0 CMYK PROCESS 0.000000 50.000000 100.000000 0.000000 C=0 M=35 Y=85 K=0 CMYK PROCESS 0.000000 35.000000 85.000000 0.000000 C=5 M=0 Y=90 K=0 CMYK PROCESS 5.000000 0.000000 90.000000 0.000000 C=20 M=0 Y=100 K=0 CMYK PROCESS 20.000000 0.000000 100.000000 0.000000 C=50 M=0 Y=100 K=0 CMYK PROCESS 50.000000 0.000000 100.000000 0.000000 C=75 M=0 Y=100 K=0 CMYK PROCESS 75.000000 0.000000 100.000000 0.000000 C=85 M=10 Y=100 K=10 CMYK PROCESS 85.000000 10.000000 100.000000 10.000000 C=90 M=30 Y=95 K=30 CMYK PROCESS 90.000000 30.000000 95.000000 30.000000 C=75 M=0 Y=75 K=0 CMYK PROCESS 75.000000 0.000000 75.000000 0.000000 C=80 M=10 Y=45 K=0 CMYK PROCESS 80.000000 10.000000 45.000000 0.000000 C=70 M=15 Y=0 K=0 CMYK PROCESS 70.000000 15.000000 0.000000 0.000000 C=85 M=50 Y=0 K=0 CMYK PROCESS 85.000000 50.000000 0.000000 0.000000 C=100 M=95 Y=5 K=0 CMYK PROCESS 100.000000 95.000000 5.000000 0.000000 C=100 M=100 Y=25 K=25 CMYK PROCESS 100.000000 100.000000 25.000000 25.000000 C=75 M=100 Y=0 K=0 CMYK PROCESS 75.000000 100.000000 0.000000 0.000000 C=50 M=100 Y=0 K=0 CMYK PROCESS 50.000000 100.000000 0.000000 0.000000 C=35 M=100 Y=35 K=10 CMYK PROCESS 35.000000 100.000000 35.000000 10.000000 C=10 M=100 Y=50 K=0 CMYK PROCESS 10.000000 100.000000 50.000000 0.000000 C=0 M=95 Y=20 K=0 CMYK PROCESS 0.000000 95.000000 20.000000 0.000000 C=25 M=25 Y=40 K=0 CMYK PROCESS 25.000000 25.000000 40.000000 0.000000 C=40 M=45 Y=50 K=5 CMYK PROCESS 40.000000 45.000000 50.000000 5.000000 C=50 M=50 Y=60 K=25 CMYK PROCESS 50.000000 50.000000 60.000000 25.000000 C=55 M=60 Y=65 K=40 CMYK PROCESS 55.000000 60.000000 65.000000 40.000000 C=25 M=40 Y=65 K=0 CMYK PROCESS 25.000000 40.000000 65.000000 0.000000 C=30 M=50 Y=75 K=10 CMYK PROCESS 30.000000 50.000000 75.000000 10.000000 C=35 M=60 Y=80 K=25 CMYK PROCESS 35.000000 60.000000 80.000000 25.000000 C=40 M=65 Y=90 K=35 CMYK PROCESS 40.000000 65.000000 90.000000 35.000000 C=40 M=70 Y=100 K=50 CMYK PROCESS 40.000000 70.000000 100.000000 50.000000 C=50 M=70 Y=80 K=70 CMYK PROCESS 50.000000 70.000000 80.000000 70.000000 Grays 1 C=0 M=0 Y=0 K=100 CMYK PROCESS 0.000000 0.000000 0.000000 100.000000 C=0 M=0 Y=0 K=90 CMYK PROCESS 0.000000 0.000000 0.000000 89.999400 C=0 M=0 Y=0 K=80 CMYK PROCESS 0.000000 0.000000 0.000000 79.998800 C=0 M=0 Y=0 K=70 CMYK PROCESS 0.000000 0.000000 0.000000 69.999700 C=0 M=0 Y=0 K=60 CMYK PROCESS 0.000000 0.000000 0.000000 59.999100 C=0 M=0 Y=0 K=50 CMYK PROCESS 0.000000 0.000000 0.000000 50.000000 C=0 M=0 Y=0 K=40 CMYK PROCESS 0.000000 0.000000 0.000000 39.999400 C=0 M=0 Y=0 K=30 CMYK PROCESS 0.000000 0.000000 0.000000 29.998800 C=0 M=0 Y=0 K=20 CMYK PROCESS 0.000000 0.000000 0.000000 19.999700 C=0 M=0 Y=0 K=10 CMYK PROCESS 0.000000 0.000000 0.000000 9.999100 C=0 M=0 Y=0 K=5 CMYK PROCESS 0.000000 0.000000 0.000000 4.998800 Brights 1 C=0 M=100 Y=100 K=0 CMYK PROCESS 0.000000 100.000000 100.000000 0.000000 C=0 M=75 Y=100 K=0 CMYK PROCESS 0.000000 75.000000 100.000000 0.000000 C=0 M=10 Y=95 K=0 CMYK PROCESS 0.000000 10.000000 95.000000 0.000000 C=85 M=10 Y=100 K=0 CMYK PROCESS 85.000000 10.000000 100.000000 0.000000 C=100 M=90 Y=0 K=0 CMYK PROCESS 100.000000 90.000000 0.000000 0.000000 C=60 M=90 Y=0 K=0 CMYK PROCESS 60.000000 90.000000 0.003100 0.003100 endstream endobj 3 0 obj <> endobj 5 0 obj <>/ExtGState<>/ProcSet[/PDF/ImageC]/Properties<>/Shading<>/XObject<>>>/Thumb 47 0 R/TrimBox[0.0 0.0 85.0391 364.252]/Type/Page/PieceInfo<>>> endobj 39 0 obj <>stream HԗInf7),q PHw-RZ$.iz'QϿ\ϯ/ǗO_t7Vt,;˞K1qԃF6:sZe͘v[{LˮL/9w,AͳnmpVn1-;ýcu|ĞǛX7ap@i;(fowl%=ʇHc >\ ּZxکGn༭gl[lllllk#A"af` ҜXt!s_h5rLtL)ӛ U=mZKR"5lQIj{1cZXNTco8hQà9M&UCWgqt2V%J.W1U,NnbF5 ZWsvWNe.U#N)rB@A6cgS )Dd}*`~˃>kdKs,Kȋ%A %o%Ъv$P!IkdVԦs4#ywhee"h%])ZES3ѥ*0GƔN=5m4ُزfha^W7nɓ!Dd Yog& 3?H8rce1@^;̦Tu !ofNioe H[7iye{_ypN3n+n#nnn nnyŘdzS͗H&rLM"&yWϲIθIξUͲ[><:864e~z}Ͽ\ϯ/t#_򩚹«4|?Βp > q l*Tdd#`ktgeжf|[&\6|g2M=![|'2M=}O2?[̙[ɱ4x V?p`aYk]Vm[wl6O&_m %Ꜽ_d/I7Nm>`,u儹Qmvۗ1╓lM n@H ֓I&$ Hq7s1S1;eZiO :>zG9G:^R@M AH.:mԇD_w~#C,/Tq:jbÃqIu٣Uh#ӝC)ɚ99zxA|pOغ`)<vQBx?Ngs[t=.c=ԩڊgN:zw_al&Z8ƒqCq)l-8> ?i=Ѵ#~zh4ߝG-K/y=R!K'm)Fs^fs"4ZՒ& 8. S ke*NcNegӁ-N7S_{c& {c3rfmO2xF礃_A{դyIμ-2J\q>bv/c&'Ǥ͘L˨XXضx<ߴo47J߈tYy uq/c wd]jwɺV mHCl3Ec\m>3<)S[HIJ=p(Σ2773z<6w$i^ܐjIpYېj=x+ 히 ;\FcK4A< {RmjfmdS+ܪwǦLD*ys|WaH`*%ǖ,iΥz[? C:gG{z_rDoDmp#I" D~1n>p#JC^JZН|x\ &v$H9!i-܌Dtnun7 g6JY&.AnonM/3'֕$֍%}6y ur۱I6癓?n!1Y} T!Cv`a*}r~w~=vXq9O)fvquЇV[-:fVj4OO,&Rђ,,<}3[SdI9AP8P $`v Fj]I1Zi ):iK>O oNeB"`Yn/VTz)[fo'fG ˍ-T {:[ _6発5O kmBAQ[_=*>ZN-OA+BEO48|u?Kl5+?XB /1YN+;9gwaJ@WG9;ob%5ś2жBŘf`U*B+ q{-#_Q c(ѥER|0G.bJQccJN0tblp)T9FQ=eD }VN1H>9锓XQAmd )ڮ]OZq O@0I2)s"Sx",՝aK|sд%QYG5=~ҡqlv䠥eϝ3vt>XљUG&/y#!B BkeF(;o{Ϟv(%#50||%W#|Ui\F.7[JxWD%=ԡ![N}իLB´^E]t5JsJlUma {[B f qҕ'IuYz}ػވNF,+OY ols%LƙOfBKN"*Q*}cs +oG2-#bf#D{GD99JT"3hI5 Tn"N[xvx:lEp&mRzqawTB"*)UIlbadٙ Y#kl֒VFzj](h X=@cH" G:yS({\^vdYⰫ~>7M[]Ƀ, VDU~5{{+D[oƬ>b) r p{ǩp_+GkpCy~ c:,~r05(R +.p J8Zx?lΎ |Ba,;\R֢:+*K d=_¥}ҩ%`9Ҝ pyx [}h m?xRKdEx?ǔN 1aq$6iꊒޥ",;J<ջt/g*[+j_$#6_47R0a)pvcѭ\$X8#ߑs qm4Cv^;#&}%DX՝rEםW Gc^78h%&"]Eb!ڭ͝oYjv2n6j~H5;DKnY]TJtġUܹbJtpY-m!9=^ƴY QTبrbHczAvT&,|EBnk \XfPђ.ah9ѓwxxh ^HA;2$$pjmpA<~˭$6]'u[<`qhPw dYyKG?vquiX"X<Ѯ]4k%T@M Cjg'T*+BO_aYUWje lh;3Z?qrẽ ڔ(Tu#%P(1|6H1nە*QXpj1A 9Q4 OC85X*М*К?4uy1C0*\GisXk#iZcJF cP@Ahyjֿ4Еb;̅2PQaRppu|,T懪NlFZἉ(kvC[NlTilA1W`e9H+wZuc})z`Tp 3=aorQdKգ94o$aFhadbͶwvHKmw+׼G~Ev&p%䎳3?\|(}Ѹ>M{ؕ<3t\rHӗN4zZkuoewlayd1{k}a~MphYrt]`uTyjZb$3 ^jК(8(-QyWGv6JM{V[ך(ayusP=ZYBvUH|*~ 3mJݵ,팻wh@cze=cPgnD5M=s3Dxn#f9[Jq&"PA7:׭[pyCiyrMʺkΰj[.vG֏y4MٮTub$v,wqEʸl]8/V^X4ZbZmqd?lȩ^2PǪl݊֝gF^~ct܇1L v  bʰ2͍߮o1ZWpccN:?33mQ4=i.nb;)<(ȃp$8ɰό qa;VzXnTezPuLMDc41:Y8ͩuiF eXs~uK|tmwaQUnΕK[V3ju˖B3om-ZlVֽTE{lkN5ޚtAifelwwkQsnq4U>["J}\A.;G9{2H mՈ]rܶA/Al%U-UL?k!ZӌH\YfC9ܑ P)}4c prU꿼WYd)J_ @Ȫ <Z]eN;e'tUZ_:fg K5Ҩ+Ȇ+̈́boܦMrn,-1gs~Ycҿ>օ޾FvOem48`"u!ɱQB^+`iE4%'9ں!s!w ,,5K{Pp͋%Tt6wZzRb( 5a(gӛ{HwE3 $˟ZݺUg;$L>[ZA q$ Q8 ~[gaQ:D-W#ݿtBAot\I T}fZکOGX,_ky+~_wlǰ `xS]zW$.N!^S;>7fs}̿So}.$G\skjٟO3R>7[3) { Bye+s\JcY Efe囏SV%O77b9^ܮLn|[M8[+mcPwEOY =ȇeJ2(AΓO JDX3$ӑy%7]3m}0 DY)+zdьʓT-(Og|(ǎdT0y@`o=Eprq^yOppGK'k{xXa4j8ɠYԯг}p|6oh 55W꘼CXLLm+a$`ߤR:FV#7vBT4RiNd&$98EWʞYًb7ηCIΎbͧ *m ? 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j^2̆2vAewvᆚs9 endstream endobj 47 0 obj <>stream 8;V.Z_%FR=#\+tDPL[$mR3GsfB@j,9\MfLR/e09BOoZ,mb,S:#IC`@N5DbcjoEQUp O=9BjGB<;0BpMlVRaolG`GM_*ffU9+Jqu!jU0YuY(V?m%VS:B%<7sAg-Ar]n0\D'e O3Ee)=>-%d&nTrp0!mgI*)*:bgt^UNg6kg?c')#r-=^PVnU4ILbZesY\s]J@O@#;` p0G[Ck2\o/[<:na?Gra)._c&cB,S!$~> endstream endobj 8 0 obj <> endobj 9 0 obj <> endobj 10 0 obj <>stream %!PS-Adobe-3.0 %%Creator: Adobe Illustrator(R) 24.0 %%AI8_CreatorVersion: 28.0.0 %%For: (Chris McDowell) () %%Title: (EG_REV1_PANEL.ai) %%CreationDate: 11/29/24 11:38 AM %%Canvassize: 16383 %%BoundingBox: 194 -365 280 1 %%HiResBoundingBox: 194.399999999991 -364.251953125 279.439123535143 0.00006103515625 %%DocumentProcessColors: Cyan Magenta Yellow Black %AI5_FileFormat 14.0 %AI12_BuildNumber: 88 %AI3_ColorUsage: Color %AI7_ImageSettings: 0 %%CMYKProcessColor: 1 1 1 1 ([Registration]) %AI3_Cropmarks: 194.399999999991 -364.251968503901 279.439123535143 0 %AI3_TemplateBox: 43.5 -182.5 43.5 -182.5 %AI3_TileBox: -51.0804382324332 -538.12598425195 524.919561767567 195.87401574805 %AI3_DocumentPreview: None %AI5_ArtSize: 14400 14400 %AI5_RulerUnits: 1 %AI24_LargeCanvasScale: 1 %AI9_ColorModel: 2 %AI5_ArtFlags: 0 0 0 1 0 0 1 0 0 %AI5_TargetResolution: 800 %AI5_NumLayers: 6 %AI17_Begin_Content_if_version_gt:24 4 %AI10_OpenToVie: -76.90976884064 13.6677368444052 2.34255812381147 0 8405.1267667083 8194.26009135471 1716 1053 18 1 0 6 58 0 0 0 1 1 0 1 1 0 1 %AI17_Alternate_Content %AI9_OpenToView: -76.90976884064 13.6677368444052 2.34255812381147 1716 1053 18 1 0 6 58 0 0 0 1 1 0 1 1 0 1 %AI17_End_Versioned_Content %AI5_OpenViewLayers: 677773 %AI17_Begin_Content_if_version_gt:24 4 %AI17_Alternate_Content %AI17_End_Versioned_Content %%PageOrigin:-263 -578 %AI7_GridSettings: 72 8 72 8 1 0 0.800000011920929 0.800000011920929 0.800000011920929 0.899999976158142 0.899999976158142 0.899999976158142 %AI9_Flatten: 1 %AI12_CMSettings: 00.MS %%EndComments endstream endobj 11 0 obj <>stream %AI24_ZStandard_Data(/Xů ;@M0 9(QOsږk hF$RF en u"#WN!%%=mWLb^\7k3"UI#g[T'^헽"냥ԎutňHi,3DtdzIS"ңIz_ԓ@QRyVu1sOE>K+%78% mW֬d[9P DYlb@J6@  C. 5040PA(ͭ8Ys|KH[by_$LИTpP  YʔTe ݔiR$H?wmz\W`,cq(%āH܋xE,LqY7H;c 8zʖ!WfՊ D/<#q-xЁ8j0#FeՔʙ1O-LD(C6baƼq,=Jez),C|N/9W'Zycs+sX@(aAcBq$xq< )! Ţh Tv~"q$ĔSad%%L'ALb4昶Ԫͺ/*(L'%HA bPZTUVWXY녨D)jQjX -vCX05lGWgw!.q[w  G&P d`''"E2\6þNXnx;>'7>"QC0"P 8&%*aK`"N2)!}rES@8 ĝxV1c`$+0 'UUQU5 )(A BN')) Ȩt 5(*hb*NØ(&1AǓscSCәi4 /H, BX, Ƃh,a 2Ab82dag `$ `0 F`LcmA jTְ5ld 7x@4DCP4E`4 s\E*2|:31/-+) d@cq[/Ύ70-La C͖vfVFVkD!sH O8 L\Dh P #C(b3#yN 3 #|i|Xa8@1qe `, "@,"-jA.fP0 BP\aE*Pq SU`$ E"8,8 pxsXpdA"Px`P`,Dž#x!p`h` 3%beDQc.sX A 9(0 (HAcR <` Ra@(p `@2AhPA a  (HȀ8Lp `< A20!A4p> 2` :p  $L@`` pLP*T ,$. $Pa "̼2C1+wy9'[[׻PKrЈ֔$ߟ+\{zWvx:t7MK?c^ݱ\:BM5/;c]=WnV^f؜՘Y͗6*S֜zȇj1ݘ, i>8wwS)\Sh/{]γѮޡϕw7 {d5՞ygûLfO<\GS78,|ۡBxBw8u|8Uwx =͂v2*gBrO,g-mS/&ݹ]]#k`8{wTK NM^~SqN!;gTt{6˻bWnICᜑJWxTSwW"<^1Ig3e!7]w %s6{ZM͹Wg;K: 0oiL6/]9+Rvi&|/cF" "_+cE573T$eͪH Jyn*S$YSef7[W'8.yɓ )HJ!zYiuJ(ˌ -TTRErZqu$,TĨƌvWNЭˇ2f21ڵ2V%` eJ)m+9TjtrD1yE'\TnJwɟUIfA'9Jib(^xV%$2O֕7 !I*vB12cK42'U"IJMeA YfHLD;<R)+$IrlT|$=\sXn8#'|H$WADr1SVR]uGrVjz>rHP!#"9&&d")BI^3wK/H,RlÛRk*eIY$Fmt+F$f4J*;ɰ.E⿦2YH~D2:yN_CbTC$T1%&'9ɡ֤rȔ畜V0ЌK[Or#‚  (@0!@ 4P!40 `&wY(W%&,gue%תAሐ"5»fvW%!^2*S*U}ngWj`8*p?zN50Ȇ(sr#t R$#+2{D5M"P@ ŮU(=VZ> ]M 崵o++h9еbIHcAlŐXʜMUJ}5-s]O*w;R/9kX*CMmhu=\h4*>Uw˺KŬRs:}4A^_"]fsl[ddSoOVز4ǎ͌%BֻgvƗc_*̬FZu]f~K r^ssOɮi{~Ќڧ%{SubR2"_*2Y\Wó+ҞCi4^q) jo=d_50^rt,HG1WYV9ffLSsל7r.m':e:>YFunx?#*r*Uu 8Dzm尦J+~Yz)sXL{ݽS0[ⷁРi\NTK#v:+uge,Ut=j50 ґҗꍊXC*]zv4mv3"ü_e'")LvP m!:j]U=g)n:Ny,5ԖQ=iYZlܝWfv,YcŤL{]̢̣rvqLu0 ˮOt@eg9瀠֫%,O`\WR>Heޫ)>: GDZ} Rّ) $kuB[MGݑ߬|tFQ\2˟uE٬k_eٍ迷Ttٝb nѐ8<yJ男)9e|XhS ͥaJV4_;yl_y%YYt3g{O}E'Z/󌯠z;>s7}n9f?r3Hu+T5S>KQmSa%S"|=u5ңQ{szdN*s9b,qζB 殲:4b×4Vs*guE[R"[&9ΰUQ.WԑP"U^$Ls3''N˵䨉Nɧl o-C٫Z T™_Y=oX|dwXˉXcZ}:l-s,4_yZVz\uYhZ#BP4Йߪe֪J,봛Dfٱi}-%:3פ_ q>w_%4ܯӒo]Ey3/uxņ_~C96wCn-a[R{!XN{&nmr/)l.w.tHSw2{9;-tǻ)ڽp<{ͻ_ٺK7ܼ;fmz;˲^UYYG3ٿZ$|ZmYe3#ʥr+J[9;yɂ&Wa12I}h|G'eMshԶmj|fNLÖd&ΟSK%I*3]6:0mSTIez^tSve#Ii^VvLLtjǫ+L ;tG2iD64k,?9k/kWL5kq &&2p4&b7Nkw"i{SM!8hJk/2{i"2wU1g6r9Mgin1)3;yٔ7<敞NuubVDphP'љC*RW5EIHc829IHWh)GҦviFlj!4+2gfϲ2hc;#9Cߌܬfg9wvhѥ}f,.lʎet*-3վlKn.e?߽4F1{֌v[dImEVfwƅtwW.#_SM;Wh,:&#x-UkZY:f=)5F eȲλ,jf ܙvfct_̭=C-WJ*˺RexͬwCreJ /,,T3]JVcy [C\\H=iTLݱzDGy^Gc9w;4*_sǾ fcK±ɜ{jp~TV&5wYjkd';m] UEfp~t3k3UonF]X>o,JrU]U.є^JLrƌ~Ӣ#JO8Gٳ(ɥ yWI^S6Uy:/N.yN*yBOrwmJHiD NQNKF?`YsYZ*^ZYL~ZUR2~S7}D~c}N]:{̭Vab_)ʾX,Ie,{gJY*զTq^g Y=1?xud=ӗJ]YëjTdƪ^*mռ6+UWGGu[*X:YͦZ|3E)|ޜ,CeT[ݹzLUVt}\UU_{_Vхʭ$][Y Mp>vNEHu8ssORr_ M!'ze]irYSCn*b<$U NV,]+nSBYֱUzh#c=-=}TU7Ϸd TD=s}]PХ:á_) $<cVz3ZN5|wZfiފvveWŧkxg9ŰV4Y[c7+G4HUVK|/)ĪW UmƇWpCV-ah-+.^ӨZWک4WK{$식}J-NniTHc9B!$H $ i>v^6P6 šuAe!@d] om{.Pq5nYV>"  "L.irY1N}K_h͸@K7iZե3!e@S9cܻ=JG%nw AdpU6T<?*t #Д8eHa>΍w̬$i#{=$kFT캃MTO8}`$ZƔʿnm-"ˈ%4X|C 4]_omf TԀkJ "sƕ2w{x'6LM-aˠse8o:aPr*CF[L2Fku*ȱ\d+|Bu30[آ6Jue$}VC\d9pr qrGLՔ)+3]S[J/lhKVxUT"Ż]Gn-++aZ@P4BG)IŖ㤻_ԍlrwքaxCvTv-,%4f4hP-7߷_೒gcA):5[G 2x6 pӀiI6i¥9ץ8O/A]>a݋g,BYmpeS^<3n9 0Rv *1~ҰPw BKlUЋt+0VƁ3>XN\" L pRÓoM<驤iҏ( '3uC1!ìd[11k_˶20 M<-d;L{ lQ6TdJKqGNy4r!1rI|;ṻK?Z"ekkӻf'.@[}s_"2KV2z+[0lET^BlEtY+B*S[҉eW';8᫜.N늜"};;tCxͬIat,G_hɆYWDFl46pQ,r5%X du @dT^Ypmdc'M'[ʇEV@si uH,j+m픤 3ՙD}!! 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